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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/hal_lld.h
19 * @brief STM32F0xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC,
30 * STM32F070x6, STM32F070xB for Value Line devices.
31 * - STM32F031x6, STM32F051x8, STM32F071xB, STM32F091xC
32 * for Access Line devices.
33 * - STM32F042x6, STM32F072xB for USB Line devices.
34 * - STM32F038xx, STM32F048xx, STM32F058xx, STM32F078xx,
35 * STM32F098xx for Low Voltage Line devices.
36 * .
37 *
38 * @addtogroup HAL
39 * @{
40 */
41
42#ifndef HAL_LLD_H
43#define HAL_LLD_H
44
45/*
46 * Registry definitions.
47 */
48#include "stm32_registry.h"
49
50/*===========================================================================*/
51/* Driver constants. */
52/*===========================================================================*/
53
54/**
55 * @name Platform identification macros
56 * @{
57 */
58#if defined(STM32F030x4) || defined(__DOXYGEN__)
59#define PLATFORM_NAME "STM32F030x4 Entry Level Value Line devices"
60
61#elif defined(STM32F030x6)
62#define PLATFORM_NAME "STM32F030x6 Entry Level Value Line devices"
63
64#elif defined(STM32F030x8)
65#define PLATFORM_NAME "STM32F030x8 Entry Level Value Line devices"
66
67#elif defined(STM32F030xC)
68#define PLATFORM_NAME "STM32F030xC Entry Level Value Line devices"
69
70#elif defined(STM32F070x6)
71#define PLATFORM_NAME "STM32F070x6 Entry Level Value Line devices"
72
73#elif defined(STM32F070xB)
74#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
75
76#elif defined(STM32F031x6)
77#define PLATFORM_NAME "STM32F031x6 Entry Level Access Line devices"
78
79#elif defined(STM32F051x8)
80#define PLATFORM_NAME "STM32F051x8 Entry Level Access Line devices"
81
82#elif defined(STM32F071xB)
83#define PLATFORM_NAME "STM32F071xB Entry Level Access Line devices"
84
85#elif defined(STM32F091xC)
86#define PLATFORM_NAME "STM32F091xC Entry Level Access Line devices"
87
88#elif defined(STM32F042x6)
89#define PLATFORM_NAME "STM32F042x6 Entry Level USB Line devices"
90
91#elif defined(STM32F072xB)
92#define PLATFORM_NAME "STM32F072xB Entry Level USB Line devices"
93
94#elif defined(STM32F038xx)
95#define PLATFORM_NAME "STM32F038xx Entry Level Low Voltage Line devices"
96
97#elif defined(STM32F048xx)
98#define PLATFORM_NAME "STM32F048xx Entry Level Low Voltage Line devices"
99
100#elif defined(STM32F058xx)
101#define PLATFORM_NAME "STM32F058xx Entry Level Low Voltage Line devices"
102
103#elif defined(STM32F078xx)
104#define PLATFORM_NAME "STM32F078xx Entry Level Low Voltage Line devices"
105
106#elif defined(STM32F098xx)
107#define PLATFORM_NAME "STM32F098xx Entry Level Low Voltage Line devices"
108
109#else
110#error "STM32F0xx device unsupported or not specified"
111#endif
112/** @} */
113
114/**
115 * @name Absolute Maximum Ratings
116 * @{
117 */
118/**
119 * @brief Maximum system clock frequency.
120 */
121#define STM32_SYSCLK_MAX 48000000
122
123/**
124 * @brief Maximum HSE clock frequency.
125 */
126#define STM32_HSECLK_MAX 32000000
127
128/**
129 * @brief Minimum HSE clock frequency.
130 */
131#define STM32_HSECLK_MIN 1000000
132
133/**
134 * @brief Maximum LSE clock frequency.
135 */
136#define STM32_LSECLK_MAX 1000000
137
138/**
139 * @brief Minimum LSE clock frequency.
140 */
141#define STM32_LSECLK_MIN 32768
142
143/**
144 * @brief Maximum PLLs input clock frequency.
145 */
146#define STM32_PLLIN_MAX 25000000
147
148/**
149 * @brief Minimum PLLs input clock frequency.
150 */
151#define STM32_PLLIN_MIN 1000000
152
153/**
154 * @brief Maximum PLL output clock frequency.
155 */
156#define STM32_PLLOUT_MAX 48000000
157
158/**
159 * @brief Minimum PLL output clock frequency.
160 */
161#define STM32_PLLOUT_MIN 16000000
162
163/**
164 * @brief Maximum APB clock frequency.
165 */
166#define STM32_PCLK_MAX 48000000
167/** @} */
168
169/**
170 * @name Internal clock sources
171 * @{
172 */
173#define STM32_HSICLK 8000000 /**< High speed internal clock. */
174#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/
175#define STM32_HSI48CLK 48000000 /**< 48MHz speed internal clock.*/
176#define STM32_LSICLK 40000 /**< Low speed internal clock. */
177/** @} */
178
179/**
180 * @name PWR_CR register bits definitions
181 * @{
182 */
183#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
184#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
185#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
186#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
187#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
188#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
189#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
190#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
191#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
192/** @} */
193
194/**
195 * @name RCC_CFGR register bits definitions
196 * @{
197 */
198#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
199#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
200#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
201#define STM32_SW_HSI48 (3 << 0) /**< SYSCLK source is HSI48. */
202
203#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
204#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
205#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
206#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
207#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
208#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
209#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
210#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
211#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
212
213#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */
214#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */
215#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */
216#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */
217#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */
218
219#define STM32_PLLSRC_HSI_DIV2 (0 << 15) /**< PLL clock source is HSI/2. */
220#define STM32_PLLSRC_HSI (1 << 15) /**< PLL clock source is HSI */
221#define STM32_PLLSRC_HSE (2 << 15) /**< PLL clock source is HSE. */
222#define STM32_PLLSRC_HSI48 (3 << 15) /**< PLL clock source is HSI48. */
223
224#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
225#define STM32_MCOSEL_HSI14 (1 << 24) /**< HSI14 clock on MCO pin. */
226#define STM32_MCOSEL_LSI (2 << 24) /**< LSI clock on MCO pin. */
227#define STM32_MCOSEL_LSE (3 << 24) /**< LSE clock on MCO pin. */
228#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
229#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
230#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
231#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
232#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
233
234#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
235#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
236#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
237#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
238#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
239#define STM32_MCOPRE_DIV32 (5 << 28) /**< MCO divided by 32. */
240#define STM32_MCOPRE_DIV64 (6 << 28) /**< MCO divided by 64. */
241#define STM32_MCOPRE_DIV128 (7 << 28) /**< MCO divided by 128. */
242
243#define STM32_PLLNODIV_MASK (1 << 31) /**< MCO PLL divider mask. */
244#define STM32_PLLNODIV_DIV2 (0 << 31) /**< MCO PLL is divided by two. */
245#define STM32_PLLNODIV_DIV1 (1 << 31) /**< MCO PLL is divided by one. */
246/** @} */
247
248/**
249 * @name RCC_CFGR2 register bits definitions
250 * @{
251 */
252#define STM32_PRE_DIV1 (0 << 0) /**< PLLSRC divided by 1. */
253#define STM32_PRE_DIV2 (1 << 0) /**< SYSCLK divided by 2. */
254#define STM32_PRE_DIV3 (2 << 0) /**< SYSCLK divided by 3. */
255#define STM32_PRE_DIV4 (3 << 0) /**< PLLSRC divided by 4. */
256#define STM32_PRE_DIV5 (4 << 0) /**< SYSCLK divided by 5. */
257#define STM32_PRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */
258#define STM32_PRE_DIV7 (6 << 0) /**< PLLSRC divided by 7. */
259#define STM32_PRE_DIV8 (7 << 0) /**< SYSCLK divided by 8. */
260#define STM32_PRE_DIV9 (8 << 0) /**< SYSCLK divided by 9. */
261#define STM32_PRE_DIV10 (9 << 0) /**< PLLSRC divided by 10. */
262#define STM32_PRE_DIV11 (10 << 0) /**< SYSCLK divided by 11. */
263#define STM32_PRE_DIV12 (11 << 0) /**< SYSCLK divided by 12. */
264#define STM32_PRE_DIV13 (12 << 0) /**< PLLSRC divided by 13. */
265#define STM32_PRE_DIV14 (13 << 0) /**< SYSCLK divided by 14. */
266#define STM32_PRE_DIV15 (14 << 0) /**< SYSCLK divided by 15. */
267#define STM32_PRE_DIV16 (15 << 0) /**< PLLSRC divided by 16. */
268/** @} */
269
270/**
271 * @name RCC_CFGR3 register bits definitions
272 * @{
273 */
274#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */
275#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */
276#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
277#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */
278#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */
279#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */
280#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */
281#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */
282#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
283#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
284#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
285#define STM32_CECSW_OFF 0xFFFFFFFF /**< CEC clock is not required. */
286#define STM32_USBSW_MASK (1 << 7) /**< USB clock source mask. */
287#define STM32_USBSW_HSI48 (0 << 7) /**< USB clock is HSI48. */
288#define STM32_USBSW_PCLK (1 << 7) /**< USB clock is PCLK. */
289/** @} */
290
291/**
292 * @name RCC_BDCR register bits definitions
293 * @{
294 */
295#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
296#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
297#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
298#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
299#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as
300 RTC clock. */
301/** @} */
302
303/*===========================================================================*/
304/* Driver pre-compile time settings. */
305/*===========================================================================*/
306
307/**
308 * @name Configuration options
309 * @{
310 */
311/**
312 * @brief Disables the PWR/RCC initialization in the HAL.
313 */
314#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
315#define STM32_NO_INIT FALSE
316#endif
317
318/**
319 * @brief Enables or disables the programmable voltage detector.
320 */
321#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
322#define STM32_PVD_ENABLE FALSE
323#endif
324
325/**
326 * @brief Sets voltage level for programmable voltage detector.
327 */
328#if !defined(STM32_PLS) || defined(__DOXYGEN__)
329#define STM32_PLS STM32_PLS_LEV0
330#endif
331
332/**
333 * @brief Enables or disables the HSI clock source.
334 */
335#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
336#define STM32_HSI_ENABLED TRUE
337#endif
338
339/**
340 * @brief Enables or disables the HSI14 clock source.
341 */
342#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
343#define STM32_HSI14_ENABLED TRUE
344#endif
345
346/**
347 * @brief Enables or disables the HSI48 clock source.
348 */
349#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
350#define STM32_HSI48_ENABLED FALSE
351#endif
352
353/**
354 * @brief Enables or disables the LSI clock source.
355 */
356#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
357#define STM32_LSI_ENABLED FALSE
358#endif
359
360/**
361 * @brief Enables or disables the HSE clock source.
362 */
363#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
364#define STM32_HSE_ENABLED TRUE
365#endif
366
367/**
368 * @brief Enables or disables the LSE clock source.
369 */
370#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
371#define STM32_LSE_ENABLED FALSE
372#endif
373
374/**
375 * @brief Main clock source selection.
376 * @note If the selected clock source is not the PLL then the PLL is not
377 * initialized and started.
378 * @note The default value is calculated for a 48MHz system clock from
379 * a 8MHz crystal using the PLL.
380 */
381#if !defined(STM32_SW) || defined(__DOXYGEN__)
382#define STM32_SW STM32_SW_PLL
383#endif
384
385/**
386 * @brief Clock source for the PLL.
387 * @note This setting has only effect if the PLL is selected as the
388 * system clock source.
389 * @note The default value is calculated for a 48MHz system clock from
390 * a 8MHz crystal using the PLL.
391 */
392#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
393#define STM32_PLLSRC STM32_PLLSRC_HSE
394#endif
395
396/**
397 * @brief Crystal PLL pre-divider.
398 * @note This setting has only effect if the PLL is selected as the
399 * system clock source.
400 * @note The default value is calculated for a 72MHz system clock from
401 * a 8MHz crystal using the PLL.
402 */
403#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
404#define STM32_PREDIV_VALUE 1
405#endif
406
407/**
408 * @brief PLL multiplier value.
409 * @note The allowed range is 2...16.
410 * @note The default value is calculated for a 48MHz system clock from
411 * a 8MHz crystal using the PLL.
412 */
413#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
414#define STM32_PLLMUL_VALUE 6
415#endif
416
417/**
418 * @brief AHB prescaler value.
419 * @note The default value is calculated for a 48MHz system clock from
420 * a 8MHz crystal using the PLL.
421 */
422#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
423#define STM32_HPRE STM32_HPRE_DIV1
424#endif
425
426/**
427 * @brief APB1 prescaler value.
428 */
429#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
430#define STM32_PPRE STM32_PPRE_DIV1
431#endif
432
433/**
434 * @brief MCO pin setting.
435 */
436#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
437#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
438#endif
439
440/**
441 * @brief MCO divider setting.
442 */
443#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
444#define STM32_MCOPRE STM32_MCOPRE_DIV1
445#endif
446
447/**
448 * @brief MCO PLL divider setting.
449 */
450#if !defined(STM32_PLLNODIV) || defined(__DOXYGEN__)
451#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
452#endif
453
454/**
455 * @brief USB Clock source.
456 */
457#if !defined(STM32_USBSW) || defined(__DOXYGEN__)
458#define STM32_USBSW STM32_USBSW_HSI48
459#endif
460
461/**
462 * @brief CEC clock source.
463 */
464#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
465#define STM32_CECSW STM32_CECSW_HSI
466#endif
467
468/**
469 * @brief I2C1 clock source.
470 */
471#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
472#define STM32_I2C1SW STM32_I2C1SW_HSI
473#endif
474
475/**
476 * @brief USART1 clock source.
477 */
478#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
479#define STM32_USART1SW STM32_USART1SW_PCLK
480#endif
481
482/**
483 * @brief RTC clock source.
484 */
485#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
486#define STM32_RTCSEL STM32_RTCSEL_LSI
487#endif
488/** @} */
489
490/*===========================================================================*/
491/* Derived constants and error checks. */
492/*===========================================================================*/
493
494/*
495 * Configuration-related checks.
496 */
497#if !defined(STM32F0xx_MCUCONF)
498#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
499#endif
500
501/*
502 * HSI related checks.
503 */
504#if STM32_HSI_ENABLED
505#if (STM32_SW == STM32_SW_PLL) && \
506 (STM32_PLLSRC == STM32_PLLSRC_HSI) && !STM32_HAS_HSI_PREDIV
507#error "STM32_PLLSRC_HSI not available on this platform. Select STM32_PLLSRC_HSI_DIV2 instead."
508#endif
509#else /* !STM32_HSI_ENABLED */
510
511#if STM32_SW == STM32_SW_HSI
512#error "HSI not enabled, required by STM32_SW"
513#endif
514
515#if STM32_CECSW == STM32_CECSW_HSI
516#error "HSI not enabled, required by STM32_CECSW"
517#endif
518
519#if STM32_I2C1SW == STM32_I2C1SW_HSI
520#error "HSI not enabled, required by STM32_I2C1SW"
521#endif
522
523#if STM32_USART1SW == STM32_USART1SW_HSI
524#error "HSI not enabled, required by STM32_USART1SW"
525#endif
526
527#if (STM32_SW == STM32_SW_PLL) && \
528 (STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
529 (STM32_PLLSRC == STM32_PLLSRC_HSI)
530#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
531#endif
532
533#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
534 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
535 ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
536 (STM32_PLLSRC == STM32_PLLSRC_HSI)))
537#error "HSI not enabled, required by STM32_MCOSEL"
538#endif
539
540#endif /* !STM32_HSI_ENABLED */
541
542/*
543 * HSI14 related checks.
544 */
545#if STM32_HSI14_ENABLED
546#else /* !STM32_HSI14_ENABLED */
547
548#if STM32_MCOSEL == STM32_MCOSEL_HSI14
549#error "HSI14 not enabled, required by STM32_MCOSEL"
550#endif
551
552#endif /* !STM32_HSI14_ENABLED */
553
554/*
555 * HSI48 related checks.
556 */
557#if STM32_HSI48_ENABLED
558#if !STM32_HAS_HSI48
559#error "HSI48 not available on this platform"
560#endif
561#else /* !STM32_HSI48_ENABLED */
562
563#if STM32_SW == STM32_SW_HSI48
564#error "HSI48 not enabled, required by STM32_SW"
565#endif
566
567#if (STM32_MCOSEL == STM32_MCOSEL_HSI48) || \
568 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
569 ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
570 (STM32_PLLSRC == STM32_PLLSRC_HSI48)))
571#error "HSI48 not enabled, required by STM32_MCOSEL"
572#endif
573
574#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI48)
575#error "HSI48 not enabled, required by STM32_SW and STM32_PLLSRC"
576#endif
577
578#endif /* !STM32_HSI48_ENABLED */
579
580/*
581 * HSE related checks.
582 */
583#if STM32_HSE_ENABLED
584
585#if STM32_HSECLK == 0
586#error "HSE frequency not defined"
587#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
588#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
589#endif
590
591#else /* !STM32_HSE_ENABLED */
592
593#if STM32_SW == STM32_SW_HSE
594#error "HSE not enabled, required by STM32_SW"
595#endif
596
597#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
598#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
599#endif
600
601#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
602 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
603 (STM32_PLLSRC == STM32_PLLSRC_HSE))
604#error "HSE not enabled, required by STM32_MCOSEL"
605#endif
606
607#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
608#error "HSE not enabled, required by STM32_RTCSEL"
609#endif
610
611#endif /* !STM32_HSE_ENABLED */
612
613/*
614 * LSI related checks.
615 */
616#if STM32_LSI_ENABLED
617#else /* !STM32_LSI_ENABLED */
618
619#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
620#error "LSI not enabled, required by STM32_RTCSEL"
621#endif
622
623#endif /* !STM32_LSI_ENABLED */
624
625/*
626 * LSE related checks.
627 */
628#if STM32_LSE_ENABLED
629
630#if (STM32_LSECLK == 0)
631#error "LSE frequency not defined"
632#endif
633
634#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
635#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
636#endif
637
638#if !defined(STM32_LSEDRV)
639#error "STM32_LSEDRV not defined"
640#endif
641
642#if (STM32_LSEDRV >> 3) > 3
643#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
644#endif
645
646#else /* !STM32_LSE_ENABLED */
647
648#if STM32_CECSW == STM32_CECSW_LSE
649#error "LSE not enabled, required by STM32_CECSW"
650#endif
651
652#if STM32_USART1SW == STM32_USART1SW_LSE
653#error "LSE not enabled, required by STM32_USART1SW"
654#endif
655
656#if STM32_RTCSEL == STM32_RTCSEL_LSE
657#error "LSE not enabled, required by STM32_RTCSEL"
658#endif
659
660#endif /* !STM32_LSE_ENABLED */
661
662/* PLL activation conditions.*/
663#if (STM32_SW == STM32_SW_PLL) || \
664 (STM32_USBSW == STM32_USBSW_PCLK) || \
665 (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
666 defined(__DOXYGEN__)
667/**
668 * @brief PLL activation flag.
669 */
670#define STM32_ACTIVATE_PLL TRUE
671#else
672#define STM32_ACTIVATE_PLL FALSE
673#endif
674
675/* HSE, HSI prescaler setting check.*/
676#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
677#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
678#else
679#error "invalid STM32_PREDIV value specified"
680#endif
681
682/**
683 * @brief PLLMUL field.
684 */
685#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
686 defined(__DOXYGEN__)
687#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
688#else
689#error "invalid STM32_PLLMUL_VALUE value specified"
690#endif
691
692/**
693 * @brief PLL input clock frequency.
694 */
695#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
696#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
697#elif STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2
698#define STM32_PLLCLKIN (STM32_HSICLK / 2)
699#elif STM32_PLLSRC == STM32_PLLSRC_HSI
700#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PREDIV_VALUE)
701#elif STM32_PLLSRC == STM32_PLLSRC_HSI48
702#define STM32_PLLCLKIN (STM32_HSI48CLK / STM32_PREDIV_VALUE)
703#else
704#error "invalid STM32_PLLSRC value specified"
705#endif
706
707/* PLL input frequency range check.*/
708#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
709#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
710#endif
711
712/**
713 * @brief PLL output clock frequency.
714 */
715#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
716
717/* PLL output frequency range check.*/
718#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
719#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
720#endif
721
722/**
723 * @brief System clock source.
724 */
725#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
726#define STM32_SYSCLK STM32_PLLCLKOUT
727#elif (STM32_SW == STM32_SW_HSI)
728#define STM32_SYSCLK STM32_HSICLK
729#elif (STM32_SW == STM32_SW_HSI48)
730#define STM32_SYSCLK STM32_HSI48CLK
731#elif (STM32_SW == STM32_SW_HSE)
732#define STM32_SYSCLK STM32_HSECLK
733#else
734#error "invalid STM32_SW value specified"
735#endif
736
737/* Check on the system clock.*/
738#if STM32_SYSCLK > STM32_SYSCLK_MAX
739#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
740#endif
741
742/**
743 * @brief AHB frequency.
744 */
745#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
746#define STM32_HCLK (STM32_SYSCLK / 1)
747#elif STM32_HPRE == STM32_HPRE_DIV2
748#define STM32_HCLK (STM32_SYSCLK / 2)
749#elif STM32_HPRE == STM32_HPRE_DIV4
750#define STM32_HCLK (STM32_SYSCLK / 4)
751#elif STM32_HPRE == STM32_HPRE_DIV8
752#define STM32_HCLK (STM32_SYSCLK / 8)
753#elif STM32_HPRE == STM32_HPRE_DIV16
754#define STM32_HCLK (STM32_SYSCLK / 16)
755#elif STM32_HPRE == STM32_HPRE_DIV64
756#define STM32_HCLK (STM32_SYSCLK / 64)
757#elif STM32_HPRE == STM32_HPRE_DIV128
758#define STM32_HCLK (STM32_SYSCLK / 128)
759#elif STM32_HPRE == STM32_HPRE_DIV256
760#define STM32_HCLK (STM32_SYSCLK / 256)
761#elif STM32_HPRE == STM32_HPRE_DIV512
762#define STM32_HCLK (STM32_SYSCLK / 512)
763#else
764#error "invalid STM32_HPRE value specified"
765#endif
766
767/* AHB frequency check.*/
768#if STM32_HCLK > STM32_SYSCLK_MAX
769#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
770#endif
771
772/**
773 * @brief APB frequency.
774 */
775#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
776#define STM32_PCLK (STM32_HCLK / 1)
777#elif STM32_PPRE == STM32_PPRE_DIV2
778#define STM32_PCLK (STM32_HCLK / 2)
779#elif STM32_PPRE == STM32_PPRE_DIV4
780#define STM32_PCLK (STM32_HCLK / 4)
781#elif STM32_PPRE == STM32_PPRE_DIV8
782#define STM32_PCLK (STM32_HCLK / 8)
783#elif STM32_PPRE == STM32_PPRE_DIV16
784#define STM32_PCLK (STM32_HCLK / 16)
785#else
786#error "invalid STM32_PPRE value specified"
787#endif
788
789/* APB frequency check.*/
790#if STM32_PCLK > STM32_PCLK_MAX
791#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
792#endif
793
794/* STM32_PLLNODIV check.*/
795#if (STM32_PLLNODIV != STM32_PLLNODIV_DIV2) && \
796 (STM32_PLLNODIV != STM32_PLLNODIV_DIV1)
797#error "invalid STM32_PLLNODIV value specified"
798#endif
799
800/**
801 * @brief MCO clock before divider.
802 */
803#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
804#define STM32_MCODIVCLK 0
805#elif STM32_MCOSEL == STM32_MCOSEL_HSI14
806#define STM32_MCODIVCLK STM32_HSI14CLK
807#elif STM32_MCOSEL == STM32_MCOSEL_LSI
808#define STM32_MCODIVCLK STM32_LSICLK
809#elif STM32_MCOSEL == STM32_MCOSEL_LSE
810#define STM32_MCODIVCLK STM32_LSECLK
811#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
812#define STM32_MCODIVCLK STM32_SYSCLK
813#elif STM32_MCOSEL == STM32_MCOSEL_HSI
814#define STM32_MCODIVCLK STM32_HSICLK
815#elif STM32_MCOSEL == STM32_MCOSEL_HSE
816#define STM32_MCODIVCLK STM32_HSECLK
817#elif STM32_MCOSEL == STM32_MCOSEL_PLLDIV2
818#if STM32_PLLNODIV == STM32_PLLNODIV_DIV2
819#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 2)
820#else
821#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 1)
822#endif
823#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
824#define STM32_MCODIVCLK STM32_HSI48CLK
825#else
826#error "invalid STM32_MCOSEL value specified"
827#endif
828
829/**
830 * @brief MCO output pin clock.
831 */
832#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
833#define STM32_MCOCLK STM32_MCODIVCLK
834#elif (STM32_MCOPRE == STM32_MCOPRE_DIV2) && STM32_HAS_MCO_PREDIV
835#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
836#elif (STM32_MCOPRE == STM32_MCOPRE_DIV4) && STM32_HAS_MCO_PREDIV
837#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
838#elif (STM32_MCOPRE == STM32_MCOPRE_DIV8) && STM32_HAS_MCO_PREDIV
839#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
840#elif (STM32_MCOPRE == STM32_MCOPRE_DIV16) && STM32_HAS_MCO_PREDIV
841#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
842#elif !STM32_HAS_MCO_PREDIV
843#error "MCO_PREDIV not available on this platform. Select STM32_MCODIVCLK."
844#else
845#error "invalid STM32_MCOPRE value specified"
846#endif
847
848/**
849 * @brief RTC clock.
850 */
851#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
852#define STM32_RTCCLK STM32_LSECLK
853#elif STM32_RTCSEL == STM32_RTCSEL_LSI
854#define STM32_RTCCLK STM32_LSICLK
855#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
856#define STM32_RTCCLK (STM32_HSECLK / 32)
857#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
858#define STM32_RTCCLK 0
859#else
860#error "invalid source selected for RTC clock"
861#endif
862
863/**
864 * @brief USB frequency.
865 */
866#if (STM32_USBSW == STM32_USBSW_HSI48) || defined(__DOXYGEN__)
867#define STM32_USBCLK STM32_HSI48CLK
868#elif STM32_USBSW == STM32_USBSW_PCLK
869#define STM32_USBCLK STM32_PLLCLKOUT
870#else
871#error "invalid source selected for USB clock"
872#endif
873
874/**
875 * @brief CEC frequency.
876 */
877#if (STM32_CECSW == STM32_CECSW_HSI) || defined(__DOXYGEN__)
878#define STM32_CECCLK STM32_HSICLK
879#elif STM32_CECSW == STM32_CECSW_LSE
880#define STM32_CECCLK STM32_LSECLK
881#elif STM32_CECSW == STM32_CECSW_OFF
882#define STM32_CECCLK 0
883#else
884#error "invalid source selected for CEC clock"
885#endif
886
887/**
888 * @brief I2C1 frequency.
889 */
890#if (STM32_I2C1SW == STM32_I2C1SW_HSI) || defined(__DOXYGEN__)
891#define STM32_I2C1CLK STM32_HSICLK
892#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
893#define STM32_I2C1CLK STM32_SYSCLK
894#else
895#error "invalid source selected for I2C1 clock"
896#endif
897
898/**
899 * @brief USART1 frequency.
900 */
901#if (STM32_USART1SW == STM32_USART1SW_PCLK) || defined(__DOXYGEN__)
902#define STM32_USART1CLK STM32_PCLK
903#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
904#define STM32_USART1CLK STM32_SYSCLK
905#elif STM32_USART1SW == STM32_USART1SW_LSE
906#define STM32_USART1CLK STM32_LSECLK
907#elif STM32_USART1SW == STM32_USART1SW_HSI
908#define STM32_USART1CLK STM32_HSICLK
909#else
910#error "invalid source selected for USART1 clock"
911#endif
912
913/**
914 * @brief USART2 frequency.
915 */
916#define STM32_USART2CLK STM32_PCLK
917
918/**
919 * @brief USART3 frequency.
920 */
921#define STM32_USART3CLK STM32_PCLK
922
923/**
924 * @brief USART4 frequency.
925 */
926#define STM32_UART4CLK STM32_PCLK
927
928/**
929 * @brief USART5 frequency.
930 */
931#define STM32_UART5CLK STM32_PCLK
932
933/**
934 * @brief USART6 frequency.
935 */
936#define STM32_USART6CLK STM32_PCLK
937
938/**
939 * @brief USART7 frequency.
940 */
941#define STM32_UART7CLK STM32_PCLK
942
943/**
944 * @brief USART8 frequency.
945 */
946#define STM32_UART8CLK STM32_PCLK
947
948/**
949 * @brief Timers clock.
950 */
951#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
952#define STM32_TIMCLK1 (STM32_PCLK * 1)
953#define STM32_TIMCLK2 (STM32_PCLK * 1)
954#else
955#define STM32_TIMCLK1 (STM32_PCLK * 2)
956#define STM32_TIMCLK2 (STM32_PCLK * 2)
957#endif
958
959/**
960 * @brief Flash settings.
961 */
962#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
963#define STM32_FLASHBITS 0x00000010
964#else
965#define STM32_FLASHBITS 0x00000011
966#endif
967
968/*
969 * For compatibility with driver assuming a specific PPRE clock.
970 */
971#define STM32_PCLK1 STM32_PCLK
972#define STM32_PCLK2 STM32_PCLK
973
974/*===========================================================================*/
975/* Driver data structures and types. */
976/*===========================================================================*/
977
978/*===========================================================================*/
979/* Driver macros. */
980/*===========================================================================*/
981
982/*===========================================================================*/
983/* External declarations. */
984/*===========================================================================*/
985
986/* Various helpers.*/
987#include "nvic.h"
988#include "cache.h"
989#include "stm32_isr.h"
990#include "stm32_dma.h"
991#include "stm32_exti.h"
992#include "stm32_rcc.h"
993#include "stm32_tim.h"
994
995#ifdef __cplusplus
996extern "C" {
997#endif
998 void hal_lld_init(void);
999 void stm32_clock_init(void);
1000#ifdef __cplusplus
1001}
1002#endif
1003
1004#endif /* HAL_LLD_H */
1005
1006/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 03:23:08 +0100