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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.c356
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.h1006
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/platform.mk44
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.c286
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.h246
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h965
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_registry.h2222
7 files changed, 5125 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.c
new file mode 100644
index 000000000..30115033c
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -0,0 +1,356 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/hal_lld.c
19 * @brief STM32F0xx HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31#define STM32_PLLXTPRE_OFFSET 17 /**< PLLXTPRE offset */
32#define STM32_PLLXTPRE_MASK 0x01 /**< PLLXTPRE mask */
33
34/*===========================================================================*/
35/* Driver exported variables. */
36/*===========================================================================*/
37
38/**
39 * @brief CMSIS system core clock variable.
40 * @note It is declared in system_stm32f0xx.h.
41 */
42uint32_t SystemCoreClock = STM32_HCLK;
43
44/*===========================================================================*/
45/* Driver local variables and types. */
46/*===========================================================================*/
47
48/*===========================================================================*/
49/* Driver local functions. */
50/*===========================================================================*/
51
52/**
53 * @brief Initializes the backup domain.
54 * @note WARNING! Changing clock source impossible without resetting
55 * of the whole BKP domain.
56 */
57static void hal_lld_backup_domain_init(void) {
58
59 /* Backup domain access enabled and left open.*/
60 PWR->CR |= PWR_CR_DBP;
61
62 /* Reset BKP domain if different clock source selected.*/
63 if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
64 /* Backup domain reset.*/
65 RCC->BDCR = RCC_BDCR_BDRST;
66 RCC->BDCR = 0;
67 }
68
69 /* If enabled then the LSE is started.*/
70#if STM32_LSE_ENABLED
71#if defined(STM32_LSE_BYPASS)
72 /* LSE Bypass.*/
73 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
74#else
75 /* No LSE Bypass.*/
76 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
77#endif
78 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
79 ; /* Waits until LSE is stable. */
80#endif
81
82#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
83 /* If the backup domain hasn't been initialized yet then proceed with
84 initialization.*/
85 if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
86 /* Selects clock source.*/
87 RCC->BDCR |= STM32_RTCSEL;
88
89 /* RTC clock enabled.*/
90 RCC->BDCR |= RCC_BDCR_RTCEN;
91 }
92#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
93}
94
95/*===========================================================================*/
96/* Driver interrupt handlers. */
97/*===========================================================================*/
98
99#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
100#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
101/**
102 * @brief DMA1 streams 2 and 3 shared ISR.
103 * @note It is declared here because this device has a non-standard
104 * DMA shared IRQ handler.
105 *
106 * @isr
107 */
108OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) {
109
110 OSAL_IRQ_PROLOGUE();
111
112 /* Check on channel 2.*/
113 dmaServeInterrupt(STM32_DMA1_STREAM2);
114
115 /* Check on channel 3.*/
116 dmaServeInterrupt(STM32_DMA1_STREAM3);
117
118 OSAL_IRQ_EPILOGUE();
119}
120#endif /* defined(STM32_DMA1_CH23_HANDLER) */
121
122#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
123/**
124 * @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
125 *
126 * @isr
127 */
128OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
129
130 OSAL_IRQ_PROLOGUE();
131
132 /* Check on channel 4.*/
133 dmaServeInterrupt(STM32_DMA1_STREAM4);
134
135 /* Check on channel 5.*/
136 dmaServeInterrupt(STM32_DMA1_STREAM5);
137
138#if STM32_DMA1_NUM_CHANNELS > 5
139 /* Check on channel 6.*/
140 dmaServeInterrupt(STM32_DMA1_STREAM6);
141#endif
142
143#if STM32_DMA1_NUM_CHANNELS > 6
144 /* Check on channel 7.*/
145 dmaServeInterrupt(STM32_DMA1_STREAM7);
146#endif
147
148 OSAL_IRQ_EPILOGUE();
149}
150#endif /* defined(STM32_DMA1_CH4567_HANDLER) */
151
152#if defined(STM32_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
153/**
154 * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
155 * @note It is declared here because this device has a non-standard
156 * DMA shared IRQ handler.
157 *
158 * @isr
159 */
160OSAL_IRQ_HANDLER(STM32_DMA12_CH23_CH12_HANDLER) {
161
162 OSAL_IRQ_PROLOGUE();
163
164 /* Check on channel 2 of DMA1.*/
165 dmaServeInterrupt(STM32_DMA1_STREAM2);
166
167 /* Check on channel 3 of DMA1.*/
168 dmaServeInterrupt(STM32_DMA1_STREAM3);
169
170 /* Check on channel 1 of DMA2.*/
171 dmaServeInterrupt(STM32_DMA2_STREAM1);
172
173 /* Check on channel 2 of DMA2.*/
174 dmaServeInterrupt(STM32_DMA2_STREAM2);
175
176 OSAL_IRQ_EPILOGUE();
177}
178#endif /* defined(STM32_DMA12_CH23_CH12_HANDLER) */
179
180#if defined(STM32_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
181/**
182 * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
183 * @note It is declared here because this device has a non-standard
184 * DMA shared IRQ handler.
185 *
186 * @isr
187 */
188OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
189
190 OSAL_IRQ_PROLOGUE();
191
192 /* Check on channel 4 of DMA1.*/
193 dmaServeInterrupt(STM32_DMA1_STREAM4);
194
195 /* Check on channel 5 of DMA1.*/
196 dmaServeInterrupt(STM32_DMA1_STREAM5);
197
198 /* Check on channel 6 of DMA1.*/
199 dmaServeInterrupt(STM32_DMA1_STREAM6);
200
201 /* Check on channel 7 of DMA1.*/
202 dmaServeInterrupt(STM32_DMA1_STREAM7);
203
204 /* Check on channel 3 of DMA2.*/
205 dmaServeInterrupt(STM32_DMA2_STREAM3);
206
207 /* Check on channel 4 of DMA2.*/
208 dmaServeInterrupt(STM32_DMA2_STREAM4);
209
210 /* Check on channel 5 of DMA2.*/
211 dmaServeInterrupt(STM32_DMA2_STREAM5);
212
213 OSAL_IRQ_EPILOGUE();
214}
215#endif /* defined(STM32_DMA12_CH4567_CH345_HANDLER) */
216#endif /* defined(STM32_DMA_REQUIRED) */
217
218/*===========================================================================*/
219/* Driver exported functions. */
220/*===========================================================================*/
221
222/**
223 * @brief Low level HAL driver initialization.
224 *
225 * @notapi
226 */
227void hal_lld_init(void) {
228
229 /* Reset of all peripherals.
230 Note, GPIOs are not reset because initialized before this point in
231 board files.*/
232 rccResetAHB(~STM32_GPIO_EN_MASK);
233 rccResetAPB1(0xFFFFFFFF);
234 rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
235
236 /* PWR clock enabled.*/
237 rccEnablePWRInterface(true);
238
239 /* Initializes the backup domain.*/
240 hal_lld_backup_domain_init();
241
242 /* DMA subsystems initialization.*/
243#if defined(STM32_DMA_REQUIRED)
244 dmaInit();
245#endif
246
247 /* IRQ subsystem initialization.*/
248 irqInit();
249
250 /* Programmable voltage detector enable.*/
251#if STM32_PVD_ENABLE
252 PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
253#endif /* STM32_PVD_ENABLE */
254}
255
256/**
257 * @brief STM32 clocks and PLL initialization.
258 * @note All the involved constants come from the file @p board.h.
259 * @note This function should be invoked just after the system reset.
260 *
261 * @special
262 */
263void stm32_clock_init(void) {
264
265#if !STM32_NO_INIT
266 /* HSI setup, it enforces the reset situation in order to handle possible
267 problems with JTAG probes and re-initializations.*/
268 RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
269 while (!(RCC->CR & RCC_CR_HSIRDY))
270 ; /* Wait until HSI is stable. */
271
272 /* HSI is selected as new source without touching the other fields in
273 CFGR. Clearing the register has to be postponed after HSI is the
274 new source.*/
275 RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
276 while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
277 ; /* Wait until HSI is selected. */
278
279 /* Registers finally cleared to reset values.*/
280 RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
281 RCC->CFGR = 0; /* CFGR reset value. */
282
283#if STM32_HSE_ENABLED
284 /* HSE activation.*/
285#if defined(STM32_HSE_BYPASS)
286 /* HSE Bypass.*/
287 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
288#else
289 /* No HSE Bypass.*/
290 RCC->CR |= RCC_CR_HSEON;
291#endif
292 while (!(RCC->CR & RCC_CR_HSERDY))
293 ; /* Waits until HSE is stable. */
294#endif
295
296#if STM32_HSI14_ENABLED
297 /* HSI14 activation.*/
298 RCC->CR2 |= RCC_CR2_HSI14ON;
299 while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
300 ; /* Waits until HSI14 is stable. */
301#endif
302
303#if STM32_HSI48_ENABLED
304 /* HSI48 activation.*/
305 RCC->CR2 |= RCC_CR2_HSI48ON;
306 while (!(RCC->CR2 & RCC_CR2_HSI48RDY))
307 ; /* Waits until HSI48 is stable. */
308#endif
309
310#if STM32_LSI_ENABLED
311 /* LSI activation.*/
312 RCC->CSR |= RCC_CSR_LSION;
313 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
314 ; /* Waits until LSI is stable. */
315#endif
316
317 /* Clock settings.*/
318 /* CFGR2 must be configured first since CFGR value could change CFGR2 */
319 RCC->CFGR2 = STM32_PREDIV;
320 RCC->CFGR = STM32_PLLNODIV | STM32_MCOPRE | STM32_MCOSEL | STM32_PLLMUL |
321 STM32_PLLSRC | STM32_PPRE | STM32_HPRE |
322 ((STM32_PREDIV & STM32_PLLXTPRE_MASK) << STM32_PLLXTPRE_OFFSET);
323#if STM32_CECSW == STM32_CECSW_OFF
324 RCC->CFGR3 = STM32_USBSW | STM32_I2C1SW | STM32_USART1SW;
325#else
326 RCC->CFGR3 = STM32_USBSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
327#endif
328
329#if STM32_ACTIVATE_PLL
330 /* PLL activation.*/
331 RCC->CR |= RCC_CR_PLLON;
332 while (!(RCC->CR & RCC_CR_PLLRDY))
333 ; /* Waits until PLL is stable. */
334#endif
335
336 /* Flash setup and final clock selection. */
337 FLASH->ACR = STM32_FLASHBITS;
338 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
339 (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
340 }
341
342 /* Switching to the configured clock source if it is different from HSI.*/
343#if (STM32_SW != STM32_SW_HSI)
344 /* Switches clock source.*/
345 RCC->CFGR |= STM32_SW;
346 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
347 ; /* Waits selection complete. */
348#endif
349
350 /* SYSCFG clock enabled here because it is a multi-functional unit shared
351 among multiple drivers.*/
352 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
353#endif /* !STM32_NO_INIT */
354}
355
356/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.h
new file mode 100644
index 000000000..8d65ec987
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/hal_lld.h
@@ -0,0 +1,1006 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/hal_lld.h
19 * @brief STM32F0xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC,
30 * STM32F070x6, STM32F070xB for Value Line devices.
31 * - STM32F031x6, STM32F051x8, STM32F071xB, STM32F091xC
32 * for Access Line devices.
33 * - STM32F042x6, STM32F072xB for USB Line devices.
34 * - STM32F038xx, STM32F048xx, STM32F058xx, STM32F078xx,
35 * STM32F098xx for Low Voltage Line devices.
36 * .
37 *
38 * @addtogroup HAL
39 * @{
40 */
41
42#ifndef HAL_LLD_H
43#define HAL_LLD_H
44
45/*
46 * Registry definitions.
47 */
48#include "stm32_registry.h"
49
50/*===========================================================================*/
51/* Driver constants. */
52/*===========================================================================*/
53
54/**
55 * @name Platform identification macros
56 * @{
57 */
58#if defined(STM32F030x4) || defined(__DOXYGEN__)
59#define PLATFORM_NAME "STM32F030x4 Entry Level Value Line devices"
60
61#elif defined(STM32F030x6)
62#define PLATFORM_NAME "STM32F030x6 Entry Level Value Line devices"
63
64#elif defined(STM32F030x8)
65#define PLATFORM_NAME "STM32F030x8 Entry Level Value Line devices"
66
67#elif defined(STM32F030xC)
68#define PLATFORM_NAME "STM32F030xC Entry Level Value Line devices"
69
70#elif defined(STM32F070x6)
71#define PLATFORM_NAME "STM32F070x6 Entry Level Value Line devices"
72
73#elif defined(STM32F070xB)
74#define PLATFORM_NAME "STM32F070xB Entry Level Value Line devices"
75
76#elif defined(STM32F031x6)
77#define PLATFORM_NAME "STM32F031x6 Entry Level Access Line devices"
78
79#elif defined(STM32F051x8)
80#define PLATFORM_NAME "STM32F051x8 Entry Level Access Line devices"
81
82#elif defined(STM32F071xB)
83#define PLATFORM_NAME "STM32F071xB Entry Level Access Line devices"
84
85#elif defined(STM32F091xC)
86#define PLATFORM_NAME "STM32F091xC Entry Level Access Line devices"
87
88#elif defined(STM32F042x6)
89#define PLATFORM_NAME "STM32F042x6 Entry Level USB Line devices"
90
91#elif defined(STM32F072xB)
92#define PLATFORM_NAME "STM32F072xB Entry Level USB Line devices"
93
94#elif defined(STM32F038xx)
95#define PLATFORM_NAME "STM32F038xx Entry Level Low Voltage Line devices"
96
97#elif defined(STM32F048xx)
98#define PLATFORM_NAME "STM32F048xx Entry Level Low Voltage Line devices"
99
100#elif defined(STM32F058xx)
101#define PLATFORM_NAME "STM32F058xx Entry Level Low Voltage Line devices"
102
103#elif defined(STM32F078xx)
104#define PLATFORM_NAME "STM32F078xx Entry Level Low Voltage Line devices"
105
106#elif defined(STM32F098xx)
107#define PLATFORM_NAME "STM32F098xx Entry Level Low Voltage Line devices"
108
109#else
110#error "STM32F0xx device unsupported or not specified"
111#endif
112/** @} */
113
114/**
115 * @name Absolute Maximum Ratings
116 * @{
117 */
118/**
119 * @brief Maximum system clock frequency.
120 */
121#define STM32_SYSCLK_MAX 48000000
122
123/**
124 * @brief Maximum HSE clock frequency.
125 */
126#define STM32_HSECLK_MAX 32000000
127
128/**
129 * @brief Minimum HSE clock frequency.
130 */
131#define STM32_HSECLK_MIN 1000000
132
133/**
134 * @brief Maximum LSE clock frequency.
135 */
136#define STM32_LSECLK_MAX 1000000
137
138/**
139 * @brief Minimum LSE clock frequency.
140 */
141#define STM32_LSECLK_MIN 32768
142
143/**
144 * @brief Maximum PLLs input clock frequency.
145 */
146#define STM32_PLLIN_MAX 25000000
147
148/**
149 * @brief Minimum PLLs input clock frequency.
150 */
151#define STM32_PLLIN_MIN 1000000
152
153/**
154 * @brief Maximum PLL output clock frequency.
155 */
156#define STM32_PLLOUT_MAX 48000000
157
158/**
159 * @brief Minimum PLL output clock frequency.
160 */
161#define STM32_PLLOUT_MIN 16000000
162
163/**
164 * @brief Maximum APB clock frequency.
165 */
166#define STM32_PCLK_MAX 48000000
167/** @} */
168
169/**
170 * @name Internal clock sources
171 * @{
172 */
173#define STM32_HSICLK 8000000 /**< High speed internal clock. */
174#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/
175#define STM32_HSI48CLK 48000000 /**< 48MHz speed internal clock.*/
176#define STM32_LSICLK 40000 /**< Low speed internal clock. */
177/** @} */
178
179/**
180 * @name PWR_CR register bits definitions
181 * @{
182 */
183#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
184#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
185#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
186#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
187#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
188#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
189#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
190#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
191#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
192/** @} */
193
194/**
195 * @name RCC_CFGR register bits definitions
196 * @{
197 */
198#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
199#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
200#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
201#define STM32_SW_HSI48 (3 << 0) /**< SYSCLK source is HSI48. */
202
203#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
204#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
205#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
206#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
207#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
208#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
209#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
210#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
211#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
212
213#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */
214#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */
215#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */
216#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */
217#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */
218
219#define STM32_PLLSRC_HSI_DIV2 (0 << 15) /**< PLL clock source is HSI/2. */
220#define STM32_PLLSRC_HSI (1 << 15) /**< PLL clock source is HSI */
221#define STM32_PLLSRC_HSE (2 << 15) /**< PLL clock source is HSE. */
222#define STM32_PLLSRC_HSI48 (3 << 15) /**< PLL clock source is HSI48. */
223
224#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
225#define STM32_MCOSEL_HSI14 (1 << 24) /**< HSI14 clock on MCO pin. */
226#define STM32_MCOSEL_LSI (2 << 24) /**< LSI clock on MCO pin. */
227#define STM32_MCOSEL_LSE (3 << 24) /**< LSE clock on MCO pin. */
228#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
229#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
230#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
231#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
232#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
233
234#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
235#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
236#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
237#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
238#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
239#define STM32_MCOPRE_DIV32 (5 << 28) /**< MCO divided by 32. */
240#define STM32_MCOPRE_DIV64 (6 << 28) /**< MCO divided by 64. */
241#define STM32_MCOPRE_DIV128 (7 << 28) /**< MCO divided by 128. */
242
243#define STM32_PLLNODIV_MASK (1 << 31) /**< MCO PLL divider mask. */
244#define STM32_PLLNODIV_DIV2 (0 << 31) /**< MCO PLL is divided by two. */
245#define STM32_PLLNODIV_DIV1 (1 << 31) /**< MCO PLL is divided by one. */
246/** @} */
247
248/**
249 * @name RCC_CFGR2 register bits definitions
250 * @{
251 */
252#define STM32_PRE_DIV1 (0 << 0) /**< PLLSRC divided by 1. */
253#define STM32_PRE_DIV2 (1 << 0) /**< SYSCLK divided by 2. */
254#define STM32_PRE_DIV3 (2 << 0) /**< SYSCLK divided by 3. */
255#define STM32_PRE_DIV4 (3 << 0) /**< PLLSRC divided by 4. */
256#define STM32_PRE_DIV5 (4 << 0) /**< SYSCLK divided by 5. */
257#define STM32_PRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */
258#define STM32_PRE_DIV7 (6 << 0) /**< PLLSRC divided by 7. */
259#define STM32_PRE_DIV8 (7 << 0) /**< SYSCLK divided by 8. */
260#define STM32_PRE_DIV9 (8 << 0) /**< SYSCLK divided by 9. */
261#define STM32_PRE_DIV10 (9 << 0) /**< PLLSRC divided by 10. */
262#define STM32_PRE_DIV11 (10 << 0) /**< SYSCLK divided by 11. */
263#define STM32_PRE_DIV12 (11 << 0) /**< SYSCLK divided by 12. */
264#define STM32_PRE_DIV13 (12 << 0) /**< PLLSRC divided by 13. */
265#define STM32_PRE_DIV14 (13 << 0) /**< SYSCLK divided by 14. */
266#define STM32_PRE_DIV15 (14 << 0) /**< SYSCLK divided by 15. */
267#define STM32_PRE_DIV16 (15 << 0) /**< PLLSRC divided by 16. */
268/** @} */
269
270/**
271 * @name RCC_CFGR3 register bits definitions
272 * @{
273 */
274#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */
275#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */
276#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
277#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */
278#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */
279#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */
280#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */
281#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */
282#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
283#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
284#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
285#define STM32_CECSW_OFF 0xFFFFFFFF /**< CEC clock is not required. */
286#define STM32_USBSW_MASK (1 << 7) /**< USB clock source mask. */
287#define STM32_USBSW_HSI48 (0 << 7) /**< USB clock is HSI48. */
288#define STM32_USBSW_PCLK (1 << 7) /**< USB clock is PCLK. */
289/** @} */
290
291/**
292 * @name RCC_BDCR register bits definitions
293 * @{
294 */
295#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
296#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
297#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
298#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
299#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as
300 RTC clock. */
301/** @} */
302
303/*===========================================================================*/
304/* Driver pre-compile time settings. */
305/*===========================================================================*/
306
307/**
308 * @name Configuration options
309 * @{
310 */
311/**
312 * @brief Disables the PWR/RCC initialization in the HAL.
313 */
314#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
315#define STM32_NO_INIT FALSE
316#endif
317
318/**
319 * @brief Enables or disables the programmable voltage detector.
320 */
321#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
322#define STM32_PVD_ENABLE FALSE
323#endif
324
325/**
326 * @brief Sets voltage level for programmable voltage detector.
327 */
328#if !defined(STM32_PLS) || defined(__DOXYGEN__)
329#define STM32_PLS STM32_PLS_LEV0
330#endif
331
332/**
333 * @brief Enables or disables the HSI clock source.
334 */
335#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
336#define STM32_HSI_ENABLED TRUE
337#endif
338
339/**
340 * @brief Enables or disables the HSI14 clock source.
341 */
342#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
343#define STM32_HSI14_ENABLED TRUE
344#endif
345
346/**
347 * @brief Enables or disables the HSI48 clock source.
348 */
349#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
350#define STM32_HSI48_ENABLED FALSE
351#endif
352
353/**
354 * @brief Enables or disables the LSI clock source.
355 */
356#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
357#define STM32_LSI_ENABLED FALSE
358#endif
359
360/**
361 * @brief Enables or disables the HSE clock source.
362 */
363#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
364#define STM32_HSE_ENABLED TRUE
365#endif
366
367/**
368 * @brief Enables or disables the LSE clock source.
369 */
370#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
371#define STM32_LSE_ENABLED FALSE
372#endif
373
374/**
375 * @brief Main clock source selection.
376 * @note If the selected clock source is not the PLL then the PLL is not
377 * initialized and started.
378 * @note The default value is calculated for a 48MHz system clock from
379 * a 8MHz crystal using the PLL.
380 */
381#if !defined(STM32_SW) || defined(__DOXYGEN__)
382#define STM32_SW STM32_SW_PLL
383#endif
384
385/**
386 * @brief Clock source for the PLL.
387 * @note This setting has only effect if the PLL is selected as the
388 * system clock source.
389 * @note The default value is calculated for a 48MHz system clock from
390 * a 8MHz crystal using the PLL.
391 */
392#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
393#define STM32_PLLSRC STM32_PLLSRC_HSE
394#endif
395
396/**
397 * @brief Crystal PLL pre-divider.
398 * @note This setting has only effect if the PLL is selected as the
399 * system clock source.
400 * @note The default value is calculated for a 72MHz system clock from
401 * a 8MHz crystal using the PLL.
402 */
403#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
404#define STM32_PREDIV_VALUE 1
405#endif
406
407/**
408 * @brief PLL multiplier value.
409 * @note The allowed range is 2...16.
410 * @note The default value is calculated for a 48MHz system clock from
411 * a 8MHz crystal using the PLL.
412 */
413#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
414#define STM32_PLLMUL_VALUE 6
415#endif
416
417/**
418 * @brief AHB prescaler value.
419 * @note The default value is calculated for a 48MHz system clock from
420 * a 8MHz crystal using the PLL.
421 */
422#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
423#define STM32_HPRE STM32_HPRE_DIV1
424#endif
425
426/**
427 * @brief APB1 prescaler value.
428 */
429#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
430#define STM32_PPRE STM32_PPRE_DIV1
431#endif
432
433/**
434 * @brief MCO pin setting.
435 */
436#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
437#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
438#endif
439
440/**
441 * @brief MCO divider setting.
442 */
443#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
444#define STM32_MCOPRE STM32_MCOPRE_DIV1
445#endif
446
447/**
448 * @brief MCO PLL divider setting.
449 */
450#if !defined(STM32_PLLNODIV) || defined(__DOXYGEN__)
451#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
452#endif
453
454/**
455 * @brief USB Clock source.
456 */
457#if !defined(STM32_USBSW) || defined(__DOXYGEN__)
458#define STM32_USBSW STM32_USBSW_HSI48
459#endif
460
461/**
462 * @brief CEC clock source.
463 */
464#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
465#define STM32_CECSW STM32_CECSW_HSI
466#endif
467
468/**
469 * @brief I2C1 clock source.
470 */
471#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
472#define STM32_I2C1SW STM32_I2C1SW_HSI
473#endif
474
475/**
476 * @brief USART1 clock source.
477 */
478#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
479#define STM32_USART1SW STM32_USART1SW_PCLK
480#endif
481
482/**
483 * @brief RTC clock source.
484 */
485#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
486#define STM32_RTCSEL STM32_RTCSEL_LSI
487#endif
488/** @} */
489
490/*===========================================================================*/
491/* Derived constants and error checks. */
492/*===========================================================================*/
493
494/*
495 * Configuration-related checks.
496 */
497#if !defined(STM32F0xx_MCUCONF)
498#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
499#endif
500
501/*
502 * HSI related checks.
503 */
504#if STM32_HSI_ENABLED
505#if (STM32_SW == STM32_SW_PLL) && \
506 (STM32_PLLSRC == STM32_PLLSRC_HSI) && !STM32_HAS_HSI_PREDIV
507#error "STM32_PLLSRC_HSI not available on this platform. Select STM32_PLLSRC_HSI_DIV2 instead."
508#endif
509#else /* !STM32_HSI_ENABLED */
510
511#if STM32_SW == STM32_SW_HSI
512#error "HSI not enabled, required by STM32_SW"
513#endif
514
515#if STM32_CECSW == STM32_CECSW_HSI
516#error "HSI not enabled, required by STM32_CECSW"
517#endif
518
519#if STM32_I2C1SW == STM32_I2C1SW_HSI
520#error "HSI not enabled, required by STM32_I2C1SW"
521#endif
522
523#if STM32_USART1SW == STM32_USART1SW_HSI
524#error "HSI not enabled, required by STM32_USART1SW"
525#endif
526
527#if (STM32_SW == STM32_SW_PLL) && \
528 (STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
529 (STM32_PLLSRC == STM32_PLLSRC_HSI)
530#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
531#endif
532
533#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
534 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
535 ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
536 (STM32_PLLSRC == STM32_PLLSRC_HSI)))
537#error "HSI not enabled, required by STM32_MCOSEL"
538#endif
539
540#endif /* !STM32_HSI_ENABLED */
541
542/*
543 * HSI14 related checks.
544 */
545#if STM32_HSI14_ENABLED
546#else /* !STM32_HSI14_ENABLED */
547
548#if STM32_MCOSEL == STM32_MCOSEL_HSI14
549#error "HSI14 not enabled, required by STM32_MCOSEL"
550#endif
551
552#endif /* !STM32_HSI14_ENABLED */
553
554/*
555 * HSI48 related checks.
556 */
557#if STM32_HSI48_ENABLED
558#if !STM32_HAS_HSI48
559#error "HSI48 not available on this platform"
560#endif
561#else /* !STM32_HSI48_ENABLED */
562
563#if STM32_SW == STM32_SW_HSI48
564#error "HSI48 not enabled, required by STM32_SW"
565#endif
566
567#if (STM32_MCOSEL == STM32_MCOSEL_HSI48) || \
568 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
569 ((STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2) || \
570 (STM32_PLLSRC == STM32_PLLSRC_HSI48)))
571#error "HSI48 not enabled, required by STM32_MCOSEL"
572#endif
573
574#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI48)
575#error "HSI48 not enabled, required by STM32_SW and STM32_PLLSRC"
576#endif
577
578#endif /* !STM32_HSI48_ENABLED */
579
580/*
581 * HSE related checks.
582 */
583#if STM32_HSE_ENABLED
584
585#if STM32_HSECLK == 0
586#error "HSE frequency not defined"
587#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
588#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
589#endif
590
591#else /* !STM32_HSE_ENABLED */
592
593#if STM32_SW == STM32_SW_HSE
594#error "HSE not enabled, required by STM32_SW"
595#endif
596
597#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
598#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
599#endif
600
601#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
602 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
603 (STM32_PLLSRC == STM32_PLLSRC_HSE))
604#error "HSE not enabled, required by STM32_MCOSEL"
605#endif
606
607#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
608#error "HSE not enabled, required by STM32_RTCSEL"
609#endif
610
611#endif /* !STM32_HSE_ENABLED */
612
613/*
614 * LSI related checks.
615 */
616#if STM32_LSI_ENABLED
617#else /* !STM32_LSI_ENABLED */
618
619#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
620#error "LSI not enabled, required by STM32_RTCSEL"
621#endif
622
623#endif /* !STM32_LSI_ENABLED */
624
625/*
626 * LSE related checks.
627 */
628#if STM32_LSE_ENABLED
629
630#if (STM32_LSECLK == 0)
631#error "LSE frequency not defined"
632#endif
633
634#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
635#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
636#endif
637
638#if !defined(STM32_LSEDRV)
639#error "STM32_LSEDRV not defined"
640#endif
641
642#if (STM32_LSEDRV >> 3) > 3
643#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
644#endif
645
646#else /* !STM32_LSE_ENABLED */
647
648#if STM32_CECSW == STM32_CECSW_LSE
649#error "LSE not enabled, required by STM32_CECSW"
650#endif
651
652#if STM32_USART1SW == STM32_USART1SW_LSE
653#error "LSE not enabled, required by STM32_USART1SW"
654#endif
655
656#if STM32_RTCSEL == STM32_RTCSEL_LSE
657#error "LSE not enabled, required by STM32_RTCSEL"
658#endif
659
660#endif /* !STM32_LSE_ENABLED */
661
662/* PLL activation conditions.*/
663#if (STM32_SW == STM32_SW_PLL) || \
664 (STM32_USBSW == STM32_USBSW_PCLK) || \
665 (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
666 defined(__DOXYGEN__)
667/**
668 * @brief PLL activation flag.
669 */
670#define STM32_ACTIVATE_PLL TRUE
671#else
672#define STM32_ACTIVATE_PLL FALSE
673#endif
674
675/* HSE, HSI prescaler setting check.*/
676#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
677#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
678#else
679#error "invalid STM32_PREDIV value specified"
680#endif
681
682/**
683 * @brief PLLMUL field.
684 */
685#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
686 defined(__DOXYGEN__)
687#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
688#else
689#error "invalid STM32_PLLMUL_VALUE value specified"
690#endif
691
692/**
693 * @brief PLL input clock frequency.
694 */
695#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
696#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
697#elif STM32_PLLSRC == STM32_PLLSRC_HSI_DIV2
698#define STM32_PLLCLKIN (STM32_HSICLK / 2)
699#elif STM32_PLLSRC == STM32_PLLSRC_HSI
700#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PREDIV_VALUE)
701#elif STM32_PLLSRC == STM32_PLLSRC_HSI48
702#define STM32_PLLCLKIN (STM32_HSI48CLK / STM32_PREDIV_VALUE)
703#else
704#error "invalid STM32_PLLSRC value specified"
705#endif
706
707/* PLL input frequency range check.*/
708#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
709#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
710#endif
711
712/**
713 * @brief PLL output clock frequency.
714 */
715#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
716
717/* PLL output frequency range check.*/
718#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
719#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
720#endif
721
722/**
723 * @brief System clock source.
724 */
725#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
726#define STM32_SYSCLK STM32_PLLCLKOUT
727#elif (STM32_SW == STM32_SW_HSI)
728#define STM32_SYSCLK STM32_HSICLK
729#elif (STM32_SW == STM32_SW_HSI48)
730#define STM32_SYSCLK STM32_HSI48CLK
731#elif (STM32_SW == STM32_SW_HSE)
732#define STM32_SYSCLK STM32_HSECLK
733#else
734#error "invalid STM32_SW value specified"
735#endif
736
737/* Check on the system clock.*/
738#if STM32_SYSCLK > STM32_SYSCLK_MAX
739#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
740#endif
741
742/**
743 * @brief AHB frequency.
744 */
745#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
746#define STM32_HCLK (STM32_SYSCLK / 1)
747#elif STM32_HPRE == STM32_HPRE_DIV2
748#define STM32_HCLK (STM32_SYSCLK / 2)
749#elif STM32_HPRE == STM32_HPRE_DIV4
750#define STM32_HCLK (STM32_SYSCLK / 4)
751#elif STM32_HPRE == STM32_HPRE_DIV8
752#define STM32_HCLK (STM32_SYSCLK / 8)
753#elif STM32_HPRE == STM32_HPRE_DIV16
754#define STM32_HCLK (STM32_SYSCLK / 16)
755#elif STM32_HPRE == STM32_HPRE_DIV64
756#define STM32_HCLK (STM32_SYSCLK / 64)
757#elif STM32_HPRE == STM32_HPRE_DIV128
758#define STM32_HCLK (STM32_SYSCLK / 128)
759#elif STM32_HPRE == STM32_HPRE_DIV256
760#define STM32_HCLK (STM32_SYSCLK / 256)
761#elif STM32_HPRE == STM32_HPRE_DIV512
762#define STM32_HCLK (STM32_SYSCLK / 512)
763#else
764#error "invalid STM32_HPRE value specified"
765#endif
766
767/* AHB frequency check.*/
768#if STM32_HCLK > STM32_SYSCLK_MAX
769#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
770#endif
771
772/**
773 * @brief APB frequency.
774 */
775#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
776#define STM32_PCLK (STM32_HCLK / 1)
777#elif STM32_PPRE == STM32_PPRE_DIV2
778#define STM32_PCLK (STM32_HCLK / 2)
779#elif STM32_PPRE == STM32_PPRE_DIV4
780#define STM32_PCLK (STM32_HCLK / 4)
781#elif STM32_PPRE == STM32_PPRE_DIV8
782#define STM32_PCLK (STM32_HCLK / 8)
783#elif STM32_PPRE == STM32_PPRE_DIV16
784#define STM32_PCLK (STM32_HCLK / 16)
785#else
786#error "invalid STM32_PPRE value specified"
787#endif
788
789/* APB frequency check.*/
790#if STM32_PCLK > STM32_PCLK_MAX
791#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
792#endif
793
794/* STM32_PLLNODIV check.*/
795#if (STM32_PLLNODIV != STM32_PLLNODIV_DIV2) && \
796 (STM32_PLLNODIV != STM32_PLLNODIV_DIV1)
797#error "invalid STM32_PLLNODIV value specified"
798#endif
799
800/**
801 * @brief MCO clock before divider.
802 */
803#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
804#define STM32_MCODIVCLK 0
805#elif STM32_MCOSEL == STM32_MCOSEL_HSI14
806#define STM32_MCODIVCLK STM32_HSI14CLK
807#elif STM32_MCOSEL == STM32_MCOSEL_LSI
808#define STM32_MCODIVCLK STM32_LSICLK
809#elif STM32_MCOSEL == STM32_MCOSEL_LSE
810#define STM32_MCODIVCLK STM32_LSECLK
811#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
812#define STM32_MCODIVCLK STM32_SYSCLK
813#elif STM32_MCOSEL == STM32_MCOSEL_HSI
814#define STM32_MCODIVCLK STM32_HSICLK
815#elif STM32_MCOSEL == STM32_MCOSEL_HSE
816#define STM32_MCODIVCLK STM32_HSECLK
817#elif STM32_MCOSEL == STM32_MCOSEL_PLLDIV2
818#if STM32_PLLNODIV == STM32_PLLNODIV_DIV2
819#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 2)
820#else
821#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 1)
822#endif
823#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
824#define STM32_MCODIVCLK STM32_HSI48CLK
825#else
826#error "invalid STM32_MCOSEL value specified"
827#endif
828
829/**
830 * @brief MCO output pin clock.
831 */
832#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
833#define STM32_MCOCLK STM32_MCODIVCLK
834#elif (STM32_MCOPRE == STM32_MCOPRE_DIV2) && STM32_HAS_MCO_PREDIV
835#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
836#elif (STM32_MCOPRE == STM32_MCOPRE_DIV4) && STM32_HAS_MCO_PREDIV
837#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
838#elif (STM32_MCOPRE == STM32_MCOPRE_DIV8) && STM32_HAS_MCO_PREDIV
839#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
840#elif (STM32_MCOPRE == STM32_MCOPRE_DIV16) && STM32_HAS_MCO_PREDIV
841#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
842#elif !STM32_HAS_MCO_PREDIV
843#error "MCO_PREDIV not available on this platform. Select STM32_MCODIVCLK."
844#else
845#error "invalid STM32_MCOPRE value specified"
846#endif
847
848/**
849 * @brief RTC clock.
850 */
851#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
852#define STM32_RTCCLK STM32_LSECLK
853#elif STM32_RTCSEL == STM32_RTCSEL_LSI
854#define STM32_RTCCLK STM32_LSICLK
855#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
856#define STM32_RTCCLK (STM32_HSECLK / 32)
857#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
858#define STM32_RTCCLK 0
859#else
860#error "invalid source selected for RTC clock"
861#endif
862
863/**
864 * @brief USB frequency.
865 */
866#if (STM32_USBSW == STM32_USBSW_HSI48) || defined(__DOXYGEN__)
867#define STM32_USBCLK STM32_HSI48CLK
868#elif STM32_USBSW == STM32_USBSW_PCLK
869#define STM32_USBCLK STM32_PLLCLKOUT
870#else
871#error "invalid source selected for USB clock"
872#endif
873
874/**
875 * @brief CEC frequency.
876 */
877#if (STM32_CECSW == STM32_CECSW_HSI) || defined(__DOXYGEN__)
878#define STM32_CECCLK STM32_HSICLK
879#elif STM32_CECSW == STM32_CECSW_LSE
880#define STM32_CECCLK STM32_LSECLK
881#elif STM32_CECSW == STM32_CECSW_OFF
882#define STM32_CECCLK 0
883#else
884#error "invalid source selected for CEC clock"
885#endif
886
887/**
888 * @brief I2C1 frequency.
889 */
890#if (STM32_I2C1SW == STM32_I2C1SW_HSI) || defined(__DOXYGEN__)
891#define STM32_I2C1CLK STM32_HSICLK
892#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
893#define STM32_I2C1CLK STM32_SYSCLK
894#else
895#error "invalid source selected for I2C1 clock"
896#endif
897
898/**
899 * @brief USART1 frequency.
900 */
901#if (STM32_USART1SW == STM32_USART1SW_PCLK) || defined(__DOXYGEN__)
902#define STM32_USART1CLK STM32_PCLK
903#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
904#define STM32_USART1CLK STM32_SYSCLK
905#elif STM32_USART1SW == STM32_USART1SW_LSE
906#define STM32_USART1CLK STM32_LSECLK
907#elif STM32_USART1SW == STM32_USART1SW_HSI
908#define STM32_USART1CLK STM32_HSICLK
909#else
910#error "invalid source selected for USART1 clock"
911#endif
912
913/**
914 * @brief USART2 frequency.
915 */
916#define STM32_USART2CLK STM32_PCLK
917
918/**
919 * @brief USART3 frequency.
920 */
921#define STM32_USART3CLK STM32_PCLK
922
923/**
924 * @brief USART4 frequency.
925 */
926#define STM32_UART4CLK STM32_PCLK
927
928/**
929 * @brief USART5 frequency.
930 */
931#define STM32_UART5CLK STM32_PCLK
932
933/**
934 * @brief USART6 frequency.
935 */
936#define STM32_USART6CLK STM32_PCLK
937
938/**
939 * @brief USART7 frequency.
940 */
941#define STM32_UART7CLK STM32_PCLK
942
943/**
944 * @brief USART8 frequency.
945 */
946#define STM32_UART8CLK STM32_PCLK
947
948/**
949 * @brief Timers clock.
950 */
951#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
952#define STM32_TIMCLK1 (STM32_PCLK * 1)
953#define STM32_TIMCLK2 (STM32_PCLK * 1)
954#else
955#define STM32_TIMCLK1 (STM32_PCLK * 2)
956#define STM32_TIMCLK2 (STM32_PCLK * 2)
957#endif
958
959/**
960 * @brief Flash settings.
961 */
962#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
963#define STM32_FLASHBITS 0x00000010
964#else
965#define STM32_FLASHBITS 0x00000011
966#endif
967
968/*
969 * For compatibility with driver assuming a specific PPRE clock.
970 */
971#define STM32_PCLK1 STM32_PCLK
972#define STM32_PCLK2 STM32_PCLK
973
974/*===========================================================================*/
975/* Driver data structures and types. */
976/*===========================================================================*/
977
978/*===========================================================================*/
979/* Driver macros. */
980/*===========================================================================*/
981
982/*===========================================================================*/
983/* External declarations. */
984/*===========================================================================*/
985
986/* Various helpers.*/
987#include "nvic.h"
988#include "cache.h"
989#include "stm32_isr.h"
990#include "stm32_dma.h"
991#include "stm32_exti.h"
992#include "stm32_rcc.h"
993#include "stm32_tim.h"
994
995#ifdef __cplusplus
996extern "C" {
997#endif
998 void hal_lld_init(void);
999 void stm32_clock_init(void);
1000#ifdef __cplusplus
1001}
1002#endif
1003
1004#endif /* HAL_LLD_H */
1005
1006/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/platform.mk b/lib/chibios/os/hal/ports/STM32/STM32F0xx/platform.mk
new file mode 100644
index 000000000..276f3556a
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -0,0 +1,44 @@
1# Required platform files.
2PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
3 $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/stm32_isr.c \
4 $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c
5
6# Required include directories.
7PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
8 $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx
9
10# Optional platform files.
11ifeq ($(USE_SMART_BUILD),yes)
12
13# Configuration files directory
14ifeq ($(HALCONFDIR),)
15 ifeq ($(CONFDIR),)
16 HALCONFDIR = .
17 else
18 HALCONFDIR := $(CONFDIR)
19 endif
20endif
21
22HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
23
24else
25endif
26
27# Drivers compatible with the platform.
28include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/driver.mk
29include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
30include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
31include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
32include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
33include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
34include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
35include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
36include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
37include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
38include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
39include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
40include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
41
42# Shared variables
43ALLCSRC += $(PLATFORMSRC)
44ALLINC += $(PLATFORMINC)
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.c
new file mode 100644
index 000000000..6077862e1
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.c
@@ -0,0 +1,286 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/stm32_isr.c
19 * @brief STM32F0xx ISR handler code.
20 *
21 * @addtogroup STM32F0xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/*===========================================================================*/
36/* Driver local variables. */
37/*===========================================================================*/
38
39/*===========================================================================*/
40/* Driver local functions. */
41/*===========================================================================*/
42
43#define exti_serve_irq(pr, channel) { \
44 \
45 if ((pr) & (1U << (channel))) { \
46 _pal_isr_code(channel); \
47 } \
48}
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
55#if !defined(STM32_DISABLE_EXTI0_1_HANDLER)
56/**
57 * @brief EXTI[0]...EXTI[1] interrupt handler.
58 *
59 * @isr
60 */
61OSAL_IRQ_HANDLER(Vector54) {
62 uint32_t pr;
63
64 OSAL_IRQ_PROLOGUE();
65
66 pr = EXTI->PR;
67 pr &= ((1U << 0) | (1U << 1));
68 EXTI->PR = pr;
69
70 exti_serve_irq(pr, 0);
71 exti_serve_irq(pr, 1);
72
73 OSAL_IRQ_EPILOGUE();
74}
75#endif
76
77#if !defined(STM32_DISABLE_EXTI2_3_HANDLER)
78/**
79 * @brief EXTI[2]...EXTI[3] interrupt handler.
80 *
81 * @isr
82 */
83OSAL_IRQ_HANDLER(Vector58) {
84 uint32_t pr;
85
86 OSAL_IRQ_PROLOGUE();
87
88 pr = EXTI->PR;
89 pr &= ((1U << 2) | (1U << 3));
90 EXTI->PR = pr;
91
92 exti_serve_irq(pr, 2);
93 exti_serve_irq(pr, 3);
94
95 OSAL_IRQ_EPILOGUE();
96}
97#endif
98
99#if !defined(STM32_DISABLE_EXTI4_15_HANDLER)
100/**
101 * @brief EXTI[4]...EXTI[15] interrupt handler.
102 *
103 * @isr
104 */
105OSAL_IRQ_HANDLER(Vector5C) {
106 uint32_t pr;
107
108 OSAL_IRQ_PROLOGUE();
109
110 pr = EXTI->PR;
111 pr &= ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
112 (1U << 9) | (1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
113 (1U << 14) | (1U << 15));
114 EXTI->PR = pr;
115
116 exti_serve_irq(pr, 4);
117 exti_serve_irq(pr, 5);
118 exti_serve_irq(pr, 6);
119 exti_serve_irq(pr, 7);
120 exti_serve_irq(pr, 8);
121 exti_serve_irq(pr, 9);
122 exti_serve_irq(pr, 10);
123 exti_serve_irq(pr, 11);
124 exti_serve_irq(pr, 12);
125 exti_serve_irq(pr, 13);
126 exti_serve_irq(pr, 14);
127 exti_serve_irq(pr, 15);
128
129 OSAL_IRQ_EPILOGUE();
130}
131#endif
132
133#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
134
135#if HAL_USE_SERIAL || HAL_USE_UART || defined(__DOXYGEN__)
136#if !defined(STM32_DISABLE_USART1_HANDLER)
137/**
138 * @brief USART1 interrupt handler.
139 *
140 * @isr
141 */
142OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
143
144 OSAL_IRQ_PROLOGUE();
145
146#if HAL_USE_SERIAL
147#if STM32_SERIAL_USE_USART1
148 sd_lld_serve_interrupt(&SD1);
149#endif
150#endif
151#if HAL_USE_UART
152#if STM32_UART_USE_USART1
153 uart_lld_serve_interrupt(&UARTD1);
154#endif
155#endif
156
157 OSAL_IRQ_EPILOGUE();
158}
159#endif
160
161#if !defined(STM32_DISABLE_USART2_HANDLER)
162/**
163 * @brief USART2 interrupt handler.
164 *
165 * @isr
166 */
167OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
168
169 OSAL_IRQ_PROLOGUE();
170
171#if HAL_USE_SERIAL
172#if STM32_SERIAL_USE_USART2
173 sd_lld_serve_interrupt(&SD2);
174#endif
175#endif
176#if HAL_USE_UART
177#if STM32_UART_USE_USART2
178 uart_lld_serve_interrupt(&UARTD2);
179#endif
180#endif
181
182 OSAL_IRQ_EPILOGUE();
183}
184#endif
185
186#if !defined(STM32_DISABLE_USART38_HANDLER)
187/**
188 * @brief USART3..8 interrupt handler.
189 *
190 * @isr
191 */
192OSAL_IRQ_HANDLER(STM32_USART3_8_HANDLER) {
193
194 OSAL_IRQ_PROLOGUE();
195
196#if HAL_USE_SERIAL
197#if STM32_SERIAL_USE_USART3
198 sd_lld_serve_interrupt(&SD3);
199#endif
200#if STM32_SERIAL_USE_UART4
201 sd_lld_serve_interrupt(&SD4);
202#endif
203#if STM32_SERIAL_USE_UART5
204 sd_lld_serve_interrupt(&SD5);
205#endif
206#if STM32_SERIAL_USE_USART6
207 sd_lld_serve_interrupt(&SD6);
208#endif
209#if STM32_SERIAL_USE_UART7
210 sd_lld_serve_interrupt(&SD7);
211#endif
212#if STM32_SERIAL_USE_UART8
213 sd_lld_serve_interrupt(&SD8);
214#endif
215#endif
216#if HAL_USE_UART
217#if STM32_UART_USE_USART3
218 uart_lld_serve_interrupt(&UARTD3);
219#endif
220#if STM32_UART_USE_UART4
221 uart_lld_serve_interrupt(&UARTD4);
222#endif
223#if STM32_UART_USE_UART5
224 uart_lld_serve_interrupt(&UARTD5);
225#endif
226#if STM32_UART_USE_USART6
227 uart_lld_serve_interrupt(&UARTD6);
228#endif
229#if STM32_UART_USE_UART7
230 uart_lld_serve_interrupt(&UARTD7);
231#endif
232#if STM32_UART_USE_UART8
233 uart_lld_serve_interrupt(&UARTD8);
234#endif
235#endif
236
237 OSAL_IRQ_EPILOGUE();
238}
239#endif
240#endif /* HAL_USE_SERIAL || HAL_USE_UART */
241
242/*===========================================================================*/
243/* Driver exported functions. */
244/*===========================================================================*/
245
246/**
247 * @brief Enables IRQ sources.
248 *
249 * @notapi
250 */
251void irqInit(void) {
252
253#if HAL_USE_PAL
254 nvicEnableVector(EXTI0_1_IRQn, STM32_IRQ_EXTI0_1_PRIORITY);
255 nvicEnableVector(EXTI2_3_IRQn, STM32_IRQ_EXTI2_3_PRIORITY);
256 nvicEnableVector(EXTI4_15_IRQn, STM32_IRQ_EXTI4_15_PRIORITY);
257#endif
258
259#if HAL_USE_SERIAL || HAL_USE_UART
260 nvicEnableVector(STM32_USART1_NUMBER, STM32_IRQ_USART1_PRIORITY);
261 nvicEnableVector(STM32_USART2_NUMBER, STM32_IRQ_USART2_PRIORITY);
262 nvicEnableVector(STM32_USART3_8_NUMBER, STM32_IRQ_USART3_8_PRIORITY);
263#endif
264}
265
266/**
267 * @brief Disables IRQ sources.
268 *
269 * @notapi
270 */
271void irqDeinit(void) {
272
273#if HAL_USE_PAL
274 nvicDisableVector(EXTI0_1_IRQn);
275 nvicDisableVector(EXTI2_3_IRQn);
276 nvicDisableVector(EXTI4_15_IRQn);
277#endif
278
279#if HAL_USE_SERIAL || HAL_USE_UART
280 nvicDisableVector(STM32_USART1_NUMBER);
281 nvicDisableVector(STM32_USART2_NUMBER);
282 nvicDisableVector(STM32_USART3_8_NUMBER);
283#endif
284}
285
286/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
new file mode 100644
index 000000000..25b4cef35
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
@@ -0,0 +1,246 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/stm32_isr.h
19 * @brief STM32F0xx ISR handler header.
20 *
21 * @addtogroup STM32F0xx_ISR
22 * @{
23 */
24
25#ifndef STM32_ISR_H
26#define STM32_ISR_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name ISRs suppressed in standard drivers
34 * @{
35 */
36#define STM32_USART1_SUPPRESS_ISR
37#define STM32_USART2_SUPPRESS_ISR
38#define STM32_USART3_SUPPRESS_ISR
39#define STM32_UART4_SUPPRESS_ISR
40#define STM32_UART5_SUPPRESS_ISR
41#define STM32_USART6_SUPPRESS_ISR
42#define STM32_UART7_SUPPRESS_ISR
43#define STM32_UART8_SUPPRESS_ISR
44/** @} */
45
46/**
47 * @name ISR names and numbers remapping
48 * @{
49 */
50/*
51 * CAN units.
52 */
53#define STM32_CAN1_UNIFIED_HANDLER VectorB8
54#define STM32_CAN1_UNIFIED_NUMBER 30
55
56/*
57 * I2C units.
58 */
59#define STM32_I2C1_GLOBAL_HANDLER Vector9C
60#define STM32_I2C1_GLOBAL_NUMBER 23
61
62#define STM32_I2C2_GLOBAL_HANDLER VectorA0
63#define STM32_I2C2_GLOBAL_NUMBER 24
64
65/*
66 * TIM units.
67 */
68#define STM32_TIM1_UP_HANDLER Vector74
69#define STM32_TIM1_CC_HANDLER Vector78
70#define STM32_TIM2_HANDLER Vector7C
71#define STM32_TIM3_HANDLER Vector80
72#define STM32_TIM6_HANDLER Vector84
73#define STM32_TIM7_HANDLER Vector88
74#define STM32_TIM14_HANDLER Vector8C
75#define STM32_TIM15_HANDLER Vector90
76#define STM32_TIM16_HANDLER Vector94
77#define STM32_TIM17_HANDLER Vector98
78
79#define STM32_TIM1_UP_NUMBER 13
80#define STM32_TIM1_CC_NUMBER 14
81#define STM32_TIM2_NUMBER 15
82#define STM32_TIM3_NUMBER 16
83#define STM32_TIM6_NUMBER 17
84#define STM32_TIM7_NUMBER 18
85#define STM32_TIM14_NUMBER 19
86#define STM32_TIM15_NUMBER 20
87#define STM32_TIM16_NUMBER 21
88#define STM32_TIM17_NUMBER 22
89
90/*
91 * USART units.
92 */
93#define STM32_USART1_HANDLER VectorAC
94#define STM32_USART2_HANDLER VectorB0
95#define STM32_USART3_8_HANDLER VectorB4
96
97#define STM32_USART1_NUMBER 27
98#define STM32_USART2_NUMBER 28
99#define STM32_USART3_8_NUMBER 29
100
101/*
102 * USB units.
103 */
104#define STM32_USB1_LP_HANDLER VectorBC
105#define STM32_USB1_LP_NUMBER 31
106#define STM32_USB1_HP_HANDLER VectorBC
107#define STM32_USB1_HP_NUMBER 31
108/** @} */
109
110/*===========================================================================*/
111/* Driver pre-compile time settings. */
112/*===========================================================================*/
113
114/**
115 * @name Configuration options
116 * @{
117 */
118/**
119 * @brief EXTI0..1 interrupt priority level setting.
120 */
121#if !defined(STM32_IRQ_EXTI0_1_PRIORITY) || defined(__DOXYGEN__)
122#define STM32_IRQ_EXTI0_1_PRIORITY 3
123#endif
124
125/**
126 * @brief EXTI2..3 interrupt priority level setting.
127 */
128#if !defined(STM32_IRQ_EXTI2_3_PRIORITY) || defined(__DOXYGEN__)
129#define STM32_IRQ_EXTI2_3_PRIORITY 3
130#endif
131
132/**
133 * @brief EXTI4..15 interrupt priority level setting.
134 */
135#if !defined(STM32_IRQ_EXTI4_15_PRIORITY) || defined(__DOXYGEN__)
136#define STM32_IRQ_EXTI4_15_PRIORITY 3
137#endif
138
139/**
140 * @brief EXTI16 interrupt priority level setting.
141 */
142#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
143#define STM32_IRQ_EXTI16_PRIORITY 3
144#endif
145
146/**
147 * @brief EXTI17,19,20 interrupt priority level setting.
148 */
149#if !defined(STM32_IRQ_EXTI17_20_PRIORITY) || defined(__DOXYGEN__)
150#define STM32_IRQ_EXTI17_20_PRIORITY 3
151#endif
152
153/**
154 * @brief EXTI21,22 interrupt priority level setting.
155 */
156#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
157#define STM32_IRQ_EXTI21_22_PRIORITY 3
158#endif
159
160/**
161 * @brief USART1 interrupt priority level setting.
162 */
163#if !defined(STM32_IRQ_USART1_PRIORITY) || defined(__DOXYGEN__)
164#define STM32_IRQ_USART1_PRIORITY 3
165#endif
166
167/**
168 * @brief USART2 interrupt priority level setting.
169 */
170#if !defined(STM32_IRQ_USART2_PRIORITY) || defined(__DOXYGEN__)
171#define STM32_IRQ_USART2_PRIORITY 3
172#endif
173
174/**
175 * @brief USART3..8 interrupt priority level setting.
176 */
177#if !defined(STM32_IRQ_USART3_8_PRIORITY) || defined(__DOXYGEN__)
178#define STM32_IRQ_USART3_8_PRIORITY 3
179#endif
180/** @} */
181
182/*===========================================================================*/
183/* Derived constants and error checks. */
184/*===========================================================================*/
185
186/* IRQ priority checks.*/
187#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_1_PRIORITY)
188#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_1_PRIORITY"
189#endif
190
191#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_3_PRIORITY)
192#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_3_PRIORITY"
193#endif
194
195#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_15_PRIORITY)
196#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_15_PRIORITY"
197#endif
198
199#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)
200#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"
201#endif
202
203#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_20_PRIORITY)
204#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_20_PRIORITY"
205#endif
206
207#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_PRIORITY)
208#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_PRIORITY"
209#endif
210
211#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART1_PRIORITY)
212#error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY"
213#endif
214
215#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART2_PRIORITY)
216#error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY"
217#endif
218
219#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART3_8_PRIORITY)
220#error "Invalid IRQ priority assigned to STM32_IRQ_USART3_8_PRIORITY"
221#endif
222
223/*===========================================================================*/
224/* Driver data structures and types. */
225/*===========================================================================*/
226
227/*===========================================================================*/
228/* Driver macros. */
229/*===========================================================================*/
230
231/*===========================================================================*/
232/* External declarations. */
233/*===========================================================================*/
234
235#ifdef __cplusplus
236extern "C" {
237#endif
238 void irqInit(void);
239 void irqDeinit(void);
240#ifdef __cplusplus
241}
242#endif
243
244#endif /* STM32_ISR_H */
245
246/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
new file mode 100644
index 000000000..b0ef86d1f
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
@@ -0,0 +1,965 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f0xx.h.
22 *
23 * @addtogroup STM32F0xx_RCC
24 * @{
25 */
26
27#ifndef STM32_RCC_H
28#define STM32_RCC_H
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Derived constants and error checks. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver data structures and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver macros. */
48/*===========================================================================*/
49
50/**
51 * @name Generic RCC operations
52 * @{
53 */
54/**
55 * @brief Enables the clock of one or more peripheral on the APB1 bus.
56 * @note The @p lp parameter is ignored in this family.
57 *
58 * @param[in] mask APB1 peripherals mask
59 * @param[in] lp low power enable flag
60 *
61 * @api
62 */
63#define rccEnableAPB1(mask, lp) { \
64 RCC->APB1ENR |= (mask); \
65 (void)RCC->APB1ENR; \
66}
67
68/**
69 * @brief Disables the clock of one or more peripheral on the APB1 bus.
70 *
71 * @param[in] mask APB1 peripherals mask
72 *
73 * @api
74 */
75#define rccDisableAPB1(mask) { \
76 RCC->APB1ENR &= ~(mask); \
77 (void)RCC->APB1ENR; \
78}
79
80/**
81 * @brief Resets one or more peripheral on the APB1 bus.
82 *
83 * @param[in] mask APB1 peripherals mask
84 *
85 * @api
86 */
87#define rccResetAPB1(mask) { \
88 RCC->APB1RSTR |= (mask); \
89 RCC->APB1RSTR &= ~(mask); \
90 (void)RCC->APB1RSTR; \
91}
92
93/**
94 * @brief Enables the clock of one or more peripheral on the APB2 bus.
95 * @note The @p lp parameter is ignored in this family.
96 *
97 * @param[in] mask APB2 peripherals mask
98 * @param[in] lp low power enable flag
99 *
100 * @api
101 */
102#define rccEnableAPB2(mask, lp) { \
103 RCC->APB2ENR |= (mask); \
104 (void)RCC->APB2ENR; \
105}
106
107/**
108 * @brief Disables the clock of one or more peripheral on the APB2 bus.
109 *
110 * @param[in] mask APB2 peripherals mask
111 *
112 * @api
113 */
114#define rccDisableAPB2(mask) { \
115 RCC->APB2ENR &= ~(mask); \
116 (void)RCC->APB2ENR; \
117}
118
119/**
120 * @brief Resets one or more peripheral on the APB2 bus.
121 *
122 * @param[in] mask APB2 peripherals mask
123 *
124 * @api
125 */
126#define rccResetAPB2(mask) { \
127 RCC->APB2RSTR |= (mask); \
128 RCC->APB2RSTR &= ~(mask); \
129 (void)RCC->APB2RSTR; \
130}
131
132/**
133 * @brief Enables the clock of one or more peripheral on the AHB bus.
134 * @note The @p lp parameter is ignored in this family.
135 *
136 * @param[in] mask AHB peripherals mask
137 * @param[in] lp low power enable flag
138 *
139 * @api
140 */
141#define rccEnableAHB(mask, lp) { \
142 RCC->AHBENR |= (mask); \
143 (void)RCC->AHBENR; \
144}
145
146/**
147 * @brief Disables the clock of one or more peripheral on the AHB bus.
148 *
149 * @param[in] mask AHB peripherals mask
150 *
151 * @api
152 */
153#define rccDisableAHB(mask) { \
154 RCC->AHBENR &= ~(mask); \
155 (void)RCC->AHBENR; \
156}
157
158/**
159 * @brief Resets one or more peripheral on the AHB bus.
160 *
161 * @param[in] mask AHB peripherals mask
162 *
163 * @api
164 */
165#define rccResetAHB(mask) { \
166 RCC->AHBRSTR |= (mask); \
167 RCC->AHBRSTR &= ~(mask); \
168 (void)RCC->AHBRSTR; \
169}
170/** @} */
171
172/**
173 * @name ADC peripherals specific RCC operations
174 * @{
175 */
176/**
177 * @brief Enables the ADC1 peripheral clock.
178 * @note The @p lp parameter is ignored in this family.
179 *
180 * @param[in] lp low power enable flag
181 *
182 * @api
183 */
184#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
185
186/**
187 * @brief Disables the ADC1 peripheral clock.
188 *
189 * @api
190 */
191#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
192
193/**
194 * @brief Resets the ADC1 peripheral.
195 *
196 * @api
197 */
198#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
199/** @} */
200
201/**
202 * @name CAN peripherals specific RCC operations
203 * @{
204 */
205/**
206 * @brief Enables the CAN1 peripheral clock.
207 * @note The @p lp parameter is ignored in this family.
208 *
209 * @param[in] lp low power enable flag
210 *
211 * @api
212 */
213#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
214
215/**
216 * @brief Disables the CAN1 peripheral clock.
217 *
218 * @api
219 */
220#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CANEN)
221
222/**
223 * @brief Resets the CAN1 peripheral.
224 *
225 * @api
226 */
227#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
228/** @} */
229
230/**
231 * @name DAC peripheral specific RCC operations
232 * @{
233 */
234/**
235 * @brief Enables the DAC1 peripheral clock.
236 * @note The @p lp parameter is ignored in this family.
237 *
238 * @param[in] lp low power enable flag
239 *
240 * @api
241 */
242#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
243
244/**
245 * @brief Disables the DAC1 peripheral clock.
246 *
247 * @api
248 */
249#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
250
251/**
252 * @brief Resets the DAC1 peripheral.
253 *
254 * @api
255 */
256#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
257/** @} */
258
259/**
260 * @name PWR interface specific RCC operations
261 * @{
262 */
263/**
264 * @brief Enables the PWR interface clock.
265 * @note The @p lp parameter is ignored in this family.
266 *
267 * @param[in] lp low power enable flag
268 *
269 * @api
270 */
271#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
272
273/**
274 * @brief Disables PWR interface clock.
275 *
276 * @api
277 */
278#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
279
280/**
281 * @brief Resets the PWR interface.
282 *
283 * @api
284 */
285#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
286/** @} */
287
288/**
289 * @name DMA peripherals specific RCC operations
290 * @{
291 */
292/**
293 * @brief Enables the DMA1 peripheral clock.
294 * @note The @p lp parameter is ignored in this family.
295 *
296 * @param[in] lp low power enable flag
297 *
298 * @api
299 */
300#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
301
302/**
303 * @brief Disables the DMA1 peripheral clock.
304 *
305 * @api
306 */
307#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
308
309/**
310 * @brief Resets the DMA1 peripheral.
311 * @note Not supported in this family, does nothing.
312 *
313 * @api
314 */
315#define rccResetDMA1()
316
317/**
318 * @brief Enables the DMA2 peripheral clock.
319 * @note The @p lp parameter is ignored in this family.
320 *
321 * @param[in] lp low power enable flag
322 *
323 * @api
324 */
325#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
326
327/**
328 * @brief Disables the DMA2 peripheral clock.
329 *
330 * @api
331 */
332#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
333
334/**
335 * @brief Resets the DMA2 peripheral.
336 * @note Not supported in this family, does nothing.
337 *
338 * @api
339 */
340#define rccResetDMA2()
341/** @} */
342
343/**
344 * @name I2C peripherals specific RCC operations
345 * @{
346 */
347/**
348 * @brief Enables the I2C1 peripheral clock.
349 * @note The @p lp parameter is ignored in this family.
350 *
351 * @param[in] lp low power enable flag
352 *
353 * @api
354 */
355#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
356
357/**
358 * @brief Disables the I2C1 peripheral clock.
359 *
360 * @api
361 */
362#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
363
364/**
365 * @brief Resets the I2C1 peripheral.
366 *
367 * @api
368 */
369#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
370
371/**
372 * @brief Enables the I2C2 peripheral clock.
373 * @note The @p lp parameter is ignored in this family.
374 *
375 * @param[in] lp low power enable flag
376 *
377 * @api
378 */
379#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
380
381/**
382 * @brief Disables the I2C2 peripheral clock.
383 *
384 * @api
385 */
386#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
387
388/**
389 * @brief Resets the I2C2 peripheral.
390 *
391 * @api
392 */
393#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
394/** @} */
395
396/**
397 * @name SPI peripherals specific RCC operations
398 * @{
399 */
400/**
401 * @brief Enables the SPI1 peripheral clock.
402 * @note The @p lp parameter is ignored in this family.
403 *
404 * @param[in] lp low power enable flag
405 *
406 * @api
407 */
408#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
409
410/**
411 * @brief Disables the SPI1 peripheral clock.
412 *
413 * @api
414 */
415#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
416
417/**
418 * @brief Resets the SPI1 peripheral.
419 *
420 * @api
421 */
422#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
423
424/**
425 * @brief Enables the SPI2 peripheral clock.
426 * @note The @p lp parameter is ignored in this family.
427 *
428 * @param[in] lp low power enable flag
429 *
430 * @api
431 */
432#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
433
434/**
435 * @brief Disables the SPI2 peripheral clock.
436 *
437 * @api
438 */
439#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
440
441/**
442 * @brief Resets the SPI2 peripheral.
443 *
444 * @api
445 */
446#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
447/** @} */
448
449/**
450 * @name TIM peripherals specific RCC operations
451 * @{
452 */
453/**
454 * @brief Enables the TIM1 peripheral clock.
455 * @note The @p lp parameter is ignored in this family.
456 *
457 * @param[in] lp low power enable flag
458 *
459 * @api
460 */
461#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
462
463/**
464 * @brief Disables the TIM1 peripheral clock.
465 *
466 * @api
467 */
468#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
469
470/**
471 * @brief Resets the TIM1 peripheral.
472 *
473 * @api
474 */
475#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
476
477/**
478 * @brief Enables the TIM2 peripheral clock.
479 * @note The @p lp parameter is ignored in this family.
480 *
481 * @param[in] lp low power enable flag
482 *
483 * @api
484 */
485#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
486
487/**
488 * @brief Disables the TIM2 peripheral clock.
489 *
490 * @api
491 */
492#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
493
494/**
495 * @brief Resets the TIM2 peripheral.
496 *
497 * @api
498 */
499#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
500
501/**
502 * @brief Enables the TIM3 peripheral clock.
503 * @note The @p lp parameter is ignored in this family.
504 *
505 * @param[in] lp low power enable flag
506 *
507 * @api
508 */
509#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
510
511/**
512 * @brief Disables the TIM3 peripheral clock.
513 *
514 * @api
515 */
516#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
517
518/**
519 * @brief Resets the TIM3 peripheral.
520 *
521 * @api
522 */
523#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
524
525/**
526 * @brief Enables the TIM6 peripheral clock.
527 * @note The @p lp parameter is ignored in this family.
528 *
529 * @param[in] lp low power enable flag
530 *
531 * @api
532 */
533#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
534
535/**
536 * @brief Disables the TIM6 peripheral clock.
537 *
538 * @api
539 */
540#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
541
542/**
543 * @brief Resets the TIM6 peripheral.
544 *
545 * @api
546 */
547#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
548
549/**
550 * @brief Enables the TIM7 peripheral clock.
551 * @note The @p lp parameter is ignored in this family.
552 *
553 * @param[in] lp low power enable flag
554 *
555 * @api
556 */
557#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
558
559/**
560 * @brief Disables the TIM7 peripheral clock.
561 *
562 * @api
563 */
564#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
565
566/**
567 * @brief Resets the TIM7 peripheral.
568 *
569 * @api
570 */
571#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
572
573/**
574 * @brief Enables the TIM14 peripheral clock.
575 * @note The @p lp parameter is ignored in this family.
576 *
577 * @param[in] lp low power enable flag
578 *
579 * @api
580 */
581#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
582
583/**
584 * @brief Disables the TIM14 peripheral clock.
585 *
586 * @api
587 */
588#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
589
590/**
591 * @brief Resets the TIM14 peripheral.
592 *
593 * @api
594 */
595#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
596
597/**
598 * @brief Enables the TIM15 peripheral clock.
599 * @note The @p lp parameter is ignored in this family.
600 *
601 * @param[in] lp low power enable flag
602 *
603 * @api
604 */
605#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
606
607/**
608 * @brief Disables the TIM15 peripheral clock.
609 *
610 * @api
611 */
612#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
613
614/**
615 * @brief Resets the TIM15 peripheral.
616 *
617 * @api
618 */
619#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
620
621/**
622 * @brief Enables the TIM16 peripheral clock.
623 * @note The @p lp parameter is ignored in this family.
624 *
625 * @param[in] lp low power enable flag
626 *
627 * @api
628 */
629#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
630
631/**
632 * @brief Disables the TIM16 peripheral clock.
633 *
634 * @api
635 */
636#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
637
638/**
639 * @brief Resets the TIM16 peripheral.
640 *
641 * @api
642 */
643#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
644
645/**
646 * @brief Enables the TIM17 peripheral clock.
647 * @note The @p lp parameter is ignored in this family.
648 *
649 * @param[in] lp low power enable flag
650 *
651 * @api
652 */
653#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
654
655/**
656 * @brief Disables the TIM17 peripheral clock.
657 *
658 * @api
659 */
660#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
661
662/**
663 * @brief Resets the TIM17 peripheral.
664 *
665 * @api
666 */
667#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
668/** @} */
669
670/**
671 * @name USART/UART peripherals specific RCC operations
672 * @{
673 */
674/**
675 * @brief Enables the USART1 peripheral clock.
676 * @note The @p lp parameter is ignored in this family.
677 *
678 * @param[in] lp low power enable flag
679 *
680 * @api
681 */
682#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
683
684/**
685 * @brief Disables the USART1 peripheral clock.
686 *
687 * @api
688 */
689#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
690
691/**
692 * @brief Resets the USART1 peripheral.
693 *
694 * @api
695 */
696#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
697
698/**
699 * @brief Enables the USART2 peripheral clock.
700 * @note The @p lp parameter is ignored in this family.
701 *
702 * @param[in] lp low power enable flag
703 *
704 * @api
705 */
706#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
707
708/**
709 * @brief Disables the USART2 peripheral clock.
710 *
711 * @api
712 */
713#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
714
715/**
716 * @brief Resets the USART2 peripheral.
717 *
718 * @api
719 */
720#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
721
722/**
723 * @brief Enables the USART3 peripheral clock.
724 * @note The @p lp parameter is ignored in this family.
725 *
726 * @param[in] lp low power enable flag
727 *
728 * @api
729 */
730#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
731
732/**
733 * @brief Disables the USART3 peripheral clock.
734 *
735 * @api
736 */
737#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
738
739/**
740 * @brief Resets the USART3 peripheral.
741 *
742 * @api
743 */
744#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
745
746/**
747 * @brief Enables the USART4 peripheral clock.
748 * @note The @p lp parameter is ignored in this family.
749 *
750 * @param[in] lp low power enable flag
751 *
752 * @api
753 */
754#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
755
756/**
757 * @brief Disables the USART4 peripheral clock.
758 *
759 * @api
760 */
761#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_USART4EN)
762
763/**
764 * @brief Resets the USART4 peripheral.
765 *
766 * @api
767 */
768#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_USART4RST)
769
770/**
771 * @brief Enables the USART5 peripheral clock.
772 * @note The @p lp parameter is ignored in this family.
773 *
774 * @param[in] lp low power enable flag
775 *
776 * @api
777 */
778#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
779
780/**
781 * @brief Disables the USART5 peripheral clock.
782 *
783 * @api
784 */
785#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_USART5EN)
786
787/**
788 * @brief Resets the USART5 peripheral.
789 *
790 * @api
791 */
792#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_USART5RST)
793
794/**
795 * @brief Enables the USART6 peripheral clock.
796 * @note The @p lp parameter is ignored in this family.
797 *
798 * @param[in] lp low power enable flag
799 *
800 * @api
801 */
802#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
803
804/**
805 * @brief Disables the USART6 peripheral clock.
806 *
807 * @api
808 */
809#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
810
811/**
812 * @brief Resets the USART6 peripheral.
813 *
814 * @api
815 */
816#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
817
818/**
819 * @brief Enables the UART7 peripheral clock.
820 *
821 * @param[in] lp low power enable flag
822 *
823 * @api
824 */
825#define rccEnableUART7(lp) rccEnableAPB2(RCC_APB2ENR_USART7EN, lp)
826
827/**
828 * @brief Disables the UART7 peripheral clock.
829 *
830 * @api
831 */
832#define rccDisableUART7() rccDisableAPB2(RCC_APB2ENR_USART7EN)
833
834/**
835 * @brief Resets the UART7 peripheral.
836 *
837 * @api
838 */
839#define rccResetUART7() rccResetAPB2(RCC_APB2RSTR_USART7RST)
840
841/**
842 * @brief Enables the UART8 peripheral clock.
843 *
844 * @param[in] lp low power enable flag
845 *
846 * @api
847 */
848#define rccEnableUART8(lp) rccEnableAPB2(RCC_APB2ENR_USART8EN, lp)
849
850/**
851 * @brief Disables the UART8 peripheral clock.
852 *
853 * @api
854 */
855#define rccDisableUART8() rccDisableAPB2(RCC_APB2ENR_USART8EN)
856
857/**
858 * @brief Resets the UART8 peripheral.
859 *
860 * @api
861 */
862#define rccResetUART8() rccResetAPB2(RCC_APB2RSTR_USART8RST)
863/** @} */
864
865/**
866 * @name USB peripherals specific RCC operations
867 * @{
868 */
869/**
870 * @brief Enables the USB peripheral clock.
871 * @note The @p lp parameter is ignored in this family.
872 *
873 * @param[in] lp low power enable flag
874 *
875 * @api
876 */
877#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
878
879/**
880 * @brief Disables the USB peripheral clock.
881 *
882 * @api
883 */
884#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
885
886/**
887 * @brief Resets the USB peripheral.
888 *
889 * @api
890 */
891#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
892/** @} */
893
894/**
895 * @name CRC peripherals specific RCC operations
896 * @{
897 */
898/**
899 * @brief Enables the CRC peripheral clock.
900 * @note The @p lp parameter is ignored in this family.
901 *
902 * @param[in] lp low power enable flag
903 *
904 * @api
905 */
906#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
907
908/**
909 * @brief Disables the CRC peripheral clock.
910 *
911 * @api
912 */
913#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
914
915/**
916 * @brief Resets the CRC peripheral.
917 *
918 * @api
919 */
920#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
921/** @} */
922
923/**
924 * @name WWDG peripherals specific RCC operations
925 * @{
926 */
927/**
928 * @brief Enables the WWDG peripheral clock.
929 * @note The @p lp parameter is ignored in this family.
930 *
931 * @param[in] lp low power enable flag
932 *
933 * @api
934 */
935#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
936
937/**
938 * @brief Disables the WWDG peripheral clock.
939 *
940 * @api
941 */
942#define rccDisableWWDG() rccDisableAPB1(RCC_APB1ENR_WWDGEN)
943
944/**
945 * @brief Resets the WWDG peripheral.
946 *
947 * @api
948 */
949#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST)
950/** @} */
951
952/*===========================================================================*/
953/* External declarations. */
954/*===========================================================================*/
955
956#ifdef __cplusplus
957extern "C" {
958#endif
959#ifdef __cplusplus
960}
961#endif
962
963#endif /* STM32_RCC_H */
964
965/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
new file mode 100644
index 000000000..2c97ab4a7
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -0,0 +1,2222 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/stm32_registry.h
19 * @brief STM32F0xx capabilities registry.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef STM32_REGISTRY_H
26#define STM32_REGISTRY_H
27
28#if !defined(STM32F0XX) || defined(__DOXYGEN__)
29#define STM32F0XX
30#endif
31
32/*===========================================================================*/
33/* Platform capabilities. */
34/*===========================================================================*/
35
36/**
37 * @name STM32F0xx capabilities
38 * @{
39 */
40
41/*===========================================================================*/
42/* Common. */
43/*===========================================================================*/
44
45/* RNG attributes.*/
46#define STM32_HAS_RNG1 FALSE
47
48/*===========================================================================*/
49/* STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC. */
50/*===========================================================================*/
51#if defined(STM32F030x4) || defined(STM32F030x6) || \
52 defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
53
54/* Common identifier of all STM32F030 devices.*/
55#define STM32F030
56
57/* RCC attributes. */
58#define STM32_HAS_HSI48 FALSE
59#if defined(STM32F030xC) || defined(__DOXYGEN__)
60#define STM32_HAS_HSI_PREDIV TRUE
61#else
62#define STM32_HAS_HSI_PREDIV FALSE
63#endif
64#define STM32_HAS_MCO_PREDIV TRUE
65
66/* ADC attributes.*/
67#define STM32_HAS_ADC1 TRUE
68#define STM32_ADC_SUPPORTS_PRESCALER FALSE
69#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
70#define STM32_ADC1_HANDLER Vector70
71#define STM32_ADC1_NUMBER 12
72#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
73 STM32_DMA_STREAM_ID_MSK(1, 2))
74#define STM32_ADC1_DMA_CHN 0x00000011
75
76#define STM32_HAS_ADC2 FALSE
77#define STM32_HAS_ADC3 FALSE
78#define STM32_HAS_ADC4 FALSE
79
80/* CAN attributes.*/
81#define STM32_HAS_CAN1 FALSE
82#define STM32_HAS_CAN2 FALSE
83#define STM32_HAS_CAN3 FALSE
84
85/* DAC attributes.*/
86#define STM32_HAS_DAC1_CH1 FALSE
87#define STM32_HAS_DAC1_CH2 FALSE
88#define STM32_HAS_DAC2_CH1 FALSE
89#define STM32_HAS_DAC2_CH2 FALSE
90
91/* DMA attributes.*/
92#define STM32_ADVANCED_DMA TRUE
93#define STM32_DMA_SUPPORTS_DMAMUX FALSE
94#if defined(STM32F030xC) || defined(__DOXYGEN__)
95#define STM32_DMA_SUPPORTS_CSELR TRUE
96#else
97#define STM32_DMA_SUPPORTS_CSELR FALSE
98#endif
99#define STM32_DMA1_NUM_CHANNELS 5
100#define STM32_DMA2_NUM_CHANNELS 0
101#define STM32_DMA1_CH1_HANDLER Vector64
102#define STM32_DMA1_CH23_HANDLER Vector68
103#define STM32_DMA1_CH4567_HANDLER Vector6C
104#define STM32_DMA1_CH1_NUMBER 9
105#define STM32_DMA1_CH23_NUMBER 10
106#define STM32_DMA1_CH4567_NUMBER 11
107
108#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
109#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
110#define STM32_DMA1_CH2_CMASK 0x00000006U
111#define STM32_DMA1_CH3_CMASK 0x00000006U
112
113#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
114#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
115#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
116#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
117#define STM32_DMA1_CH4_CMASK 0x00000078U
118#define STM32_DMA1_CH5_CMASK 0x00000078U
119#define STM32_DMA1_CH6_CMASK 0x00000078U
120#define STM32_DMA1_CH7_CMASK 0x00000078U
121
122/* ETH attributes.*/
123#define STM32_HAS_ETH FALSE
124
125/* EXTI attributes.*/
126#define STM32_EXTI_NUM_LINES 20
127#define STM32_EXTI_IMR1_MASK 0xFFF50000U
128
129/* GPIO attributes.*/
130#define STM32_HAS_GPIOA TRUE
131#define STM32_HAS_GPIOB TRUE
132#if !defined(STM32F030x4) && !defined(STM32F030x6)
133#define STM32_HAS_GPIOC TRUE
134#define STM32_HAS_GPIOD TRUE
135#else
136#define STM32_HAS_GPIOC FALSE
137#define STM32_HAS_GPIOD FALSE
138#endif
139#define STM32_HAS_GPIOE FALSE
140#define STM32_HAS_GPIOF TRUE
141#define STM32_HAS_GPIOG FALSE
142#define STM32_HAS_GPIOH FALSE
143#define STM32_HAS_GPIOI FALSE
144#define STM32_HAS_GPIOJ FALSE
145#define STM32_HAS_GPIOK FALSE
146#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
147 RCC_AHBENR_GPIOBEN | \
148 RCC_AHBENR_GPIOCEN | \
149 RCC_AHBENR_GPIODEN | \
150 RCC_AHBENR_GPIOFEN)
151
152/* I2C attributes.*/
153#define STM32_HAS_I2C1 TRUE
154#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
155#define STM32_I2C1_RX_DMA_CHN 0x00000200
156#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
157#define STM32_I2C1_TX_DMA_CHN 0x00000020
158
159#if defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
160#define STM32_HAS_I2C2 TRUE
161#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
162#define STM32_I2C2_RX_DMA_CHN 0x00020000
163#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
164#define STM32_I2C2_TX_DMA_CHN 0x00002000
165#else
166#define STM32_HAS_I2C2 FALSE
167#endif
168
169#define STM32_HAS_I2C3 FALSE
170#define STM32_HAS_I2C4 FALSE
171
172/* QUADSPI attributes.*/
173#define STM32_HAS_QUADSPI1 FALSE
174
175/* RTC attributes.*/
176#define STM32_HAS_RTC TRUE
177#define STM32_RTC_HAS_SUBSECONDS TRUE
178#if defined (STM32F030xC)
179#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
180#else
181#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
182#endif
183#define STM32_RTC_NUM_ALARMS 1
184#define STM32_RTC_STORAGE_SIZE 0
185#define STM32_RTC_COMMON_HANDLER Vector48
186#define STM32_RTC_COMMON_NUMBER 2
187#define STM32_RTC_ALARM_EXTI 17
188#define STM32_RTC_TAMP_STAMP_EXTI 19
189#define STM32_RTC_WKUP_EXTI 20
190#define STM32_RTC_IRQ_ENABLE() \
191 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
192
193/* SDIO attributes.*/
194#define STM32_HAS_SDIO FALSE
195
196/* SPI attributes.*/
197#define STM32_HAS_SPI1 TRUE
198#define STM32_SPI1_SUPPORTS_I2S FALSE
199#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
200#define STM32_SPI1_RX_DMA_CHN 0x00000030
201#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
202#define STM32_SPI1_TX_DMA_CHN 0x00000300
203
204#if defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
205#define STM32_HAS_SPI2 TRUE
206#define STM32_SPI2_SUPPORTS_I2S FALSE
207#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
208#define STM32_SPI2_RX_DMA_CHN 0x00003000
209#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
210#define STM32_SPI2_TX_DMA_CHN 0x00030000
211#else
212#define STM32_HAS_SPI2 FALSE
213#endif
214
215#define STM32_HAS_SPI3 FALSE
216#define STM32_HAS_SPI4 FALSE
217#define STM32_HAS_SPI5 FALSE
218#define STM32_HAS_SPI6 FALSE
219
220/* TIM attributes.*/
221#define STM32_TIM_MAX_CHANNELS 4
222
223#define STM32_HAS_TIM1 TRUE
224#define STM32_TIM1_IS_32BITS FALSE
225#define STM32_TIM1_CHANNELS 4
226
227#define STM32_HAS_TIM3 TRUE
228#define STM32_TIM3_IS_32BITS FALSE
229#define STM32_TIM3_CHANNELS 4
230
231#if defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
232#define STM32_HAS_TIM6 TRUE
233#define STM32_TIM6_IS_32BITS FALSE
234#define STM32_TIM6_CHANNELS 0
235#else
236#define STM32_HAS_TIM6 FALSE
237#endif
238
239#if defined(STM32F030xC)
240#define STM32_HAS_TIM7 TRUE
241#define STM32_TIM7_IS_32BITS FALSE
242#define STM32_TIM7_CHANNELS 0
243#else
244#define STM32_HAS_TIM7 FALSE
245#endif
246
247#define STM32_HAS_TIM14 TRUE
248#define STM32_TIM14_IS_32BITS FALSE
249#define STM32_TIM14_CHANNELS 1
250
251#if defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
252#define STM32_HAS_TIM15 TRUE
253#define STM32_TIM15_IS_32BITS FALSE
254#define STM32_TIM15_CHANNELS 2
255#else
256#define STM32_HAS_TIM15 FALSE
257#endif
258
259#define STM32_HAS_TIM16 TRUE
260#define STM32_TIM16_IS_32BITS FALSE
261#define STM32_TIM16_CHANNELS 1
262
263#define STM32_HAS_TIM17 TRUE
264#define STM32_TIM17_IS_32BITS FALSE
265#define STM32_TIM17_CHANNELS 1
266
267#define STM32_HAS_TIM2 FALSE
268#define STM32_HAS_TIM4 FALSE
269#define STM32_HAS_TIM5 FALSE
270#define STM32_HAS_TIM8 FALSE
271#define STM32_HAS_TIM9 FALSE
272#define STM32_HAS_TIM10 FALSE
273#define STM32_HAS_TIM11 FALSE
274#define STM32_HAS_TIM12 FALSE
275#define STM32_HAS_TIM13 FALSE
276#define STM32_HAS_TIM18 FALSE
277#define STM32_HAS_TIM19 FALSE
278#define STM32_HAS_TIM20 FALSE
279#define STM32_HAS_TIM21 FALSE
280#define STM32_HAS_TIM22 FALSE
281
282/* USART attributes.*/
283#define STM32_HAS_USART1 TRUE
284#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
285 STM32_DMA_STREAM_ID_MSK(1, 3) |\
286 STM32_DMA_STREAM_ID_MSK(1, 5))
287#define STM32_USART1_RX_DMA_CHN 0x00080808
288#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
289 STM32_DMA_STREAM_ID_MSK(1, 4))
290#define STM32_USART1_TX_DMA_CHN 0x00008080
291
292#if defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
293#define STM32_HAS_USART2 TRUE
294#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
295 STM32_DMA_STREAM_ID_MSK(1, 3) |\
296 STM32_DMA_STREAM_ID_MSK(1, 5))
297#define STM32_USART2_RX_DMA_CHN 0x00090909
298#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
299 STM32_DMA_STREAM_ID_MSK(1, 4))
300#define STM32_USART2_TX_DMA_CHN 0x00009090
301#else
302#define STM32_HAS_USART2 FALSE
303#endif
304
305#if defined(STM32F030xC) || defined(__DOXYGEN__)
306#define STM32_HAS_USART3 TRUE
307#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
308 STM32_DMA_STREAM_ID_MSK(1, 3) |\
309 STM32_DMA_STREAM_ID_MSK(1, 5))
310#define STM32_USART3_RX_DMA_CHN 0x000A0A0A
311#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
312 STM32_DMA_STREAM_ID_MSK(1, 4))
313#define STM32_USART3_TX_DMA_CHN 0x0000A0A0
314
315#define STM32_HAS_UART4 TRUE
316#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
317 STM32_DMA_STREAM_ID_MSK(1, 3) |\
318 STM32_DMA_STREAM_ID_MSK(1, 5))
319#define STM32_UART4_RX_DMA_CHN 0x000B0B0B
320#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
321 STM32_DMA_STREAM_ID_MSK(1, 4))
322#define STM32_UART4_TX_DMA_CHN 0x0000B0B0
323
324#define STM32_HAS_UART5 TRUE
325#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
326 STM32_DMA_STREAM_ID_MSK(1, 3) |\
327 STM32_DMA_STREAM_ID_MSK(1, 5))
328#define STM32_UART5_RX_DMA_CHN 0x000C0C0C
329#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
330 STM32_DMA_STREAM_ID_MSK(1, 4))
331#define STM32_UART5_TX_DMA_CHN 0x0000C0C0
332
333#define STM32_HAS_USART6 TRUE
334#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
335 STM32_DMA_STREAM_ID_MSK(1, 3) |\
336 STM32_DMA_STREAM_ID_MSK(1, 5))
337#define STM32_USART6_RX_DMA_CHN 0x000D0D0D
338#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
339 STM32_DMA_STREAM_ID_MSK(1, 4))
340#define STM32_USART6_TX_DMA_CHN 0x0000D0D0
341
342#define STM32_HAS_UART7 FALSE
343#define STM32_HAS_UART8 FALSE
344#define STM32_HAS_LPUART1 FALSE
345#else
346#define STM32_HAS_USART3 FALSE
347#define STM32_HAS_UART4 FALSE
348#define STM32_HAS_UART5 FALSE
349#define STM32_HAS_USART6 FALSE
350#define STM32_HAS_UART7 FALSE
351#define STM32_HAS_UART8 FALSE
352#define STM32_HAS_LPUART1 FALSE
353#endif
354
355/* USB attributes.*/
356#define STM32_HAS_USB FALSE
357#define STM32_HAS_OTG1 FALSE
358#define STM32_HAS_OTG2 FALSE
359
360/* IWDG attributes.*/
361#define STM32_HAS_IWDG TRUE
362#define STM32_IWDG_IS_WINDOWED TRUE
363
364/* LTDC attributes.*/
365#define STM32_HAS_LTDC FALSE
366
367/* DMA2D attributes.*/
368#define STM32_HAS_DMA2D FALSE
369
370/* FSMC attributes.*/
371#define STM32_HAS_FSMC FALSE
372
373/* CRC attributes.*/
374#define STM32_HAS_CRC TRUE
375#define STM32_CRC_PROGRAMMABLE FALSE
376
377/*===========================================================================*/
378/* STM32F031x6, STM32F038xx. */
379/*===========================================================================*/
380#elif defined(STM32F031x6) || defined(STM32F038xx)
381
382/* RCC attributes. */
383#define STM32_HAS_HSI48 FALSE
384#define STM32_HAS_HSI_PREDIV FALSE
385#define STM32_HAS_MCO_PREDIV TRUE
386
387/* ADC attributes.*/
388#define STM32_HAS_ADC1 TRUE
389#define STM32_ADC_SUPPORTS_PRESCALER FALSE
390#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
391#define STM32_ADC1_HANDLER Vector70
392#define STM32_ADC1_NUMBER 12
393#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
394 STM32_DMA_STREAM_ID_MSK(1, 2))
395#define STM32_ADC1_DMA_CHN 0x00000000
396
397#define STM32_HAS_ADC2 FALSE
398#define STM32_HAS_ADC3 FALSE
399#define STM32_HAS_ADC4 FALSE
400
401/* CAN attributes.*/
402#define STM32_HAS_CAN1 FALSE
403#define STM32_HAS_CAN2 FALSE
404#define STM32_HAS_CAN3 FALSE
405
406/* DAC attributes.*/
407#define STM32_HAS_DAC1_CH1 FALSE
408#define STM32_HAS_DAC1_CH2 FALSE
409#define STM32_HAS_DAC2_CH1 FALSE
410#define STM32_HAS_DAC2_CH2 FALSE
411
412/* DMA attributes.*/
413#define STM32_ADVANCED_DMA TRUE
414#define STM32_DMA_SUPPORTS_DMAMUX FALSE
415#define STM32_DMA_SUPPORTS_CSELR FALSE
416#define STM32_DMA1_NUM_CHANNELS 5
417#define STM32_DMA2_NUM_CHANNELS 0
418#define STM32_DMA1_CH1_HANDLER Vector64
419#define STM32_DMA1_CH23_HANDLER Vector68
420#define STM32_DMA1_CH4567_HANDLER Vector6C
421#define STM32_DMA1_CH1_NUMBER 9
422#define STM32_DMA1_CH23_NUMBER 10
423#define STM32_DMA1_CH4567_NUMBER 11
424
425#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
426#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
427#define STM32_DMA1_CH2_CMASK 0x00000006U
428#define STM32_DMA1_CH3_CMASK 0x00000006U
429
430#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
431#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
432#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
433#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
434#define STM32_DMA1_CH4_CMASK 0x00000078U
435#define STM32_DMA1_CH5_CMASK 0x00000078U
436#define STM32_DMA1_CH6_CMASK 0x00000078U
437#define STM32_DMA1_CH7_CMASK 0x00000078U
438
439/* ETH attributes.*/
440#define STM32_HAS_ETH FALSE
441
442/* EXTI attributes.*/
443#define STM32_EXTI_NUM_LINES 32
444#define STM32_EXTI_IMR1_MASK 0x0FF40000U
445
446/* GPIO attributes.*/
447#define STM32_HAS_GPIOA TRUE
448#define STM32_HAS_GPIOB TRUE
449#define STM32_HAS_GPIOC TRUE
450#define STM32_HAS_GPIOD FALSE
451#define STM32_HAS_GPIOE FALSE
452#define STM32_HAS_GPIOF TRUE
453#define STM32_HAS_GPIOG FALSE
454#define STM32_HAS_GPIOH FALSE
455#define STM32_HAS_GPIOI FALSE
456#define STM32_HAS_GPIOJ FALSE
457#define STM32_HAS_GPIOK FALSE
458#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
459 RCC_AHBENR_GPIOBEN | \
460 RCC_AHBENR_GPIOCEN | \
461 RCC_AHBENR_GPIOFEN)
462
463/* I2C attributes.*/
464#define STM32_HAS_I2C1 TRUE
465#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
466#define STM32_I2C1_RX_DMA_CHN 0x00000000
467#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
468#define STM32_I2C1_TX_DMA_CHN 0x00000000
469
470#define STM32_HAS_I2C2 FALSE
471#define STM32_HAS_I2C3 FALSE
472#define STM32_HAS_I2C4 FALSE
473
474/* QUADSPI attributes.*/
475#define STM32_HAS_QUADSPI1 FALSE
476
477/* RTC attributes.*/
478#define STM32_HAS_RTC TRUE
479#define STM32_RTC_HAS_SUBSECONDS TRUE
480#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
481#define STM32_RTC_NUM_ALARMS 1
482#define STM32_RTC_STORAGE_SIZE 0
483#define STM32_RTC_COMMON_HANDLER Vector48
484#define STM32_RTC_COMMON_NUMBER 2
485#define STM32_RTC_ALARM_EXTI 17
486#define STM32_RTC_TAMP_STAMP_EXTI 19
487#define STM32_RTC_WKUP_EXTI 20
488#define STM32_RTC_IRQ_ENABLE() \
489 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
490
491/* SDIO attributes.*/
492#define STM32_HAS_SDIO FALSE
493
494/* SPI attributes.*/
495#define STM32_HAS_SPI1 TRUE
496#define STM32_SPI1_SUPPORTS_I2S TRUE
497#define STM32_SPI1_I2S_FULLDUPLEX FALSE
498#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
499#define STM32_SPI1_RX_DMA_CHN 0x00000000
500#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
501#define STM32_SPI1_TX_DMA_CHN 0x00000000
502
503#define STM32_HAS_SPI2 FALSE
504#define STM32_HAS_SPI3 FALSE
505#define STM32_HAS_SPI4 FALSE
506#define STM32_HAS_SPI5 FALSE
507#define STM32_HAS_SPI6 FALSE
508
509/* TIM attributes.*/
510#define STM32_TIM_MAX_CHANNELS 4
511
512#define STM32_HAS_TIM1 TRUE
513#define STM32_TIM1_IS_32BITS FALSE
514#define STM32_TIM1_CHANNELS 4
515
516#define STM32_HAS_TIM2 TRUE
517#define STM32_TIM2_IS_32BITS TRUE
518#define STM32_TIM2_CHANNELS 4
519
520#define STM32_HAS_TIM3 TRUE
521#define STM32_TIM3_IS_32BITS FALSE
522#define STM32_TIM3_CHANNELS 4
523
524#define STM32_HAS_TIM14 TRUE
525#define STM32_TIM14_IS_32BITS FALSE
526#define STM32_TIM14_CHANNELS 1
527
528#define STM32_HAS_TIM16 TRUE
529#define STM32_TIM16_IS_32BITS FALSE
530#define STM32_TIM16_CHANNELS 1
531
532#define STM32_HAS_TIM17 TRUE
533#define STM32_TIM17_IS_32BITS FALSE
534#define STM32_TIM17_CHANNELS 1
535
536#define STM32_HAS_TIM4 FALSE
537#define STM32_HAS_TIM5 FALSE
538#define STM32_HAS_TIM6 FALSE
539#define STM32_HAS_TIM7 FALSE
540#define STM32_HAS_TIM8 FALSE
541#define STM32_HAS_TIM9 FALSE
542#define STM32_HAS_TIM10 FALSE
543#define STM32_HAS_TIM11 FALSE
544#define STM32_HAS_TIM12 FALSE
545#define STM32_HAS_TIM13 FALSE
546#define STM32_HAS_TIM15 FALSE
547#define STM32_HAS_TIM18 FALSE
548#define STM32_HAS_TIM19 FALSE
549#define STM32_HAS_TIM20 FALSE
550#define STM32_HAS_TIM21 FALSE
551#define STM32_HAS_TIM22 FALSE
552
553/* USART attributes.*/
554#define STM32_HAS_USART1 TRUE
555#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
556 STM32_DMA_STREAM_ID_MSK(1, 5))
557#define STM32_USART1_RX_DMA_CHN 0x00000000
558#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
559 STM32_DMA_STREAM_ID_MSK(1, 4))
560#define STM32_USART1_TX_DMA_CHN 0x00000000
561
562#define STM32_HAS_USART2 FALSE
563#define STM32_HAS_USART3 FALSE
564#define STM32_HAS_UART4 FALSE
565#define STM32_HAS_UART5 FALSE
566#define STM32_HAS_USART6 FALSE
567#define STM32_HAS_UART7 FALSE
568#define STM32_HAS_UART8 FALSE
569#define STM32_HAS_LPUART1 FALSE
570
571/* USB attributes.*/
572#define STM32_HAS_USB FALSE
573#define STM32_HAS_OTG1 FALSE
574#define STM32_HAS_OTG2 FALSE
575
576/* IWDG attributes.*/
577#define STM32_HAS_IWDG TRUE
578#define STM32_IWDG_IS_WINDOWED TRUE
579
580/* LTDC attributes.*/
581#define STM32_HAS_LTDC FALSE
582
583/* DMA2D attributes.*/
584#define STM32_HAS_DMA2D FALSE
585
586/* FSMC attributes.*/
587#define STM32_HAS_FSMC FALSE
588
589/* CRC attributes.*/
590#define STM32_HAS_CRC TRUE
591#define STM32_CRC_PROGRAMMABLE TRUE
592
593/*===========================================================================*/
594/* STM32F042x6. */
595/*===========================================================================*/
596#elif defined(STM32F042x6)
597
598/* RCC attributes. */
599#define STM32_HAS_HSI48 TRUE
600#define STM32_HAS_HSI_PREDIV TRUE
601#define STM32_HAS_MCO_PREDIV TRUE
602
603/* ADC attributes.*/
604#define STM32_HAS_ADC1 TRUE
605#define STM32_ADC_SUPPORTS_PRESCALER FALSE
606#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
607#define STM32_ADC1_HANDLER Vector70
608#define STM32_ADC1_NUMBER 12
609#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
610 STM32_DMA_STREAM_ID_MSK(1, 2))
611#define STM32_ADC1_DMA_CHN 0x00000000
612
613#define STM32_HAS_ADC2 FALSE
614#define STM32_HAS_ADC3 FALSE
615#define STM32_HAS_ADC4 FALSE
616
617/* CAN attributes.*/
618#define STM32_HAS_CAN1 TRUE
619#define STM32_HAS_CAN2 FALSE
620#define STM32_HAS_CAN3 FALSE
621#define STM32_CAN_MAX_FILTERS 14
622
623/* DAC attributes.*/
624#define STM32_HAS_DAC1_CH1 FALSE
625#define STM32_HAS_DAC1_CH2 FALSE
626#define STM32_HAS_DAC2_CH1 FALSE
627#define STM32_HAS_DAC2_CH2 FALSE
628
629/* DMA attributes.*/
630#define STM32_ADVANCED_DMA TRUE
631#define STM32_DMA_SUPPORTS_DMAMUX FALSE
632#define STM32_DMA_SUPPORTS_CSELR FALSE
633#define STM32_DMA1_NUM_CHANNELS 5
634#define STM32_DMA2_NUM_CHANNELS 0
635#define STM32_DMA1_CH1_HANDLER Vector64
636#define STM32_DMA1_CH23_HANDLER Vector68
637#define STM32_DMA1_CH4567_HANDLER Vector6C
638#define STM32_DMA1_CH1_NUMBER 9
639#define STM32_DMA1_CH23_NUMBER 10
640#define STM32_DMA1_CH4567_NUMBER 11
641
642#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
643#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
644#define STM32_DMA1_CH2_CMASK 0x00000006U
645#define STM32_DMA1_CH3_CMASK 0x00000006U
646
647#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
648#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
649#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
650#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
651#define STM32_DMA1_CH4_CMASK 0x00000078U
652#define STM32_DMA1_CH5_CMASK 0x00000078U
653#define STM32_DMA1_CH6_CMASK 0x00000078U
654#define STM32_DMA1_CH7_CMASK 0x00000078U
655
656/* ETH attributes.*/
657#define STM32_HAS_ETH FALSE
658
659/* EXTI attributes.*/
660#define STM32_EXTI_NUM_LINES 32
661#define STM32_EXTI_IMR1_MASK 0x7FF40000U
662
663/* GPIO attributes.*/
664#define STM32_HAS_GPIOA TRUE
665#define STM32_HAS_GPIOB TRUE
666#define STM32_HAS_GPIOC TRUE
667#define STM32_HAS_GPIOD FALSE
668#define STM32_HAS_GPIOE FALSE
669#define STM32_HAS_GPIOF TRUE
670#define STM32_HAS_GPIOG FALSE
671#define STM32_HAS_GPIOH FALSE
672#define STM32_HAS_GPIOI FALSE
673#define STM32_HAS_GPIOJ FALSE
674#define STM32_HAS_GPIOK FALSE
675#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
676 RCC_AHBENR_GPIOBEN | \
677 RCC_AHBENR_GPIOCEN | \
678 RCC_AHBENR_GPIOFEN)
679
680/* I2C attributes.*/
681#define STM32_HAS_I2C1 TRUE
682#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
683#define STM32_I2C1_RX_DMA_CHN 0x00000000
684#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
685#define STM32_I2C1_TX_DMA_CHN 0x00000000
686
687#define STM32_HAS_I2C2 FALSE
688#define STM32_HAS_I2C3 FALSE
689#define STM32_HAS_I2C4 FALSE
690
691/* QUADSPI attributes.*/
692#define STM32_HAS_QUADSPI1 FALSE
693
694/* RTC attributes.*/
695#define STM32_HAS_RTC TRUE
696#define STM32_RTC_HAS_SUBSECONDS TRUE
697#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
698#define STM32_RTC_NUM_ALARMS 1
699#define STM32_RTC_STORAGE_SIZE 0
700#define STM32_RTC_COMMON_HANDLER Vector48
701#define STM32_RTC_COMMON_NUMBER 2
702#define STM32_RTC_ALARM_EXTI 17
703#define STM32_RTC_TAMP_STAMP_EXTI 19
704#define STM32_RTC_WKUP_EXTI 20
705#define STM32_RTC_IRQ_ENABLE() \
706 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
707
708/* SDIO attributes.*/
709#define STM32_HAS_SDIO FALSE
710
711/* SPI attributes.*/
712#define STM32_HAS_SPI1 TRUE
713#define STM32_SPI1_SUPPORTS_I2S TRUE
714#define STM32_SPI1_I2S_FULLDUPLEX FALSE
715#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
716#define STM32_SPI1_RX_DMA_CHN 0x00000000
717#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
718#define STM32_SPI1_TX_DMA_CHN 0x00000000
719
720#define STM32_HAS_SPI2 FALSE
721#define STM32_HAS_SPI3 FALSE
722#define STM32_HAS_SPI4 FALSE
723#define STM32_HAS_SPI5 FALSE
724#define STM32_HAS_SPI6 FALSE
725
726/* TIM attributes.*/
727#define STM32_TIM_MAX_CHANNELS 4
728
729#define STM32_HAS_TIM1 TRUE
730#define STM32_TIM1_IS_32BITS FALSE
731#define STM32_TIM1_CHANNELS 4
732
733#define STM32_HAS_TIM2 TRUE
734#define STM32_TIM2_IS_32BITS TRUE
735#define STM32_TIM2_CHANNELS 4
736
737#define STM32_HAS_TIM3 TRUE
738#define STM32_TIM3_IS_32BITS FALSE
739#define STM32_TIM3_CHANNELS 4
740
741#define STM32_HAS_TIM14 TRUE
742#define STM32_TIM14_IS_32BITS FALSE
743#define STM32_TIM14_CHANNELS 1
744
745#define STM32_HAS_TIM16 TRUE
746#define STM32_TIM16_IS_32BITS FALSE
747#define STM32_TIM16_CHANNELS 1
748
749#define STM32_HAS_TIM17 TRUE
750#define STM32_TIM17_IS_32BITS FALSE
751#define STM32_TIM17_CHANNELS 1
752
753#define STM32_HAS_TIM4 FALSE
754#define STM32_HAS_TIM5 FALSE
755#define STM32_HAS_TIM6 FALSE
756#define STM32_HAS_TIM7 FALSE
757#define STM32_HAS_TIM8 FALSE
758#define STM32_HAS_TIM9 FALSE
759#define STM32_HAS_TIM10 FALSE
760#define STM32_HAS_TIM11 FALSE
761#define STM32_HAS_TIM12 FALSE
762#define STM32_HAS_TIM13 FALSE
763#define STM32_HAS_TIM15 FALSE
764#define STM32_HAS_TIM18 FALSE
765#define STM32_HAS_TIM19 FALSE
766#define STM32_HAS_TIM20 FALSE
767#define STM32_HAS_TIM21 FALSE
768#define STM32_HAS_TIM22 FALSE
769
770/* USART attributes.*/
771#define STM32_HAS_USART1 TRUE
772#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
773 STM32_DMA_STREAM_ID_MSK(1, 5))
774#define STM32_USART1_RX_DMA_CHN 0x00000000
775#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
776 STM32_DMA_STREAM_ID_MSK(1, 4))
777#define STM32_USART1_TX_DMA_CHN 0x00000000
778
779#define STM32_HAS_USART2 TRUE
780#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
781#define STM32_USART2_RX_DMA_CHN 0x00000000
782#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
783#define STM32_USART2_TX_DMA_CHN 0x00000000
784
785#define STM32_HAS_USART3 FALSE
786#define STM32_HAS_UART4 FALSE
787#define STM32_HAS_UART5 FALSE
788#define STM32_HAS_USART6 FALSE
789#define STM32_HAS_UART7 FALSE
790#define STM32_HAS_UART8 FALSE
791#define STM32_HAS_LPUART1 FALSE
792
793/* USB attributes.*/
794#define STM32_HAS_USB TRUE
795#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
796#define STM32_USB_PMA_SIZE 768
797#define STM32_USB_HAS_BCDR TRUE
798
799#define STM32_HAS_OTG1 FALSE
800#define STM32_HAS_OTG2 FALSE
801
802/* IWDG attributes.*/
803#define STM32_HAS_IWDG TRUE
804#define STM32_IWDG_IS_WINDOWED TRUE
805
806/* LTDC attributes.*/
807#define STM32_HAS_LTDC FALSE
808
809/* DMA2D attributes.*/
810#define STM32_HAS_DMA2D FALSE
811
812/* FSMC attributes.*/
813#define STM32_HAS_FSMC FALSE
814
815/* CRC attributes.*/
816#define STM32_HAS_CRC TRUE
817#define STM32_CRC_PROGRAMMABLE TRUE
818
819/*===========================================================================*/
820/* STM32F048xx. */
821/*===========================================================================*/
822#elif defined(STM32F048xx)
823
824/* RCC attributes. */
825#define STM32_HAS_HSI48 TRUE
826#define STM32_HAS_HSI_PREDIV TRUE
827#define STM32_HAS_MCO_PREDIV TRUE
828
829/* ADC attributes.*/
830#define STM32_HAS_ADC1 TRUE
831#define STM32_ADC_SUPPORTS_PRESCALER FALSE
832#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
833#define STM32_ADC1_HANDLER Vector70
834#define STM32_ADC1_NUMBER 12
835#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
836 STM32_DMA_STREAM_ID_MSK(1, 2))
837#define STM32_ADC1_DMA_CHN 0x00000000
838
839#define STM32_HAS_ADC2 FALSE
840#define STM32_HAS_ADC3 FALSE
841#define STM32_HAS_ADC4 FALSE
842
843/* CAN attributes.*/
844#define STM32_HAS_CAN1 FALSE
845#define STM32_HAS_CAN2 FALSE
846#define STM32_HAS_CAN3 FALSE
847
848/* DAC attributes.*/
849#define STM32_HAS_DAC1_CH1 FALSE
850#define STM32_HAS_DAC1_CH2 FALSE
851#define STM32_HAS_DAC2_CH1 FALSE
852#define STM32_HAS_DAC2_CH2 FALSE
853
854/* DMA attributes.*/
855#define STM32_ADVANCED_DMA TRUE
856#define STM32_DMA_SUPPORTS_DMAMUX FALSE
857#define STM32_DMA_SUPPORTS_CSELR FALSE
858#define STM32_DMA1_NUM_CHANNELS 5
859#define STM32_DMA2_NUM_CHANNELS 0
860#define STM32_DMA1_CH1_HANDLER Vector64
861#define STM32_DMA1_CH23_HANDLER Vector68
862#define STM32_DMA1_CH4567_HANDLER Vector6C
863#define STM32_DMA1_CH1_NUMBER 9
864#define STM32_DMA1_CH23_NUMBER 10
865#define STM32_DMA1_CH4567_NUMBER 11
866
867#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
868#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
869#define STM32_DMA1_CH2_CMASK 0x00000006U
870#define STM32_DMA1_CH3_CMASK 0x00000006U
871
872#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
873#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
874#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
875#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
876#define STM32_DMA1_CH4_CMASK 0x00000078U
877#define STM32_DMA1_CH5_CMASK 0x00000078U
878#define STM32_DMA1_CH6_CMASK 0x00000078U
879#define STM32_DMA1_CH7_CMASK 0x00000078U
880
881/* ETH attributes.*/
882#define STM32_HAS_ETH FALSE
883
884/* EXTI attributes.*/
885#define STM32_EXTI_NUM_LINES 32
886#define STM32_EXTI_IMR1_MASK 0x7FF40000U
887
888/* GPIO attributes.*/
889#define STM32_HAS_GPIOA TRUE
890#define STM32_HAS_GPIOB TRUE
891#define STM32_HAS_GPIOC TRUE
892#define STM32_HAS_GPIOD FALSE
893#define STM32_HAS_GPIOE FALSE
894#define STM32_HAS_GPIOF TRUE
895#define STM32_HAS_GPIOG FALSE
896#define STM32_HAS_GPIOH FALSE
897#define STM32_HAS_GPIOI FALSE
898#define STM32_HAS_GPIOJ FALSE
899#define STM32_HAS_GPIOK FALSE
900#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
901 RCC_AHBENR_GPIOBEN | \
902 RCC_AHBENR_GPIOCEN | \
903 RCC_AHBENR_GPIOFEN)
904
905/* I2C attributes.*/
906#define STM32_HAS_I2C1 TRUE
907#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
908#define STM32_I2C1_RX_DMA_CHN 0x00000000
909#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
910#define STM32_I2C1_TX_DMA_CHN 0x00000000
911
912#define STM32_HAS_I2C2 FALSE
913#define STM32_HAS_I2C3 FALSE
914#define STM32_HAS_I2C4 FALSE
915
916/* QUADSPI attributes.*/
917#define STM32_HAS_QUADSPI1 FALSE
918
919/* RTC attributes.*/
920#define STM32_HAS_RTC TRUE
921#define STM32_RTC_HAS_SUBSECONDS TRUE
922#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
923#define STM32_RTC_NUM_ALARMS 1
924#define STM32_RTC_STORAGE_SIZE 0
925#define STM32_RTC_COMMON_HANDLER Vector48
926#define STM32_RTC_COMMON_NUMBER 2
927#define STM32_RTC_ALARM_EXTI 17
928#define STM32_RTC_TAMP_STAMP_EXTI 19
929#define STM32_RTC_WKUP_EXTI 20
930#define STM32_RTC_IRQ_ENABLE() \
931 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
932
933/* SDIO attributes.*/
934#define STM32_HAS_SDIO FALSE
935
936/* SPI attributes.*/
937#define STM32_HAS_SPI1 TRUE
938#define STM32_SPI1_SUPPORTS_I2S TRUE
939#define STM32_SPI1_I2S_FULLDUPLEX FALSE
940#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
941#define STM32_SPI1_RX_DMA_CHN 0x00000000
942#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
943#define STM32_SPI1_TX_DMA_CHN 0x00000000
944
945#define STM32_HAS_SPI2 TRUE
946#define STM32_SPI2_SUPPORTS_I2S FALSE
947#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
948#define STM32_SPI2_RX_DMA_CHN 0x00000000
949#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
950#define STM32_SPI2_TX_DMA_CHN 0x00000000
951
952#define STM32_HAS_SPI3 FALSE
953#define STM32_HAS_SPI4 FALSE
954#define STM32_HAS_SPI5 FALSE
955#define STM32_HAS_SPI6 FALSE
956
957/* TIM attributes.*/
958#define STM32_TIM_MAX_CHANNELS 4
959
960#define STM32_HAS_TIM1 TRUE
961#define STM32_TIM1_IS_32BITS FALSE
962#define STM32_TIM1_CHANNELS 4
963
964#define STM32_HAS_TIM2 TRUE
965#define STM32_TIM2_IS_32BITS TRUE
966#define STM32_TIM2_CHANNELS 4
967
968#define STM32_HAS_TIM3 TRUE
969#define STM32_TIM3_IS_32BITS FALSE
970#define STM32_TIM3_CHANNELS 4
971
972#define STM32_HAS_TIM14 TRUE
973#define STM32_TIM14_IS_32BITS FALSE
974#define STM32_TIM14_CHANNELS 1
975
976#define STM32_HAS_TIM16 TRUE
977#define STM32_TIM16_IS_32BITS FALSE
978#define STM32_TIM16_CHANNELS 1
979
980#define STM32_HAS_TIM17 TRUE
981#define STM32_TIM17_IS_32BITS FALSE
982#define STM32_TIM17_CHANNELS 1
983
984#define STM32_HAS_TIM4 FALSE
985#define STM32_HAS_TIM5 FALSE
986#define STM32_HAS_TIM6 FALSE
987#define STM32_HAS_TIM7 FALSE
988#define STM32_HAS_TIM8 FALSE
989#define STM32_HAS_TIM9 FALSE
990#define STM32_HAS_TIM10 FALSE
991#define STM32_HAS_TIM11 FALSE
992#define STM32_HAS_TIM12 FALSE
993#define STM32_HAS_TIM13 FALSE
994#define STM32_HAS_TIM15 FALSE
995#define STM32_HAS_TIM18 FALSE
996#define STM32_HAS_TIM19 FALSE
997#define STM32_HAS_TIM20 FALSE
998#define STM32_HAS_TIM21 FALSE
999#define STM32_HAS_TIM22 FALSE
1000
1001/* USART attributes.*/
1002#define STM32_HAS_USART1 TRUE
1003#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1004 STM32_DMA_STREAM_ID_MSK(1, 5))
1005#define STM32_USART1_RX_DMA_CHN 0x00000000
1006#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1007 STM32_DMA_STREAM_ID_MSK(1, 4))
1008#define STM32_USART1_TX_DMA_CHN 0x00000000
1009
1010#define STM32_HAS_USART2 TRUE
1011#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1012#define STM32_USART2_RX_DMA_CHN 0x00000000
1013#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1014#define STM32_USART2_TX_DMA_CHN 0x00000000
1015
1016#define STM32_HAS_USART3 FALSE
1017#define STM32_HAS_UART4 FALSE
1018#define STM32_HAS_UART5 FALSE
1019#define STM32_HAS_USART6 FALSE
1020#define STM32_HAS_UART7 FALSE
1021#define STM32_HAS_UART8 FALSE
1022#define STM32_HAS_LPUART1 FALSE
1023
1024/* USB attributes.*/
1025#define STM32_HAS_USB TRUE
1026#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
1027#define STM32_USB_PMA_SIZE 768
1028#define STM32_USB_HAS_BCDR TRUE
1029#define STM32_HAS_OTG1 FALSE
1030#define STM32_HAS_OTG2 FALSE
1031
1032/* IWDG attributes.*/
1033#define STM32_HAS_IWDG TRUE
1034#define STM32_IWDG_IS_WINDOWED TRUE
1035
1036/* LTDC attributes.*/
1037#define STM32_HAS_LTDC FALSE
1038
1039/* DMA2D attributes.*/
1040#define STM32_HAS_DMA2D FALSE
1041
1042/* FSMC attributes.*/
1043#define STM32_HAS_FSMC FALSE
1044
1045/* CRC attributes.*/
1046#define STM32_HAS_CRC TRUE
1047#define STM32_CRC_PROGRAMMABLE TRUE
1048
1049/*===========================================================================*/
1050/* STM32F051x8, STM32F058xx. */
1051/*===========================================================================*/
1052#elif defined(STM32F051x8) || defined(STM32F058xx)
1053
1054/* RCC attributes. */
1055#define STM32_HAS_HSI48 FALSE
1056#define STM32_HAS_HSI_PREDIV FALSE
1057#define STM32_HAS_MCO_PREDIV FALSE
1058
1059/* ADC attributes.*/
1060#define STM32_HAS_ADC1 TRUE
1061#define STM32_ADC_SUPPORTS_PRESCALER FALSE
1062#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
1063#define STM32_ADC1_HANDLER Vector70
1064#define STM32_ADC1_NUMBER 12
1065#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
1066 STM32_DMA_STREAM_ID_MSK(1, 2))
1067#define STM32_ADC1_DMA_CHN 0x00000000
1068
1069#define STM32_HAS_ADC2 FALSE
1070#define STM32_HAS_ADC3 FALSE
1071#define STM32_HAS_ADC4 FALSE
1072
1073/* CAN attributes.*/
1074#define STM32_HAS_CAN1 FALSE
1075#define STM32_HAS_CAN2 FALSE
1076#define STM32_HAS_CAN3 FALSE
1077
1078/* DAC attributes.*/
1079#define STM32_HAS_DAC1_CH1 TRUE
1080#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1081#define STM32_DAC1_CH1_DMA_CHN 0x00000000
1082
1083#define STM32_HAS_DAC1_CH2 FALSE
1084#define STM32_HAS_DAC2_CH1 FALSE
1085#define STM32_HAS_DAC2_CH2 FALSE
1086
1087/* DMA attributes.*/
1088#define STM32_ADVANCED_DMA TRUE
1089#define STM32_DMA_SUPPORTS_DMAMUX FALSE
1090#define STM32_DMA_SUPPORTS_CSELR FALSE
1091#define STM32_DMA1_NUM_CHANNELS 5
1092#define STM32_DMA2_NUM_CHANNELS 0
1093
1094#define STM32_DMA1_CH1_HANDLER Vector64
1095#define STM32_DMA1_CH23_HANDLER Vector68
1096#define STM32_DMA1_CH4567_HANDLER Vector6C
1097#define STM32_DMA1_CH1_NUMBER 9
1098#define STM32_DMA1_CH23_NUMBER 10
1099#define STM32_DMA1_CH4567_NUMBER 11
1100
1101#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
1102#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
1103#define STM32_DMA1_CH2_CMASK 0x00000006U
1104#define STM32_DMA1_CH3_CMASK 0x00000006U
1105
1106#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
1107#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
1108#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
1109#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
1110#define STM32_DMA1_CH4_CMASK 0x00000078U
1111#define STM32_DMA1_CH5_CMASK 0x00000078U
1112#define STM32_DMA1_CH6_CMASK 0x00000078U
1113#define STM32_DMA1_CH7_CMASK 0x00000078U
1114
1115/* ETH attributes.*/
1116#define STM32_HAS_ETH FALSE
1117
1118/* EXTI attributes.*/
1119#define STM32_EXTI_NUM_LINES 32
1120#define STM32_EXTI_IMR1_MASK 0x0F940000U
1121
1122/* GPIO attributes.*/
1123#define STM32_HAS_GPIOA TRUE
1124#define STM32_HAS_GPIOB TRUE
1125#define STM32_HAS_GPIOC TRUE
1126#define STM32_HAS_GPIOD TRUE
1127#define STM32_HAS_GPIOE FALSE
1128#define STM32_HAS_GPIOF TRUE
1129#define STM32_HAS_GPIOG FALSE
1130#define STM32_HAS_GPIOH FALSE
1131#define STM32_HAS_GPIOI FALSE
1132#define STM32_HAS_GPIOJ FALSE
1133#define STM32_HAS_GPIOK FALSE
1134#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
1135 RCC_AHBENR_GPIOBEN | \
1136 RCC_AHBENR_GPIOCEN | \
1137 RCC_AHBENR_GPIODEN | \
1138 RCC_AHBENR_GPIOFEN)
1139
1140/* I2C attributes.*/
1141#define STM32_HAS_I2C1 TRUE
1142#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1143#define STM32_I2C1_RX_DMA_CHN 0x00000000
1144#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1145#define STM32_I2C1_TX_DMA_CHN 0x00000000
1146
1147#define STM32_HAS_I2C2 TRUE
1148#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1149#define STM32_I2C2_RX_DMA_CHN 0x00000000
1150#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1151#define STM32_I2C2_TX_DMA_CHN 0x00000000
1152
1153#define STM32_HAS_I2C3 FALSE
1154#define STM32_HAS_I2C4 FALSE
1155
1156/* QUADSPI attributes.*/
1157#define STM32_HAS_QUADSPI1 FALSE
1158
1159/* RTC attributes.*/
1160#define STM32_HAS_RTC TRUE
1161#define STM32_RTC_HAS_SUBSECONDS TRUE
1162#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
1163#define STM32_RTC_NUM_ALARMS 1
1164#define STM32_RTC_STORAGE_SIZE 0
1165#define STM32_RTC_COMMON_HANDLER Vector48
1166#define STM32_RTC_COMMON_NUMBER 2
1167#define STM32_RTC_ALARM_EXTI 17
1168#define STM32_RTC_TAMP_STAMP_EXTI 19
1169#define STM32_RTC_WKUP_EXTI 20
1170#define STM32_RTC_IRQ_ENABLE() \
1171 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
1172
1173/* SDIO attributes.*/
1174#define STM32_HAS_SDIO FALSE
1175
1176/* SPI attributes.*/
1177#define STM32_HAS_SPI1 TRUE
1178#define STM32_SPI1_SUPPORTS_I2S TRUE
1179#define STM32_SPI1_I2S_FULLDUPLEX FALSE
1180#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1181#define STM32_SPI1_RX_DMA_CHN 0x00000000
1182#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1183#define STM32_SPI1_TX_DMA_CHN 0x00000000
1184
1185#define STM32_HAS_SPI2 TRUE
1186#define STM32_SPI2_SUPPORTS_I2S FALSE
1187#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1188#define STM32_SPI2_RX_DMA_CHN 0x00000000
1189#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1190#define STM32_SPI2_TX_DMA_CHN 0x00000000
1191
1192#define STM32_HAS_SPI3 FALSE
1193#define STM32_HAS_SPI4 FALSE
1194#define STM32_HAS_SPI5 FALSE
1195#define STM32_HAS_SPI6 FALSE
1196
1197/* TIM attributes.*/
1198#define STM32_TIM_MAX_CHANNELS 4
1199
1200#define STM32_HAS_TIM1 TRUE
1201#define STM32_TIM1_IS_32BITS FALSE
1202#define STM32_TIM1_CHANNELS 4
1203
1204#define STM32_HAS_TIM2 TRUE
1205#define STM32_TIM2_IS_32BITS TRUE
1206#define STM32_TIM2_CHANNELS 4
1207
1208#define STM32_HAS_TIM3 TRUE
1209#define STM32_TIM3_IS_32BITS FALSE
1210#define STM32_TIM3_CHANNELS 4
1211
1212#define STM32_HAS_TIM6 TRUE
1213#define STM32_TIM6_IS_32BITS FALSE
1214#define STM32_TIM6_CHANNELS 0
1215
1216#define STM32_HAS_TIM14 TRUE
1217#define STM32_TIM14_IS_32BITS FALSE
1218#define STM32_TIM14_CHANNELS 1
1219
1220#define STM32_HAS_TIM15 TRUE
1221#define STM32_TIM15_IS_32BITS FALSE
1222#define STM32_TIM15_CHANNELS 2
1223
1224#define STM32_HAS_TIM16 TRUE
1225#define STM32_TIM16_IS_32BITS FALSE
1226#define STM32_TIM16_CHANNELS 1
1227
1228#define STM32_HAS_TIM17 TRUE
1229#define STM32_TIM17_IS_32BITS FALSE
1230#define STM32_TIM17_CHANNELS 1
1231
1232#define STM32_HAS_TIM4 FALSE
1233#define STM32_HAS_TIM5 FALSE
1234#define STM32_HAS_TIM7 FALSE
1235#define STM32_HAS_TIM8 FALSE
1236#define STM32_HAS_TIM9 FALSE
1237#define STM32_HAS_TIM10 FALSE
1238#define STM32_HAS_TIM11 FALSE
1239#define STM32_HAS_TIM12 FALSE
1240#define STM32_HAS_TIM13 FALSE
1241#define STM32_HAS_TIM18 FALSE
1242#define STM32_HAS_TIM19 FALSE
1243#define STM32_HAS_TIM20 FALSE
1244#define STM32_HAS_TIM21 FALSE
1245#define STM32_HAS_TIM22 FALSE
1246
1247/* USART attributes.*/
1248#define STM32_HAS_USART1 TRUE
1249#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1250 STM32_DMA_STREAM_ID_MSK(1, 5))
1251#define STM32_USART1_RX_DMA_CHN 0x00000000
1252#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1253 STM32_DMA_STREAM_ID_MSK(1, 4))
1254#define STM32_USART1_TX_DMA_CHN 0x00000000
1255
1256#define STM32_HAS_USART2 TRUE
1257#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1258#define STM32_USART2_RX_DMA_CHN 0x00000000
1259#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1260#define STM32_USART2_TX_DMA_CHN 0x00000000
1261
1262#define STM32_HAS_USART3 FALSE
1263#define STM32_HAS_UART4 FALSE
1264#define STM32_HAS_UART5 FALSE
1265#define STM32_HAS_USART6 FALSE
1266#define STM32_HAS_UART7 FALSE
1267#define STM32_HAS_UART8 FALSE
1268#define STM32_HAS_LPUART1 FALSE
1269
1270/* USB attributes.*/
1271#define STM32_HAS_USB FALSE
1272#define STM32_HAS_OTG1 FALSE
1273#define STM32_HAS_OTG2 FALSE
1274
1275/* IWDG attributes.*/
1276#define STM32_HAS_IWDG TRUE
1277#define STM32_IWDG_IS_WINDOWED TRUE
1278
1279/* LTDC attributes.*/
1280#define STM32_HAS_LTDC FALSE
1281
1282/* DMA2D attributes.*/
1283#define STM32_HAS_DMA2D FALSE
1284
1285/* FSMC attributes.*/
1286#define STM32_HAS_FSMC FALSE
1287
1288/* CRC attributes.*/
1289#define STM32_HAS_CRC TRUE
1290#define STM32_CRC_PROGRAMMABLE TRUE
1291
1292/*===========================================================================*/
1293/* STM32F070x6, STM32F070xB. */
1294/*===========================================================================*/
1295#elif defined(STM32F070x6) || defined(STM32F070xB)
1296
1297/* Common identifier of all STM32F070 devices.*/
1298#define STM32F070
1299
1300/* RCC attributes. */
1301#define STM32_HAS_HSI48 FALSE
1302#define STM32_HAS_HSI_PREDIV TRUE
1303#define STM32_HAS_MCO_PREDIV TRUE
1304
1305/* ADC attributes.*/
1306#define STM32_HAS_ADC1 TRUE
1307#define STM32_ADC_SUPPORTS_PRESCALER FALSE
1308#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
1309#define STM32_ADC1_HANDLER Vector70
1310#define STM32_ADC1_NUMBER 12
1311#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
1312 STM32_DMA_STREAM_ID_MSK(1, 2))
1313#define STM32_ADC1_DMA_CHN 0x00000000
1314
1315#define STM32_HAS_ADC2 FALSE
1316#define STM32_HAS_ADC3 FALSE
1317#define STM32_HAS_ADC4 FALSE
1318
1319/* CAN attributes.*/
1320#define STM32_HAS_CAN1 FALSE
1321#define STM32_HAS_CAN2 FALSE
1322#define STM32_HAS_CAN3 FALSE
1323
1324/* DAC attributes.*/
1325#define STM32_HAS_DAC1_CH1 FALSE
1326#define STM32_HAS_DAC1_CH2 FALSE
1327#define STM32_HAS_DAC2_CH1 FALSE
1328#define STM32_HAS_DAC2_CH2 FALSE
1329
1330/* DMA attributes.*/
1331#define STM32_ADVANCED_DMA TRUE
1332#define STM32_DMA_SUPPORTS_DMAMUX FALSE
1333#define STM32_DMA_SUPPORTS_CSELR FALSE
1334#define STM32_DMA1_NUM_CHANNELS 5
1335#define STM32_DMA2_NUM_CHANNELS 0
1336#define STM32_DMA1_CH1_HANDLER Vector64
1337#define STM32_DMA1_CH23_HANDLER Vector68
1338#define STM32_DMA1_CH4567_HANDLER Vector6C
1339#define STM32_DMA1_CH1_NUMBER 9
1340#define STM32_DMA1_CH23_NUMBER 10
1341#define STM32_DMA1_CH4567_NUMBER 11
1342
1343#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
1344#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
1345#define STM32_DMA1_CH2_CMASK 0x00000006U
1346#define STM32_DMA1_CH3_CMASK 0x00000006U
1347
1348#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
1349#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
1350#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
1351#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
1352#define STM32_DMA1_CH4_CMASK 0x00000078U
1353#define STM32_DMA1_CH5_CMASK 0x00000078U
1354#define STM32_DMA1_CH6_CMASK 0x00000078U
1355#define STM32_DMA1_CH7_CMASK 0x00000078U
1356
1357/* ETH attributes.*/
1358#define STM32_HAS_ETH FALSE
1359
1360/* EXTI attributes.*/
1361#define STM32_EXTI_NUM_LINES 32
1362#define STM32_EXTI_IMR1_MASK 0x7F840000U
1363
1364/* GPIO attributes.*/
1365#define STM32_HAS_GPIOA TRUE
1366#define STM32_HAS_GPIOB TRUE
1367#define STM32_HAS_GPIOC TRUE
1368#if defined(STM32F070x6)
1369#define STM32_HAS_GPIOD FALSE
1370#else
1371#define STM32_HAS_GPIOD TRUE
1372#endif
1373#define STM32_HAS_GPIOE FALSE
1374#define STM32_HAS_GPIOF TRUE
1375#define STM32_HAS_GPIOG FALSE
1376#define STM32_HAS_GPIOH FALSE
1377#define STM32_HAS_GPIOI FALSE
1378#define STM32_HAS_GPIOJ FALSE
1379#define STM32_HAS_GPIOK FALSE
1380#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
1381 RCC_AHBENR_GPIOBEN | \
1382 RCC_AHBENR_GPIOCEN | \
1383 RCC_AHBENR_GPIODEN | \
1384 RCC_AHBENR_GPIOFEN)
1385
1386/* I2C attributes.*/
1387#define STM32_HAS_I2C1 TRUE
1388#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1389#define STM32_I2C1_RX_DMA_CHN 0x00000000
1390#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1391#define STM32_I2C1_TX_DMA_CHN 0x00000000
1392
1393#define STM32_HAS_I2C2 TRUE
1394#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1395#define STM32_I2C2_RX_DMA_CHN 0x00000000
1396#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1397#define STM32_I2C2_TX_DMA_CHN 0x00000000
1398
1399#define STM32_HAS_I2C3 FALSE
1400#define STM32_HAS_I2C4 FALSE
1401
1402/* QUADSPI attributes.*/
1403#define STM32_HAS_QUADSPI1 FALSE
1404
1405/* RTC attributes.*/
1406#define STM32_HAS_RTC TRUE
1407#define STM32_RTC_HAS_SUBSECONDS TRUE
1408#if defined (STM32F070xB)
1409#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
1410#else
1411#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
1412#endif
1413#define STM32_RTC_NUM_ALARMS 1
1414#define STM32_RTC_STORAGE_SIZE 0
1415#define STM32_RTC_COMMON_HANDLER Vector48
1416#define STM32_RTC_COMMON_NUMBER 2
1417#define STM32_RTC_ALARM_EXTI 17
1418#define STM32_RTC_TAMP_STAMP_EXTI 19
1419#define STM32_RTC_WKUP_EXTI 20
1420#define STM32_RTC_IRQ_ENABLE() \
1421 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
1422
1423/* SDIO attributes.*/
1424#define STM32_HAS_SDIO FALSE
1425
1426/* SPI attributes.*/
1427#define STM32_HAS_SPI1 TRUE
1428#define STM32_SPI1_SUPPORTS_I2S FALSE
1429#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1430#define STM32_SPI1_RX_DMA_CHN 0x00000000
1431#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1432#define STM32_SPI1_TX_DMA_CHN 0x00000000
1433
1434#define STM32_HAS_SPI2 TRUE
1435#define STM32_SPI2_SUPPORTS_I2S FALSE
1436#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1437#define STM32_SPI2_RX_DMA_CHN 0x00000000
1438#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1439#define STM32_SPI2_TX_DMA_CHN 0x00000000
1440
1441#define STM32_HAS_SPI3 FALSE
1442#define STM32_HAS_SPI4 FALSE
1443#define STM32_HAS_SPI5 FALSE
1444#define STM32_HAS_SPI6 FALSE
1445
1446/* TIM attributes.*/
1447#define STM32_TIM_MAX_CHANNELS 4
1448
1449#define STM32_HAS_TIM1 TRUE
1450#define STM32_TIM1_IS_32BITS FALSE
1451#define STM32_TIM1_CHANNELS 4
1452
1453#define STM32_HAS_TIM3 TRUE
1454#define STM32_TIM3_IS_32BITS FALSE
1455#define STM32_TIM3_CHANNELS 4
1456
1457#define STM32_HAS_TIM6 TRUE
1458#define STM32_TIM6_IS_32BITS FALSE
1459#define STM32_TIM6_CHANNELS 0
1460
1461#define STM32_HAS_TIM7 TRUE
1462#define STM32_TIM7_IS_32BITS FALSE
1463#define STM32_TIM7_CHANNELS 0
1464
1465#define STM32_HAS_TIM14 TRUE
1466#define STM32_TIM14_IS_32BITS FALSE
1467#define STM32_TIM14_CHANNELS 1
1468
1469#define STM32_HAS_TIM15 TRUE
1470#define STM32_TIM15_IS_32BITS FALSE
1471#define STM32_TIM15_CHANNELS 2
1472
1473#define STM32_HAS_TIM16 TRUE
1474#define STM32_TIM16_IS_32BITS FALSE
1475#define STM32_TIM16_CHANNELS 1
1476
1477#define STM32_HAS_TIM17 TRUE
1478#define STM32_TIM17_IS_32BITS FALSE
1479#define STM32_TIM17_CHANNELS 1
1480
1481#define STM32_HAS_TIM2 FALSE
1482#define STM32_HAS_TIM4 FALSE
1483#define STM32_HAS_TIM5 FALSE
1484#define STM32_HAS_TIM8 FALSE
1485#define STM32_HAS_TIM9 FALSE
1486#define STM32_HAS_TIM10 FALSE
1487#define STM32_HAS_TIM11 FALSE
1488#define STM32_HAS_TIM12 FALSE
1489#define STM32_HAS_TIM13 FALSE
1490#define STM32_HAS_TIM18 FALSE
1491#define STM32_HAS_TIM19 FALSE
1492#define STM32_HAS_TIM20 FALSE
1493#define STM32_HAS_TIM21 FALSE
1494#define STM32_HAS_TIM22 FALSE
1495
1496/* USART attributes.*/
1497#define STM32_HAS_USART1 TRUE
1498#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1499 STM32_DMA_STREAM_ID_MSK(1, 5))
1500#define STM32_USART1_RX_DMA_CHN 0x00000000
1501#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1502 STM32_DMA_STREAM_ID_MSK(1, 4))
1503#define STM32_USART1_TX_DMA_CHN 0x00000000
1504
1505#define STM32_HAS_USART2 TRUE
1506#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1507#define STM32_USART2_RX_DMA_CHN 0x00000000
1508#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1509#define STM32_USART2_TX_DMA_CHN 0x00000000
1510
1511#define STM32_HAS_USART3 TRUE
1512#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1513#define STM32_USART3_RX_DMA_CHN 0x00000000
1514#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1515#define STM32_USART3_TX_DMA_CHN 0x00000000
1516
1517#define STM32_HAS_UART4 TRUE
1518#define STM32_UART4_RX_DMA_MSK 0
1519#define STM32_UART4_RX_DMA_CHN 0x00000000
1520#define STM32_UART4_TX_DMA_MSK 0
1521#define STM32_UART4_TX_DMA_CHN 0x00000000
1522
1523#define STM32_HAS_UART5 FALSE
1524#define STM32_HAS_USART6 FALSE
1525#define STM32_HAS_UART7 FALSE
1526#define STM32_HAS_UART8 FALSE
1527#define STM32_HAS_LPUART1 FALSE
1528
1529/* USB attributes.*/
1530#define STM32_HAS_USB TRUE
1531#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
1532#define STM32_USB_PMA_SIZE 768
1533#define STM32_USB_HAS_BCDR TRUE
1534
1535#define STM32_HAS_OTG1 FALSE
1536#define STM32_HAS_OTG2 FALSE
1537
1538/* IWDG attributes.*/
1539#define STM32_HAS_IWDG TRUE
1540#define STM32_IWDG_IS_WINDOWED TRUE
1541
1542/* LTDC attributes.*/
1543#define STM32_HAS_LTDC FALSE
1544
1545/* DMA2D attributes.*/
1546#define STM32_HAS_DMA2D FALSE
1547
1548/* FSMC attributes.*/
1549#define STM32_HAS_FSMC FALSE
1550
1551/* CRC attributes.*/
1552#define STM32_HAS_CRC TRUE
1553#define STM32_CRC_PROGRAMMABLE FALSE
1554
1555/*===========================================================================*/
1556/* STM32F071xB, STM32F072xB, STM32F078xx. */
1557/*===========================================================================*/
1558#elif defined(STM32F071xB) || defined(STM32F072xB) || \
1559 defined(STM32F078xx)
1560
1561/* RCC attributes. */
1562#define STM32_HAS_HSI48 TRUE
1563#define STM32_HAS_HSI_PREDIV TRUE
1564#define STM32_HAS_MCO_PREDIV TRUE
1565
1566/* ADC attributes.*/
1567#define STM32_HAS_ADC1 TRUE
1568#define STM32_ADC_SUPPORTS_PRESCALER FALSE
1569#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
1570#define STM32_ADC1_HANDLER Vector70
1571#define STM32_ADC1_NUMBER 12
1572#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
1573 STM32_DMA_STREAM_ID_MSK(1, 2))
1574#define STM32_ADC1_DMA_CHN 0x00000000
1575
1576#define STM32_HAS_ADC2 FALSE
1577#define STM32_HAS_ADC3 FALSE
1578#define STM32_HAS_ADC4 FALSE
1579
1580/* CAN attributes.*/
1581#if defined(STM32F072xB)
1582#define STM32_HAS_CAN1 TRUE
1583#define STM32_CAN_MAX_FILTERS 14
1584#else
1585#define STM32_HAS_CAN1 FALSE
1586#endif
1587#define STM32_HAS_CAN2 FALSE
1588#define STM32_HAS_CAN3 FALSE
1589
1590/* DAC attributes.*/
1591#define STM32_HAS_DAC1_CH1 TRUE
1592#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1593#define STM32_DAC1_CH1_DMA_CHN 0x00000000
1594
1595#define STM32_HAS_DAC1_CH2 TRUE
1596#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1597#define STM32_DAC1_CH2_DMA_CHN 0x00000000
1598
1599#define STM32_HAS_DAC2_CH1 FALSE
1600#define STM32_HAS_DAC2_CH2 FALSE
1601
1602/* DMA attributes.*/
1603#define STM32_ADVANCED_DMA TRUE
1604#define STM32_DMA_SUPPORTS_DMAMUX FALSE
1605#define STM32_DMA_SUPPORTS_CSELR FALSE
1606#define STM32_DMA1_NUM_CHANNELS 7
1607#define STM32_DMA2_NUM_CHANNELS 0
1608#define STM32_DMA1_CH1_HANDLER Vector64
1609#define STM32_DMA1_CH23_HANDLER Vector68
1610#define STM32_DMA1_CH4567_HANDLER Vector6C
1611#define STM32_DMA1_CH1_NUMBER 9
1612#define STM32_DMA1_CH23_NUMBER 10
1613#define STM32_DMA1_CH4567_NUMBER 11
1614
1615#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
1616#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
1617#define STM32_DMA1_CH2_CMASK 0x00000006U
1618#define STM32_DMA1_CH3_CMASK 0x00000006U
1619
1620#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
1621#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
1622#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
1623#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
1624#define STM32_DMA1_CH4_CMASK 0x00000078U
1625#define STM32_DMA1_CH5_CMASK 0x00000078U
1626#define STM32_DMA1_CH6_CMASK 0x00000078U
1627#define STM32_DMA1_CH7_CMASK 0x00000078U
1628
1629/* ETH attributes.*/
1630#define STM32_HAS_ETH FALSE
1631
1632/* EXTI attributes.*/
1633#define STM32_EXTI_NUM_LINES 32
1634#define STM32_EXTI_IMR1_MASK 0x7F840000U
1635
1636/* GPIO attributes.*/
1637#define STM32_HAS_GPIOA TRUE
1638#define STM32_HAS_GPIOB TRUE
1639#define STM32_HAS_GPIOC TRUE
1640#define STM32_HAS_GPIOD TRUE
1641#define STM32_HAS_GPIOE TRUE
1642#define STM32_HAS_GPIOF TRUE
1643#define STM32_HAS_GPIOG FALSE
1644#define STM32_HAS_GPIOH FALSE
1645#define STM32_HAS_GPIOI FALSE
1646#define STM32_HAS_GPIOJ FALSE
1647#define STM32_HAS_GPIOK FALSE
1648#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
1649 RCC_AHBENR_GPIOBEN | \
1650 RCC_AHBENR_GPIOCEN | \
1651 RCC_AHBENR_GPIODEN | \
1652 RCC_AHBENR_GPIOEEN | \
1653 RCC_AHBENR_GPIOFEN)
1654
1655/* I2C attributes.*/
1656#define STM32_HAS_I2C1 TRUE
1657#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1658 STM32_DMA_STREAM_ID_MSK(1, 7))
1659#define STM32_I2C1_RX_DMA_CHN 0x00000000
1660#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1661 STM32_DMA_STREAM_ID_MSK(1, 6))
1662#define STM32_I2C1_TX_DMA_CHN 0x00000000
1663
1664#define STM32_HAS_I2C2 TRUE
1665#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1666#define STM32_I2C2_RX_DMA_CHN 0x00000000
1667#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1668#define STM32_I2C2_TX_DMA_CHN 0x00000000
1669
1670#define STM32_HAS_I2C3 FALSE
1671#define STM32_HAS_I2C4 FALSE
1672
1673/* QUADSPI attributes.*/
1674#define STM32_HAS_QUADSPI1 FALSE
1675
1676/* RTC attributes.*/
1677#define STM32_HAS_RTC TRUE
1678#define STM32_RTC_HAS_SUBSECONDS TRUE
1679#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
1680#define STM32_RTC_NUM_ALARMS 1
1681#define STM32_RTC_STORAGE_SIZE 0
1682#define STM32_RTC_COMMON_HANDLER Vector48
1683#define STM32_RTC_COMMON_NUMBER 2
1684#define STM32_RTC_ALARM_EXTI 17
1685#define STM32_RTC_TAMP_STAMP_EXTI 19
1686#define STM32_RTC_WKUP_EXTI 20
1687#define STM32_RTC_IRQ_ENABLE() \
1688 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
1689
1690/* SDIO attributes.*/
1691#define STM32_HAS_SDIO FALSE
1692
1693/* SPI attributes.*/
1694#define STM32_HAS_SPI1 TRUE
1695#define STM32_SPI1_SUPPORTS_I2S TRUE
1696#define STM32_SPI1_I2S_FULLDUPLEX FALSE
1697#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1698#define STM32_SPI1_RX_DMA_CHN 0x00000000
1699#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1700#define STM32_SPI1_TX_DMA_CHN 0x00000000
1701
1702#define STM32_HAS_SPI2 TRUE
1703#define STM32_SPI2_SUPPORTS_I2S TRUE
1704#define STM32_SPI2_I2S_FULLDUPLEX FALSE
1705#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
1706 STM32_DMA_STREAM_ID_MSK(1, 6))
1707#define STM32_SPI2_RX_DMA_CHN 0x00000000
1708#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
1709 STM32_DMA_STREAM_ID_MSK(1, 7))
1710#define STM32_SPI2_TX_DMA_CHN 0x00000000
1711
1712#define STM32_HAS_SPI3 FALSE
1713#define STM32_HAS_SPI4 FALSE
1714#define STM32_HAS_SPI5 FALSE
1715#define STM32_HAS_SPI6 FALSE
1716
1717/* TIM attributes.*/
1718#define STM32_TIM_MAX_CHANNELS 4
1719
1720#define STM32_HAS_TIM1 TRUE
1721#define STM32_TIM1_IS_32BITS FALSE
1722#define STM32_TIM1_CHANNELS 4
1723
1724#define STM32_HAS_TIM2 TRUE
1725#define STM32_TIM2_IS_32BITS TRUE
1726#define STM32_TIM2_CHANNELS 4
1727
1728#define STM32_HAS_TIM3 TRUE
1729#define STM32_TIM3_IS_32BITS FALSE
1730#define STM32_TIM3_CHANNELS 4
1731
1732#define STM32_HAS_TIM6 TRUE
1733#define STM32_TIM6_IS_32BITS FALSE
1734#define STM32_TIM6_CHANNELS 0
1735
1736#define STM32_HAS_TIM14 TRUE
1737#define STM32_TIM14_IS_32BITS FALSE
1738#define STM32_TIM14_CHANNELS 1
1739
1740#define STM32_HAS_TIM15 TRUE
1741#define STM32_TIM15_IS_32BITS FALSE
1742#define STM32_TIM15_CHANNELS 2
1743
1744#define STM32_HAS_TIM16 TRUE
1745#define STM32_TIM16_IS_32BITS FALSE
1746#define STM32_TIM16_CHANNELS 1
1747
1748#define STM32_HAS_TIM17 TRUE
1749#define STM32_TIM17_IS_32BITS FALSE
1750#define STM32_TIM17_CHANNELS 1
1751
1752#define STM32_HAS_TIM4 FALSE
1753#define STM32_HAS_TIM5 FALSE
1754#define STM32_HAS_TIM7 FALSE
1755#define STM32_HAS_TIM8 FALSE
1756#define STM32_HAS_TIM9 FALSE
1757#define STM32_HAS_TIM10 FALSE
1758#define STM32_HAS_TIM11 FALSE
1759#define STM32_HAS_TIM12 FALSE
1760#define STM32_HAS_TIM13 FALSE
1761#define STM32_HAS_TIM18 FALSE
1762#define STM32_HAS_TIM19 FALSE
1763#define STM32_HAS_TIM20 FALSE
1764#define STM32_HAS_TIM21 FALSE
1765#define STM32_HAS_TIM22 FALSE
1766
1767/* USART attributes.*/
1768#define STM32_HAS_USART1 TRUE
1769#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1770 STM32_DMA_STREAM_ID_MSK(1, 5))
1771#define STM32_USART1_RX_DMA_CHN 0x00000000
1772#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1773 STM32_DMA_STREAM_ID_MSK(1, 4))
1774#define STM32_USART1_TX_DMA_CHN 0x00000000
1775
1776#define STM32_HAS_USART2 TRUE
1777#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
1778 STM32_DMA_STREAM_ID_MSK(1, 6))
1779#define STM32_USART2_RX_DMA_CHN 0x00000000
1780#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
1781 STM32_DMA_STREAM_ID_MSK(1, 7))
1782#define STM32_USART2_TX_DMA_CHN 0x00000000
1783
1784#define STM32_HAS_USART3 TRUE
1785#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
1786 STM32_DMA_STREAM_ID_MSK(1, 3))
1787#define STM32_USART3_RX_DMA_CHN 0x00000000
1788#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
1789 STM32_DMA_STREAM_ID_MSK(1, 2))
1790#define STM32_USART3_TX_DMA_CHN 0x00000000
1791
1792#define STM32_HAS_UART4 TRUE
1793#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
1794#define STM32_UART4_RX_DMA_CHN 0x00000000
1795#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
1796#define STM32_UART4_TX_DMA_CHN 0x00000000
1797
1798#define STM32_HAS_UART5 FALSE
1799#define STM32_HAS_USART6 FALSE
1800#define STM32_HAS_UART7 FALSE
1801#define STM32_HAS_UART8 FALSE
1802#define STM32_HAS_LPUART1 FALSE
1803
1804/* USB attributes.*/
1805#if defined(STM32F072xB) || defined(STM32F078xx)
1806#define STM32_HAS_USB TRUE
1807#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
1808#define STM32_USB_PMA_SIZE 768
1809#define STM32_USB_HAS_BCDR TRUE
1810#else
1811#define STM32_HAS_USB FALSE
1812#endif
1813#define STM32_HAS_OTG1 FALSE
1814#define STM32_HAS_OTG2 FALSE
1815
1816/* IWDG attributes.*/
1817#define STM32_HAS_IWDG TRUE
1818#define STM32_IWDG_IS_WINDOWED TRUE
1819
1820/* LTDC attributes.*/
1821#define STM32_HAS_LTDC FALSE
1822
1823/* DMA2D attributes.*/
1824#define STM32_HAS_DMA2D FALSE
1825
1826/* FSMC attributes.*/
1827#define STM32_HAS_FSMC FALSE
1828
1829/* CRC attributes.*/
1830#define STM32_HAS_CRC TRUE
1831#define STM32_CRC_PROGRAMMABLE TRUE
1832
1833/*===========================================================================*/
1834/* STM32F091xC, STM32F098xx. */
1835/*===========================================================================*/
1836#elif defined(STM32F091xC) || defined(STM32F098xx)
1837
1838/* RCC attributes. */
1839#define STM32_HAS_HSI48 TRUE
1840#define STM32_HAS_HSI_PREDIV TRUE
1841#define STM32_HAS_MCO_PREDIV TRUE
1842
1843/* ADC attributes.*/
1844#define STM32_HAS_ADC1 TRUE
1845#define STM32_ADC_SUPPORTS_PRESCALER FALSE
1846#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
1847#define STM32_ADC1_HANDLER Vector70
1848#define STM32_ADC1_NUMBER 12
1849#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
1850 STM32_DMA_STREAM_ID_MSK(1, 2) |\
1851 STM32_DMA_STREAM_ID_MSK(2, 5))
1852#define STM32_ADC1_DMA_CHN 0x00100011
1853
1854#define STM32_HAS_ADC2 FALSE
1855#define STM32_HAS_ADC3 FALSE
1856#define STM32_HAS_ADC4 FALSE
1857
1858/* CAN attributes.*/
1859#define STM32_HAS_CAN1 TRUE
1860#define STM32_HAS_CAN2 FALSE
1861#define STM32_HAS_CAN3 FALSE
1862#define STM32_CAN_MAX_FILTERS 14
1863
1864/* DAC attributes.*/
1865#define STM32_HAS_DAC1_CH1 TRUE
1866#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1867 STM32_DMA_STREAM_ID_MSK(2, 3))
1868#define STM32_DAC1_CH1_DMA_CHN 0x00000100
1869
1870#define STM32_HAS_DAC1_CH2 TRUE
1871#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
1872 STM32_DMA_STREAM_ID_MSK(2, 4))
1873#define STM32_DAC1_CH2_DMA_CHN 0x00001000
1874
1875#define STM32_HAS_DAC2_CH1 FALSE
1876#define STM32_HAS_DAC2_CH2 FALSE
1877
1878/* DMA attributes.*/
1879#define STM32_ADVANCED_DMA TRUE
1880#define STM32_DMA_SUPPORTS_DMAMUX FALSE
1881#define STM32_DMA_SUPPORTS_CSELR TRUE
1882
1883#define STM32_DMA1_NUM_CHANNELS 7
1884#define STM32_DMA2_NUM_CHANNELS 5
1885
1886#define STM32_DMA1_CH1_HANDLER Vector64
1887#define STM32_DMA12_CH23_CH12_HANDLER Vector68
1888#define STM32_DMA12_CH4567_CH345_HANDLER Vector6C
1889#define STM32_DMA1_CH1_NUMBER 9
1890#define STM32_DMA12_CH23_CH12_NUMBER 10
1891#define STM32_DMA12_CH4567_CH345_NUMBER 11
1892
1893#define STM32_DMA1_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
1894#define STM32_DMA1_CH3_NUMBER STM32_DMA12_CH23_CH12_NUMBER
1895#define STM32_DMA2_CH1_NUMBER STM32_DMA12_CH23_CH12_NUMBER
1896#define STM32_DMA2_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
1897#define STM32_DMA1_CH2_CMASK 0x00000186U
1898#define STM32_DMA1_CH3_CMASK 0x00000186U
1899#define STM32_DMA2_CH1_CMASK 0x00000186U
1900#define STM32_DMA2_CH2_CMASK 0x00000186U
1901
1902#define STM32_DMA1_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1903#define STM32_DMA1_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1904#define STM32_DMA1_CH6_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1905#define STM32_DMA1_CH7_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1906#define STM32_DMA2_CH3_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1907#define STM32_DMA2_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1908#define STM32_DMA2_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
1909#define STM32_DMA1_CH4_CMASK 0x00000E78U
1910#define STM32_DMA1_CH5_CMASK 0x00000E78U
1911#define STM32_DMA1_CH6_CMASK 0x00000E78U
1912#define STM32_DMA1_CH7_CMASK 0x00000E78U
1913#define STM32_DMA2_CH3_CMASK 0x00000E78U
1914#define STM32_DMA2_CH4_CMASK 0x00000E78U
1915#define STM32_DMA2_CH5_CMASK 0x00000E78U
1916
1917/* ETH attributes.*/
1918#define STM32_HAS_ETH FALSE
1919
1920/* EXTI attributes.*/
1921#define STM32_EXTI_NUM_LINES 32
1922#define STM32_EXTI_IMR1_MASK 0x7F840000U
1923
1924/* GPIO attributes.*/
1925#define STM32_HAS_GPIOA TRUE
1926#define STM32_HAS_GPIOB TRUE
1927#define STM32_HAS_GPIOC TRUE
1928#define STM32_HAS_GPIOD TRUE
1929#define STM32_HAS_GPIOE FALSE
1930#define STM32_HAS_GPIOF TRUE
1931#define STM32_HAS_GPIOG FALSE
1932#define STM32_HAS_GPIOH FALSE
1933#define STM32_HAS_GPIOI FALSE
1934#define STM32_HAS_GPIOJ FALSE
1935#define STM32_HAS_GPIOK FALSE
1936#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
1937 RCC_AHBENR_GPIOBEN | \
1938 RCC_AHBENR_GPIOCEN | \
1939 RCC_AHBENR_GPIODEN | \
1940 RCC_AHBENR_GPIOFEN)
1941
1942/* I2C attributes.*/
1943#define STM32_HAS_I2C1 TRUE
1944#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1945 STM32_DMA_STREAM_ID_MSK(1, 7))
1946#define STM32_I2C1_RX_DMA_CHN 0x02000200
1947#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1948 STM32_DMA_STREAM_ID_MSK(1, 6))
1949#define STM32_I2C1_TX_DMA_CHN 0x00200020
1950
1951#define STM32_HAS_I2C2 TRUE
1952#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
1953 STM32_DMA_STREAM_ID_MSK(2, 2))
1954#define STM32_I2C2_RX_DMA_CHN 0x00020020
1955#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
1956 STM32_DMA_STREAM_ID_MSK(2, 1))
1957#define STM32_I2C2_TX_DMA_CHN 0x00002002
1958
1959#define STM32_HAS_I2C3 FALSE
1960#define STM32_HAS_I2C4 FALSE
1961
1962/* QUADSPI attributes.*/
1963#define STM32_HAS_QUADSPI1 FALSE
1964
1965/* RTC attributes.*/
1966#define STM32_HAS_RTC TRUE
1967#define STM32_RTC_HAS_SUBSECONDS TRUE
1968#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
1969#define STM32_RTC_NUM_ALARMS 1
1970#define STM32_RTC_STORAGE_SIZE 0
1971#define STM32_RTC_COMMON_HANDLER Vector48
1972#define STM32_RTC_COMMON_NUMBER 2
1973#define STM32_RTC_ALARM_EXTI 17
1974#define STM32_RTC_TAMP_STAMP_EXTI 19
1975#define STM32_RTC_WKUP_EXTI 20
1976#define STM32_RTC_IRQ_ENABLE() \
1977 nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
1978
1979/* SDIO attributes.*/
1980#define STM32_HAS_SDIO FALSE
1981
1982/* SPI attributes.*/
1983#define STM32_HAS_SPI1 TRUE
1984#define STM32_SPI1_SUPPORTS_I2S TRUE
1985#define STM32_SPI1_I2S_FULLDUPLEX FALSE
1986#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
1987 STM32_DMA_STREAM_ID_MSK(2, 3))
1988#define STM32_SPI1_RX_DMA_CHN 0x00000330
1989#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1990 STM32_DMA_STREAM_ID_MSK(2, 4))
1991#define STM32_SPI1_TX_DMA_CHN 0x00003300
1992
1993#define STM32_HAS_SPI2 TRUE
1994#define STM32_SPI2_SUPPORTS_I2S TRUE
1995#define STM32_SPI2_I2S_FULLDUPLEX FALSE
1996#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
1997 STM32_DMA_STREAM_ID_MSK(1, 6))
1998#define STM32_SPI2_RX_DMA_CHN 0x00303000
1999#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
2000 STM32_DMA_STREAM_ID_MSK(1, 7))
2001#define STM32_SPI2_TX_DMA_CHN 0x03030000
2002
2003#define STM32_HAS_SPI3 FALSE
2004#define STM32_HAS_SPI4 FALSE
2005#define STM32_HAS_SPI5 FALSE
2006#define STM32_HAS_SPI6 FALSE
2007
2008/* TIM attributes.*/
2009#define STM32_TIM_MAX_CHANNELS 4
2010
2011#define STM32_HAS_TIM1 TRUE
2012#define STM32_TIM1_IS_32BITS FALSE
2013#define STM32_TIM1_CHANNELS 4
2014
2015#define STM32_HAS_TIM2 TRUE
2016#define STM32_TIM2_IS_32BITS TRUE
2017#define STM32_TIM2_CHANNELS 4
2018
2019#define STM32_HAS_TIM3 TRUE
2020#define STM32_TIM3_IS_32BITS FALSE
2021#define STM32_TIM3_CHANNELS 4
2022
2023#define STM32_HAS_TIM6 TRUE
2024#define STM32_TIM6_IS_32BITS FALSE
2025#define STM32_TIM6_CHANNELS 0
2026
2027#define STM32_HAS_TIM7 TRUE
2028#define STM32_TIM7_IS_32BITS FALSE
2029#define STM32_TIM7_CHANNELS 0
2030
2031#define STM32_HAS_TIM14 TRUE
2032#define STM32_TIM14_IS_32BITS FALSE
2033#define STM32_TIM14_CHANNELS 1
2034
2035#define STM32_HAS_TIM15 TRUE
2036#define STM32_TIM15_IS_32BITS FALSE
2037#define STM32_TIM15_CHANNELS 2
2038
2039#define STM32_HAS_TIM16 TRUE
2040#define STM32_TIM16_IS_32BITS FALSE
2041#define STM32_TIM16_CHANNELS 1
2042
2043#define STM32_HAS_TIM17 TRUE
2044#define STM32_TIM17_IS_32BITS FALSE
2045#define STM32_TIM17_CHANNELS 1
2046
2047#define STM32_HAS_TIM4 FALSE
2048#define STM32_HAS_TIM5 FALSE
2049#define STM32_HAS_TIM8 FALSE
2050#define STM32_HAS_TIM9 FALSE
2051#define STM32_HAS_TIM10 FALSE
2052#define STM32_HAS_TIM11 FALSE
2053#define STM32_HAS_TIM12 FALSE
2054#define STM32_HAS_TIM13 FALSE
2055#define STM32_HAS_TIM18 FALSE
2056#define STM32_HAS_TIM19 FALSE
2057#define STM32_HAS_TIM20 FALSE
2058#define STM32_HAS_TIM21 FALSE
2059#define STM32_HAS_TIM22 FALSE
2060
2061/* USART attributes.*/
2062#define STM32_HAS_USART1 TRUE
2063#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2064 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2065 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2066 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2067 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2068 STM32_DMA_STREAM_ID_MSK(2, 3))
2069#define STM32_USART1_RX_DMA_CHN 0x00880888
2070#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2071 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2072 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2073 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2074 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2075 STM32_DMA_STREAM_ID_MSK(2, 5))
2076#define STM32_USART1_TX_DMA_CHN 0x08088088
2077
2078#define STM32_HAS_USART2 TRUE
2079#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2080 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2081 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2082 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2083 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2084 STM32_DMA_STREAM_ID_MSK(2, 3))
2085#define STM32_USART2_RX_DMA_CHN 0x00990999
2086#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2087 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2088 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2089 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2090 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2091 STM32_DMA_STREAM_ID_MSK(2, 5))
2092#define STM32_USART2_TX_DMA_CHN 0x09099099
2093
2094#define STM32_HAS_USART3 TRUE
2095#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2096 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2097 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2098 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2099 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2100 STM32_DMA_STREAM_ID_MSK(2, 3))
2101#define STM32_USART3_RX_DMA_CHN 0x00AA0AAA
2102#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2103 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2104 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2105 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2106 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2107 STM32_DMA_STREAM_ID_MSK(2, 5))
2108#define STM32_USART3_TX_DMA_CHN 0x0A0AA0AA
2109
2110#define STM32_HAS_UART4 TRUE
2111#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2112 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2113 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2114 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2115 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2116 STM32_DMA_STREAM_ID_MSK(2, 3))
2117#define STM32_UART4_RX_DMA_CHN 0x00BB0BBB
2118#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2119 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2120 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2121 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2122 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2123 STM32_DMA_STREAM_ID_MSK(2, 5))
2124#define STM32_UART4_TX_DMA_CHN 0x0B0BB0BB
2125
2126#define STM32_HAS_UART5 TRUE
2127#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2128 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2129 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2130 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2131 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2132 STM32_DMA_STREAM_ID_MSK(2, 3))
2133#define STM32_UART5_RX_DMA_CHN 0x00CC0CCC
2134#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2135 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2136 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2137 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2138 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2139 STM32_DMA_STREAM_ID_MSK(2, 5))
2140#define STM32_UART5_TX_DMA_CHN 0x0C0CC0CC
2141
2142#define STM32_HAS_USART6 TRUE
2143#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2144 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2145 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2146 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2147 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2148 STM32_DMA_STREAM_ID_MSK(2, 3))
2149#define STM32_USART6_RX_DMA_CHN 0x00DD0DDD
2150#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2151 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2152 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2153 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2154 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2155 STM32_DMA_STREAM_ID_MSK(2, 5))
2156#define STM32_USART6_TX_DMA_CHN 0x0D0DD0DD
2157
2158#define STM32_HAS_UART7 TRUE
2159#define STM32_UART7_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2160 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2161 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2162 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2163 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2164 STM32_DMA_STREAM_ID_MSK(2, 3))
2165#define STM32_UART7_RX_DMA_CHN 0x00EE0EEE
2166#define STM32_UART7_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2167 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2168 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2169 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2170 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2171 STM32_DMA_STREAM_ID_MSK(2, 5))
2172#define STM32_UART7_TX_DMA_CHN 0x0E0EE0EE
2173
2174#define STM32_HAS_UART8 TRUE
2175#define STM32_UART8_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
2176 STM32_DMA_STREAM_ID_MSK(1, 3) |\
2177 STM32_DMA_STREAM_ID_MSK(1, 5) |\
2178 STM32_DMA_STREAM_ID_MSK(1, 6) |\
2179 STM32_DMA_STREAM_ID_MSK(2, 2) |\
2180 STM32_DMA_STREAM_ID_MSK(2, 3))
2181#define STM32_UART8_RX_DMA_CHN 0x00FF0FFF
2182#define STM32_UART8_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
2183 STM32_DMA_STREAM_ID_MSK(1, 4) |\
2184 STM32_DMA_STREAM_ID_MSK(1, 7) |\
2185 STM32_DMA_STREAM_ID_MSK(2, 1) |\
2186 STM32_DMA_STREAM_ID_MSK(2, 4) |\
2187 STM32_DMA_STREAM_ID_MSK(2, 5))
2188#define STM32_UART8_TX_DMA_CHN 0x0F0FF0FF
2189
2190#define STM32_HAS_LPUART1 FALSE
2191
2192/* USB attributes.*/
2193#define STM32_HAS_USB FALSE
2194#define STM32_HAS_OTG1 FALSE
2195#define STM32_HAS_OTG2 FALSE
2196
2197/* IWDG attributes.*/
2198#define STM32_HAS_IWDG TRUE
2199#define STM32_IWDG_IS_WINDOWED TRUE
2200
2201/* LTDC attributes.*/
2202#define STM32_HAS_LTDC FALSE
2203
2204/* DMA2D attributes.*/
2205#define STM32_HAS_DMA2D FALSE
2206
2207/* FSMC attributes.*/
2208#define STM32_HAS_FSMC FALSE
2209
2210/* CRC attributes.*/
2211#define STM32_HAS_CRC TRUE
2212#define STM32_CRC_PROGRAMMABLE TRUE
2213
2214#else
2215#error "STM32F0xx device not specified"
2216#endif
2217
2218/** @} */
2219
2220#endif /* STM32_REGISTRY_H */
2221
2222/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:51:14 +0100