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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F0xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f0xx.h.
22 *
23 * @addtogroup STM32F0xx_RCC
24 * @{
25 */
26
27#ifndef STM32_RCC_H
28#define STM32_RCC_H
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Derived constants and error checks. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver data structures and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver macros. */
48/*===========================================================================*/
49
50/**
51 * @name Generic RCC operations
52 * @{
53 */
54/**
55 * @brief Enables the clock of one or more peripheral on the APB1 bus.
56 * @note The @p lp parameter is ignored in this family.
57 *
58 * @param[in] mask APB1 peripherals mask
59 * @param[in] lp low power enable flag
60 *
61 * @api
62 */
63#define rccEnableAPB1(mask, lp) { \
64 RCC->APB1ENR |= (mask); \
65 (void)RCC->APB1ENR; \
66}
67
68/**
69 * @brief Disables the clock of one or more peripheral on the APB1 bus.
70 *
71 * @param[in] mask APB1 peripherals mask
72 *
73 * @api
74 */
75#define rccDisableAPB1(mask) { \
76 RCC->APB1ENR &= ~(mask); \
77 (void)RCC->APB1ENR; \
78}
79
80/**
81 * @brief Resets one or more peripheral on the APB1 bus.
82 *
83 * @param[in] mask APB1 peripherals mask
84 *
85 * @api
86 */
87#define rccResetAPB1(mask) { \
88 RCC->APB1RSTR |= (mask); \
89 RCC->APB1RSTR &= ~(mask); \
90 (void)RCC->APB1RSTR; \
91}
92
93/**
94 * @brief Enables the clock of one or more peripheral on the APB2 bus.
95 * @note The @p lp parameter is ignored in this family.
96 *
97 * @param[in] mask APB2 peripherals mask
98 * @param[in] lp low power enable flag
99 *
100 * @api
101 */
102#define rccEnableAPB2(mask, lp) { \
103 RCC->APB2ENR |= (mask); \
104 (void)RCC->APB2ENR; \
105}
106
107/**
108 * @brief Disables the clock of one or more peripheral on the APB2 bus.
109 *
110 * @param[in] mask APB2 peripherals mask
111 *
112 * @api
113 */
114#define rccDisableAPB2(mask) { \
115 RCC->APB2ENR &= ~(mask); \
116 (void)RCC->APB2ENR; \
117}
118
119/**
120 * @brief Resets one or more peripheral on the APB2 bus.
121 *
122 * @param[in] mask APB2 peripherals mask
123 *
124 * @api
125 */
126#define rccResetAPB2(mask) { \
127 RCC->APB2RSTR |= (mask); \
128 RCC->APB2RSTR &= ~(mask); \
129 (void)RCC->APB2RSTR; \
130}
131
132/**
133 * @brief Enables the clock of one or more peripheral on the AHB bus.
134 * @note The @p lp parameter is ignored in this family.
135 *
136 * @param[in] mask AHB peripherals mask
137 * @param[in] lp low power enable flag
138 *
139 * @api
140 */
141#define rccEnableAHB(mask, lp) { \
142 RCC->AHBENR |= (mask); \
143 (void)RCC->AHBENR; \
144}
145
146/**
147 * @brief Disables the clock of one or more peripheral on the AHB bus.
148 *
149 * @param[in] mask AHB peripherals mask
150 *
151 * @api
152 */
153#define rccDisableAHB(mask) { \
154 RCC->AHBENR &= ~(mask); \
155 (void)RCC->AHBENR; \
156}
157
158/**
159 * @brief Resets one or more peripheral on the AHB bus.
160 *
161 * @param[in] mask AHB peripherals mask
162 *
163 * @api
164 */
165#define rccResetAHB(mask) { \
166 RCC->AHBRSTR |= (mask); \
167 RCC->AHBRSTR &= ~(mask); \
168 (void)RCC->AHBRSTR; \
169}
170/** @} */
171
172/**
173 * @name ADC peripherals specific RCC operations
174 * @{
175 */
176/**
177 * @brief Enables the ADC1 peripheral clock.
178 * @note The @p lp parameter is ignored in this family.
179 *
180 * @param[in] lp low power enable flag
181 *
182 * @api
183 */
184#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
185
186/**
187 * @brief Disables the ADC1 peripheral clock.
188 *
189 * @api
190 */
191#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
192
193/**
194 * @brief Resets the ADC1 peripheral.
195 *
196 * @api
197 */
198#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
199/** @} */
200
201/**
202 * @name CAN peripherals specific RCC operations
203 * @{
204 */
205/**
206 * @brief Enables the CAN1 peripheral clock.
207 * @note The @p lp parameter is ignored in this family.
208 *
209 * @param[in] lp low power enable flag
210 *
211 * @api
212 */
213#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
214
215/**
216 * @brief Disables the CAN1 peripheral clock.
217 *
218 * @api
219 */
220#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CANEN)
221
222/**
223 * @brief Resets the CAN1 peripheral.
224 *
225 * @api
226 */
227#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
228/** @} */
229
230/**
231 * @name DAC peripheral specific RCC operations
232 * @{
233 */
234/**
235 * @brief Enables the DAC1 peripheral clock.
236 * @note The @p lp parameter is ignored in this family.
237 *
238 * @param[in] lp low power enable flag
239 *
240 * @api
241 */
242#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
243
244/**
245 * @brief Disables the DAC1 peripheral clock.
246 *
247 * @api
248 */
249#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
250
251/**
252 * @brief Resets the DAC1 peripheral.
253 *
254 * @api
255 */
256#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
257/** @} */
258
259/**
260 * @name PWR interface specific RCC operations
261 * @{
262 */
263/**
264 * @brief Enables the PWR interface clock.
265 * @note The @p lp parameter is ignored in this family.
266 *
267 * @param[in] lp low power enable flag
268 *
269 * @api
270 */
271#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
272
273/**
274 * @brief Disables PWR interface clock.
275 *
276 * @api
277 */
278#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
279
280/**
281 * @brief Resets the PWR interface.
282 *
283 * @api
284 */
285#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
286/** @} */
287
288/**
289 * @name DMA peripherals specific RCC operations
290 * @{
291 */
292/**
293 * @brief Enables the DMA1 peripheral clock.
294 * @note The @p lp parameter is ignored in this family.
295 *
296 * @param[in] lp low power enable flag
297 *
298 * @api
299 */
300#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
301
302/**
303 * @brief Disables the DMA1 peripheral clock.
304 *
305 * @api
306 */
307#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
308
309/**
310 * @brief Resets the DMA1 peripheral.
311 * @note Not supported in this family, does nothing.
312 *
313 * @api
314 */
315#define rccResetDMA1()
316
317/**
318 * @brief Enables the DMA2 peripheral clock.
319 * @note The @p lp parameter is ignored in this family.
320 *
321 * @param[in] lp low power enable flag
322 *
323 * @api
324 */
325#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
326
327/**
328 * @brief Disables the DMA2 peripheral clock.
329 *
330 * @api
331 */
332#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
333
334/**
335 * @brief Resets the DMA2 peripheral.
336 * @note Not supported in this family, does nothing.
337 *
338 * @api
339 */
340#define rccResetDMA2()
341/** @} */
342
343/**
344 * @name I2C peripherals specific RCC operations
345 * @{
346 */
347/**
348 * @brief Enables the I2C1 peripheral clock.
349 * @note The @p lp parameter is ignored in this family.
350 *
351 * @param[in] lp low power enable flag
352 *
353 * @api
354 */
355#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
356
357/**
358 * @brief Disables the I2C1 peripheral clock.
359 *
360 * @api
361 */
362#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
363
364/**
365 * @brief Resets the I2C1 peripheral.
366 *
367 * @api
368 */
369#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
370
371/**
372 * @brief Enables the I2C2 peripheral clock.
373 * @note The @p lp parameter is ignored in this family.
374 *
375 * @param[in] lp low power enable flag
376 *
377 * @api
378 */
379#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
380
381/**
382 * @brief Disables the I2C2 peripheral clock.
383 *
384 * @api
385 */
386#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
387
388/**
389 * @brief Resets the I2C2 peripheral.
390 *
391 * @api
392 */
393#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
394/** @} */
395
396/**
397 * @name SPI peripherals specific RCC operations
398 * @{
399 */
400/**
401 * @brief Enables the SPI1 peripheral clock.
402 * @note The @p lp parameter is ignored in this family.
403 *
404 * @param[in] lp low power enable flag
405 *
406 * @api
407 */
408#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
409
410/**
411 * @brief Disables the SPI1 peripheral clock.
412 *
413 * @api
414 */
415#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
416
417/**
418 * @brief Resets the SPI1 peripheral.
419 *
420 * @api
421 */
422#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
423
424/**
425 * @brief Enables the SPI2 peripheral clock.
426 * @note The @p lp parameter is ignored in this family.
427 *
428 * @param[in] lp low power enable flag
429 *
430 * @api
431 */
432#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
433
434/**
435 * @brief Disables the SPI2 peripheral clock.
436 *
437 * @api
438 */
439#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
440
441/**
442 * @brief Resets the SPI2 peripheral.
443 *
444 * @api
445 */
446#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
447/** @} */
448
449/**
450 * @name TIM peripherals specific RCC operations
451 * @{
452 */
453/**
454 * @brief Enables the TIM1 peripheral clock.
455 * @note The @p lp parameter is ignored in this family.
456 *
457 * @param[in] lp low power enable flag
458 *
459 * @api
460 */
461#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
462
463/**
464 * @brief Disables the TIM1 peripheral clock.
465 *
466 * @api
467 */
468#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
469
470/**
471 * @brief Resets the TIM1 peripheral.
472 *
473 * @api
474 */
475#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
476
477/**
478 * @brief Enables the TIM2 peripheral clock.
479 * @note The @p lp parameter is ignored in this family.
480 *
481 * @param[in] lp low power enable flag
482 *
483 * @api
484 */
485#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
486
487/**
488 * @brief Disables the TIM2 peripheral clock.
489 *
490 * @api
491 */
492#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
493
494/**
495 * @brief Resets the TIM2 peripheral.
496 *
497 * @api
498 */
499#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
500
501/**
502 * @brief Enables the TIM3 peripheral clock.
503 * @note The @p lp parameter is ignored in this family.
504 *
505 * @param[in] lp low power enable flag
506 *
507 * @api
508 */
509#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
510
511/**
512 * @brief Disables the TIM3 peripheral clock.
513 *
514 * @api
515 */
516#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
517
518/**
519 * @brief Resets the TIM3 peripheral.
520 *
521 * @api
522 */
523#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
524
525/**
526 * @brief Enables the TIM6 peripheral clock.
527 * @note The @p lp parameter is ignored in this family.
528 *
529 * @param[in] lp low power enable flag
530 *
531 * @api
532 */
533#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
534
535/**
536 * @brief Disables the TIM6 peripheral clock.
537 *
538 * @api
539 */
540#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
541
542/**
543 * @brief Resets the TIM6 peripheral.
544 *
545 * @api
546 */
547#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
548
549/**
550 * @brief Enables the TIM7 peripheral clock.
551 * @note The @p lp parameter is ignored in this family.
552 *
553 * @param[in] lp low power enable flag
554 *
555 * @api
556 */
557#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
558
559/**
560 * @brief Disables the TIM7 peripheral clock.
561 *
562 * @api
563 */
564#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
565
566/**
567 * @brief Resets the TIM7 peripheral.
568 *
569 * @api
570 */
571#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
572
573/**
574 * @brief Enables the TIM14 peripheral clock.
575 * @note The @p lp parameter is ignored in this family.
576 *
577 * @param[in] lp low power enable flag
578 *
579 * @api
580 */
581#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
582
583/**
584 * @brief Disables the TIM14 peripheral clock.
585 *
586 * @api
587 */
588#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
589
590/**
591 * @brief Resets the TIM14 peripheral.
592 *
593 * @api
594 */
595#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
596
597/**
598 * @brief Enables the TIM15 peripheral clock.
599 * @note The @p lp parameter is ignored in this family.
600 *
601 * @param[in] lp low power enable flag
602 *
603 * @api
604 */
605#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
606
607/**
608 * @brief Disables the TIM15 peripheral clock.
609 *
610 * @api
611 */
612#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
613
614/**
615 * @brief Resets the TIM15 peripheral.
616 *
617 * @api
618 */
619#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
620
621/**
622 * @brief Enables the TIM16 peripheral clock.
623 * @note The @p lp parameter is ignored in this family.
624 *
625 * @param[in] lp low power enable flag
626 *
627 * @api
628 */
629#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
630
631/**
632 * @brief Disables the TIM16 peripheral clock.
633 *
634 * @api
635 */
636#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
637
638/**
639 * @brief Resets the TIM16 peripheral.
640 *
641 * @api
642 */
643#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
644
645/**
646 * @brief Enables the TIM17 peripheral clock.
647 * @note The @p lp parameter is ignored in this family.
648 *
649 * @param[in] lp low power enable flag
650 *
651 * @api
652 */
653#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
654
655/**
656 * @brief Disables the TIM17 peripheral clock.
657 *
658 * @api
659 */
660#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
661
662/**
663 * @brief Resets the TIM17 peripheral.
664 *
665 * @api
666 */
667#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
668/** @} */
669
670/**
671 * @name USART/UART peripherals specific RCC operations
672 * @{
673 */
674/**
675 * @brief Enables the USART1 peripheral clock.
676 * @note The @p lp parameter is ignored in this family.
677 *
678 * @param[in] lp low power enable flag
679 *
680 * @api
681 */
682#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
683
684/**
685 * @brief Disables the USART1 peripheral clock.
686 *
687 * @api
688 */
689#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
690
691/**
692 * @brief Resets the USART1 peripheral.
693 *
694 * @api
695 */
696#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
697
698/**
699 * @brief Enables the USART2 peripheral clock.
700 * @note The @p lp parameter is ignored in this family.
701 *
702 * @param[in] lp low power enable flag
703 *
704 * @api
705 */
706#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
707
708/**
709 * @brief Disables the USART2 peripheral clock.
710 *
711 * @api
712 */
713#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
714
715/**
716 * @brief Resets the USART2 peripheral.
717 *
718 * @api
719 */
720#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
721
722/**
723 * @brief Enables the USART3 peripheral clock.
724 * @note The @p lp parameter is ignored in this family.
725 *
726 * @param[in] lp low power enable flag
727 *
728 * @api
729 */
730#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
731
732/**
733 * @brief Disables the USART3 peripheral clock.
734 *
735 * @api
736 */
737#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
738
739/**
740 * @brief Resets the USART3 peripheral.
741 *
742 * @api
743 */
744#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
745
746/**
747 * @brief Enables the USART4 peripheral clock.
748 * @note The @p lp parameter is ignored in this family.
749 *
750 * @param[in] lp low power enable flag
751 *
752 * @api
753 */
754#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
755
756/**
757 * @brief Disables the USART4 peripheral clock.
758 *
759 * @api
760 */
761#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_USART4EN)
762
763/**
764 * @brief Resets the USART4 peripheral.
765 *
766 * @api
767 */
768#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_USART4RST)
769
770/**
771 * @brief Enables the USART5 peripheral clock.
772 * @note The @p lp parameter is ignored in this family.
773 *
774 * @param[in] lp low power enable flag
775 *
776 * @api
777 */
778#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
779
780/**
781 * @brief Disables the USART5 peripheral clock.
782 *
783 * @api
784 */
785#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_USART5EN)
786
787/**
788 * @brief Resets the USART5 peripheral.
789 *
790 * @api
791 */
792#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_USART5RST)
793
794/**
795 * @brief Enables the USART6 peripheral clock.
796 * @note The @p lp parameter is ignored in this family.
797 *
798 * @param[in] lp low power enable flag
799 *
800 * @api
801 */
802#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
803
804/**
805 * @brief Disables the USART6 peripheral clock.
806 *
807 * @api
808 */
809#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
810
811/**
812 * @brief Resets the USART6 peripheral.
813 *
814 * @api
815 */
816#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
817
818/**
819 * @brief Enables the UART7 peripheral clock.
820 *
821 * @param[in] lp low power enable flag
822 *
823 * @api
824 */
825#define rccEnableUART7(lp) rccEnableAPB2(RCC_APB2ENR_USART7EN, lp)
826
827/**
828 * @brief Disables the UART7 peripheral clock.
829 *
830 * @api
831 */
832#define rccDisableUART7() rccDisableAPB2(RCC_APB2ENR_USART7EN)
833
834/**
835 * @brief Resets the UART7 peripheral.
836 *
837 * @api
838 */
839#define rccResetUART7() rccResetAPB2(RCC_APB2RSTR_USART7RST)
840
841/**
842 * @brief Enables the UART8 peripheral clock.
843 *
844 * @param[in] lp low power enable flag
845 *
846 * @api
847 */
848#define rccEnableUART8(lp) rccEnableAPB2(RCC_APB2ENR_USART8EN, lp)
849
850/**
851 * @brief Disables the UART8 peripheral clock.
852 *
853 * @api
854 */
855#define rccDisableUART8() rccDisableAPB2(RCC_APB2ENR_USART8EN)
856
857/**
858 * @brief Resets the UART8 peripheral.
859 *
860 * @api
861 */
862#define rccResetUART8() rccResetAPB2(RCC_APB2RSTR_USART8RST)
863/** @} */
864
865/**
866 * @name USB peripherals specific RCC operations
867 * @{
868 */
869/**
870 * @brief Enables the USB peripheral clock.
871 * @note The @p lp parameter is ignored in this family.
872 *
873 * @param[in] lp low power enable flag
874 *
875 * @api
876 */
877#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
878
879/**
880 * @brief Disables the USB peripheral clock.
881 *
882 * @api
883 */
884#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
885
886/**
887 * @brief Resets the USB peripheral.
888 *
889 * @api
890 */
891#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
892/** @} */
893
894/**
895 * @name CRC peripherals specific RCC operations
896 * @{
897 */
898/**
899 * @brief Enables the CRC peripheral clock.
900 * @note The @p lp parameter is ignored in this family.
901 *
902 * @param[in] lp low power enable flag
903 *
904 * @api
905 */
906#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
907
908/**
909 * @brief Disables the CRC peripheral clock.
910 *
911 * @api
912 */
913#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
914
915/**
916 * @brief Resets the CRC peripheral.
917 *
918 * @api
919 */
920#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
921/** @} */
922
923/**
924 * @name WWDG peripherals specific RCC operations
925 * @{
926 */
927/**
928 * @brief Enables the WWDG peripheral clock.
929 * @note The @p lp parameter is ignored in this family.
930 *
931 * @param[in] lp low power enable flag
932 *
933 * @api
934 */
935#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
936
937/**
938 * @brief Disables the WWDG peripheral clock.
939 *
940 * @api
941 */
942#define rccDisableWWDG() rccDisableAPB1(RCC_APB1ENR_WWDGEN)
943
944/**
945 * @brief Resets the WWDG peripheral.
946 *
947 * @api
948 */
949#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST)
950/** @} */
951
952/*===========================================================================*/
953/* External declarations. */
954/*===========================================================================*/
955
956#ifdef __cplusplus
957extern "C" {
958#endif
959#ifdef __cplusplus
960}
961#endif
962
963#endif /* STM32_RCC_H */
964
965/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:58:51 +0100