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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_adc_lld.h
19 * @brief STM32F37x ADC subsystem low level driver header.
20 *
21 * @addtogroup ADC
22 * @{
23 */
24
25#ifndef HAL_ADC_LLD_H
26#define HAL_ADC_LLD_H
27
28#if HAL_USE_ADC || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/**
35 * @name Triggers selection
36 * @{
37 */
38#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */
39/** @} */
40
41/**
42 * @name ADC clock divider settings
43 * @{
44 */
45#define ADC_CCR_ADCPRE_DIV2 0
46#define ADC_CCR_ADCPRE_DIV4 1
47#define ADC_CCR_ADCPRE_DIV6 2
48#define ADC_CCR_ADCPRE_DIV8 3
49/** @} */
50
51/**
52 * @name Available analog channels
53 * @{
54 */
55#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
56#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
57#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
58#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
59#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
60#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
61#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
62#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
63#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
64#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
65#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
66#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
67#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
68#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
69#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
70#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
71#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
72#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
73#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */
74/** @} */
75
76/**
77 * @name Sampling rates
78 * @{
79 */
80#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
81#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
82#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
83#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
84#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
85#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
86#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
87#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
88/** @} */
89
90/**
91 * @name SDADC JCHGR bit definitions
92 * @{
93 */
94#define SDADC_JCHG_MASK (511U << 0)
95#define SDADC_JCHG(n) (1U << (n))
96/** @} */
97
98/**
99 * @name SDADC channels definitions
100 * @{
101 */
102#define SDADC_CHANNEL_0 SDADC_JCHG(0)
103#define SDADC_CHANNEL_1 SDADC_JCHG(1)
104#define SDADC_CHANNEL_2 SDADC_JCHG(2)
105#define SDADC_CHANNEL_3 SDADC_JCHG(3)
106#define SDADC_CHANNEL_4 SDADC_JCHG(4)
107#define SDADC_CHANNEL_5 SDADC_JCHG(5)
108#define SDADC_CHANNEL_6 SDADC_JCHG(6)
109#define SDADC_CHANNEL_7 SDADC_JCHG(7)
110#define SDADC_CHANNEL_8 SDADC_JCHG(8)
111#define SDADC_CHANNEL_9 SDADC_JCHG(9)
112/** @} */
113
114/*===========================================================================*/
115/* Driver pre-compile time settings. */
116/*===========================================================================*/
117
118/**
119 * @name Configuration options
120 * @{
121 */
122/**
123 * @brief ADC1 driver enable switch.
124 * @details If set to @p TRUE the support for ADC1 is included.
125 */
126#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
127#define STM32_ADC_USE_ADC1 FALSE
128#endif
129
130/**
131 * @brief SDADC1 driver enable switch.
132 * @details If set to @p TRUE the support for SDADC1 is included.
133 */
134#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
135#define STM32_ADC_USE_SDADC1 FALSE
136#endif
137
138/**
139 * @brief SDADC2 driver enable switch.
140 * @details If set to @p TRUE the support for SDADC2 is included.
141 */
142#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
143#define STM32_ADC_USE_SDADC2 FALSE
144#endif
145
146/**
147 * @brief SDADC3 driver enable switch.
148 * @details If set to @p TRUE the support for SDADC3 is included.
149 */
150#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
151#define STM32_ADC_USE_SDADC3 FALSE
152#endif
153
154/**
155 * @brief ADC1 DMA priority (0..3|lowest..highest).
156 */
157#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
158#define STM32_ADC_ADC1_DMA_PRIORITY 2
159#endif
160
161/**
162 * @brief SDADC1 DMA priority (0..3|lowest..highest).
163 */
164#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
165#define STM32_ADC_SDADC1_DMA_PRIORITY 2
166#endif
167
168/**
169 * @brief SDADC2 DMA priority (0..3|lowest..highest).
170 */
171#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
172#define STM32_ADC_SDADC2_DMA_PRIORITY 2
173#endif
174
175/**
176 * @brief SDADC3 DMA priority (0..3|lowest..highest).
177 */
178#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
179#define STM32_ADC_SDADC3_DMA_PRIORITY 2
180#endif
181
182/**
183 * @brief ADC interrupt priority level setting.
184 */
185#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
186#define STM32_ADC_ADC1_IRQ_PRIORITY 5
187#endif
188
189/**
190 * @brief ADC DMA interrupt priority level setting.
191 */
192#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
193#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
194#endif
195
196/**
197 * @brief SDADC1 interrupt priority level setting.
198 */
199#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
200#define STM32_ADC_SDADC1_IRQ_PRIORITY 5
201#endif
202
203/**
204 * @brief SDADC2 interrupt priority level setting.
205 */
206#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
207#define STM32_ADC_SDADC2_IRQ_PRIORITY 5
208#endif
209
210/**
211 * @brief SDADC3 interrupt priority level setting.
212 */
213#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
214#define STM32_ADC_SDADC3_IRQ_PRIORITY 5
215#endif
216
217/**
218 * @brief SDADC1 DMA interrupt priority level setting.
219 */
220#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
221#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5
222#endif
223
224/**
225 * @brief SDADC2 DMA interrupt priority level setting.
226 */
227#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
228#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5
229#endif
230
231/**
232 * @brief SDADC3 DMA interrupt priority level setting.
233 */
234#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
235#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5
236#endif
237/** @} */
238
239/*===========================================================================*/
240/* Derived constants and error checks. */
241/*===========================================================================*/
242
243/**
244 * @brief At least an ADC unit is in use.
245 */
246#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1
247
248/**
249 * @brief At least an SDADC unit is in use.
250 */
251#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \
252 STM32_ADC_USE_SDADC2 || \
253 STM32_ADC_USE_SDADC3)
254
255#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
256#error "ADC1 not present in the selected device"
257#endif
258
259#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
260#error "SDADC1 not present in the selected device"
261#endif
262
263#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
264#error "SDADC2 not present in the selected device"
265#endif
266
267#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
268#error "SDADC3 not present in the selected device"
269#endif
270
271#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
272#error "ADC driver activated but no ADC/SDADC peripheral assigned"
273#endif
274
275#if STM32_ADC_USE_ADC1 && \
276 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
277#error "Invalid IRQ priority assigned to ADC1"
278#endif
279
280#if STM32_ADC_USE_ADC1 && \
281 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
282#error "Invalid IRQ priority assigned to ADC1 DMA"
283#endif
284
285#if STM32_ADC_USE_ADC1 && \
286 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
287#error "Invalid DMA priority assigned to ADC1"
288#endif
289
290#if STM32_ADC_USE_SDADC1 && \
291 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY)
292#error "Invalid IRQ priority assigned to SDADC1"
293#endif
294
295#if STM32_ADC_USE_SDADC1 && \
296 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY)
297#error "Invalid IRQ priority assigned to SDADC1 DMA"
298#endif
299
300#if STM32_ADC_USE_SDADC1 && \
301 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY)
302#error "Invalid DMA priority assigned to SDADC1"
303#endif
304
305#if STM32_ADC_USE_SDADC2 && \
306 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY)
307#error "Invalid IRQ priority assigned to SDADC2"
308#endif
309
310#if STM32_ADC_USE_SDADC2 && \
311 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY)
312#error "Invalid IRQ priority assigned to SDADC2 DMA"
313#endif
314
315#if STM32_ADC_USE_SDADC2 && \
316 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY)
317#error "Invalid DMA priority assigned to SDADC2"
318#endif
319
320#if STM32_ADC_USE_SDADC3 && \
321 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY)
322#error "Invalid IRQ priority assigned to SDADC3"
323#endif
324
325#if STM32_ADC_USE_SDADC3 && \
326 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY)
327#error "Invalid IRQ priority assigned to SDADC3 DMA"
328#endif
329
330#if STM32_ADC_USE_SDADC3 && \
331 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY)
332#error "Invalid DMA priority assigned to SDADC3"
333#endif
334
335#if !defined(STM32_DMA_REQUIRED)
336#define STM32_DMA_REQUIRED
337#endif
338
339/*===========================================================================*/
340/* Driver data structures and types. */
341/*===========================================================================*/
342
343/**
344 * @brief ADC sample data type.
345 */
346typedef uint16_t adcsample_t;
347
348/**
349 * @brief Channels number in a conversion group.
350 */
351typedef uint16_t adc_channels_num_t;
352
353/**
354 * @brief Possible ADC failure causes.
355 * @note Error codes are architecture dependent and should not relied
356 * upon.
357 */
358typedef enum {
359 ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
360 ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
361 ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */
362} adcerror_t;
363
364/*===========================================================================*/
365/* Driver macros. */
366/*===========================================================================*/
367
368#if (STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC) || defined(__DOXYGEN__)
369/**
370 * @brief Low level fields of the ADC driver structure.
371 */
372#define adc_lld_driver_fields \
373 /* Pointer to the ADCx registers block.*/ \
374 ADC_TypeDef *adc; \
375 /* Pointer to the SDADCx registers block.*/ \
376 SDADC_TypeDef *sdadc; \
377 /* Pointer to associated DMA channel.*/ \
378 const stm32_dma_stream_t *dmastp; \
379 /* DMA mode bit mask.*/ \
380 uint32_t dmamode
381
382/**
383 * @brief Low level fields of the ADC configuration structure.
384 */
385#define adc_lld_config_fields \
386 /* SDADC CR1 register initialization data.*/ \
387 uint32_t cr1; \
388 /* SDADC CONFxR registers initialization data.*/ \
389 uint32_t confxr[3]
390
391/**
392 * @brief Low level fields of the ADC configuration structure.
393 */
394#define adc_lld_configuration_group_fields \
395 union { \
396 struct { \
397 /* ADC CR1 register initialization data. \
398 NOTE: All the required bits must be defined into this field except \
399 @p ADC_CR1_SCAN that is enforced inside the driver.*/ \
400 uint32_t cr1; \
401 /* ADC CR2 register initialization data. \
402 NOTE: All the required bits must be defined into this field except \
403 @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
404 enforced inside the driver.*/ \
405 uint32_t cr2; \
406 /* ADC LTR register initialization data.*/ \
407 uint32_t ltr; \
408 /* ADC HTR register initialization data.*/ \
409 uint32_t htr; \
410 /* ADC SMPRx registers initialization data.*/ \
411 uint32_t smpr[2]; \
412 /* ADC SQRx register initialization data.*/ \
413 uint32_t sqr[3]; \
414 } adc; \
415 struct { \
416 /* SDADC CR2 register initialization data. \
417 NOTE: Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL \
418 and @p SDADC_CR2_JEXTEN can be specified in this field.*/ \
419 uint32_t cr2; \
420 /* SDADC JCHGR register initialization data.*/ \
421 uint32_t jchgr; \
422 /* SDADC CONFCHxR registers initialization data.*/ \
423 uint32_t confchr[2]; \
424 } sdadc; \
425 } u
426
427#elif STM32_ADC_USE_ADC
428#define adc_lld_driver_fields \
429 /* Pointer to the ADCx registers block.*/ \
430 ADC_TypeDef *adc; \
431 /* Pointer to associated DMA channel.*/ \
432 const stm32_dma_stream_t *dmastp; \
433 /* DMA mode bit mask.*/ \
434 uint32_t dmamode
435
436#define adc_lld_config_fields \
437 /* Dummy configuration, it is not needed.*/ \
438 uint32_t dummy
439
440#define adc_lld_configuration_group_fields \
441 union { \
442 struct { \
443 /* ADC CR1 register initialization data. \
444 NOTE: All the required bits must be defined into this field except \
445 @p ADC_CR1_SCAN that is enforced inside the driver.*/ \
446 uint32_t cr1; \
447 /* ADC CR2 register initialization data. \
448 NOTE: All the required bits must be defined into this field except \
449 @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
450 enforced inside the driver.*/ \
451 uint32_t cr2; \
452 /* ADC LTR register initialization data.*/ \
453 uint32_t ltr; \
454 /* ADC HTR register initialization data.*/ \
455 uint32_t htr; \
456 /* ADC SMPRx registers initialization data.*/ \
457 uint32_t smpr[2]; \
458 /* ADC SQRx register initialization data.*/ \
459 uint32_t sqr[3]; \
460 } adc; \
461 } u
462
463#elif STM32_ADC_USE_SDADC
464#define adc_lld_driver_fields \
465 /* Pointer to the SDADCx registers block.*/ \
466 SDADC_TypeDef *sdadc; \
467 /* Pointer to associated DMA channel.*/ \
468 const stm32_dma_stream_t *dmastp; \
469 /* DMA mode bit mask.*/ \
470 uint32_t dmamode
471
472#define adc_lld_config_fields \
473 /* SDADC CR1 register initialization data.*/ \
474 uint32_t cr1; \
475 /* SDADC CONFxR registers initialization data.*/ \
476 uint32_t confxr[3]
477
478#define adc_lld_configuration_group_fields \
479 union { \
480 struct { \
481 /* SDADC CR2 register initialization data. \
482 NOTE: Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL \
483 and @p SDADC_CR2_JEXTEN can be specified in this field.*/ \
484 uint32_t cr2; \
485 /* SDADC JCHGR register initialization data.*/ \
486 uint32_t jchgr; \
487 /* SDADC CONFCHxR registers initialization data.*/ \
488 uint32_t confchr[2]; \
489 } sdadc; \
490 } u
491
492#endif
493
494/**
495 * @name Sequences building helper macros for ADC
496 * @{
497 */
498/**
499 * @brief Number of channels in a conversion sequence.
500 */
501#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
502#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
503#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
504#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
505#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
506
507#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
508#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
509#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
510#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
511#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
512#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
513
514#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
515#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
516#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
517#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
518#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
519#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
520/** @} */
521
522/**
523 * @name Sampling rate settings helper macros
524 * @{
525 */
526#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
527#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
528#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
529#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
530#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
531#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
532#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
533#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
534#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
535#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
536
537#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
538#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
539#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
540#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
541#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
542#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
543#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
544 sampling time. */
545#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
546 sampling time. */
547#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
548/** @} */
549
550/**
551 * @name Sequences building helper macros for SDADC
552 * @{
553 */
554#define SDADC_JCHGR_CH(n) (1U << (n))
555/** @} */
556
557/**
558 * @name Channel configuration number helper macros for SDADC
559 * @{
560 */
561#define SDADC_CONFCHR1_CH0(n) ((n) << 0)
562#define SDADC_CONFCHR1_CH1(n) ((n) << 4)
563#define SDADC_CONFCHR1_CH2(n) ((n) << 8)
564#define SDADC_CONFCHR1_CH3(n) ((n) << 12)
565#define SDADC_CONFCHR1_CH4(n) ((n) << 16)
566#define SDADC_CONFCHR1_CH5(n) ((n) << 20)
567#define SDADC_CONFCHR1_CH6(n) ((n) << 24)
568#define SDADC_CONFCHR1_CH7(n) ((n) << 28)
569#define SDADC_CONFCHR2_CH8(n) ((n) << 0)
570/** @} */
571
572/**
573 * @name Configuration registers helper macros for SDADC
574 * @{
575 */
576#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0)
577#define SDADC_CONFR_OFFSET(n) ((n) << 0)
578#define SDADC_CONFR_GAIN_MASK (7U << 20)
579#define SDADC_CONFR_GAIN_1X (0U << 20)
580#define SDADC_CONFR_GAIN_2X (1U << 20)
581#define SDADC_CONFR_GAIN_4X (2U << 20)
582#define SDADC_CONFR_GAIN_8X (3U << 20)
583#define SDADC_CONFR_GAIN_16X (4U << 20)
584#define SDADC_CONFR_GAIN_32X (5U << 20)
585#define SDADC_CONFR_GAIN_0P5X (7U << 20)
586#define SDADC_CONFR_SE_MASK (3U << 26)
587#define SDADC_CONFR_SE_DIFF (0U << 26)
588#define SDADC_CONFR_SE_OFFSET (1U << 26)
589#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26)
590#define SDADC_CONFR_COMMON_MASK (3U << 30)
591#define SDADC_CONFR_COMMON_VSSSD (0U << 30)
592#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30)
593#define SDADC_CONFR_COMMON_VDDSD (2U << 30)
594/** @} */
595
596/*===========================================================================*/
597/* External declarations. */
598/*===========================================================================*/
599
600#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
601extern ADCDriver ADCD1;
602#endif
603
604#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
605extern ADCDriver SDADCD1;
606#endif
607
608#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
609extern ADCDriver SDADCD2;
610#endif
611
612#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
613extern ADCDriver SDADCD3;
614#endif
615
616#ifdef __cplusplus
617extern "C" {
618#endif
619 void adc_lld_init(void);
620 void adc_lld_start(ADCDriver *adcp);
621 void adc_lld_stop(ADCDriver *adcp);
622 void adc_lld_start_conversion(ADCDriver *adcp);
623 void adc_lld_stop_conversion(ADCDriver *adcp);
624 void adcSTM32Calibrate(ADCDriver *adcdp);
625#if STM32_ADC_USE_ADC
626 void adcSTM32EnableTSVREFE(void);
627 void adcSTM32DisableTSVREFE(void);
628 void adcSTM32EnableVBATE(void);
629 void adcSTM32DisableVBATE(void);
630#endif /* STM32_ADC_USE_ADC */
631#ifdef __cplusplus
632}
633#endif
634
635#endif /* HAL_USE_ADC */
636
637#endif /* HAL_ADC_LLD_H */
638
639/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 10:19:28 +0100