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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c740
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h639
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.c216
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.h1011
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/platform.mk47
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.c255
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.h243
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_rcc.h1020
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_registry.h572
9 files changed, 4743 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
new file mode 100644
index 000000000..0631b5e48
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
@@ -0,0 +1,740 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_adc_lld.c
19 * @brief STM32F37x ADC subsystem low level driver source.
20 *
21 * @addtogroup ADC
22 * @{
23 */
24
25#include "hal.h"
26
27#if HAL_USE_ADC || defined(__DOXYGEN__)
28
29/*===========================================================================*/
30/* Driver local definitions. */
31/*===========================================================================*/
32
33#define SDADC_FORBIDDEN_CR1_FLAGS (SDADC_CR1_INIT | SDADC_CR1_RDMAEN | \
34 SDADC_CR1_RSYNC | SDADC_CR1_JSYNC | \
35 SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE | \
36 SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE)
37
38#define SDADC_ENFORCED_CR1_FLAGS (SDADC_CR1_JDMAEN | SDADC_CR1_JOVRIE)
39
40#define SDADC_FORBIDDEN_CR2_FLAGS (SDADC_CR2_RSWSTART | \
41 SDADC_CR2_RCONT | \
42 SDADC_CR2_RCH | \
43 SDADC_CR2_JCONT | \
44 SDADC_CR2_STARTCALIB | \
45 SDADC_CR2_CALIBCNT)
46
47/*===========================================================================*/
48/* Driver exported variables. */
49/*===========================================================================*/
50
51/** @brief ADC1 driver identifier.*/
52#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
53ADCDriver ADCD1;
54#endif
55
56/** @brief SDADC1 driver identifier.*/
57#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
58ADCDriver SDADCD1;
59#endif
60
61/** @brief SDADC2 driver identifier.*/
62#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
63ADCDriver SDADCD2;
64#endif
65
66/** @brief SDADC3 driver identifier.*/
67#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
68ADCDriver SDADCD3;
69#endif
70
71/*===========================================================================*/
72/* Driver local variables and types. */
73/*===========================================================================*/
74
75static const ADCConfig adc_lld_default_config = {
76#if STM32_ADC_USE_SDADC
77 0,
78 {
79 0,
80 0,
81 0
82 }
83#else /* !STM32_ADC_USE_SDADC */
84 0
85#endif /* !STM32_ADC_USE_SDADC */
86};
87
88/*===========================================================================*/
89/* Driver local functions. */
90/*===========================================================================*/
91
92/**
93 * @brief Stops, reconfigures and restarts an ADC/SDADC.
94 *
95 * @param[in] adcp pointer to the @p ADCDriver object
96 */
97static void adc_lld_reconfig(ADCDriver *adcp) {
98
99#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
100 if (adcp->adc != NULL)
101#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
102#if STM32_ADC_USE_ADC
103 {
104 /* ADC initial setup, starting the analog part here in order to reduce
105 the latency when starting a conversion.*/
106 uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
107 adcp->adc->CR2 = cr2;
108 adcp->adc->CR1 = 0;
109 adcp->adc->CR2 = cr2 | ADC_CR2_ADON;
110
111 }
112#endif /* STM32_ADC_USE_ADC */
113#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
114 else if (adcp->sdadc != NULL)
115#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
116#if STM32_ADC_USE_SDADC
117 {
118 /* SDADC initial setup, starting the analog part here in order to reduce
119 the latency when starting a conversion.*/
120 adcp->sdadc->CR2 = 0;
121 adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
122 ~SDADC_FORBIDDEN_CR1_FLAGS;
123 adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) |
124 adcp->config->confxr[0];
125 adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) |
126 adcp->config->confxr[1];
127 adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) |
128 adcp->config->confxr[2];
129 adcp->sdadc->CR2 = SDADC_CR2_ADON;
130 }
131#endif /* STM32_ADC_USE_SDADC */
132#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
133else {
134 osalDbgAssert(FALSE, "invalid state");
135 }
136#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
137}
138
139/**
140 * @brief ADC DMA ISR service routine.
141 *
142 * @param[in] adcp pointer to the @p ADCDriver object
143 * @param[in] flags pre-shifted content of the ISR register
144 *
145 * @notapi
146 */
147static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
148
149 /* DMA errors handling.*/
150 if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
151 /* DMA, this could help only if the DMA tries to access an unmapped
152 address space or violates alignment rules.*/
153 _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
154 }
155 else {
156 /* It is possible that the conversion group has already be reset by the
157 ADC error handler, in this case this interrupt is spurious.*/
158 if (adcp->grpp != NULL) {
159 if ((flags & STM32_DMA_ISR_TCIF) != 0) {
160 /* Transfer complete processing.*/
161 _adc_isr_full_code(adcp);
162 }
163 else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
164 /* Half transfer processing.*/
165 _adc_isr_half_code(adcp);
166 }
167 }
168 }
169}
170
171#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
172/**
173 * @brief ADC ISR service routine.
174 *
175 * @param[in] adcp pointer to the @p ADCDriver object
176 * @param[in] sr content of the ISR register
177 *
178 * @notapi
179 */
180static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) {
181
182 /* It could be a spurious interrupt caused by overflows after DMA disabling,
183 just ignore it in this case.*/
184 if (adcp->grpp != NULL) {
185 if (sr & ADC_SR_AWD) {
186 /* Analog watchdog error.*/
187 _adc_isr_error_code(adcp, ADC_ERR_AWD1);
188 }
189 }
190}
191#endif /* STM32_ADC_USE_ADC */
192
193#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
194/**
195 * @brief ADC ISR service routine.
196 *
197 * @param[in] adcp pointer to the @p ADCDriver object
198 * @param[in] isr content of the ISR register
199 *
200 * @notapi
201 */
202static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
203
204 /* It could be a spurious interrupt caused by overflows after DMA disabling,
205 just ignore it in this case.*/
206 if (adcp->grpp != NULL) {
207 /* Note, an overflow may occur after the conversion ended before the driver
208 is able to stop the ADC, this is why the DMA channel is checked too.*/
209 if ((isr & SDADC_ISR_JOVRF) &&
210 (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
211 /* ADC overflow condition, this could happen only if the DMA is unable
212 to read data fast enough.*/
213 _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
214 }
215 }
216}
217#endif /* STM32_ADC_USE_SDADC */
218
219/*===========================================================================*/
220/* Driver interrupt handlers. */
221/*===========================================================================*/
222
223#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
224/**
225 * @brief ADC1 interrupt handler.
226 *
227 * @isr
228 */
229OSAL_IRQ_HANDLER(Vector88) {
230 uint32_t sr;
231
232 OSAL_IRQ_PROLOGUE();
233
234 sr = ADC1->SR;
235 ADC1->SR = 0;
236 adc_lld_serve_interrupt(&ADCD1, sr);
237
238 OSAL_IRQ_EPILOGUE();
239}
240#endif /* STM32_ADC_USE_ADC1 */
241
242#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__)
243/**
244 * @brief SDADC1 interrupt handler.
245 *
246 * @isr
247 */
248OSAL_IRQ_HANDLER(Vector134) {
249 uint32_t isr;
250
251 OSAL_IRQ_PROLOGUE();
252
253 isr = SDADC1->ISR;
254 SDADC1->CLRISR = isr;
255 sdadc_lld_serve_interrupt(&SDADCD1, isr);
256
257 OSAL_IRQ_EPILOGUE();
258}
259#endif /* STM32_ADC_USE_SDADC1 */
260
261#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__)
262/**
263 * @brief SDADC2 interrupt handler.
264 *
265 * @isr
266 */
267OSAL_IRQ_HANDLER(Vector138) {
268 uint32_t isr;
269
270 OSAL_IRQ_PROLOGUE();
271
272 isr = SDADC2->ISR;
273 SDADC2->CLRISR = isr;
274 sdadc_lld_serve_interrupt(&SDADCD2, isr);
275
276 OSAL_IRQ_EPILOGUE();
277}
278#endif /* STM32_ADC_USE_SDADC2 */
279
280#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__)
281/**
282 * @brief SDADC3 interrupt handler.
283 *
284 * @isr
285 */
286OSAL_IRQ_HANDLER(Vector13C) {
287 uint32_t isr;
288
289 OSAL_IRQ_PROLOGUE();
290
291 isr = SDADC3->ISR;
292 SDADC3->CLRISR = isr;
293 sdadc_lld_serve_interrupt(&SDADCD3, isr);
294
295 OSAL_IRQ_EPILOGUE();
296}
297#endif /* STM32_ADC_USE_SDADC3 */
298
299/*===========================================================================*/
300/* Driver exported functions. */
301/*===========================================================================*/
302
303/**
304 * @brief Low level ADC driver initialization.
305 *
306 * @notapi
307 */
308void adc_lld_init(void) {
309
310#if STM32_ADC_USE_ADC1
311 /* Driver initialization.*/
312 adcObjectInit(&ADCD1);
313 ADCD1.adc = ADC1;
314#if STM32_ADC_USE_SDADC
315 ADCD1.sdadc = NULL;
316#endif
317 ADCD1.dmastp = NULL;
318 ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
319 STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
320 STM32_DMA_CR_DIR_P2M |
321 STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
322 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
323 STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
324 nvicEnableVector(ADC1_IRQn, STM32_ADC_ADC1_IRQ_PRIORITY);
325#endif
326
327#if STM32_ADC_USE_SDADC1
328 /* Driver initialization.*/
329 adcObjectInit(&SDADCD1);
330#if STM32_ADC_USE_ADC
331 SDADCD1.adc = NULL;
332#endif
333 SDADCD1.sdadc = SDADC1;
334 SDADCD1.dmastp = NULL;
335 SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
336 STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
337 STM32_DMA_CR_DIR_P2M |
338 STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
339 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
340 STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
341 nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY);
342#endif
343
344#if STM32_ADC_USE_SDADC2
345 /* Driver initialization.*/
346 adcObjectInit(&SDADCD2);
347#if STM32_ADC_USE_ADC
348 SDADCD2.adc = NULL;
349#endif
350 SDADCD2.sdadc = SDADC2;
351 SDADCD2.dmastp = NULL;
352 SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
353 STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
354 STM32_DMA_CR_DIR_P2M |
355 STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
356 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
357 STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
358 nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY);
359#endif
360
361#if STM32_ADC_USE_SDADC3
362 /* Driver initialization.*/
363 adcObjectInit(&SDADCD3);
364#if STM32_ADC_USE_ADC
365 SDADCD3.adc = NULL;
366#endif
367 SDADCD3.sdadc = SDADC3;
368 SDADCD3.dmastp = NULL;
369 SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
370 STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
371 STM32_DMA_CR_DIR_P2M |
372 STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
373 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
374 STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
375 nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY);
376#endif
377}
378
379/**
380 * @brief Configures and activates the ADC peripheral.
381 *
382 * @param[in] adcp pointer to the @p ADCDriver object
383 *
384 * @notapi
385 */
386void adc_lld_start(ADCDriver *adcp) {
387
388 if (adcp->config == NULL)
389 adcp->config = &adc_lld_default_config;
390
391 /* If in stopped state then enables the ADC and DMA clocks.*/
392 if (adcp->state == ADC_STOP) {
393#if STM32_ADC_USE_ADC1
394 if (&ADCD1 == adcp) {
395 adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
396 STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
397 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
398 (void *)adcp);
399 osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
400
401 dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
402 rccEnableADC1(true);
403 }
404#endif /* STM32_ADC_USE_ADC1 */
405
406#if STM32_ADC_USE_SDADC1
407 if (&SDADCD1 == adcp) {
408 adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 3),
409 STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,
410 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
411 (void *)adcp);
412 osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
413
414 dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);
415 rccEnableSDADC1(true);
416 PWR->CR |= PWR_CR_SDADC1EN;
417 adcp->sdadc->CR2 = 0;
418 adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
419 ~SDADC_FORBIDDEN_CR1_FLAGS;
420 adcp->sdadc->CR2 = SDADC_CR2_ADON;
421 }
422#endif /* STM32_ADC_USE_SDADC1 */
423
424#if STM32_ADC_USE_SDADC2
425 if (&SDADCD2 == adcp) {
426 adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 4),
427 STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,
428 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
429 (void *)adcp);
430 osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
431
432 dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
433 rccEnableSDADC2(true);
434 PWR->CR |= PWR_CR_SDADC2EN;
435 adcp->sdadc->CR2 = 0;
436 adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
437 ~SDADC_FORBIDDEN_CR1_FLAGS;
438 adcp->sdadc->CR2 = SDADC_CR2_ADON;
439 }
440#endif /* STM32_ADC_USE_SDADC2 */
441
442#if STM32_ADC_USE_SDADC3
443 if (&SDADCD3 == adcp) {
444 adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(2, 5),
445 STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,
446 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
447 (void *)adcp);
448 osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
449
450 dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
451 rccEnableSDADC3(true);
452 PWR->CR |= PWR_CR_SDADC3EN;
453 adcp->sdadc->CR2 = 0;
454 adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
455 ~SDADC_FORBIDDEN_CR1_FLAGS;
456 adcp->sdadc->CR2 = SDADC_CR2_ADON;
457 }
458#endif /* STM32_ADC_USE_SDADC3 */
459 }
460
461 adc_lld_reconfig(adcp);
462}
463
464/**
465 * @brief Deactivates the ADC peripheral.
466 *
467 * @param[in] adcp pointer to the @p ADCDriver object
468 *
469 * @notapi
470 */
471void adc_lld_stop(ADCDriver *adcp) {
472
473 /* If in ready state then disables the ADC clock.*/
474 if (adcp->state == ADC_READY) {
475 dmaStreamFreeI(adcp->dmastp);
476 adcp->dmastp = NULL;
477
478#if STM32_ADC_USE_ADC1
479 if (&ADCD1 == adcp) {
480 adcp->adc->CR1 = 0;
481 adcp->adc->CR2 = 0;
482 rccDisableADC1();
483 }
484#endif
485
486#if STM32_ADC_USE_SDADC1
487 if (&SDADCD1 == adcp) {
488 adcp->sdadc->CR1 = 0;
489 adcp->sdadc->CR2 = 0;
490 rccDisableSDADC1();
491 PWR->CR &= ~PWR_CR_SDADC1EN;
492 }
493#endif
494
495#if STM32_ADC_USE_SDADC2
496 if (&SDADCD2 == adcp) {
497 adcp->sdadc->CR1 = 0;
498 adcp->sdadc->CR2 = 0;
499 rccDisableSDADC2();
500 PWR->CR &= ~PWR_CR_SDADC2EN;
501 }
502#endif
503
504#if STM32_ADC_USE_SDADC3
505 if (&SDADCD3 == adcp) {
506 adcp->sdadc->CR1 = 0;
507 adcp->sdadc->CR2 = 0;
508 rccDisableSDADC3();
509 PWR->CR &= ~PWR_CR_SDADC3EN;
510 }
511#endif
512 }
513}
514
515/**
516 * @brief Starts an ADC conversion.
517 *
518 * @param[in] adcp pointer to the @p ADCDriver object
519 *
520 * @notapi
521 */
522void adc_lld_start_conversion(ADCDriver *adcp) {
523 uint32_t mode;
524 const ADCConversionGroup* grpp = adcp->grpp;
525
526 /* DMA setup.*/
527 mode = adcp->dmamode;
528 if (grpp->circular) {
529 mode |= STM32_DMA_CR_CIRC;
530 if (adcp->depth > 1) {
531 /* If circular buffer depth > 1, then the half transfer interrupt
532 is enabled in order to allow streaming processing.*/
533 mode |= STM32_DMA_CR_HTIE;
534 }
535 }
536 dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
537 dmaStreamSetTransactionSize(adcp->dmastp,
538 (uint32_t)grpp->num_channels *
539 (uint32_t)adcp->depth);
540 dmaStreamSetMode(adcp->dmastp, mode);
541 dmaStreamEnable(adcp->dmastp);
542
543#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
544 if (adcp->adc != NULL)
545#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
546#if STM32_ADC_USE_ADC
547 {
548 uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE;
549 cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
550 if ((cr2 & ADC_CR2_SWSTART) != 0)
551 cr2 |= ADC_CR2_CONT;
552 adcp->adc->CR2 = cr2;
553
554 /* ADC setup.*/
555 adcp->adc->SR = 0;
556 adcp->adc->LTR = grpp->u.adc.ltr;
557 adcp->adc->HTR = grpp->u.adc.htr;
558 adcp->adc->SMPR1 = grpp->u.adc.smpr[0];
559 adcp->adc->SMPR2 = grpp->u.adc.smpr[1];
560 adcp->adc->SQR1 = grpp->u.adc.sqr[0] |
561 ADC_SQR1_NUM_CH(grpp->num_channels);
562 adcp->adc->SQR2 = grpp->u.adc.sqr[1];
563 adcp->adc->SQR3 = grpp->u.adc.sqr[2];
564
565 /* ADC conversion start, the start is performed using the method
566 specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
567 adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN;
568 adcp->adc->CR2 = adcp->adc->CR2; /* Triggers the conversion start.*/
569 }
570#endif /* STM32_ADC_USE_ADC */
571#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
572 else if (adcp->sdadc != NULL)
573#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
574#if STM32_ADC_USE_SDADC
575 {
576 uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) |
577 SDADC_CR2_ADON;
578 if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0)
579 cr2 |= SDADC_CR2_JCONT;
580
581 /* Entering initialization mode.*/
582 adcp->sdadc->CR1 |= SDADC_CR1_INIT;
583 while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0)
584 ;
585
586 /* SDADC setup.*/
587 adcp->sdadc->JCHGR = grpp->u.sdadc.jchgr;
588 adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
589 adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
590
591 /* SDADC trigger modes, this write must be performed when
592 SDADC_CR1_INIT=1.*/
593 adcp->sdadc->CR2 = cr2;
594
595 /* Leaving initialization mode.*/
596 adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
597
598 /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
599 written after SDADC_CR1_INIT has been set to zero. Just a write is
600 performed, any other bit is ingore if not in initialization mode.*/
601 adcp->sdadc->CR2 = cr2;
602 }
603#endif /* STM32_ADC_USE_SDADC */
604#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
605 else {
606 osalDbgAssert(FALSE, "invalid state");
607 }
608#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
609}
610
611/**
612 * @brief Stops an ongoing conversion.
613 *
614 * @param[in] adcp pointer to the @p ADCDriver object
615 *
616 * @notapi
617 */
618void adc_lld_stop_conversion(ADCDriver *adcp) {
619
620 /* Disabling the associated DMA stream.*/
621 dmaStreamDisable(adcp->dmastp);
622
623 /* Stopping and restarting the whole ADC, apparently the only way to stop
624 a conversion.*/
625 adc_lld_reconfig(adcp);
626}
627
628/**
629 * @brief Calibrates an ADC unit.
630 * @note The calibration must be performed after calling @p adcStart().
631 * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT
632 * has been
633 *
634 * @param[in] adcp pointer to the @p ADCDriver object
635 *
636 * @api
637 */
638void adcSTM32Calibrate(ADCDriver *adcp) {
639
640 osalDbgAssert((adcp->state == ADC_READY) ||
641 (adcp->state == ADC_COMPLETE) ||
642 (adcp->state == ADC_ERROR),
643 "not ready");
644
645#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
646 if (adcp->adc != NULL)
647#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
648#if STM32_ADC_USE_ADC
649 {
650 /* Resetting calibration just to be safe.*/
651 ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
652 while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
653 ;
654
655 /* Calibration.*/
656 ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
657 while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
658 ;
659 }
660#endif /* STM32_ADC_USE_ADC */
661#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
662 else if (adcp->sdadc != NULL)
663#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
664#if STM32_ADC_USE_SDADC
665 {
666 /* Selecting a full calibration in three steps.*/
667 adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) |
668 SDADC_CR2_CALIBCNT_1;
669
670 /* Calibration.*/
671 adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB;
672 while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0)
673 ;
674
675 /* Clearing the EOCALF flag.*/
676 adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
677 }
678#endif /* STM32_ADC_USE_SDADC */
679#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
680 else {
681 osalDbgAssert(FALSE, "invalid state");
682 }
683#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
684}
685
686#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
687/**
688 * @brief Enables the TSVREFE bit.
689 * @details The TSVREFE bit is required in order to sample the internal
690 * temperature sensor and internal reference voltage.
691 * @note This is an STM32-only functionality.
692 *
693 * @api
694 */
695void adcSTM32EnableTSVREFE(void) {
696
697 ADC1->CR2 |= ADC_CR2_TSVREFE;
698}
699
700/**
701 * @brief Disables the TSVREFE bit.
702 * @details The TSVREFE bit is required in order to sample the internal
703 * temperature sensor and internal reference voltage.
704 * @note This is an STM32-only functionality.
705 *
706 * @api
707 */
708void adcSTM32DisableTSVREFE(void) {
709
710 ADC1->CR2 &= ~ADC_CR2_TSVREFE;
711}
712
713/**
714 * @brief Enables the VBATE bit.
715 * @details The VBATE bit is required in order to sample the VBAT channel.
716 * @note This is an STM32-only functionality.
717 *
718 * @api
719 */
720void adcSTM32EnableVBATE(void) {
721
722 SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
723}
724
725/**
726 * @brief Disables the VBATE bit.
727 * @details The VBATE bit is required in order to sample the VBAT channel.
728 * @note This is an STM32-only functionality.
729 *
730 * @api
731 */
732void adcSTM32DisableVBATE(void) {
733
734 SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT;
735}
736#endif /* STM32_ADC_USE_ADC */
737
738#endif /* HAL_USE_ADC */
739
740/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h
new file mode 100644
index 000000000..dceeaba71
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h
@@ -0,0 +1,639 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_adc_lld.h
19 * @brief STM32F37x ADC subsystem low level driver header.
20 *
21 * @addtogroup ADC
22 * @{
23 */
24
25#ifndef HAL_ADC_LLD_H
26#define HAL_ADC_LLD_H
27
28#if HAL_USE_ADC || defined(__DOXYGEN__)
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/**
35 * @name Triggers selection
36 * @{
37 */
38#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */
39/** @} */
40
41/**
42 * @name ADC clock divider settings
43 * @{
44 */
45#define ADC_CCR_ADCPRE_DIV2 0
46#define ADC_CCR_ADCPRE_DIV4 1
47#define ADC_CCR_ADCPRE_DIV6 2
48#define ADC_CCR_ADCPRE_DIV8 3
49/** @} */
50
51/**
52 * @name Available analog channels
53 * @{
54 */
55#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
56#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
57#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
58#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
59#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
60#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
61#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
62#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
63#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
64#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
65#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
66#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
67#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
68#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
69#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
70#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
71#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
72#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
73#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */
74/** @} */
75
76/**
77 * @name Sampling rates
78 * @{
79 */
80#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
81#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
82#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
83#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
84#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
85#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
86#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
87#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
88/** @} */
89
90/**
91 * @name SDADC JCHGR bit definitions
92 * @{
93 */
94#define SDADC_JCHG_MASK (511U << 0)
95#define SDADC_JCHG(n) (1U << (n))
96/** @} */
97
98/**
99 * @name SDADC channels definitions
100 * @{
101 */
102#define SDADC_CHANNEL_0 SDADC_JCHG(0)
103#define SDADC_CHANNEL_1 SDADC_JCHG(1)
104#define SDADC_CHANNEL_2 SDADC_JCHG(2)
105#define SDADC_CHANNEL_3 SDADC_JCHG(3)
106#define SDADC_CHANNEL_4 SDADC_JCHG(4)
107#define SDADC_CHANNEL_5 SDADC_JCHG(5)
108#define SDADC_CHANNEL_6 SDADC_JCHG(6)
109#define SDADC_CHANNEL_7 SDADC_JCHG(7)
110#define SDADC_CHANNEL_8 SDADC_JCHG(8)
111#define SDADC_CHANNEL_9 SDADC_JCHG(9)
112/** @} */
113
114/*===========================================================================*/
115/* Driver pre-compile time settings. */
116/*===========================================================================*/
117
118/**
119 * @name Configuration options
120 * @{
121 */
122/**
123 * @brief ADC1 driver enable switch.
124 * @details If set to @p TRUE the support for ADC1 is included.
125 */
126#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
127#define STM32_ADC_USE_ADC1 FALSE
128#endif
129
130/**
131 * @brief SDADC1 driver enable switch.
132 * @details If set to @p TRUE the support for SDADC1 is included.
133 */
134#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__)
135#define STM32_ADC_USE_SDADC1 FALSE
136#endif
137
138/**
139 * @brief SDADC2 driver enable switch.
140 * @details If set to @p TRUE the support for SDADC2 is included.
141 */
142#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__)
143#define STM32_ADC_USE_SDADC2 FALSE
144#endif
145
146/**
147 * @brief SDADC3 driver enable switch.
148 * @details If set to @p TRUE the support for SDADC3 is included.
149 */
150#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__)
151#define STM32_ADC_USE_SDADC3 FALSE
152#endif
153
154/**
155 * @brief ADC1 DMA priority (0..3|lowest..highest).
156 */
157#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
158#define STM32_ADC_ADC1_DMA_PRIORITY 2
159#endif
160
161/**
162 * @brief SDADC1 DMA priority (0..3|lowest..highest).
163 */
164#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
165#define STM32_ADC_SDADC1_DMA_PRIORITY 2
166#endif
167
168/**
169 * @brief SDADC2 DMA priority (0..3|lowest..highest).
170 */
171#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
172#define STM32_ADC_SDADC2_DMA_PRIORITY 2
173#endif
174
175/**
176 * @brief SDADC3 DMA priority (0..3|lowest..highest).
177 */
178#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
179#define STM32_ADC_SDADC3_DMA_PRIORITY 2
180#endif
181
182/**
183 * @brief ADC interrupt priority level setting.
184 */
185#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
186#define STM32_ADC_ADC1_IRQ_PRIORITY 5
187#endif
188
189/**
190 * @brief ADC DMA interrupt priority level setting.
191 */
192#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
193#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
194#endif
195
196/**
197 * @brief SDADC1 interrupt priority level setting.
198 */
199#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
200#define STM32_ADC_SDADC1_IRQ_PRIORITY 5
201#endif
202
203/**
204 * @brief SDADC2 interrupt priority level setting.
205 */
206#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__)
207#define STM32_ADC_SDADC2_IRQ_PRIORITY 5
208#endif
209
210/**
211 * @brief SDADC3 interrupt priority level setting.
212 */
213#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
214#define STM32_ADC_SDADC3_IRQ_PRIORITY 5
215#endif
216
217/**
218 * @brief SDADC1 DMA interrupt priority level setting.
219 */
220#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
221#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5
222#endif
223
224/**
225 * @brief SDADC2 DMA interrupt priority level setting.
226 */
227#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
228#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5
229#endif
230
231/**
232 * @brief SDADC3 DMA interrupt priority level setting.
233 */
234#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
235#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5
236#endif
237/** @} */
238
239/*===========================================================================*/
240/* Derived constants and error checks. */
241/*===========================================================================*/
242
243/**
244 * @brief At least an ADC unit is in use.
245 */
246#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1
247
248/**
249 * @brief At least an SDADC unit is in use.
250 */
251#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \
252 STM32_ADC_USE_SDADC2 || \
253 STM32_ADC_USE_SDADC3)
254
255#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
256#error "ADC1 not present in the selected device"
257#endif
258
259#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1
260#error "SDADC1 not present in the selected device"
261#endif
262
263#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2
264#error "SDADC2 not present in the selected device"
265#endif
266
267#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3
268#error "SDADC3 not present in the selected device"
269#endif
270
271#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
272#error "ADC driver activated but no ADC/SDADC peripheral assigned"
273#endif
274
275#if STM32_ADC_USE_ADC1 && \
276 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
277#error "Invalid IRQ priority assigned to ADC1"
278#endif
279
280#if STM32_ADC_USE_ADC1 && \
281 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
282#error "Invalid IRQ priority assigned to ADC1 DMA"
283#endif
284
285#if STM32_ADC_USE_ADC1 && \
286 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
287#error "Invalid DMA priority assigned to ADC1"
288#endif
289
290#if STM32_ADC_USE_SDADC1 && \
291 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY)
292#error "Invalid IRQ priority assigned to SDADC1"
293#endif
294
295#if STM32_ADC_USE_SDADC1 && \
296 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY)
297#error "Invalid IRQ priority assigned to SDADC1 DMA"
298#endif
299
300#if STM32_ADC_USE_SDADC1 && \
301 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY)
302#error "Invalid DMA priority assigned to SDADC1"
303#endif
304
305#if STM32_ADC_USE_SDADC2 && \
306 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY)
307#error "Invalid IRQ priority assigned to SDADC2"
308#endif
309
310#if STM32_ADC_USE_SDADC2 && \
311 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY)
312#error "Invalid IRQ priority assigned to SDADC2 DMA"
313#endif
314
315#if STM32_ADC_USE_SDADC2 && \
316 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY)
317#error "Invalid DMA priority assigned to SDADC2"
318#endif
319
320#if STM32_ADC_USE_SDADC3 && \
321 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY)
322#error "Invalid IRQ priority assigned to SDADC3"
323#endif
324
325#if STM32_ADC_USE_SDADC3 && \
326 !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY)
327#error "Invalid IRQ priority assigned to SDADC3 DMA"
328#endif
329
330#if STM32_ADC_USE_SDADC3 && \
331 !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY)
332#error "Invalid DMA priority assigned to SDADC3"
333#endif
334
335#if !defined(STM32_DMA_REQUIRED)
336#define STM32_DMA_REQUIRED
337#endif
338
339/*===========================================================================*/
340/* Driver data structures and types. */
341/*===========================================================================*/
342
343/**
344 * @brief ADC sample data type.
345 */
346typedef uint16_t adcsample_t;
347
348/**
349 * @brief Channels number in a conversion group.
350 */
351typedef uint16_t adc_channels_num_t;
352
353/**
354 * @brief Possible ADC failure causes.
355 * @note Error codes are architecture dependent and should not relied
356 * upon.
357 */
358typedef enum {
359 ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
360 ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
361 ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */
362} adcerror_t;
363
364/*===========================================================================*/
365/* Driver macros. */
366/*===========================================================================*/
367
368#if (STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC) || defined(__DOXYGEN__)
369/**
370 * @brief Low level fields of the ADC driver structure.
371 */
372#define adc_lld_driver_fields \
373 /* Pointer to the ADCx registers block.*/ \
374 ADC_TypeDef *adc; \
375 /* Pointer to the SDADCx registers block.*/ \
376 SDADC_TypeDef *sdadc; \
377 /* Pointer to associated DMA channel.*/ \
378 const stm32_dma_stream_t *dmastp; \
379 /* DMA mode bit mask.*/ \
380 uint32_t dmamode
381
382/**
383 * @brief Low level fields of the ADC configuration structure.
384 */
385#define adc_lld_config_fields \
386 /* SDADC CR1 register initialization data.*/ \
387 uint32_t cr1; \
388 /* SDADC CONFxR registers initialization data.*/ \
389 uint32_t confxr[3]
390
391/**
392 * @brief Low level fields of the ADC configuration structure.
393 */
394#define adc_lld_configuration_group_fields \
395 union { \
396 struct { \
397 /* ADC CR1 register initialization data. \
398 NOTE: All the required bits must be defined into this field except \
399 @p ADC_CR1_SCAN that is enforced inside the driver.*/ \
400 uint32_t cr1; \
401 /* ADC CR2 register initialization data. \
402 NOTE: All the required bits must be defined into this field except \
403 @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
404 enforced inside the driver.*/ \
405 uint32_t cr2; \
406 /* ADC LTR register initialization data.*/ \
407 uint32_t ltr; \
408 /* ADC HTR register initialization data.*/ \
409 uint32_t htr; \
410 /* ADC SMPRx registers initialization data.*/ \
411 uint32_t smpr[2]; \
412 /* ADC SQRx register initialization data.*/ \
413 uint32_t sqr[3]; \
414 } adc; \
415 struct { \
416 /* SDADC CR2 register initialization data. \
417 NOTE: Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL \
418 and @p SDADC_CR2_JEXTEN can be specified in this field.*/ \
419 uint32_t cr2; \
420 /* SDADC JCHGR register initialization data.*/ \
421 uint32_t jchgr; \
422 /* SDADC CONFCHxR registers initialization data.*/ \
423 uint32_t confchr[2]; \
424 } sdadc; \
425 } u
426
427#elif STM32_ADC_USE_ADC
428#define adc_lld_driver_fields \
429 /* Pointer to the ADCx registers block.*/ \
430 ADC_TypeDef *adc; \
431 /* Pointer to associated DMA channel.*/ \
432 const stm32_dma_stream_t *dmastp; \
433 /* DMA mode bit mask.*/ \
434 uint32_t dmamode
435
436#define adc_lld_config_fields \
437 /* Dummy configuration, it is not needed.*/ \
438 uint32_t dummy
439
440#define adc_lld_configuration_group_fields \
441 union { \
442 struct { \
443 /* ADC CR1 register initialization data. \
444 NOTE: All the required bits must be defined into this field except \
445 @p ADC_CR1_SCAN that is enforced inside the driver.*/ \
446 uint32_t cr1; \
447 /* ADC CR2 register initialization data. \
448 NOTE: All the required bits must be defined into this field except \
449 @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \
450 enforced inside the driver.*/ \
451 uint32_t cr2; \
452 /* ADC LTR register initialization data.*/ \
453 uint32_t ltr; \
454 /* ADC HTR register initialization data.*/ \
455 uint32_t htr; \
456 /* ADC SMPRx registers initialization data.*/ \
457 uint32_t smpr[2]; \
458 /* ADC SQRx register initialization data.*/ \
459 uint32_t sqr[3]; \
460 } adc; \
461 } u
462
463#elif STM32_ADC_USE_SDADC
464#define adc_lld_driver_fields \
465 /* Pointer to the SDADCx registers block.*/ \
466 SDADC_TypeDef *sdadc; \
467 /* Pointer to associated DMA channel.*/ \
468 const stm32_dma_stream_t *dmastp; \
469 /* DMA mode bit mask.*/ \
470 uint32_t dmamode
471
472#define adc_lld_config_fields \
473 /* SDADC CR1 register initialization data.*/ \
474 uint32_t cr1; \
475 /* SDADC CONFxR registers initialization data.*/ \
476 uint32_t confxr[3]
477
478#define adc_lld_configuration_group_fields \
479 union { \
480 struct { \
481 /* SDADC CR2 register initialization data. \
482 NOTE: Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL \
483 and @p SDADC_CR2_JEXTEN can be specified in this field.*/ \
484 uint32_t cr2; \
485 /* SDADC JCHGR register initialization data.*/ \
486 uint32_t jchgr; \
487 /* SDADC CONFCHxR registers initialization data.*/ \
488 uint32_t confchr[2]; \
489 } sdadc; \
490 } u
491
492#endif
493
494/**
495 * @name Sequences building helper macros for ADC
496 * @{
497 */
498/**
499 * @brief Number of channels in a conversion sequence.
500 */
501#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
502#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
503#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
504#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
505#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
506
507#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
508#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
509#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
510#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
511#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
512#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
513
514#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
515#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
516#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
517#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
518#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
519#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
520/** @} */
521
522/**
523 * @name Sampling rate settings helper macros
524 * @{
525 */
526#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
527#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
528#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
529#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
530#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
531#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
532#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
533#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
534#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
535#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
536
537#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
538#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
539#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
540#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
541#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
542#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
543#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
544 sampling time. */
545#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
546 sampling time. */
547#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
548/** @} */
549
550/**
551 * @name Sequences building helper macros for SDADC
552 * @{
553 */
554#define SDADC_JCHGR_CH(n) (1U << (n))
555/** @} */
556
557/**
558 * @name Channel configuration number helper macros for SDADC
559 * @{
560 */
561#define SDADC_CONFCHR1_CH0(n) ((n) << 0)
562#define SDADC_CONFCHR1_CH1(n) ((n) << 4)
563#define SDADC_CONFCHR1_CH2(n) ((n) << 8)
564#define SDADC_CONFCHR1_CH3(n) ((n) << 12)
565#define SDADC_CONFCHR1_CH4(n) ((n) << 16)
566#define SDADC_CONFCHR1_CH5(n) ((n) << 20)
567#define SDADC_CONFCHR1_CH6(n) ((n) << 24)
568#define SDADC_CONFCHR1_CH7(n) ((n) << 28)
569#define SDADC_CONFCHR2_CH8(n) ((n) << 0)
570/** @} */
571
572/**
573 * @name Configuration registers helper macros for SDADC
574 * @{
575 */
576#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0)
577#define SDADC_CONFR_OFFSET(n) ((n) << 0)
578#define SDADC_CONFR_GAIN_MASK (7U << 20)
579#define SDADC_CONFR_GAIN_1X (0U << 20)
580#define SDADC_CONFR_GAIN_2X (1U << 20)
581#define SDADC_CONFR_GAIN_4X (2U << 20)
582#define SDADC_CONFR_GAIN_8X (3U << 20)
583#define SDADC_CONFR_GAIN_16X (4U << 20)
584#define SDADC_CONFR_GAIN_32X (5U << 20)
585#define SDADC_CONFR_GAIN_0P5X (7U << 20)
586#define SDADC_CONFR_SE_MASK (3U << 26)
587#define SDADC_CONFR_SE_DIFF (0U << 26)
588#define SDADC_CONFR_SE_OFFSET (1U << 26)
589#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26)
590#define SDADC_CONFR_COMMON_MASK (3U << 30)
591#define SDADC_CONFR_COMMON_VSSSD (0U << 30)
592#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30)
593#define SDADC_CONFR_COMMON_VDDSD (2U << 30)
594/** @} */
595
596/*===========================================================================*/
597/* External declarations. */
598/*===========================================================================*/
599
600#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
601extern ADCDriver ADCD1;
602#endif
603
604#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__)
605extern ADCDriver SDADCD1;
606#endif
607
608#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__)
609extern ADCDriver SDADCD2;
610#endif
611
612#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__)
613extern ADCDriver SDADCD3;
614#endif
615
616#ifdef __cplusplus
617extern "C" {
618#endif
619 void adc_lld_init(void);
620 void adc_lld_start(ADCDriver *adcp);
621 void adc_lld_stop(ADCDriver *adcp);
622 void adc_lld_start_conversion(ADCDriver *adcp);
623 void adc_lld_stop_conversion(ADCDriver *adcp);
624 void adcSTM32Calibrate(ADCDriver *adcdp);
625#if STM32_ADC_USE_ADC
626 void adcSTM32EnableTSVREFE(void);
627 void adcSTM32DisableTSVREFE(void);
628 void adcSTM32EnableVBATE(void);
629 void adcSTM32DisableVBATE(void);
630#endif /* STM32_ADC_USE_ADC */
631#ifdef __cplusplus
632}
633#endif
634
635#endif /* HAL_USE_ADC */
636
637#endif /* HAL_ADC_LLD_H */
638
639/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.c
new file mode 100644
index 000000000..725de2f6a
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -0,0 +1,216 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_lld.c
19 * @brief STM32F37x HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/**
36 * @brief CMSIS system core clock variable.
37 * @note It is declared in system_stm32f3xx.h.
38 */
39uint32_t SystemCoreClock = STM32_HCLK;
40
41/*===========================================================================*/
42/* Driver local variables and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver local functions. */
47/*===========================================================================*/
48
49/**
50 * @brief Initializes the backup domain.
51 * @note WARNING! Changing clock source impossible without resetting
52 * of the whole BKP domain.
53 */
54static void hal_lld_backup_domain_init(void) {
55
56 /* Backup domain access enabled and left open.*/
57 PWR->CR |= PWR_CR_DBP;
58
59 /* Reset BKP domain if different clock source selected.*/
60 if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
61 /* Backup domain reset.*/
62 RCC->BDCR = RCC_BDCR_BDRST;
63 RCC->BDCR = 0;
64 }
65
66 /* If enabled then the LSE is started.*/
67#if STM32_LSE_ENABLED
68#if defined(STM32_LSE_BYPASS)
69 /* LSE Bypass.*/
70 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
71#else
72 /* No LSE Bypass.*/
73 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
74#endif
75 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
76 ; /* Waits until LSE is stable. */
77#endif
78
79#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
80 /* If the backup domain hasn't been initialized yet then proceed with
81 initialization.*/
82 if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
83 /* Selects clock source.*/
84 RCC->BDCR |= STM32_RTCSEL;
85
86 /* RTC clock enabled.*/
87 RCC->BDCR |= RCC_BDCR_RTCEN;
88 }
89#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
90}
91
92/*===========================================================================*/
93/* Driver interrupt handlers. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Driver exported functions. */
98/*===========================================================================*/
99
100/**
101 * @brief Low level HAL driver initialization.
102 *
103 * @notapi
104 */
105void hal_lld_init(void) {
106
107 /* Reset of all peripherals.
108 Note, GPIOs are not reset because initialized before this point in
109 board files.*/
110 rccResetAHB(~STM32_GPIO_EN_MASK);
111 rccResetAPB1(0xFFFFFFFF);
112 rccResetAPB2(0xFFFFFFFF);
113
114 /* PWR clock enabled.*/
115 rccEnablePWRInterface(true);
116
117 /* Initializes the backup domain.*/
118 hal_lld_backup_domain_init();
119
120 /* DMA subsystems initialization.*/
121#if defined(STM32_DMA_REQUIRED)
122 dmaInit();
123#endif
124
125 /* IRQ subsystem initialization.*/
126 irqInit();
127
128 /* Programmable voltage detector enable.*/
129#if STM32_PVD_ENABLE
130 PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
131#endif /* STM32_PVD_ENABLE */
132
133 /* SYSCFG clock enabled here because it is a multi-functional unit shared
134 among multiple drivers.*/
135 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
136}
137
138/**
139 * @brief STM32 clocks and PLL initialization.
140 * @note All the involved constants come from the file @p board.h.
141 * @note This function should be invoked just after the system reset.
142 *
143 * @special
144 */
145void stm32_clock_init(void) {
146
147#if !STM32_NO_INIT
148 /* HSI setup, it enforces the reset situation in order to handle possible
149 problems with JTAG probes and re-initializations.*/
150 RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
151 while (!(RCC->CR & RCC_CR_HSIRDY))
152 ; /* Wait until HSI is stable. */
153
154 /* HSI is selected as new source without touching the other fields in
155 CFGR. Clearing the register has to be postponed after HSI is the
156 new source.*/
157 RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
158 while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
159 ; /* Wait until HSI is selected. */
160
161 /* Registers finally cleared to reset values.*/
162 RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
163 RCC->CFGR = 0; /* CFGR reset value. */
164
165#if STM32_HSE_ENABLED
166 /* HSE activation.*/
167#if defined(STM32_HSE_BYPASS)
168 /* HSE Bypass.*/
169 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
170#else
171 /* No HSE Bypass.*/
172 RCC->CR |= RCC_CR_HSEON;
173#endif
174 while (!(RCC->CR & RCC_CR_HSERDY))
175 ; /* Waits until HSE is stable. */
176#endif
177
178#if STM32_LSI_ENABLED
179 /* LSI activation.*/
180 RCC->CSR |= RCC_CSR_LSION;
181 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
182 ; /* Waits until LSI is stable. */
183#endif
184
185 /* Clock settings.*/
186 RCC->CFGR = STM32_SDPRE | STM32_MCOSEL | STM32_USBPRE |
187 STM32_PLLMUL | STM32_PLLSRC | STM32_ADCPRE |
188 STM32_PPRE1 | STM32_PPRE2 | STM32_HPRE;
189 RCC->CFGR2 = STM32_PREDIV;
190 RCC->CFGR3 = STM32_USART3SW | STM32_USART2SW | STM32_I2C2SW |
191 STM32_I2C1SW | STM32_USART1SW;
192
193#if STM32_ACTIVATE_PLL
194 /* PLL activation.*/
195 RCC->CR |= RCC_CR_PLLON;
196 while (!(RCC->CR & RCC_CR_PLLRDY))
197 ; /* Waits until PLL is stable. */
198#endif
199
200 /* Flash setup and final clock selection. */
201 FLASH->ACR = STM32_FLASHBITS;
202 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
203 (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
204 }
205
206 /* Switching to the configured clock source if it is different from HSI.*/
207#if (STM32_SW != STM32_SW_HSI)
208 /* Switches clock source.*/
209 RCC->CFGR |= STM32_SW;
210 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
211 ; /* Waits selection complete. */
212#endif
213#endif /* !STM32_NO_INIT */
214}
215
216/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.h
new file mode 100644
index 000000000..5c2296662
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/hal_lld.h
@@ -0,0 +1,1011 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_lld.h
19 * @brief STM32F37x HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F373xC for Analog & DSP devices.
30 * - STM32F378xx for Analog & DSP devices.
31 * .
32 *
33 * @addtogroup HAL
34 * @{
35 */
36
37#ifndef HAL_LLD_H
38#define HAL_LLD_H
39
40/*===========================================================================*/
41/* Driver constants. */
42/*===========================================================================*/
43
44/**
45 * @name Platform identification macros
46 * @{
47 */
48#if defined(STM32F373xC) || defined(__DOXYGEN__)
49#define PLATFORM_NAME "STM32F373xC Analog & DSP"
50
51#elif defined(STM32F378xx)
52#define PLATFORM_NAME "STM32F378xx Analog & DSP"
53
54#else
55#error "STM32F7x device not specified"
56#endif
57
58/**
59 * @brief Sub-family identifier.
60 */
61#if !defined(STM32F37X) || defined(__DOXYGEN__)
62#define STM32F37X
63#endif
64/** @} */
65
66/**
67 * @name Absolute Maximum Ratings
68 * @{
69 */
70/**
71 * @brief Maximum system clock frequency.
72 */
73#define STM32_SYSCLK_MAX 72000000
74
75/**
76 * @brief Maximum HSE clock frequency.
77 */
78#define STM32_HSECLK_MAX 32000000
79
80/**
81 * @brief Minimum HSE clock frequency.
82 */
83#define STM32_HSECLK_MIN 1000000
84
85/**
86 * @brief Maximum LSE clock frequency.
87 */
88#define STM32_LSECLK_MAX 1000000
89
90/**
91 * @brief Minimum LSE clock frequency.
92 */
93#define STM32_LSECLK_MIN 32768
94
95/**
96 * @brief Maximum PLLs input clock frequency.
97 */
98#define STM32_PLLIN_MAX 24000000
99
100/**
101 * @brief Minimum PLLs input clock frequency.
102 */
103#define STM32_PLLIN_MIN 1000000
104
105/**
106 * @brief Maximum PLL output clock frequency.
107 */
108#define STM32_PLLOUT_MAX 72000000
109
110/**
111 * @brief Minimum PLL output clock frequency.
112 */
113#define STM32_PLLOUT_MIN 16000000
114
115/**
116 * @brief Maximum APB1 clock frequency.
117 */
118#define STM32_PCLK1_MAX 36000000
119
120/**
121 * @brief Maximum APB2 clock frequency.
122 */
123#define STM32_PCLK2_MAX 72000000
124
125/**
126 * @brief Maximum ADC clock frequency.
127 */
128#define STM32_ADCCLK_MAX 14000000
129
130/**
131 * @brief Minimum ADC clock frequency.
132 */
133#define STM32_ADCCLK_MIN 600000
134
135/**
136 * @brief Maximum SDADC clock frequency in fast mode.
137 */
138#define STM32_SDADCCLK_FAST_MAX 6000000
139
140/**
141 * @brief Maximum SDADC clock frequency in slow mode.
142 */
143#define STM32_SDADCCLK_SLOW_MAX 1500000
144
145/**
146 * @brief Minimum SDADC clock frequency.
147 */
148#define STM32_SDADCCLK_MIN 500000
149/** @} */
150
151/**
152 * @name Internal clock sources
153 * @{
154 */
155#define STM32_HSICLK 8000000 /**< High speed internal clock. */
156#define STM32_LSICLK 40000 /**< Low speed internal clock. */
157/** @} */
158
159/**
160 * @name PWR_CR register bits definitions
161 * @{
162 */
163#define STM32_PLS_MASK (7U << 5) /**< PLS bits mask. */
164#define STM32_PLS_LEV0 (0U << 5) /**< PVD level 0. */
165#define STM32_PLS_LEV1 (1U << 5) /**< PVD level 1. */
166#define STM32_PLS_LEV2 (2U << 5) /**< PVD level 2. */
167#define STM32_PLS_LEV3 (3U << 5) /**< PVD level 3. */
168#define STM32_PLS_LEV4 (4U << 5) /**< PVD level 4. */
169#define STM32_PLS_LEV5 (5U << 5) /**< PVD level 5. */
170#define STM32_PLS_LEV6 (6U << 5) /**< PVD level 6. */
171#define STM32_PLS_LEV7 (7U << 5) /**< PVD level 7. */
172/** @} */
173
174/**
175 * @name RCC_CFGR register bits definitions
176 * @{
177 */
178#define STM32_SW_HSI (0U << 0) /**< SYSCLK source is HSI. */
179#define STM32_SW_HSE (1U << 0) /**< SYSCLK source is HSE. */
180#define STM32_SW_PLL (2U << 0) /**< SYSCLK source is PLL. */
181
182#define STM32_HPRE_DIV1 (0U << 4) /**< SYSCLK divided by 1. */
183#define STM32_HPRE_DIV2 (8u << 4) /**< SYSCLK divided by 2. */
184#define STM32_HPRE_DIV4 (9U << 4) /**< SYSCLK divided by 4. */
185#define STM32_HPRE_DIV8 (10U << 4) /**< SYSCLK divided by 8. */
186#define STM32_HPRE_DIV16 (11U << 4) /**< SYSCLK divided by 16. */
187#define STM32_HPRE_DIV64 (12U << 4) /**< SYSCLK divided by 64. */
188#define STM32_HPRE_DIV128 (13U << 4) /**< SYSCLK divided by 128. */
189#define STM32_HPRE_DIV256 (14U << 4) /**< SYSCLK divided by 256. */
190#define STM32_HPRE_DIV512 (15U << 4) /**< SYSCLK divided by 512. */
191
192#define STM32_PPRE1_DIV1 (0U << 8) /**< HCLK divided by 1. */
193#define STM32_PPRE1_DIV2 (4U << 8) /**< HCLK divided by 2. */
194#define STM32_PPRE1_DIV4 (5U << 8) /**< HCLK divided by 4. */
195#define STM32_PPRE1_DIV8 (6U << 8) /**< HCLK divided by 8. */
196#define STM32_PPRE1_DIV16 (7U << 8) /**< HCLK divided by 16. */
197
198#define STM32_PPRE2_DIV1 (0U << 11) /**< HCLK divided by 1. */
199#define STM32_PPRE2_DIV2 (4U << 11) /**< HCLK divided by 2. */
200#define STM32_PPRE2_DIV4 (5U << 11) /**< HCLK divided by 4. */
201#define STM32_PPRE2_DIV8 (6U << 11) /**< HCLK divided by 8. */
202#define STM32_PPRE2_DIV16 (7U << 11) /**< HCLK divided by 16. */
203
204#define STM32_ADCPRE_DIV2 (0U << 14) /**< PPRE2 divided by 2. */
205#define STM32_ADCPRE_DIV4 (1U << 14) /**< PPRE2 divided by 4. */
206#define STM32_ADCPRE_DIV6 (2U << 14) /**< PPRE2 divided by 6. */
207#define STM32_ADCPRE_DIV8 (3U << 14) /**< PPRE2 divided by 8. */
208
209#define STM32_PLLSRC_HSI (0U << 16) /**< PLL clock source is HSI/2. */
210#define STM32_PLLSRC_HSE (1U << 16) /**< PLL clock source is
211 HSE/PREDIV. */
212
213#define STM32_USBPRE_DIV1P5 (0U << 22) /**< USB clock is PLLCLK/1.5. */
214#define STM32_USBPRE_DIV1 (1U << 22) /**< USB clock is PLLCLK/1. */
215
216#define STM32_MCOSEL_NOCLOCK (0U << 24) /**< No clock on MCO pin. */
217#define STM32_MCOSEL_LSI (2U << 24) /**< LSI clock on MCO pin. */
218#define STM32_MCOSEL_LSE (3U << 24) /**< LSE clock on MCO pin. */
219#define STM32_MCOSEL_SYSCLK (4U << 24) /**< SYSCLK on MCO pin. */
220#define STM32_MCOSEL_HSI (5U << 24) /**< HSI clock on MCO pin. */
221#define STM32_MCOSEL_HSE (6U << 24) /**< HSE clock on MCO pin. */
222#define STM32_MCOSEL_PLLDIV2 (7U << 24) /**< PLL/2 clock on MCO pin. */
223
224#define STM32_SDPRE_DIV2 (16U << 27) /**< SYSCLK divided by 2. */
225#define STM32_SDPRE_DIV4 (17U << 27) /**< SYSCLK divided by 4. */
226#define STM32_SDPRE_DIV6 (18U << 27) /**< SYSCLK divided by 6. */
227#define STM32_SDPRE_DIV8 (19U << 27) /**< SYSCLK divided by 8. */
228#define STM32_SDPRE_DIV10 (20U << 27) /**< SYSCLK divided by 10. */
229#define STM32_SDPRE_DIV12 (21U << 27) /**< SYSCLK divided by 12. */
230#define STM32_SDPRE_DIV14 (22U << 27) /**< SYSCLK divided by 14. */
231#define STM32_SDPRE_DIV16 (23U << 27) /**< SYSCLK divided by 16. */
232#define STM32_SDPRE_DIV20 (24U << 27) /**< SYSCLK divided by 20. */
233#define STM32_SDPRE_DIV24 (25U << 27) /**< SYSCLK divided by 24. */
234#define STM32_SDPRE_DIV28 (26U << 27) /**< SYSCLK divided by 28. */
235#define STM32_SDPRE_DIV32 (27U << 27) /**< SYSCLK divided by 32. */
236#define STM32_SDPRE_DIV36 (28U << 27) /**< SYSCLK divided by 36. */
237#define STM32_SDPRE_DIV40 (29U << 27) /**< SYSCLK divided by 40. */
238#define STM32_SDPRE_DIV44 (30U << 27) /**< SYSCLK divided by 44. */
239#define STM32_SDPRE_DIV48 (31U << 27) /**< SYSCLK divided by 48. */
240/** @} */
241
242/**
243 * @name RCC_BDCR register bits definitions
244 * @{
245 */
246#define STM32_RTCSEL_MASK (3U << 8) /**< RTC clock source mask. */
247#define STM32_RTCSEL_NOCLOCK (0U << 8) /**< No clock. */
248#define STM32_RTCSEL_LSE (1U << 8) /**< LSE used as RTC clock. */
249#define STM32_RTCSEL_LSI (2U << 8) /**< LSI used as RTC clock. */
250#define STM32_RTCSEL_HSEDIV (3U << 8) /**< HSE divided by 32 used as
251 RTC clock. */
252/** @} */
253
254/**
255 * @name RCC_CFGR2 register bits definitions
256 * @{
257 */
258#define STM32_PREDIV_MASK (15U << 0) /**< PREDIV divisor mask. */
259/** @} */
260
261/**
262 * @name RCC_CFGR3 register bits definitions
263 * @{
264 */
265#define STM32_USART1SW_MASK (3U << 0) /**< USART1 clock source mask. */
266#define STM32_USART1SW_PCLK (0U << 0) /**< USART1 clock is PCLK. */
267#define STM32_USART1SW_SYSCLK (1U << 0) /**< USART1 clock is SYSCLK. */
268#define STM32_USART1SW_LSE (2U << 0) /**< USART1 clock is LSE. */
269#define STM32_USART1SW_HSI (3U << 0) /**< USART1 clock is HSI. */
270#define STM32_I2C1SW_MASK (1U << 4) /**< I2C1 clock source mask. */
271#define STM32_I2C1SW_HSI (0U << 4) /**< I2C1 clock is HSI. */
272#define STM32_I2C1SW_SYSCLK (1U << 4) /**< I2C1 clock is SYSCLK. */
273#define STM32_I2C2SW_MASK (1U << 5) /**< I2C2 clock source mask. */
274#define STM32_I2C2SW_HSI (0U << 5) /**< I2C2 clock is HSI. */
275#define STM32_I2C2SW_SYSCLK (1U << 5) /**< I2C2 clock is SYSCLK. */
276#define STM32_USART2SW_MASK (3U << 16) /**< USART2 clock source mask. */
277#define STM32_USART2SW_PCLK (0U << 16) /**< USART2 clock is PCLK. */
278#define STM32_USART2SW_SYSCLK (1U << 16) /**< USART2 clock is SYSCLK. */
279#define STM32_USART2SW_LSE (2U << 16) /**< USART2 clock is LSE. */
280#define STM32_USART2SW_HSI (3U << 16) /**< USART2 clock is HSI. */
281#define STM32_USART3SW_MASK (3U << 18) /**< USART3 clock source mask. */
282#define STM32_USART3SW_PCLK (0U << 18) /**< USART3 clock is PCLK. */
283#define STM32_USART3SW_SYSCLK (1U << 18) /**< USART3 clock is SYSCLK. */
284#define STM32_USART3SW_LSE (2U << 18) /**< USART3 clock is LSE. */
285#define STM32_USART3SW_HSI (3U << 18) /**< USART3 clock is HSI. */
286/** @} */
287
288/*===========================================================================*/
289/* Driver pre-compile time settings. */
290/*===========================================================================*/
291
292/**
293 * @name Configuration options
294 * @{
295 */
296/**
297 * @brief Disables the PWR/RCC initialization in the HAL.
298 */
299#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
300#define STM32_NO_INIT FALSE
301#endif
302
303/**
304 * @brief Enables or disables the programmable voltage detector.
305 */
306#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
307#define STM32_PVD_ENABLE FALSE
308#endif
309
310/**
311 * @brief Sets voltage level for programmable voltage detector.
312 */
313#if !defined(STM32_PLS) || defined(__DOXYGEN__)
314#define STM32_PLS STM32_PLS_LEV0
315#endif
316
317/**
318 * @brief Enables or disables the HSI clock source.
319 */
320#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
321#define STM32_HSI_ENABLED TRUE
322#endif
323
324/**
325 * @brief Enables or disables the LSI clock source.
326 */
327#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
328#define STM32_LSI_ENABLED TRUE
329#endif
330
331/**
332 * @brief Enables or disables the HSE clock source.
333 */
334#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
335#define STM32_HSE_ENABLED TRUE
336#endif
337
338/**
339 * @brief Enables or disables the LSE clock source.
340 */
341#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
342#define STM32_LSE_ENABLED FALSE
343#endif
344
345/**
346 * @brief Main clock source selection.
347 * @note If the selected clock source is not the PLL then the PLL is not
348 * initialized and started.
349 * @note The default value is calculated for a 72MHz system clock from
350 * a 8MHz crystal using the PLL.
351 */
352#if !defined(STM32_SW) || defined(__DOXYGEN__)
353#define STM32_SW STM32_SW_PLL
354#endif
355
356/**
357 * @brief Clock source for the PLL.
358 * @note This setting has only effect if the PLL is selected as the
359 * system clock source.
360 * @note The default value is calculated for a 72MHz system clock from
361 * a 8MHz crystal using the PLL.
362 */
363#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
364#define STM32_PLLSRC STM32_PLLSRC_HSE
365#endif
366
367/**
368 * @brief Crystal PLL pre-divider.
369 * @note This setting has only effect if the PLL is selected as the
370 * system clock source.
371 * @note The default value is calculated for a 72MHz system clock from
372 * a 8MHz crystal using the PLL.
373 */
374#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
375#define STM32_PREDIV_VALUE 1
376#endif
377
378/**
379 * @brief PLL multiplier value.
380 * @note The allowed range is 2...16.
381 * @note The default value is calculated for a 72MHz system clock from
382 * a 8MHz crystal using the PLL.
383 */
384#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
385#define STM32_PLLMUL_VALUE 9
386#endif
387
388/**
389 * @brief AHB prescaler value.
390 * @note The default value is calculated for a 72MHz system clock from
391 * a 8MHz crystal using the PLL.
392 */
393#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
394#define STM32_HPRE STM32_HPRE_DIV1
395#endif
396
397/**
398 * @brief APB1 prescaler value.
399 */
400#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
401#define STM32_PPRE1 STM32_PPRE1_DIV2
402#endif
403
404/**
405 * @brief APB2 prescaler value.
406 */
407#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
408#define STM32_PPRE2 STM32_PPRE2_DIV2
409#endif
410
411/**
412 * @brief MCO pin setting.
413 */
414#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
415#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
416#endif
417
418/**
419 * @brief ADC prescaler value.
420 */
421#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
422#define STM32_ADCPRE STM32_ADCPRE_DIV4
423#endif
424
425/**
426 * @brief SDADC prescaler value.
427 */
428#if !defined(STM32_SDPRE) || defined(__DOXYGEN__)
429#define STM32_SDPRE STM32_SDPRE_DIV12
430#endif
431
432/**
433 * @brief USART1 clock source.
434 */
435#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
436#define STM32_USART1SW STM32_USART1SW_PCLK
437#endif
438
439/**
440 * @brief USART2 clock source.
441 */
442#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
443#define STM32_USART2SW STM32_USART2SW_PCLK
444#endif
445
446/**
447 * @brief USART3 clock source.
448 */
449#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
450#define STM32_USART3SW STM32_USART3SW_PCLK
451#endif
452
453/**
454 * @brief I2C1 clock source.
455 */
456#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
457#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
458#endif
459
460/**
461 * @brief I2C2 clock source.
462 */
463#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
464#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
465#endif
466
467/**
468 * @brief RTC clock source.
469 */
470#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
471#define STM32_RTCSEL STM32_RTCSEL_LSI
472#endif
473
474/**
475 * @brief USB clock setting.
476 */
477#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
478#define STM32_USB_CLOCK_REQUIRED TRUE
479#endif
480
481/**
482 * @brief USB prescaler initialization.
483 */
484#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
485#define STM32_USBPRE STM32_USBPRE_DIV1P5
486#endif
487/** @} */
488
489/*===========================================================================*/
490/* Derived constants and error checks. */
491/*===========================================================================*/
492
493/*
494 * Configuration-related checks.
495 */
496#if !defined(STM32F37x_MCUCONF)
497#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined"
498#endif
499
500/*
501 * HSI related checks.
502 */
503#if STM32_HSI_ENABLED
504#else /* !STM32_HSI_ENABLED */
505
506#if STM32_SW == STM32_SW_HSI
507#error "HSI not enabled, required by STM32_SW"
508#endif
509
510#if STM32_USART1SW == STM32_USART1SW_HSI
511#error "HSI not enabled, required by STM32_USART1SW"
512#endif
513
514#if STM32_USART2SW == STM32_USART2SW_HSI
515#error "HSI not enabled, required by STM32_USART2SW"
516#endif
517
518#if STM32_USART3SW == STM32_USART3SW_HSI
519#error "HSI not enabled, required by STM32_USART3SW"
520#endif
521
522#if STM32_I2C1SW == STM32_I2C1SW_HSI
523#error "HSI not enabled, required by STM32_I2C1SW"
524#endif
525
526#if STM32_I2C2SW == STM32_I2C2SW_HSI
527#error "HSI not enabled, required by STM32_I2C2SW"
528#endif
529
530#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
531#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
532#endif
533
534#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
535 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
536 (STM32_PLLSRC == STM32_PLLSRC_HSI))
537#error "HSI not enabled, required by STM32_MCOSEL"
538#endif
539
540#endif /* !STM32_HSI_ENABLED */
541
542/*
543 * HSE related checks.
544 */
545#if STM32_HSE_ENABLED
546
547#if STM32_HSECLK == 0
548#error "HSE frequency not defined"
549#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
550#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
551#endif
552
553#else /* !STM32_HSE_ENABLED */
554
555#if STM32_SW == STM32_SW_HSE
556#error "HSE not enabled, required by STM32_SW"
557#endif
558
559#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
560#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
561#endif
562
563#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
564 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
565 (STM32_PLLSRC == STM32_PLLSRC_HSE))
566#error "HSE not enabled, required by STM32_MCOSEL"
567#endif
568
569#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
570#error "HSE not enabled, required by STM32_RTCSEL"
571#endif
572
573#endif /* !STM32_HSE_ENABLED */
574
575/*
576 * LSI related checks.
577 */
578#if STM32_LSI_ENABLED
579#else /* !STM32_LSI_ENABLED */
580
581#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
582#error "LSI not enabled, required by STM32_RTCSEL"
583#endif
584
585#endif /* !STM32_LSI_ENABLED */
586
587/*
588 * LSE related checks.
589 */
590#if STM32_LSE_ENABLED
591
592#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
593#error "STM32_LSECLK not defined"
594#endif
595
596#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
597#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
598#endif
599
600#if !defined(STM32_LSEDRV)
601#error "STM32_LSEDRV not defined"
602#endif
603
604#if (STM32_LSEDRV >> 3) > 3
605#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
606#endif
607
608#if STM32_USART1SW == STM32_USART1SW_LSE
609#error "LSE not enabled, required by STM32_USART1SW"
610#endif
611
612#if STM32_USART2SW == STM32_USART2SW_LSE
613#error "LSE not enabled, required by STM32_USART2SW"
614#endif
615
616#if STM32_USART3SW == STM32_USART3SW_LSE
617#error "LSE not enabled, required by STM32_USART3SW"
618#endif
619
620#else /* !STM32_LSE_ENABLED */
621
622#if STM32_RTCSEL == STM32_RTCSEL_LSE
623#error "LSE not enabled, required by STM32_RTCSEL"
624#endif
625
626#endif /* !STM32_LSE_ENABLED */
627
628/* PLL activation conditions.*/
629#if (STM32_SW == STM32_SW_PLL) || \
630 (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
631 STM32_USB_CLOCK_REQUIRED || \
632 defined(__DOXYGEN__)
633/**
634 * @brief PLL activation flag.
635 */
636#define STM32_ACTIVATE_PLL TRUE
637#else
638#define STM32_ACTIVATE_PLL FALSE
639#endif
640
641/* HSE prescaler setting check.*/
642#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
643#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
644#else
645#error "invalid STM32_PREDIV value specified"
646#endif
647
648/**
649 * @brief PLLMUL field.
650 */
651#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
652 defined(__DOXYGEN__)
653#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
654#else
655#error "invalid STM32_PLLMUL_VALUE value specified"
656#endif
657
658/**
659 * @brief PLL input clock frequency.
660 */
661#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
662#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
663#elif STM32_PLLSRC == STM32_PLLSRC_HSI
664#define STM32_PLLCLKIN (STM32_HSICLK / 2)
665#else
666#error "invalid STM32_PLLSRC value specified"
667#endif
668
669/* PLL input frequency range check.*/
670#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
671#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
672#endif
673
674/**
675 * @brief PLL output clock frequency.
676 */
677#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
678
679/* PLL output frequency range check.*/
680#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
681#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
682#endif
683
684/**
685 * @brief System clock source.
686 */
687#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
688#define STM32_SYSCLK STM32_PLLCLKOUT
689#elif (STM32_SW == STM32_SW_HSI)
690#define STM32_SYSCLK STM32_HSICLK
691#elif (STM32_SW == STM32_SW_HSE)
692#define STM32_SYSCLK STM32_HSECLK
693#else
694#error "invalid STM32_SW value specified"
695#endif
696
697/* Check on the system clock.*/
698#if STM32_SYSCLK > STM32_SYSCLK_MAX
699#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
700#endif
701
702/**
703 * @brief AHB frequency.
704 */
705#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
706#define STM32_HCLK (STM32_SYSCLK / 1)
707#elif STM32_HPRE == STM32_HPRE_DIV2
708#define STM32_HCLK (STM32_SYSCLK / 2)
709#elif STM32_HPRE == STM32_HPRE_DIV4
710#define STM32_HCLK (STM32_SYSCLK / 4)
711#elif STM32_HPRE == STM32_HPRE_DIV8
712#define STM32_HCLK (STM32_SYSCLK / 8)
713#elif STM32_HPRE == STM32_HPRE_DIV16
714#define STM32_HCLK (STM32_SYSCLK / 16)
715#elif STM32_HPRE == STM32_HPRE_DIV64
716#define STM32_HCLK (STM32_SYSCLK / 64)
717#elif STM32_HPRE == STM32_HPRE_DIV128
718#define STM32_HCLK (STM32_SYSCLK / 128)
719#elif STM32_HPRE == STM32_HPRE_DIV256
720#define STM32_HCLK (STM32_SYSCLK / 256)
721#elif STM32_HPRE == STM32_HPRE_DIV512
722#define STM32_HCLK (STM32_SYSCLK / 512)
723#else
724#error "invalid STM32_HPRE value specified"
725#endif
726
727/* AHB frequency check.*/
728#if STM32_HCLK > STM32_SYSCLK_MAX
729#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
730#endif
731
732/**
733 * @brief APB1 frequency.
734 */
735#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
736#define STM32_PCLK1 (STM32_HCLK / 1)
737#elif STM32_PPRE1 == STM32_PPRE1_DIV2
738#define STM32_PCLK1 (STM32_HCLK / 2)
739#elif STM32_PPRE1 == STM32_PPRE1_DIV4
740#define STM32_PCLK1 (STM32_HCLK / 4)
741#elif STM32_PPRE1 == STM32_PPRE1_DIV8
742#define STM32_PCLK1 (STM32_HCLK / 8)
743#elif STM32_PPRE1 == STM32_PPRE1_DIV16
744#define STM32_PCLK1 (STM32_HCLK / 16)
745#else
746#error "invalid STM32_PPRE1 value specified"
747#endif
748
749/* APB1 frequency check.*/
750#if STM32_PCLK1 > STM32_PCLK1_MAX
751#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
752#endif
753
754/**
755 * @brief APB2 frequency.
756 */
757#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
758#define STM32_PCLK2 (STM32_HCLK / 1)
759#elif STM32_PPRE2 == STM32_PPRE2_DIV2
760#define STM32_PCLK2 (STM32_HCLK / 2)
761#elif STM32_PPRE2 == STM32_PPRE2_DIV4
762#define STM32_PCLK2 (STM32_HCLK / 4)
763#elif STM32_PPRE2 == STM32_PPRE2_DIV8
764#define STM32_PCLK2 (STM32_HCLK / 8)
765#elif STM32_PPRE2 == STM32_PPRE2_DIV16
766#define STM32_PCLK2 (STM32_HCLK / 16)
767#else
768#error "invalid STM32_PPRE2 value specified"
769#endif
770
771/* APB2 frequency check.*/
772#if STM32_PCLK2 > STM32_PCLK2_MAX
773#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
774#endif
775
776/**
777 * @brief RTC clock.
778 */
779#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
780#define STM32_RTCCLK STM32_LSECLK
781#elif STM32_RTCSEL == STM32_RTCSEL_LSI
782#define STM32_RTCCLK STM32_LSICLK
783#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
784#define STM32_RTCCLK (STM32_HSECLK / 32)
785#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
786#define STM32_RTCCLK 0
787#else
788#error "invalid source selected for RTC clock"
789#endif
790
791/**
792 * @brief ADC frequency.
793 */
794#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
795#define STM32_ADCCLK (STM32_PCLK2 / 2)
796#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
797#define STM32_ADCCLK (STM32_PCLK2 / 4)
798#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
799#define STM32_ADCCLK (STM32_PCLK2 / 6)
800#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
801#define STM32_ADCCLK (STM32_PCLK2 / 8)
802#else
803#error "invalid STM32_ADCPRE value specified"
804#endif
805
806/* ADC maximum frequency check.*/
807#if STM32_ADC_USE_ADC1 && (STM32_ADCCLK > STM32_ADCCLK_MAX)
808#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
809#endif
810
811/* ADC minimum frequency check.*/
812#if STM32_ADC_USE_ADC1 && (STM32_ADCCLK < STM32_ADCCLK_MIN)
813#error "STM32_ADCCLK exceeding minimum frequency (STM32_ADCCLK_MIN)"
814#endif
815
816/**
817 * @brief SDADC frequency.
818 */
819#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__)
820#define STM32_SDADCCLK (STM32_SYSCLK / 2)
821#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__)
822#define STM32_SDADCCLK (STM32_SYSCLK / 4)
823#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__)
824#define STM32_SDADCCLK (STM32_SYSCLK / 6)
825#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__)
826#define STM32_SDADCCLK (STM32_SYSCLK / 8)
827#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__)
828#define STM32_SDADCCLK (STM32_SYSCLK / 10)
829#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__)
830#define STM32_SDADCCLK (STM32_SYSCLK / 12)
831#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__)
832#define STM32_SDADCCLK (STM32_SYSCLK / 14)
833#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__)
834#define STM32_SDADCCLK (STM32_SYSCLK / 16)
835#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__)
836#define STM32_SDADCCLK (STM32_SYSCLK / 20)
837#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__)
838#define STM32_SDADCCLK (STM32_SYSCLK / 24)
839#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__)
840#define STM32_SDADCCLK (STM32_SYSCLK / 28)
841#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__)
842#define STM32_SDADCCLK (STM32_SYSCLK / 32)
843#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__)
844#define STM32_SDADCCLK (STM32_SYSCLK / 36)
845#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__)
846#define STM32_SDADCCLK (STM32_SYSCLK / 40)
847#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__)
848#define STM32_SDADCCLK (STM32_SYSCLK / 44)
849#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__)
850#define STM32_SDADCCLK (STM32_SYSCLK / 48)
851#else
852#error "invalid STM32_SDPRE value specified"
853#endif
854
855/* SDADC maximum frequency check.*/
856#if (STM32_ADC_USE_SDADC1 || \
857 STM32_ADC_USE_SDADC2 || \
858 STM32_ADC_USE_SDADC3) && (STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX)
859#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)"
860#endif
861
862/* SDADC minimum frequency check.*/
863#if (STM32_ADC_USE_SDADC1 || \
864 STM32_ADC_USE_SDADC2 || \
865 STM32_ADC_USE_SDADC3) && \
866 (STM32_SDADCCLK < STM32_SDADCCLK_MIN)
867#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)"
868#endif
869
870/**
871 * @brief I2C1 frequency.
872 */
873#if STM32_I2C1SW == STM32_I2C1SW_HSI
874#define STM32_I2C1CLK STM32_HSICLK
875#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
876#define STM32_I2C1CLK STM32_SYSCLK
877#else
878#error "invalid source selected for I2C1 clock"
879#endif
880
881/**
882 * @brief I2C2 frequency.
883 */
884#if STM32_I2C2SW == STM32_I2C2SW_HSI
885#define STM32_I2C2CLK STM32_HSICLK
886#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
887#define STM32_I2C2CLK STM32_SYSCLK
888#else
889#error "invalid source selected for I2C2 clock"
890#endif
891
892/**
893 * @brief USART1 frequency.
894 */
895#if STM32_USART1SW == STM32_USART1SW_PCLK
896#define STM32_USART1CLK STM32_PCLK2
897#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
898#define STM32_USART1CLK STM32_SYSCLK
899#elif STM32_USART1SW == STM32_USART1SW_LSE
900#define STM32_USART1CLK STM32_LSECLK
901#elif STM32_USART1SW == STM32_USART1SW_HSI
902#define STM32_USART1CLK STM32_HSICLK
903#else
904#error "invalid source selected for USART1 clock"
905#endif
906
907/**
908 * @brief USART2 frequency.
909 */
910#if STM32_USART2SW == STM32_USART2SW_PCLK
911#define STM32_USART2CLK STM32_PCLK1
912#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
913#define STM32_USART2CLK STM32_SYSCLK
914#elif STM32_USART2SW == STM32_USART2SW_LSE
915#define STM32_USART2CLK STM32_LSECLK
916#elif STM32_USART2SW == STM32_USART2SW_HSI
917#define STM32_USART2CLK STM32_HSICLK
918#else
919#error "invalid source selected for USART2 clock"
920#endif
921
922/**
923 * @brief USART3 frequency.
924 */
925#if STM32_USART3SW == STM32_USART3SW_PCLK
926#define STM32_USART3CLK STM32_PCLK1
927#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
928#define STM32_USART3CLK STM32_SYSCLK
929#elif STM32_USART3SW == STM32_USART3SW_LSE
930#define STM32_USART3CLK STM32_LSECLK
931#elif STM32_USART3SW == STM32_USART3SW_HSI
932#define STM32_USART3CLK STM32_HSICLK
933#else
934#error "invalid source selected for USART3 clock"
935#endif
936
937/**
938 * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency.
939 */
940#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
941#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
942#else
943#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
944#endif
945
946/**
947 * @brief Timers 15, 16, 17, 19 frequency.
948 */
949#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
950#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
951#else
952#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
953#endif
954
955/**
956 * @brief USB frequency.
957 */
958#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
959#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
960#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
961#define STM32_USBCLK STM32_PLLCLKOUT
962#else
963#error "invalid STM32_USBPRE value specified"
964#endif
965
966/**
967 * @brief Flash settings.
968 */
969#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
970#define STM32_FLASHBITS 0x00000010
971#elif STM32_HCLK <= 48000000
972#define STM32_FLASHBITS 0x00000011
973#else
974#define STM32_FLASHBITS 0x00000012
975#endif
976
977/*===========================================================================*/
978/* Driver data structures and types. */
979/*===========================================================================*/
980
981/*===========================================================================*/
982/* Driver macros. */
983/*===========================================================================*/
984
985/*===========================================================================*/
986/* External declarations. */
987/*===========================================================================*/
988
989/* Various helpers.*/
990#include "nvic.h"
991#include "cache.h"
992#include "mpu_v7m.h"
993#include "stm32_registry.h"
994#include "stm32_isr.h"
995#include "stm32_dma.h"
996#include "stm32_exti.h"
997#include "stm32_rcc.h"
998#include "stm32_tim.h"
999
1000#ifdef __cplusplus
1001extern "C" {
1002#endif
1003 void hal_lld_init(void);
1004 void stm32_clock_init(void);
1005#ifdef __cplusplus
1006}
1007#endif
1008
1009#endif /* HAL_LLD_H */
1010
1011/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/platform.mk b/lib/chibios/os/hal/ports/STM32/STM32F37x/platform.mk
new file mode 100644
index 000000000..ad020d7e3
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/platform.mk
@@ -0,0 +1,47 @@
1# Required platform files.
2PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
3 $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/stm32_isr.c \
4 $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c
5
6# Required include directories.
7PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
8 $(CHIBIOS)/os/hal/ports/STM32/STM32F37x
9
10# Optional platform files.
11ifeq ($(USE_SMART_BUILD),yes)
12
13# Configuration files directory
14ifeq ($(HALCONFDIR),)
15 ifeq ($(CONFDIR),)
16 HALCONFDIR = .
17 else
18 HALCONFDIR := $(CONFDIR)
19 endif
20endif
21
22HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
23
24ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
25PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
26endif
27else
28PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
29endif
30
31# Drivers compatible with the platform.
32include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
33include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
34include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
35include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
36include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
37include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
38include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
39include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
40include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
41include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
42include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
43include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
44
45# Shared variables
46ALLCSRC += $(PLATFORMSRC)
47ALLINC += $(PLATFORMINC)
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.c
new file mode 100644
index 000000000..3336d030b
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.c
@@ -0,0 +1,255 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F3xx/stm32_isr.c
19 * @brief STM32F3xx ISR handler code.
20 *
21 * @addtogroup STM32F3xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/*===========================================================================*/
36/* Driver local variables. */
37/*===========================================================================*/
38
39/*===========================================================================*/
40/* Driver local functions. */
41/*===========================================================================*/
42
43#define exti_serve_irq(pr, channel) { \
44 \
45 if ((pr) & (1U << (channel))) { \
46 _pal_isr_code(channel); \
47 } \
48}
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
55#if !defined(STM32_DISABLE_EXTI0_HANDLER)
56/**
57 * @brief EXTI[0] interrupt handler.
58 *
59 * @isr
60 */
61OSAL_IRQ_HANDLER(Vector58) {
62 uint32_t pr;
63
64 OSAL_IRQ_PROLOGUE();
65
66 pr = EXTI->PR;
67 pr &= EXTI->IMR & (1U << 0);
68 EXTI->PR = pr;
69
70 exti_serve_irq(pr, 0);
71
72 OSAL_IRQ_EPILOGUE();
73}
74#endif
75
76#if !defined(STM32_DISABLE_EXTI1_HANDLER)
77/**
78 * @brief EXTI[1] interrupt handler.
79 *
80 * @isr
81 */
82OSAL_IRQ_HANDLER(Vector5C) {
83 uint32_t pr;
84
85 OSAL_IRQ_PROLOGUE();
86
87 pr = EXTI->PR;
88 pr &= EXTI->IMR & (1U << 1);
89 EXTI->PR = pr;
90
91 exti_serve_irq(pr, 1);
92
93 OSAL_IRQ_EPILOGUE();
94}
95#endif
96
97#if !defined(STM32_DISABLE_EXTI2_HANDLER)
98/**
99 * @brief EXTI[2] interrupt handler.
100 *
101 * @isr
102 */
103OSAL_IRQ_HANDLER(Vector60) {
104 uint32_t pr;
105
106 OSAL_IRQ_PROLOGUE();
107
108 pr = EXTI->PR;
109 pr &= EXTI->IMR & (1U << 2);
110 EXTI->PR = pr;
111
112 exti_serve_irq(pr, 2);
113
114 OSAL_IRQ_EPILOGUE();
115}
116#endif
117
118#if !defined(STM32_DISABLE_EXTI3_HANDLER)
119/**
120 * @brief EXTI[3] interrupt handler.
121 *
122 * @isr
123 */
124OSAL_IRQ_HANDLER(Vector64) {
125 uint32_t pr;
126
127 OSAL_IRQ_PROLOGUE();
128
129 pr = EXTI->PR;
130 pr &= EXTI->IMR & (1U << 3);
131 EXTI->PR = pr;
132
133 exti_serve_irq(pr, 3);
134
135 OSAL_IRQ_EPILOGUE();
136}
137#endif
138
139#if !defined(STM32_DISABLE_EXTI4_HANDLER)
140/**
141 * @brief EXTI[4] interrupt handler.
142 *
143 * @isr
144 */
145OSAL_IRQ_HANDLER(Vector68) {
146 uint32_t pr;
147
148 OSAL_IRQ_PROLOGUE();
149
150 pr = EXTI->PR;
151 pr &= EXTI->IMR & (1U << 4);
152 EXTI->PR = pr;
153
154 exti_serve_irq(pr, 4);
155
156 OSAL_IRQ_EPILOGUE();
157}
158#endif
159
160#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
161/**
162 * @brief EXTI[5]...EXTI[9] interrupt handler.
163 *
164 * @isr
165 */
166OSAL_IRQ_HANDLER(Vector9C) {
167 uint32_t pr;
168
169 OSAL_IRQ_PROLOGUE();
170
171 pr = EXTI->PR;
172 pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
173 (1U << 9));
174 EXTI->PR = pr;
175
176 exti_serve_irq(pr, 5);
177 exti_serve_irq(pr, 6);
178 exti_serve_irq(pr, 7);
179 exti_serve_irq(pr, 8);
180 exti_serve_irq(pr, 9);
181
182 OSAL_IRQ_EPILOGUE();
183}
184#endif
185
186#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
187/**
188 * @brief EXTI[10]...EXTI[15] interrupt handler.
189 *
190 * @isr
191 */
192OSAL_IRQ_HANDLER(VectorE0) {
193 uint32_t pr;
194
195 OSAL_IRQ_PROLOGUE();
196
197 pr = EXTI->PR;
198 pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
199 (1U << 14) | (1U << 15));
200 EXTI->PR = pr;
201
202 exti_serve_irq(pr, 10);
203 exti_serve_irq(pr, 11);
204 exti_serve_irq(pr, 12);
205 exti_serve_irq(pr, 13);
206 exti_serve_irq(pr, 14);
207 exti_serve_irq(pr, 15);
208
209 OSAL_IRQ_EPILOGUE();
210}
211#endif
212
213#endif /* HAL_USE_PAL */
214
215/*===========================================================================*/
216/* Driver exported functions. */
217/*===========================================================================*/
218
219/**
220 * @brief Enables IRQ sources.
221 *
222 * @notapi
223 */
224void irqInit(void) {
225
226#if HAL_USE_PAL
227 nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
228 nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
229 nvicEnableVector(EXTI2_TSC_IRQn, STM32_IRQ_EXTI2_PRIORITY);
230 nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
231 nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
232 nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
233 nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
234#endif
235}
236
237/**
238 * @brief Disables IRQ sources.
239 *
240 * @notapi
241 */
242void irqDeinit(void) {
243
244#if HAL_USE_PAL
245 nvicDisableVector(EXTI0_IRQn);
246 nvicDisableVector(EXTI1_IRQn);
247 nvicDisableVector(EXTI2_TSC_IRQn);
248 nvicDisableVector(EXTI3_IRQn);
249 nvicDisableVector(EXTI4_IRQn);
250 nvicDisableVector(EXTI9_5_IRQn);
251 nvicDisableVector(EXTI15_10_IRQn);
252#endif
253}
254
255/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.h b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.h
new file mode 100644
index 000000000..7690f7d97
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_isr.h
@@ -0,0 +1,243 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/stm32_isr.h
19 * @brief STM32F37x ISR handler header.
20 *
21 * @addtogroup STM32F37x_ISR
22 * @{
23 */
24
25#ifndef STM32_ISR_H
26#define STM32_ISR_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name ISR names and numbers remapping
34 * @{
35 */
36/*
37 * CAN units.
38 */
39#define STM32_CAN1_TX_HANDLER Vector8C
40#define STM32_CAN1_RX0_HANDLER Vector90
41#define STM32_CAN1_RX1_HANDLER Vector94
42#define STM32_CAN1_SCE_HANDLER Vector98
43
44#define STM32_CAN1_TX_NUMBER 19
45#define STM32_CAN1_RX0_NUMBER 20
46#define STM32_CAN1_RX1_NUMBER 21
47#define STM32_CAN1_SCE_NUMBER 22
48
49/*
50 * I2C units.
51 */
52#define STM32_I2C1_EVENT_HANDLER VectorBC
53#define STM32_I2C1_ERROR_HANDLER VectorC0
54#define STM32_I2C1_EVENT_NUMBER 31
55#define STM32_I2C1_ERROR_NUMBER 32
56
57#define STM32_I2C2_EVENT_HANDLER VectorC4
58#define STM32_I2C2_ERROR_HANDLER VectorC8
59#define STM32_I2C2_EVENT_NUMBER 33
60#define STM32_I2C2_ERROR_NUMBER 34
61
62/*
63 * TIM units.
64 */
65#define STM32_TIM2_HANDLER VectorB0
66#define STM32_TIM3_HANDLER VectorB4
67#define STM32_TIM4_HANDLER VectorB8
68#define STM32_TIM5_HANDLER Vector108
69#define STM32_TIM6_HANDLER Vector118
70#define STM32_TIM7_HANDLER Vector11C
71#define STM32_TIM12_HANDLER VectorEC
72#define STM32_TIM13_HANDLER VectorF0
73#define STM32_TIM14_HANDLER VectorF4
74#define STM32_TIM15_HANDLER VectorA0
75#define STM32_TIM16_HANDLER VectorA4
76#define STM32_TIM17_HANDLER VectorA8
77#define STM32_TIM18_HANDLER VectorAC
78#define STM32_TIM19_HANDLER Vector178
79
80#define STM32_TIM2_NUMBER 28
81#define STM32_TIM3_NUMBER 29
82#define STM32_TIM4_NUMBER 30
83#define STM32_TIM5_NUMBER 50
84#define STM32_TIM6_NUMBER 54
85#define STM32_TIM7_NUMBER 55
86#define STM32_TIM12_NUMBER 43
87#define STM32_TIM13_NUMBER 44
88#define STM32_TIM14_NUMBER 45
89#define STM32_TIM15_NUMBER 24
90#define STM32_TIM16_NUMBER 25
91#define STM32_TIM17_NUMBER 26
92#define STM32_TIM18_NUMBER 27
93#define STM32_TIM19_NUMBER 78
94
95/*
96 * USART units.
97 */
98#define STM32_USART1_HANDLER VectorD4
99#define STM32_USART2_HANDLER VectorD8
100#define STM32_USART3_HANDLER VectorDC
101
102#define STM32_USART1_NUMBER 37
103#define STM32_USART2_NUMBER 38
104#define STM32_USART3_NUMBER 39
105
106/*
107 * USB units.
108 */
109#define STM32_USB1_HP_HANDLER Vector168
110#define STM32_USB1_LP_HANDLER Vector16C
111
112#define STM32_USB1_HP_NUMBER 74
113#define STM32_USB1_LP_NUMBER 75
114/** @} */
115
116/*===========================================================================*/
117/* Driver pre-compile time settings. */
118/*===========================================================================*/
119
120/**
121 * @name Configuration options
122 * @{
123 */
124/**
125 * @brief EXTI0 interrupt priority level setting.
126 */
127#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
128#define STM32_IRQ_EXTI0_PRIORITY 6
129#endif
130
131/**
132 * @brief EXTI1 interrupt priority level setting.
133 */
134#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
135#define STM32_IRQ_EXTI1_PRIORITY 6
136#endif
137
138/**
139 * @brief EXTI2 interrupt priority level setting.
140 */
141#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
142#define STM32_IRQ_EXTI2_PRIORITY 6
143#endif
144
145/**
146 * @brief EXTI3 interrupt priority level setting.
147 */
148#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
149#define STM32_IRQ_EXTI3_PRIORITY 6
150#endif
151
152/**
153 * @brief EXTI4 interrupt priority level setting.
154 */
155#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
156#define STM32_IRQ_EXTI4_PRIORITY 6
157#endif
158
159/**
160 * @brief EXTI5..9 interrupt priority level setting.
161 */
162#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
163#define STM32_IRQ_EXTI5_9_PRIORITY 6
164#endif
165
166/**
167 * @brief EXTI10..15 interrupt priority level setting.
168 */
169#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
170#define STM32_IRQ_EXTI10_15_PRIORITY 6
171#endif
172
173/**
174 * @brief EXTI16 interrupt priority level setting.
175 */
176#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
177#define STM32_IRQ_EXTI16_PRIORITY 6
178#endif
179
180/**
181 * @brief EXTI17 interrupt priority level setting.
182 */
183#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
184#define STM32_IRQ_EXTI17_PRIORITY 6
185#endif
186
187/**
188 * @brief EXTI18 interrupt priority level setting.
189 */
190#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
191#define STM32_IRQ_EXTI18_PRIORITY 6
192#endif
193
194/**
195 * @brief EXTI19 interrupt priority level setting.
196 */
197#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
198#define STM32_IRQ_EXTI19_PRIORITY 6
199#endif
200
201/**
202 * @brief EXTI20 interrupt priority level setting.
203 */
204#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__)
205#define STM32_IRQ_EXTI20_PRIORITY 6
206#endif
207
208/**
209 * @brief EXTI21..22 interrupt priority level setting.
210 */
211#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
212#define STM32_IRQ_EXTI21_22_PRIORITY 6
213#endif
214/** @} */
215
216/*===========================================================================*/
217/* Derived constants and error checks. */
218/*===========================================================================*/
219
220/*===========================================================================*/
221/* Driver data structures and types. */
222/*===========================================================================*/
223
224/*===========================================================================*/
225/* Driver macros. */
226/*===========================================================================*/
227
228/*===========================================================================*/
229/* External declarations. */
230/*===========================================================================*/
231
232#ifdef __cplusplus
233extern "C" {
234#endif
235 void irqInit(void);
236 void irqDeinit(void);
237#ifdef __cplusplus
238}
239#endif
240
241#endif /* STM32_ISR_H */
242
243/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
new file mode 100644
index 000000000..7dbc78bea
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_rcc.h
@@ -0,0 +1,1020 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f30x.h.
22 *
23 * @addtogroup STM32F37x_RCC
24 * @{
25 */
26
27#ifndef STM32_RCC_H
28#define STM32_RCC_H
29
30/*===========================================================================*/
31/* Driver constants. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Driver pre-compile time settings. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Derived constants and error checks. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver data structures and types. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver macros. */
48/*===========================================================================*/
49
50/**
51 * @name Generic RCC operations
52 * @{
53 */
54/**
55 * @brief Enables the clock of one or more peripheral on the APB1 bus.
56 *
57 * @param[in] mask APB1 peripherals mask
58 * @param[in] lp low power enable flag
59 *
60 * @api
61 */
62#define rccEnableAPB1(mask, lp) { \
63 RCC->APB1ENR |= (mask); \
64 (void)RCC->APB1ENR; \
65}
66
67/**
68 * @brief Disables the clock of one or more peripheral on the APB1 bus.
69 *
70 * @param[in] mask APB1 peripherals mask
71 *
72 * @api
73 */
74#define rccDisableAPB1(mask) { \
75 RCC->APB1ENR &= ~(mask); \
76 (void)RCC->APB1ENR; \
77}
78
79/**
80 * @brief Resets one or more peripheral on the APB1 bus.
81 *
82 * @param[in] mask APB1 peripherals mask
83 *
84 * @api
85 */
86#define rccResetAPB1(mask) { \
87 RCC->APB1RSTR |= (mask); \
88 RCC->APB1RSTR &= ~(mask); \
89 (void)RCC->APB1RSTR; \
90}
91
92/**
93 * @brief Enables the clock of one or more peripheral on the APB2 bus.
94 *
95 * @param[in] mask APB2 peripherals mask
96 * @param[in] lp low power enable flag
97 *
98 * @api
99 */
100#define rccEnableAPB2(mask, lp) { \
101 RCC->APB2ENR |= (mask); \
102 (void)RCC->APB2ENR; \
103}
104
105/**
106 * @brief Disables the clock of one or more peripheral on the APB2 bus.
107 *
108 * @param[in] mask APB2 peripherals mask
109 *
110 * @api
111 */
112#define rccDisableAPB2(mask) { \
113 RCC->APB2ENR &= ~(mask); \
114 (void)RCC->APB2ENR; \
115}
116
117/**
118 * @brief Resets one or more peripheral on the APB2 bus.
119 *
120 * @param[in] mask APB2 peripherals mask
121 *
122 * @api
123 */
124#define rccResetAPB2(mask) { \
125 RCC->APB2RSTR |= (mask); \
126 RCC->APB2RSTR &= ~(mask); \
127 (void)RCC->APB2RSTR; \
128}
129
130/**
131 * @brief Enables the clock of one or more peripheral on the AHB bus.
132 *
133 * @param[in] mask AHB peripherals mask
134 * @param[in] lp low power enable flag
135 *
136 * @api
137 */
138#define rccEnableAHB(mask, lp) { \
139 RCC->AHBENR |= (mask); \
140 (void)RCC->AHBENR; \
141}
142
143/**
144 * @brief Disables the clock of one or more peripheral on the AHB bus.
145 *
146 * @param[in] mask AHB peripherals mask
147 *
148 * @api
149 */
150#define rccDisableAHB(mask) { \
151 RCC->AHBENR &= ~(mask); \
152 (void)RCC->AHBENR; \
153}
154
155/**
156 * @brief Resets one or more peripheral on the AHB bus.
157 *
158 * @param[in] mask AHB peripherals mask
159 *
160 * @api
161 */
162#define rccResetAHB(mask) { \
163 RCC->AHBRSTR |= (mask); \
164 RCC->AHBRSTR &= ~(mask); \
165 (void)RCC->AHBRSTR; \
166}
167/** @} */
168
169/**
170 * @name ADC1 peripheral specific RCC operations
171 * @{
172 */
173/**
174 * @brief Enables the ADC peripheral clock.
175 *
176 * @param[in] lp low power enable flag
177 *
178 * @api
179 */
180#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
181
182/**
183 * @brief Disables the ADC1 peripheral clock.
184 *
185 * @api
186 */
187#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
188
189/**
190 * @brief Resets the ADC1 peripheral.
191 *
192 * @api
193 */
194#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
195/** @} */
196
197/**
198 * @name DAC peripheral specific RCC operations
199 * @{
200 */
201/**
202 * @brief Enables the DAC1 peripheral clock.
203 *
204 * @param[in] lp low power enable flag
205 *
206 * @api
207 */
208#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DAC1EN, lp)
209
210/**
211 * @brief Disables the DAC1 peripheral clock.
212 *
213 * @api
214 */
215#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DAC1EN)
216
217/**
218 * @brief Resets the DAC1 peripheral.
219 *
220 * @api
221 */
222#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DAC1RST)
223
224/**
225 * @brief Enables the DAC1 peripheral clock.
226 *
227 * @param[in] lp low power enable flag
228 *
229 * @api
230 */
231#define rccEnableDAC2(lp) rccEnableAPB1(RCC_APB1ENR_DAC2EN, lp)
232
233/**
234 * @brief Disables the DAC1 peripheral clock.
235 *
236 * @api
237 */
238#define rccDisableDAC2() rccDisableAPB1(RCC_APB1ENR_DAC2EN)
239
240/**
241 * @brief Resets the DAC1 peripheral.
242 *
243 * @api
244 */
245#define rccResetDAC2() rccResetAPB1(RCC_APB1RSTR_DAC2RST)
246/** @} */
247
248/**
249 * @name CAN peripherals specific RCC operations
250 * @{
251 */
252/**
253 * @brief Enables the CAN1 peripheral clock.
254 * @note The @p lp parameter is ignored in this family.
255 *
256 * @param[in] lp low power enable flag
257 *
258 * @api
259 */
260#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
261
262/**
263 * @brief Disables the CAN1 peripheral clock.
264 *
265 * @api
266 */
267#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CANEN)
268
269/**
270 * @brief Resets the CAN1 peripheral.
271 *
272 * @api
273 */
274#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
275/** @} */
276
277/**
278 * @name DMA peripheral specific RCC operations
279 * @{
280 */
281/**
282 * @brief Enables the DMA1 peripheral clock.
283 *
284 * @param[in] lp low power enable flag
285 *
286 * @api
287 */
288#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
289
290/**
291 * @brief Disables the DMA1 peripheral clock.
292 *
293 * @api
294 */
295#define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
296
297/**
298 * @brief Resets the DMA1 peripheral.
299 *
300 * @api
301 */
302#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
303
304/**
305 * @brief Enables the DMA2 peripheral clock.
306 *
307 * @param[in] lp low power enable flag
308 *
309 * @api
310 */
311#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
312
313/**
314 * @brief Disables the DMA2 peripheral clock.
315 *
316 * @api
317 */
318#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN)
319
320/**
321 * @brief Resets the DMA2 peripheral.
322 *
323 * @api
324 */
325#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
326/** @} */
327
328/**
329 * @name PWR interface specific RCC operations
330 * @{
331 */
332/**
333 * @brief Enables the PWR interface clock.
334 * @note The @p lp parameter is ignored in this family.
335 *
336 * @param[in] lp low power enable flag
337 *
338 * @api
339 */
340#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
341
342/**
343 * @brief Disables PWR interface clock.
344 *
345 * @api
346 */
347#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
348
349/**
350 * @brief Resets the PWR interface.
351 *
352 * @api
353 */
354#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
355/** @} */
356
357/**
358 * @name I2C peripherals specific RCC operations
359 * @{
360 */
361/**
362 * @brief Enables the I2C1 peripheral clock.
363 *
364 * @param[in] lp low power enable flag
365 *
366 * @api
367 */
368#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
369
370/**
371 * @brief Disables the I2C1 peripheral clock.
372 *
373 * @api
374 */
375#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
376
377/**
378 * @brief Resets the I2C1 peripheral.
379 *
380 * @api
381 */
382#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
383
384/**
385 * @brief Enables the I2C2 peripheral clock.
386 *
387 * @param[in] lp low power enable flag
388 *
389 * @api
390 */
391#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
392
393/**
394 * @brief Disables the I2C2 peripheral clock.
395 *
396 * @api
397 */
398#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
399
400/**
401 * @brief Resets the I2C2 peripheral.
402 *
403 * @api
404 */
405#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
406/** @} */
407
408/**
409 * @name SDADC peripherals specific RCC operations
410 * @{
411 */
412/**
413 * @brief Enables the SDADC1 peripheral clock.
414 *
415 * @param[in] lp low power enable flag
416 *
417 * @api
418 */
419#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp)
420
421/**
422 * @brief Disables the SDADC1 peripheral clock.
423 *
424 * @api
425 */
426#define rccDisableSDADC1() rccDisableAPB2(RCC_APB2ENR_SDADC1EN)
427
428/**
429 * @brief Resets the SDADC1 peripheral.
430 *
431 * @api
432 */
433#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST)
434
435/**
436 * @brief Enables the SDADC2 peripheral clock.
437 *
438 * @param[in] lp low power enable flag
439 *
440 * @api
441 */
442#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp)
443
444/**
445 * @brief Disables the SDADC2 peripheral clock.
446 *
447 * @api
448 */
449#define rccDisableSDADC2() rccDisableAPB2(RCC_APB2ENR_SDADC2EN)
450
451/**
452 * @brief Resets the SDADC2 peripheral.
453 *
454 * @api
455 */
456#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST)
457
458/**
459 * @brief Enables the SDADC3 peripheral clock.
460 *
461 * @param[in] lp low power enable flag
462 *
463 * @api
464 */
465#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp)
466
467/**
468 * @brief Disables the SDADC3 peripheral clock.
469 *
470 * @api
471 */
472#define rccDisableSDADC3() rccDisableAPB2(RCC_APB2ENR_SDADC3EN)
473
474/**
475 * @brief Resets the SDADC3 peripheral.
476 *
477 * @api
478 */
479#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST)
480/** @} */
481
482/**
483 * @name SPI peripherals specific RCC operations
484 * @{
485 */
486/**
487 * @brief Enables the SPI1 peripheral clock.
488 *
489 * @param[in] lp low power enable flag
490 *
491 * @api
492 */
493#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
494
495/**
496 * @brief Disables the SPI1 peripheral clock.
497 *
498 * @api
499 */
500#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
501
502/**
503 * @brief Resets the SPI1 peripheral.
504 *
505 * @api
506 */
507#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
508
509/**
510 * @brief Enables the SPI2 peripheral clock.
511 *
512 * @param[in] lp low power enable flag
513 *
514 * @api
515 */
516#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
517
518/**
519 * @brief Disables the SPI2 peripheral clock.
520 *
521 * @api
522 */
523#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
524
525/**
526 * @brief Resets the SPI2 peripheral.
527 *
528 * @api
529 */
530#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
531
532/**
533 * @brief Enables the SPI3 peripheral clock.
534 * @note The @p lp parameter is ignored in this family.
535 *
536 * @param[in] lp low power enable flag
537 *
538 * @api
539 */
540#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
541
542/**
543 * @brief Disables the SPI3 peripheral clock.
544 *
545 * @api
546 */
547#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
548
549/**
550 * @brief Resets the SPI3 peripheral.
551 *
552 * @api
553 */
554#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
555/** @} */
556
557/**
558 * @name TIM peripherals specific RCC operations
559 * @{
560 */
561/**
562 * @brief Enables the TIM2 peripheral clock.
563 *
564 * @param[in] lp low power enable flag
565 *
566 * @api
567 */
568#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
569
570/**
571 * @brief Disables the TIM2 peripheral clock.
572 *
573 * @api
574 */
575#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
576
577/**
578 * @brief Resets the TIM2 peripheral.
579 *
580 * @api
581 */
582#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
583
584/**
585 * @brief Enables the TIM3 peripheral clock.
586 *
587 * @param[in] lp low power enable flag
588 *
589 * @api
590 */
591#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
592
593/**
594 * @brief Disables the TIM3 peripheral clock.
595 *
596 * @api
597 */
598#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
599
600/**
601 * @brief Resets the TIM3 peripheral.
602 *
603 * @api
604 */
605#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
606
607/**
608 * @brief Enables the TIM4 peripheral clock.
609 *
610 * @param[in] lp low power enable flag
611 *
612 * @api
613 */
614#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
615
616/**
617 * @brief Disables the TIM4 peripheral clock.
618 *
619 * @api
620 */
621#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
622
623/**
624 * @brief Resets the TIM4 peripheral.
625 *
626 * @api
627 */
628#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
629
630/**
631 * @brief Enables the TIM5 peripheral clock.
632 *
633 * @param[in] lp low power enable flag
634 *
635 * @api
636 */
637#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
638
639/**
640 * @brief Disables the TIM5 peripheral clock.
641 *
642 * @api
643 */
644#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
645
646/**
647 * @brief Resets the TIM5 peripheral.
648 *
649 * @api
650 */
651#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
652
653/**
654 * @brief Enables the TIM6 peripheral clock.
655 *
656 * @param[in] lp low power enable flag
657 *
658 * @api
659 */
660#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
661
662/**
663 * @brief Disables the TIM6 peripheral clock.
664 *
665 * @api
666 */
667#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
668
669/**
670 * @brief Resets the TIM6 peripheral.
671 *
672 * @api
673 */
674#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
675
676/**
677 * @brief Enables the TIM7 peripheral clock.
678 *
679 * @param[in] lp low power enable flag
680 *
681 * @api
682 */
683#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
684
685/**
686 * @brief Disables the TIM7 peripheral clock.
687 *
688 * @api
689 */
690#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
691
692/**
693 * @brief Resets the TIM7 peripheral.
694 *
695 * @api
696 */
697#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
698
699/**
700 * @brief Enables the TIM12 peripheral clock.
701 *
702 * @param[in] lp low power enable flag
703 *
704 * @api
705 */
706#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
707
708/**
709 * @brief Disables the TIM12 peripheral clock.
710 *
711 * @api
712 */
713#define rccDisableTIM12() rccDisableAPB1(RCC_APB1ENR_TIM12EN)
714
715/**
716 * @brief Resets the TIM12 peripheral.
717 *
718 * @api
719 */
720#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
721
722/**
723 * @brief Enables the TIM13 peripheral clock.
724 *
725 * @param[in] lp low power enable flag
726 *
727 * @api
728 */
729#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
730
731/**
732 * @brief Disables the TIM13 peripheral clock.
733 *
734 * @api
735 */
736#define rccDisableTIM13() rccDisableAPB1(RCC_APB1ENR_TIM13EN)
737
738/**
739 * @brief Resets the TIM13 peripheral.
740 *
741 * @api
742 */
743#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
744
745/**
746 * @brief Enables the TIM14 peripheral clock.
747 *
748 * @param[in] lp low power enable flag
749 *
750 * @api
751 */
752#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
753
754/**
755 * @brief Disables the TIM14 peripheral clock.
756 *
757 * @api
758 */
759#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
760
761/**
762 * @brief Resets the TIM14 peripheral.
763 *
764 * @api
765 */
766#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
767
768/**
769 * @brief Enables the TIM15 peripheral clock.
770 *
771 * @param[in] lp low power enable flag
772 *
773 * @api
774 */
775#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
776
777/**
778 * @brief Disables the TIM15 peripheral clock.
779 *
780 * @api
781 */
782#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
783
784/**
785 * @brief Resets the TIM15 peripheral.
786 *
787 * @api
788 */
789#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
790
791/**
792 * @brief Enables the TIM16 peripheral clock.
793 *
794 * @param[in] lp low power enable flag
795 *
796 * @api
797 */
798#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
799
800/**
801 * @brief Disables the TIM16 peripheral clock.
802 *
803 * @api
804 */
805#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
806
807/**
808 * @brief Resets the TIM16 peripheral.
809 *
810 * @api
811 */
812#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
813
814/**
815 * @brief Enables the TIM17 peripheral clock.
816 *
817 * @param[in] lp low power enable flag
818 *
819 * @api
820 */
821#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
822
823/**
824 * @brief Disables the TIM17 peripheral clock.
825 *
826 * @api
827 */
828#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
829
830/**
831 * @brief Resets the TIM17 peripheral.
832 *
833 * @api
834 */
835#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
836
837/**
838 * @brief Enables the TIM18 peripheral clock.
839 *
840 * @param[in] lp low power enable flag
841 *
842 * @api
843 */
844#define rccEnableTIM18(lp) rccEnableAPB1(RCC_APB1ENR_TIM18EN, lp)
845
846/**
847 * @brief Disables the TIM18 peripheral clock.
848 *
849 * @api
850 */
851#define rccDisableTIM18() rccDisableAPB1(RCC_APB1ENR_TIM18EN)
852
853/**
854 * @brief Resets the TIM18 peripheral.
855 *
856 * @api
857 */
858#define rccResetTIM18() rccResetAPB1(RCC_APB1RSTR_TIM18RST)
859
860/**
861 * @brief Enables the TIM19 peripheral clock.
862 *
863 * @param[in] lp low power enable flag
864 *
865 * @api
866 */
867#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp)
868
869/**
870 * @brief Disables the TIM19 peripheral clock.
871 *
872 * @api
873 */
874#define rccDisableTIM19() rccDisableAPB2(RCC_APB2ENR_TIM19EN)
875
876/**
877 * @brief Resets the TIM19 peripheral.
878 *
879 * @api
880 */
881#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST)
882/** @} */
883
884/**
885 * @name USART/UART peripherals specific RCC operations
886 * @{
887 */
888/**
889 * @brief Enables the USART1 peripheral clock.
890 *
891 * @param[in] lp low power enable flag
892 *
893 * @api
894 */
895#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
896
897/**
898 * @brief Disables the USART1 peripheral clock.
899 *
900 * @api
901 */
902#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
903
904/**
905 * @brief Resets the USART1 peripheral.
906 *
907 * @api
908 */
909#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
910
911/**
912 * @brief Enables the USART2 peripheral clock.
913 *
914 * @param[in] lp low power enable flag
915 *
916 * @api
917 */
918#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
919
920/**
921 * @brief Disables the USART2 peripheral clock.
922 *
923 * @api
924 */
925#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
926
927/**
928 * @brief Resets the USART2 peripheral.
929 *
930 * @api
931 */
932#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
933
934/**
935 * @brief Enables the USART3 peripheral clock.
936 *
937 * @param[in] lp low power enable flag
938 *
939 * @api
940 */
941#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
942
943/**
944 * @brief Disables the USART3 peripheral clock.
945 *
946 * @api
947 */
948#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
949
950/**
951 * @brief Resets the USART3 peripheral.
952 *
953 * @api
954 */
955#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
956/** @} */
957
958/**
959 * @name USB peripheral specific RCC operations
960 * @{
961 */
962/**
963 * @brief Enables the USB peripheral clock.
964 *
965 * @param[in] lp low power enable flag
966 *
967 * @api
968 */
969#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
970
971/**
972 * @brief Disables the USB peripheral clock.
973 *
974 * @api
975 */
976#define rccDisableUSB() rccDisableAPB1(RCC_APB1ENR_USBEN)
977
978/**
979 * @brief Resets the USB peripheral.
980 *
981 * @api
982 */
983#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
984/** @} */
985
986/**
987 * @name CRC peripherals specific RCC operations
988 * @{
989 */
990/**
991 * @brief Enables the CRC peripheral clock.
992 *
993 * @param[in] lp low power enable flag
994 *
995 * @api
996 */
997#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
998
999/**
1000 * @brief Disables the CRC peripheral clock.
1001 *
1002 * @api
1003 */
1004#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
1005/** @} */
1006
1007/*===========================================================================*/
1008/* External declarations. */
1009/*===========================================================================*/
1010
1011#ifdef __cplusplus
1012extern "C" {
1013#endif
1014#ifdef __cplusplus
1015}
1016#endif
1017
1018#endif /* STM32_RCC_H */
1019
1020/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_registry.h
new file mode 100644
index 000000000..295a538c5
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F37x/stm32_registry.h
@@ -0,0 +1,572 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/stm32_registry.h
19 * @brief STM32F37x capabilities registry.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef STM32_REGISTRY_H
26#define STM32_REGISTRY_H
27
28/*===========================================================================*/
29/* Platform capabilities. */
30/*===========================================================================*/
31
32/**
33 * @name STM32F37x capabilities
34 * @{
35 */
36/*===========================================================================*/
37/* STM32F373xC. */
38/*===========================================================================*/
39#if defined(STM32F373xC) || defined(__DOXYGEN__)
40/* ADC attributes.*/
41#define STM32_HAS_ADC1 TRUE
42#define STM32_HAS_ADC2 FALSE
43#define STM32_HAS_ADC3 FALSE
44#define STM32_HAS_ADC4 FALSE
45
46#define STM32_HAS_SDADC1 TRUE
47#define STM32_HAS_SDADC2 TRUE
48#define STM32_HAS_SDADC3 TRUE
49
50/* CAN attributes.*/
51#define STM32_HAS_CAN1 TRUE
52#define STM32_HAS_CAN2 FALSE
53#define STM32_HAS_CAN3 FALSE
54#define STM32_CAN_MAX_FILTERS 14
55
56/* DAC attributes.*/
57#define STM32_HAS_DAC1_CH1 TRUE
58#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
59
60#define STM32_HAS_DAC1_CH2 TRUE
61#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
62
63#define STM32_HAS_DAC2_CH1 TRUE
64#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
65
66#define STM32_HAS_DAC2_CH2 FALSE
67
68/* DMA attributes.*/
69#define STM32_ADVANCED_DMA FALSE
70#define STM32_DMA_SUPPORTS_DMAMUX FALSE
71#define STM32_DMA_SUPPORTS_CSELR FALSE
72
73#define STM32_DMA1_NUM_CHANNELS 7
74#define STM32_DMA1_CH1_HANDLER Vector6C
75#define STM32_DMA1_CH2_HANDLER Vector70
76#define STM32_DMA1_CH3_HANDLER Vector74
77#define STM32_DMA1_CH4_HANDLER Vector78
78#define STM32_DMA1_CH5_HANDLER Vector7C
79#define STM32_DMA1_CH6_HANDLER Vector80
80#define STM32_DMA1_CH7_HANDLER Vector84
81#define STM32_DMA1_CH1_NUMBER 11
82#define STM32_DMA1_CH2_NUMBER 12
83#define STM32_DMA1_CH3_NUMBER 13
84#define STM32_DMA1_CH4_NUMBER 14
85#define STM32_DMA1_CH5_NUMBER 15
86#define STM32_DMA1_CH6_NUMBER 16
87#define STM32_DMA1_CH7_NUMBER 17
88
89#define STM32_DMA2_NUM_CHANNELS 5
90#define STM32_DMA2_CH1_HANDLER Vector120
91#define STM32_DMA2_CH2_HANDLER Vector124
92#define STM32_DMA2_CH3_HANDLER Vector128
93#define STM32_DMA2_CH4_HANDLER Vector12C
94#define STM32_DMA2_CH5_HANDLER Vector130
95#define STM32_DMA2_CH1_NUMBER 56
96#define STM32_DMA2_CH2_NUMBER 57
97#define STM32_DMA2_CH3_NUMBER 58
98#define STM32_DMA2_CH4_NUMBER 59
99#define STM32_DMA2_CH5_NUMBER 60
100
101/* ETH attributes.*/
102#define STM32_HAS_ETH FALSE
103
104/* EXTI attributes.*/
105#define STM32_EXTI_NUM_LINES 23
106#define STM32_EXTI_IMR1_MASK 0x1F800000U
107
108/* GPIO attributes.*/
109#define STM32_HAS_GPIOA TRUE
110#define STM32_HAS_GPIOB TRUE
111#define STM32_HAS_GPIOC TRUE
112#define STM32_HAS_GPIOD TRUE
113#define STM32_HAS_GPIOE TRUE
114#define STM32_HAS_GPIOF TRUE
115#define STM32_HAS_GPIOG FALSE
116#define STM32_HAS_GPIOH FALSE
117#define STM32_HAS_GPIOI FALSE
118#define STM32_HAS_GPIOJ FALSE
119#define STM32_HAS_GPIOK FALSE
120#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
121 RCC_AHBENR_GPIOBEN | \
122 RCC_AHBENR_GPIOCEN | \
123 RCC_AHBENR_GPIODEN | \
124 RCC_AHBENR_GPIOEEN | \
125 RCC_AHBENR_GPIOFEN)
126
127/* I2C attributes.*/
128#define STM32_HAS_I2C1 TRUE
129#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
130#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
131
132#define STM32_HAS_I2C2 TRUE
133#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
134#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
135
136#define STM32_HAS_I2C3 FALSE
137#define STM32_HAS_I2C4 FALSE
138
139/* QUADSPI attributes.*/
140#define STM32_HAS_QUADSPI1 FALSE
141
142/* RTC attributes.*/
143#define STM32_HAS_RTC TRUE
144#define STM32_RTC_HAS_SUBSECONDS TRUE
145#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
146#define STM32_RTC_NUM_ALARMS 1
147#define STM32_RTC_STORAGE_SIZE 64
148#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
149#define STM32_RTC_WKUP_HANDLER Vector4C
150#define STM32_RTC_ALARM_HANDLER VectorE4
151#define STM32_RTC_TAMP_STAMP_NUMBER 2
152#define STM32_RTC_WKUP_NUMBER 3
153#define STM32_RTC_ALARM_NUMBER 41
154#define STM32_RTC_ALARM_EXTI 17
155#define STM32_RTC_TAMP_STAMP_EXTI 19
156#define STM32_RTC_WKUP_EXTI 20
157#define STM32_RTC_IRQ_ENABLE() do { \
158 nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
159 nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
160 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
161} while (false)
162
163/* SDIO attributes.*/
164#define STM32_HAS_SDIO FALSE
165
166/* SPI attributes.*/
167#define STM32_HAS_SPI1 TRUE
168#define STM32_SPI1_SUPPORTS_I2S TRUE
169#define STM32_SPI1_I2S_FULLDUPLEX FALSE
170#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
171#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
172
173#define STM32_HAS_SPI2 TRUE
174#define STM32_SPI2_SUPPORTS_I2S TRUE
175#define STM32_SPI2_I2S_FULLDUPLEX FALSE
176#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
177#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
178
179#define STM32_HAS_SPI3 TRUE
180#define STM32_SPI3_SUPPORTS_I2S TRUE
181#define STM32_SPI3_I2S_FULLDUPLEX FALSE
182#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
183#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
184
185#define STM32_HAS_SPI4 FALSE
186#define STM32_HAS_SPI5 FALSE
187#define STM32_HAS_SPI6 FALSE
188
189/* TIM attributes.*/
190#define STM32_TIM_MAX_CHANNELS 4
191
192#define STM32_HAS_TIM2 TRUE
193#define STM32_TIM2_IS_32BITS TRUE
194#define STM32_TIM2_CHANNELS 4
195
196#define STM32_HAS_TIM3 TRUE
197#define STM32_TIM3_IS_32BITS FALSE
198#define STM32_TIM3_CHANNELS 4
199
200#define STM32_HAS_TIM4 TRUE
201#define STM32_TIM4_IS_32BITS FALSE
202#define STM32_TIM4_CHANNELS 4
203
204#define STM32_HAS_TIM5 TRUE
205#define STM32_TIM5_IS_32BITS TRUE
206#define STM32_TIM5_CHANNELS 4
207
208#define STM32_HAS_TIM6 TRUE
209#define STM32_TIM6_IS_32BITS FALSE
210#define STM32_TIM6_CHANNELS 0
211
212#define STM32_HAS_TIM7 TRUE
213#define STM32_TIM7_IS_32BITS FALSE
214#define STM32_TIM7_CHANNELS 0
215
216#define STM32_HAS_TIM12 TRUE
217#define STM32_TIM12_IS_32BITS FALSE
218#define STM32_TIM12_CHANNELS 2
219
220#define STM32_HAS_TIM13 TRUE
221#define STM32_TIM13_IS_32BITS FALSE
222#define STM32_TIM13_CHANNELS 1
223
224#define STM32_HAS_TIM14 TRUE
225#define STM32_TIM14_IS_32BITS FALSE
226#define STM32_TIM14_CHANNELS 1
227
228#define STM32_HAS_TIM15 TRUE
229#define STM32_TIM15_IS_32BITS FALSE
230#define STM32_TIM15_CHANNELS 2
231
232#define STM32_HAS_TIM16 TRUE
233#define STM32_TIM16_IS_32BITS FALSE
234#define STM32_TIM16_CHANNELS 1
235
236#define STM32_HAS_TIM17 TRUE
237#define STM32_TIM17_IS_32BITS FALSE
238#define STM32_TIM17_CHANNELS 1
239
240#define STM32_HAS_TIM18 TRUE
241#define STM32_TIM18_IS_32BITS FALSE
242#define STM32_TIM18_CHANNELS 0
243
244#define STM32_HAS_TIM19 TRUE
245#define STM32_TIM19_IS_32BITS FALSE
246#define STM32_TIM19_CHANNELS 4
247
248#define STM32_HAS_TIM1 FALSE
249#define STM32_HAS_TIM8 FALSE
250#define STM32_HAS_TIM9 FALSE
251#define STM32_HAS_TIM10 FALSE
252#define STM32_HAS_TIM11 FALSE
253#define STM32_HAS_TIM20 FALSE
254#define STM32_HAS_TIM21 FALSE
255#define STM32_HAS_TIM22 FALSE
256
257/* USART attributes.*/
258#define STM32_HAS_USART1 TRUE
259#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
260#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
261
262#define STM32_HAS_USART2 TRUE
263#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
264#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
265
266#define STM32_HAS_USART3 TRUE
267#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
268#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
269
270#define STM32_HAS_UART4 FALSE
271#define STM32_HAS_UART5 FALSE
272#define STM32_HAS_USART6 FALSE
273#define STM32_HAS_UART7 FALSE
274#define STM32_HAS_UART8 FALSE
275#define STM32_HAS_LPUART1 FALSE
276
277/* USB attributes.*/
278#define STM32_HAS_USB TRUE
279#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
280#define STM32_USB_PMA_SIZE 512
281#define STM32_USB_HAS_BCDR FALSE
282#define STM32_HAS_OTG1 FALSE
283#define STM32_HAS_OTG2 FALSE
284
285/* IWDG attributes.*/
286#define STM32_HAS_IWDG TRUE
287#define STM32_IWDG_IS_WINDOWED TRUE
288
289/* LTDC attributes.*/
290#define STM32_HAS_LTDC FALSE
291
292/* DMA2D attributes.*/
293#define STM32_HAS_DMA2D FALSE
294
295/* FSMC attributes.*/
296#define STM32_HAS_FSMC FALSE
297
298/* CRC attributes.*/
299#define STM32_HAS_CRC TRUE
300#define STM32_CRC_PROGRAMMABLE TRUE
301#endif /* defined(STM32F373xC) */
302
303/*===========================================================================*/
304/* STM32F378xx. */
305/*===========================================================================*/
306#if defined(STM32F378xx) || defined(__DOXYGEN__)
307/* ADC attributes.*/
308#define STM32_HAS_ADC1 TRUE
309#define STM32_HAS_ADC2 FALSE
310#define STM32_HAS_ADC3 FALSE
311#define STM32_HAS_ADC4 FALSE
312
313#define STM32_HAS_SDADC1 TRUE
314#define STM32_HAS_SDADC2 TRUE
315#define STM32_HAS_SDADC3 TRUE
316
317/* CAN attributes.*/
318#define STM32_HAS_CAN1 TRUE
319#define STM32_HAS_CAN2 FALSE
320#define STM32_HAS_CAN3 FALSE
321#define STM32_CAN_MAX_FILTERS 14
322
323/* DAC attributes.*/
324#define STM32_HAS_DAC1_CH1 TRUE
325#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
326
327#define STM32_HAS_DAC1_CH2 TRUE
328#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
329
330#define STM32_HAS_DAC2_CH1 TRUE
331#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
332
333#define STM32_HAS_DAC2_CH2 FALSE
334
335/* DMA attributes.*/
336#define STM32_ADVANCED_DMA FALSE
337#define STM32_DMA_SUPPORTS_DMAMUX FALSE
338#define STM32_DMA_SUPPORTS_CSELR FALSE
339
340#define STM32_DMA1_NUM_CHANNELS 7
341#define STM32_DMA1_CH1_HANDLER Vector6C
342#define STM32_DMA1_CH2_HANDLER Vector70
343#define STM32_DMA1_CH3_HANDLER Vector74
344#define STM32_DMA1_CH4_HANDLER Vector78
345#define STM32_DMA1_CH5_HANDLER Vector7C
346#define STM32_DMA1_CH6_HANDLER Vector80
347#define STM32_DMA1_CH7_HANDLER Vector84
348#define STM32_DMA1_CH1_NUMBER 11
349#define STM32_DMA1_CH2_NUMBER 12
350#define STM32_DMA1_CH3_NUMBER 13
351#define STM32_DMA1_CH4_NUMBER 14
352#define STM32_DMA1_CH5_NUMBER 15
353#define STM32_DMA1_CH6_NUMBER 16
354#define STM32_DMA1_CH7_NUMBER 17
355
356#define STM32_DMA2_NUM_CHANNELS 5
357#define STM32_DMA2_CH1_HANDLER Vector120
358#define STM32_DMA2_CH2_HANDLER Vector124
359#define STM32_DMA2_CH3_HANDLER Vector128
360#define STM32_DMA2_CH4_HANDLER Vector12C
361#define STM32_DMA2_CH5_HANDLER Vector130
362#define STM32_DMA2_CH1_NUMBER 56
363#define STM32_DMA2_CH2_NUMBER 57
364#define STM32_DMA2_CH3_NUMBER 58
365#define STM32_DMA2_CH4_NUMBER 59
366#define STM32_DMA2_CH5_NUMBER 60
367
368/* ETH attributes.*/
369#define STM32_HAS_ETH FALSE
370
371/* EXTI attributes.*/
372#define STM32_EXTI_NUM_LINES 23
373#define STM32_EXTI_IMR1_MASK 0x1F800000U
374
375/* GPIO attributes.*/
376#define STM32_HAS_GPIOA TRUE
377#define STM32_HAS_GPIOB TRUE
378#define STM32_HAS_GPIOC TRUE
379#define STM32_HAS_GPIOD TRUE
380#define STM32_HAS_GPIOE TRUE
381#define STM32_HAS_GPIOF TRUE
382#define STM32_HAS_GPIOG FALSE
383#define STM32_HAS_GPIOH FALSE
384#define STM32_HAS_GPIOI FALSE
385#define STM32_HAS_GPIOJ FALSE
386#define STM32_HAS_GPIOK FALSE
387#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
388 RCC_AHBENR_GPIOBEN | \
389 RCC_AHBENR_GPIOCEN | \
390 RCC_AHBENR_GPIODEN | \
391 RCC_AHBENR_GPIOEEN | \
392 RCC_AHBENR_GPIOFEN)
393
394/* I2C attributes.*/
395#define STM32_HAS_I2C1 TRUE
396#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
397#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
398
399#define STM32_HAS_I2C2 TRUE
400#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
401#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
402
403#define STM32_HAS_I2C3 FALSE
404#define STM32_HAS_I2C4 FALSE
405
406/* QUADSPI attributes.*/
407#define STM32_HAS_QUADSPI1 FALSE
408
409/* RTC attributes.*/
410#define STM32_HAS_RTC TRUE
411#define STM32_RTC_HAS_SUBSECONDS TRUE
412#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
413#define STM32_RTC_NUM_ALARMS 1
414#define STM32_RTC_STORAGE_SIZE 64
415#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
416#define STM32_RTC_WKUP_HANDLER Vector4C
417#define STM32_RTC_ALARM_HANDLER VectorE4
418#define STM32_RTC_TAMP_STAMP_NUMBER 2
419#define STM32_RTC_WKUP_NUMBER 3
420#define STM32_RTC_ALARM_NUMBER 41
421#define STM32_RTC_ALARM_EXTI 17
422#define STM32_RTC_TAMP_STAMP_EXTI 19
423#define STM32_RTC_WKUP_EXTI 20
424#define STM32_RTC_IRQ_ENABLE() do { \
425 nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
426 nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
427 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
428} while (false)
429
430/* SDIO attributes.*/
431#define STM32_HAS_SDIO FALSE
432
433/* SPI attributes.*/
434#define STM32_HAS_SPI1 TRUE
435#define STM32_SPI1_SUPPORTS_I2S TRUE
436#define STM32_SPI1_I2S_FULLDUPLEX FALSE
437#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
438#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
439
440#define STM32_HAS_SPI2 TRUE
441#define STM32_SPI2_SUPPORTS_I2S TRUE
442#define STM32_SPI2_I2S_FULLDUPLEX FALSE
443#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
444#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
445
446#define STM32_HAS_SPI3 TRUE
447#define STM32_SPI3_SUPPORTS_I2S TRUE
448#define STM32_SPI3_I2S_FULLDUPLEX FALSE
449#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
450#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
451
452#define STM32_HAS_SPI4 FALSE
453#define STM32_HAS_SPI5 FALSE
454#define STM32_HAS_SPI6 FALSE
455
456/* TIM attributes.*/
457#define STM32_TIM_MAX_CHANNELS 4
458
459#define STM32_HAS_TIM2 TRUE
460#define STM32_TIM2_IS_32BITS TRUE
461#define STM32_TIM2_CHANNELS 4
462
463#define STM32_HAS_TIM3 TRUE
464#define STM32_TIM3_IS_32BITS FALSE
465#define STM32_TIM3_CHANNELS 4
466
467#define STM32_HAS_TIM4 TRUE
468#define STM32_TIM4_IS_32BITS FALSE
469#define STM32_TIM4_CHANNELS 4
470
471#define STM32_HAS_TIM5 TRUE
472#define STM32_TIM5_IS_32BITS TRUE
473#define STM32_TIM5_CHANNELS 4
474
475#define STM32_HAS_TIM6 TRUE
476#define STM32_TIM6_IS_32BITS FALSE
477#define STM32_TIM6_CHANNELS 0
478
479#define STM32_HAS_TIM7 TRUE
480#define STM32_TIM7_IS_32BITS FALSE
481#define STM32_TIM7_CHANNELS 0
482
483#define STM32_HAS_TIM12 TRUE
484#define STM32_TIM12_IS_32BITS FALSE
485#define STM32_TIM12_CHANNELS 2
486
487#define STM32_HAS_TIM13 TRUE
488#define STM32_TIM13_IS_32BITS FALSE
489#define STM32_TIM13_CHANNELS 1
490
491#define STM32_HAS_TIM14 TRUE
492#define STM32_TIM14_IS_32BITS FALSE
493#define STM32_TIM14_CHANNELS 1
494
495#define STM32_HAS_TIM15 TRUE
496#define STM32_TIM15_IS_32BITS FALSE
497#define STM32_TIM15_CHANNELS 2
498
499#define STM32_HAS_TIM16 TRUE
500#define STM32_TIM16_IS_32BITS FALSE
501#define STM32_TIM16_CHANNELS 1
502
503#define STM32_HAS_TIM17 TRUE
504#define STM32_TIM17_IS_32BITS FALSE
505#define STM32_TIM17_CHANNELS 1
506
507#define STM32_HAS_TIM18 TRUE
508#define STM32_TIM18_IS_32BITS FALSE
509#define STM32_TIM18_CHANNELS 0
510
511#define STM32_HAS_TIM19 TRUE
512#define STM32_TIM19_IS_32BITS FALSE
513#define STM32_TIM19_CHANNELS 4
514
515#define STM32_HAS_TIM1 FALSE
516#define STM32_HAS_TIM8 FALSE
517#define STM32_HAS_TIM9 FALSE
518#define STM32_HAS_TIM10 FALSE
519#define STM32_HAS_TIM11 FALSE
520#define STM32_HAS_TIM20 FALSE
521#define STM32_HAS_TIM21 FALSE
522#define STM32_HAS_TIM22 FALSE
523
524/* USART attributes.*/
525#define STM32_HAS_USART1 TRUE
526#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
527#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
528
529#define STM32_HAS_USART2 TRUE
530#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
531#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
532
533#define STM32_HAS_USART3 TRUE
534#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
535#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
536
537#define STM32_HAS_UART4 FALSE
538#define STM32_HAS_UART5 FALSE
539#define STM32_HAS_USART6 FALSE
540#define STM32_HAS_UART7 FALSE
541#define STM32_HAS_UART8 FALSE
542#define STM32_HAS_LPUART1 FALSE
543
544/* USB attributes.*/
545#define STM32_HAS_USB FALSE
546#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
547#define STM32_USB_PMA_SIZE 512
548#define STM32_HAS_OTG1 FALSE
549#define STM32_HAS_OTG2 FALSE
550
551/* IWDG attributes.*/
552#define STM32_HAS_IWDG TRUE
553#define STM32_IWDG_IS_WINDOWED TRUE
554
555/* LTDC attributes.*/
556#define STM32_HAS_LTDC FALSE
557
558/* DMA2D attributes.*/
559#define STM32_HAS_DMA2D FALSE
560
561/* FSMC attributes.*/
562#define STM32_HAS_FSMC FALSE
563
564/* CRC attributes.*/
565#define STM32_HAS_CRC TRUE
566#define STM32_CRC_PROGRAMMABLE TRUE
567#endif /* defined(STM32F378xx) */
568/** @} */
569
570#endif /* STM32_REGISTRY_H */
571
572/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 09:23:35 +0100