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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F37x/hal_lld.h
19 * @brief STM32F37x HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32F373xC for Analog & DSP devices.
30 * - STM32F378xx for Analog & DSP devices.
31 * .
32 *
33 * @addtogroup HAL
34 * @{
35 */
36
37#ifndef HAL_LLD_H
38#define HAL_LLD_H
39
40/*===========================================================================*/
41/* Driver constants. */
42/*===========================================================================*/
43
44/**
45 * @name Platform identification macros
46 * @{
47 */
48#if defined(STM32F373xC) || defined(__DOXYGEN__)
49#define PLATFORM_NAME "STM32F373xC Analog & DSP"
50
51#elif defined(STM32F378xx)
52#define PLATFORM_NAME "STM32F378xx Analog & DSP"
53
54#else
55#error "STM32F7x device not specified"
56#endif
57
58/**
59 * @brief Sub-family identifier.
60 */
61#if !defined(STM32F37X) || defined(__DOXYGEN__)
62#define STM32F37X
63#endif
64/** @} */
65
66/**
67 * @name Absolute Maximum Ratings
68 * @{
69 */
70/**
71 * @brief Maximum system clock frequency.
72 */
73#define STM32_SYSCLK_MAX 72000000
74
75/**
76 * @brief Maximum HSE clock frequency.
77 */
78#define STM32_HSECLK_MAX 32000000
79
80/**
81 * @brief Minimum HSE clock frequency.
82 */
83#define STM32_HSECLK_MIN 1000000
84
85/**
86 * @brief Maximum LSE clock frequency.
87 */
88#define STM32_LSECLK_MAX 1000000
89
90/**
91 * @brief Minimum LSE clock frequency.
92 */
93#define STM32_LSECLK_MIN 32768
94
95/**
96 * @brief Maximum PLLs input clock frequency.
97 */
98#define STM32_PLLIN_MAX 24000000
99
100/**
101 * @brief Minimum PLLs input clock frequency.
102 */
103#define STM32_PLLIN_MIN 1000000
104
105/**
106 * @brief Maximum PLL output clock frequency.
107 */
108#define STM32_PLLOUT_MAX 72000000
109
110/**
111 * @brief Minimum PLL output clock frequency.
112 */
113#define STM32_PLLOUT_MIN 16000000
114
115/**
116 * @brief Maximum APB1 clock frequency.
117 */
118#define STM32_PCLK1_MAX 36000000
119
120/**
121 * @brief Maximum APB2 clock frequency.
122 */
123#define STM32_PCLK2_MAX 72000000
124
125/**
126 * @brief Maximum ADC clock frequency.
127 */
128#define STM32_ADCCLK_MAX 14000000
129
130/**
131 * @brief Minimum ADC clock frequency.
132 */
133#define STM32_ADCCLK_MIN 600000
134
135/**
136 * @brief Maximum SDADC clock frequency in fast mode.
137 */
138#define STM32_SDADCCLK_FAST_MAX 6000000
139
140/**
141 * @brief Maximum SDADC clock frequency in slow mode.
142 */
143#define STM32_SDADCCLK_SLOW_MAX 1500000
144
145/**
146 * @brief Minimum SDADC clock frequency.
147 */
148#define STM32_SDADCCLK_MIN 500000
149/** @} */
150
151/**
152 * @name Internal clock sources
153 * @{
154 */
155#define STM32_HSICLK 8000000 /**< High speed internal clock. */
156#define STM32_LSICLK 40000 /**< Low speed internal clock. */
157/** @} */
158
159/**
160 * @name PWR_CR register bits definitions
161 * @{
162 */
163#define STM32_PLS_MASK (7U << 5) /**< PLS bits mask. */
164#define STM32_PLS_LEV0 (0U << 5) /**< PVD level 0. */
165#define STM32_PLS_LEV1 (1U << 5) /**< PVD level 1. */
166#define STM32_PLS_LEV2 (2U << 5) /**< PVD level 2. */
167#define STM32_PLS_LEV3 (3U << 5) /**< PVD level 3. */
168#define STM32_PLS_LEV4 (4U << 5) /**< PVD level 4. */
169#define STM32_PLS_LEV5 (5U << 5) /**< PVD level 5. */
170#define STM32_PLS_LEV6 (6U << 5) /**< PVD level 6. */
171#define STM32_PLS_LEV7 (7U << 5) /**< PVD level 7. */
172/** @} */
173
174/**
175 * @name RCC_CFGR register bits definitions
176 * @{
177 */
178#define STM32_SW_HSI (0U << 0) /**< SYSCLK source is HSI. */
179#define STM32_SW_HSE (1U << 0) /**< SYSCLK source is HSE. */
180#define STM32_SW_PLL (2U << 0) /**< SYSCLK source is PLL. */
181
182#define STM32_HPRE_DIV1 (0U << 4) /**< SYSCLK divided by 1. */
183#define STM32_HPRE_DIV2 (8u << 4) /**< SYSCLK divided by 2. */
184#define STM32_HPRE_DIV4 (9U << 4) /**< SYSCLK divided by 4. */
185#define STM32_HPRE_DIV8 (10U << 4) /**< SYSCLK divided by 8. */
186#define STM32_HPRE_DIV16 (11U << 4) /**< SYSCLK divided by 16. */
187#define STM32_HPRE_DIV64 (12U << 4) /**< SYSCLK divided by 64. */
188#define STM32_HPRE_DIV128 (13U << 4) /**< SYSCLK divided by 128. */
189#define STM32_HPRE_DIV256 (14U << 4) /**< SYSCLK divided by 256. */
190#define STM32_HPRE_DIV512 (15U << 4) /**< SYSCLK divided by 512. */
191
192#define STM32_PPRE1_DIV1 (0U << 8) /**< HCLK divided by 1. */
193#define STM32_PPRE1_DIV2 (4U << 8) /**< HCLK divided by 2. */
194#define STM32_PPRE1_DIV4 (5U << 8) /**< HCLK divided by 4. */
195#define STM32_PPRE1_DIV8 (6U << 8) /**< HCLK divided by 8. */
196#define STM32_PPRE1_DIV16 (7U << 8) /**< HCLK divided by 16. */
197
198#define STM32_PPRE2_DIV1 (0U << 11) /**< HCLK divided by 1. */
199#define STM32_PPRE2_DIV2 (4U << 11) /**< HCLK divided by 2. */
200#define STM32_PPRE2_DIV4 (5U << 11) /**< HCLK divided by 4. */
201#define STM32_PPRE2_DIV8 (6U << 11) /**< HCLK divided by 8. */
202#define STM32_PPRE2_DIV16 (7U << 11) /**< HCLK divided by 16. */
203
204#define STM32_ADCPRE_DIV2 (0U << 14) /**< PPRE2 divided by 2. */
205#define STM32_ADCPRE_DIV4 (1U << 14) /**< PPRE2 divided by 4. */
206#define STM32_ADCPRE_DIV6 (2U << 14) /**< PPRE2 divided by 6. */
207#define STM32_ADCPRE_DIV8 (3U << 14) /**< PPRE2 divided by 8. */
208
209#define STM32_PLLSRC_HSI (0U << 16) /**< PLL clock source is HSI/2. */
210#define STM32_PLLSRC_HSE (1U << 16) /**< PLL clock source is
211 HSE/PREDIV. */
212
213#define STM32_USBPRE_DIV1P5 (0U << 22) /**< USB clock is PLLCLK/1.5. */
214#define STM32_USBPRE_DIV1 (1U << 22) /**< USB clock is PLLCLK/1. */
215
216#define STM32_MCOSEL_NOCLOCK (0U << 24) /**< No clock on MCO pin. */
217#define STM32_MCOSEL_LSI (2U << 24) /**< LSI clock on MCO pin. */
218#define STM32_MCOSEL_LSE (3U << 24) /**< LSE clock on MCO pin. */
219#define STM32_MCOSEL_SYSCLK (4U << 24) /**< SYSCLK on MCO pin. */
220#define STM32_MCOSEL_HSI (5U << 24) /**< HSI clock on MCO pin. */
221#define STM32_MCOSEL_HSE (6U << 24) /**< HSE clock on MCO pin. */
222#define STM32_MCOSEL_PLLDIV2 (7U << 24) /**< PLL/2 clock on MCO pin. */
223
224#define STM32_SDPRE_DIV2 (16U << 27) /**< SYSCLK divided by 2. */
225#define STM32_SDPRE_DIV4 (17U << 27) /**< SYSCLK divided by 4. */
226#define STM32_SDPRE_DIV6 (18U << 27) /**< SYSCLK divided by 6. */
227#define STM32_SDPRE_DIV8 (19U << 27) /**< SYSCLK divided by 8. */
228#define STM32_SDPRE_DIV10 (20U << 27) /**< SYSCLK divided by 10. */
229#define STM32_SDPRE_DIV12 (21U << 27) /**< SYSCLK divided by 12. */
230#define STM32_SDPRE_DIV14 (22U << 27) /**< SYSCLK divided by 14. */
231#define STM32_SDPRE_DIV16 (23U << 27) /**< SYSCLK divided by 16. */
232#define STM32_SDPRE_DIV20 (24U << 27) /**< SYSCLK divided by 20. */
233#define STM32_SDPRE_DIV24 (25U << 27) /**< SYSCLK divided by 24. */
234#define STM32_SDPRE_DIV28 (26U << 27) /**< SYSCLK divided by 28. */
235#define STM32_SDPRE_DIV32 (27U << 27) /**< SYSCLK divided by 32. */
236#define STM32_SDPRE_DIV36 (28U << 27) /**< SYSCLK divided by 36. */
237#define STM32_SDPRE_DIV40 (29U << 27) /**< SYSCLK divided by 40. */
238#define STM32_SDPRE_DIV44 (30U << 27) /**< SYSCLK divided by 44. */
239#define STM32_SDPRE_DIV48 (31U << 27) /**< SYSCLK divided by 48. */
240/** @} */
241
242/**
243 * @name RCC_BDCR register bits definitions
244 * @{
245 */
246#define STM32_RTCSEL_MASK (3U << 8) /**< RTC clock source mask. */
247#define STM32_RTCSEL_NOCLOCK (0U << 8) /**< No clock. */
248#define STM32_RTCSEL_LSE (1U << 8) /**< LSE used as RTC clock. */
249#define STM32_RTCSEL_LSI (2U << 8) /**< LSI used as RTC clock. */
250#define STM32_RTCSEL_HSEDIV (3U << 8) /**< HSE divided by 32 used as
251 RTC clock. */
252/** @} */
253
254/**
255 * @name RCC_CFGR2 register bits definitions
256 * @{
257 */
258#define STM32_PREDIV_MASK (15U << 0) /**< PREDIV divisor mask. */
259/** @} */
260
261/**
262 * @name RCC_CFGR3 register bits definitions
263 * @{
264 */
265#define STM32_USART1SW_MASK (3U << 0) /**< USART1 clock source mask. */
266#define STM32_USART1SW_PCLK (0U << 0) /**< USART1 clock is PCLK. */
267#define STM32_USART1SW_SYSCLK (1U << 0) /**< USART1 clock is SYSCLK. */
268#define STM32_USART1SW_LSE (2U << 0) /**< USART1 clock is LSE. */
269#define STM32_USART1SW_HSI (3U << 0) /**< USART1 clock is HSI. */
270#define STM32_I2C1SW_MASK (1U << 4) /**< I2C1 clock source mask. */
271#define STM32_I2C1SW_HSI (0U << 4) /**< I2C1 clock is HSI. */
272#define STM32_I2C1SW_SYSCLK (1U << 4) /**< I2C1 clock is SYSCLK. */
273#define STM32_I2C2SW_MASK (1U << 5) /**< I2C2 clock source mask. */
274#define STM32_I2C2SW_HSI (0U << 5) /**< I2C2 clock is HSI. */
275#define STM32_I2C2SW_SYSCLK (1U << 5) /**< I2C2 clock is SYSCLK. */
276#define STM32_USART2SW_MASK (3U << 16) /**< USART2 clock source mask. */
277#define STM32_USART2SW_PCLK (0U << 16) /**< USART2 clock is PCLK. */
278#define STM32_USART2SW_SYSCLK (1U << 16) /**< USART2 clock is SYSCLK. */
279#define STM32_USART2SW_LSE (2U << 16) /**< USART2 clock is LSE. */
280#define STM32_USART2SW_HSI (3U << 16) /**< USART2 clock is HSI. */
281#define STM32_USART3SW_MASK (3U << 18) /**< USART3 clock source mask. */
282#define STM32_USART3SW_PCLK (0U << 18) /**< USART3 clock is PCLK. */
283#define STM32_USART3SW_SYSCLK (1U << 18) /**< USART3 clock is SYSCLK. */
284#define STM32_USART3SW_LSE (2U << 18) /**< USART3 clock is LSE. */
285#define STM32_USART3SW_HSI (3U << 18) /**< USART3 clock is HSI. */
286/** @} */
287
288/*===========================================================================*/
289/* Driver pre-compile time settings. */
290/*===========================================================================*/
291
292/**
293 * @name Configuration options
294 * @{
295 */
296/**
297 * @brief Disables the PWR/RCC initialization in the HAL.
298 */
299#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
300#define STM32_NO_INIT FALSE
301#endif
302
303/**
304 * @brief Enables or disables the programmable voltage detector.
305 */
306#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
307#define STM32_PVD_ENABLE FALSE
308#endif
309
310/**
311 * @brief Sets voltage level for programmable voltage detector.
312 */
313#if !defined(STM32_PLS) || defined(__DOXYGEN__)
314#define STM32_PLS STM32_PLS_LEV0
315#endif
316
317/**
318 * @brief Enables or disables the HSI clock source.
319 */
320#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
321#define STM32_HSI_ENABLED TRUE
322#endif
323
324/**
325 * @brief Enables or disables the LSI clock source.
326 */
327#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
328#define STM32_LSI_ENABLED TRUE
329#endif
330
331/**
332 * @brief Enables or disables the HSE clock source.
333 */
334#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
335#define STM32_HSE_ENABLED TRUE
336#endif
337
338/**
339 * @brief Enables or disables the LSE clock source.
340 */
341#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
342#define STM32_LSE_ENABLED FALSE
343#endif
344
345/**
346 * @brief Main clock source selection.
347 * @note If the selected clock source is not the PLL then the PLL is not
348 * initialized and started.
349 * @note The default value is calculated for a 72MHz system clock from
350 * a 8MHz crystal using the PLL.
351 */
352#if !defined(STM32_SW) || defined(__DOXYGEN__)
353#define STM32_SW STM32_SW_PLL
354#endif
355
356/**
357 * @brief Clock source for the PLL.
358 * @note This setting has only effect if the PLL is selected as the
359 * system clock source.
360 * @note The default value is calculated for a 72MHz system clock from
361 * a 8MHz crystal using the PLL.
362 */
363#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
364#define STM32_PLLSRC STM32_PLLSRC_HSE
365#endif
366
367/**
368 * @brief Crystal PLL pre-divider.
369 * @note This setting has only effect if the PLL is selected as the
370 * system clock source.
371 * @note The default value is calculated for a 72MHz system clock from
372 * a 8MHz crystal using the PLL.
373 */
374#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
375#define STM32_PREDIV_VALUE 1
376#endif
377
378/**
379 * @brief PLL multiplier value.
380 * @note The allowed range is 2...16.
381 * @note The default value is calculated for a 72MHz system clock from
382 * a 8MHz crystal using the PLL.
383 */
384#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
385#define STM32_PLLMUL_VALUE 9
386#endif
387
388/**
389 * @brief AHB prescaler value.
390 * @note The default value is calculated for a 72MHz system clock from
391 * a 8MHz crystal using the PLL.
392 */
393#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
394#define STM32_HPRE STM32_HPRE_DIV1
395#endif
396
397/**
398 * @brief APB1 prescaler value.
399 */
400#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
401#define STM32_PPRE1 STM32_PPRE1_DIV2
402#endif
403
404/**
405 * @brief APB2 prescaler value.
406 */
407#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
408#define STM32_PPRE2 STM32_PPRE2_DIV2
409#endif
410
411/**
412 * @brief MCO pin setting.
413 */
414#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
415#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
416#endif
417
418/**
419 * @brief ADC prescaler value.
420 */
421#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
422#define STM32_ADCPRE STM32_ADCPRE_DIV4
423#endif
424
425/**
426 * @brief SDADC prescaler value.
427 */
428#if !defined(STM32_SDPRE) || defined(__DOXYGEN__)
429#define STM32_SDPRE STM32_SDPRE_DIV12
430#endif
431
432/**
433 * @brief USART1 clock source.
434 */
435#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
436#define STM32_USART1SW STM32_USART1SW_PCLK
437#endif
438
439/**
440 * @brief USART2 clock source.
441 */
442#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
443#define STM32_USART2SW STM32_USART2SW_PCLK
444#endif
445
446/**
447 * @brief USART3 clock source.
448 */
449#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
450#define STM32_USART3SW STM32_USART3SW_PCLK
451#endif
452
453/**
454 * @brief I2C1 clock source.
455 */
456#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
457#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
458#endif
459
460/**
461 * @brief I2C2 clock source.
462 */
463#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
464#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
465#endif
466
467/**
468 * @brief RTC clock source.
469 */
470#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
471#define STM32_RTCSEL STM32_RTCSEL_LSI
472#endif
473
474/**
475 * @brief USB clock setting.
476 */
477#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
478#define STM32_USB_CLOCK_REQUIRED TRUE
479#endif
480
481/**
482 * @brief USB prescaler initialization.
483 */
484#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
485#define STM32_USBPRE STM32_USBPRE_DIV1P5
486#endif
487/** @} */
488
489/*===========================================================================*/
490/* Derived constants and error checks. */
491/*===========================================================================*/
492
493/*
494 * Configuration-related checks.
495 */
496#if !defined(STM32F37x_MCUCONF)
497#error "Using a wrong mcuconf.h file, STM32F37x_MCUCONF not defined"
498#endif
499
500/*
501 * HSI related checks.
502 */
503#if STM32_HSI_ENABLED
504#else /* !STM32_HSI_ENABLED */
505
506#if STM32_SW == STM32_SW_HSI
507#error "HSI not enabled, required by STM32_SW"
508#endif
509
510#if STM32_USART1SW == STM32_USART1SW_HSI
511#error "HSI not enabled, required by STM32_USART1SW"
512#endif
513
514#if STM32_USART2SW == STM32_USART2SW_HSI
515#error "HSI not enabled, required by STM32_USART2SW"
516#endif
517
518#if STM32_USART3SW == STM32_USART3SW_HSI
519#error "HSI not enabled, required by STM32_USART3SW"
520#endif
521
522#if STM32_I2C1SW == STM32_I2C1SW_HSI
523#error "HSI not enabled, required by STM32_I2C1SW"
524#endif
525
526#if STM32_I2C2SW == STM32_I2C2SW_HSI
527#error "HSI not enabled, required by STM32_I2C2SW"
528#endif
529
530#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
531#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
532#endif
533
534#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
535 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
536 (STM32_PLLSRC == STM32_PLLSRC_HSI))
537#error "HSI not enabled, required by STM32_MCOSEL"
538#endif
539
540#endif /* !STM32_HSI_ENABLED */
541
542/*
543 * HSE related checks.
544 */
545#if STM32_HSE_ENABLED
546
547#if STM32_HSECLK == 0
548#error "HSE frequency not defined"
549#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
550#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
551#endif
552
553#else /* !STM32_HSE_ENABLED */
554
555#if STM32_SW == STM32_SW_HSE
556#error "HSE not enabled, required by STM32_SW"
557#endif
558
559#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
560#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
561#endif
562
563#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
564 ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
565 (STM32_PLLSRC == STM32_PLLSRC_HSE))
566#error "HSE not enabled, required by STM32_MCOSEL"
567#endif
568
569#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
570#error "HSE not enabled, required by STM32_RTCSEL"
571#endif
572
573#endif /* !STM32_HSE_ENABLED */
574
575/*
576 * LSI related checks.
577 */
578#if STM32_LSI_ENABLED
579#else /* !STM32_LSI_ENABLED */
580
581#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
582#error "LSI not enabled, required by STM32_RTCSEL"
583#endif
584
585#endif /* !STM32_LSI_ENABLED */
586
587/*
588 * LSE related checks.
589 */
590#if STM32_LSE_ENABLED
591
592#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
593#error "STM32_LSECLK not defined"
594#endif
595
596#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
597#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
598#endif
599
600#if !defined(STM32_LSEDRV)
601#error "STM32_LSEDRV not defined"
602#endif
603
604#if (STM32_LSEDRV >> 3) > 3
605#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
606#endif
607
608#if STM32_USART1SW == STM32_USART1SW_LSE
609#error "LSE not enabled, required by STM32_USART1SW"
610#endif
611
612#if STM32_USART2SW == STM32_USART2SW_LSE
613#error "LSE not enabled, required by STM32_USART2SW"
614#endif
615
616#if STM32_USART3SW == STM32_USART3SW_LSE
617#error "LSE not enabled, required by STM32_USART3SW"
618#endif
619
620#else /* !STM32_LSE_ENABLED */
621
622#if STM32_RTCSEL == STM32_RTCSEL_LSE
623#error "LSE not enabled, required by STM32_RTCSEL"
624#endif
625
626#endif /* !STM32_LSE_ENABLED */
627
628/* PLL activation conditions.*/
629#if (STM32_SW == STM32_SW_PLL) || \
630 (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
631 STM32_USB_CLOCK_REQUIRED || \
632 defined(__DOXYGEN__)
633/**
634 * @brief PLL activation flag.
635 */
636#define STM32_ACTIVATE_PLL TRUE
637#else
638#define STM32_ACTIVATE_PLL FALSE
639#endif
640
641/* HSE prescaler setting check.*/
642#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
643#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
644#else
645#error "invalid STM32_PREDIV value specified"
646#endif
647
648/**
649 * @brief PLLMUL field.
650 */
651#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
652 defined(__DOXYGEN__)
653#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
654#else
655#error "invalid STM32_PLLMUL_VALUE value specified"
656#endif
657
658/**
659 * @brief PLL input clock frequency.
660 */
661#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
662#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
663#elif STM32_PLLSRC == STM32_PLLSRC_HSI
664#define STM32_PLLCLKIN (STM32_HSICLK / 2)
665#else
666#error "invalid STM32_PLLSRC value specified"
667#endif
668
669/* PLL input frequency range check.*/
670#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
671#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
672#endif
673
674/**
675 * @brief PLL output clock frequency.
676 */
677#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
678
679/* PLL output frequency range check.*/
680#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
681#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
682#endif
683
684/**
685 * @brief System clock source.
686 */
687#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
688#define STM32_SYSCLK STM32_PLLCLKOUT
689#elif (STM32_SW == STM32_SW_HSI)
690#define STM32_SYSCLK STM32_HSICLK
691#elif (STM32_SW == STM32_SW_HSE)
692#define STM32_SYSCLK STM32_HSECLK
693#else
694#error "invalid STM32_SW value specified"
695#endif
696
697/* Check on the system clock.*/
698#if STM32_SYSCLK > STM32_SYSCLK_MAX
699#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
700#endif
701
702/**
703 * @brief AHB frequency.
704 */
705#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
706#define STM32_HCLK (STM32_SYSCLK / 1)
707#elif STM32_HPRE == STM32_HPRE_DIV2
708#define STM32_HCLK (STM32_SYSCLK / 2)
709#elif STM32_HPRE == STM32_HPRE_DIV4
710#define STM32_HCLK (STM32_SYSCLK / 4)
711#elif STM32_HPRE == STM32_HPRE_DIV8
712#define STM32_HCLK (STM32_SYSCLK / 8)
713#elif STM32_HPRE == STM32_HPRE_DIV16
714#define STM32_HCLK (STM32_SYSCLK / 16)
715#elif STM32_HPRE == STM32_HPRE_DIV64
716#define STM32_HCLK (STM32_SYSCLK / 64)
717#elif STM32_HPRE == STM32_HPRE_DIV128
718#define STM32_HCLK (STM32_SYSCLK / 128)
719#elif STM32_HPRE == STM32_HPRE_DIV256
720#define STM32_HCLK (STM32_SYSCLK / 256)
721#elif STM32_HPRE == STM32_HPRE_DIV512
722#define STM32_HCLK (STM32_SYSCLK / 512)
723#else
724#error "invalid STM32_HPRE value specified"
725#endif
726
727/* AHB frequency check.*/
728#if STM32_HCLK > STM32_SYSCLK_MAX
729#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
730#endif
731
732/**
733 * @brief APB1 frequency.
734 */
735#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
736#define STM32_PCLK1 (STM32_HCLK / 1)
737#elif STM32_PPRE1 == STM32_PPRE1_DIV2
738#define STM32_PCLK1 (STM32_HCLK / 2)
739#elif STM32_PPRE1 == STM32_PPRE1_DIV4
740#define STM32_PCLK1 (STM32_HCLK / 4)
741#elif STM32_PPRE1 == STM32_PPRE1_DIV8
742#define STM32_PCLK1 (STM32_HCLK / 8)
743#elif STM32_PPRE1 == STM32_PPRE1_DIV16
744#define STM32_PCLK1 (STM32_HCLK / 16)
745#else
746#error "invalid STM32_PPRE1 value specified"
747#endif
748
749/* APB1 frequency check.*/
750#if STM32_PCLK1 > STM32_PCLK1_MAX
751#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
752#endif
753
754/**
755 * @brief APB2 frequency.
756 */
757#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
758#define STM32_PCLK2 (STM32_HCLK / 1)
759#elif STM32_PPRE2 == STM32_PPRE2_DIV2
760#define STM32_PCLK2 (STM32_HCLK / 2)
761#elif STM32_PPRE2 == STM32_PPRE2_DIV4
762#define STM32_PCLK2 (STM32_HCLK / 4)
763#elif STM32_PPRE2 == STM32_PPRE2_DIV8
764#define STM32_PCLK2 (STM32_HCLK / 8)
765#elif STM32_PPRE2 == STM32_PPRE2_DIV16
766#define STM32_PCLK2 (STM32_HCLK / 16)
767#else
768#error "invalid STM32_PPRE2 value specified"
769#endif
770
771/* APB2 frequency check.*/
772#if STM32_PCLK2 > STM32_PCLK2_MAX
773#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
774#endif
775
776/**
777 * @brief RTC clock.
778 */
779#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
780#define STM32_RTCCLK STM32_LSECLK
781#elif STM32_RTCSEL == STM32_RTCSEL_LSI
782#define STM32_RTCCLK STM32_LSICLK
783#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
784#define STM32_RTCCLK (STM32_HSECLK / 32)
785#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
786#define STM32_RTCCLK 0
787#else
788#error "invalid source selected for RTC clock"
789#endif
790
791/**
792 * @brief ADC frequency.
793 */
794#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
795#define STM32_ADCCLK (STM32_PCLK2 / 2)
796#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
797#define STM32_ADCCLK (STM32_PCLK2 / 4)
798#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
799#define STM32_ADCCLK (STM32_PCLK2 / 6)
800#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
801#define STM32_ADCCLK (STM32_PCLK2 / 8)
802#else
803#error "invalid STM32_ADCPRE value specified"
804#endif
805
806/* ADC maximum frequency check.*/
807#if STM32_ADC_USE_ADC1 && (STM32_ADCCLK > STM32_ADCCLK_MAX)
808#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
809#endif
810
811/* ADC minimum frequency check.*/
812#if STM32_ADC_USE_ADC1 && (STM32_ADCCLK < STM32_ADCCLK_MIN)
813#error "STM32_ADCCLK exceeding minimum frequency (STM32_ADCCLK_MIN)"
814#endif
815
816/**
817 * @brief SDADC frequency.
818 */
819#if (STM32_SDPRE == STM32_SDPRE_DIV2) || defined(__DOXYGEN__)
820#define STM32_SDADCCLK (STM32_SYSCLK / 2)
821#elif (STM32_SDPRE == STM32_SDPRE_DIV4) || defined(__DOXYGEN__)
822#define STM32_SDADCCLK (STM32_SYSCLK / 4)
823#elif (STM32_SDPRE == STM32_SDPRE_DIV6) || defined(__DOXYGEN__)
824#define STM32_SDADCCLK (STM32_SYSCLK / 6)
825#elif (STM32_SDPRE == STM32_SDPRE_DIV8) || defined(__DOXYGEN__)
826#define STM32_SDADCCLK (STM32_SYSCLK / 8)
827#elif (STM32_SDPRE == STM32_SDPRE_DIV10) || defined(__DOXYGEN__)
828#define STM32_SDADCCLK (STM32_SYSCLK / 10)
829#elif (STM32_SDPRE == STM32_SDPRE_DIV12) || defined(__DOXYGEN__)
830#define STM32_SDADCCLK (STM32_SYSCLK / 12)
831#elif (STM32_SDPRE == STM32_SDPRE_DIV14) || defined(__DOXYGEN__)
832#define STM32_SDADCCLK (STM32_SYSCLK / 14)
833#elif (STM32_SDPRE == STM32_SDPRE_DIV16) || defined(__DOXYGEN__)
834#define STM32_SDADCCLK (STM32_SYSCLK / 16)
835#elif (STM32_SDPRE == STM32_SDPRE_DIV20) || defined(__DOXYGEN__)
836#define STM32_SDADCCLK (STM32_SYSCLK / 20)
837#elif (STM32_SDPRE == STM32_SDPRE_DIV24) || defined(__DOXYGEN__)
838#define STM32_SDADCCLK (STM32_SYSCLK / 24)
839#elif (STM32_SDPRE == STM32_SDPRE_DIV28) || defined(__DOXYGEN__)
840#define STM32_SDADCCLK (STM32_SYSCLK / 28)
841#elif (STM32_SDPRE == STM32_SDPRE_DIV32) || defined(__DOXYGEN__)
842#define STM32_SDADCCLK (STM32_SYSCLK / 32)
843#elif (STM32_SDPRE == STM32_SDPRE_DIV36) || defined(__DOXYGEN__)
844#define STM32_SDADCCLK (STM32_SYSCLK / 36)
845#elif (STM32_SDPRE == STM32_SDPRE_DIV40) || defined(__DOXYGEN__)
846#define STM32_SDADCCLK (STM32_SYSCLK / 40)
847#elif (STM32_SDPRE == STM32_SDPRE_DIV44) || defined(__DOXYGEN__)
848#define STM32_SDADCCLK (STM32_SYSCLK / 44)
849#elif (STM32_SDPRE == STM32_SDPRE_DIV48) || defined(__DOXYGEN__)
850#define STM32_SDADCCLK (STM32_SYSCLK / 48)
851#else
852#error "invalid STM32_SDPRE value specified"
853#endif
854
855/* SDADC maximum frequency check.*/
856#if (STM32_ADC_USE_SDADC1 || \
857 STM32_ADC_USE_SDADC2 || \
858 STM32_ADC_USE_SDADC3) && (STM32_SDADCCLK > STM32_SDADCCLK_FAST_MAX)
859#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_FAST_MAX)"
860#endif
861
862/* SDADC minimum frequency check.*/
863#if (STM32_ADC_USE_SDADC1 || \
864 STM32_ADC_USE_SDADC2 || \
865 STM32_ADC_USE_SDADC3) && \
866 (STM32_SDADCCLK < STM32_SDADCCLK_MIN)
867#error "STM32_SDADCCLK exceeding maximum frequency (STM32_SDADCCLK_MIN)"
868#endif
869
870/**
871 * @brief I2C1 frequency.
872 */
873#if STM32_I2C1SW == STM32_I2C1SW_HSI
874#define STM32_I2C1CLK STM32_HSICLK
875#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
876#define STM32_I2C1CLK STM32_SYSCLK
877#else
878#error "invalid source selected for I2C1 clock"
879#endif
880
881/**
882 * @brief I2C2 frequency.
883 */
884#if STM32_I2C2SW == STM32_I2C2SW_HSI
885#define STM32_I2C2CLK STM32_HSICLK
886#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
887#define STM32_I2C2CLK STM32_SYSCLK
888#else
889#error "invalid source selected for I2C2 clock"
890#endif
891
892/**
893 * @brief USART1 frequency.
894 */
895#if STM32_USART1SW == STM32_USART1SW_PCLK
896#define STM32_USART1CLK STM32_PCLK2
897#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
898#define STM32_USART1CLK STM32_SYSCLK
899#elif STM32_USART1SW == STM32_USART1SW_LSE
900#define STM32_USART1CLK STM32_LSECLK
901#elif STM32_USART1SW == STM32_USART1SW_HSI
902#define STM32_USART1CLK STM32_HSICLK
903#else
904#error "invalid source selected for USART1 clock"
905#endif
906
907/**
908 * @brief USART2 frequency.
909 */
910#if STM32_USART2SW == STM32_USART2SW_PCLK
911#define STM32_USART2CLK STM32_PCLK1
912#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
913#define STM32_USART2CLK STM32_SYSCLK
914#elif STM32_USART2SW == STM32_USART2SW_LSE
915#define STM32_USART2CLK STM32_LSECLK
916#elif STM32_USART2SW == STM32_USART2SW_HSI
917#define STM32_USART2CLK STM32_HSICLK
918#else
919#error "invalid source selected for USART2 clock"
920#endif
921
922/**
923 * @brief USART3 frequency.
924 */
925#if STM32_USART3SW == STM32_USART3SW_PCLK
926#define STM32_USART3CLK STM32_PCLK1
927#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
928#define STM32_USART3CLK STM32_SYSCLK
929#elif STM32_USART3SW == STM32_USART3SW_LSE
930#define STM32_USART3CLK STM32_LSECLK
931#elif STM32_USART3SW == STM32_USART3SW_HSI
932#define STM32_USART3CLK STM32_HSICLK
933#else
934#error "invalid source selected for USART3 clock"
935#endif
936
937/**
938 * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14, 18 frequency.
939 */
940#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
941#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
942#else
943#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
944#endif
945
946/**
947 * @brief Timers 15, 16, 17, 19 frequency.
948 */
949#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
950#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
951#else
952#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
953#endif
954
955/**
956 * @brief USB frequency.
957 */
958#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
959#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
960#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
961#define STM32_USBCLK STM32_PLLCLKOUT
962#else
963#error "invalid STM32_USBPRE value specified"
964#endif
965
966/**
967 * @brief Flash settings.
968 */
969#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
970#define STM32_FLASHBITS 0x00000010
971#elif STM32_HCLK <= 48000000
972#define STM32_FLASHBITS 0x00000011
973#else
974#define STM32_FLASHBITS 0x00000012
975#endif
976
977/*===========================================================================*/
978/* Driver data structures and types. */
979/*===========================================================================*/
980
981/*===========================================================================*/
982/* Driver macros. */
983/*===========================================================================*/
984
985/*===========================================================================*/
986/* External declarations. */
987/*===========================================================================*/
988
989/* Various helpers.*/
990#include "nvic.h"
991#include "cache.h"
992#include "mpu_v7m.h"
993#include "stm32_registry.h"
994#include "stm32_isr.h"
995#include "stm32_dma.h"
996#include "stm32_exti.h"
997#include "stm32_rcc.h"
998#include "stm32_tim.h"
999
1000#ifdef __cplusplus
1001extern "C" {
1002#endif
1003 void hal_lld_init(void);
1004 void stm32_clock_init(void);
1005#ifdef __cplusplus
1006}
1007#endif
1008
1009#endif /* HAL_LLD_H */
1010
1011/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 15:32:29 +0100