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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.c311
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.h2181
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/platform.mk49
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.c176
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.h340
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h1700
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_registry.h1107
7 files changed, 5864 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.c
new file mode 100644
index 000000000..1b4ee1329
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -0,0 +1,311 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/hal_lld.c
19 * @brief STM32F7xx HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/**
36 * @brief CMSIS system core clock variable.
37 * @note It is declared in system_stm32f7xx.h.
38 */
39uint32_t SystemCoreClock = STM32_HCLK;
40
41/*===========================================================================*/
42/* Driver local variables and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver local functions. */
47/*===========================================================================*/
48
49/**
50 * @brief Initializes the backup domain.
51 * @note WARNING! Changing clock source impossible without resetting
52 * of the whole BKP domain.
53 */
54static void hal_lld_backup_domain_init(void) {
55
56 /* Backup domain access enabled and left open.*/
57 PWR->CR1 |= PWR_CR1_DBP;
58
59 /* Reset BKP domain if different clock source selected.*/
60 if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
61 /* Backup domain reset.*/
62 RCC->BDCR = RCC_BDCR_BDRST;
63 RCC->BDCR = 0;
64 }
65
66#if STM32_LSE_ENABLED
67#if defined(STM32_LSE_BYPASS)
68 /* LSE Bypass.*/
69 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
70#else
71 /* No LSE Bypass.*/
72 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
73#endif
74 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
75 ; /* Waits until LSE is stable. */
76#endif
77
78#if HAL_USE_RTC
79 /* If the backup domain hasn't been initialized yet then proceed with
80 initialization.*/
81 if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
82 /* Selects clock source.*/
83 RCC->BDCR |= STM32_RTCSEL;
84
85 /* RTC clock enabled.*/
86 RCC->BDCR |= RCC_BDCR_RTCEN;
87 }
88#endif /* HAL_USE_RTC */
89
90#if STM32_BKPRAM_ENABLE
91 rccEnableBKPSRAM(true);
92
93 PWR->CSR1 |= PWR_CSR1_BRE;
94 while ((PWR->CSR1 & PWR_CSR1_BRR) == 0)
95 ; /* Waits until the regulator is stable */
96#else
97 PWR->CSR1 &= ~PWR_CSR1_BRE;
98#endif /* STM32_BKPRAM_ENABLE */
99}
100
101/*===========================================================================*/
102/* Driver interrupt handlers. */
103/*===========================================================================*/
104
105/*===========================================================================*/
106/* Driver exported functions. */
107/*===========================================================================*/
108
109/**
110 * @brief Low level HAL driver initialization.
111 *
112 * @notapi
113 */
114void hal_lld_init(void) {
115
116 /* Reset of all peripherals. AHB3 is not reseted because it could have
117 been initialized in the board initialization file (board.c).
118 Note, GPIOs are not reset because initialized before this point in
119 board files.*/
120 rccResetAHB1(~STM32_GPIO_EN_MASK);
121 rccResetAHB2(~0);
122 rccResetAPB1(~RCC_APB1RSTR_PWRRST);
123 rccResetAPB2(~0);
124
125 /* Initializes the backup domain.*/
126 hal_lld_backup_domain_init();
127
128 /* DMA subsystems initialization.*/
129#if defined(STM32_DMA_REQUIRED)
130 dmaInit();
131#endif
132
133 /* IRQ subsystem initialization.*/
134 irqInit();
135
136#if STM32_SRAM2_NOCACHE
137 /* The SRAM2 bank can optionally made a non cache-able area for use by
138 DMA engines.*/
139 mpuConfigureRegion(MPU_REGION_7,
140 SRAM2_BASE,
141 MPU_RASR_ATTR_AP_RW_RW |
142 MPU_RASR_ATTR_NON_CACHEABLE |
143 MPU_RASR_SIZE_16K |
144 MPU_RASR_ENABLE);
145 mpuEnable(MPU_CTRL_PRIVDEFENA);
146
147 /* Invalidating data cache to make sure that the MPU settings are taken
148 immediately.*/
149 SCB_CleanInvalidateDCache();
150#endif
151
152 /* Programmable voltage detector enable.*/
153#if STM32_PVD_ENABLE
154 PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK);
155#endif /* STM32_PVD_ENABLE */
156}
157
158/**
159 * @brief STM32F2xx clocks and PLL initialization.
160 * @note All the involved constants come from the file @p board.h.
161 * @note This function should be invoked just after the system reset.
162 *
163 * @special
164 */
165void stm32_clock_init(void) {
166
167#if !STM32_NO_INIT
168 /* PWR clock enabled.*/
169#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCEN)
170 RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN;
171#else
172 RCC->APB1ENR = RCC_APB1ENR_PWREN;
173#endif
174
175 /* PWR initialization.*/
176 PWR->CR1 = STM32_VOS;
177
178 /* HSI setup, it enforces the reset situation in order to handle possible
179 problems with JTAG probes and re-initializations.*/
180 RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
181 while (!(RCC->CR & RCC_CR_HSIRDY))
182 ; /* Wait until HSI is stable. */
183
184 /* HSI is selected as new source without touching the other fields in
185 CFGR. Clearing the register has to be postponed after HSI is the
186 new source.*/
187 RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
188 while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
189 ; /* Wait until HSI is selected. */
190
191 /* Registers finally cleared to reset values.*/
192 RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
193 RCC->CFGR = 0; /* CFGR reset value. */
194
195#if STM32_HSE_ENABLED
196 /* HSE activation.*/
197#if defined(STM32_HSE_BYPASS)
198 /* HSE Bypass.*/
199 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
200#else
201 /* No HSE Bypass.*/
202 RCC->CR |= RCC_CR_HSEON;
203#endif
204 while ((RCC->CR & RCC_CR_HSERDY) == 0)
205 ; /* Waits until HSE is stable. */
206#endif
207
208#if STM32_LSI_ENABLED
209 /* LSI activation.*/
210 RCC->CSR |= RCC_CSR_LSION;
211 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
212 ; /* Waits until LSI is stable. */
213#endif
214
215#if STM32_ACTIVATE_PLL
216 /* PLL activation.*/
217 RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
218 STM32_PLLM;
219 RCC->CR |= RCC_CR_PLLON;
220
221 /* Synchronization with voltage regulator stabilization.*/
222 while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0)
223 ; /* Waits until power regulator is stable. */
224
225#if STM32_OVERDRIVE_REQUIRED
226 /* Overdrive activation performed after activating the PLL in order to save
227 time as recommended in RM in "Entering Over-drive mode" paragraph.*/
228 PWR->CR1 |= PWR_CR1_ODEN;
229 while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
230 ;
231 PWR->CR1 |= PWR_CR1_ODSWEN;
232 while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
233 ;
234#endif /* STM32_OVERDRIVE_REQUIRED */
235
236 /* Waiting for PLL lock.*/
237 while (!(RCC->CR & RCC_CR_PLLRDY))
238 ;
239#endif /* STM32_OVERDRIVE_REQUIRED */
240
241#if STM32_ACTIVATE_PLLI2S
242 /* PLLI2S activation.*/
243 RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SQ | STM32_PLLI2SP |
244 STM32_PLLI2SN;
245 RCC->CR |= RCC_CR_PLLI2SON;
246
247 /* Waiting for PLL lock.*/
248 while (!(RCC->CR & RCC_CR_PLLI2SRDY))
249 ;
250#endif
251
252#if STM32_ACTIVATE_PLLSAI
253 /* PLLSAI activation.*/
254 RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |
255 STM32_PLLSAIN;
256 RCC->CR |= RCC_CR_PLLSAION;
257
258 /* Waiting for PLL lock.*/
259 while (!(RCC->CR & RCC_CR_PLLSAIRDY))
260 ;
261#endif
262
263 /* Other clock-related settings (dividers, MCO etc).*/
264 RCC->CFGR = STM32_MCO2SEL | STM32_MCO2PRE | STM32_MCO1PRE | STM32_I2SSRC |
265 STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
266 STM32_HPRE;
267
268 /* DCKCFGR1 register initialization, note, must take care of the _OFF
269 pseudo settings.*/
270 {
271 uint32_t dckcfgr1 = STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | STM32_PLLSAIDIVR;
272#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
273 dckcfgr1 |= STM32_SAI2SEL;
274#endif
275#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
276 dckcfgr1 |= STM32_SAI1SEL;
277#endif
278#if STM32_TIMPRE_ENABLE == TRUE
279 dckcfgr1 |= RCC_DCKCFGR1_TIMPRE;
280#endif
281 RCC->DCKCFGR1 = dckcfgr1;
282 }
283
284 /* Peripheral clock sources.*/
285 RCC->DCKCFGR2 = STM32_SDMMC2SEL | STM32_SDMMC1SEL | STM32_CK48MSEL |
286 STM32_CECSEL | STM32_LPTIM1SEL | STM32_I2C4SEL |
287 STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
288 STM32_UART8SEL | STM32_UART7SEL | STM32_USART6SEL |
289 STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
290 STM32_USART2SEL | STM32_USART1SEL;
291
292 /* Flash setup.*/
293 FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;
294 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
295 (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
296 }
297
298 /* Switching to the configured clock source if it is different from HSI.*/
299#if (STM32_SW != STM32_SW_HSI)
300 RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
301 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
302 ;
303#endif
304#endif /* STM32_NO_INIT */
305
306 /* SYSCFG clock enabled here because it is a multi-functional unit shared
307 among multiple drivers.*/
308 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
309}
310
311/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.h
new file mode 100644
index 000000000..c38dab80d
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -0,0 +1,2181 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/hal_lld.h
19 * @brief STM32F7xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * - STM32_VDD (as hundredths of Volt).
28 * .
29 * One of the following macros must also be defined:
30 * - STM32F722xx, STM32F723xx very high-performance MCUs.
31 * - STM32F732xx, STM32F733xx very high-performance MCUs.
32 * - STM32F745xx, STM32F746xx, STM32F756xx very high-performance MCUs.
33 * - STM32F765xx, STM32F767xx, STM32F769xx very high-performance MCUs.
34 * - STM32F777xx, STM32F779xx very high-performance MCUs.
35 * .
36 *
37 * @addtogroup HAL
38 * @{
39 */
40
41#ifndef HAL_LLD_H
42#define HAL_LLD_H
43
44#include "stm32_registry.h"
45
46/*===========================================================================*/
47/* Driver constants. */
48/*===========================================================================*/
49
50/**
51 * @brief Defines the support for realtime counters in the HAL.
52 */
53#define HAL_IMPLEMENTS_COUNTERS TRUE
54
55/**
56 * @name Platform identification macros
57 * @{
58 */
59#if defined(STM32F722xx) || defined(__DOXYGEN__)
60#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
61
62#elif defined(STM32F723xx)
63#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
64
65#elif defined(STM32F732xx)
66#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
67
68#elif defined(STM32F733xx)
69#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
70
71#elif defined(STM32F745xx)
72#define PLATFORM_NAME "STM32F745 Very High Performance with DSP and FPU"
73
74#elif defined(STM32F746xx)
75#define PLATFORM_NAME "STM32F746 Very High Performance with DSP and FPU"
76
77#elif defined(STM32F756xx)
78#define PLATFORM_NAME "STM32F756 Very High Performance with DSP and FPU"
79
80#elif defined(STM32F765xx)
81#define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU"
82
83#elif defined(STM32F767xx)
84#define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU"
85
86#elif defined(STM32F769xx)
87#define PLATFORM_NAME "STM32F769 Very High Performance with DSP and DP FPU"
88
89#elif defined(STM32F777xx)
90#define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU"
91
92#elif defined(STM32F779xx)
93#define PLATFORM_NAME "STM32F769 Very High Performance with DSP and DP FPU"
94
95#else
96#error "STM32F7xx device not specified"
97#endif
98/** @} */
99
100/**
101 * @name Sub-family identifier
102 */
103#if !defined(STM32F7XX) || defined(__DOXYGEN__)
104#define STM32F7XX
105#endif
106/** @} */
107
108/**
109 * @name Absolute Maximum Ratings
110 * @{
111 */
112/**
113 * @brief Absolute maximum system clock.
114 */
115#define STM32_SYSCLK_MAX 216000000
116
117/**
118 * @brief Maximum HSE clock frequency.
119 */
120#define STM32_HSECLK_MAX 26000000
121
122/**
123 * @brief Maximum HSE clock frequency using an external source.
124 */
125#define STM32_HSECLK_BYP_MAX 50000000
126
127/**
128 * @brief Minimum HSE clock frequency.
129 */
130#define STM32_HSECLK_MIN 4000000
131
132/**
133 * @brief Minimum HSE clock frequency.
134 */
135#define STM32_HSECLK_BYP_MIN 1000000
136
137/**
138 * @brief Maximum LSE clock frequency.
139 */
140#define STM32_LSECLK_MAX 32768
141
142/**
143 * @brief Maximum LSE clock frequency.
144 */
145#define STM32_LSECLK_BYP_MAX 1000000
146
147/**
148 * @brief Minimum LSE clock frequency.
149 */
150#define STM32_LSECLK_MIN 32768
151
152/**
153 * @brief Maximum PLLs input clock frequency.
154 */
155#define STM32_PLLIN_MAX 2100000
156
157/**
158 * @brief Minimum PLLs input clock frequency.
159 */
160#define STM32_PLLIN_MIN 950000
161
162/**
163 * @brief Maximum PLLs VCO clock frequency.
164 */
165#define STM32_PLLVCO_MAX 432000000
166
167/**
168 * @brief Minimum PLLs VCO clock frequency.
169 */
170#define STM32_PLLVCO_MIN 192000000
171
172/**
173 * @brief Maximum PLL output clock frequency.
174 */
175#define STM32_PLLOUT_MAX 216000000
176
177/**
178 * @brief Minimum PLL output clock frequency.
179 */
180#define STM32_PLLOUT_MIN 24000000
181
182/**
183 * @brief Maximum APB1 clock frequency.
184 */
185#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
186
187/**
188 * @brief Maximum APB2 clock frequency.
189 */
190#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
191
192/**
193 * @brief Maximum SPI/I2S clock frequency.
194 */
195#define STM32_SPII2S_MAX 54000000
196/** @} */
197
198/**
199 * @name Internal clock sources
200 * @{
201 */
202#define STM32_HSICLK 16000000 /**< High speed internal clock. */
203#define STM32_LSICLK 32000 /**< Low speed internal clock. */
204/** @} */
205
206/**
207 * @name PWR_CR register bits definitions
208 * @{
209 */
210#define STM32_VOS_SCALE3 (PWR_CR1_VOS_0)
211#define STM32_VOS_SCALE2 (PWR_CR1_VOS_1)
212#define STM32_VOS_SCALE1 (PWR_CR1_VOS_1 | PWR_CR1_VOS_0)
213
214#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
215#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
216#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
217#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
218#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
219#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
220#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
221#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
222#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
223/** @} */
224
225/**
226 * @name RCC_PLLCFGR register bits definitions
227 * @{
228 */
229#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
230#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
231#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
232#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
233#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
234
235#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
236#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
237/** @} */
238
239/**
240 * @name RCC_CFGR register bits definitions
241 * @{
242 */
243#define STM32_SW_MASK (3 << 0) /**< SW mask. */
244#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
245#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
246#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
247
248#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
249#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
250#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
251#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
252#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
253#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
254#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
255#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
256#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
257#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
258
259#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
260#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
261#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
262#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
263#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
264#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
265
266#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
267#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
268#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
269#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
270#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
271#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
272
273#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
274
275#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
276#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
277#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
278#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
279#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
280
281#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
282#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
283#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
284#define STM32_I2SSRC_OFF (1 << 23) /**< ISS clock not required. */
285
286#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
287#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
288#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
289#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
290#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
291#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
292
293#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
294#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
295#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
296#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
297#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
298#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
299
300#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
301#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
302#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
303#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
304#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
305/** @} */
306
307/**
308 * @name RCC_PLLI2SCFGR register bits definitions
309 * @{
310 */
311#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
312#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
313/** @} */
314
315/**
316 * @name RCC_DCKCFGR1 register bits definitions
317 * @{
318 */
319#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
320#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
321#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
322#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
323#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
324
325#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
326#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
327#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
328#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */
329#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
330
331#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
332#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
333#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
334#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */
335#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
336
337#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
338#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
339#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
340/** @} */
341
342/**
343 * @name RCC_DCKCFGR2 register bits definitions
344 * @{
345 */
346#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */
347#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */
348#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */
349#define STM32_USART1SEL_HSI (2 << 0) /**< USART1 source is HSI. */
350#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */
351
352#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */
353#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */
354#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */
355#define STM32_USART2SEL_HSI (2 << 2) /**< USART2 source is HSI. */
356#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */
357
358#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */
359#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */
360#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */
361#define STM32_USART3SEL_HSI (2 << 4) /**< USART3 source is HSI. */
362#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */
363
364#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */
365#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */
366#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */
367#define STM32_UART4SEL_HSI (2 << 6) /**< UART4 source is HSI. */
368#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */
369
370#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */
371#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */
372#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */
373#define STM32_UART5SEL_HSI (2 << 8) /**< UART5 source is HSI. */
374#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */
375
376#define STM32_USART6SEL_MASK (3 << 10) /**< USART6SEL mask. */
377#define STM32_USART6SEL_PCLK2 (0 << 10) /**< USART6 source is PCLK2. */
378#define STM32_USART6SEL_SYSCLK (1 << 10) /**< USART6 source is SYSCLK. */
379#define STM32_USART6SEL_HSI (2 << 10) /**< USART6 source is HSI. */
380#define STM32_USART6SEL_LSE (3 << 10) /**< USART6 source is LSE. */
381
382#define STM32_UART7SEL_MASK (3 << 12) /**< UART7 mask. */
383#define STM32_UART7SEL_PCLK1 (0 << 12) /**< UART7 source is PCLK1. */
384#define STM32_UART7SEL_SYSCLK (1 << 12) /**< UART7 source is SYSCLK. */
385#define STM32_UART7SEL_HSI (2 << 12) /**< UART7 source is HSI. */
386#define STM32_UART7SEL_LSE (3 << 12) /**< UART7 source is LSE. */
387
388#define STM32_UART8SEL_MASK (3 << 14) /**< UART8 mask. */
389#define STM32_UART8SEL_PCLK1 (0 << 14) /**< UART8 source is PCLK1. */
390#define STM32_UART8SEL_SYSCLK (1 << 14) /**< UART8 source is SYSCLK. */
391#define STM32_UART8SEL_HSI (2 << 14) /**< UART8 source is HSI. */
392#define STM32_UART8SEL_LSE (3 << 14) /**< UART8 source is LSE. */
393
394#define STM32_I2C1SEL_MASK (3 << 16) /**< I2C1SEL mask. */
395#define STM32_I2C1SEL_PCLK1 (0 << 16) /**< I2C1 source is PCLK1. */
396#define STM32_I2C1SEL_SYSCLK (1 << 16) /**< I2C1 source is SYSCLK. */
397#define STM32_I2C1SEL_HSI (2 << 16) /**< I2C1 source is HSI. */
398#define STM32_I2C1SEL_LSE (3 << 16) /**< I2C1 source is LSE. */
399
400#define STM32_I2C2SEL_MASK (3 << 18) /**< I2C2SEL mask. */
401#define STM32_I2C2SEL_PCLK1 (0 << 18) /**< I2C2 source is PCLK1. */
402#define STM32_I2C2SEL_SYSCLK (1 << 18) /**< I2C2 source is SYSCLK. */
403#define STM32_I2C2SEL_HSI (2 << 18) /**< I2C2 source is HSI. */
404#define STM32_I2C2SEL_LSE (3 << 18) /**< I2C2 source is LSE. */
405
406#define STM32_I2C3SEL_MASK (3 << 20) /**< I2C3SEL mask. */
407#define STM32_I2C3SEL_PCLK1 (0 << 20) /**< I2C3 source is PCLK1. */
408#define STM32_I2C3SEL_SYSCLK (1 << 20) /**< I2C3 source is SYSCLK. */
409#define STM32_I2C3SEL_HSI (2 << 20) /**< I2C3 source is HSI. */
410#define STM32_I2C3SEL_LSE (3 << 20) /**< I2C3 source is LSE. */
411
412#define STM32_I2C4SEL_MASK (3 << 22) /**< I2C4SEL mask. */
413#define STM32_I2C4SEL_PCLK1 (0 << 22) /**< I2C4 source is PCLK1. */
414#define STM32_I2C4SEL_SYSCLK (1 << 22) /**< I2C4 source is SYSCLK. */
415#define STM32_I2C4SEL_HSI (2 << 22) /**< I2C4 source is HSI. */
416#define STM32_I2C4SEL_LSE (3 << 22) /**< I2C4 source is LSE. */
417
418#define STM32_LPTIM1SEL_MASK (3 << 24) /**< LPTIM1SEL mask. */
419#define STM32_LPTIM1SEL_PCLK1 (0 << 24) /**< LPTIM1 source is PCLK1. */
420#define STM32_LPTIM1SEL_LSI (1 << 24) /**< LPTIM1 source is LSI. */
421#define STM32_LPTIM1SEL_HSI (2 << 24) /**< LPTIM1 source is HSI. */
422#define STM32_LPTIM1SEL_LSE (3 << 24) /**< LPTIM1 source is LSE. */
423
424#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
425#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
426#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
427
428#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
429#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
430#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
431
432#define STM32_SDMMC1SEL_MASK (1 << 28) /**< SDMMC1SEL mask. */
433#define STM32_SDMMC1SEL_PLL48CLK (0 << 28) /**< SDMMC1 source is PLL48CLK. */
434#define STM32_SDMMC1SEL_SYSCLK (1 << 28) /**< SDMMC1 source is SYSCLK. */
435
436#define STM32_SDMMC2SEL_MASK (1 << 29) /**< SDMMC2SEL mask. */
437#define STM32_SDMMC2SEL_PLL48CLK (0 << 29) /**< SDMMC2 source is PLL48CLK. */
438#define STM32_SDMMC2SEL_SYSCLK (1 << 29) /**< SDMMC2 source is SYSCLK. */
439/** @} */
440
441/**
442 * @name RCC_BDCR register bits definitions
443 * @{
444 */
445#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
446#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
447#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
448#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
449#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
450/** @} */
451
452/*===========================================================================*/
453/* Driver pre-compile time settings. */
454/*===========================================================================*/
455
456/**
457 * @name Configuration options
458 * @{
459 */
460/**
461 * @brief Disables the PWR/RCC initialization in the HAL.
462 */
463#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
464#define STM32_NO_INIT FALSE
465#endif
466
467/**
468 * @brief Enables or disables the programmable voltage detector.
469 */
470#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
471#define STM32_PVD_ENABLE FALSE
472#endif
473
474/**
475 * @brief Sets voltage level for programmable voltage detector.
476 */
477#if !defined(STM32_PLS) || defined(__DOXYGEN__)
478#define STM32_PLS STM32_PLS_LEV0
479#endif
480
481/**
482 * @brief Enables the backup RAM regulator.
483 */
484#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
485#define STM32_BKPRAM_ENABLE FALSE
486#endif
487
488/**
489 * @brief Enables or disables the HSI clock source.
490 */
491#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
492#define STM32_HSI_ENABLED TRUE
493#endif
494
495/**
496 * @brief Enables or disables the LSI clock source.
497 */
498#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
499#define STM32_LSI_ENABLED FALSE
500#endif
501
502/**
503 * @brief Enables or disables the HSE clock source.
504 */
505#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
506#define STM32_HSE_ENABLED TRUE
507#endif
508
509/**
510 * @brief Enables or disables the LSE clock source.
511 */
512#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
513#define STM32_LSE_ENABLED TRUE
514#endif
515
516/**
517 * @brief USB/SDIO clock setting.
518 */
519#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
520#define STM32_CLOCK48_REQUIRED TRUE
521#endif
522
523/**
524 * @brief Main clock source selection.
525 * @note If the selected clock source is not the PLL then the PLL is not
526 * initialized and started.
527 * @note The default value is calculated for a 216MHz system clock from
528 * an external 25MHz HSE clock.
529 */
530#if !defined(STM32_SW) || defined(__DOXYGEN__)
531#define STM32_SW STM32_SW_PLL
532#endif
533
534/**
535 * @brief Clock source for the PLLs.
536 * @note This setting has only effect if the PLL is selected as the
537 * system clock source.
538 * @note The default value is calculated for a 216MHz system clock from
539 * an external 25MHz HSE clock.
540 */
541#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
542#define STM32_PLLSRC STM32_PLLSRC_HSE
543#endif
544
545/**
546 * @brief PLLM divider value.
547 * @note The allowed values are 2..63.
548 * @note The default value is calculated for a 216MHz system clock from
549 * an external 25MHz HSE clock.
550 */
551#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
552#define STM32_PLLM_VALUE 25
553#endif
554
555/**
556 * @brief PLLN multiplier value.
557 * @note The allowed values are 192..432.
558 * @note The default value is calculated for a 216MHz system clock from
559 * an external 25MHz HSE clock.
560 */
561#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
562#define STM32_PLLN_VALUE 432
563#endif
564
565/**
566 * @brief PLLP divider value.
567 * @note The allowed values are 2, 4, 6, 8.
568 * @note The default value is calculated for a 216MHz system clock from
569 * an external 25MHz HSE clock.
570 */
571#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
572#define STM32_PLLP_VALUE 2
573#endif
574
575/**
576 * @brief PLLQ divider value.
577 * @note The allowed values are 2..15.
578 * @note The default value is calculated for a 216MHz system clock from
579 * an external 25MHz HSE clock.
580 */
581#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
582#define STM32_PLLQ_VALUE 9
583#endif
584
585/**
586 * @brief AHB prescaler value.
587 */
588#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
589#define STM32_HPRE STM32_HPRE_DIV1
590#endif
591
592/**
593 * @brief APB1 prescaler value.
594 */
595#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
596#define STM32_PPRE1 STM32_PPRE1_DIV4
597#endif
598
599/**
600 * @brief APB2 prescaler value.
601 */
602#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
603#define STM32_PPRE2 STM32_PPRE2_DIV2
604#endif
605
606/**
607 * @brief RTC clock source.
608 */
609#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
610#define STM32_RTCSEL STM32_RTCSEL_LSE
611#endif
612
613/**
614 * @brief RTC HSE prescaler value.
615 * @note The allowed values are 2..31.
616 */
617#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
618#define STM32_RTCPRE_VALUE 25
619#endif
620
621/**
622 * @brief MCO1 clock source value.
623 * @note The default value outputs HSI clock on MCO1 pin.
624 */
625#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
626#define STM32_MCO1SEL STM32_MCO1SEL_HSI
627#endif
628
629/**
630 * @brief MCO1 prescaler value.
631 * @note The default value outputs HSI clock on MCO1 pin.
632 */
633#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
634#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
635#endif
636
637/**
638 * @brief MCO2 clock source value.
639 * @note The default value outputs SYSCLK / 4 on MCO2 pin.
640 */
641#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
642#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
643#endif
644
645/**
646 * @brief MCO2 prescaler value.
647 * @note The default value outputs SYSCLK / 4 on MCO2 pin.
648 */
649#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
650#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
651#endif
652
653/**
654 * @brief TIM clock prescaler selection.
655 */
656#if !defined(STM32_TIMPRE_ENABLE) || defined(__DOXYGEN__)
657#define STM32_TIMPRE_ENABLE FALSE
658#endif
659
660/**
661 * @brief I2S clock source.
662 */
663#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
664#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
665#endif
666
667/**
668 * @brief PLLI2SN multiplier value.
669 * @note The allowed values are 49..432.
670 */
671#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
672#define STM32_PLLI2SN_VALUE 192
673#endif
674
675/**
676 * @brief PLLI2SP divider value.
677 * @note The allowed values are 2, 4, 6 and 8.
678 */
679#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
680#define STM32_PLLI2SP_VALUE 4
681#endif
682
683/**
684 * @brief PLLI2SQ divider value.
685 * @note The allowed values are 2..15.
686 */
687#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
688#define STM32_PLLI2SQ_VALUE 4
689#endif
690
691/**
692 * @brief PLLI2SDIVQ divider value (SAI clock divider).
693 */
694#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
695#define STM32_PLLI2SDIVQ_VALUE 2
696#endif
697
698/**
699 * @brief PLLI2SR divider value.
700 * @note The allowed values are 2..7.
701 */
702#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
703#define STM32_PLLI2SR_VALUE 4
704#endif
705
706/**
707 * @brief PLLSAIN multiplier value.
708 * @note The allowed values are 49..432.
709 */
710#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
711#define STM32_PLLSAIN_VALUE 192
712#endif
713
714/**
715 * @brief PLLSAIP divider value.
716 * @note The allowed values are 2, 4, 6 and 8.
717 */
718#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
719#define STM32_PLLSAIP_VALUE 4
720#endif
721
722/**
723 * @brief PLLSAIQ divider value.
724 * @note The allowed values are 2..15.
725 */
726#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
727#define STM32_PLLSAIQ_VALUE 4
728#endif
729
730/**
731 * @brief PLLSAIR divider value.
732 * @note The allowed values are 2..7.
733 */
734#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
735#define STM32_PLLSAIR_VALUE 4
736#endif
737
738/**
739 * @brief PLLSAIDIVQ divider value (SAI clock divider).
740 */
741#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
742#define STM32_PLLSAIDIVQ_VALUE 2
743#endif
744
745/**
746 * @brief PLLSAIDIVR divider value (LCD clock divider).
747 */
748#if !defined(STM32_PLLSAIDIVR_VALUE) || defined(__DOXYGEN__)
749#define STM32_PLLSAIDIVR_VALUE 2
750#endif
751
752/**
753 * @brief SAI1SEL value (SAI1 clock source).
754 */
755#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
756#define STM32_SAI1SEL STM32_SAI1SEL_OFF
757#endif
758
759/**
760 * @brief SAI2SEL value (SAI2 clock source).
761 */
762#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
763#define STM32_SAI2SEL STM32_SAI2SEL_OFF
764#endif
765
766/**
767 * @brief LCD-TFT clock enable switch.
768 */
769#if !defined(STM32_LCDTFT_REQUIRED) || defined(__DOXYGEN__)
770#define STM32_LCDTFT_REQUIRED FALSE
771#endif
772
773/**
774 * @brief USART1 clock source.
775 */
776#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
777#define STM32_USART1SEL STM32_USART1SEL_PCLK2
778#endif
779
780/**
781 * @brief USART2 clock source.
782 */
783#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
784#define STM32_USART2SEL STM32_USART2SEL_PCLK1
785#endif
786
787/**
788 * @brief USART3 clock source.
789 */
790#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
791#define STM32_USART3SEL STM32_USART3SEL_PCLK1
792#endif
793
794/**
795 * @brief UART4 clock source.
796 */
797#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
798#define STM32_UART4SEL STM32_UART4SEL_PCLK1
799#endif
800
801/**
802 * @brief UART5 clock source.
803 */
804#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
805#define STM32_UART5SEL STM32_UART5SEL_PCLK1
806#endif
807
808/**
809 * @brief USART6 clock source.
810 */
811#if !defined(STM32_USART6SEL) || defined(__DOXYGEN__)
812#define STM32_USART6SEL STM32_USART6SEL_PCLK2
813#endif
814
815/**
816 * @brief UART7 clock source.
817 */
818#if !defined(STM32_UART7SEL) || defined(__DOXYGEN__)
819#define STM32_UART7SEL STM32_UART7SEL_PCLK1
820#endif
821
822/**
823 * @brief UART8 clock source.
824 */
825#if !defined(STM32_UART8SEL) || defined(__DOXYGEN__)
826#define STM32_UART8SEL STM32_UART8SEL_PCLK1
827#endif
828
829/**
830 * @brief I2C1 clock source.
831 */
832#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
833#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
834#endif
835
836/**
837 * @brief I2C2 clock source.
838 */
839#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
840#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
841#endif
842
843/**
844 * @brief I2C3 clock source.
845 */
846#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
847#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
848#endif
849
850/**
851 * @brief I2C4 clock source.
852 */
853#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
854#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
855#endif
856
857/**
858 * @brief LPTIM1 clock source.
859 */
860#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
861#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
862#endif
863
864/**
865 * @brief CEC clock source.
866 */
867#if !defined(STM32_CECSEL) || defined(__DOXYGEN__)
868#define STM32_CECSEL STM32_CECSEL_LSE
869#endif
870
871/**
872 * @brief PLL48CLK clock source.
873 */
874#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
875#define STM32_CK48MSEL STM32_CK48MSEL_PLL
876#endif
877
878/**
879 * @brief SDMMC1 clock source.
880 */
881#if !defined(STM32_SDMMC1SEL) || defined(__DOXYGEN__)
882#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
883#endif
884
885/**
886 * @brief SDMMC2 clock source.
887 */
888#if !defined(STM32_SDMMC2SEL) || defined(__DOXYGEN__)
889#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK
890#endif
891
892/**
893 * @brief SRAM2 cache-ability.
894 * @note This setting uses the MPU region 7 if at @p TRUE.
895 */
896#if !defined(STM32_SRAM2_NOCACHE) || defined(__DOXYGEN__)
897#define STM32_SRAM2_NOCACHE FALSE
898#endif
899/** @} */
900
901/*===========================================================================*/
902/* Derived constants and error checks. */
903/*===========================================================================*/
904
905/*
906 * Configuration-related checks.
907 */
908#if !defined(STM32F7xx_MCUCONF)
909#error "Using a wrong mcuconf.h file, STM32F7xx_MCUCONF not defined"
910#endif
911
912#if defined(STM32F722xx) && !defined(STM32F722_MCUCONF)
913#error "Using a wrong mcuconf.h file, STM32F722_MCUCONF not defined"
914#endif
915
916#if defined(STM32F732xx) && !defined(STM32F732_MCUCONF)
917#error "Using a wrong mcuconf.h file, STM32F732_MCUCONF not defined"
918#endif
919
920#if defined(STM32F723xx) && !defined(STM32F723_MCUCONF)
921#error "Using a wrong mcuconf.h file, STM32F723_MCUCONF not defined"
922#endif
923
924#if defined(STM32F733xx) && !defined(STM32F733_MCUCONF)
925#error "Using a wrong mcuconf.h file, STM32F733_MCUCONF not defined"
926#endif
927
928#if defined(STM32F746xx) && !defined(STM32F746_MCUCONF)
929#error "Using a wrong mcuconf.h file, STM32F746_MCUCONF not defined"
930#endif
931
932#if defined(STM32F756xx) && !defined(STM32F756_MCUCONF)
933#error "Using a wrong mcuconf.h file, STM32F756_MCUCONF not defined"
934#endif
935
936#if defined(STM32F765xx) && !defined(STM32F765_MCUCONF)
937#error "Using a wrong mcuconf.h file, STM32F765_MCUCONF not defined"
938#endif
939
940#if defined(STM32F767xx) && !defined(STM32F767_MCUCONF)
941#error "Using a wrong mcuconf.h file, STM32F767_MCUCONF not defined"
942#endif
943
944#if defined(STM32F777xx) && !defined(STM32F777_MCUCONF)
945#error "Using a wrong mcuconf.h file, STM32F777_MCUCONF not defined"
946#endif
947
948#if defined(STM32F769xx) && !defined(STM32F769_MCUCONF)
949#error "Using a wrong mcuconf.h file, STM32F769_MCUCONF not defined"
950#endif
951
952#if defined(STM32F779xx) && !defined(STM32F779_MCUCONF)
953#error "Using a wrong mcuconf.h file, STM32F779_MCUCONF not defined"
954#endif
955
956/*
957 * Board file checks.
958 */
959#if !defined(STM32_LSECLK)
960#error "STM32_LSECLK not defined in board.h"
961#endif
962#if !defined(STM32_LSEDRV)
963#error "STM32_LSEDRV not defined in board.h"
964#endif
965#if !defined(STM32_HSECLK)
966#error "STM32_HSECLK not defined in board.h"
967#endif
968#if !defined(STM32_VDD)
969#error "STM32_VDD not defined in board.h"
970#endif
971
972/**
973 * @brief Maximum frequency thresholds and wait states for flash access.
974 * @note The values are valid for 2.7V to 3.6V supply range.
975 */
976#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
977#define STM32_0WS_THRESHOLD 30000000
978#define STM32_1WS_THRESHOLD 60000000
979#define STM32_2WS_THRESHOLD 90000000
980#define STM32_3WS_THRESHOLD 120000000
981#define STM32_4WS_THRESHOLD 150000000
982#define STM32_5WS_THRESHOLD 180000000
983#define STM32_6WS_THRESHOLD 210000000
984#define STM32_7WS_THRESHOLD STM32_SYSCLK_MAX
985#define STM32_8WS_THRESHOLD 0
986#define STM32_9WS_THRESHOLD 0
987
988#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
989#define STM32_0WS_THRESHOLD 24000000
990#define STM32_1WS_THRESHOLD 48000000
991#define STM32_2WS_THRESHOLD 72000000
992#define STM32_3WS_THRESHOLD 96000000
993#define STM32_4WS_THRESHOLD 120000000
994#define STM32_5WS_THRESHOLD 144000000
995#define STM32_6WS_THRESHOLD 168000000
996#define STM32_7WS_THRESHOLD 192000000
997#define STM32_8WS_THRESHOLD STM32_SYSCLK_MAX
998#define STM32_9WS_THRESHOLD 0
999
1000#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
1001#define STM32_0WS_THRESHOLD 22000000
1002#define STM32_1WS_THRESHOLD 44000000
1003#define STM32_2WS_THRESHOLD 66000000
1004#define STM32_3WS_THRESHOLD 88000000
1005#define STM32_4WS_THRESHOLD 110000000
1006#define STM32_5WS_THRESHOLD 132000000
1007#define STM32_6WS_THRESHOLD 154000000
1008#define STM32_7WS_THRESHOLD 176000000
1009#define STM32_8WS_THRESHOLD 198000000
1010#define STM32_9WS_THRESHOLD STM32_SYSCLK_MAX
1011
1012#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
1013#define STM32_0WS_THRESHOLD 20000000
1014#define STM32_1WS_THRESHOLD 40000000
1015#define STM32_2WS_THRESHOLD 60000000
1016#define STM32_3WS_THRESHOLD 80000000
1017#define STM32_4WS_THRESHOLD 100000000
1018#define STM32_5WS_THRESHOLD 120000000
1019#define STM32_6WS_THRESHOLD 140000000
1020#define STM32_7WS_THRESHOLD 160000000
1021#define STM32_8WS_THRESHOLD 180000000
1022#define STM32_9WS_THRESHOLD 0
1023
1024#else
1025#error "invalid VDD voltage specified"
1026#endif
1027
1028/*
1029 * HSI related checks.
1030 */
1031#if STM32_HSI_ENABLED
1032#else /* !STM32_HSI_ENABLED */
1033
1034#if STM32_SW == STM32_SW_HSI
1035#error "HSI not enabled, required by STM32_SW"
1036#endif
1037
1038#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
1039#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
1040#endif
1041
1042#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \
1043 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
1044 (STM32_PLLSRC == STM32_PLLSRC_HSI))
1045#error "HSI not enabled, required by STM32_MCO1SEL"
1046#endif
1047
1048#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
1049 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1050#error "HSI not enabled, required by STM32_MCO2SEL"
1051#endif
1052
1053#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
1054 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1055#error "HSI not enabled, required by STM32_I2SSRC"
1056#endif
1057
1058#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \
1059 (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \
1060 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1061#error "HSI not enabled, required by STM32_SAI1SEL"
1062#endif
1063
1064#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \
1065 (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \
1066 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1067#error "HSI not enabled, required by STM32_SAI2SEL"
1068#endif
1069
1070#if STM32_LCDTFT_REQUIRED && \
1071 (STM32_PLLSRC == STM32_PLLSRC_HSI)
1072#error "HSI not enabled, required by STM32_LCDTFT_REQUIRED"
1073#endif
1074
1075#endif /* !STM32_HSI_ENABLED */
1076
1077/*
1078 * HSE related checks.
1079 */
1080#if STM32_HSE_ENABLED
1081
1082#if STM32_HSECLK == 0
1083#error "HSE frequency not defined"
1084#else /* STM32_HSECLK != 0 */
1085#if defined(STM32_HSE_BYPASS)
1086#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
1087#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
1088#endif
1089#else /* !defined(STM32_HSE_BYPASS) */
1090#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
1091#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
1092#endif
1093#endif /* !defined(STM32_HSE_BYPASS) */
1094#endif /* STM32_HSECLK != 0 */
1095#else /* !STM32_HSE_ENABLED */
1096
1097#if STM32_SW == STM32_SW_HSE
1098#error "HSE not enabled, required by STM32_SW"
1099#endif
1100
1101#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
1102#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
1103#endif
1104
1105#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \
1106 ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
1107 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1108#error "HSE not enabled, required by STM32_MCO1SEL"
1109#endif
1110
1111#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \
1112 ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
1113 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1114#error "HSE not enabled, required by STM32_MCO2SEL"
1115#endif
1116
1117#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
1118 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1119#error "HSE not enabled, required by STM32_I2SSRC"
1120#endif
1121
1122#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) | \
1123 (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \
1124 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1125#error "HSE not enabled, required by STM32_SAI1SEL"
1126#endif
1127
1128#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) | \
1129 (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \
1130 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1131#error "HSE not enabled, required by STM32_SAI2SEL"
1132#endif
1133
1134#if STM32_LCDTFT_REQUIRED && \
1135 (STM32_PLLSRC == STM32_PLLSRC_HSE)
1136#error "HSE not enabled, required by STM32_LCDTFT_REQUIRED"
1137#endif
1138
1139#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1140#error "HSE not enabled, required by STM32_RTCSEL"
1141#endif
1142
1143#endif /* !STM32_HSE_ENABLED */
1144
1145/*
1146 * LSI related checks.
1147 */
1148#if STM32_LSI_ENABLED
1149#else /* !STM32_LSI_ENABLED */
1150
1151#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
1152#error "LSI not enabled, required by STM32_RTCSEL"
1153#endif
1154
1155#endif /* !STM32_LSI_ENABLED */
1156
1157/*
1158 * LSE related checks.
1159 */
1160#if STM32_LSE_ENABLED
1161
1162#if (STM32_LSECLK == 0)
1163#error "LSE frequency not defined"
1164#endif
1165
1166#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
1167#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
1168#endif
1169
1170#if !defined(STM32_LSEDRV)
1171#error "STM32_LSEDRV not defined"
1172#endif
1173
1174#if (STM32_LSEDRV >> 3) > 3
1175#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
1176#endif
1177
1178#else /* !STM32_LSE_ENABLED */
1179
1180#if STM32_RTCSEL == STM32_RTCSEL_LSE
1181#error "LSE not enabled, required by STM32_RTCSEL"
1182#endif
1183
1184#if STM32_MCO1SEL == STM32_MCO1SEL_LSE
1185#error "LSE not enabled, required by STM32_MCO1SEL"
1186#endif
1187
1188#endif /* !STM32_LSE_ENABLED */
1189
1190/**
1191 * @brief STM32_PLLM field.
1192 */
1193#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
1194 defined(__DOXYGEN__)
1195#define STM32_PLLM (STM32_PLLM_VALUE << 0)
1196#else
1197#error "invalid STM32_PLLM_VALUE value specified"
1198#endif
1199
1200/**
1201 * @brief PLLs input clock frequency.
1202 */
1203#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1204#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
1205
1206#elif STM32_PLLSRC == STM32_PLLSRC_HSI
1207#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
1208
1209#else
1210#error "invalid STM32_PLLSRC value specified"
1211#endif
1212
1213/*
1214 * PLLs input frequency range check.
1215 */
1216#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
1217#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1218#endif
1219
1220/*
1221 * PLL enable check.
1222 */
1223#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
1224 (STM32_SW == STM32_SW_PLL) || \
1225 (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
1226 (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
1227 defined(__DOXYGEN__)
1228/**
1229 * @brief PLL activation flag.
1230 */
1231#define STM32_ACTIVATE_PLL TRUE
1232#else
1233#define STM32_ACTIVATE_PLL FALSE
1234#endif
1235
1236/**
1237 * @brief STM32_PLLN field.
1238 */
1239#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
1240 defined(__DOXYGEN__)
1241#define STM32_PLLN (STM32_PLLN_VALUE << 6)
1242#else
1243#error "invalid STM32_PLLN_VALUE value specified"
1244#endif
1245
1246/**
1247 * @brief STM32_PLLP field.
1248 */
1249#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
1250#define STM32_PLLP (0 << 16)
1251
1252#elif STM32_PLLP_VALUE == 4
1253#define STM32_PLLP (1 << 16)
1254
1255#elif STM32_PLLP_VALUE == 6
1256#define STM32_PLLP (2 << 16)
1257
1258#elif STM32_PLLP_VALUE == 8
1259#define STM32_PLLP (3 << 16)
1260
1261#else
1262#error "invalid STM32_PLLP_VALUE value specified"
1263#endif
1264
1265/**
1266 * @brief STM32_PLLQ field.
1267 */
1268#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
1269 defined(__DOXYGEN__)
1270#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
1271#else
1272#error "invalid STM32_PLLQ_VALUE value specified"
1273#endif
1274
1275/**
1276 * @brief PLL VCO frequency.
1277 */
1278#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1279
1280/*
1281 * PLL VCO frequency range check.
1282 */
1283#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
1284#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1285#endif
1286
1287/**
1288 * @brief PLL P output clock frequency.
1289 */
1290#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1291
1292/**
1293 * @brief PLL Q output clock frequency.
1294 */
1295#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
1296
1297/*
1298 * PLL output frequency range check.
1299 */
1300#if (STM32_PLL_P_CLKOUT < STM32_PLLOUT_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLOUT_MAX)
1301#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
1302#endif
1303
1304/**
1305 * @brief System clock source.
1306 */
1307#if STM32_NO_INIT || defined(__DOXYGEN__)
1308#define STM32_SYSCLK STM32_HSICLK
1309
1310#elif (STM32_SW == STM32_SW_HSI)
1311#define STM32_SYSCLK STM32_HSICLK
1312
1313#elif (STM32_SW == STM32_SW_HSE)
1314#define STM32_SYSCLK STM32_HSECLK
1315
1316#elif (STM32_SW == STM32_SW_PLL)
1317#define STM32_SYSCLK STM32_PLL_P_CLKOUT
1318
1319#else
1320#error "invalid STM32_SW value specified"
1321#endif
1322
1323/* Check on the system clock.*/
1324#if STM32_SYSCLK > STM32_SYSCLK_MAX
1325#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1326#endif
1327
1328/* Calculating VOS settings.*/
1329#if STM32_SYSCLK <= 144000000
1330#define STM32_VOS STM32_VOS_SCALE3
1331#define STM32_OVERDRIVE_REQUIRED FALSE
1332
1333#elif STM32_SYSCLK <= 168000000
1334#define STM32_VOS STM32_VOS_SCALE2
1335#define STM32_OVERDRIVE_REQUIRED FALSE
1336
1337#elif STM32_SYSCLK <= 180000000
1338#define STM32_VOS STM32_VOS_SCALE1
1339#define STM32_OVERDRIVE_REQUIRED FALSE
1340
1341#else
1342#define STM32_VOS STM32_VOS_SCALE1
1343#define STM32_OVERDRIVE_REQUIRED TRUE
1344#endif
1345
1346/**
1347 * @brief AHB frequency.
1348 */
1349#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1350#define STM32_HCLK (STM32_SYSCLK / 1)
1351
1352#elif STM32_HPRE == STM32_HPRE_DIV2
1353#define STM32_HCLK (STM32_SYSCLK / 2)
1354
1355#elif STM32_HPRE == STM32_HPRE_DIV4
1356#define STM32_HCLK (STM32_SYSCLK / 4)
1357
1358#elif STM32_HPRE == STM32_HPRE_DIV8
1359#define STM32_HCLK (STM32_SYSCLK / 8)
1360
1361#elif STM32_HPRE == STM32_HPRE_DIV16
1362#define STM32_HCLK (STM32_SYSCLK / 16)
1363
1364#elif STM32_HPRE == STM32_HPRE_DIV64
1365#define STM32_HCLK (STM32_SYSCLK / 64)
1366
1367#elif STM32_HPRE == STM32_HPRE_DIV128
1368#define STM32_HCLK (STM32_SYSCLK / 128)
1369
1370#elif STM32_HPRE == STM32_HPRE_DIV256
1371#define STM32_HCLK (STM32_SYSCLK / 256)
1372
1373#elif STM32_HPRE == STM32_HPRE_DIV512
1374#define STM32_HCLK (STM32_SYSCLK / 512)
1375
1376#else
1377#error "invalid STM32_HPRE value specified"
1378#endif
1379
1380/*
1381 * AHB frequency check.
1382 */
1383#if STM32_HCLK > STM32_SYSCLK_MAX
1384#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1385#endif
1386
1387/**
1388 * @brief APB1 frequency.
1389 */
1390#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1391#define STM32_PCLK1 (STM32_HCLK / 1)
1392
1393#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1394#define STM32_PCLK1 (STM32_HCLK / 2)
1395
1396#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1397#define STM32_PCLK1 (STM32_HCLK / 4)
1398
1399#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1400#define STM32_PCLK1 (STM32_HCLK / 8)
1401
1402#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1403#define STM32_PCLK1 (STM32_HCLK / 16)
1404
1405#else
1406#error "invalid STM32_PPRE1 value specified"
1407#endif
1408
1409/*
1410 * APB1 frequency check.
1411 */
1412#if STM32_PCLK1 > STM32_PCLK1_MAX
1413#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1414#endif
1415
1416/**
1417 * @brief APB2 frequency.
1418 */
1419#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1420#define STM32_PCLK2 (STM32_HCLK / 1)
1421
1422#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1423#define STM32_PCLK2 (STM32_HCLK / 2)
1424
1425#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1426#define STM32_PCLK2 (STM32_HCLK / 4)
1427
1428#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1429#define STM32_PCLK2 (STM32_HCLK / 8)
1430
1431#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1432#define STM32_PCLK2 (STM32_HCLK / 16)
1433
1434#else
1435#error "invalid STM32_PPRE2 value specified"
1436#endif
1437
1438/*
1439 * APB2 frequency check.
1440 */
1441#if STM32_PCLK2 > STM32_PCLK2_MAX
1442#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1443#endif
1444
1445/*
1446 * PLLI2S enable check.
1447 */
1448#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
1449 (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL) || \
1450 (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL) || \
1451 defined(__DOXYGEN__)
1452/**
1453 * @brief PLLI2S activation flag.
1454 */
1455#define STM32_ACTIVATE_PLLI2S TRUE
1456#else
1457#define STM32_ACTIVATE_PLLI2S FALSE
1458#endif
1459
1460/**
1461 * @brief STM32_PLLI2SN field.
1462 */
1463#if ((STM32_PLLI2SN_VALUE >= 49) && (STM32_PLLI2SN_VALUE <= 432)) || \
1464 defined(__DOXYGEN__)
1465#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
1466#else
1467#error "invalid STM32_PLLI2SN_VALUE value specified"
1468#endif
1469
1470/**
1471 * @brief STM32_PLLI2SQ field.
1472 */
1473#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
1474 defined(__DOXYGEN__)
1475#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
1476#else
1477#error "invalid STM32_PLLI2SQ_VALUE value specified"
1478#endif
1479
1480/**
1481 * @brief STM32_PLLI2SR field.
1482 */
1483#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
1484 defined(__DOXYGEN__)
1485#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
1486#else
1487#error "invalid STM32_PLLI2SR_VALUE value specified"
1488#endif
1489
1490/**
1491 * @brief STM32_PLLI2SP field.
1492 */
1493#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
1494#define STM32_PLLI2SP (0 << 16)
1495
1496#elif STM32_PLLI2SP_VALUE == 4
1497#define STM32_PLLI2SP (1 << 16)
1498
1499#elif STM32_PLLI2SP_VALUE == 6
1500#define STM32_PLLI2SP (2 << 16)
1501
1502#elif STM32_PLLI2SP_VALUE == 8
1503#define STM32_PLLI2SP (3 << 16)
1504
1505#else
1506#error "invalid STM32_PLLI2SP_VALUE value specified"
1507#endif
1508
1509/**
1510 * @brief PLLI2S VCO frequency.
1511 */
1512#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
1513
1514/*
1515 * PLLI2S VCO frequency range check.
1516 */
1517#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
1518 (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
1519#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1520#endif
1521
1522/**
1523 * @brief PLLI2S P output clock frequency.
1524 */
1525#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
1526
1527/**
1528 * @brief PLLI2S Q output clock frequency.
1529 */
1530#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
1531
1532/**
1533 * @brief PLLI2S R output clock frequency.
1534 */
1535#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
1536
1537/**
1538 * @brief STM32_PLLI2SDIVQ field.
1539 */
1540#if (STM32_PLLI2SDIVQ_VALUE < 1) || (STM32_PLLI2SDIVQ_VALUE > 32)
1541#error "STM32_PLLI2SDIVQ_VALUE out of acceptable range"
1542#endif
1543#define STM32_PLLI2SDIVQ ((STM32_PLLI2SDIVQ_VALUE - 1) << 0)
1544
1545/**
1546 * @brief PLLI2S Q output clock frequency after divisor.
1547 */
1548#define STM32_PLLI2SDIVQ_CLKOUT (STM32_PLLI2S_Q_CLKOUT / STM32_PLLI2SDIVQ_VALUE)
1549
1550/*
1551 * PLLSAI enable check.
1552 */
1553#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \
1554 STM32_LCDTFT_REQUIRED || \
1555 (STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \
1556 (STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \
1557 defined(__DOXYGEN__)
1558/**
1559 * @brief PLLSAI activation flag.
1560 */
1561#define STM32_ACTIVATE_PLLSAI TRUE
1562#else
1563#define STM32_ACTIVATE_PLLSAI FALSE
1564#endif
1565
1566/**
1567 * @brief STM32_PLLSAIN field.
1568 */
1569#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
1570 defined(__DOXYGEN__)
1571#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
1572#else
1573#error "invalid STM32_PLLSAIN_VALUE value specified"
1574#endif
1575
1576/**
1577 * @brief STM32_PLLSAIQ field.
1578 */
1579#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
1580 defined(__DOXYGEN__)
1581#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
1582#else
1583#error "invalid STM32_PLLSAIR_VALUE value specified"
1584#endif
1585
1586/**
1587 * @brief STM32_PLLSAIR field.
1588 */
1589#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
1590 defined(__DOXYGEN__)
1591#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
1592#else
1593#error "invalid STM32_PLLSAIR_VALUE value specified"
1594#endif
1595
1596/**
1597 * @brief STM32_PLLSAIP field.
1598 */
1599#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
1600#define STM32_PLLSAIP (0 << 16)
1601
1602#elif STM32_PLLSAIP_VALUE == 4
1603#define STM32_PLLSAIP (1 << 16)
1604
1605#elif STM32_PLLSAIP_VALUE == 6
1606#define STM32_PLLSAIP (2 << 16)
1607
1608#elif STM32_PLLSAIP_VALUE == 8
1609#define STM32_PLLSAIP (3 << 16)
1610
1611#else
1612#error "invalid STM32_PLLSAIP_VALUE value specified"
1613#endif
1614
1615/**
1616 * @brief PLLSAI VCO frequency.
1617 */
1618#define STM32_PLLSAIVCO (STM32_PLLCLKIN * STM32_PLLSAIN_VALUE)
1619
1620/*
1621 * PLLSAI VCO frequency range check.
1622 */
1623#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
1624 (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)
1625#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1626#endif
1627
1628/**
1629 * @brief PLLSAI P output clock frequency.
1630 */
1631#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
1632
1633/**
1634 * @brief PLLSAI Q output clock frequency.
1635 */
1636#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
1637
1638/**
1639 * @brief PLLSAI R output clock frequency.
1640 */
1641#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
1642
1643/**
1644 * @brief STM32_PLLSAIDIVQ field.
1645 */
1646#if (STM32_PLLSAIDIVQ_VALUE < 1) || (STM32_PLLSAIDIVQ_VALUE > 32)
1647#error "STM32_PLLSAIDIVQ_VALUE out of acceptable range"
1648#endif
1649#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)
1650
1651/**
1652 * @brief PLLSAI Q output clock frequency after divisor.
1653 */
1654#define STM32_PLLSAIDIVQ_CLKOUT (STM32_PLLSAI_Q_CLKOUT / STM32_PLLSAIDIVQ_VALUE)
1655
1656/*
1657 * STM32_PLLSAIDIVR field.
1658 */
1659#if (STM32_PLLSAIDIVR_VALUE == 2) || defined(__DOXYGEN__)
1660#define STM32_PLLSAIDIVR (0 << 16)
1661
1662#elif STM32_PLLSAIDIVR_VALUE == 4
1663#define STM32_PLLSAIDIVR (1 << 16)
1664
1665#elif STM32_PLLSAIDIVR_VALUE == 8
1666#define STM32_PLLSAIDIVR (2 << 16)
1667
1668#elif STM32_PLLSAIDIVR_VALUE == 16
1669#define STM32_PLLSAIDIVR (3 << 16)
1670
1671#else
1672#error "invalid STM32_PLLSAIDIVR_VALUE value specified"
1673#endif
1674
1675/**
1676 * @brief PLLSAI R output clock frequency after divisor.
1677 */
1678#define STM32_PLLSAIDIVR_CLKOUT (STM32_PLLSAI_R_CLKOUT / STM32_PLLSAIDIVR_VALUE)
1679
1680/**
1681 * @brief MCO1 divider clock.
1682 */
1683#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
1684#define STM32_MCO1DIVCLK STM32_HSICLK
1685
1686#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
1687#define STM32_MCO1DIVCLK STM32_LSECLK
1688
1689#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
1690#define STM32_MCO1DIVCLK STM32_HSECLK
1691
1692#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
1693#define STM32_MCO1DIVCLK STM32_PLL_P_CLKOUT
1694
1695#else
1696#error "invalid STM32_MCO1SEL value specified"
1697#endif
1698
1699/**
1700 * @brief MCO1 output pin clock.
1701 */
1702#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
1703#define STM32_MCO1CLK STM32_MCO1DIVCLK
1704
1705#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
1706#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
1707
1708#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
1709#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
1710
1711#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
1712#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
1713
1714#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
1715#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
1716
1717#else
1718#error "invalid STM32_MCO1PRE value specified"
1719#endif
1720
1721/**
1722 * @brief MCO2 divider clock.
1723 */
1724#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
1725#define STM32_MCO2DIVCLK STM32_HSECLK
1726
1727#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
1728#define STM32_MCO2DIVCLK STM32_PLL_P_CLKOUT
1729
1730#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
1731#define STM32_MCO2DIVCLK STM32_SYSCLK
1732
1733#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
1734#define STM32_MCO2DIVCLK STM32_PLLI2S
1735
1736#else
1737#error "invalid STM32_MCO2SEL value specified"
1738#endif
1739
1740/**
1741 * @brief MCO2 output pin clock.
1742 */
1743#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
1744#define STM32_MCO2CLK STM32_MCO2DIVCLK
1745
1746#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
1747#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
1748
1749#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
1750#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
1751
1752#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
1753#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
1754
1755#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
1756#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
1757
1758#else
1759#error "invalid STM32_MCO2PRE value specified"
1760#endif
1761
1762/**
1763 * @brief RTC HSE divider setting.
1764 */
1765#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
1766 defined(__DOXYGEN__)
1767#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
1768#else
1769#error "invalid STM32_RTCPRE value specified"
1770#endif
1771
1772/**
1773 * @brief HSE divider toward RTC clock.
1774 */
1775#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
1776 defined(__DOXYGEN__)
1777#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
1778#else
1779#error "invalid STM32_RTCPRE value specified"
1780#endif
1781
1782/**
1783 * @brief RTC clock.
1784 */
1785#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
1786#define STM32_RTCCLK 0
1787
1788#elif STM32_RTCSEL == STM32_RTCSEL_LSE
1789#define STM32_RTCCLK STM32_LSECLK
1790
1791#elif STM32_RTCSEL == STM32_RTCSEL_LSI
1792#define STM32_RTCCLK STM32_LSICLK
1793
1794#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1795#define STM32_RTCCLK STM32_HSEDIVCLK
1796
1797#else
1798#error "invalid STM32_RTCSEL value specified"
1799#endif
1800
1801/**
1802 * @brief USART1 frequency.
1803 */
1804#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
1805#define STM32_USART1CLK STM32_PCLK2
1806#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
1807#define STM32_USART1CLK STM32_SYSCLK
1808#elif STM32_USART1SEL == STM32_USART1SEL_HSI
1809#define STM32_USART1CLK STM32_HSICLK
1810#elif STM32_USART1SEL == STM32_USART1SEL_LSE
1811#define STM32_USART1CLK STM32_LSECLK
1812#else
1813#error "invalid source selected for USART1 clock"
1814#endif
1815
1816/**
1817 * @brief USART2 frequency.
1818 */
1819#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
1820#define STM32_USART2CLK STM32_PCLK1
1821#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
1822#define STM32_USART2CLK STM32_SYSCLK
1823#elif STM32_USART2SEL == STM32_USART2SEL_HSI
1824#define STM32_USART2CLK STM32_HSICLK
1825#elif STM32_USART2SEL == STM32_USART2SEL_LSE
1826#define STM32_USART2CLK STM32_LSECLK
1827#else
1828#error "invalid source selected for USART2 clock"
1829#endif
1830
1831/**
1832 * @brief USART3 frequency.
1833 */
1834#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
1835#define STM32_USART3CLK STM32_PCLK1
1836#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
1837#define STM32_USART3CLK STM32_SYSCLK
1838#elif STM32_USART3SEL == STM32_USART3SEL_HSI
1839#define STM32_USART3CLK STM32_HSICLK
1840#elif STM32_USART3SEL == STM32_USART3SEL_LSE
1841#define STM32_USART3CLK STM32_LSECLK
1842#else
1843#error "invalid source selected for USART3 clock"
1844#endif
1845
1846/**
1847 * @brief UART4 frequency.
1848 */
1849#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
1850#define STM32_UART4CLK STM32_PCLK1
1851#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
1852#define STM32_UART4CLK STM32_SYSCLK
1853#elif STM32_UART4SEL == STM32_UART4SEL_HSI
1854#define STM32_UART4CLK STM32_HSICLK
1855#elif STM32_UART4SEL == STM32_UART4SEL_LSE
1856#define STM32_UART4CLK STM32_LSECLK
1857#else
1858#error "invalid source selected for UART4 clock"
1859#endif
1860
1861/**
1862 * @brief UART5 frequency.
1863 */
1864#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
1865#define STM32_UART5CLK STM32_PCLK1
1866#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
1867#define STM32_UART5CLK STM32_SYSCLK
1868#elif STM32_UART5SEL == STM32_UART5SEL_HSI
1869#define STM32_UART5CLK STM32_HSICLK
1870#elif STM32_UART5SEL == STM32_UART5SEL_LSE
1871#define STM32_UART5CLK STM32_LSECLK
1872#else
1873#error "invalid source selected for UART5 clock"
1874#endif
1875
1876/**
1877 * @brief USART6 frequency.
1878 */
1879#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__)
1880#define STM32_USART6CLK STM32_PCLK2
1881#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK
1882#define STM32_USART6CLK STM32_SYSCLK
1883#elif STM32_USART6SEL == STM32_USART6SEL_HSI
1884#define STM32_USART6CLK STM32_HSICLK
1885#elif STM32_USART6SEL == STM32_USART6SEL_LSE
1886#define STM32_USART6CLK STM32_LSECLK
1887#else
1888#error "invalid source selected for USART6 clock"
1889#endif
1890
1891/**
1892 * @brief UART7 frequency.
1893 */
1894#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__)
1895#define STM32_UART7CLK STM32_PCLK1
1896#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK
1897#define STM32_UART7CLK STM32_SYSCLK
1898#elif STM32_UART7SEL == STM32_UART7SEL_HSI
1899#define STM32_UART7CLK STM32_HSICLK
1900#elif STM32_UART7SEL == STM32_UART7SEL_LSE
1901#define STM32_UART7CLK STM32_LSECLK
1902#else
1903#error "invalid source selected for UART7 clock"
1904#endif
1905
1906/**
1907 * @brief UART8 frequency.
1908 */
1909#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__)
1910#define STM32_UART8CLK STM32_PCLK1
1911#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK
1912#define STM32_UART8CLK STM32_SYSCLK
1913#elif STM32_UART8SEL == STM32_UART8SEL_HSI
1914#define STM32_UART8CLK STM32_HSICLK
1915#elif STM32_UART8SEL == STM32_UART8SEL_LSE
1916#define STM32_UART8CLK STM32_LSECLK
1917#else
1918#error "invalid source selected for UART8 clock"
1919#endif
1920
1921/**
1922 * @brief I2C1 frequency.
1923 */
1924#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
1925#define STM32_I2C1CLK STM32_PCLK1
1926#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
1927#define STM32_I2C1CLK STM32_SYSCLK
1928#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI
1929#define STM32_I2C1CLK STM32_HSICLK
1930#else
1931#error "invalid source selected for I2C1 clock"
1932#endif
1933
1934/**
1935 * @brief I2C2 frequency.
1936 */
1937#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
1938#define STM32_I2C2CLK STM32_PCLK1
1939#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
1940#define STM32_I2C2CLK STM32_SYSCLK
1941#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI
1942#define STM32_I2C2CLK STM32_HSICLK
1943#else
1944#error "invalid source selected for I2C2 clock"
1945#endif
1946
1947/**
1948 * @brief I2C3 frequency.
1949 */
1950#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
1951#define STM32_I2C3CLK STM32_PCLK1
1952#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
1953#define STM32_I2C3CLK STM32_SYSCLK
1954#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI
1955#define STM32_I2C3CLK STM32_HSICLK
1956#else
1957#error "invalid source selected for I2C3 clock"
1958#endif
1959
1960/**
1961 * @brief I2C4 frequency.
1962 */
1963#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
1964#define STM32_I2C4CLK STM32_PCLK1
1965#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
1966#define STM32_I2C4CLK STM32_SYSCLK
1967#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI
1968#define STM32_I2C4CLK STM32_HSICLK
1969#else
1970#error "invalid source selected for I2C4 clock"
1971#endif
1972
1973/**
1974 * @brief LPTIM1 frequency.
1975 */
1976#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
1977#define STM32_LPTIM1CLK STM32_PCLK1
1978#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
1979#define STM32_LPTIM1CLK STM32_LSICLK
1980#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI
1981#define STM32_LPTIM1CLK STM32_HSICLK
1982#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
1983#define STM32_LPTIM1CLK STM32_LSECLK
1984#else
1985#error "invalid source selected for LPTIM1 clock"
1986#endif
1987
1988/**
1989 * @brief 48MHz frequency.
1990 */
1991#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
1992#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
1993#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
1994#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
1995#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
1996#else
1997#error "invalid source selected for PLL48CLK clock"
1998#endif
1999#else /* !STM32_CLOCK48_REQUIRED */
2000#define STM32_PLL48CLK 0
2001#endif /* !STM32_CLOCK48_REQUIRED */
2002
2003/**
2004 * @brief I2S frequency.
2005 */
2006#if (STM32_I2SSRC == STM32_I2SSRC_OFF) || defined(__DOXYGEN__)
2007#define STM32_I2SCLK 0
2008#elif STM32_I2SSRC == STM32_I2SSRC_CKIN
2009#define STM32_I2SCLK 0 /* Unknown, would require a board value */
2010#elif STM32_I2SSRC == STM32_I2SSRC_PLLI2S
2011#define STM32_I2SCLK STM32_PLLI2S_R_CLKOUT
2012#else
2013#error "invalid source selected for I2S clock"
2014#endif
2015
2016/**
2017 * @brief SAI1 frequency.
2018 */
2019#if (STM32_SAI1SEL == STM32_SAI1SEL_OFF) || defined(__DOXYGEN__)
2020#define STM32_SAI1CLK 0
2021#elif STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL
2022#define STM32_SAI1CLK STM32_PLLSAIDIVQ_CLKOUT
2023#elif STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL
2024#define STM32_SAI1CLK STM32_PLLI2SDIVQ_CLKOUT
2025#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
2026#define STM32_SAI1CLK 0 /* Unknown, would require a board value */
2027#else
2028#error "invalid source selected for SAI1 clock"
2029#endif
2030
2031/**
2032 * @brief SAI2 frequency.
2033 */
2034#if (STM32_SAI2SEL == STM32_SAI2SEL_OFF) || defined(__DOXYGEN__)
2035#define STM32_SAI2CLK 0
2036#elif STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL
2037#define STM32_SAI2CLK STM32_PLLSAIDIVQ_CLKOUT
2038#elif STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL
2039#define STM32_SAI2CLK STM32_PLLI2SDIVQ_CLKOUT
2040#elif STM32_SAI2SEL == STM32_SAI2SEL_CKIN
2041#define STM32_SAI2CLK 0 /* Unknown, would require a board value */
2042#else
2043#error "invalid source selected for SAI2 clock"
2044#endif
2045
2046/**
2047 * @brief SDMMC1 frequency.
2048 */
2049#if (STM32_SDMMC1SEL == STM32_SDMMC1SEL_PLL48CLK) || defined(__DOXYGEN__)
2050#define STM32_SDMMC1CLK STM32_PLL48CLK
2051#elif STM32_SDMMC1SEL == STM32_SDMMC1SEL_SYSCLK
2052#define STM32_SDMMC1CLK STM32_SYSCLK
2053#else
2054#error "invalid source selected for SDMMC1 clock"
2055#endif
2056
2057/**
2058 * @brief SDMMC2 frequency.
2059 */
2060#if (STM32_SDMMC2SEL == STM32_SDMMC2SEL_PLL48CLK) || defined(__DOXYGEN__)
2061#define STM32_SDMMC2CLK STM32_PLL48CLK
2062#elif STM32_SDMMC2SEL == STM32_SDMMC2SEL_SYSCLK
2063#define STM32_SDMMC2CLK STM32_SYSCLK
2064#else
2065#error "invalid source selected for SDMMC2 clock"
2066#endif
2067
2068/**
2069 * @brief Clock of timers connected to APB1
2070 */
2071#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__)
2072#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
2073#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
2074#else
2075#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
2076#endif
2077#else
2078#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
2079 (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
2080 (STM32_PPRE1 == STM32_PPRE1_DIV4)
2081#define STM32_TIMCLK1 (STM32_HCLK * 1)
2082#else
2083#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
2084#endif
2085#endif
2086
2087/**
2088 * @brief Clock of timers connected to APB2.
2089 */
2090#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__)
2091#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
2092#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
2093#else
2094#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
2095#endif
2096#else
2097#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
2098 (STM32_PPRE2 == STM32_PPRE2_DIV2) || \
2099 (STM32_PPRE2 == STM32_PPRE2_DIV4)
2100#define STM32_TIMCLK2 (STM32_HCLK * 1)
2101#else
2102#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
2103#endif
2104#endif
2105
2106/**
2107 * @brief RNG clock point.
2108 */
2109#define STM32_RNGCLK STM32_PLL48CLK
2110
2111/**
2112 * @brief Flash settings.
2113 */
2114#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
2115#define STM32_FLASHBITS 0x00000000
2116
2117#elif STM32_HCLK <= STM32_1WS_THRESHOLD
2118#define STM32_FLASHBITS 0x00000001
2119
2120#elif STM32_HCLK <= STM32_2WS_THRESHOLD
2121#define STM32_FLASHBITS 0x00000002
2122
2123#elif STM32_HCLK <= STM32_3WS_THRESHOLD
2124#define STM32_FLASHBITS 0x00000003
2125
2126#elif STM32_HCLK <= STM32_4WS_THRESHOLD
2127#define STM32_FLASHBITS 0x00000004
2128
2129#elif STM32_HCLK <= STM32_5WS_THRESHOLD
2130#define STM32_FLASHBITS 0x00000005
2131
2132#elif STM32_HCLK <= STM32_6WS_THRESHOLD
2133#define STM32_FLASHBITS 0x00000006
2134
2135#elif STM32_HCLK <= STM32_7WS_THRESHOLD
2136#define STM32_FLASHBITS 0x00000007
2137
2138#elif STM32_HCLK <= STM32_8WS_THRESHOLD
2139#define STM32_FLASHBITS 0x00000008
2140
2141#elif STM32_HCLK <= STM32_9WS_THRESHOLD
2142#define STM32_FLASHBITS 0x00000009
2143
2144#else
2145#error "invalid frequency at specified VDD level"
2146#endif
2147
2148/*===========================================================================*/
2149/* Driver data structures and types. */
2150/*===========================================================================*/
2151
2152/*===========================================================================*/
2153/* Driver macros. */
2154/*===========================================================================*/
2155
2156/*===========================================================================*/
2157/* External declarations. */
2158/*===========================================================================*/
2159
2160/* Various helpers.*/
2161#include "nvic.h"
2162#include "cache.h"
2163#include "mpu_v7m.h"
2164#include "stm32_isr.h"
2165#include "stm32_dma.h"
2166#include "stm32_exti.h"
2167#include "stm32_rcc.h"
2168#include "stm32_tim.h"
2169
2170#ifdef __cplusplus
2171extern "C" {
2172#endif
2173 void hal_lld_init(void);
2174 void stm32_clock_init(void);
2175#ifdef __cplusplus
2176}
2177#endif
2178
2179#endif /* HAL_LLD_H */
2180
2181/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/platform.mk b/lib/chibios/os/hal/ports/STM32/STM32F7xx/platform.mk
new file mode 100644
index 000000000..f65bc1448
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/platform.mk
@@ -0,0 +1,49 @@
1# Required platform files.
2PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
3 $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/stm32_isr.c \
4 $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c
5
6# Required include directories.
7PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
8 $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx
9
10# Optional platform files.
11ifeq ($(USE_SMART_BUILD),yes)
12
13# Configuration files directory
14ifeq ($(HALCONFDIR),)
15 ifeq ($(CONFDIR),)
16 HALCONFDIR = .
17 else
18 HALCONFDIR := $(CONFDIR)
19 endif
20endif
21
22HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
23
24else
25endif
26
27# Drivers compatible with the platform.
28include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/driver.mk
29include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
30include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
31include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
32include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
33include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
34include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
35include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
36include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
37include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
38include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
39include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
40include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
41include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
42include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
43include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
44include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
45include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
46
47# Shared variables
48ALLCSRC += $(PLATFORMSRC)
49ALLINC += $(PLATFORMINC)
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.c
new file mode 100644
index 000000000..1fd78d5f4
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.c
@@ -0,0 +1,176 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_isr.c
19 * @brief STM32F7xx ISR handler code.
20 *
21 * @addtogroup STM32F7xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/*===========================================================================*/
36/* Driver local variables. */
37/*===========================================================================*/
38
39/*===========================================================================*/
40/* Driver local functions. */
41/*===========================================================================*/
42
43#define exti_serve_irq(pr, channel) { \
44 \
45 if ((pr) & (1U << (channel))) { \
46 _pal_isr_code(channel); \
47 } \
48}
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#include "stm32_exti0.inc"
55#include "stm32_exti1.inc"
56#include "stm32_exti2.inc"
57#include "stm32_exti3.inc"
58#include "stm32_exti4.inc"
59#include "stm32_exti5_9.inc"
60#include "stm32_exti10_15.inc"
61#include "stm32_exti16.inc"
62#include "stm32_exti17.inc"
63#include "stm32_exti18.inc"
64#include "stm32_exti19.inc"
65#include "stm32_exti20.inc"
66#include "stm32_exti21.inc"
67#include "stm32_exti22.inc"
68#include "stm32_exti23.inc"
69
70#include "stm32_usart1.inc"
71#include "stm32_usart2.inc"
72#include "stm32_usart3.inc"
73#include "stm32_uart4.inc"
74#include "stm32_uart5.inc"
75#include "stm32_usart6.inc"
76#include "stm32_uart7.inc"
77#include "stm32_uart8.inc"
78
79#include "stm32_tim1_9_10_11.inc"
80#include "stm32_tim2.inc"
81#include "stm32_tim3.inc"
82#include "stm32_tim4.inc"
83#include "stm32_tim5.inc"
84#include "stm32_tim6.inc"
85#include "stm32_tim7.inc"
86#include "stm32_tim8_12_13_14.inc"
87
88/*===========================================================================*/
89/* Driver exported functions. */
90/*===========================================================================*/
91
92/**
93 * @brief Enables IRQ sources.
94 *
95 * @notapi
96 */
97void irqInit(void) {
98
99 exti0_irq_init();
100 exti1_irq_init();
101 exti2_irq_init();
102 exti3_irq_init();
103 exti4_irq_init();
104 exti5_9_irq_init();
105 exti10_15_irq_init();
106 exti16_irq_init();
107 exti17_irq_init();
108 exti18_irq_init();
109 exti19_irq_init();
110 exti20_irq_init();
111 exti21_irq_init();
112 exti22_irq_init();
113 exti23_irq_init();
114
115 tim1_tim9_tim10_tim11_irq_init();
116 tim2_irq_init();
117 tim3_irq_init();
118 tim4_irq_init();
119 tim5_irq_init();
120 tim6_irq_init();
121 tim7_irq_init();
122 tim8_tim12_tim13_tim14_irq_init();
123
124 usart1_irq_init();
125 usart2_irq_init();
126 usart3_irq_init();
127 uart4_irq_init();
128 uart5_irq_init();
129 usart6_irq_init();
130 uart7_irq_init();
131 uart8_irq_init();
132}
133
134/**
135 * @brief Disables IRQ sources.
136 *
137 * @notapi
138 */
139void irqDeinit(void) {
140
141 exti0_irq_deinit();
142 exti1_irq_deinit();
143 exti2_irq_deinit();
144 exti3_irq_deinit();
145 exti4_irq_deinit();
146 exti5_9_irq_deinit();
147 exti10_15_irq_deinit();
148 exti16_irq_deinit();
149 exti17_irq_deinit();
150 exti18_irq_deinit();
151 exti19_irq_deinit();
152 exti20_irq_deinit();
153 exti21_irq_deinit();
154 exti22_irq_deinit();
155 exti23_irq_deinit();
156
157 tim1_tim9_tim10_tim11_irq_deinit();
158 tim2_irq_deinit();
159 tim3_irq_deinit();
160 tim4_irq_deinit();
161 tim5_irq_deinit();
162 tim6_irq_deinit();
163 tim7_irq_deinit();
164 tim8_tim12_tim13_tim14_irq_deinit();
165
166 usart1_irq_deinit();
167 usart2_irq_deinit();
168 usart3_irq_deinit();
169 uart4_irq_deinit();
170 uart5_irq_deinit();
171 usart6_irq_deinit();
172 uart7_irq_deinit();
173 uart8_irq_deinit();
174}
175
176/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.h b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.h
new file mode 100644
index 000000000..1ed43c388
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_isr.h
@@ -0,0 +1,340 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_isr.h
19 * @brief STM32F7xx ISR handler header.
20 *
21 * @addtogroup STM32F7xx_ISR
22 * @{
23 */
24
25#ifndef STM32_ISR_H
26#define STM32_ISR_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name ISRs suppressed in standard drivers
34 * @{
35 */
36#define STM32_TIM1_SUPPRESS_ISR
37#define STM32_TIM2_SUPPRESS_ISR
38#define STM32_TIM3_SUPPRESS_ISR
39#define STM32_TIM4_SUPPRESS_ISR
40#define STM32_TIM5_SUPPRESS_ISR
41#define STM32_TIM6_SUPPRESS_ISR
42#define STM32_TIM7_SUPPRESS_ISR
43#define STM32_TIM8_SUPPRESS_ISR
44#define STM32_TIM9_SUPPRESS_ISR
45#define STM32_TIM10_SUPPRESS_ISR
46#define STM32_TIM11_SUPPRESS_ISR
47#define STM32_TIM12_SUPPRESS_ISR
48#define STM32_TIM13_SUPPRESS_ISR
49#define STM32_TIM14_SUPPRESS_ISR
50
51#define STM32_USART1_SUPPRESS_ISR
52#define STM32_USART2_SUPPRESS_ISR
53#define STM32_USART3_SUPPRESS_ISR
54#define STM32_UART4_SUPPRESS_ISR
55#define STM32_UART5_SUPPRESS_ISR
56#define STM32_USART6_SUPPRESS_ISR
57#define STM32_UART7_SUPPRESS_ISR
58#define STM32_UART8_SUPPRESS_ISR
59/** @} */
60
61/**
62 * @name ISR names and numbers
63 * @{
64 */
65/*
66 * ADC units.
67 */
68#define STM32_ADC_HANDLER Vector88
69
70#define STM32_ADC_NUMBER 18
71
72/*
73 * CAN units.
74 */
75#define STM32_CAN1_TX_HANDLER Vector8C
76#define STM32_CAN1_RX0_HANDLER Vector90
77#define STM32_CAN1_RX1_HANDLER Vector94
78#define STM32_CAN1_SCE_HANDLER Vector98
79#define STM32_CAN2_TX_HANDLER Vector13C
80#define STM32_CAN2_RX0_HANDLER Vector140
81#define STM32_CAN2_RX1_HANDLER Vector144
82#define STM32_CAN2_SCE_HANDLER Vector148
83#define STM32_CAN3_TX_HANDLER Vector1E0
84#define STM32_CAN3_RX0_HANDLER Vector1E4
85#define STM32_CAN3_RX1_HANDLER Vector1E8
86#define STM32_CAN3_SCE_HANDLER Vector1EC
87
88#define STM32_CAN1_TX_NUMBER 19
89#define STM32_CAN1_RX0_NUMBER 20
90#define STM32_CAN1_RX1_NUMBER 21
91#define STM32_CAN1_SCE_NUMBER 22
92#define STM32_CAN2_TX_NUMBER 63
93#define STM32_CAN2_RX0_NUMBER 64
94#define STM32_CAN2_RX1_NUMBER 65
95#define STM32_CAN2_SCE_NUMBER 66
96#define STM32_CAN3_TX_NUMBER 104
97#define STM32_CAN3_RX0_NUMBER 105
98#define STM32_CAN3_RX1_NUMBER 106
99#define STM32_CAN3_SCE_NUMBER 107
100
101/*
102 * DMA units.
103 */
104#define STM32_DMA1_CH0_HANDLER Vector6C
105#define STM32_DMA1_CH1_HANDLER Vector70
106#define STM32_DMA1_CH2_HANDLER Vector74
107#define STM32_DMA1_CH3_HANDLER Vector78
108#define STM32_DMA1_CH4_HANDLER Vector7C
109#define STM32_DMA1_CH5_HANDLER Vector80
110#define STM32_DMA1_CH6_HANDLER Vector84
111#define STM32_DMA1_CH7_HANDLER VectorFC
112#define STM32_DMA2_CH0_HANDLER Vector120
113#define STM32_DMA2_CH1_HANDLER Vector124
114#define STM32_DMA2_CH2_HANDLER Vector128
115#define STM32_DMA2_CH3_HANDLER Vector12C
116#define STM32_DMA2_CH4_HANDLER Vector130
117#define STM32_DMA2_CH5_HANDLER Vector150
118#define STM32_DMA2_CH6_HANDLER Vector154
119#define STM32_DMA2_CH7_HANDLER Vector158
120
121#define STM32_DMA1_CH0_NUMBER 11
122#define STM32_DMA1_CH1_NUMBER 12
123#define STM32_DMA1_CH2_NUMBER 13
124#define STM32_DMA1_CH3_NUMBER 14
125#define STM32_DMA1_CH4_NUMBER 15
126#define STM32_DMA1_CH5_NUMBER 16
127#define STM32_DMA1_CH6_NUMBER 17
128#define STM32_DMA1_CH7_NUMBER 47
129#define STM32_DMA2_CH0_NUMBER 56
130#define STM32_DMA2_CH1_NUMBER 57
131#define STM32_DMA2_CH2_NUMBER 58
132#define STM32_DMA2_CH3_NUMBER 59
133#define STM32_DMA2_CH4_NUMBER 60
134#define STM32_DMA2_CH5_NUMBER 68
135#define STM32_DMA2_CH6_NUMBER 69
136#define STM32_DMA2_CH7_NUMBER 70
137
138/*
139 * EXTI unit.
140 */
141#define STM32_EXTI0_HANDLER Vector58
142#define STM32_EXTI1_HANDLER Vector5C
143#define STM32_EXTI2_HANDLER Vector60
144#define STM32_EXTI3_HANDLER Vector64
145#define STM32_EXTI4_HANDLER Vector68
146#define STM32_EXTI5_9_HANDLER Vector9C
147#define STM32_EXTI10_15_HANDLER VectorE0
148#define STM32_EXTI16_HANDLER Vector44 /* PVD */
149#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
150#define STM32_EXTI18_HANDLER VectorE8 /* USB FS WAKEUP */
151#define STM32_EXTI19_HANDLER Vector138 /* ETH WAKEUP */
152#define STM32_EXTI20_HANDLER Vector170 /* USB HS WAKEUP */
153#define STM32_EXTI21_HANDLER Vector48 /* RTC TAMPER */
154#define STM32_EXTI22_HANDLER Vector4C /* RTC WAKEUP */
155#define STM32_EXTI23_HANDLER Vector1B4 /* LPTIM1 */
156
157#define STM32_EXTI0_NUMBER 6
158#define STM32_EXTI1_NUMBER 7
159#define STM32_EXTI2_NUMBER 8
160#define STM32_EXTI3_NUMBER 9
161#define STM32_EXTI4_NUMBER 10
162#define STM32_EXTI5_9_NUMBER 23
163#define STM32_EXTI10_15_NUMBER 40
164#define STM32_EXTI16_NUMBER 1
165#define STM32_EXTI17_NUMBER 41
166#define STM32_EXTI18_NUMBER 42
167#define STM32_EXTI19_NUMBER 62
168#define STM32_EXTI20_NUMBER 76
169#define STM32_EXTI21_NUMBER 2
170#define STM32_EXTI22_NUMBER 3
171#define STM32_EXTI23_NUMBER 93
172
173/*
174 * I2C units.
175 */
176#define STM32_I2C1_EVENT_HANDLER VectorBC
177#define STM32_I2C1_ERROR_HANDLER VectorC0
178#define STM32_I2C2_EVENT_HANDLER VectorC4
179#define STM32_I2C2_ERROR_HANDLER VectorC8
180#define STM32_I2C3_EVENT_HANDLER Vector160
181#define STM32_I2C3_ERROR_HANDLER Vector164
182#define STM32_I2C4_EVENT_HANDLER Vector1BC
183#define STM32_I2C4_ERROR_HANDLER Vector1C0
184
185#define STM32_I2C1_EVENT_NUMBER 31
186#define STM32_I2C1_ERROR_NUMBER 32
187#define STM32_I2C2_EVENT_NUMBER 33
188#define STM32_I2C2_ERROR_NUMBER 34
189#define STM32_I2C3_EVENT_NUMBER 72
190#define STM32_I2C3_ERROR_NUMBER 73
191#define STM32_I2C4_EVENT_NUMBER 95
192#define STM32_I2C4_ERROR_NUMBER 96
193
194/*
195 * ETH units.
196 */
197#define STM32_ETH_HANDLER Vector134
198
199#define STM32_ETH_NUMBER 61
200
201/*
202 * QUADSPI units.
203 */
204#define STM32_QUADSPI1_HANDLER Vector1B0
205
206#define STM32_QUADSPI1_NUMBER 92
207
208/*
209 * SDMMC units.
210 */
211#define STM32_SDMMC1_HANDLER Vector104
212#define STM32_SDMMC2_HANDLER Vector1DC
213
214#define STM32_SDMMC1_NUMBER 49
215#define STM32_SDMMC2_NUMBER 103
216
217/*
218 * TIM units.
219 */
220#define STM32_TIM1_BRK_TIM9_HANDLER VectorA0
221#define STM32_TIM1_UP_TIM10_HANDLER VectorA4
222#define STM32_TIM1_TRGCO_TIM11_HANDLER VectorA8
223#define STM32_TIM1_CC_HANDLER VectorAC
224#define STM32_TIM2_HANDLER VectorB0
225#define STM32_TIM3_HANDLER VectorB4
226#define STM32_TIM4_HANDLER VectorB8
227#define STM32_TIM5_HANDLER Vector108
228#define STM32_TIM6_HANDLER Vector118
229#define STM32_TIM7_HANDLER Vector11C
230#define STM32_TIM8_BRK_TIM12_HANDLER VectorEC
231#define STM32_TIM8_UP_TIM13_HANDLER VectorF0
232#define STM32_TIM8_TRGCO_TIM14_HANDLER VectorF4
233#define STM32_TIM8_CC_HANDLER VectorF8
234
235#define STM32_TIM1_BRK_TIM9_NUMBER 24
236#define STM32_TIM1_UP_TIM10_NUMBER 25
237#define STM32_TIM1_TRGCO_TIM11_NUMBER 26
238#define STM32_TIM1_CC_NUMBER 27
239#define STM32_TIM2_NUMBER 28
240#define STM32_TIM3_NUMBER 29
241#define STM32_TIM4_NUMBER 30
242#define STM32_TIM5_NUMBER 50
243#define STM32_TIM6_NUMBER 54
244#define STM32_TIM7_NUMBER 55
245#define STM32_TIM8_BRK_TIM12_NUMBER 43
246#define STM32_TIM8_UP_TIM13_NUMBER 44
247#define STM32_TIM8_TRGCO_TIM14_NUMBER 45
248#define STM32_TIM8_CC_NUMBER 46
249
250/*
251 * USART/UART units.
252 */
253#define STM32_USART1_HANDLER VectorD4
254#define STM32_USART2_HANDLER VectorD8
255#define STM32_USART3_HANDLER VectorDC
256#define STM32_UART4_HANDLER Vector110
257#define STM32_UART5_HANDLER Vector114
258#define STM32_USART6_HANDLER Vector15C
259#define STM32_UART7_HANDLER Vector188
260#define STM32_UART8_HANDLER Vector18C
261
262#define STM32_USART1_NUMBER 37
263#define STM32_USART2_NUMBER 38
264#define STM32_USART3_NUMBER 39
265#define STM32_UART4_NUMBER 52
266#define STM32_UART5_NUMBER 53
267#define STM32_USART6_NUMBER 71
268#define STM32_UART7_NUMBER 82
269#define STM32_UART8_NUMBER 83
270
271/*
272 * USB/OTG units.
273 */
274#define STM32_OTG1_HANDLER Vector14C
275#define STM32_OTG2_HANDLER Vector174
276#define STM32_OTG2_EP1OUT_HANDLER Vector168
277#define STM32_OTG2_EP1IN_HANDLER Vector16C
278
279#define STM32_OTG1_NUMBER 67
280#define STM32_OTG2_NUMBER 77
281#define STM32_OTG2_EP1OUT_NUMBER 74
282#define STM32_OTG2_EP1IN_NUMBER 75
283
284/*
285 * FSMC units.
286 */
287#define STM32_FSMC_HANDLER Vector100
288
289#define STM32_FSMC_NUMBER 48
290
291/*
292 * LTDC units.
293 */
294#define STM32_LTDC_EV_HANDLER Vector1A0
295#define STM32_LTDC_ER_HANDLER Vector1A4
296
297#define STM32_LTDC_EV_NUMBER 88
298#define STM32_LTDC_ER_NUMBER 89
299
300/*
301 * DMA2D units.
302 */
303#define STM32_DMA2D_HANDLER Vector1A8
304
305#define STM32_DMA2D_NUMBER 90
306
307/** @} */
308
309/*===========================================================================*/
310/* Driver pre-compile time settings. */
311/*===========================================================================*/
312
313/*===========================================================================*/
314/* Derived constants and error checks. */
315/*===========================================================================*/
316
317/*===========================================================================*/
318/* Driver data structures and types. */
319/*===========================================================================*/
320
321/*===========================================================================*/
322/* Driver macros. */
323/*===========================================================================*/
324
325/*===========================================================================*/
326/* External declarations. */
327/*===========================================================================*/
328
329#ifdef __cplusplus
330extern "C" {
331#endif
332 void irqInit(void);
333 void irqDeinit(void);
334#ifdef __cplusplus
335}
336#endif
337
338#endif /* STM32_ISR_H */
339
340/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
new file mode 100644
index 000000000..daa5162a2
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
@@ -0,0 +1,1700 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f7xx.h.
22 *
23 * @addtogroup STM32F7xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus.
55 *
56 * @param[in] mask APB1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1(mask, lp) { \
62 RCC->APB1ENR |= (mask); \
63 if (lp) \
64 RCC->APB1LPENR |= (mask); \
65 else \
66 RCC->APB1LPENR &= ~(mask); \
67 (void)RCC->APB1LPENR; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus.
72 *
73 * @param[in] mask APB1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1(mask) { \
78 RCC->APB1ENR &= ~(mask); \
79 RCC->APB1LPENR &= ~(mask); \
80 (void)RCC->APB1LPENR; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus.
85 *
86 * @param[in] mask APB1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1(mask) { \
91 RCC->APB1RSTR |= (mask); \
92 RCC->APB1RSTR &= ~(mask); \
93 (void)RCC->APB1RSTR; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB2 bus.
98 *
99 * @param[in] mask APB2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB2(mask, lp) { \
105 RCC->APB2ENR |= (mask); \
106 if (lp) \
107 RCC->APB2LPENR |= (mask); \
108 else \
109 RCC->APB2LPENR &= ~(mask); \
110 (void)RCC->APB2LPENR; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB2 bus.
115 *
116 * @param[in] mask APB2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB2(mask) { \
121 RCC->APB2ENR &= ~(mask); \
122 RCC->APB2LPENR &= ~(mask); \
123 (void)RCC->APB2LPENR; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB2 bus.
128 *
129 * @param[in] mask APB2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB2(mask) { \
134 RCC->APB2RSTR |= (mask); \
135 RCC->APB2RSTR &= ~(mask); \
136 (void)RCC->APB2RSTR; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
141 *
142 * @param[in] mask AHB1 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAHB1(mask, lp) { \
148 RCC->AHB1ENR |= (mask); \
149 if (lp) \
150 RCC->AHB1LPENR |= (mask); \
151 else \
152 RCC->AHB1LPENR &= ~(mask); \
153 (void)RCC->AHB1LPENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
158 *
159 * @param[in] mask AHB1 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAHB1(mask) { \
164 RCC->AHB1ENR &= ~(mask); \
165 RCC->AHB1LPENR &= ~(mask); \
166 (void)RCC->AHB1LPENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the AHB1 bus.
171 *
172 * @param[in] mask AHB1 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAHB1(mask) { \
177 RCC->AHB1RSTR |= (mask); \
178 RCC->AHB1RSTR &= ~(mask); \
179 (void)RCC->AHB1RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
184 *
185 * @param[in] mask AHB2 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB2(mask, lp) { \
191 RCC->AHB2ENR |= (mask); \
192 if (lp) \
193 RCC->AHB2LPENR |= (mask); \
194 else \
195 RCC->AHB2LPENR &= ~(mask); \
196 (void)RCC->AHB2LPENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
201 *
202 * @param[in] mask AHB2 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB2(mask) { \
207 RCC->AHB2ENR &= ~(mask); \
208 RCC->AHB2LPENR &= ~(mask); \
209 (void)RCC->AHB2LPENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB2 bus.
214 *
215 * @param[in] mask AHB2 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB2(mask) { \
220 RCC->AHB2RSTR |= (mask); \
221 RCC->AHB2RSTR &= ~(mask); \
222 (void)RCC->AHB2RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
227 *
228 * @param[in] mask AHB3 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB3(mask, lp) { \
234 RCC->AHB3ENR |= (mask); \
235 if (lp) \
236 RCC->AHB3LPENR |= (mask); \
237 else \
238 RCC->AHB3LPENR &= ~(mask); \
239 (void)RCC->AHB3LPENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
244 *
245 * @param[in] mask AHB3 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB3(mask) { \
250 RCC->AHB3ENR &= ~(mask); \
251 RCC->AHB3LPENR &= ~(mask); \
252 (void)RCC->AHB3LPENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
257 *
258 * @param[in] mask AHB3 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB3(mask) { \
263 RCC->AHB3RSTR |= (mask); \
264 RCC->AHB3RSTR &= ~(mask); \
265 (void)RCC->AHB3RSTR; \
266}
267/** @} */
268
269/**
270 * @name ADC peripherals specific RCC operations
271 * @{
272 */
273/**
274 * @brief Enables the ADC1 peripheral clock.
275 *
276 * @param[in] lp low power enable flag
277 *
278 * @api
279 */
280#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
281
282/**
283 * @brief Disables the ADC1 peripheral clock.
284 *
285 * @api
286 */
287#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
288
289/**
290 * @brief Resets the ADC1 peripheral.
291 *
292 * @api
293 */
294#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
295
296/**
297 * @brief Enables the ADC2 peripheral clock.
298 *
299 * @param[in] lp low power enable flag
300 *
301 * @api
302 */
303#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)
304
305/**
306 * @brief Disables the ADC2 peripheral clock.
307 *
308 * @api
309 */
310#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
311
312/**
313 * @brief Resets the ADC2 peripheral.
314 *
315 * @api
316 */
317#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
318
319/**
320 * @brief Enables the ADC3 peripheral clock.
321 *
322 * @param[in] lp low power enable flag
323 *
324 * @api
325 */
326#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)
327
328/**
329 * @brief Disables the ADC3 peripheral clock.
330 *
331 * @api
332 */
333#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
334
335/**
336 * @brief Resets the ADC3 peripheral.
337 *
338 * @api
339 */
340#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
341/** @} */
342
343/**
344 * @name DAC peripheral specific RCC operations
345 * @{
346 */
347/**
348 * @brief Enables the DAC1 peripheral clock.
349 *
350 * @param[in] lp low power enable flag
351 *
352 * @api
353 */
354#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
355
356/**
357 * @brief Disables the DAC1 peripheral clock.
358 *
359 * @api
360 */
361#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
362
363/**
364 * @brief Resets the DAC1 peripheral.
365 *
366 * @api
367 */
368#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
369/** @} */
370
371/**
372 * @name DMA peripheral specific RCC operations
373 * @{
374 */
375/**
376 * @brief Enables the DMA1 peripheral clock.
377 *
378 * @param[in] lp low power enable flag
379 *
380 * @api
381 */
382#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
383
384/**
385 * @brief Disables the DMA1 peripheral clock.
386 *
387 * @api
388 */
389#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
390
391/**
392 * @brief Resets the DMA1 peripheral.
393 *
394 * @api
395 */
396#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
397
398/**
399 * @brief Enables the DMA2 peripheral clock.
400 *
401 * @param[in] lp low power enable flag
402 *
403 * @api
404 */
405#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
406
407/**
408 * @brief Disables the DMA2 peripheral clock.
409 *
410 * @api
411 */
412#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
413
414/**
415 * @brief Resets the DMA2 peripheral.
416 *
417 * @api
418 */
419#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
420/** @} */
421
422/**
423 * @name BKPSRAM specific RCC operations
424 * @{
425 */
426/**
427 * @brief Enables the BKPSRAM peripheral clock.
428 *
429 * @param[in] lp low power enable flag
430 *
431 * @api
432 */
433#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
434
435/**
436 * @brief Disables the BKPSRAM peripheral clock.
437 *
438 * @api
439 */
440#define rccDisableBKPSRAM() rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN)
441/** @} */
442
443/**
444 * @name PWR interface specific RCC operations
445 * @{
446 */
447/**
448 * @brief Enables the PWR interface clock.
449 *
450 * @param[in] lp low power enable flag
451 *
452 * @api
453 */
454#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
455
456/**
457 * @brief Disables PWR interface clock.
458 *
459 * @api
460 */
461#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
462
463/**
464 * @brief Resets the PWR interface.
465 *
466 * @api
467 */
468#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
469/** @} */
470
471/**
472 * @name CAN peripherals specific RCC operations
473 * @{
474 */
475/**
476 * @brief Enables the CAN1 peripheral clock.
477 *
478 * @param[in] lp low power enable flag
479 *
480 * @api
481 */
482#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
483
484/**
485 * @brief Disables the CAN1 peripheral clock.
486 *
487 * @api
488 */
489#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CAN1EN)
490
491/**
492 * @brief Resets the CAN1 peripheral.
493 *
494 * @api
495 */
496#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
497
498/**
499 * @brief Enables the CAN2 peripheral clock.
500 *
501 * @param[in] lp low power enable flag
502 *
503 * @api
504 */
505#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
506
507/**
508 * @brief Disables the CAN2 peripheral clock.
509 *
510 * @api
511 */
512#define rccDisableCAN2() rccDisableAPB1(RCC_APB1ENR_CAN2EN)
513
514/**
515 * @brief Resets the CAN2 peripheral.
516 *
517 * @api
518 */
519#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
520
521/**
522 * @brief Resets the CAN3 peripheral.
523 *
524 * @api
525 */
526#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST)
527
528/**
529 * @brief Enables the CAN3 peripheral clock.
530 *
531 * @param[in] lp low power enable flag
532 *
533 * @api
534 */
535#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp)
536
537/**
538 * @brief Disables the CAN3 peripheral clock.
539 *
540 * @api
541 */
542#define rccDisableCAN3() rccDisableAPB1(RCC_APB1ENR_CAN3EN)
543/** @} */
544
545/**
546 * @name ETH peripheral specific RCC operations
547 * @{
548 */
549/**
550 * @brief Enables the ETH peripheral clock.
551 *
552 * @api
553 */
554#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
555 RCC_AHB1ENR_ETHMACTXEN | \
556 RCC_AHB1ENR_ETHMACRXEN, lp)
557
558/**
559 * @brief Disables the ETH peripheral clock.
560 *
561 * @param[in] lp low power enable flag
562 *
563 * @api
564 */
565#define rccDisableETH() rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
566 RCC_AHB1ENR_ETHMACTXEN | \
567 RCC_AHB1ENR_ETHMACRXEN)
568
569/**
570 * @brief Resets the ETH peripheral.
571 *
572 * @api
573 */
574#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
575/** @} */
576
577/**
578 * @name I2C peripherals specific RCC operations
579 * @{
580 */
581/**
582 * @brief Enables the I2C1 peripheral clock.
583 *
584 * @param[in] lp low power enable flag
585 *
586 * @api
587 */
588#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
589
590/**
591 * @brief Disables the I2C1 peripheral clock.
592 *
593 * @api
594 */
595#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
596
597/**
598 * @brief Resets the I2C1 peripheral.
599 *
600 * @api
601 */
602#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
603
604/**
605 * @brief Enables the I2C2 peripheral clock.
606 *
607 * @param[in] lp low power enable flag
608 *
609 * @api
610 */
611#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
612
613/**
614 * @brief Disables the I2C2 peripheral clock.
615 *
616 * @api
617 */
618#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
619
620/**
621 * @brief Resets the I2C2 peripheral.
622 *
623 * @api
624 */
625#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
626
627/**
628 * @brief Enables the I2C3 peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
635
636/**
637 * @brief Disables the I2C3 peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableI2C3() rccDisableAPB1(RCC_APB1ENR_I2C3EN)
642
643/**
644 * @brief Resets the I2C3 peripheral.
645 *
646 * @api
647 */
648#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
649
650/**
651 * @brief Enables the I2C4 peripheral clock.
652 *
653 * @param[in] lp low power enable flag
654 *
655 * @api
656 */
657#define rccEnableI2C4(lp) rccEnableAPB1(RCC_APB1ENR_I2C4EN, lp)
658
659/**
660 * @brief Disables the I2C4 peripheral clock.
661 *
662 * @api
663 */
664#define rccDisableI2C4() rccDisableAPB1(RCC_APB1ENR_I2C4EN)
665
666/**
667 * @brief Resets the I2C4 peripheral.
668 *
669 * @api
670 */
671#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_I2C4RST)
672/** @} */
673
674/**
675 * @name OTG peripherals specific RCC operations
676 * @{
677 */
678/**
679 * @brief Enables the OTG_FS peripheral clock.
680 *
681 * @param[in] lp low power enable flag
682 *
683 * @api
684 */
685#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
686
687/**
688 * @brief Disables the OTG_FS peripheral clock.
689 *
690 * @api
691 */
692#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
693
694/**
695 * @brief Resets the OTG_FS peripheral.
696 *
697 * @api
698 */
699#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
700
701/**
702 * @brief Enables the OTG_HS peripheral clock.
703 *
704 * @param[in] lp low power enable flag
705 *
706 * @api
707 */
708#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
709
710/**
711 * @brief Disables the OTG_HS peripheral clock.
712 *
713 * @api
714 */
715#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_OTGHSEN)
716
717/**
718 * @brief Resets the OTG_HS peripheral.
719 *
720 * @api
721 */
722#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)
723
724/**
725 * @brief Enables the OTG_HS peripheral clock.
726 *
727 * @param[in] lp low power enable flag
728 *
729 * @api
730 */
731#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
732
733/**
734 * @brief Disables the OTG_HS peripheral clock.
735 *
736 * @api
737 */
738#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN)
739/** @} */
740
741/**
742 * @name QUADSPI peripherals specific RCC operations
743 * @{
744 */
745/**
746 * @brief Enables the QUADSPI1 peripheral clock.
747 *
748 * @param[in] lp low power enable flag
749 *
750 * @api
751 */
752#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
753
754/**
755 * @brief Disables the QUADSPI1 peripheral clock.
756 *
757 * @api
758 */
759#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
760
761/**
762 * @brief Resets the QUADSPI1 peripheral.
763 *
764 * @api
765 */
766#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
767/** @} */
768
769/**
770 * @name RNG peripherals specific RCC operations
771 * @{
772 */
773/**
774 * @brief Enables the RNG peripheral clock.
775 *
776 * @param[in] lp low power enable flag
777 *
778 * @api
779 */
780#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
781
782/**
783 * @brief Disables the RNG peripheral clock.
784 *
785 * @api
786 */
787#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
788
789/**
790 * @brief Resets the RNG peripheral.
791 *
792 * @api
793 */
794#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
795/** @} */
796
797/**
798 * @name SDMMC peripheral specific RCC operations
799 * @{
800 */
801/**
802 * @brief Enables the SDMMC1 peripheral clock.
803 *
804 * @param[in] lp low power enable flag
805 *
806 * @api
807 */
808#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
809
810/**
811 * @brief Disables the SDMMC1 peripheral clock.
812 *
813 * @api
814 */
815#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
816
817/**
818 * @brief Resets the SDMMC1 peripheral.
819 *
820 * @api
821 */
822#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
823
824/**
825 * @brief Enables the SDMMC2 peripheral clock.
826 *
827 * @param[in] lp low power enable flag
828 *
829 * @api
830 */
831#define rccEnableSDMMC2(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC2EN, lp)
832
833/**
834 * @brief Disables the SDMMC2 peripheral clock.
835 *
836 * @api
837 */
838#define rccDisableSDMMC2() rccDisableAPB2(RCC_APB2ENR_SDMMC2EN)
839
840/**
841 * @brief Resets the SDMMC2 peripheral.
842 *
843 * @api
844 */
845#define rccResetSDMMC2() rccResetAPB2(RCC_APB2RSTR_SDMMC2RST)
846/** @} */
847
848/**
849 * @name SPI peripherals specific RCC operations
850 * @{
851 */
852/**
853 * @brief Enables the SPI1 peripheral clock.
854 *
855 * @param[in] lp low power enable flag
856 *
857 * @api
858 */
859#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
860
861/**
862 * @brief Disables the SPI1 peripheral clock.
863 *
864 * @api
865 */
866#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
867
868/**
869 * @brief Resets the SPI1 peripheral.
870 *
871 * @api
872 */
873#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
874
875/**
876 * @brief Enables the SPI2 peripheral clock.
877 *
878 * @param[in] lp low power enable flag
879 *
880 * @api
881 */
882#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
883
884/**
885 * @brief Disables the SPI2 peripheral clock.
886 *
887 * @api
888 */
889#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
890
891/**
892 * @brief Resets the SPI2 peripheral.
893 *
894 * @api
895 */
896#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
897
898/**
899 * @brief Enables the SPI3 peripheral clock.
900 *
901 * @param[in] lp low power enable flag
902 *
903 * @api
904 */
905#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
906
907/**
908 * @brief Disables the SPI3 peripheral clock.
909 *
910 * @api
911 */
912#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
913
914/**
915 * @brief Resets the SPI3 peripheral.
916 *
917 * @api
918 */
919#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
920
921/**
922 * @brief Enables the SPI4 peripheral clock.
923 *
924 * @param[in] lp low power enable flag
925 *
926 * @api
927 */
928#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
929
930/**
931 * @brief Disables the SPI4 peripheral clock.
932 *
933 * @api
934 */
935#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
936
937/**
938 * @brief Resets the SPI4 peripheral.
939 *
940 * @api
941 */
942#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
943
944/**
945 * @brief Enables the SPI5 peripheral clock.
946 *
947 * @param[in] lp low power enable flag
948 *
949 * @api
950 */
951#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)
952
953/**
954 * @brief Disables the SPI5 peripheral clock.
955 *
956 * @api
957 */
958#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN)
959
960/**
961 * @brief Resets the SPI5 peripheral.
962 *
963 * @api
964 */
965#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)
966
967/**
968 * @brief Enables the SPI6 peripheral clock.
969 *
970 * @param[in] lp low power enable flag
971 *
972 * @api
973 */
974#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)
975
976/**
977 * @brief Disables the SPI6 peripheral clock.
978 *
979 * @api
980 */
981#define rccDisableSPI6() rccDisableAPB2(RCC_APB2ENR_SPI6EN)
982
983/**
984 * @brief Resets the SPI6 peripheral.
985 *
986 * @api
987 */
988#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)
989/** @} */
990
991/**
992 * @name TIM peripherals specific RCC operations
993 * @{
994 */
995/**
996 * @brief Enables the TIM1 peripheral clock.
997 *
998 * @param[in] lp low power enable flag
999 *
1000 * @api
1001 */
1002#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
1003
1004/**
1005 * @brief Disables the TIM1 peripheral clock.
1006 *
1007 * @api
1008 */
1009#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
1010
1011/**
1012 * @brief Resets the TIM1 peripheral.
1013 *
1014 * @api
1015 */
1016#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
1017
1018/**
1019 * @brief Enables the TIM2 peripheral clock.
1020 *
1021 * @param[in] lp low power enable flag
1022 *
1023 * @api
1024 */
1025#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
1026
1027/**
1028 * @brief Disables the TIM2 peripheral clock.
1029 *
1030 * @api
1031 */
1032#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
1033
1034/**
1035 * @brief Resets the TIM2 peripheral.
1036 *
1037 * @api
1038 */
1039#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
1040
1041/**
1042 * @brief Enables the TIM3 peripheral clock.
1043 *
1044 * @param[in] lp low power enable flag
1045 *
1046 * @api
1047 */
1048#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
1049
1050/**
1051 * @brief Disables the TIM3 peripheral clock.
1052 *
1053 * @api
1054 */
1055#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
1056
1057/**
1058 * @brief Resets the TIM3 peripheral.
1059 *
1060 * @api
1061 */
1062#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
1063
1064/**
1065 * @brief Enables the TIM4 peripheral clock.
1066 *
1067 * @param[in] lp low power enable flag
1068 *
1069 * @api
1070 */
1071#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
1072
1073/**
1074 * @brief Disables the TIM4 peripheral clock.
1075 *
1076 * @api
1077 */
1078#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
1079
1080/**
1081 * @brief Resets the TIM4 peripheral.
1082 *
1083 * @api
1084 */
1085#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
1086
1087/**
1088 * @brief Enables the TIM5 peripheral clock.
1089 *
1090 * @param[in] lp low power enable flag
1091 *
1092 * @api
1093 */
1094#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
1095
1096/**
1097 * @brief Disables the TIM5 peripheral clock.
1098 *
1099 * @api
1100 */
1101#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
1102
1103/**
1104 * @brief Resets the TIM5 peripheral.
1105 *
1106 * @api
1107 */
1108#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
1109
1110/**
1111 * @brief Enables the TIM6 peripheral clock.
1112 *
1113 * @param[in] lp low power enable flag
1114 *
1115 * @api
1116 */
1117#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
1118
1119/**
1120 * @brief Disables the TIM6 peripheral clock.
1121 *
1122 * @api
1123 */
1124#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
1125
1126/**
1127 * @brief Resets the TIM6 peripheral.
1128 *
1129 * @api
1130 */
1131#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
1132
1133/**
1134 * @brief Enables the TIM7 peripheral clock.
1135 *
1136 * @param[in] lp low power enable flag
1137 *
1138 * @api
1139 */
1140#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
1141
1142/**
1143 * @brief Disables the TIM7 peripheral clock.
1144 *
1145 * @api
1146 */
1147#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
1148
1149/**
1150 * @brief Resets the TIM7 peripheral.
1151 *
1152 * @api
1153 */
1154#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
1155
1156/**
1157 * @brief Enables the TIM8 peripheral clock.
1158 *
1159 * @param[in] lp low power enable flag
1160 *
1161 * @api
1162 */
1163#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1164
1165/**
1166 * @brief Disables the TIM8 peripheral clock.
1167 *
1168 * @api
1169 */
1170#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1171
1172/**
1173 * @brief Resets the TIM8 peripheral.
1174 *
1175 * @api
1176 */
1177#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1178
1179/**
1180 * @brief Enables the TIM9 peripheral clock.
1181 *
1182 * @param[in] lp low power enable flag
1183 *
1184 * @api
1185 */
1186#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
1187
1188/**
1189 * @brief Disables the TIM9 peripheral clock.
1190 *
1191 * @api
1192 */
1193#define rccDisableTIM9() rccDisableAPB2(RCC_APB2ENR_TIM9EN)
1194
1195/**
1196 * @brief Resets the TIM9 peripheral.
1197 *
1198 * @api
1199 */
1200#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
1201
1202/**
1203 * @brief Enables the TIM10 peripheral clock.
1204 *
1205 * @param[in] lp low power enable flag
1206 *
1207 * @api
1208 */
1209#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
1210
1211/**
1212 * @brief Disables the TIM10 peripheral clock.
1213 *
1214 * @api
1215 */
1216#define rccDisableTIM10() rccDisableAPB2(RCC_APB2ENR_TIM10EN)
1217
1218/**
1219 * @brief Resets the TIM10 peripheral.
1220 *
1221 * @api
1222 */
1223#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
1224
1225/**
1226 * @brief Enables the TIM11 peripheral clock.
1227 *
1228 * @param[in] lp low power enable flag
1229 *
1230 * @api
1231 */
1232#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
1233
1234/**
1235 * @brief Disables the TIM11 peripheral clock.
1236 *
1237 * @api
1238 */
1239#define rccDisableTIM11() rccDisableAPB2(RCC_APB2ENR_TIM11EN)
1240
1241/**
1242 * @brief Resets the TIM11 peripheral.
1243 *
1244 * @api
1245 */
1246#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
1247
1248/**
1249 * @brief Enables the TIM12 peripheral clock.
1250 *
1251 * @param[in] lp low power enable flag
1252 *
1253 * @api
1254 */
1255#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
1256
1257/**
1258 * @brief Disables the TIM12 peripheral clock.
1259 *
1260 * @api
1261 */
1262#define rccDisableTIM12() rccDisableAPB1(RCC_APB1ENR_TIM12EN)
1263
1264/**
1265 * @brief Resets the TIM12 peripheral.
1266 *
1267 * @api
1268 */
1269#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
1270
1271/**
1272 * @brief Enables the TIM13 peripheral clock.
1273 *
1274 * @param[in] lp low power enable flag
1275 *
1276 * @api
1277 */
1278#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
1279
1280/**
1281 * @brief Disables the TIM13 peripheral clock.
1282 *
1283 * @api
1284 */
1285#define rccDisableTIM13() rccDisableAPB1(RCC_APB1ENR_TIM13EN)
1286
1287/**
1288 * @brief Resets the TIM13 peripheral.
1289 *
1290 * @api
1291 */
1292#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
1293
1294/**
1295 * @brief Enables the TIM14 peripheral clock.
1296 *
1297 * @param[in] lp low power enable flag
1298 *
1299 * @api
1300 */
1301#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
1302
1303/**
1304 * @brief Disables the TIM14 peripheral clock.
1305 *
1306 * @api
1307 */
1308#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
1309
1310/**
1311 * @brief Resets the TIM14 peripheral.
1312 *
1313 * @api
1314 */
1315#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
1316/** @} */
1317
1318/**
1319 * @name USART/UART peripherals specific RCC operations
1320 * @{
1321 */
1322/**
1323 * @brief Enables the USART1 peripheral clock.
1324 *
1325 * @param[in] lp low power enable flag
1326 *
1327 * @api
1328 */
1329#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1330
1331/**
1332 * @brief Disables the USART1 peripheral clock.
1333 *
1334 * @api
1335 */
1336#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1337
1338/**
1339 * @brief Resets the USART1 peripheral.
1340 *
1341 * @api
1342 */
1343#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1344
1345/**
1346 * @brief Enables the USART2 peripheral clock.
1347 *
1348 * @param[in] lp low power enable flag
1349 *
1350 * @api
1351 */
1352#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
1353
1354/**
1355 * @brief Disables the USART2 peripheral clock.
1356 *
1357 * @api
1358 */
1359#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
1360
1361/**
1362 * @brief Resets the USART2 peripheral.
1363 *
1364 * @api
1365 */
1366#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
1367
1368/**
1369 * @brief Enables the USART3 peripheral clock.
1370 *
1371 * @param[in] lp low power enable flag
1372 *
1373 * @api
1374 */
1375#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
1376
1377/**
1378 * @brief Disables the USART3 peripheral clock.
1379 *
1380 * @api
1381 */
1382#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
1383
1384/**
1385 * @brief Resets the USART3 peripheral.
1386 *
1387 * @api
1388 */
1389#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
1390
1391/**
1392 * @brief Enables the UART4 peripheral clock.
1393 *
1394 * @param[in] lp low power enable flag
1395 *
1396 * @api
1397 */
1398#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
1399
1400/**
1401 * @brief Disables the UART4 peripheral clock.
1402 *
1403 * @api
1404 */
1405#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_UART4EN)
1406
1407/**
1408 * @brief Resets the UART4 peripheral.
1409 *
1410 * @api
1411 */
1412#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
1413
1414/**
1415 * @brief Enables the UART5 peripheral clock.
1416 *
1417 * @param[in] lp low power enable flag
1418 *
1419 * @api
1420 */
1421#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
1422
1423/**
1424 * @brief Disables the UART5 peripheral clock.
1425 *
1426 * @api
1427 */
1428#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
1429
1430/**
1431 * @brief Resets the UART5 peripheral.
1432 *
1433 * @api
1434 */
1435#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
1436
1437/**
1438 * @brief Enables the USART6 peripheral clock.
1439 *
1440 * @param[in] lp low power enable flag
1441 *
1442 * @api
1443 */
1444#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
1445
1446/**
1447 * @brief Disables the USART6 peripheral clock.
1448 *
1449 * @api
1450 */
1451#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
1452
1453/**
1454 * @brief Resets the USART6 peripheral.
1455 *
1456 * @api
1457 */
1458#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
1459
1460/**
1461 * @brief Enables the UART7 peripheral clock.
1462 *
1463 * @param[in] lp low power enable flag
1464 *
1465 * @api
1466 */
1467#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp)
1468
1469/**
1470 * @brief Disables the UART7 peripheral clock.
1471 *
1472 * @api
1473 */
1474#define rccDisableUART7() rccDisableAPB1(RCC_APB1ENR_UART7EN)
1475
1476/**
1477 * @brief Resets the UART7 peripheral.
1478 *
1479 * @api
1480 */
1481#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST)
1482
1483/**
1484 * @brief Enables the UART8 peripheral clock.
1485 *
1486 * @param[in] lp low power enable flag
1487 *
1488 * @api
1489 */
1490#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp)
1491
1492/**
1493 * @brief Disables the UART8 peripheral clock.
1494 *
1495 * @api
1496 */
1497#define rccDisableUART8() rccDisableAPB1(RCC_APB1ENR_UART8EN)
1498
1499/**
1500 * @brief Resets the UART8 peripheral.
1501 *
1502 * @api
1503 */
1504#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST)
1505/** @} */
1506
1507/**
1508 * @name LTDC peripheral specific RCC operations
1509 * @{
1510 */
1511/**
1512 * @brief Enables the LTDC peripheral clock.
1513 *
1514 * @param[in] lp low power enable flag
1515 *
1516 * @api
1517 */
1518#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)
1519
1520/**
1521 * @brief Disables the LTDC peripheral clock.
1522 *
1523 * @api
1524 */
1525#define rccDisableLTDC() rccDisableAPB2(RCC_APB2ENR_LTDCEN)
1526
1527/**
1528 * @brief Resets the LTDC peripheral.
1529 *
1530 * @api
1531 */
1532#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
1533/** @} */
1534
1535/**
1536 * @name DMA2D peripheral specific RCC operations
1537 * @{
1538 */
1539/**
1540 * @brief Enables the DMA2D peripheral clock.
1541 *
1542 * @param[in] lp low power enable flag
1543 *
1544 * @api
1545 */
1546#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
1547
1548/**
1549 * @brief Disables the DMA2D peripheral clock.
1550 *
1551 * @api
1552 */
1553#define rccDisableDMA2D() rccDisableAHB1(RCC_AHB1ENR_DMA2DEN)
1554
1555/**
1556 * @brief Resets the DMA2D peripheral.
1557 *
1558 * @api
1559 */
1560#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
1561/** @} */
1562
1563/**
1564 * @name CRC peripheral specific RCC operations
1565 * @{
1566 */
1567/**
1568 * @brief Enables the CRC peripheral clock.
1569 *
1570 * @param[in] lp low power enable flag
1571 *
1572 * @api
1573 */
1574#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1575
1576/**
1577 * @brief Disables the CRC peripheral clock.
1578 *
1579 * @api
1580 */
1581#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1582
1583/**
1584 * @brief Resets the CRC peripheral.
1585 *
1586 * @api
1587 */
1588#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1589/** @} */
1590
1591/**
1592 * @name HASH peripheral specific RCC operations
1593 * @{
1594 */
1595/**
1596 * @brief Enables the CRYP peripheral clock.
1597 *
1598 * @param[in] lp low power enable flag
1599 *
1600 * @api
1601 */
1602#define rccEnableCRYP(lp) rccEnableAHB2(RCC_AHB2ENR_CRYPEN, lp)
1603
1604/**
1605 * @brief Disables the CRYP peripheral clock.
1606 *
1607 * @api
1608 */
1609#define rccDisableCRYP() rccDisableAHB2(RCC_AHB2ENR_CRYPEN)
1610
1611/**
1612 * @brief Resets the CRYP peripheral.
1613 *
1614 * @api
1615 */
1616#define rccResetCRYP() rccResetAHB2(RCC_AHB2RSTR_CRYPRST)
1617/** @} */
1618
1619/**
1620 * @name HASH peripheral specific RCC operations
1621 * @{
1622 */
1623/**
1624 * @brief Enables the HASH peripheral clock.
1625 *
1626 * @param[in] lp low power enable flag
1627 *
1628 * @api
1629 */
1630#define rccEnableHASH(lp) rccEnableAHB2(RCC_AHB2ENR_HASHEN, lp)
1631
1632/**
1633 * @brief Disables the HASH peripheral clock.
1634 *
1635 * @api
1636 */
1637#define rccDisableHASH() rccDisableAHB2(RCC_AHB2ENR_HASHEN)
1638
1639/**
1640 * @brief Resets the HASH peripheral.
1641 *
1642 * @api
1643 */
1644#define rccResetHASH() rccResetAHB2(RCC_AHB2RSTR_HASHRST)
1645/** @} */
1646
1647/**
1648 * @name FSMC peripherals specific RCC operations
1649 * @{
1650 */
1651/**
1652 * @brief Enables the FSMC peripheral clock.
1653 *
1654 * @param[in] lp low power enable flag
1655 *
1656 * @api
1657 */
1658#if defined(STM32_FSMC_IS_FMC)
1659 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
1660#else
1661 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
1662#endif
1663
1664/**
1665 * @brief Disables the FSMC peripheral clock.
1666 *
1667 * @api
1668 */
1669#if defined(STM32_FSMC_IS_FMC)
1670 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
1671#else
1672 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FSMCEN)
1673#endif
1674
1675/**
1676 * @brief Resets the FSMC peripheral.
1677 *
1678 * @api
1679 */
1680#if defined(STM32_FSMC_IS_FMC)
1681 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
1682#else
1683 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
1684#endif
1685/** @} */
1686
1687/*===========================================================================*/
1688/* External declarations. */
1689/*===========================================================================*/
1690
1691#ifdef __cplusplus
1692extern "C" {
1693#endif
1694#ifdef __cplusplus
1695}
1696#endif
1697
1698#endif /* STM32_RCC_H */
1699
1700/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
new file mode 100644
index 000000000..7db0e69ef
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32F7xx/stm32_registry.h
@@ -0,0 +1,1107 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_registry.h
19 * @brief STM32F7xx capabilities registry.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef STM32_REGISTRY_H
26#define STM32_REGISTRY_H
27
28/*===========================================================================*/
29/* Platform capabilities. */
30/*===========================================================================*/
31
32/**
33 * @name STM32F7xx capabilities
34 * @{
35 */
36
37/*===========================================================================*/
38/* Common. */
39/*===========================================================================*/
40
41/* RNG attributes.*/
42#define STM32_HAS_RNG1 TRUE
43
44/* RTC attributes.*/
45#define STM32_HAS_RTC TRUE
46#define STM32_RTC_HAS_SUBSECONDS TRUE
47#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
48#define STM32_RTC_NUM_ALARMS 2
49#define STM32_RTC_STORAGE_SIZE 128
50#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
51#define STM32_RTC_WKUP_HANDLER Vector4C
52#define STM32_RTC_ALARM_HANDLER VectorE4
53#define STM32_RTC_TAMP_STAMP_NUMBER 2
54#define STM32_RTC_WKUP_NUMBER 3
55#define STM32_RTC_ALARM_NUMBER 41
56#define STM32_RTC_ALARM_EXTI 17
57#define STM32_RTC_TAMP_STAMP_EXTI 21
58#define STM32_RTC_WKUP_EXTI 22
59#define STM32_RTC_IRQ_ENABLE() do { \
60 nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI21_PRIORITY); \
61 nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI22_PRIORITY); \
62 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
63} while (false)
64
65#if defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F756xx) || \
66 defined(STM32F777xx) || defined(STM32F779xx) || defined(__DOXYGEN__)
67#define STM32_HAS_HASH1 TRUE
68#define STM32_HAS_CRYP1 TRUE
69#define STM32_HASH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
70#define STM32_HASH1_DMA_CHN 0x20000000
71#define STM32_CRYP1_IN_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6)
72#define STM32_CRYP1_IN_DMA_CHN 0x02000000
73#define STM32_CRYP1_OUT_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
74#define STM32_CRYP1_OUT_DMA_CHN 0x00200000
75
76#else /* Devices without cryp nor hash.*/
77#define STM32_HAS_HASH1 FALSE
78#define STM32_HAS_CRYP1 FALSE
79#endif
80
81/*===========================================================================*/
82/* STM32F722xx, STM32F723xx, STM32F732xx, STM32F733xx. */
83/*===========================================================================*/
84#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || \
85 defined(STM32F733xx) || defined(__DOXYGEN__)
86/* ADC attributes.*/
87#define STM32_HAS_ADC1 TRUE
88#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
89 STM32_DMA_STREAM_ID_MSK(2, 4))
90#define STM32_ADC1_DMA_CHN 0x00000000
91
92#define STM32_HAS_ADC2 TRUE
93#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
94 STM32_DMA_STREAM_ID_MSK(2, 3))
95#define STM32_ADC2_DMA_CHN 0x00001100
96
97#define STM32_HAS_ADC3 TRUE
98#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
99 STM32_DMA_STREAM_ID_MSK(2, 1))
100#define STM32_ADC3_DMA_CHN 0x00000022
101
102#define STM32_HAS_ADC4 FALSE
103
104#define STM32_HAS_SDADC1 FALSE
105#define STM32_HAS_SDADC2 FALSE
106#define STM32_HAS_SDADC3 FALSE
107
108/* CAN attributes.*/
109#define STM32_CAN_MAX_FILTERS 28
110
111#define STM32_HAS_CAN1 TRUE
112#define STM32_HAS_CAN2 FALSE
113#define STM32_HAS_CAN3 FALSE
114
115/* DAC attributes.*/
116#define STM32_HAS_DAC1_CH1 TRUE
117#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
118#define STM32_DAC1_CH1_DMA_CHN 0x00700000
119
120#define STM32_HAS_DAC1_CH2 TRUE
121#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
122#define STM32_DAC1_CH2_DMA_CHN 0x07000000
123
124#define STM32_HAS_DAC2_CH1 FALSE
125#define STM32_HAS_DAC2_CH2 FALSE
126
127/* DMA attributes.*/
128#define STM32_ADVANCED_DMA TRUE
129#define STM32_DMA_CACHE_HANDLING TRUE
130#define STM32_DMA_SUPPORTS_DMAMUX FALSE
131
132#define STM32_HAS_DMA1 TRUE
133#define STM32_HAS_DMA2 TRUE
134
135/* ETH attributes.*/
136#define STM32_HAS_ETH FALSE
137
138/* EXTI attributes.*/
139#define STM32_EXTI_NUM_LINES 24
140#define STM32_EXTI_IMR1_MASK 0xFF000000
141
142/* GPIO attributes.*/
143#define STM32_HAS_GPIOA TRUE
144#define STM32_HAS_GPIOB TRUE
145#define STM32_HAS_GPIOC TRUE
146#define STM32_HAS_GPIOD TRUE
147#define STM32_HAS_GPIOE TRUE
148#define STM32_HAS_GPIOH TRUE
149#define STM32_HAS_GPIOF TRUE
150#define STM32_HAS_GPIOG TRUE
151#define STM32_HAS_GPIOI TRUE
152#define STM32_HAS_GPIOJ FALSE
153#define STM32_HAS_GPIOK FALSE
154#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
155 RCC_AHB1ENR_GPIOBEN | \
156 RCC_AHB1ENR_GPIOCEN | \
157 RCC_AHB1ENR_GPIODEN | \
158 RCC_AHB1ENR_GPIOEEN | \
159 RCC_AHB1ENR_GPIOFEN | \
160 RCC_AHB1ENR_GPIOGEN | \
161 RCC_AHB1ENR_GPIOHEN | \
162 RCC_AHB1ENR_GPIOIEN)
163
164/* I2C attributes.*/
165#define STM32_HAS_I2C1 TRUE
166#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
167 STM32_DMA_STREAM_ID_MSK(1, 5))
168#define STM32_I2C1_RX_DMA_CHN 0x00100001
169#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
170 STM32_DMA_STREAM_ID_MSK(1, 6))
171#define STM32_I2C1_TX_DMA_CHN 0x11000000
172
173#define STM32_HAS_I2C2 TRUE
174#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
175 STM32_DMA_STREAM_ID_MSK(1, 3))
176#define STM32_I2C2_RX_DMA_CHN 0x00007700
177#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
178#define STM32_I2C2_TX_DMA_CHN 0x70000000
179
180#define STM32_HAS_I2C3 TRUE
181#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
182 STM32_DMA_STREAM_ID_MSK(1, 2))
183#define STM32_I2C3_RX_DMA_CHN 0x00000310
184#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
185#define STM32_I2C3_TX_DMA_CHN 0x00030000
186
187#define STM32_HAS_I2C4 FALSE
188
189/* QUADSPI attributes.*/
190#define STM32_HAS_QUADSPI1 TRUE
191#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
192#define STM32_QUADSPI1_DMA_CHN 0x30000000
193
194/* RTC attributes.*/
195#define STM32_HAS_RTC TRUE
196#define STM32_RTC_HAS_SUBSECONDS TRUE
197#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
198#define STM32_RTC_NUM_ALARMS 2
199#define STM32_RTC_HAS_INTERRUPTS FALSE
200
201/* SDMMC attributes.*/
202#define STM32_HAS_SDMMC1 TRUE
203#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
204 STM32_DMA_STREAM_ID_MSK(2, 6))
205#define STM32_SDC_SDMMC1_DMA_CHN 0x04004000
206
207#define STM32_HAS_SDMMC2 TRUE
208#define STM32_SDC_SDMMC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
209 STM32_DMA_STREAM_ID_MSK(2, 5))
210#define STM32_SDC_SDMMC2_DMA_CHN 0x00B0000B
211
212/* SPI attributes.*/
213#define STM32_HAS_SPI1 TRUE
214#define STM32_SPI1_SUPPORTS_I2S TRUE
215#define STM32_SPI1_I2S_FULLDUPLEX TRUE
216#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
217 STM32_DMA_STREAM_ID_MSK(2, 2))
218#define STM32_SPI1_RX_DMA_CHN 0x00000303
219#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
220 STM32_DMA_STREAM_ID_MSK(2, 5))
221#define STM32_SPI1_TX_DMA_CHN 0x00303000
222
223#define STM32_HAS_SPI2 TRUE
224#define STM32_SPI2_SUPPORTS_I2S TRUE
225#define STM32_SPI2_I2S_FULLDUPLEX TRUE
226#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
227#define STM32_SPI2_RX_DMA_CHN 0x00000000
228#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
229#define STM32_SPI2_TX_DMA_CHN 0x00000000
230
231#define STM32_HAS_SPI3 TRUE
232#define STM32_SPI3_SUPPORTS_I2S TRUE
233#define STM32_SPI3_I2S_FULLDUPLEX TRUE
234#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
235 STM32_DMA_STREAM_ID_MSK(1, 2))
236#define STM32_SPI3_RX_DMA_CHN 0x00000000
237#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
238 STM32_DMA_STREAM_ID_MSK(1, 7))
239#define STM32_SPI3_TX_DMA_CHN 0x00000000
240
241#define STM32_HAS_SPI4 TRUE
242#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
243 STM32_DMA_STREAM_ID_MSK(2, 3))
244#define STM32_SPI4_RX_DMA_CHN 0x00005004
245#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
246 STM32_DMA_STREAM_ID_MSK(2, 4))
247#define STM32_SPI4_TX_DMA_CHN 0x00050040
248
249#define STM32_HAS_SPI5 TRUE
250#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
251 STM32_DMA_STREAM_ID_MSK(2, 5))
252#define STM32_SPI5_RX_DMA_CHN 0x00702000
253#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
254 STM32_DMA_STREAM_ID_MSK(2, 6))
255#define STM32_SPI5_TX_DMA_CHN 0x07020000
256
257#define STM32_HAS_SPI6 FALSE
258
259/* TIM attributes.*/
260#define STM32_TIM_MAX_CHANNELS 6
261
262#define STM32_HAS_TIM1 TRUE
263#define STM32_TIM1_IS_32BITS FALSE
264#define STM32_TIM1_CHANNELS 6
265
266#define STM32_HAS_TIM2 TRUE
267#define STM32_TIM2_IS_32BITS TRUE
268#define STM32_TIM2_CHANNELS 4
269
270#define STM32_HAS_TIM3 TRUE
271#define STM32_TIM3_IS_32BITS FALSE
272#define STM32_TIM3_CHANNELS 4
273
274#define STM32_HAS_TIM4 TRUE
275#define STM32_TIM4_IS_32BITS FALSE
276#define STM32_TIM4_CHANNELS 4
277
278#define STM32_HAS_TIM5 TRUE
279#define STM32_TIM5_IS_32BITS TRUE
280#define STM32_TIM5_CHANNELS 4
281
282#define STM32_HAS_TIM6 TRUE
283#define STM32_TIM6_IS_32BITS FALSE
284#define STM32_TIM6_CHANNELS 0
285
286#define STM32_HAS_TIM7 TRUE
287#define STM32_TIM7_IS_32BITS FALSE
288#define STM32_TIM7_CHANNELS 0
289
290#define STM32_HAS_TIM8 TRUE
291#define STM32_TIM8_IS_32BITS FALSE
292#define STM32_TIM8_CHANNELS 6
293
294#define STM32_HAS_TIM9 TRUE
295#define STM32_TIM9_IS_32BITS FALSE
296#define STM32_TIM9_CHANNELS 2
297
298#define STM32_HAS_TIM10 TRUE
299#define STM32_TIM10_IS_32BITS FALSE
300#define STM32_TIM10_CHANNELS 1
301
302#define STM32_HAS_TIM11 TRUE
303#define STM32_TIM11_IS_32BITS FALSE
304#define STM32_TIM11_CHANNELS 1
305
306#define STM32_HAS_TIM12 TRUE
307#define STM32_TIM12_IS_32BITS FALSE
308#define STM32_TIM12_CHANNELS 2
309
310#define STM32_HAS_TIM13 TRUE
311#define STM32_TIM13_IS_32BITS FALSE
312#define STM32_TIM13_CHANNELS 1
313
314#define STM32_HAS_TIM14 TRUE
315#define STM32_TIM14_IS_32BITS FALSE
316#define STM32_TIM14_CHANNELS 1
317
318#define STM32_HAS_TIM15 FALSE
319#define STM32_HAS_TIM16 FALSE
320#define STM32_HAS_TIM17 FALSE
321#define STM32_HAS_TIM18 FALSE
322#define STM32_HAS_TIM19 FALSE
323#define STM32_HAS_TIM20 FALSE
324#define STM32_HAS_TIM21 FALSE
325#define STM32_HAS_TIM22 FALSE
326
327/* USART attributes.*/
328#define STM32_HAS_USART1 TRUE
329#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
330 STM32_DMA_STREAM_ID_MSK(2, 5))
331#define STM32_USART1_RX_DMA_CHN 0x00400400
332#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
333#define STM32_USART1_TX_DMA_CHN 0x40000000
334
335#define STM32_HAS_USART2 TRUE
336#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
337#define STM32_USART2_RX_DMA_CHN 0x00400000
338#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
339#define STM32_USART2_TX_DMA_CHN 0x04000000
340
341#define STM32_HAS_USART3 TRUE
342#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
343#define STM32_USART3_RX_DMA_CHN 0x00000040
344#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
345 STM32_DMA_STREAM_ID_MSK(1, 4))
346#define STM32_USART3_TX_DMA_CHN 0x00074000
347
348#define STM32_HAS_UART4 TRUE
349#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
350#define STM32_UART4_RX_DMA_CHN 0x00000400
351#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
352#define STM32_UART4_TX_DMA_CHN 0x00040000
353
354#define STM32_HAS_UART5 TRUE
355#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
356#define STM32_UART5_RX_DMA_CHN 0x00000004
357#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
358#define STM32_UART5_TX_DMA_CHN 0x40000000
359
360#define STM32_HAS_USART6 TRUE
361#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
362 STM32_DMA_STREAM_ID_MSK(2, 2))
363#define STM32_USART6_RX_DMA_CHN 0x00000550
364#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
365 STM32_DMA_STREAM_ID_MSK(2, 7))
366#define STM32_USART6_TX_DMA_CHN 0x55000000
367
368#define STM32_HAS_UART7 TRUE
369#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
370#define STM32_UART7_RX_DMA_CHN 0x00005000
371#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
372#define STM32_UART7_TX_DMA_CHN 0x00000050
373
374#define STM32_HAS_UART8 TRUE
375#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
376#define STM32_UART8_RX_DMA_CHN 0x05000000
377#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
378#define STM32_UART8_TX_DMA_CHN 0x00000005
379
380#define STM32_HAS_LPUART1 FALSE
381
382/* USB attributes.*/
383#define STM32_OTG_STEPPING 2
384#define STM32_HAS_OTG1 TRUE
385#define STM32_OTG1_ENDPOINTS 5
386
387#define STM32_HAS_OTG2 TRUE
388#define STM32_OTG2_ENDPOINTS 8
389
390#define STM32_HAS_USB FALSE
391
392/* IWDG attributes.*/
393#define STM32_HAS_IWDG TRUE
394#define STM32_IWDG_IS_WINDOWED TRUE
395
396/* LTDC attributes.*/
397#define STM32_HAS_LTDC TRUE
398
399/* DMA2D attributes.*/
400#define STM32_HAS_DMA2D TRUE
401
402/* FSMC attributes.*/
403#define STM32_HAS_FSMC TRUE
404#define STM32_FSMC_IS_FMC TRUE
405
406/* CRC attributes.*/
407#define STM32_HAS_CRC TRUE
408#define STM32_CRC_PROGRAMMABLE TRUE
409
410#endif /* defined(STM32F722xx) || defined(STM32F723xx) ||
411 defined(STM32F732xx) || defined(STM32F733xx) */
412
413/*===========================================================================*/
414/* STM32F745xx, STM32F746xx, STM32F756xx. */
415/*===========================================================================*/
416#if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \
417 defined(__DOXYGEN__)
418/* ADC attributes.*/
419#define STM32_HAS_ADC1 TRUE
420#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
421 STM32_DMA_STREAM_ID_MSK(2, 4))
422#define STM32_ADC1_DMA_CHN 0x00000000
423
424#define STM32_HAS_ADC2 TRUE
425#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
426 STM32_DMA_STREAM_ID_MSK(2, 3))
427#define STM32_ADC2_DMA_CHN 0x00001100
428
429#define STM32_HAS_ADC3 TRUE
430#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
431 STM32_DMA_STREAM_ID_MSK(2, 1))
432#define STM32_ADC3_DMA_CHN 0x00000022
433
434#define STM32_HAS_ADC4 FALSE
435
436#define STM32_HAS_SDADC1 FALSE
437#define STM32_HAS_SDADC2 FALSE
438#define STM32_HAS_SDADC3 FALSE
439
440/* CAN attributes.*/
441#define STM32_CAN_MAX_FILTERS 28
442#define STM32_CAN3_MAX_FILTERS 14
443
444#define STM32_HAS_CAN1 TRUE
445#define STM32_HAS_CAN2 TRUE
446#define STM32_HAS_CAN3 TRUE
447
448/* DAC attributes.*/
449#define STM32_HAS_DAC1_CH1 TRUE
450#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
451#define STM32_DAC1_CH1_DMA_CHN 0x00700000
452
453#define STM32_HAS_DAC1_CH2 TRUE
454#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
455#define STM32_DAC1_CH2_DMA_CHN 0x07000000
456
457#define STM32_HAS_DAC2_CH1 FALSE
458#define STM32_HAS_DAC2_CH2 FALSE
459
460/* DMA attributes.*/
461#define STM32_ADVANCED_DMA TRUE
462#define STM32_DMA_CACHE_HANDLING TRUE
463#define STM32_DMA_SUPPORTS_DMAMUX FALSE
464
465#define STM32_HAS_DMA1 TRUE
466#define STM32_HAS_DMA2 TRUE
467
468/* ETH attributes.*/
469#define STM32_HAS_ETH TRUE
470
471/* EXTI attributes.*/
472#define STM32_EXTI_NUM_LINES 24
473#define STM32_EXTI_IMR1_MASK 0xFF000000
474
475/* GPIO attributes.*/
476#define STM32_HAS_GPIOA TRUE
477#define STM32_HAS_GPIOB TRUE
478#define STM32_HAS_GPIOC TRUE
479#define STM32_HAS_GPIOD TRUE
480#define STM32_HAS_GPIOE TRUE
481#define STM32_HAS_GPIOH TRUE
482#define STM32_HAS_GPIOF TRUE
483#define STM32_HAS_GPIOG TRUE
484#define STM32_HAS_GPIOI TRUE
485#define STM32_HAS_GPIOJ TRUE
486#define STM32_HAS_GPIOK TRUE
487#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
488 RCC_AHB1ENR_GPIOBEN | \
489 RCC_AHB1ENR_GPIOCEN | \
490 RCC_AHB1ENR_GPIODEN | \
491 RCC_AHB1ENR_GPIOEEN | \
492 RCC_AHB1ENR_GPIOFEN | \
493 RCC_AHB1ENR_GPIOGEN | \
494 RCC_AHB1ENR_GPIOHEN | \
495 RCC_AHB1ENR_GPIOIEN | \
496 RCC_AHB1ENR_GPIOJEN | \
497 RCC_AHB1ENR_GPIOKEN)
498
499/* I2C attributes.*/
500#define STM32_HAS_I2C1 TRUE
501#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
502 STM32_DMA_STREAM_ID_MSK(1, 5))
503#define STM32_I2C1_RX_DMA_CHN 0x00100001
504#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
505 STM32_DMA_STREAM_ID_MSK(1, 6))
506#define STM32_I2C1_TX_DMA_CHN 0x11000000
507
508#define STM32_HAS_I2C2 TRUE
509#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
510 STM32_DMA_STREAM_ID_MSK(1, 3))
511#define STM32_I2C2_RX_DMA_CHN 0x00007700
512#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
513#define STM32_I2C2_TX_DMA_CHN 0x70000000
514
515#define STM32_HAS_I2C3 TRUE
516#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
517 STM32_DMA_STREAM_ID_MSK(1, 2))
518#define STM32_I2C3_RX_DMA_CHN 0x00000310
519#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
520#define STM32_I2C3_TX_DMA_CHN 0x00030000
521
522#define STM32_HAS_I2C4 TRUE
523#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
524#define STM32_I2C4_RX_DMA_CHN 0x00000200
525#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
526#define STM32_I2C4_TX_DMA_CHN 0x00200000
527
528/* QUADSPI attributes.*/
529#define STM32_HAS_QUADSPI1 TRUE
530#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
531#define STM32_QUADSPI1_DMA_CHN 0x30000000
532
533/* RTC attributes.*/
534#define STM32_HAS_RTC TRUE
535#define STM32_RTC_HAS_SUBSECONDS TRUE
536#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
537#define STM32_RTC_NUM_ALARMS 2
538#define STM32_RTC_HAS_INTERRUPTS FALSE
539
540/* SDMMC attributes.*/
541#define STM32_HAS_SDMMC1 TRUE
542#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
543 STM32_DMA_STREAM_ID_MSK(2, 6))
544#define STM32_SDC_SDMMC1_DMA_CHN 0x04004000
545
546#define STM32_HAS_SDMMC2 FALSE
547
548/* SPI attributes.*/
549#define STM32_HAS_SPI1 TRUE
550#define STM32_SPI1_SUPPORTS_I2S TRUE
551#define STM32_SPI1_I2S_FULLDUPLEX TRUE
552#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
553 STM32_DMA_STREAM_ID_MSK(2, 2))
554#define STM32_SPI1_RX_DMA_CHN 0x00000303
555#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
556 STM32_DMA_STREAM_ID_MSK(2, 5))
557#define STM32_SPI1_TX_DMA_CHN 0x00303000
558
559#define STM32_HAS_SPI2 TRUE
560#define STM32_SPI2_SUPPORTS_I2S TRUE
561#define STM32_SPI2_I2S_FULLDUPLEX TRUE
562#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
563#define STM32_SPI2_RX_DMA_CHN 0x00000000
564#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
565#define STM32_SPI2_TX_DMA_CHN 0x00000000
566
567#define STM32_HAS_SPI3 TRUE
568#define STM32_SPI3_SUPPORTS_I2S TRUE
569#define STM32_SPI3_I2S_FULLDUPLEX TRUE
570#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
571 STM32_DMA_STREAM_ID_MSK(1, 2))
572#define STM32_SPI3_RX_DMA_CHN 0x00000000
573#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
574 STM32_DMA_STREAM_ID_MSK(1, 7))
575#define STM32_SPI3_TX_DMA_CHN 0x00000000
576
577#define STM32_HAS_SPI4 TRUE
578#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
579 STM32_DMA_STREAM_ID_MSK(2, 3))
580#define STM32_SPI4_RX_DMA_CHN 0x00005004
581#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
582 STM32_DMA_STREAM_ID_MSK(2, 4))
583#define STM32_SPI4_TX_DMA_CHN 0x00050040
584
585#define STM32_HAS_SPI5 TRUE
586#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
587 STM32_DMA_STREAM_ID_MSK(2, 5))
588#define STM32_SPI5_RX_DMA_CHN 0x00702000
589#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
590 STM32_DMA_STREAM_ID_MSK(2, 6))
591#define STM32_SPI5_TX_DMA_CHN 0x07020000
592
593#define STM32_HAS_SPI6 TRUE
594#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
595#define STM32_SPI6_RX_DMA_CHN 0x01000000
596#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
597#define STM32_SPI6_TX_DMA_CHN 0x00100000
598
599/* TIM attributes.*/
600#define STM32_TIM_MAX_CHANNELS 6
601
602#define STM32_HAS_TIM1 TRUE
603#define STM32_TIM1_IS_32BITS FALSE
604#define STM32_TIM1_CHANNELS 6
605
606#define STM32_HAS_TIM2 TRUE
607#define STM32_TIM2_IS_32BITS TRUE
608#define STM32_TIM2_CHANNELS 4
609
610#define STM32_HAS_TIM3 TRUE
611#define STM32_TIM3_IS_32BITS FALSE
612#define STM32_TIM3_CHANNELS 4
613
614#define STM32_HAS_TIM4 TRUE
615#define STM32_TIM4_IS_32BITS FALSE
616#define STM32_TIM4_CHANNELS 4
617
618#define STM32_HAS_TIM5 TRUE
619#define STM32_TIM5_IS_32BITS TRUE
620#define STM32_TIM5_CHANNELS 4
621
622#define STM32_HAS_TIM6 TRUE
623#define STM32_TIM6_IS_32BITS FALSE
624#define STM32_TIM6_CHANNELS 0
625
626#define STM32_HAS_TIM7 TRUE
627#define STM32_TIM7_IS_32BITS FALSE
628#define STM32_TIM7_CHANNELS 0
629
630#define STM32_HAS_TIM8 TRUE
631#define STM32_TIM8_IS_32BITS FALSE
632#define STM32_TIM8_CHANNELS 6
633
634#define STM32_HAS_TIM9 TRUE
635#define STM32_TIM9_IS_32BITS FALSE
636#define STM32_TIM9_CHANNELS 2
637
638#define STM32_HAS_TIM10 TRUE
639#define STM32_TIM10_IS_32BITS FALSE
640#define STM32_TIM10_CHANNELS 1
641
642#define STM32_HAS_TIM11 TRUE
643#define STM32_TIM11_IS_32BITS FALSE
644#define STM32_TIM11_CHANNELS 1
645
646#define STM32_HAS_TIM12 TRUE
647#define STM32_TIM12_IS_32BITS FALSE
648#define STM32_TIM12_CHANNELS 2
649
650#define STM32_HAS_TIM13 TRUE
651#define STM32_TIM13_IS_32BITS FALSE
652#define STM32_TIM13_CHANNELS 1
653
654#define STM32_HAS_TIM14 TRUE
655#define STM32_TIM14_IS_32BITS FALSE
656#define STM32_TIM14_CHANNELS 1
657
658#define STM32_HAS_TIM15 FALSE
659#define STM32_HAS_TIM16 FALSE
660#define STM32_HAS_TIM17 FALSE
661#define STM32_HAS_TIM18 FALSE
662#define STM32_HAS_TIM19 FALSE
663#define STM32_HAS_TIM20 FALSE
664#define STM32_HAS_TIM21 FALSE
665#define STM32_HAS_TIM22 FALSE
666
667/* USART attributes.*/
668#define STM32_HAS_USART1 TRUE
669#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
670 STM32_DMA_STREAM_ID_MSK(2, 5))
671#define STM32_USART1_RX_DMA_CHN 0x00400400
672#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
673#define STM32_USART1_TX_DMA_CHN 0x40000000
674
675#define STM32_HAS_USART2 TRUE
676#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
677#define STM32_USART2_RX_DMA_CHN 0x00400000
678#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
679#define STM32_USART2_TX_DMA_CHN 0x04000000
680
681#define STM32_HAS_USART3 TRUE
682#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
683#define STM32_USART3_RX_DMA_CHN 0x00000040
684#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
685 STM32_DMA_STREAM_ID_MSK(1, 4))
686#define STM32_USART3_TX_DMA_CHN 0x00074000
687
688#define STM32_HAS_UART4 TRUE
689#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
690#define STM32_UART4_RX_DMA_CHN 0x00000400
691#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
692#define STM32_UART4_TX_DMA_CHN 0x00040000
693
694#define STM32_HAS_UART5 TRUE
695#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
696#define STM32_UART5_RX_DMA_CHN 0x00000004
697#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
698#define STM32_UART5_TX_DMA_CHN 0x40000000
699
700#define STM32_HAS_USART6 TRUE
701#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
702 STM32_DMA_STREAM_ID_MSK(2, 2))
703#define STM32_USART6_RX_DMA_CHN 0x00000550
704#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
705 STM32_DMA_STREAM_ID_MSK(2, 7))
706#define STM32_USART6_TX_DMA_CHN 0x55000000
707
708#define STM32_HAS_UART7 TRUE
709#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
710#define STM32_UART7_RX_DMA_CHN 0x00005000
711#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
712#define STM32_UART7_TX_DMA_CHN 0x00000050
713
714#define STM32_HAS_UART8 TRUE
715#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
716#define STM32_UART8_RX_DMA_CHN 0x05000000
717#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
718#define STM32_UART8_TX_DMA_CHN 0x00000005
719
720#define STM32_HAS_LPUART1 FALSE
721
722/* USB attributes.*/
723#define STM32_OTG_STEPPING 2
724#define STM32_HAS_OTG1 TRUE
725#define STM32_OTG1_ENDPOINTS 5
726
727#define STM32_HAS_OTG2 TRUE
728#define STM32_OTG2_ENDPOINTS 8
729
730#define STM32_HAS_USB FALSE
731
732/* IWDG attributes.*/
733#define STM32_HAS_IWDG TRUE
734#define STM32_IWDG_IS_WINDOWED TRUE
735
736/* LTDC attributes.*/
737#define STM32_HAS_LTDC TRUE
738
739/* DMA2D attributes.*/
740#define STM32_HAS_DMA2D TRUE
741
742/* FSMC attributes.*/
743#define STM32_HAS_FSMC TRUE
744#define STM32_FSMC_IS_FMC TRUE
745
746/* CRC attributes.*/
747#define STM32_HAS_CRC TRUE
748#define STM32_CRC_PROGRAMMABLE FALSE
749
750#endif /* defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) */
751
752/*===========================================================================*/
753/* STM32F765xx, STM32F767xx, STM32F769xx, STM32F777xx, STM32F779xx. */
754/*===========================================================================*/
755#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || \
756 defined(STM32F777xx) || defined(STM32F779xx) || \
757 defined(__DOXYGEN__)
758/* ADC attributes.*/
759#define STM32_HAS_ADC1 TRUE
760#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
761 STM32_DMA_STREAM_ID_MSK(2, 4))
762#define STM32_ADC1_DMA_CHN 0x00000000
763
764#define STM32_HAS_ADC2 TRUE
765#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
766 STM32_DMA_STREAM_ID_MSK(2, 3))
767#define STM32_ADC2_DMA_CHN 0x00001100
768
769#define STM32_HAS_ADC3 TRUE
770#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
771 STM32_DMA_STREAM_ID_MSK(2, 1))
772#define STM32_ADC3_DMA_CHN 0x00000022
773
774#define STM32_HAS_ADC4 FALSE
775
776#define STM32_HAS_SDADC1 FALSE
777#define STM32_HAS_SDADC2 FALSE
778#define STM32_HAS_SDADC3 FALSE
779
780/* CAN attributes.*/
781#define STM32_CAN_MAX_FILTERS 28
782#define STM32_CAN3_MAX_FILTERS 14
783
784#define STM32_HAS_CAN1 TRUE
785#define STM32_HAS_CAN2 TRUE
786#define STM32_HAS_CAN3 TRUE
787
788/* DAC attributes.*/
789#define STM32_HAS_DAC1_CH1 TRUE
790#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
791#define STM32_DAC1_CH1_DMA_CHN 0x00700000
792
793#define STM32_HAS_DAC1_CH2 TRUE
794#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
795#define STM32_DAC1_CH2_DMA_CHN 0x07000000
796
797#define STM32_HAS_DAC2_CH1 FALSE
798#define STM32_HAS_DAC2_CH2 FALSE
799
800/* DMA attributes.*/
801#define STM32_ADVANCED_DMA TRUE
802#define STM32_DMA_CACHE_HANDLING TRUE
803#define STM32_DMA_SUPPORTS_DMAMUX FALSE
804
805#define STM32_HAS_DMA1 TRUE
806#define STM32_HAS_DMA2 TRUE
807
808/* ETH attributes.*/
809#define STM32_HAS_ETH TRUE
810
811/* EXTI attributes.*/
812#define STM32_EXTI_NUM_LINES 24
813#define STM32_EXTI_IMR1_MASK 0xFF000000
814
815/* GPIO attributes.*/
816#define STM32_HAS_GPIOA TRUE
817#define STM32_HAS_GPIOB TRUE
818#define STM32_HAS_GPIOC TRUE
819#define STM32_HAS_GPIOD TRUE
820#define STM32_HAS_GPIOE TRUE
821#define STM32_HAS_GPIOH TRUE
822#define STM32_HAS_GPIOF TRUE
823#define STM32_HAS_GPIOG TRUE
824#define STM32_HAS_GPIOI TRUE
825#define STM32_HAS_GPIOJ TRUE
826#define STM32_HAS_GPIOK TRUE
827#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
828 RCC_AHB1ENR_GPIOBEN | \
829 RCC_AHB1ENR_GPIOCEN | \
830 RCC_AHB1ENR_GPIODEN | \
831 RCC_AHB1ENR_GPIOEEN | \
832 RCC_AHB1ENR_GPIOFEN | \
833 RCC_AHB1ENR_GPIOGEN | \
834 RCC_AHB1ENR_GPIOHEN | \
835 RCC_AHB1ENR_GPIOIEN | \
836 RCC_AHB1ENR_GPIOJEN | \
837 RCC_AHB1ENR_GPIOKEN)
838
839/* I2C attributes.*/
840#define STM32_HAS_I2C1 TRUE
841#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
842 STM32_DMA_STREAM_ID_MSK(1, 5))
843#define STM32_I2C1_RX_DMA_CHN 0x00100001
844#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
845 STM32_DMA_STREAM_ID_MSK(1, 6))
846#define STM32_I2C1_TX_DMA_CHN 0x11000000
847
848#define STM32_HAS_I2C2 TRUE
849#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
850 STM32_DMA_STREAM_ID_MSK(1, 3))
851#define STM32_I2C2_RX_DMA_CHN 0x00007700
852#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
853 STM32_DMA_STREAM_ID_MSK(1, 7))
854#define STM32_I2C2_TX_DMA_CHN 0x70080000
855
856#define STM32_HAS_I2C3 TRUE
857#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
858 STM32_DMA_STREAM_ID_MSK(1, 2))
859#define STM32_I2C3_RX_DMA_CHN 0x00000310
860#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
861 STM32_DMA_STREAM_ID_MSK(1, 4))
862#define STM32_I2C3_TX_DMA_CHN 0x00030008
863
864#define STM32_HAS_I2C4 TRUE
865#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
866 STM32_DMA_STREAM_ID_MSK(1, 1))
867#define STM32_I2C4_RX_DMA_CHN 0x00000280
868#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
869 STM32_DMA_STREAM_ID_MSK(1, 6))
870#define STM32_I2C4_TX_DMA_CHN 0x08200000
871
872/* QUADSPI attributes.*/
873#define STM32_HAS_QUADSPI1 TRUE
874#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
875 STM32_DMA_STREAM_ID_MSK(2, 7))
876#define STM32_QUADSPI1_DMA_CHN 0x30000B00
877
878/* RTC attributes.*/
879#define STM32_HAS_RTC TRUE
880#define STM32_RTC_HAS_SUBSECONDS TRUE
881#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
882#define STM32_RTC_NUM_ALARMS 2
883#define STM32_RTC_HAS_INTERRUPTS FALSE
884
885/* SDMMC attributes.*/
886#define STM32_HAS_SDMMC1 TRUE
887#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
888 STM32_DMA_STREAM_ID_MSK(2, 6))
889#define STM32_SDC_SDMMC1_DMA_CHN 0x04004000
890
891#define STM32_HAS_SDMMC2 TRUE
892#define STM32_SDC_SDMMC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
893 STM32_DMA_STREAM_ID_MSK(2, 5))
894#define STM32_SDC_SDMMC2_DMA_CHN 0x00B0000B
895
896/* SPI attributes.*/
897#define STM32_HAS_SPI1 TRUE
898#define STM32_SPI1_SUPPORTS_I2S TRUE
899#define STM32_SPI1_I2S_FULLDUPLEX TRUE
900#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
901 STM32_DMA_STREAM_ID_MSK(2, 2))
902#define STM32_SPI1_RX_DMA_CHN 0x00000303
903#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
904 STM32_DMA_STREAM_ID_MSK(2, 5))
905#define STM32_SPI1_TX_DMA_CHN 0x00303000
906
907#define STM32_HAS_SPI2 TRUE
908#define STM32_SPI2_SUPPORTS_I2S TRUE
909#define STM32_SPI2_I2S_FULLDUPLEX TRUE
910#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
911 STM32_DMA_STREAM_ID_MSK(1, 3))
912#define STM32_SPI2_RX_DMA_CHN 0x00000090
913#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
914 STM32_DMA_STREAM_ID_MSK(1, 6))
915#define STM32_SPI2_TX_DMA_CHN 0x09000000
916
917#define STM32_HAS_SPI3 TRUE
918#define STM32_SPI3_SUPPORTS_I2S TRUE
919#define STM32_SPI3_I2S_FULLDUPLEX TRUE
920#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
921 STM32_DMA_STREAM_ID_MSK(1, 2))
922#define STM32_SPI3_RX_DMA_CHN 0x00000000
923#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
924 STM32_DMA_STREAM_ID_MSK(1, 7))
925#define STM32_SPI3_TX_DMA_CHN 0x00000000
926
927#define STM32_HAS_SPI4 TRUE
928#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
929 STM32_DMA_STREAM_ID_MSK(2, 3))
930#define STM32_SPI4_RX_DMA_CHN 0x00005004
931#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
932 STM32_DMA_STREAM_ID_MSK(2, 2) |\
933 STM32_DMA_STREAM_ID_MSK(2, 4))
934#define STM32_SPI4_TX_DMA_CHN 0x00050940
935
936#define STM32_HAS_SPI5 TRUE
937#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)|\
938 STM32_DMA_STREAM_ID_MSK(2, 5))
939#define STM32_SPI5_RX_DMA_CHN 0x00902000
940#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4)|\
941 STM32_DMA_STREAM_ID_MSK(2, 6))
942#define STM32_SPI5_TX_DMA_CHN 0x07020000
943
944#define STM32_HAS_SPI6 TRUE
945#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
946#define STM32_SPI6_RX_DMA_CHN 0x01000000
947#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
948#define STM32_SPI6_TX_DMA_CHN 0x00100000
949
950/* TIM attributes.*/
951#define STM32_TIM_MAX_CHANNELS 6
952
953#define STM32_HAS_TIM1 TRUE
954#define STM32_TIM1_IS_32BITS FALSE
955#define STM32_TIM1_CHANNELS 6
956
957#define STM32_HAS_TIM2 TRUE
958#define STM32_TIM2_IS_32BITS TRUE
959#define STM32_TIM2_CHANNELS 4
960
961#define STM32_HAS_TIM3 TRUE
962#define STM32_TIM3_IS_32BITS FALSE
963#define STM32_TIM3_CHANNELS 4
964
965#define STM32_HAS_TIM4 TRUE
966#define STM32_TIM4_IS_32BITS FALSE
967#define STM32_TIM4_CHANNELS 4
968
969#define STM32_HAS_TIM5 TRUE
970#define STM32_TIM5_IS_32BITS TRUE
971#define STM32_TIM5_CHANNELS 4
972
973#define STM32_HAS_TIM6 TRUE
974#define STM32_TIM6_IS_32BITS FALSE
975#define STM32_TIM6_CHANNELS 0
976
977#define STM32_HAS_TIM7 TRUE
978#define STM32_TIM7_IS_32BITS FALSE
979#define STM32_TIM7_CHANNELS 0
980
981#define STM32_HAS_TIM8 TRUE
982#define STM32_TIM8_IS_32BITS FALSE
983#define STM32_TIM8_CHANNELS 6
984
985#define STM32_HAS_TIM9 TRUE
986#define STM32_TIM9_IS_32BITS FALSE
987#define STM32_TIM9_CHANNELS 2
988
989#define STM32_HAS_TIM10 TRUE
990#define STM32_TIM10_IS_32BITS FALSE
991#define STM32_TIM10_CHANNELS 1
992
993#define STM32_HAS_TIM11 TRUE
994#define STM32_TIM11_IS_32BITS FALSE
995#define STM32_TIM11_CHANNELS 1
996
997#define STM32_HAS_TIM12 TRUE
998#define STM32_TIM12_IS_32BITS FALSE
999#define STM32_TIM12_CHANNELS 2
1000
1001#define STM32_HAS_TIM13 TRUE
1002#define STM32_TIM13_IS_32BITS FALSE
1003#define STM32_TIM13_CHANNELS 1
1004
1005#define STM32_HAS_TIM14 TRUE
1006#define STM32_TIM14_IS_32BITS FALSE
1007#define STM32_TIM14_CHANNELS 1
1008
1009#define STM32_HAS_TIM15 FALSE
1010#define STM32_HAS_TIM16 FALSE
1011#define STM32_HAS_TIM17 FALSE
1012#define STM32_HAS_TIM18 FALSE
1013#define STM32_HAS_TIM19 FALSE
1014#define STM32_HAS_TIM20 FALSE
1015#define STM32_HAS_TIM21 FALSE
1016#define STM32_HAS_TIM22 FALSE
1017
1018/* USART attributes.*/
1019#define STM32_HAS_USART1 TRUE
1020#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
1021 STM32_DMA_STREAM_ID_MSK(2, 5))
1022#define STM32_USART1_RX_DMA_CHN 0x00400400
1023#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
1024#define STM32_USART1_TX_DMA_CHN 0x40000000
1025
1026#define STM32_HAS_USART2 TRUE
1027#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
1028#define STM32_USART2_RX_DMA_CHN 0x00400000
1029#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
1030#define STM32_USART2_TX_DMA_CHN 0x04000000
1031
1032#define STM32_HAS_USART3 TRUE
1033#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
1034#define STM32_USART3_RX_DMA_CHN 0x00000040
1035#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
1036 STM32_DMA_STREAM_ID_MSK(1, 4))
1037#define STM32_USART3_TX_DMA_CHN 0x00074000
1038
1039#define STM32_HAS_UART4 TRUE
1040#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
1041#define STM32_UART4_RX_DMA_CHN 0x00000400
1042#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
1043#define STM32_UART4_TX_DMA_CHN 0x00040000
1044
1045#define STM32_HAS_UART5 TRUE
1046#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
1047#define STM32_UART5_RX_DMA_CHN 0x00000004
1048#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
1049#define STM32_UART5_TX_DMA_CHN 0x40000000
1050
1051#define STM32_HAS_USART6 TRUE
1052#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
1053 STM32_DMA_STREAM_ID_MSK(2, 2))
1054#define STM32_USART6_RX_DMA_CHN 0x00000550
1055#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
1056 STM32_DMA_STREAM_ID_MSK(2, 7))
1057#define STM32_USART6_TX_DMA_CHN 0x55000000
1058
1059#define STM32_HAS_UART7 TRUE
1060#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
1061#define STM32_UART7_RX_DMA_CHN 0x00005000
1062#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
1063#define STM32_UART7_TX_DMA_CHN 0x00000050
1064
1065#define STM32_HAS_UART8 TRUE
1066#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
1067#define STM32_UART8_RX_DMA_CHN 0x05000000
1068#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
1069#define STM32_UART8_TX_DMA_CHN 0x00000005
1070
1071#define STM32_HAS_LPUART1 FALSE
1072
1073/* USB attributes.*/
1074#define STM32_OTG_STEPPING 2
1075#define STM32_HAS_OTG1 TRUE
1076#define STM32_OTG1_ENDPOINTS 5
1077
1078#define STM32_HAS_OTG2 TRUE
1079#define STM32_OTG2_ENDPOINTS 8
1080
1081#define STM32_HAS_USB FALSE
1082
1083/* IWDG attributes.*/
1084#define STM32_HAS_IWDG TRUE
1085#define STM32_IWDG_IS_WINDOWED TRUE
1086
1087/* LTDC attributes.*/
1088#define STM32_HAS_LTDC TRUE
1089
1090/* DMA2D attributes.*/
1091#define STM32_HAS_DMA2D TRUE
1092
1093/* FSMC attributes.*/
1094#define STM32_HAS_FSMC TRUE
1095#define STM32_FSMC_IS_FMC TRUE
1096
1097/* CRC attributes.*/
1098#define STM32_HAS_CRC TRUE
1099#define STM32_CRC_PROGRAMMABLE FALSE
1100
1101#endif /* defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) ||
1102 defined(STM32F777xx) || defined(STM32F779xx) */
1103/** @} */
1104
1105#endif /* STM32_REGISTRY_H */
1106
1107/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 06:39:36 +0100