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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32F7xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32f7xx.h.
22 *
23 * @addtogroup STM32F7xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus.
55 *
56 * @param[in] mask APB1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1(mask, lp) { \
62 RCC->APB1ENR |= (mask); \
63 if (lp) \
64 RCC->APB1LPENR |= (mask); \
65 else \
66 RCC->APB1LPENR &= ~(mask); \
67 (void)RCC->APB1LPENR; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus.
72 *
73 * @param[in] mask APB1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1(mask) { \
78 RCC->APB1ENR &= ~(mask); \
79 RCC->APB1LPENR &= ~(mask); \
80 (void)RCC->APB1LPENR; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus.
85 *
86 * @param[in] mask APB1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1(mask) { \
91 RCC->APB1RSTR |= (mask); \
92 RCC->APB1RSTR &= ~(mask); \
93 (void)RCC->APB1RSTR; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB2 bus.
98 *
99 * @param[in] mask APB2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB2(mask, lp) { \
105 RCC->APB2ENR |= (mask); \
106 if (lp) \
107 RCC->APB2LPENR |= (mask); \
108 else \
109 RCC->APB2LPENR &= ~(mask); \
110 (void)RCC->APB2LPENR; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB2 bus.
115 *
116 * @param[in] mask APB2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB2(mask) { \
121 RCC->APB2ENR &= ~(mask); \
122 RCC->APB2LPENR &= ~(mask); \
123 (void)RCC->APB2LPENR; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB2 bus.
128 *
129 * @param[in] mask APB2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB2(mask) { \
134 RCC->APB2RSTR |= (mask); \
135 RCC->APB2RSTR &= ~(mask); \
136 (void)RCC->APB2RSTR; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
141 *
142 * @param[in] mask AHB1 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAHB1(mask, lp) { \
148 RCC->AHB1ENR |= (mask); \
149 if (lp) \
150 RCC->AHB1LPENR |= (mask); \
151 else \
152 RCC->AHB1LPENR &= ~(mask); \
153 (void)RCC->AHB1LPENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
158 *
159 * @param[in] mask AHB1 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAHB1(mask) { \
164 RCC->AHB1ENR &= ~(mask); \
165 RCC->AHB1LPENR &= ~(mask); \
166 (void)RCC->AHB1LPENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the AHB1 bus.
171 *
172 * @param[in] mask AHB1 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAHB1(mask) { \
177 RCC->AHB1RSTR |= (mask); \
178 RCC->AHB1RSTR &= ~(mask); \
179 (void)RCC->AHB1RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
184 *
185 * @param[in] mask AHB2 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB2(mask, lp) { \
191 RCC->AHB2ENR |= (mask); \
192 if (lp) \
193 RCC->AHB2LPENR |= (mask); \
194 else \
195 RCC->AHB2LPENR &= ~(mask); \
196 (void)RCC->AHB2LPENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
201 *
202 * @param[in] mask AHB2 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB2(mask) { \
207 RCC->AHB2ENR &= ~(mask); \
208 RCC->AHB2LPENR &= ~(mask); \
209 (void)RCC->AHB2LPENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB2 bus.
214 *
215 * @param[in] mask AHB2 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB2(mask) { \
220 RCC->AHB2RSTR |= (mask); \
221 RCC->AHB2RSTR &= ~(mask); \
222 (void)RCC->AHB2RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
227 *
228 * @param[in] mask AHB3 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB3(mask, lp) { \
234 RCC->AHB3ENR |= (mask); \
235 if (lp) \
236 RCC->AHB3LPENR |= (mask); \
237 else \
238 RCC->AHB3LPENR &= ~(mask); \
239 (void)RCC->AHB3LPENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
244 *
245 * @param[in] mask AHB3 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB3(mask) { \
250 RCC->AHB3ENR &= ~(mask); \
251 RCC->AHB3LPENR &= ~(mask); \
252 (void)RCC->AHB3LPENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
257 *
258 * @param[in] mask AHB3 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB3(mask) { \
263 RCC->AHB3RSTR |= (mask); \
264 RCC->AHB3RSTR &= ~(mask); \
265 (void)RCC->AHB3RSTR; \
266}
267/** @} */
268
269/**
270 * @name ADC peripherals specific RCC operations
271 * @{
272 */
273/**
274 * @brief Enables the ADC1 peripheral clock.
275 *
276 * @param[in] lp low power enable flag
277 *
278 * @api
279 */
280#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
281
282/**
283 * @brief Disables the ADC1 peripheral clock.
284 *
285 * @api
286 */
287#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
288
289/**
290 * @brief Resets the ADC1 peripheral.
291 *
292 * @api
293 */
294#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
295
296/**
297 * @brief Enables the ADC2 peripheral clock.
298 *
299 * @param[in] lp low power enable flag
300 *
301 * @api
302 */
303#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp)
304
305/**
306 * @brief Disables the ADC2 peripheral clock.
307 *
308 * @api
309 */
310#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
311
312/**
313 * @brief Resets the ADC2 peripheral.
314 *
315 * @api
316 */
317#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
318
319/**
320 * @brief Enables the ADC3 peripheral clock.
321 *
322 * @param[in] lp low power enable flag
323 *
324 * @api
325 */
326#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp)
327
328/**
329 * @brief Disables the ADC3 peripheral clock.
330 *
331 * @api
332 */
333#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
334
335/**
336 * @brief Resets the ADC3 peripheral.
337 *
338 * @api
339 */
340#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
341/** @} */
342
343/**
344 * @name DAC peripheral specific RCC operations
345 * @{
346 */
347/**
348 * @brief Enables the DAC1 peripheral clock.
349 *
350 * @param[in] lp low power enable flag
351 *
352 * @api
353 */
354#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
355
356/**
357 * @brief Disables the DAC1 peripheral clock.
358 *
359 * @api
360 */
361#define rccDisableDAC1() rccDisableAPB1(RCC_APB1ENR_DACEN)
362
363/**
364 * @brief Resets the DAC1 peripheral.
365 *
366 * @api
367 */
368#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
369/** @} */
370
371/**
372 * @name DMA peripheral specific RCC operations
373 * @{
374 */
375/**
376 * @brief Enables the DMA1 peripheral clock.
377 *
378 * @param[in] lp low power enable flag
379 *
380 * @api
381 */
382#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
383
384/**
385 * @brief Disables the DMA1 peripheral clock.
386 *
387 * @api
388 */
389#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
390
391/**
392 * @brief Resets the DMA1 peripheral.
393 *
394 * @api
395 */
396#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
397
398/**
399 * @brief Enables the DMA2 peripheral clock.
400 *
401 * @param[in] lp low power enable flag
402 *
403 * @api
404 */
405#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
406
407/**
408 * @brief Disables the DMA2 peripheral clock.
409 *
410 * @api
411 */
412#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
413
414/**
415 * @brief Resets the DMA2 peripheral.
416 *
417 * @api
418 */
419#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
420/** @} */
421
422/**
423 * @name BKPSRAM specific RCC operations
424 * @{
425 */
426/**
427 * @brief Enables the BKPSRAM peripheral clock.
428 *
429 * @param[in] lp low power enable flag
430 *
431 * @api
432 */
433#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp)
434
435/**
436 * @brief Disables the BKPSRAM peripheral clock.
437 *
438 * @api
439 */
440#define rccDisableBKPSRAM() rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN)
441/** @} */
442
443/**
444 * @name PWR interface specific RCC operations
445 * @{
446 */
447/**
448 * @brief Enables the PWR interface clock.
449 *
450 * @param[in] lp low power enable flag
451 *
452 * @api
453 */
454#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
455
456/**
457 * @brief Disables PWR interface clock.
458 *
459 * @api
460 */
461#define rccDisablePWRInterface() rccDisableAPB1(RCC_APB1ENR_PWREN)
462
463/**
464 * @brief Resets the PWR interface.
465 *
466 * @api
467 */
468#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
469/** @} */
470
471/**
472 * @name CAN peripherals specific RCC operations
473 * @{
474 */
475/**
476 * @brief Enables the CAN1 peripheral clock.
477 *
478 * @param[in] lp low power enable flag
479 *
480 * @api
481 */
482#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
483
484/**
485 * @brief Disables the CAN1 peripheral clock.
486 *
487 * @api
488 */
489#define rccDisableCAN1() rccDisableAPB1(RCC_APB1ENR_CAN1EN)
490
491/**
492 * @brief Resets the CAN1 peripheral.
493 *
494 * @api
495 */
496#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
497
498/**
499 * @brief Enables the CAN2 peripheral clock.
500 *
501 * @param[in] lp low power enable flag
502 *
503 * @api
504 */
505#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp)
506
507/**
508 * @brief Disables the CAN2 peripheral clock.
509 *
510 * @api
511 */
512#define rccDisableCAN2() rccDisableAPB1(RCC_APB1ENR_CAN2EN)
513
514/**
515 * @brief Resets the CAN2 peripheral.
516 *
517 * @api
518 */
519#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
520
521/**
522 * @brief Resets the CAN3 peripheral.
523 *
524 * @api
525 */
526#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST)
527
528/**
529 * @brief Enables the CAN3 peripheral clock.
530 *
531 * @param[in] lp low power enable flag
532 *
533 * @api
534 */
535#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp)
536
537/**
538 * @brief Disables the CAN3 peripheral clock.
539 *
540 * @api
541 */
542#define rccDisableCAN3() rccDisableAPB1(RCC_APB1ENR_CAN3EN)
543/** @} */
544
545/**
546 * @name ETH peripheral specific RCC operations
547 * @{
548 */
549/**
550 * @brief Enables the ETH peripheral clock.
551 *
552 * @api
553 */
554#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
555 RCC_AHB1ENR_ETHMACTXEN | \
556 RCC_AHB1ENR_ETHMACRXEN, lp)
557
558/**
559 * @brief Disables the ETH peripheral clock.
560 *
561 * @param[in] lp low power enable flag
562 *
563 * @api
564 */
565#define rccDisableETH() rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
566 RCC_AHB1ENR_ETHMACTXEN | \
567 RCC_AHB1ENR_ETHMACRXEN)
568
569/**
570 * @brief Resets the ETH peripheral.
571 *
572 * @api
573 */
574#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
575/** @} */
576
577/**
578 * @name I2C peripherals specific RCC operations
579 * @{
580 */
581/**
582 * @brief Enables the I2C1 peripheral clock.
583 *
584 * @param[in] lp low power enable flag
585 *
586 * @api
587 */
588#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
589
590/**
591 * @brief Disables the I2C1 peripheral clock.
592 *
593 * @api
594 */
595#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
596
597/**
598 * @brief Resets the I2C1 peripheral.
599 *
600 * @api
601 */
602#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
603
604/**
605 * @brief Enables the I2C2 peripheral clock.
606 *
607 * @param[in] lp low power enable flag
608 *
609 * @api
610 */
611#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
612
613/**
614 * @brief Disables the I2C2 peripheral clock.
615 *
616 * @api
617 */
618#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
619
620/**
621 * @brief Resets the I2C2 peripheral.
622 *
623 * @api
624 */
625#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
626
627/**
628 * @brief Enables the I2C3 peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
635
636/**
637 * @brief Disables the I2C3 peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableI2C3() rccDisableAPB1(RCC_APB1ENR_I2C3EN)
642
643/**
644 * @brief Resets the I2C3 peripheral.
645 *
646 * @api
647 */
648#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
649
650/**
651 * @brief Enables the I2C4 peripheral clock.
652 *
653 * @param[in] lp low power enable flag
654 *
655 * @api
656 */
657#define rccEnableI2C4(lp) rccEnableAPB1(RCC_APB1ENR_I2C4EN, lp)
658
659/**
660 * @brief Disables the I2C4 peripheral clock.
661 *
662 * @api
663 */
664#define rccDisableI2C4() rccDisableAPB1(RCC_APB1ENR_I2C4EN)
665
666/**
667 * @brief Resets the I2C4 peripheral.
668 *
669 * @api
670 */
671#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_I2C4RST)
672/** @} */
673
674/**
675 * @name OTG peripherals specific RCC operations
676 * @{
677 */
678/**
679 * @brief Enables the OTG_FS peripheral clock.
680 *
681 * @param[in] lp low power enable flag
682 *
683 * @api
684 */
685#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
686
687/**
688 * @brief Disables the OTG_FS peripheral clock.
689 *
690 * @api
691 */
692#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
693
694/**
695 * @brief Resets the OTG_FS peripheral.
696 *
697 * @api
698 */
699#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
700
701/**
702 * @brief Enables the OTG_HS peripheral clock.
703 *
704 * @param[in] lp low power enable flag
705 *
706 * @api
707 */
708#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
709
710/**
711 * @brief Disables the OTG_HS peripheral clock.
712 *
713 * @api
714 */
715#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_OTGHSEN)
716
717/**
718 * @brief Resets the OTG_HS peripheral.
719 *
720 * @api
721 */
722#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST)
723
724/**
725 * @brief Enables the OTG_HS peripheral clock.
726 *
727 * @param[in] lp low power enable flag
728 *
729 * @api
730 */
731#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
732
733/**
734 * @brief Disables the OTG_HS peripheral clock.
735 *
736 * @api
737 */
738#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN)
739/** @} */
740
741/**
742 * @name QUADSPI peripherals specific RCC operations
743 * @{
744 */
745/**
746 * @brief Enables the QUADSPI1 peripheral clock.
747 *
748 * @param[in] lp low power enable flag
749 *
750 * @api
751 */
752#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
753
754/**
755 * @brief Disables the QUADSPI1 peripheral clock.
756 *
757 * @api
758 */
759#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
760
761/**
762 * @brief Resets the QUADSPI1 peripheral.
763 *
764 * @api
765 */
766#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
767/** @} */
768
769/**
770 * @name RNG peripherals specific RCC operations
771 * @{
772 */
773/**
774 * @brief Enables the RNG peripheral clock.
775 *
776 * @param[in] lp low power enable flag
777 *
778 * @api
779 */
780#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
781
782/**
783 * @brief Disables the RNG peripheral clock.
784 *
785 * @api
786 */
787#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
788
789/**
790 * @brief Resets the RNG peripheral.
791 *
792 * @api
793 */
794#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
795/** @} */
796
797/**
798 * @name SDMMC peripheral specific RCC operations
799 * @{
800 */
801/**
802 * @brief Enables the SDMMC1 peripheral clock.
803 *
804 * @param[in] lp low power enable flag
805 *
806 * @api
807 */
808#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
809
810/**
811 * @brief Disables the SDMMC1 peripheral clock.
812 *
813 * @api
814 */
815#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
816
817/**
818 * @brief Resets the SDMMC1 peripheral.
819 *
820 * @api
821 */
822#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
823
824/**
825 * @brief Enables the SDMMC2 peripheral clock.
826 *
827 * @param[in] lp low power enable flag
828 *
829 * @api
830 */
831#define rccEnableSDMMC2(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC2EN, lp)
832
833/**
834 * @brief Disables the SDMMC2 peripheral clock.
835 *
836 * @api
837 */
838#define rccDisableSDMMC2() rccDisableAPB2(RCC_APB2ENR_SDMMC2EN)
839
840/**
841 * @brief Resets the SDMMC2 peripheral.
842 *
843 * @api
844 */
845#define rccResetSDMMC2() rccResetAPB2(RCC_APB2RSTR_SDMMC2RST)
846/** @} */
847
848/**
849 * @name SPI peripherals specific RCC operations
850 * @{
851 */
852/**
853 * @brief Enables the SPI1 peripheral clock.
854 *
855 * @param[in] lp low power enable flag
856 *
857 * @api
858 */
859#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
860
861/**
862 * @brief Disables the SPI1 peripheral clock.
863 *
864 * @api
865 */
866#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
867
868/**
869 * @brief Resets the SPI1 peripheral.
870 *
871 * @api
872 */
873#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
874
875/**
876 * @brief Enables the SPI2 peripheral clock.
877 *
878 * @param[in] lp low power enable flag
879 *
880 * @api
881 */
882#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
883
884/**
885 * @brief Disables the SPI2 peripheral clock.
886 *
887 * @api
888 */
889#define rccDisableSPI2() rccDisableAPB1(RCC_APB1ENR_SPI2EN)
890
891/**
892 * @brief Resets the SPI2 peripheral.
893 *
894 * @api
895 */
896#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
897
898/**
899 * @brief Enables the SPI3 peripheral clock.
900 *
901 * @param[in] lp low power enable flag
902 *
903 * @api
904 */
905#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
906
907/**
908 * @brief Disables the SPI3 peripheral clock.
909 *
910 * @api
911 */
912#define rccDisableSPI3() rccDisableAPB1(RCC_APB1ENR_SPI3EN)
913
914/**
915 * @brief Resets the SPI3 peripheral.
916 *
917 * @api
918 */
919#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
920
921/**
922 * @brief Enables the SPI4 peripheral clock.
923 *
924 * @param[in] lp low power enable flag
925 *
926 * @api
927 */
928#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
929
930/**
931 * @brief Disables the SPI4 peripheral clock.
932 *
933 * @api
934 */
935#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
936
937/**
938 * @brief Resets the SPI4 peripheral.
939 *
940 * @api
941 */
942#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
943
944/**
945 * @brief Enables the SPI5 peripheral clock.
946 *
947 * @param[in] lp low power enable flag
948 *
949 * @api
950 */
951#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp)
952
953/**
954 * @brief Disables the SPI5 peripheral clock.
955 *
956 * @api
957 */
958#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN)
959
960/**
961 * @brief Resets the SPI5 peripheral.
962 *
963 * @api
964 */
965#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST)
966
967/**
968 * @brief Enables the SPI6 peripheral clock.
969 *
970 * @param[in] lp low power enable flag
971 *
972 * @api
973 */
974#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp)
975
976/**
977 * @brief Disables the SPI6 peripheral clock.
978 *
979 * @api
980 */
981#define rccDisableSPI6() rccDisableAPB2(RCC_APB2ENR_SPI6EN)
982
983/**
984 * @brief Resets the SPI6 peripheral.
985 *
986 * @api
987 */
988#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST)
989/** @} */
990
991/**
992 * @name TIM peripherals specific RCC operations
993 * @{
994 */
995/**
996 * @brief Enables the TIM1 peripheral clock.
997 *
998 * @param[in] lp low power enable flag
999 *
1000 * @api
1001 */
1002#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
1003
1004/**
1005 * @brief Disables the TIM1 peripheral clock.
1006 *
1007 * @api
1008 */
1009#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
1010
1011/**
1012 * @brief Resets the TIM1 peripheral.
1013 *
1014 * @api
1015 */
1016#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
1017
1018/**
1019 * @brief Enables the TIM2 peripheral clock.
1020 *
1021 * @param[in] lp low power enable flag
1022 *
1023 * @api
1024 */
1025#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
1026
1027/**
1028 * @brief Disables the TIM2 peripheral clock.
1029 *
1030 * @api
1031 */
1032#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
1033
1034/**
1035 * @brief Resets the TIM2 peripheral.
1036 *
1037 * @api
1038 */
1039#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
1040
1041/**
1042 * @brief Enables the TIM3 peripheral clock.
1043 *
1044 * @param[in] lp low power enable flag
1045 *
1046 * @api
1047 */
1048#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
1049
1050/**
1051 * @brief Disables the TIM3 peripheral clock.
1052 *
1053 * @api
1054 */
1055#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
1056
1057/**
1058 * @brief Resets the TIM3 peripheral.
1059 *
1060 * @api
1061 */
1062#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
1063
1064/**
1065 * @brief Enables the TIM4 peripheral clock.
1066 *
1067 * @param[in] lp low power enable flag
1068 *
1069 * @api
1070 */
1071#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
1072
1073/**
1074 * @brief Disables the TIM4 peripheral clock.
1075 *
1076 * @api
1077 */
1078#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
1079
1080/**
1081 * @brief Resets the TIM4 peripheral.
1082 *
1083 * @api
1084 */
1085#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
1086
1087/**
1088 * @brief Enables the TIM5 peripheral clock.
1089 *
1090 * @param[in] lp low power enable flag
1091 *
1092 * @api
1093 */
1094#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
1095
1096/**
1097 * @brief Disables the TIM5 peripheral clock.
1098 *
1099 * @api
1100 */
1101#define rccDisableTIM5() rccDisableAPB1(RCC_APB1ENR_TIM5EN)
1102
1103/**
1104 * @brief Resets the TIM5 peripheral.
1105 *
1106 * @api
1107 */
1108#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
1109
1110/**
1111 * @brief Enables the TIM6 peripheral clock.
1112 *
1113 * @param[in] lp low power enable flag
1114 *
1115 * @api
1116 */
1117#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
1118
1119/**
1120 * @brief Disables the TIM6 peripheral clock.
1121 *
1122 * @api
1123 */
1124#define rccDisableTIM6() rccDisableAPB1(RCC_APB1ENR_TIM6EN)
1125
1126/**
1127 * @brief Resets the TIM6 peripheral.
1128 *
1129 * @api
1130 */
1131#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
1132
1133/**
1134 * @brief Enables the TIM7 peripheral clock.
1135 *
1136 * @param[in] lp low power enable flag
1137 *
1138 * @api
1139 */
1140#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
1141
1142/**
1143 * @brief Disables the TIM7 peripheral clock.
1144 *
1145 * @api
1146 */
1147#define rccDisableTIM7() rccDisableAPB1(RCC_APB1ENR_TIM7EN)
1148
1149/**
1150 * @brief Resets the TIM7 peripheral.
1151 *
1152 * @api
1153 */
1154#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
1155
1156/**
1157 * @brief Enables the TIM8 peripheral clock.
1158 *
1159 * @param[in] lp low power enable flag
1160 *
1161 * @api
1162 */
1163#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1164
1165/**
1166 * @brief Disables the TIM8 peripheral clock.
1167 *
1168 * @api
1169 */
1170#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1171
1172/**
1173 * @brief Resets the TIM8 peripheral.
1174 *
1175 * @api
1176 */
1177#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1178
1179/**
1180 * @brief Enables the TIM9 peripheral clock.
1181 *
1182 * @param[in] lp low power enable flag
1183 *
1184 * @api
1185 */
1186#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
1187
1188/**
1189 * @brief Disables the TIM9 peripheral clock.
1190 *
1191 * @api
1192 */
1193#define rccDisableTIM9() rccDisableAPB2(RCC_APB2ENR_TIM9EN)
1194
1195/**
1196 * @brief Resets the TIM9 peripheral.
1197 *
1198 * @api
1199 */
1200#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
1201
1202/**
1203 * @brief Enables the TIM10 peripheral clock.
1204 *
1205 * @param[in] lp low power enable flag
1206 *
1207 * @api
1208 */
1209#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
1210
1211/**
1212 * @brief Disables the TIM10 peripheral clock.
1213 *
1214 * @api
1215 */
1216#define rccDisableTIM10() rccDisableAPB2(RCC_APB2ENR_TIM10EN)
1217
1218/**
1219 * @brief Resets the TIM10 peripheral.
1220 *
1221 * @api
1222 */
1223#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
1224
1225/**
1226 * @brief Enables the TIM11 peripheral clock.
1227 *
1228 * @param[in] lp low power enable flag
1229 *
1230 * @api
1231 */
1232#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
1233
1234/**
1235 * @brief Disables the TIM11 peripheral clock.
1236 *
1237 * @api
1238 */
1239#define rccDisableTIM11() rccDisableAPB2(RCC_APB2ENR_TIM11EN)
1240
1241/**
1242 * @brief Resets the TIM11 peripheral.
1243 *
1244 * @api
1245 */
1246#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
1247
1248/**
1249 * @brief Enables the TIM12 peripheral clock.
1250 *
1251 * @param[in] lp low power enable flag
1252 *
1253 * @api
1254 */
1255#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp)
1256
1257/**
1258 * @brief Disables the TIM12 peripheral clock.
1259 *
1260 * @api
1261 */
1262#define rccDisableTIM12() rccDisableAPB1(RCC_APB1ENR_TIM12EN)
1263
1264/**
1265 * @brief Resets the TIM12 peripheral.
1266 *
1267 * @api
1268 */
1269#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
1270
1271/**
1272 * @brief Enables the TIM13 peripheral clock.
1273 *
1274 * @param[in] lp low power enable flag
1275 *
1276 * @api
1277 */
1278#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
1279
1280/**
1281 * @brief Disables the TIM13 peripheral clock.
1282 *
1283 * @api
1284 */
1285#define rccDisableTIM13() rccDisableAPB1(RCC_APB1ENR_TIM13EN)
1286
1287/**
1288 * @brief Resets the TIM13 peripheral.
1289 *
1290 * @api
1291 */
1292#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
1293
1294/**
1295 * @brief Enables the TIM14 peripheral clock.
1296 *
1297 * @param[in] lp low power enable flag
1298 *
1299 * @api
1300 */
1301#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp)
1302
1303/**
1304 * @brief Disables the TIM14 peripheral clock.
1305 *
1306 * @api
1307 */
1308#define rccDisableTIM14() rccDisableAPB1(RCC_APB1ENR_TIM14EN)
1309
1310/**
1311 * @brief Resets the TIM14 peripheral.
1312 *
1313 * @api
1314 */
1315#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
1316/** @} */
1317
1318/**
1319 * @name USART/UART peripherals specific RCC operations
1320 * @{
1321 */
1322/**
1323 * @brief Enables the USART1 peripheral clock.
1324 *
1325 * @param[in] lp low power enable flag
1326 *
1327 * @api
1328 */
1329#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1330
1331/**
1332 * @brief Disables the USART1 peripheral clock.
1333 *
1334 * @api
1335 */
1336#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1337
1338/**
1339 * @brief Resets the USART1 peripheral.
1340 *
1341 * @api
1342 */
1343#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1344
1345/**
1346 * @brief Enables the USART2 peripheral clock.
1347 *
1348 * @param[in] lp low power enable flag
1349 *
1350 * @api
1351 */
1352#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
1353
1354/**
1355 * @brief Disables the USART2 peripheral clock.
1356 *
1357 * @api
1358 */
1359#define rccDisableUSART2() rccDisableAPB1(RCC_APB1ENR_USART2EN)
1360
1361/**
1362 * @brief Resets the USART2 peripheral.
1363 *
1364 * @api
1365 */
1366#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
1367
1368/**
1369 * @brief Enables the USART3 peripheral clock.
1370 *
1371 * @param[in] lp low power enable flag
1372 *
1373 * @api
1374 */
1375#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
1376
1377/**
1378 * @brief Disables the USART3 peripheral clock.
1379 *
1380 * @api
1381 */
1382#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
1383
1384/**
1385 * @brief Resets the USART3 peripheral.
1386 *
1387 * @api
1388 */
1389#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
1390
1391/**
1392 * @brief Enables the UART4 peripheral clock.
1393 *
1394 * @param[in] lp low power enable flag
1395 *
1396 * @api
1397 */
1398#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
1399
1400/**
1401 * @brief Disables the UART4 peripheral clock.
1402 *
1403 * @api
1404 */
1405#define rccDisableUART4() rccDisableAPB1(RCC_APB1ENR_UART4EN)
1406
1407/**
1408 * @brief Resets the UART4 peripheral.
1409 *
1410 * @api
1411 */
1412#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
1413
1414/**
1415 * @brief Enables the UART5 peripheral clock.
1416 *
1417 * @param[in] lp low power enable flag
1418 *
1419 * @api
1420 */
1421#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
1422
1423/**
1424 * @brief Disables the UART5 peripheral clock.
1425 *
1426 * @api
1427 */
1428#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
1429
1430/**
1431 * @brief Resets the UART5 peripheral.
1432 *
1433 * @api
1434 */
1435#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
1436
1437/**
1438 * @brief Enables the USART6 peripheral clock.
1439 *
1440 * @param[in] lp low power enable flag
1441 *
1442 * @api
1443 */
1444#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
1445
1446/**
1447 * @brief Disables the USART6 peripheral clock.
1448 *
1449 * @api
1450 */
1451#define rccDisableUSART6() rccDisableAPB2(RCC_APB2ENR_USART6EN)
1452
1453/**
1454 * @brief Resets the USART6 peripheral.
1455 *
1456 * @api
1457 */
1458#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
1459
1460/**
1461 * @brief Enables the UART7 peripheral clock.
1462 *
1463 * @param[in] lp low power enable flag
1464 *
1465 * @api
1466 */
1467#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp)
1468
1469/**
1470 * @brief Disables the UART7 peripheral clock.
1471 *
1472 * @api
1473 */
1474#define rccDisableUART7() rccDisableAPB1(RCC_APB1ENR_UART7EN)
1475
1476/**
1477 * @brief Resets the UART7 peripheral.
1478 *
1479 * @api
1480 */
1481#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST)
1482
1483/**
1484 * @brief Enables the UART8 peripheral clock.
1485 *
1486 * @param[in] lp low power enable flag
1487 *
1488 * @api
1489 */
1490#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp)
1491
1492/**
1493 * @brief Disables the UART8 peripheral clock.
1494 *
1495 * @api
1496 */
1497#define rccDisableUART8() rccDisableAPB1(RCC_APB1ENR_UART8EN)
1498
1499/**
1500 * @brief Resets the UART8 peripheral.
1501 *
1502 * @api
1503 */
1504#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST)
1505/** @} */
1506
1507/**
1508 * @name LTDC peripheral specific RCC operations
1509 * @{
1510 */
1511/**
1512 * @brief Enables the LTDC peripheral clock.
1513 *
1514 * @param[in] lp low power enable flag
1515 *
1516 * @api
1517 */
1518#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp)
1519
1520/**
1521 * @brief Disables the LTDC peripheral clock.
1522 *
1523 * @api
1524 */
1525#define rccDisableLTDC() rccDisableAPB2(RCC_APB2ENR_LTDCEN)
1526
1527/**
1528 * @brief Resets the LTDC peripheral.
1529 *
1530 * @api
1531 */
1532#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
1533/** @} */
1534
1535/**
1536 * @name DMA2D peripheral specific RCC operations
1537 * @{
1538 */
1539/**
1540 * @brief Enables the DMA2D peripheral clock.
1541 *
1542 * @param[in] lp low power enable flag
1543 *
1544 * @api
1545 */
1546#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)
1547
1548/**
1549 * @brief Disables the DMA2D peripheral clock.
1550 *
1551 * @api
1552 */
1553#define rccDisableDMA2D() rccDisableAHB1(RCC_AHB1ENR_DMA2DEN)
1554
1555/**
1556 * @brief Resets the DMA2D peripheral.
1557 *
1558 * @api
1559 */
1560#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)
1561/** @} */
1562
1563/**
1564 * @name CRC peripheral specific RCC operations
1565 * @{
1566 */
1567/**
1568 * @brief Enables the CRC peripheral clock.
1569 *
1570 * @param[in] lp low power enable flag
1571 *
1572 * @api
1573 */
1574#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1575
1576/**
1577 * @brief Disables the CRC peripheral clock.
1578 *
1579 * @api
1580 */
1581#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1582
1583/**
1584 * @brief Resets the CRC peripheral.
1585 *
1586 * @api
1587 */
1588#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1589/** @} */
1590
1591/**
1592 * @name HASH peripheral specific RCC operations
1593 * @{
1594 */
1595/**
1596 * @brief Enables the CRYP peripheral clock.
1597 *
1598 * @param[in] lp low power enable flag
1599 *
1600 * @api
1601 */
1602#define rccEnableCRYP(lp) rccEnableAHB2(RCC_AHB2ENR_CRYPEN, lp)
1603
1604/**
1605 * @brief Disables the CRYP peripheral clock.
1606 *
1607 * @api
1608 */
1609#define rccDisableCRYP() rccDisableAHB2(RCC_AHB2ENR_CRYPEN)
1610
1611/**
1612 * @brief Resets the CRYP peripheral.
1613 *
1614 * @api
1615 */
1616#define rccResetCRYP() rccResetAHB2(RCC_AHB2RSTR_CRYPRST)
1617/** @} */
1618
1619/**
1620 * @name HASH peripheral specific RCC operations
1621 * @{
1622 */
1623/**
1624 * @brief Enables the HASH peripheral clock.
1625 *
1626 * @param[in] lp low power enable flag
1627 *
1628 * @api
1629 */
1630#define rccEnableHASH(lp) rccEnableAHB2(RCC_AHB2ENR_HASHEN, lp)
1631
1632/**
1633 * @brief Disables the HASH peripheral clock.
1634 *
1635 * @api
1636 */
1637#define rccDisableHASH() rccDisableAHB2(RCC_AHB2ENR_HASHEN)
1638
1639/**
1640 * @brief Resets the HASH peripheral.
1641 *
1642 * @api
1643 */
1644#define rccResetHASH() rccResetAHB2(RCC_AHB2RSTR_HASHRST)
1645/** @} */
1646
1647/**
1648 * @name FSMC peripherals specific RCC operations
1649 * @{
1650 */
1651/**
1652 * @brief Enables the FSMC peripheral clock.
1653 *
1654 * @param[in] lp low power enable flag
1655 *
1656 * @api
1657 */
1658#if defined(STM32_FSMC_IS_FMC)
1659 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
1660#else
1661 #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp)
1662#endif
1663
1664/**
1665 * @brief Disables the FSMC peripheral clock.
1666 *
1667 * @api
1668 */
1669#if defined(STM32_FSMC_IS_FMC)
1670 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
1671#else
1672 #define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FSMCEN)
1673#endif
1674
1675/**
1676 * @brief Resets the FSMC peripheral.
1677 *
1678 * @api
1679 */
1680#if defined(STM32_FSMC_IS_FMC)
1681 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
1682#else
1683 #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST)
1684#endif
1685/** @} */
1686
1687/*===========================================================================*/
1688/* External declarations. */
1689/*===========================================================================*/
1690
1691#ifdef __cplusplus
1692extern "C" {
1693#endif
1694#ifdef __cplusplus
1695}
1696#endif
1697
1698#endif /* STM32_RCC_H */
1699
1700/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:01:16 +0100