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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/hal_lld.h
19 * @brief STM32G4xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32G431xx, STM32G441xx, STM32G471xx.
30 * - STM32G473xx, STM32G483xx.
31 * - STM32G474xx, STM32G484xx.
32 * - STM32GBK1CB.
33 * .
34 *
35 * @addtogroup HAL
36 * @{
37 */
38
39#ifndef HAL_LLD_H
40#define HAL_LLD_H
41
42#include "stm32_registry.h"
43
44/*===========================================================================*/
45/* Driver constants. */
46/*===========================================================================*/
47
48/**
49 * @name Platform identification
50 * @{
51 */
52#if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
53 defined(__DOXYGEN__)
54#define PLATFORM_NAME "STM32G4 Access Line"
55
56#elif defined(STM32G473xx)
57#define PLATFORM_NAME "STM32G4 Performance Line"
58
59#elif defined(STM32G483xx)
60#define PLATFORM_NAME "STM32G4 Performance Line with Crypto"
61
62#elif defined(STM32G474xx)
63#define PLATFORM_NAME "STM32G4 Hi-resolution Line"
64
65#elif defined(STM32G484xx)
66#define PLATFORM_NAME "STM32G4 Hi-resolution Line with Crypto"
67
68#elif defined(STM32GBK1CB)
69#define PLATFORM_NAME "STM32G4 Mystery Line"
70
71#else
72#error "STM32G4 device not specified"
73#endif
74
75/**
76 * @brief Sub-family identifier.
77 */
78#if !defined(STM32G4XX) || defined(__DOXYGEN__)
79#define STM32G4XX
80#endif
81/** @} */
82
83/**
84 * @name Internal clock sources
85 * @{
86 */
87#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
88#define STM32_HSI48CLK 48000000U /**< 48MHz internal clock. */
89#define STM32_LSICLK 32000U /**< Low speed internal clock. */
90/** @} */
91
92/**
93 * @name VOS field definitions
94 * @{
95 */
96#define STM32_VOS_MASK (3U << 9U) /**< Core voltage mask. */
97#define STM32_VOS_RANGE1 (1U << 9U) /**< Core voltage 1.2 Volts. */
98#define STM32_VOS_RANGE2 (2U << 9U) /**< Core voltage 1.0 Volts. */
99/** @} */
100
101/**
102 * @name RCC_CFGR register bits definitions
103 * @{
104 */
105#define STM32_SW_MASK (3U << 0U) /**< SW field mask. */
106#define STM32_SW_HSI16 (1U << 0U) /**< SYSCLK source is HSI16. */
107#define STM32_SW_HSE (2U << 0U) /**< SYSCLK source is HSE. */
108#define STM32_SW_PLLRCLK (3U << 0U) /**< SYSCLK source is PLL. */
109
110#define STM32_HPRE_MASK (15U << 4U) /**< HPRE field mask. */
111#define STM32_HPRE_FIELD(n) ((n) << 4U) /**< HPRE field value. */
112#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
113#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
114#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
115#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
116#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
117#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
118#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
119#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
120#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
121
122#define STM32_PPRE1_MASK (7U << 8U) /**< PPRE1 field mask. */
123#define STM32_PPRE1_FIELD(n) ((n) << 8U) /**< PPRE1 field value. */
124#define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U)
125#define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U)
126#define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U)
127#define STM32_PPRE1_DIV8 STM32_PPRE1_FIELD(6U)
128#define STM32_PPRE1_DIV16 STM32_PPRE1_FIELD(7U)
129
130#define STM32_PPRE2_MASK (7U << 11U) /**< PPRE2 field mask. */
131#define STM32_PPRE2_FIELD(n) ((n) << 11U) /**< PPRE2 field value. */
132#define STM32_PPRE2_DIV1 STM32_PPRE2_FIELD(0U)
133#define STM32_PPRE2_DIV2 STM32_PPRE2_FIELD(4U)
134#define STM32_PPRE2_DIV4 STM32_PPRE2_FIELD(5U)
135#define STM32_PPRE2_DIV8 STM32_PPRE2_FIELD(6U)
136#define STM32_PPRE2_DIV16 STM32_PPRE2_FIELD(7U)
137
138#define STM32_MCOSEL_MASK (15U << 24U)/**< MCOSEL field mask. */
139#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
140#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
141#define STM32_MCOSEL_HSI16 (3U << 24U) /**< HSI16 clock on MCO pin. */
142#define STM32_MCOSEL_HSE (4U << 24U) /**< HSE clock on MCO pin. */
143#define STM32_MCOSEL_PLLRCLK (5U << 24U) /**< PLLR clock on MCO pin. */
144#define STM32_MCOSEL_LSI (6U << 24U) /**< LSI clock on MCO pin. */
145#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
146#define STM32_MCOSEL_HSI48 (8U << 24U) /**< HSI48 clock on MCO pin. */
147
148#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
149#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
150#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U)
151#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U)
152#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U)
153#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U)
154#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U)
155/** @} */
156
157/**
158 * @name RCC_PLLCFGR register bits definitions
159 * @{
160 */
161#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
162#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
163#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
164#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
165/** @} */
166
167/**
168 * @name RCC_CCIPR register bits definitions
169 * @{
170 */
171#define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */
172#define STM32_USART1SEL_PCLK2 (0U << 0U) /**< USART1 source is PCLK2. */
173#define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */
174#define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */
175#define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */
176
177#define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */
178#define STM32_USART2SEL_PCLK1 (0U << 2U) /**< USART2 source is PCLK1. */
179#define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */
180#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
181#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
182
183#define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */
184#define STM32_USART3SEL_PCLK1 (0U << 4U) /**< USART3 source is PCLK1. */
185#define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */
186#define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */
187#define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */
188
189#define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */
190#define STM32_UART4SEL_PCLK1 (0U << 6U) /**< UART4 source is PCLK1. */
191#define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */
192#define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */
193#define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */
194
195#define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */
196#define STM32_UART5SEL_PCLK1 (0U << 8U) /**< UART5 source is PCLK1. */
197#define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */
198#define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */
199#define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */
200
201#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
202#define STM32_LPUART1SEL_PCLK1 (0U << 10U) /**< LPUART1 source is PCLK1. */
203#define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */
204#define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */
205#define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */
206
207#define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */
208#define STM32_I2C1SEL_PCLK1 (0U << 12U) /**< I2C1 source is PCLK1. */
209#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
210#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
211
212#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */
213#define STM32_I2C2SEL_PCLK1 (0U << 14U) /**< I2C2 source is PCLK1. */
214#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */
215#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */
216
217#define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */
218#define STM32_I2C3SEL_PCLK1 (0U << 16U) /**< I2C3 source is PCLK1. */
219#define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */
220#define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */
221
222#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
223#define STM32_LPTIM1SEL_PCLK1 (0U << 18U) /**< LPTIM1 source is PCLK1. */
224#define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */
225#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
226#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
227
228#define STM32_SAI1SEL_MASK (3U << 20U) /**< SAI1SEL mask. */
229#define STM32_SAI1SEL_SYSCLK (0U << 20U) /**< SAI1 source is SYSCLK. */
230#define STM32_SAI1SEL_PLLQCLK (1U << 20U) /**< SAI1 source is PLLQCLK. */
231#define STM32_SAI1SEL_CKIN (2U << 20U) /**< SAI1 source is CKIN. */
232#define STM32_SAI1SEL_HSI16 (3U << 20U) /**< SAI1 source is HSI16. */
233
234#define STM32_I2S23SEL_MASK (3U << 22U) /**< I2S23SEL mask. */
235#define STM32_I2S23SEL_SYSCLK (0U << 22U) /**< I2S23 source is SYSCLK. */
236#define STM32_I2S23SEL_PLLQCLK (1U << 22U) /**< I2S23 source is PLLQCLK. */
237#define STM32_I2S23SEL_CKIN (2U << 22U) /**< I2S23 source is CKIN. */
238#define STM32_I2S23SEL_HSI16 (3U << 22U) /**< I2S23 source is HSI16. */
239
240#define STM32_FDCANSEL_MASK (3U << 24U) /**< FDCANSEL mask. */
241#define STM32_FDCANSEL_HSE (0U << 24U) /**< FDCAN source is HSE. */
242#define STM32_FDCANSEL_PLLQCLK (1U << 24U) /**< FDCAN source is PLLQCLK. */
243#define STM32_FDCANSEL_PCLK1 (2U << 24U) /**< FDCAN source is PCLK1. */
244
245#define STM32_CLK48SEL_MASK (3U << 26U) /**< CLK48SEL mask. */
246#define STM32_CLK48SEL_HSI48 (0U << 26U) /**< CLK48 source is HSI48. */
247#define STM32_CLK48SEL_PLLQCLK (2U << 26U) /**< CLK48 source is PLLQCLK. */
248
249#define STM32_ADC12SEL_MASK (3U << 28U) /**< ADC12SEL mask. */
250#define STM32_ADC12SEL_NOCLK (0U << 28U) /**< ADC12 source is none. */
251#define STM32_ADC12SEL_PLLPCLK (1U << 28U) /**< ADC12 source is PLLPCLK. */
252#define STM32_ADC12SEL_SYSCLK (2U << 28U) /**< ADC12 source is SYSCLK. */
253
254#define STM32_ADC345SEL_MASK (3U << 30U) /**< ADC345SEL mask. */
255#define STM32_ADC345SEL_NOCLK (0U << 30U) /**< ADC345 source is none. */
256#define STM32_ADC345SEL_PLLPCLK (1U << 30U) /**< ADC345 source is PLLPCLK. */
257#define STM32_ADC345SEL_SYSCLK (2U << 30U) /**< ADC345 source is SYSCLK. */
258/** @} */
259
260/**
261 * @name RCC_CCIPR2 register bits definitions
262 * @{
263 */
264#define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */
265#define STM32_I2C4SEL_PCLK1 (0U << 0U) /**< I2C4 source is PCLK1. */
266#define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */
267#define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */
268
269#define STM32_QSPISEL_MASK (3U << 20U) /**< QSPISEL mask. */
270#define STM32_QSPISEL_SYSCLK (0U << 20U) /**< QSPI source is SYSCLK. */
271#define STM32_QSPISEL_HSI16 (1U << 20U) /**< QSPI source is HSI16. */
272#define STM32_QSPISEL_PLLQCLK (2U << 20U) /**< QSPI source is PLLQCLK. */
273/** @} */
274
275/**
276 * @name RCC_BDCR register bits definitions
277 * @{
278 */
279#define STM32_RTCSEL_MASK (3U << 8U) /**< RTC source mask. */
280#define STM32_RTCSEL_NOCLOCK (0U << 8U) /**< No RTC source. */
281#define STM32_RTCSEL_LSE (1U << 8U) /**< RTC source is LSE. */
282#define STM32_RTCSEL_LSI (2U << 8U) /**< RTC source is LSI. */
283#define STM32_RTCSEL_HSEDIV (3U << 8U) /**< RTC source is HSE divided. */
284
285#define STM32_LSCOSEL_MASK (3U << 24U) /**< LSCO pin clock source. */
286#define STM32_LSCOSEL_NOCLOCK (0U << 24U) /**< No clock on LSCO pin. */
287#define STM32_LSCOSEL_LSI (1U << 24U) /**< LSI on LSCO pin. */
288#define STM32_LSCOSEL_LSE (3U << 24U) /**< LSE on LSCO pin. */
289/** @} */
290
291/*===========================================================================*/
292/* Driver pre-compile time settings. */
293/*===========================================================================*/
294
295/**
296 * @name Configuration options
297 * @{
298 */
299/**
300 * @brief Disables the PWR/RCC initialization in the HAL.
301 */
302#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
303#define STM32_NO_INIT FALSE
304#endif
305
306/**
307 * @brief Core voltage selection.
308 * @note This setting affects all the performance and clock related
309 * settings, the maximum performance is only obtainable selecting
310 * the maximum voltage.
311 */
312#if !defined(STM32_VOS) || defined(__DOXYGEN__)
313#define STM32_VOS STM32_VOS_RANGE1
314#endif
315
316/**
317 * @brief Core voltage boost.
318 * @note The boost can only be used when STM32_VOS==STM32_VOS_RANGE1.
319 */
320#if !defined(STM32_PWR_BOOST) || defined(__DOXYGEN__)
321#define STM32_PWR_BOOST TRUE
322#endif
323
324/**
325 * @brief PWR CR2 register initialization value.
326 */
327#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__)
328#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
329#endif
330
331/**
332 * @brief PWR CR3 register initialization value.
333 */
334#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)
335#define STM32_PWR_CR3 (PWR_CR3_EIWF)
336#endif
337
338/**
339 * @brief PWR CR4 register initialization value.
340 */
341#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__)
342#define STM32_PWR_CR4 (0U)
343#endif
344
345/**
346 * @brief PWR PUCRA register initialization value.
347 */
348#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__)
349#define STM32_PWR_PUCRA (0U)
350#endif
351
352/**
353 * @brief PWR PDCRA register initialization value.
354 */
355#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__)
356#define STM32_PWR_PDCRA (0U)
357#endif
358
359/**
360 * @brief PWR PUCRB register initialization value.
361 */
362#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__)
363#define STM32_PWR_PUCRB (0U)
364#endif
365
366/**
367 * @brief PWR PDCRB register initialization value.
368 */
369#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__)
370#define STM32_PWR_PDCRB (0U)
371#endif
372
373/**
374 * @brief PWR PUCRC register initialization value.
375 */
376#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__)
377#define STM32_PWR_PUCRC (0U)
378#endif
379
380/**
381 * @brief PWR PDCRC register initialization value.
382 */
383#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__)
384#define STM32_PWR_PDCRC (0U)
385#endif
386
387/**
388 * @brief PWR PUCRD register initialization value.
389 */
390#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__)
391#define STM32_PWR_PUCRD (0U)
392#endif
393
394/**
395 * @brief PWR PDCRD register initialization value.
396 */
397#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__)
398#define STM32_PWR_PDCRD (0U)
399#endif
400
401/**
402 * @brief PWR PUCRE register initialization value.
403 */
404#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__)
405#define STM32_PWR_PUCRE (0U)
406#endif
407
408/**
409 * @brief PWR PDCRE register initialization value.
410 */
411#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__)
412#define STM32_PWR_PDCRE (0U)
413#endif
414
415/**
416 * @brief PWR PUCRF register initialization value.
417 */
418#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__)
419#define STM32_PWR_PUCRF (0U)
420#endif
421
422/**
423 * @brief PWR PDCRF register initialization value.
424 */
425#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__)
426#define STM32_PWR_PDCRF (0U)
427#endif
428
429/**
430 * @brief PWR PUCRG register initialization value.
431 */
432#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__)
433#define STM32_PWR_PUCRG (0U)
434#endif
435
436/**
437 * @brief PWR PDCRG register initialization value.
438 */
439#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__)
440#define STM32_PWR_PDCRG (0U)
441#endif
442
443/**
444 * @brief Enables or disables the HSI16 clock source.
445 */
446#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
447#define STM32_HSI16_ENABLED FALSE
448#endif
449
450/**
451 * @brief Enables or disables the HSI48 clock source.
452 */
453#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
454#define STM32_HSI48_ENABLED FALSE
455#endif
456
457/**
458 * @brief Enables or disables the HSE clock source.
459 */
460#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
461#define STM32_HSE_ENABLED FALSE
462#endif
463
464/**
465 * @brief Enables or disables the LSI clock source.
466 */
467#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
468#define STM32_LSI_ENABLED FALSE
469#endif
470
471/**
472 * @brief Enables or disables the LSE clock source.
473 */
474#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
475#define STM32_LSE_ENABLED FALSE
476#endif
477
478/**
479 * @brief Main clock source selection.
480 * @note If the selected clock source is not the PLL then the PLL is not
481 * initialized and started.
482 * @note The default value is calculated for a 170MHz system clock from
483 * the internal 16MHz HSI clock.
484 */
485#if !defined(STM32_SW) || defined(__DOXYGEN__)
486#define STM32_SW STM32_SW_PLLRCLK
487#endif
488
489/**
490 * @brief Clock source for the PLL.
491 * @note This setting has only effect if the PLL is selected as the
492 * system clock source.
493 * @note The default value is calculated for a 170MHz system clock from
494 * the internal 16MHz HSI clock.
495 */
496#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
497#define STM32_PLLSRC STM32_PLLSRC_HSI16
498#endif
499
500/**
501 * @brief PLLM divider value.
502 * @note The allowed values are 1..16.
503 * @note The default value is calculated for a 170MHz system clock from
504 * the internal 16MHz HSI clock.
505 */
506#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
507#define STM32_PLLM_VALUE 4
508#endif
509
510/**
511 * @brief PLLN multiplier value.
512 * @note The allowed values are 8..127.
513 * @note The default value is calculated for a 170MHz system clock from
514 * the internal 16MHz HSI clock.
515 */
516#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
517#define STM32_PLLN_VALUE 84
518#endif
519
520/**
521 * @brief PLLPDIV divider value or zero if disabled.
522 * @note The allowed values are 0, 2..31.
523 */
524#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
525#define STM32_PLLPDIV_VALUE 0
526#endif
527
528/**
529 * @brief PLLP divider value.
530 * @note The allowed values are 7, 17.
531 */
532#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
533#define STM32_PLLP_VALUE 7
534#endif
535
536/**
537 * @brief PLLQ divider value.
538 * @note The allowed values are 2, 4, 6, 8.
539 */
540#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
541#define STM32_PLLQ_VALUE 8
542#endif
543
544/**
545 * @brief PLLR divider value.
546 * @note The allowed values are 2, 4, 6, 8.
547 * @note The default value is calculated for a 170MHz system clock from
548 * the internal 16MHz HSI clock.
549 */
550#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
551#define STM32_PLLR_VALUE 2
552#endif
553
554/**
555 * @brief AHB prescaler value.
556 * @note The default value is calculated for a 170MHz system clock from
557 * the internal 16MHz HSI clock.
558 */
559#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
560#define STM32_HPRE STM32_HPRE_DIV1
561#endif
562
563/**
564 * @brief APB1 prescaler value.
565 */
566#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
567#define STM32_PPRE1 STM32_PPRE1_DIV2
568#endif
569
570/**
571 * @brief APB2 prescaler value.
572 */
573#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
574#define STM32_PPRE2 STM32_PPRE2_DIV1
575#endif
576
577/**
578 * @brief MCO clock source.
579 */
580#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
581#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
582#endif
583
584/**
585 * @brief MCO divider setting.
586 */
587#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
588#define STM32_MCOPRE STM32_MCOPRE_DIV1
589#endif
590
591/**
592 * @brief LSCO clock source.
593 */
594#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
595#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
596#endif
597
598/**
599 * @brief USART1 clock source.
600 */
601#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
602#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
603#endif
604
605/**
606 * @brief USART2 clock source.
607 */
608#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
609#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
610#endif
611
612/**
613 * @brief USART3 clock source.
614 */
615#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
616#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
617#endif
618
619/**
620 * @brief UART4 clock source.
621 */
622#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
623#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
624#endif
625
626/**
627 * @brief UART5 clock source.
628 */
629#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
630#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
631#endif
632
633/**
634 * @brief LPUART1 clock source.
635 */
636#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
637#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
638#endif
639
640/**
641 * @brief I2C1 clock source.
642 */
643#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
644#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
645#endif
646
647/**
648 * @brief I2C2 clock source.
649 */
650#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
651#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
652#endif
653
654/**
655 * @brief I2C3 clock source.
656 */
657#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
658#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
659#endif
660
661/**
662 * @brief I2C4 clock source.
663 */
664#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
665#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
666#endif
667
668/**
669 * @brief LPTIM1 clock source.
670 */
671#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
672#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
673#endif
674
675/**
676 * @brief SAI1 clock source.
677 */
678#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
679#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
680#endif
681
682/**
683 * @brief I2S23 clock source.
684 */
685#if !defined(STM32_I2S23SEL) || defined(__DOXYGEN__)
686#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
687#endif
688
689/**
690 * @brief FDCAN clock source.
691 */
692#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
693#define STM32_FDCANSEL STM32_FDCANSEL_HSE
694#endif
695
696/**
697 * @brief CLK48 clock source.
698 */
699#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
700#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
701#endif
702
703/**
704 * @brief ADC12 clock source.
705 */
706#if !defined(STM32_ADC12SEL) || defined(__DOXYGEN__)
707#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
708#endif
709
710/**
711 * @brief ADC34 clock source.
712 */
713#if !defined(STM32_ADC345SEL) || defined(__DOXYGEN__)
714#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
715#endif
716
717/**
718 * @brief QSPI clock source.
719 */
720#if !defined(STM32_QSPISEL) || defined(__DOXYGEN__)
721#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
722#endif
723
724/**
725 * @brief RTC clock source.
726 */
727#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
728#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
729#endif
730/** @} */
731
732/*===========================================================================*/
733/* Derived constants and error checks. */
734/*===========================================================================*/
735
736/* Boost mode checks.*/
737#if STM32_PWR_BOOST && (STM32_VOS != STM32_VOS_RANGE1)
738#error "STM32_PWR_BOOST requires STM32_VOS_RANGE1"
739#endif
740
741/*
742 * Configuration-related checks.
743 */
744#if !defined(STM32G4xx_MCUCONF)
745#error "Using a wrong mcuconf.h file, STM32G4xx_MCUCONF not defined"
746#endif
747
748#if defined(STM32G431xx) && !defined(STM32G431_MCUCONF)
749#error "Using a wrong mcuconf.h file, STM32G431_MCUCONF not defined"
750
751#elif defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
752#error "Using a wrong mcuconf.h file, STM32G441_MCUCONF not defined"
753
754#elif defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
755#error "Using a wrong mcuconf.h file, STM32G471_MCUCONF not defined"
756
757#elif defined(STM32G473xx) && !defined(STM32G473_MCUCONF)
758#error "Using a wrong mcuconf.h file, STM32G473_MCUCONF not defined"
759
760#elif defined(STM32G483xx) && !defined(STM32G473_MCUCONF)
761#error "Using a wrong mcuconf.h file, STM32G483_MCUCONF not defined"
762
763#elif defined(STM32G474xx) && !defined(STM32G474_MCUCONF)
764#error "Using a wrong mcuconf.h file, STM32G474_MCUCONF not defined"
765
766#elif defined(STM32G484xx) && !defined(STM32G484_MCUCONF)
767#error "Using a wrong mcuconf.h file, STM32G484_MCUCONF not defined"
768
769#elif defined(STM32GBK1CB) && !defined(STM32GBK1CB_MCUCONF)
770#error "Using a wrong mcuconf.h file, STM32GBK1CB_MCUCONF not defined"
771
772#endif
773
774/*
775 * Board files sanity checks.
776 */
777#if !defined(STM32_LSECLK)
778#error "STM32_LSECLK not defined in board.h"
779#endif
780
781#if !defined(STM32_LSEDRV)
782#error "STM32_LSEDRV not defined in board.h"
783#endif
784
785#if !defined(STM32_HSECLK)
786#error "STM32_HSECLK not defined in board.h"
787#endif
788
789/**
790 * @name System Limits for VOS range 1 with boost
791 * @{
792 */
793#define STM32_BOOST_SYSCLK_MAX 170000000
794#define STM32_BOOST_HSECLK_MAX 48000000
795#define STM32_BOOST_HSECLK_BYP_MAX 48000000
796#define STM32_BOOST_HSECLK_MIN 8000000
797#define STM32_BOOST_HSECLK_BYP_MIN 8000000
798#define STM32_BOOST_LSECLK_MAX 32768
799#define STM32_BOOST_LSECLK_BYP_MAX 1000000
800#define STM32_BOOST_LSECLK_MIN 32768
801#define STM32_BOOST_LSECLK_BYP_MIN 32768
802#define STM32_BOOST_PLLIN_MAX 16000000
803#define STM32_BOOST_PLLIN_MIN 2660000
804#define STM32_BOOST_PLLVCO_MAX 344000000
805#define STM32_BOOST_PLLVCO_MIN 96000000
806#define STM32_BOOST_PLLP_MAX 170000000
807#define STM32_BOOST_PLLP_MIN 2064500
808#define STM32_BOOST_PLLQ_MAX 170000000
809#define STM32_BOOST_PLLQ_MIN 8000000
810#define STM32_BOOST_PLLR_MAX 170000000
811#define STM32_BOOST_PLLR_MIN 8000000
812#define STM32_BOOST_PCLK1_MAX 170000000
813#define STM32_BOOST_PCLK2_MAX 170000000
814#define STM32_BOOST_ADCCLK_MAX 60000000
815
816#define STM32_BOOST_0WS_THRESHOLD 34000000
817#define STM32_BOOST_1WS_THRESHOLD 68000000
818#define STM32_BOOST_2WS_THRESHOLD 102000000
819#define STM32_BOOST_3WS_THRESHOLD 136000000
820#define STM32_BOOST_4WS_THRESHOLD 170000000
821/** @} */
822
823/**
824 * @name System Limits for VOS range 1 without boost
825 * @{
826 */
827#define STM32_VOS1_SYSCLK_MAX 150000000
828#define STM32_VOS1_HSECLK_MAX 48000000
829#define STM32_VOS1_HSECLK_BYP_MAX 48000000
830#define STM32_VOS1_HSECLK_MIN 8000000
831#define STM32_VOS1_HSECLK_BYP_MIN 8000000
832#define STM32_VOS1_LSECLK_MAX 32768
833#define STM32_VOS1_LSECLK_BYP_MAX 1000000
834#define STM32_VOS1_LSECLK_MIN 32768
835#define STM32_VOS1_LSECLK_BYP_MIN 32768
836#define STM32_VOS1_PLLIN_MAX 16000000
837#define STM32_VOS1_PLLIN_MIN 2660000
838#define STM32_VOS1_PLLVCO_MAX 344000000
839#define STM32_VOS1_PLLVCO_MIN 96000000
840#define STM32_VOS1_PLLP_MAX 150000000
841#define STM32_VOS1_PLLP_MIN 2064500
842#define STM32_VOS1_PLLQ_MAX 150000000
843#define STM32_VOS1_PLLQ_MIN 8000000
844#define STM32_VOS1_PLLR_MAX 150000000
845#define STM32_VOS1_PLLR_MIN 8000000
846#define STM32_VOS1_PCLK1_MAX 150000000
847#define STM32_VOS1_PCLK2_MAX 150000000
848#define STM32_VOS1_ADCCLK_MAX 60000000
849
850#define STM32_VOS1_0WS_THRESHOLD 30000000
851#define STM32_VOS1_1WS_THRESHOLD 60000000
852#define STM32_VOS1_2WS_THRESHOLD 90000000
853#define STM32_VOS1_3WS_THRESHOLD 120000000
854#define STM32_VOS1_4WS_THRESHOLD 150000000
855/** @} */
856
857/**
858 * @name System Limits for VOS range 2
859 * @{
860 */
861#define STM32_VOS2_SYSCLK_MAX 26000000
862#define STM32_VOS2_HSECLK_MAX 26000000
863#define STM32_VOS2_HSECLK_BYP_MAX 26000000
864#define STM32_VOS2_HSECLK_MIN 8000000
865#define STM32_VOS2_HSECLK_BYP_MIN 8000000
866#define STM32_VOS2_LSECLK_MAX 32768
867#define STM32_VOS2_LSECLK_BYP_MAX 1000000
868#define STM32_VOS2_LSECLK_MIN 32768
869#define STM32_VOS2_LSECLK_BYP_MIN 32768
870#define STM32_VOS2_PLLIN_MAX 16000000
871#define STM32_VOS2_PLLIN_MIN 2660000
872#define STM32_VOS2_PLLVCO_MAX 128000000
873#define STM32_VOS2_PLLVCO_MIN 96000000
874#define STM32_VOS2_PLLP_MAX 26000000
875#define STM32_VOS2_PLLP_MIN 2064500
876#define STM32_VOS2_PLLQ_MAX 26000000
877#define STM32_VOS2_PLLQ_MIN 8000000
878#define STM32_VOS2_PLLR_MAX 26000000
879#define STM32_VOS2_PLLR_MIN 8000000
880#define STM32_VOS2_PCLK1_MAX 26000000
881#define STM32_VOS2_PCLK2_MAX 26000000
882#define STM32_VOS2_ADCCLK_MAX 26000000
883
884#define STM32_VOS2_0WS_THRESHOLD 12000000
885#define STM32_VOS2_1WS_THRESHOLD 24000000
886#define STM32_VOS2_2WS_THRESHOLD 26000000
887#define STM32_VOS2_3WS_THRESHOLD 0
888#define STM32_VOS2_4WS_THRESHOLD 0
889/** @} */
890
891/* Voltage related limits.*/
892#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
893#if STM32_PWR_BOOST || defined(__DOXYGEN__)
894#define STM32_SYSCLK_MAX STM32_BOOST_SYSCLK_MAX
895#define STM32_HSECLK_MAX STM32_BOOST_HSECLK_MAX
896#define STM32_HSECLK_BYP_MAX STM32_BOOST_HSECLK_BYP_MAX
897#define STM32_HSECLK_MIN STM32_BOOST_HSECLK_MIN
898#define STM32_HSECLK_BYP_MIN STM32_BOOST_HSECLK_BYP_MIN
899#define STM32_LSECLK_MAX STM32_BOOST_LSECLK_MAX
900#define STM32_LSECLK_BYP_MAX STM32_BOOST_LSECLK_BYP_MAX
901#define STM32_LSECLK_MIN STM32_BOOST_LSECLK_MIN
902#define STM32_LSECLK_BYP_MIN STM32_BOOST_LSECLK_BYP_MIN
903#define STM32_PLLIN_MAX STM32_BOOST_PLLIN_MAX
904#define STM32_PLLIN_MIN STM32_BOOST_PLLIN_MIN
905#define STM32_PLLVCO_MAX STM32_BOOST_PLLVCO_MAX
906#define STM32_PLLVCO_MIN STM32_BOOST_PLLVCO_MIN
907#define STM32_PLLP_MAX STM32_BOOST_PLLP_MAX
908#define STM32_PLLP_MIN STM32_BOOST_PLLP_MIN
909#define STM32_PLLQ_MAX STM32_BOOST_PLLQ_MAX
910#define STM32_PLLQ_MIN STM32_BOOST_PLLQ_MIN
911#define STM32_PLLR_MAX STM32_BOOST_PLLR_MAX
912#define STM32_PLLR_MIN STM32_BOOST_PLLR_MIN
913#define STM32_PCLK1_MAX STM32_BOOST_PCLK1_MAX
914#define STM32_PCLK2_MAX STM32_BOOST_PCLK2_MAX
915#define STM32_ADCCLK_MAX STM32_BOOST_ADCCLK_MAX
916
917#define STM32_0WS_THRESHOLD STM32_BOOST_0WS_THRESHOLD
918#define STM32_1WS_THRESHOLD STM32_BOOST_1WS_THRESHOLD
919#define STM32_2WS_THRESHOLD STM32_BOOST_2WS_THRESHOLD
920#define STM32_3WS_THRESHOLD STM32_BOOST_3WS_THRESHOLD
921#define STM32_4WS_THRESHOLD STM32_BOOST_4WS_THRESHOLD
922#define STM32_5WS_THRESHOLD STM32_BOOST_5WS_THRESHOLD
923#define STM32_6WS_THRESHOLD STM32_BOOST_6WS_THRESHOLD
924#define STM32_7WS_THRESHOLD STM32_BOOST_7WS_THRESHOLD
925#define STM32_8WS_THRESHOLD STM32_BOOST_8WS_THRESHOLD
926
927#else /* !STM32_PWR_BOOST */
928#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX_NOBOOST
929#define STM32_HSECLK_MAX STM32_VOS1_HSECLK_MAX
930#define STM32_HSECLK_BYP_MAX STM32_VOS1_HSECLK_BYP_MAX
931#define STM32_HSECLK_MIN STM32_VOS1_HSECLK_MIN
932#define STM32_HSECLK_BYP_MIN STM32_VOS1_HSECLK_BYP_MIN
933#define STM32_LSECLK_MAX STM32_VOS1_LSECLK_MAX
934#define STM32_LSECLK_BYP_MAX STM32_VOS1_LSECLK_BYP_MAX
935#define STM32_LSECLK_MIN STM32_VOS1_LSECLK_MIN
936#define STM32_LSECLK_BYP_MIN STM32_VOS1_LSECLK_BYP_MIN
937#define STM32_PLLIN_MAX STM32_VOS1_PLLIN_MAX
938#define STM32_PLLIN_MIN STM32_VOS1_PLLIN_MIN
939#define STM32_PLLVCO_MAX STM32_VOS1_PLLVCO_MAX
940#define STM32_PLLVCO_MIN STM32_VOS1_PLLVCO_MIN
941#define STM32_PLLP_MAX STM32_VOS1_PLLP_MAX
942#define STM32_PLLP_MIN STM32_VOS1_PLLP_MIN
943#define STM32_PLLQ_MAX STM32_VOS1_PLLQ_MAX
944#define STM32_PLLQ_MIN STM32_VOS1_PLLQ_MIN
945#define STM32_PLLR_MAX STM32_VOS1_PLLR_MAX
946#define STM32_PLLR_MIN STM32_VOS1_PLLR_MIN
947#define STM32_PCLK1_MAX STM32_VOS1_PCLK1_MAX
948#define STM32_PCLK2_MAX STM32_VOS1_PCLK2_MAX
949#define STM32_ADCCLK_MAX STM32_VOS1_ADCCLK_MAX
950
951#define STM32_0WS_THRESHOLD STM32_VOS1_0WS_THRESHOLD
952#define STM32_1WS_THRESHOLD STM32_VOS1_1WS_THRESHOLD
953#define STM32_2WS_THRESHOLD STM32_VOS1_2WS_THRESHOLD
954#define STM32_3WS_THRESHOLD STM32_VOS1_3WS_THRESHOLD
955#define STM32_4WS_THRESHOLD STM32_VOS1_4WS_THRESHOLD
956#define STM32_5WS_THRESHOLD STM32_VOS1_5WS_THRESHOLD
957#define STM32_6WS_THRESHOLD STM32_VOS1_6WS_THRESHOLD
958#define STM32_7WS_THRESHOLD STM32_VOS1_7WS_THRESHOLD
959#define STM32_8WS_THRESHOLD STM32_VOS1_8WS_THRESHOLD
960#endif /* !STM32_PWR_BOOST */
961
962#elif STM32_VOS == STM32_VOS_RANGE2
963#define STM32_SYSCLK_MAX STM32_VOS2_SYSCLK_MAX
964#define STM32_SYSCLK_MAX_NOBOOST STM32_VOS2_SYSCLK_MAX_NOBOOST
965#define STM32_HSECLK_MAX STM32_VOS2_HSECLK_MAX
966#define STM32_HSECLK_BYP_MAX STM32_VOS2_HSECLK_BYP_MAX
967#define STM32_HSECLK_MIN STM32_VOS2_HSECLK_MIN
968#define STM32_HSECLK_BYP_MIN STM32_VOS2_HSECLK_BYP_MIN
969#define STM32_LSECLK_MAX STM32_VOS2_LSECLK_MAX
970#define STM32_LSECLK_BYP_MAX STM32_VOS2_LSECLK_BYP_MAX
971#define STM32_LSECLK_MIN STM32_VOS2_LSECLK_MIN
972#define STM32_LSECLK_BYP_MIN STM32_VOS2_LSECLK_BYP_MIN
973#define STM32_PLLIN_MAX STM32_VOS2_PLLIN_MAX
974#define STM32_PLLIN_MIN STM32_VOS2_PLLIN_MIN
975#define STM32_PLLVCO_MAX STM32_VOS2_PLLVCO_MAX
976#define STM32_PLLVCO_MIN STM32_VOS2_PLLVCO_MIN
977#define STM32_PLLP_MAX STM32_VOS2_PLLP_MAX
978#define STM32_PLLP_MIN STM32_VOS2_PLLP_MIN
979#define STM32_PLLQ_MAX STM32_VOS2_PLLQ_MAX
980#define STM32_PLLQ_MIN STM32_VOS2_PLLQ_MIN
981#define STM32_PLLR_MAX STM32_VOS2_PLLR_MAX
982#define STM32_PLLR_MIN STM32_VOS2_PLLR_MIN
983#define STM32_PCLK1_MAX STM32_VOS2_PCLK1_MAX
984#define STM32_PCLK2_MAX STM32_VOS2_PCLK2_MAX
985#define STM32_ADCCLK_MAX STM32_VOS2_ADCCLK_MAX
986
987#define STM32_0WS_THRESHOLD STM32_VOS2_0WS_THRESHOLD
988#define STM32_1WS_THRESHOLD STM32_VOS2_1WS_THRESHOLD
989#define STM32_2WS_THRESHOLD STM32_VOS2_2WS_THRESHOLD
990#define STM32_3WS_THRESHOLD STM32_VOS2_3WS_THRESHOLD
991#define STM32_4WS_THRESHOLD STM32_VOS2_4WS_THRESHOLD
992#define STM32_5WS_THRESHOLD STM32_VOS2_5WS_THRESHOLD
993#define STM32_6WS_THRESHOLD STM32_VOS2_6WS_THRESHOLD
994#define STM32_7WS_THRESHOLD STM32_VOS2_7WS_THRESHOLD
995#define STM32_8WS_THRESHOLD STM32_VOS2_8WS_THRESHOLD
996
997#else
998#error "invalid STM32_VOS value specified"
999#endif
1000
1001/*
1002 * HSI16 related checks.
1003 */
1004#if STM32_HSI16_ENABLED
1005#else /* !STM32_HSI16_ENABLED */
1006
1007 #if STM32_SW == STM32_SW_HSI16
1008 #error "HSI16 not enabled, required by STM32_SW"
1009 #endif
1010
1011 #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
1012 #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
1013 #endif
1014
1015 #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
1016 ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
1017 (STM32_PLLSRC == STM32_PLLSRC_HSI16))
1018 #error "HSI16 not enabled, required by STM32_MCOSEL"
1019 #endif
1020
1021 #if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
1022 #error "HSI16 not enabled, required by STM32_USART1SEL"
1023 #endif
1024 #if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
1025 #error "HSI16 not enabled, required by STM32_USART2SEL"
1026 #endif
1027 #if (STM32_USART3SEL == STM32_USART3SEL_HSI16)
1028 #error "HSI16 not enabled, required by STM32_USART3SEL"
1029 #endif
1030 #if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
1031 #error "HSI16 not enabled, required by STM32_UART4SEL_HSI16"
1032 #endif
1033 #if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
1034 #error "HSI16 not enabled, required by STM32_UART5SEL_HSI16"
1035 #endif
1036 #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
1037 #error "HSI16 not enabled, required by STM32_LPUART1SEL"
1038 #endif
1039
1040 #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
1041 #error "HSI16 not enabled, required by STM32_I2C1SEL"
1042 #endif
1043 #if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16)
1044 #error "HSI16 not enabled, required by STM32_I2C2SEL"
1045 #endif
1046 #if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
1047 #error "HSI16 not enabled, required by STM32_I2C3SEL"
1048 #endif
1049 #if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
1050 #error "HSI16 not enabled, required by STM32_I2C4SEL"
1051 #endif
1052
1053 #if (STM32_SAI1SEL == STM32_SAI1SEL_HSI16)
1054 #error "HSI16 not enabled, required by STM32_SAI1SEL"
1055 #endif
1056 #if (STM32_I2S23SEL == STM32_I2S23SEL_HSI16)
1057 #error "HSI16 not enabled, required by STM32_I2S23SEL"
1058 #endif
1059
1060 #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
1061 #error "HSI16 not enabled, required by STM32_LPTIM1SEL"
1062 #endif
1063
1064 #if (STM32_QSPISEL == STM32_QSPISEL_HSI16)
1065 #error "HSI16 not enabled, required by STM32_QSPISEL_HSI16"
1066 #endif
1067
1068#endif /* !STM32_HSI16_ENABLED */
1069
1070/*
1071 * HSI48 related checks.
1072 */
1073#if STM32_HSI48_ENABLED
1074#else /* !STM32_HSI48_ENABLED */
1075
1076 #if STM32_MCOSEL == STM32_MCOSEL_HSI48
1077 #error "HSI48 not enabled, required by STM32_MCOSEL"
1078 #endif
1079
1080 #if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
1081 #error "HSI48 not enabled, required by STM32_CLK48SEL"
1082 #endif
1083
1084#endif /* !STM32_HSI48_ENABLED */
1085
1086/*
1087 * HSE related checks.
1088 */
1089#if STM32_HSE_ENABLED
1090
1091#else /* !STM32_HSE_ENABLED */
1092
1093 #if STM32_SW == STM32_SW_HSE
1094 #error "HSE not enabled, required by STM32_SW"
1095 #endif
1096
1097 #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
1098 #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
1099 #endif
1100
1101 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
1102 ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
1103 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1104 #error "HSE not enabled, required by STM32_MCOSEL"
1105 #endif
1106
1107 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1108 #error "HSE not enabled, required by STM32_RTCSEL"
1109 #endif
1110
1111#endif /* !STM32_HSE_ENABLED */
1112
1113/*
1114 * LSI related checks.
1115 */
1116#if STM32_LSI_ENABLED
1117#else /* !STM32_LSI_ENABLED */
1118
1119 #if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
1120 #error "LSI not enabled, required by STM32_RTCSEL"
1121 #endif
1122
1123 #if STM32_MCOSEL == STM32_MCOSEL_LSI
1124 #error "LSI not enabled, required by STM32_MCOSEL"
1125 #endif
1126
1127 #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
1128 #error "LSI not enabled, required by STM32_LSCOSEL"
1129 #endif
1130
1131#endif /* !STM32_LSI_ENABLED */
1132
1133/*
1134 * LSE related checks.
1135 */
1136#if STM32_LSE_ENABLED
1137
1138 #if (STM32_LSECLK == 0)
1139 #error "LSE frequency not defined"
1140 #endif
1141
1142 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
1143 #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
1144 #endif
1145
1146#else /* !STM32_LSE_ENABLED */
1147
1148 #if STM32_RTCSEL == STM32_RTCSEL_LSE
1149 #error "LSE not enabled, required by STM32_RTCSEL"
1150 #endif
1151
1152 #if STM32_MCOSEL == STM32_MCOSEL_LSE
1153 #error "LSE not enabled, required by STM32_MCOSEL"
1154 #endif
1155
1156 #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
1157 #error "LSE not enabled, required by STM32_LSCOSEL"
1158 #endif
1159
1160#endif /* !STM32_LSE_ENABLED */
1161
1162/**
1163 * @brief STM32_PLLM field.
1164 */
1165#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
1166 defined(__DOXYGEN__)
1167 #define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
1168#else
1169 #error "invalid STM32_PLLM_VALUE value specified"
1170#endif
1171
1172/**
1173 * @brief PLL input clock frequency.
1174 */
1175#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1176 #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
1177
1178#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
1179 #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
1180
1181#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
1182 #define STM32_PLLCLKIN 0
1183
1184#else
1185 #error "invalid STM32_PLLSRC value specified"
1186#endif
1187
1188/*
1189 * PLL input frequency range check.
1190 */
1191#if (STM32_PLLCLKIN != 0) && \
1192 ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
1193 #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1194#endif
1195
1196/*
1197 * PLL enable check.
1198 */
1199#if (STM32_SW == STM32_SW_PLLRCLK) || \
1200 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
1201 (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
1202 (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
1203 (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
1204 (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
1205 (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
1206 (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
1207 (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
1208 defined(__DOXYGEN__)
1209
1210 #if STM32_PLLCLKIN == 0
1211 #error "PLL activation required but no PLL clock selected"
1212 #endif
1213
1214 /**
1215 * @brief PLL activation flag.
1216 */
1217 #define STM32_ACTIVATE_PLL TRUE
1218#else
1219
1220 #define STM32_ACTIVATE_PLL FALSE
1221#endif
1222
1223/**
1224 * @brief STM32_PLLN field.
1225 */
1226#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
1227 defined(__DOXYGEN__)
1228 #define STM32_PLLN (STM32_PLLN_VALUE << 8)
1229#else
1230 #error "invalid STM32_PLLN_VALUE value specified"
1231#endif
1232
1233/**
1234 * @brief STM32_PLLP field.
1235 */
1236#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
1237 #define STM32_PLLP (0 << 17)
1238
1239#elif STM32_PLLP_VALUE == 17
1240 #define STM32_PLLP (1 << 17)
1241
1242#else
1243 #error "invalid STM32_PLLP_VALUE value specified"
1244#endif
1245
1246/**
1247 * @brief STM32_PLLQ field.
1248 */
1249#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
1250 #define STM32_PLLQ (0 << 21)
1251
1252#elif STM32_PLLQ_VALUE == 4
1253 #define STM32_PLLQ (1 << 21)
1254
1255#elif STM32_PLLQ_VALUE == 6
1256 #define STM32_PLLQ (2 << 21)
1257
1258#elif STM32_PLLQ_VALUE == 8
1259 #define STM32_PLLQ (3 << 21)
1260
1261#else
1262 #error "invalid STM32_PLLQ_VALUE value specified"
1263#endif
1264
1265/**
1266 * @brief STM32_PLLR field.
1267 */
1268#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
1269 #define STM32_PLLR (0 << 25)
1270
1271#elif STM32_PLLR_VALUE == 4
1272 #define STM32_PLLR (1 << 25)
1273
1274#elif STM32_PLLR_VALUE == 6
1275 #define STM32_PLLR (2 << 25)
1276
1277#elif STM32_PLLR_VALUE == 8
1278 #define STM32_PLLR (3 << 25)
1279
1280#else
1281 #error "invalid STM32_PLLR_VALUE value specified"
1282#endif
1283
1284/**
1285 * @brief STM32_PLLPDIV field.
1286 */
1287#if (STM32_PLLPDIV_VALUE == 0) || \
1288 ((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
1289 defined(__DOXYGEN__)
1290#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
1291#else
1292#error "invalid STM32_PLLPDIV_VALUE value specified"
1293#endif
1294
1295/**
1296 * @brief STM32_PLLPEN field.
1297 */
1298#if (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
1299 (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
1300 defined(__DOXYGEN__)
1301 #define STM32_PLLPEN (1 << 16)
1302
1303#else
1304 #define STM32_PLLPEN (0 << 16)
1305#endif
1306
1307/**
1308 * @brief STM32_PLLQEN field.
1309 */
1310#if (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
1311 (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
1312 (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
1313 (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
1314 (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
1315 defined(__DOXYGEN__)
1316 #define STM32_PLLQEN (1 << 20)
1317
1318#else
1319 #define STM32_PLLQEN (0 << 20)
1320#endif
1321
1322/**
1323 * @brief STM32_PLLREN field.
1324 */
1325#if (STM32_SW == STM32_SW_PLLRCLK) || \
1326 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
1327 defined(__DOXYGEN__)
1328 #define STM32_PLLREN (1 << 24)
1329
1330#else
1331 #define STM32_PLLREN (0 << 24)
1332#endif
1333
1334/**
1335 * @brief PLL VCO frequency.
1336 */
1337#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1338
1339/*
1340 * PLL VCO frequency range check.
1341 */
1342#if STM32_ACTIVATE_PLL && \
1343 ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
1344 #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1345#endif
1346
1347/**
1348 * @brief PLL P output clock frequency.
1349 */
1350#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
1351 #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1352#else
1353 #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
1354#endif
1355
1356/**
1357 * @brief PLL Q output clock frequency.
1358 */
1359#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
1360
1361/**
1362 * @brief PLL R output clock frequency.
1363 */
1364#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
1365
1366/*
1367 * PLL-P output frequency range check.
1368 */
1369#if STM32_ACTIVATE_PLL && \
1370 ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
1371 #error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
1372#endif
1373
1374/*
1375 * PLL-Q output frequency range check.
1376 */
1377#if STM32_ACTIVATE_PLL && \
1378 ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
1379 #error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
1380#endif
1381
1382/*
1383 * PLL-R output frequency range check.
1384 */
1385#if STM32_ACTIVATE_PLL && \
1386 ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
1387 #error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
1388#endif
1389
1390/**
1391 * @brief System clock source.
1392 */
1393#if STM32_NO_INIT || defined(__DOXYGEN__)
1394 #define STM32_SYSCLK STM32_HSI16CLK
1395
1396#elif (STM32_SW == STM32_SW_HSI16)
1397 #define STM32_SYSCLK STM32_HSI16CLK
1398
1399#elif (STM32_SW == STM32_SW_HSE)
1400 #define STM32_SYSCLK STM32_HSECLK
1401
1402#elif (STM32_SW == STM32_SW_PLLRCLK)
1403 #define STM32_SYSCLK STM32_PLL_R_CLKOUT
1404
1405#else
1406 #error "invalid STM32_SW value specified"
1407#endif
1408
1409/*
1410 * Check on the system clock.
1411 */
1412#if STM32_SYSCLK > STM32_SYSCLK_MAX
1413 #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1414#endif
1415
1416/**
1417 * @brief AHB frequency.
1418 */
1419#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1420 #define STM32_HCLK (STM32_SYSCLK / 1)
1421
1422#elif STM32_HPRE == STM32_HPRE_DIV2
1423 #define STM32_HCLK (STM32_SYSCLK / 2)
1424
1425#elif STM32_HPRE == STM32_HPRE_DIV4
1426 #define STM32_HCLK (STM32_SYSCLK / 4)
1427
1428#elif STM32_HPRE == STM32_HPRE_DIV8
1429 #define STM32_HCLK (STM32_SYSCLK / 8)
1430
1431#elif STM32_HPRE == STM32_HPRE_DIV16
1432 #define STM32_HCLK (STM32_SYSCLK / 16)
1433
1434#elif STM32_HPRE == STM32_HPRE_DIV64
1435 #define STM32_HCLK (STM32_SYSCLK / 64)
1436
1437#elif STM32_HPRE == STM32_HPRE_DIV128
1438 #define STM32_HCLK (STM32_SYSCLK / 128)
1439
1440#elif STM32_HPRE == STM32_HPRE_DIV256
1441 #define STM32_HCLK (STM32_SYSCLK / 256)
1442
1443#elif STM32_HPRE == STM32_HPRE_DIV512
1444 #define STM32_HCLK (STM32_SYSCLK / 512)
1445
1446#else
1447 #error "invalid STM32_HPRE value specified"
1448#endif
1449
1450/*
1451 * AHB frequency check.
1452 */
1453#if STM32_HCLK > STM32_SYSCLK_MAX
1454 #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1455#endif
1456
1457/**
1458 * @brief APB1 frequency.
1459 */
1460#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1461 #define STM32_PCLK1 (STM32_HCLK / 1)
1462
1463#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1464 #define STM32_PCLK1 (STM32_HCLK / 2)
1465
1466#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1467 #define STM32_PCLK1 (STM32_HCLK / 4)
1468
1469#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1470 #define STM32_PCLK1 (STM32_HCLK / 8)
1471
1472#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1473 #define STM32_PCLK1 (STM32_HCLK / 16)
1474
1475#else
1476 #error "invalid STM32_PPRE1 value specified"
1477#endif
1478
1479/*
1480 * APB1 frequency check.
1481 */
1482#if STM32_PCLK1 > STM32_PCLK1_MAX
1483#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1484#endif
1485
1486/**
1487 * @brief APB2 frequency.
1488 */
1489#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1490 #define STM32_PCLK2 (STM32_HCLK / 1)
1491
1492#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1493 #define STM32_PCLK2 (STM32_HCLK / 2)
1494
1495#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1496 #define STM32_PCLK2 (STM32_HCLK / 4)
1497
1498#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1499 #define STM32_PCLK2 (STM32_HCLK / 8)
1500
1501#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1502 #define STM32_PCLK2 (STM32_HCLK / 16)
1503
1504#else
1505 #error "invalid STM32_PPRE2 value specified"
1506#endif
1507
1508/*
1509 * APB2 frequency check.
1510 */
1511#if STM32_PCLK2 > STM32_PCLK2_MAX
1512#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1513#endif
1514
1515/**
1516 * @brief MCO divider clock frequency.
1517 */
1518#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
1519 #define STM32_MCODIVCLK 0
1520
1521#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
1522 #define STM32_MCODIVCLK STM32_SYSCLK
1523
1524#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
1525 #define STM32_MCODIVCLK STM32_HSI16CLK
1526
1527#elif STM32_MCOSEL == STM32_MCOSEL_HSE
1528 #define STM32_MCODIVCLK STM32_HSECLK
1529
1530#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
1531 #define STM32_MCODIVCLK STM32_PLL_R_CLKOUT
1532
1533#elif STM32_MCOSEL == STM32_MCOSEL_LSI
1534 #define STM32_MCODIVCLK STM32_LSICLK
1535
1536#elif STM32_MCOSEL == STM32_MCOSEL_LSE
1537 #define STM32_MCODIVCLK STM32_LSECLK
1538
1539#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
1540 #define STM32_MCODIVCLK STM32_HSI48CLK
1541
1542#else
1543 #error "invalid STM32_MCOSEL value specified"
1544#endif
1545
1546/**
1547 * @brief MCO output pin clock frequency.
1548 */
1549#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
1550 #define STM32_MCOCLK STM32_MCODIVCLK
1551
1552#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
1553 #define STM32_MCOCLK (STM32_MCODIVCLK / 2)
1554
1555#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
1556 #define STM32_MCOCLK (STM32_MCODIVCLK / 4)
1557
1558#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
1559 #define STM32_MCOCLK (STM32_MCODIVCLK / 8)
1560
1561#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
1562 #define STM32_MCOCLK (STM32_MCODIVCLK / 16)
1563
1564#else
1565#error "invalid STM32_MCOPRE value specified"
1566#endif
1567
1568/**
1569 * @brief RTC clock frequency.
1570 */
1571#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
1572 #define STM32_RTCCLK 0
1573
1574#elif STM32_RTCSEL == STM32_RTCSEL_LSE
1575 #define STM32_RTCCLK STM32_LSECLK
1576
1577#elif STM32_RTCSEL == STM32_RTCSEL_LSI
1578 #define STM32_RTCCLK STM32_LSICLK
1579
1580#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1581 #define STM32_RTCCLK (STM32_HSECLK / 32)
1582
1583#else
1584 #error "invalid STM32_RTCSEL value specified"
1585#endif
1586
1587/**
1588 * @brief USART1 clock frequency.
1589 */
1590#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
1591 #define STM32_USART1CLK STM32_PCLK2
1592
1593#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
1594 #define STM32_USART1CLK STM32_SYSCLK
1595
1596#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
1597 #define STM32_USART1CLK STM32_HSI16CLK
1598
1599#elif STM32_USART1SEL == STM32_USART1SEL_LSE
1600 #define STM32_USART1CLK STM32_LSECLK
1601
1602#else
1603 #error "invalid source selected for USART1 clock"
1604#endif
1605
1606 /**
1607 * @brief USART2 clock frequency.
1608 */
1609 #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
1610 #define STM32_USART2CLK STM32_PCLK1
1611
1612 #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
1613 #define STM32_USART2CLK STM32_SYSCLK
1614
1615 #elif STM32_USART2SEL == STM32_USART2SEL_HSI16
1616 #define STM32_USART2CLK STM32_HSI16CLK
1617
1618 #elif STM32_USART2SEL == STM32_USART2SEL_LSE
1619 #define STM32_USART2CLK STM32_LSECLK
1620
1621 #else
1622 #error "invalid source selected for USART2 clock"
1623 #endif
1624
1625 /**
1626 * @brief USART3 clock frequency.
1627 */
1628 #if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
1629 #define STM32_USART3CLK STM32_PCLK1
1630
1631 #elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
1632 #define STM32_USART3CLK STM32_SYSCLK
1633
1634 #elif STM32_USART3SEL == STM32_USART3SEL_HSI16
1635 #define STM32_USART3CLK STM32_HSI16CLK
1636
1637 #elif STM32_USART3SEL == STM32_USART3SEL_LSE
1638 #define STM32_USART3CLK STM32_LSECLK
1639
1640 #else
1641 #error "invalid source selected for USART3 clock"
1642 #endif
1643
1644/**
1645 * @brief UART4 clock frequency.
1646 */
1647#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
1648 #define STM32_UART4CLK STM32_PCLK1
1649
1650#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
1651 #define STM32_UART4CLK STM32_SYSCLK
1652
1653#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
1654 #define STM32_UART4CLK STM32_HSI16CLK
1655
1656#elif STM32_UART4SEL == STM32_UART4SEL_LSE
1657 #define STM32_UART4CLK STM32_LSECLK
1658
1659#else
1660 #error "invalid source selected for UART4 clock"
1661#endif
1662
1663/**
1664 * @brief UART5 clock frequency.
1665 */
1666#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
1667 #define STM32_UART5CLK STM32_PCLK1
1668
1669#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
1670 #define STM32_UART5CLK STM32_SYSCLK
1671
1672#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
1673 #define STM32_UART5CLK STM32_HSI16CLK
1674
1675#elif STM32_UART5SEL == STM32_UART5SEL_LSE
1676 #define STM32_UART5CLK STM32_LSECLK
1677
1678#else
1679 #error "invalid source selected for UART5 clock"
1680#endif
1681
1682/**
1683 * @brief LPUART1 clock frequency.
1684 */
1685#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
1686 #define STM32_LPUART1CLK STM32_PCLK1
1687
1688#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
1689 #define STM32_LPUART1CLK STM32_SYSCLK
1690
1691#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
1692 #define STM32_LPUART1CLK STM32_HSI16CLK
1693
1694#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
1695 #define STM32_LPUART1CLK STM32_LSECLK
1696
1697#else
1698#error "invalid source selected for LPUART1 clock"
1699#endif
1700
1701/**
1702 * @brief I2C1 clock frequency.
1703 */
1704#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
1705 #define STM32_I2C1CLK STM32_PCLK1
1706
1707#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
1708 #define STM32_I2C1CLK STM32_SYSCLK
1709
1710#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
1711 #define STM32_I2C1CLK STM32_HSI16CLK
1712
1713#else
1714 #error "invalid source selected for I2C1 clock"
1715#endif
1716
1717/**
1718 * @brief I2C2 clock frequency.
1719 */
1720#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
1721 #define STM32_I2C2CLK STM32_PCLK1
1722
1723#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
1724 #define STM32_I2C2CLK STM32_SYSCLK
1725
1726#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
1727 #define STM32_I2C2CLK STM32_HSI16CLK
1728
1729#else
1730 #error "invalid source selected for I2C1 clock"
1731#endif
1732
1733/**
1734 * @brief I2C3 clock frequency.
1735 */
1736#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
1737 #define STM32_I2C3CLK STM32_PCLK1
1738
1739#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
1740 #define STM32_I2C3CLK STM32_SYSCLK
1741
1742#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
1743 #define STM32_I2C3CLK STM32_HSI16CLK
1744
1745#else
1746 #error "invalid source selected for I2C3 clock"
1747#endif
1748
1749/**
1750 * @brief I2C4 clock frequency.
1751 */
1752#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
1753 #define STM32_I2C4CLK STM32_PCLK1
1754
1755#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
1756 #define STM32_I2C4CLK STM32_SYSCLK
1757
1758#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
1759 #define STM32_I2C4CLK STM32_HSI16CLK
1760
1761#else
1762 #error "invalid source selected for I2C4 clock"
1763#endif
1764
1765/**
1766 * @brief LPTIM1 clock frequency.
1767 */
1768#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
1769 #define STM32_LPTIM1CLK STM32_PCLK1
1770
1771#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
1772 #define STM32_LPTIM1CLK STM32_LSICLK
1773
1774#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
1775 #define STM32_LPTIM1CLK STM32_HSI16CLK
1776
1777#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
1778 #define STM32_LPTIM1CLK STM32_LSECLK
1779
1780#else
1781 #error "invalid source selected for LPTIM1 clock"
1782#endif
1783
1784/**
1785 * @brief SAI1 clock frequency.
1786 */
1787#if (STM32_SAI1SEL == STM32_SAI1SEL_SYSCLK) || defined(__DOXYGEN__)
1788 #define STM32_SAI1CLK STM32_SYSCLK
1789
1790#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK
1791 #define STM32_SAI1CLK STM32_PLL_Q_CLKOUT
1792
1793#elif STM32_SAI1SEL == STM32_SAI1SEL_HSI16
1794 #define STM32_SAI1CLK STM32_HSI16CLK
1795
1796#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
1797 #define STM32_SAI1CLK 0 /* Unknown, would require a board value */
1798
1799#else
1800 #error "invalid source selected for SAI1 clock"
1801#endif
1802
1803/**
1804 * @brief I2S23 clock frequency.
1805 */
1806#if (STM32_I2S23SEL == STM32_I2S23SEL_SYSCLK) || defined(__DOXYGEN__)
1807 #define STM32_I2S23CLK STM32_SYSCLK
1808
1809#elif STM32_I2S23SEL == STM32_I2S23SEL_PLLPCLK
1810 #define STM32_I2S23CLK STM32_PLL_P_CLKOUT
1811
1812#elif STM32_I2S23SEL == STM32_I2S23SEL_HSI16
1813 #define STM32_I2S23CLK STM32_HSI16CLK
1814
1815#elif STM32_I2S23SEL == STM32_I2S23SEL_CKIN
1816 #define STM32_I2S23CLK 0 /* Unknown, would require a board value */
1817
1818#else
1819 #error "invalid source selected for SAI1 clock"
1820#endif
1821
1822/**
1823 * @brief FDCAN clock frequency.
1824 */
1825#if (STM32_FDCANSEL == STM32_FDCANSEL_HSE) || defined(__DOXYGEN__)
1826 #define STM32_FDCANCLK STM32_HSECLK
1827
1828#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
1829 #define STM32_FDCANCLK STM32_PLL_Q_CLKOUT
1830
1831#elif STM32_FDCANSEL == STM32_FDCANSEL_PCLK1
1832 #define STM32_FDCANCLK STM32_PCLK1
1833
1834#else
1835 #error "invalid source selected for FDCAN clock"
1836#endif
1837
1838/**
1839 * @brief 48MHz clock frequency.
1840 */
1841#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
1842 #define STM32_48CLK STM32_HSI48CLK
1843
1844#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK
1845 #define STM32_48CLK STM32_PLL_Q_CLKOUT
1846
1847#else
1848 #error "invalid source selected for 48MHz clock"
1849#endif
1850
1851/**
1852 * @brief ADC clock frequency.
1853 */
1854#if (STM32_ADC12SEL == STM32_ADC12SEL_NOCLK) || defined(__DOXYGEN__)
1855 #define STM32_ADC12CLK 0
1856
1857#elif STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK
1858 #define STM32_ADC12CLK STM32_PLL_P_CLKOUT
1859
1860#elif STM32_ADC12SEL == STM32_ADC12SEL_SYSCLK
1861 #define STM32_ADC12CLK STM32_SYSCLK
1862
1863#else
1864 #error "invalid source selected for ADC clock"
1865#endif
1866
1867/**
1868 * @brief ADC clock frequency.
1869 */
1870#if (STM32_ADC345SEL == STM32_ADC345SEL_NOCLK) || defined(__DOXYGEN__)
1871 #define STM32_ADC345CLK 0
1872
1873#elif STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK
1874 #define STM32_ADC345CLK STM32_PLL_P_CLKOUT
1875
1876#elif STM32_ADC345SEL == STM32_ADC345SEL_SYSCLK
1877 #define STM32_ADC345CLK STM32_SYSCLK
1878
1879#else
1880 #error "invalid source selected for ADC clock"
1881#endif
1882
1883/**
1884 * @brief TIMP1CLK clock frequency.
1885 */
1886#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1887 #define STM32_TIMP1CLK (STM32_PCLK1 * 1)
1888#else
1889 #define STM32_TIMP1CLK (STM32_PCLK1 * 2)
1890#endif
1891
1892/**
1893 * @brief TIMP2CLK clock frequency.
1894 */
1895#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1896 #define STM32_TIMP2CLK (STM32_PCLK2 * 1)
1897#else
1898 #define STM32_TIMP2CLK (STM32_PCLK2 * 2)
1899#endif
1900
1901/**
1902 * @brief Clock of timers connected to APB1.
1903 */
1904#define STM32_TIMCLK1 STM32_TIMP1CLK
1905
1906/**
1907 * @brief Clock of timers connected to APB2.
1908 */
1909#define STM32_TIMCLK2 STM32_TIMP2CLK
1910
1911/**
1912 * @brief RNG clock point.
1913 */
1914#define STM32_RNGCLK STM32_48CLK
1915
1916/**
1917 * @brief USB clock point.
1918 */
1919#define STM32_USBCLK STM32_48CLK
1920
1921/**
1922 * @brief Voltage boost settings.
1923 */
1924#if STM32_PWR_BOOST || defined(__DOXYGEN__)
1925#define STM32_CR5BITS PWR_CR5_R1MODE
1926#else
1927#define STM32_CR5BITS 0U
1928#endif
1929
1930/**
1931 * @brief Flash settings.
1932 */
1933#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
1934 #define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
1935
1936#elif STM32_HCLK <= STM32_1WS_THRESHOLD
1937 #define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
1938
1939#elif STM32_HCLK <= STM32_2WS_THRESHOLD
1940 #define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
1941
1942#elif STM32_HCLK <= STM32_3WS_THRESHOLD
1943 #define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
1944
1945#elif STM32_HCLK <= STM32_4WS_THRESHOLD
1946 #define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
1947
1948#else
1949 #define STM32_FLASHBITS FLASH_ACR_LATENCY_5WS
1950#endif
1951
1952/*===========================================================================*/
1953/* Driver data structures and types. */
1954/*===========================================================================*/
1955
1956/*===========================================================================*/
1957/* Driver macros. */
1958/*===========================================================================*/
1959
1960/*===========================================================================*/
1961/* External declarations. */
1962/*===========================================================================*/
1963
1964/* Various helpers.*/
1965#include "nvic.h"
1966#include "cache.h"
1967#include "mpu_v7m.h"
1968#include "stm32_isr.h"
1969#include "stm32_dma.h"
1970#include "stm32_exti.h"
1971#include "stm32_rcc.h"
1972#include "stm32_tim.h"
1973
1974#ifdef __cplusplus
1975extern "C" {
1976#endif
1977 void hal_lld_init(void);
1978 void stm32_clock_init(void);
1979#ifdef __cplusplus
1980}
1981#endif
1982
1983#endif /* HAL_LLD_H */
1984
1985/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:06:24 +0100