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-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.c277
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.h1985
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/platform.mk46
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h183
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.c183
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.h298
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h1366
-rw-r--r--lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_registry.h524
8 files changed, 4862 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.c b/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.c
new file mode 100644
index 000000000..454f7f401
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.c
@@ -0,0 +1,277 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/hal_lld.c
19 * @brief STM32G4xx HAL subsystem low level driver source.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31/*===========================================================================*/
32/* Driver exported variables. */
33/*===========================================================================*/
34
35/**
36 * @brief CMSIS system core clock variable.
37 * @note It is declared in system_stm32g4xx.h.
38 */
39uint32_t SystemCoreClock = STM32_HCLK;
40
41/*===========================================================================*/
42/* Driver local variables and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver local functions. */
47/*===========================================================================*/
48
49/**
50 * @brief Initializes the backup domain.
51 * @note WARNING! Changing RTC clock source impossible without resetting
52 * of the whole BKP domain.
53 */
54static void hal_lld_backup_domain_init(void) {
55
56 /* Reset BKP domain if different clock source selected.*/
57 if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
58 /* Backup domain reset.*/
59 RCC->BDCR = RCC_BDCR_BDRST;
60 RCC->BDCR = 0;
61 }
62
63#if STM32_LSE_ENABLED
64 /* LSE activation.*/
65#if defined(STM32_LSE_BYPASS)
66 /* LSE Bypass.*/
67 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
68#else
69 /* No LSE Bypass.*/
70 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
71#endif
72 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
73 ; /* Wait until LSE is stable. */
74#endif
75
76#if HAL_USE_RTC
77 /* If the backup domain hasn't been initialized yet then proceed with
78 initialization.*/
79 if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
80 /* Selects clock source.*/
81 RCC->BDCR |= STM32_RTCSEL;
82
83 /* RTC clock enabled.*/
84 RCC->BDCR |= RCC_BDCR_RTCEN;
85 }
86#endif /* HAL_USE_RTC */
87
88 /* Low speed output mode.*/
89 RCC->BDCR |= STM32_LSCOSEL;
90}
91
92/*===========================================================================*/
93/* Driver interrupt handlers. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Driver exported functions. */
98/*===========================================================================*/
99
100/**
101 * @brief Low level HAL driver initialization.
102 *
103 * @notapi
104 */
105void hal_lld_init(void) {
106
107 /* Initializes the backup domain.*/
108 hal_lld_backup_domain_init();
109
110 /* DMA subsystems initialization.*/
111#if defined(STM32_DMA_REQUIRED)
112 dmaInit();
113#endif
114
115 /* IRQ subsystem initialization.*/
116 irqInit();
117
118 /* Programmable voltage detector settings.*/
119 PWR->CR2 = STM32_PWR_CR2;
120}
121
122/**
123 * @brief STM32L4xx clocks and PLL initialization.
124 * @note All the involved constants come from the file @p board.h.
125 * @note This function should be invoked just after the system reset.
126 *
127 * @special
128 */
129void stm32_clock_init(void) {
130
131#if !STM32_NO_INIT
132
133 /* Reset of all peripherals.
134 Note, GPIOs are not reset because initialized before this point in
135 board files.*/
136 rccResetAHB1(~0);
137 rccResetAHB2(~STM32_GPIO_EN_MASK);
138 rccResetAHB3(~0);
139 rccResetAPB1R1(~0);
140 rccResetAPB1R2(~0);
141 rccResetAPB2(~0);
142
143 /* PWR clock enable.*/
144#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
145 rccEnableAPB1R1(RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN, false)
146#else
147 rccEnableAPB1R1(RCC_APB1ENR1_PWREN, false)
148#endif
149
150 /* Core voltage setup.*/
151 PWR->CR1 = STM32_VOS;
152 while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
153 ; /* stable. */
154
155 /* Additional PWR configurations.*/
156 PWR->CR2 = STM32_PWR_CR2;
157 PWR->CR3 = STM32_PWR_CR3;
158 PWR->CR4 = STM32_PWR_CR4;
159 PWR->CR5 = STM32_CR5BITS;
160 PWR->PUCRA = STM32_PWR_PUCRA;
161 PWR->PDCRA = STM32_PWR_PDCRA;
162 PWR->PUCRB = STM32_PWR_PUCRB;
163 PWR->PDCRB = STM32_PWR_PDCRB;
164 PWR->PUCRC = STM32_PWR_PUCRC;
165 PWR->PDCRC = STM32_PWR_PDCRC;
166 PWR->PUCRD = STM32_PWR_PUCRD;
167 PWR->PDCRD = STM32_PWR_PDCRD;
168 PWR->PUCRE = STM32_PWR_PUCRE;
169 PWR->PDCRE = STM32_PWR_PDCRE;
170 PWR->PUCRF = STM32_PWR_PUCRF;
171 PWR->PDCRF = STM32_PWR_PDCRF;
172 PWR->PUCRG = STM32_PWR_PUCRG;
173 PWR->PDCRG = STM32_PWR_PDCRG;
174
175#if STM32_HSI16_ENABLED
176 /* HSI activation.*/
177 RCC->CR |= RCC_CR_HSION;
178 while ((RCC->CR & RCC_CR_HSIRDY) == 0)
179 ; /* Wait until HSI16 is stable. */
180#endif
181
182#if STM32_HSI48_ENABLED
183 /* HSI activation.*/
184 RCC->CRRCR |= RCC_CRRCR_HSI48ON;
185 while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
186 ; /* Wait until HSI48 is stable. */
187#endif
188
189#if STM32_HSE_ENABLED
190#if defined(STM32_HSE_BYPASS)
191 /* HSE Bypass.*/
192 RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
193#endif
194 /* HSE activation.*/
195 RCC->CR |= RCC_CR_HSEON;
196 while ((RCC->CR & RCC_CR_HSERDY) == 0)
197 ; /* Wait until HSE is stable. */
198#endif
199
200#if STM32_LSI_ENABLED
201 /* LSI activation.*/
202 RCC->CSR |= RCC_CSR_LSION;
203 while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
204 ; /* Wait until LSI is stable. */
205#endif
206
207 /* Backup domain access enabled and left open.*/
208 PWR->CR1 |= PWR_CR1_DBP;
209
210#if STM32_LSE_ENABLED
211 /* LSE activation.*/
212#if defined(STM32_LSE_BYPASS)
213 /* LSE Bypass.*/
214 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
215#else
216 /* No LSE Bypass.*/
217 RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
218#endif
219 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
220 ; /* Wait until LSE is stable. */
221#endif
222
223#if STM32_ACTIVATE_PLL
224 /* PLLM and PLLSRC are common to all PLLs.*/
225 RCC->PLLCFGR = STM32_PLLPDIV |
226 STM32_PLLR | STM32_PLLREN |
227 STM32_PLLQ | STM32_PLLQEN |
228 STM32_PLLP | STM32_PLLPEN |
229 STM32_PLLN | STM32_PLLM |
230 STM32_PLLSRC;
231#endif
232
233#if STM32_ACTIVATE_PLL
234 /* PLL activation.*/
235 RCC->CR |= RCC_CR_PLLON;
236
237 /* Waiting for PLL lock.*/
238 while ((RCC->CR & RCC_CR_PLLRDY) == 0)
239 ;
240#endif
241
242 /* Other clock-related settings (dividers, MCO etc).*/
243 RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 |
244 STM32_HPRE;
245
246 /* CCIPR registers initialization, note.*/
247 RCC->CCIPR = STM32_ADC345SEL | STM32_ADC12SEL | STM32_CLK48SEL |
248 STM32_FDCANSEL | STM32_I2S23SEL | STM32_SAI1SEL |
249 STM32_LPTIM1SEL | STM32_I2C3SEL | STM32_I2C2SEL |
250 STM32_I2C1SEL | STM32_LPUART1SEL | STM32_UART5SEL |
251 STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
252 STM32_USART1SEL;
253 RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL;
254
255 /* Set flash WS's for SYSCLK source */
256 FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |
257 FLASH_ACR_PRFTEN | STM32_FLASHBITS;
258 while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
259 (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
260 }
261
262 /* Switching to the configured SYSCLK source if it is different from HSI16.*/
263#if STM32_SW != STM32_SW_HSI16
264 RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
265 /* Wait until SYSCLK is stable.*/
266 while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
267 ;
268#endif
269
270#endif /* STM32_NO_INIT */
271
272 /* SYSCFG clock enabled here because it is a multi-functional unit shared
273 among multiple drivers.*/
274 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
275}
276
277/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.h b/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.h
new file mode 100644
index 000000000..3954096a9
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/hal_lld.h
@@ -0,0 +1,1985 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/hal_lld.h
19 * @brief STM32G4xx HAL subsystem low level driver header.
20 * @pre This module requires the following macros to be defined in the
21 * @p board.h file:
22 * - STM32_LSECLK.
23 * - STM32_LSEDRV.
24 * - STM32_LSE_BYPASS (optionally).
25 * - STM32_HSECLK.
26 * - STM32_HSE_BYPASS (optionally).
27 * .
28 * One of the following macros must also be defined:
29 * - STM32G431xx, STM32G441xx, STM32G471xx.
30 * - STM32G473xx, STM32G483xx.
31 * - STM32G474xx, STM32G484xx.
32 * - STM32GBK1CB.
33 * .
34 *
35 * @addtogroup HAL
36 * @{
37 */
38
39#ifndef HAL_LLD_H
40#define HAL_LLD_H
41
42#include "stm32_registry.h"
43
44/*===========================================================================*/
45/* Driver constants. */
46/*===========================================================================*/
47
48/**
49 * @name Platform identification
50 * @{
51 */
52#if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
53 defined(__DOXYGEN__)
54#define PLATFORM_NAME "STM32G4 Access Line"
55
56#elif defined(STM32G473xx)
57#define PLATFORM_NAME "STM32G4 Performance Line"
58
59#elif defined(STM32G483xx)
60#define PLATFORM_NAME "STM32G4 Performance Line with Crypto"
61
62#elif defined(STM32G474xx)
63#define PLATFORM_NAME "STM32G4 Hi-resolution Line"
64
65#elif defined(STM32G484xx)
66#define PLATFORM_NAME "STM32G4 Hi-resolution Line with Crypto"
67
68#elif defined(STM32GBK1CB)
69#define PLATFORM_NAME "STM32G4 Mystery Line"
70
71#else
72#error "STM32G4 device not specified"
73#endif
74
75/**
76 * @brief Sub-family identifier.
77 */
78#if !defined(STM32G4XX) || defined(__DOXYGEN__)
79#define STM32G4XX
80#endif
81/** @} */
82
83/**
84 * @name Internal clock sources
85 * @{
86 */
87#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
88#define STM32_HSI48CLK 48000000U /**< 48MHz internal clock. */
89#define STM32_LSICLK 32000U /**< Low speed internal clock. */
90/** @} */
91
92/**
93 * @name VOS field definitions
94 * @{
95 */
96#define STM32_VOS_MASK (3U << 9U) /**< Core voltage mask. */
97#define STM32_VOS_RANGE1 (1U << 9U) /**< Core voltage 1.2 Volts. */
98#define STM32_VOS_RANGE2 (2U << 9U) /**< Core voltage 1.0 Volts. */
99/** @} */
100
101/**
102 * @name RCC_CFGR register bits definitions
103 * @{
104 */
105#define STM32_SW_MASK (3U << 0U) /**< SW field mask. */
106#define STM32_SW_HSI16 (1U << 0U) /**< SYSCLK source is HSI16. */
107#define STM32_SW_HSE (2U << 0U) /**< SYSCLK source is HSE. */
108#define STM32_SW_PLLRCLK (3U << 0U) /**< SYSCLK source is PLL. */
109
110#define STM32_HPRE_MASK (15U << 4U) /**< HPRE field mask. */
111#define STM32_HPRE_FIELD(n) ((n) << 4U) /**< HPRE field value. */
112#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
113#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
114#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
115#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
116#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
117#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
118#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
119#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
120#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
121
122#define STM32_PPRE1_MASK (7U << 8U) /**< PPRE1 field mask. */
123#define STM32_PPRE1_FIELD(n) ((n) << 8U) /**< PPRE1 field value. */
124#define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U)
125#define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U)
126#define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U)
127#define STM32_PPRE1_DIV8 STM32_PPRE1_FIELD(6U)
128#define STM32_PPRE1_DIV16 STM32_PPRE1_FIELD(7U)
129
130#define STM32_PPRE2_MASK (7U << 11U) /**< PPRE2 field mask. */
131#define STM32_PPRE2_FIELD(n) ((n) << 11U) /**< PPRE2 field value. */
132#define STM32_PPRE2_DIV1 STM32_PPRE2_FIELD(0U)
133#define STM32_PPRE2_DIV2 STM32_PPRE2_FIELD(4U)
134#define STM32_PPRE2_DIV4 STM32_PPRE2_FIELD(5U)
135#define STM32_PPRE2_DIV8 STM32_PPRE2_FIELD(6U)
136#define STM32_PPRE2_DIV16 STM32_PPRE2_FIELD(7U)
137
138#define STM32_MCOSEL_MASK (15U << 24U)/**< MCOSEL field mask. */
139#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
140#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
141#define STM32_MCOSEL_HSI16 (3U << 24U) /**< HSI16 clock on MCO pin. */
142#define STM32_MCOSEL_HSE (4U << 24U) /**< HSE clock on MCO pin. */
143#define STM32_MCOSEL_PLLRCLK (5U << 24U) /**< PLLR clock on MCO pin. */
144#define STM32_MCOSEL_LSI (6U << 24U) /**< LSI clock on MCO pin. */
145#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
146#define STM32_MCOSEL_HSI48 (8U << 24U) /**< HSI48 clock on MCO pin. */
147
148#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
149#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
150#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U)
151#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U)
152#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U)
153#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U)
154#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U)
155/** @} */
156
157/**
158 * @name RCC_PLLCFGR register bits definitions
159 * @{
160 */
161#define STM32_PLLSRC_MASK (3 << 0) /**< PLL clock source mask. */
162#define STM32_PLLSRC_NOCLOCK (0 << 0) /**< PLL clock source disabled. */
163#define STM32_PLLSRC_HSI16 (2 << 0) /**< PLL clock source is HSI16. */
164#define STM32_PLLSRC_HSE (3 << 0) /**< PLL clock source is HSE. */
165/** @} */
166
167/**
168 * @name RCC_CCIPR register bits definitions
169 * @{
170 */
171#define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */
172#define STM32_USART1SEL_PCLK2 (0U << 0U) /**< USART1 source is PCLK2. */
173#define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */
174#define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */
175#define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */
176
177#define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */
178#define STM32_USART2SEL_PCLK1 (0U << 2U) /**< USART2 source is PCLK1. */
179#define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */
180#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
181#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
182
183#define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */
184#define STM32_USART3SEL_PCLK1 (0U << 4U) /**< USART3 source is PCLK1. */
185#define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */
186#define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */
187#define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */
188
189#define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */
190#define STM32_UART4SEL_PCLK1 (0U << 6U) /**< UART4 source is PCLK1. */
191#define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */
192#define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */
193#define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */
194
195#define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */
196#define STM32_UART5SEL_PCLK1 (0U << 8U) /**< UART5 source is PCLK1. */
197#define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */
198#define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */
199#define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */
200
201#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
202#define STM32_LPUART1SEL_PCLK1 (0U << 10U) /**< LPUART1 source is PCLK1. */
203#define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */
204#define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */
205#define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */
206
207#define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */
208#define STM32_I2C1SEL_PCLK1 (0U << 12U) /**< I2C1 source is PCLK1. */
209#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
210#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
211
212#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */
213#define STM32_I2C2SEL_PCLK1 (0U << 14U) /**< I2C2 source is PCLK1. */
214#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */
215#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */
216
217#define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */
218#define STM32_I2C3SEL_PCLK1 (0U << 16U) /**< I2C3 source is PCLK1. */
219#define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */
220#define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */
221
222#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
223#define STM32_LPTIM1SEL_PCLK1 (0U << 18U) /**< LPTIM1 source is PCLK1. */
224#define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */
225#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
226#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
227
228#define STM32_SAI1SEL_MASK (3U << 20U) /**< SAI1SEL mask. */
229#define STM32_SAI1SEL_SYSCLK (0U << 20U) /**< SAI1 source is SYSCLK. */
230#define STM32_SAI1SEL_PLLQCLK (1U << 20U) /**< SAI1 source is PLLQCLK. */
231#define STM32_SAI1SEL_CKIN (2U << 20U) /**< SAI1 source is CKIN. */
232#define STM32_SAI1SEL_HSI16 (3U << 20U) /**< SAI1 source is HSI16. */
233
234#define STM32_I2S23SEL_MASK (3U << 22U) /**< I2S23SEL mask. */
235#define STM32_I2S23SEL_SYSCLK (0U << 22U) /**< I2S23 source is SYSCLK. */
236#define STM32_I2S23SEL_PLLQCLK (1U << 22U) /**< I2S23 source is PLLQCLK. */
237#define STM32_I2S23SEL_CKIN (2U << 22U) /**< I2S23 source is CKIN. */
238#define STM32_I2S23SEL_HSI16 (3U << 22U) /**< I2S23 source is HSI16. */
239
240#define STM32_FDCANSEL_MASK (3U << 24U) /**< FDCANSEL mask. */
241#define STM32_FDCANSEL_HSE (0U << 24U) /**< FDCAN source is HSE. */
242#define STM32_FDCANSEL_PLLQCLK (1U << 24U) /**< FDCAN source is PLLQCLK. */
243#define STM32_FDCANSEL_PCLK1 (2U << 24U) /**< FDCAN source is PCLK1. */
244
245#define STM32_CLK48SEL_MASK (3U << 26U) /**< CLK48SEL mask. */
246#define STM32_CLK48SEL_HSI48 (0U << 26U) /**< CLK48 source is HSI48. */
247#define STM32_CLK48SEL_PLLQCLK (2U << 26U) /**< CLK48 source is PLLQCLK. */
248
249#define STM32_ADC12SEL_MASK (3U << 28U) /**< ADC12SEL mask. */
250#define STM32_ADC12SEL_NOCLK (0U << 28U) /**< ADC12 source is none. */
251#define STM32_ADC12SEL_PLLPCLK (1U << 28U) /**< ADC12 source is PLLPCLK. */
252#define STM32_ADC12SEL_SYSCLK (2U << 28U) /**< ADC12 source is SYSCLK. */
253
254#define STM32_ADC345SEL_MASK (3U << 30U) /**< ADC345SEL mask. */
255#define STM32_ADC345SEL_NOCLK (0U << 30U) /**< ADC345 source is none. */
256#define STM32_ADC345SEL_PLLPCLK (1U << 30U) /**< ADC345 source is PLLPCLK. */
257#define STM32_ADC345SEL_SYSCLK (2U << 30U) /**< ADC345 source is SYSCLK. */
258/** @} */
259
260/**
261 * @name RCC_CCIPR2 register bits definitions
262 * @{
263 */
264#define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */
265#define STM32_I2C4SEL_PCLK1 (0U << 0U) /**< I2C4 source is PCLK1. */
266#define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */
267#define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */
268
269#define STM32_QSPISEL_MASK (3U << 20U) /**< QSPISEL mask. */
270#define STM32_QSPISEL_SYSCLK (0U << 20U) /**< QSPI source is SYSCLK. */
271#define STM32_QSPISEL_HSI16 (1U << 20U) /**< QSPI source is HSI16. */
272#define STM32_QSPISEL_PLLQCLK (2U << 20U) /**< QSPI source is PLLQCLK. */
273/** @} */
274
275/**
276 * @name RCC_BDCR register bits definitions
277 * @{
278 */
279#define STM32_RTCSEL_MASK (3U << 8U) /**< RTC source mask. */
280#define STM32_RTCSEL_NOCLOCK (0U << 8U) /**< No RTC source. */
281#define STM32_RTCSEL_LSE (1U << 8U) /**< RTC source is LSE. */
282#define STM32_RTCSEL_LSI (2U << 8U) /**< RTC source is LSI. */
283#define STM32_RTCSEL_HSEDIV (3U << 8U) /**< RTC source is HSE divided. */
284
285#define STM32_LSCOSEL_MASK (3U << 24U) /**< LSCO pin clock source. */
286#define STM32_LSCOSEL_NOCLOCK (0U << 24U) /**< No clock on LSCO pin. */
287#define STM32_LSCOSEL_LSI (1U << 24U) /**< LSI on LSCO pin. */
288#define STM32_LSCOSEL_LSE (3U << 24U) /**< LSE on LSCO pin. */
289/** @} */
290
291/*===========================================================================*/
292/* Driver pre-compile time settings. */
293/*===========================================================================*/
294
295/**
296 * @name Configuration options
297 * @{
298 */
299/**
300 * @brief Disables the PWR/RCC initialization in the HAL.
301 */
302#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
303#define STM32_NO_INIT FALSE
304#endif
305
306/**
307 * @brief Core voltage selection.
308 * @note This setting affects all the performance and clock related
309 * settings, the maximum performance is only obtainable selecting
310 * the maximum voltage.
311 */
312#if !defined(STM32_VOS) || defined(__DOXYGEN__)
313#define STM32_VOS STM32_VOS_RANGE1
314#endif
315
316/**
317 * @brief Core voltage boost.
318 * @note The boost can only be used when STM32_VOS==STM32_VOS_RANGE1.
319 */
320#if !defined(STM32_PWR_BOOST) || defined(__DOXYGEN__)
321#define STM32_PWR_BOOST TRUE
322#endif
323
324/**
325 * @brief PWR CR2 register initialization value.
326 */
327#if !defined(STM32_PWR_CR2) || defined(__DOXYGEN__)
328#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
329#endif
330
331/**
332 * @brief PWR CR3 register initialization value.
333 */
334#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)
335#define STM32_PWR_CR3 (PWR_CR3_EIWF)
336#endif
337
338/**
339 * @brief PWR CR4 register initialization value.
340 */
341#if !defined(STM32_PWR_CR4) || defined(__DOXYGEN__)
342#define STM32_PWR_CR4 (0U)
343#endif
344
345/**
346 * @brief PWR PUCRA register initialization value.
347 */
348#if !defined(STM32_PWR_PUCRA) || defined(__DOXYGEN__)
349#define STM32_PWR_PUCRA (0U)
350#endif
351
352/**
353 * @brief PWR PDCRA register initialization value.
354 */
355#if !defined(STM32_PWR_PDCRA) || defined(__DOXYGEN__)
356#define STM32_PWR_PDCRA (0U)
357#endif
358
359/**
360 * @brief PWR PUCRB register initialization value.
361 */
362#if !defined(STM32_PWR_PUCRB) || defined(__DOXYGEN__)
363#define STM32_PWR_PUCRB (0U)
364#endif
365
366/**
367 * @brief PWR PDCRB register initialization value.
368 */
369#if !defined(STM32_PWR_PDCRB) || defined(__DOXYGEN__)
370#define STM32_PWR_PDCRB (0U)
371#endif
372
373/**
374 * @brief PWR PUCRC register initialization value.
375 */
376#if !defined(STM32_PWR_PUCRC) || defined(__DOXYGEN__)
377#define STM32_PWR_PUCRC (0U)
378#endif
379
380/**
381 * @brief PWR PDCRC register initialization value.
382 */
383#if !defined(STM32_PWR_PDCRC) || defined(__DOXYGEN__)
384#define STM32_PWR_PDCRC (0U)
385#endif
386
387/**
388 * @brief PWR PUCRD register initialization value.
389 */
390#if !defined(STM32_PWR_PUCRD) || defined(__DOXYGEN__)
391#define STM32_PWR_PUCRD (0U)
392#endif
393
394/**
395 * @brief PWR PDCRD register initialization value.
396 */
397#if !defined(STM32_PWR_PDCRD) || defined(__DOXYGEN__)
398#define STM32_PWR_PDCRD (0U)
399#endif
400
401/**
402 * @brief PWR PUCRE register initialization value.
403 */
404#if !defined(STM32_PWR_PUCRE) || defined(__DOXYGEN__)
405#define STM32_PWR_PUCRE (0U)
406#endif
407
408/**
409 * @brief PWR PDCRE register initialization value.
410 */
411#if !defined(STM32_PWR_PDCRE) || defined(__DOXYGEN__)
412#define STM32_PWR_PDCRE (0U)
413#endif
414
415/**
416 * @brief PWR PUCRF register initialization value.
417 */
418#if !defined(STM32_PWR_PUCRF) || defined(__DOXYGEN__)
419#define STM32_PWR_PUCRF (0U)
420#endif
421
422/**
423 * @brief PWR PDCRF register initialization value.
424 */
425#if !defined(STM32_PWR_PDCRF) || defined(__DOXYGEN__)
426#define STM32_PWR_PDCRF (0U)
427#endif
428
429/**
430 * @brief PWR PUCRG register initialization value.
431 */
432#if !defined(STM32_PWR_PUCRG) || defined(__DOXYGEN__)
433#define STM32_PWR_PUCRG (0U)
434#endif
435
436/**
437 * @brief PWR PDCRG register initialization value.
438 */
439#if !defined(STM32_PWR_PDCRG) || defined(__DOXYGEN__)
440#define STM32_PWR_PDCRG (0U)
441#endif
442
443/**
444 * @brief Enables or disables the HSI16 clock source.
445 */
446#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
447#define STM32_HSI16_ENABLED FALSE
448#endif
449
450/**
451 * @brief Enables or disables the HSI48 clock source.
452 */
453#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
454#define STM32_HSI48_ENABLED FALSE
455#endif
456
457/**
458 * @brief Enables or disables the HSE clock source.
459 */
460#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
461#define STM32_HSE_ENABLED FALSE
462#endif
463
464/**
465 * @brief Enables or disables the LSI clock source.
466 */
467#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
468#define STM32_LSI_ENABLED FALSE
469#endif
470
471/**
472 * @brief Enables or disables the LSE clock source.
473 */
474#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
475#define STM32_LSE_ENABLED FALSE
476#endif
477
478/**
479 * @brief Main clock source selection.
480 * @note If the selected clock source is not the PLL then the PLL is not
481 * initialized and started.
482 * @note The default value is calculated for a 170MHz system clock from
483 * the internal 16MHz HSI clock.
484 */
485#if !defined(STM32_SW) || defined(__DOXYGEN__)
486#define STM32_SW STM32_SW_PLLRCLK
487#endif
488
489/**
490 * @brief Clock source for the PLL.
491 * @note This setting has only effect if the PLL is selected as the
492 * system clock source.
493 * @note The default value is calculated for a 170MHz system clock from
494 * the internal 16MHz HSI clock.
495 */
496#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
497#define STM32_PLLSRC STM32_PLLSRC_HSI16
498#endif
499
500/**
501 * @brief PLLM divider value.
502 * @note The allowed values are 1..16.
503 * @note The default value is calculated for a 170MHz system clock from
504 * the internal 16MHz HSI clock.
505 */
506#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
507#define STM32_PLLM_VALUE 4
508#endif
509
510/**
511 * @brief PLLN multiplier value.
512 * @note The allowed values are 8..127.
513 * @note The default value is calculated for a 170MHz system clock from
514 * the internal 16MHz HSI clock.
515 */
516#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
517#define STM32_PLLN_VALUE 84
518#endif
519
520/**
521 * @brief PLLPDIV divider value or zero if disabled.
522 * @note The allowed values are 0, 2..31.
523 */
524#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
525#define STM32_PLLPDIV_VALUE 0
526#endif
527
528/**
529 * @brief PLLP divider value.
530 * @note The allowed values are 7, 17.
531 */
532#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
533#define STM32_PLLP_VALUE 7
534#endif
535
536/**
537 * @brief PLLQ divider value.
538 * @note The allowed values are 2, 4, 6, 8.
539 */
540#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
541#define STM32_PLLQ_VALUE 8
542#endif
543
544/**
545 * @brief PLLR divider value.
546 * @note The allowed values are 2, 4, 6, 8.
547 * @note The default value is calculated for a 170MHz system clock from
548 * the internal 16MHz HSI clock.
549 */
550#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
551#define STM32_PLLR_VALUE 2
552#endif
553
554/**
555 * @brief AHB prescaler value.
556 * @note The default value is calculated for a 170MHz system clock from
557 * the internal 16MHz HSI clock.
558 */
559#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
560#define STM32_HPRE STM32_HPRE_DIV1
561#endif
562
563/**
564 * @brief APB1 prescaler value.
565 */
566#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
567#define STM32_PPRE1 STM32_PPRE1_DIV2
568#endif
569
570/**
571 * @brief APB2 prescaler value.
572 */
573#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
574#define STM32_PPRE2 STM32_PPRE2_DIV1
575#endif
576
577/**
578 * @brief MCO clock source.
579 */
580#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
581#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
582#endif
583
584/**
585 * @brief MCO divider setting.
586 */
587#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
588#define STM32_MCOPRE STM32_MCOPRE_DIV1
589#endif
590
591/**
592 * @brief LSCO clock source.
593 */
594#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
595#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
596#endif
597
598/**
599 * @brief USART1 clock source.
600 */
601#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
602#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
603#endif
604
605/**
606 * @brief USART2 clock source.
607 */
608#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
609#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
610#endif
611
612/**
613 * @brief USART3 clock source.
614 */
615#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__)
616#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
617#endif
618
619/**
620 * @brief UART4 clock source.
621 */
622#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__)
623#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
624#endif
625
626/**
627 * @brief UART5 clock source.
628 */
629#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__)
630#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
631#endif
632
633/**
634 * @brief LPUART1 clock source.
635 */
636#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
637#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
638#endif
639
640/**
641 * @brief I2C1 clock source.
642 */
643#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
644#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
645#endif
646
647/**
648 * @brief I2C2 clock source.
649 */
650#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__)
651#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
652#endif
653
654/**
655 * @brief I2C3 clock source.
656 */
657#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__)
658#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
659#endif
660
661/**
662 * @brief I2C4 clock source.
663 */
664#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__)
665#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
666#endif
667
668/**
669 * @brief LPTIM1 clock source.
670 */
671#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
672#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
673#endif
674
675/**
676 * @brief SAI1 clock source.
677 */
678#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
679#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
680#endif
681
682/**
683 * @brief I2S23 clock source.
684 */
685#if !defined(STM32_I2S23SEL) || defined(__DOXYGEN__)
686#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
687#endif
688
689/**
690 * @brief FDCAN clock source.
691 */
692#if !defined(STM32_FDCANSEL) || defined(__DOXYGEN__)
693#define STM32_FDCANSEL STM32_FDCANSEL_HSE
694#endif
695
696/**
697 * @brief CLK48 clock source.
698 */
699#if !defined(STM32_CLK48SEL) || defined(__DOXYGEN__)
700#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
701#endif
702
703/**
704 * @brief ADC12 clock source.
705 */
706#if !defined(STM32_ADC12SEL) || defined(__DOXYGEN__)
707#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
708#endif
709
710/**
711 * @brief ADC34 clock source.
712 */
713#if !defined(STM32_ADC345SEL) || defined(__DOXYGEN__)
714#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
715#endif
716
717/**
718 * @brief QSPI clock source.
719 */
720#if !defined(STM32_QSPISEL) || defined(__DOXYGEN__)
721#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
722#endif
723
724/**
725 * @brief RTC clock source.
726 */
727#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
728#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
729#endif
730/** @} */
731
732/*===========================================================================*/
733/* Derived constants and error checks. */
734/*===========================================================================*/
735
736/* Boost mode checks.*/
737#if STM32_PWR_BOOST && (STM32_VOS != STM32_VOS_RANGE1)
738#error "STM32_PWR_BOOST requires STM32_VOS_RANGE1"
739#endif
740
741/*
742 * Configuration-related checks.
743 */
744#if !defined(STM32G4xx_MCUCONF)
745#error "Using a wrong mcuconf.h file, STM32G4xx_MCUCONF not defined"
746#endif
747
748#if defined(STM32G431xx) && !defined(STM32G431_MCUCONF)
749#error "Using a wrong mcuconf.h file, STM32G431_MCUCONF not defined"
750
751#elif defined(STM32G441xx) && !defined(STM32G441_MCUCONF)
752#error "Using a wrong mcuconf.h file, STM32G441_MCUCONF not defined"
753
754#elif defined(STM32G471xx) && !defined(STM32G471_MCUCONF)
755#error "Using a wrong mcuconf.h file, STM32G471_MCUCONF not defined"
756
757#elif defined(STM32G473xx) && !defined(STM32G473_MCUCONF)
758#error "Using a wrong mcuconf.h file, STM32G473_MCUCONF not defined"
759
760#elif defined(STM32G483xx) && !defined(STM32G473_MCUCONF)
761#error "Using a wrong mcuconf.h file, STM32G483_MCUCONF not defined"
762
763#elif defined(STM32G474xx) && !defined(STM32G474_MCUCONF)
764#error "Using a wrong mcuconf.h file, STM32G474_MCUCONF not defined"
765
766#elif defined(STM32G484xx) && !defined(STM32G484_MCUCONF)
767#error "Using a wrong mcuconf.h file, STM32G484_MCUCONF not defined"
768
769#elif defined(STM32GBK1CB) && !defined(STM32GBK1CB_MCUCONF)
770#error "Using a wrong mcuconf.h file, STM32GBK1CB_MCUCONF not defined"
771
772#endif
773
774/*
775 * Board files sanity checks.
776 */
777#if !defined(STM32_LSECLK)
778#error "STM32_LSECLK not defined in board.h"
779#endif
780
781#if !defined(STM32_LSEDRV)
782#error "STM32_LSEDRV not defined in board.h"
783#endif
784
785#if !defined(STM32_HSECLK)
786#error "STM32_HSECLK not defined in board.h"
787#endif
788
789/**
790 * @name System Limits for VOS range 1 with boost
791 * @{
792 */
793#define STM32_BOOST_SYSCLK_MAX 170000000
794#define STM32_BOOST_HSECLK_MAX 48000000
795#define STM32_BOOST_HSECLK_BYP_MAX 48000000
796#define STM32_BOOST_HSECLK_MIN 8000000
797#define STM32_BOOST_HSECLK_BYP_MIN 8000000
798#define STM32_BOOST_LSECLK_MAX 32768
799#define STM32_BOOST_LSECLK_BYP_MAX 1000000
800#define STM32_BOOST_LSECLK_MIN 32768
801#define STM32_BOOST_LSECLK_BYP_MIN 32768
802#define STM32_BOOST_PLLIN_MAX 16000000
803#define STM32_BOOST_PLLIN_MIN 2660000
804#define STM32_BOOST_PLLVCO_MAX 344000000
805#define STM32_BOOST_PLLVCO_MIN 96000000
806#define STM32_BOOST_PLLP_MAX 170000000
807#define STM32_BOOST_PLLP_MIN 2064500
808#define STM32_BOOST_PLLQ_MAX 170000000
809#define STM32_BOOST_PLLQ_MIN 8000000
810#define STM32_BOOST_PLLR_MAX 170000000
811#define STM32_BOOST_PLLR_MIN 8000000
812#define STM32_BOOST_PCLK1_MAX 170000000
813#define STM32_BOOST_PCLK2_MAX 170000000
814#define STM32_BOOST_ADCCLK_MAX 60000000
815
816#define STM32_BOOST_0WS_THRESHOLD 34000000
817#define STM32_BOOST_1WS_THRESHOLD 68000000
818#define STM32_BOOST_2WS_THRESHOLD 102000000
819#define STM32_BOOST_3WS_THRESHOLD 136000000
820#define STM32_BOOST_4WS_THRESHOLD 170000000
821/** @} */
822
823/**
824 * @name System Limits for VOS range 1 without boost
825 * @{
826 */
827#define STM32_VOS1_SYSCLK_MAX 150000000
828#define STM32_VOS1_HSECLK_MAX 48000000
829#define STM32_VOS1_HSECLK_BYP_MAX 48000000
830#define STM32_VOS1_HSECLK_MIN 8000000
831#define STM32_VOS1_HSECLK_BYP_MIN 8000000
832#define STM32_VOS1_LSECLK_MAX 32768
833#define STM32_VOS1_LSECLK_BYP_MAX 1000000
834#define STM32_VOS1_LSECLK_MIN 32768
835#define STM32_VOS1_LSECLK_BYP_MIN 32768
836#define STM32_VOS1_PLLIN_MAX 16000000
837#define STM32_VOS1_PLLIN_MIN 2660000
838#define STM32_VOS1_PLLVCO_MAX 344000000
839#define STM32_VOS1_PLLVCO_MIN 96000000
840#define STM32_VOS1_PLLP_MAX 150000000
841#define STM32_VOS1_PLLP_MIN 2064500
842#define STM32_VOS1_PLLQ_MAX 150000000
843#define STM32_VOS1_PLLQ_MIN 8000000
844#define STM32_VOS1_PLLR_MAX 150000000
845#define STM32_VOS1_PLLR_MIN 8000000
846#define STM32_VOS1_PCLK1_MAX 150000000
847#define STM32_VOS1_PCLK2_MAX 150000000
848#define STM32_VOS1_ADCCLK_MAX 60000000
849
850#define STM32_VOS1_0WS_THRESHOLD 30000000
851#define STM32_VOS1_1WS_THRESHOLD 60000000
852#define STM32_VOS1_2WS_THRESHOLD 90000000
853#define STM32_VOS1_3WS_THRESHOLD 120000000
854#define STM32_VOS1_4WS_THRESHOLD 150000000
855/** @} */
856
857/**
858 * @name System Limits for VOS range 2
859 * @{
860 */
861#define STM32_VOS2_SYSCLK_MAX 26000000
862#define STM32_VOS2_HSECLK_MAX 26000000
863#define STM32_VOS2_HSECLK_BYP_MAX 26000000
864#define STM32_VOS2_HSECLK_MIN 8000000
865#define STM32_VOS2_HSECLK_BYP_MIN 8000000
866#define STM32_VOS2_LSECLK_MAX 32768
867#define STM32_VOS2_LSECLK_BYP_MAX 1000000
868#define STM32_VOS2_LSECLK_MIN 32768
869#define STM32_VOS2_LSECLK_BYP_MIN 32768
870#define STM32_VOS2_PLLIN_MAX 16000000
871#define STM32_VOS2_PLLIN_MIN 2660000
872#define STM32_VOS2_PLLVCO_MAX 128000000
873#define STM32_VOS2_PLLVCO_MIN 96000000
874#define STM32_VOS2_PLLP_MAX 26000000
875#define STM32_VOS2_PLLP_MIN 2064500
876#define STM32_VOS2_PLLQ_MAX 26000000
877#define STM32_VOS2_PLLQ_MIN 8000000
878#define STM32_VOS2_PLLR_MAX 26000000
879#define STM32_VOS2_PLLR_MIN 8000000
880#define STM32_VOS2_PCLK1_MAX 26000000
881#define STM32_VOS2_PCLK2_MAX 26000000
882#define STM32_VOS2_ADCCLK_MAX 26000000
883
884#define STM32_VOS2_0WS_THRESHOLD 12000000
885#define STM32_VOS2_1WS_THRESHOLD 24000000
886#define STM32_VOS2_2WS_THRESHOLD 26000000
887#define STM32_VOS2_3WS_THRESHOLD 0
888#define STM32_VOS2_4WS_THRESHOLD 0
889/** @} */
890
891/* Voltage related limits.*/
892#if (STM32_VOS == STM32_VOS_RANGE1) || defined(__DOXYGEN__)
893#if STM32_PWR_BOOST || defined(__DOXYGEN__)
894#define STM32_SYSCLK_MAX STM32_BOOST_SYSCLK_MAX
895#define STM32_HSECLK_MAX STM32_BOOST_HSECLK_MAX
896#define STM32_HSECLK_BYP_MAX STM32_BOOST_HSECLK_BYP_MAX
897#define STM32_HSECLK_MIN STM32_BOOST_HSECLK_MIN
898#define STM32_HSECLK_BYP_MIN STM32_BOOST_HSECLK_BYP_MIN
899#define STM32_LSECLK_MAX STM32_BOOST_LSECLK_MAX
900#define STM32_LSECLK_BYP_MAX STM32_BOOST_LSECLK_BYP_MAX
901#define STM32_LSECLK_MIN STM32_BOOST_LSECLK_MIN
902#define STM32_LSECLK_BYP_MIN STM32_BOOST_LSECLK_BYP_MIN
903#define STM32_PLLIN_MAX STM32_BOOST_PLLIN_MAX
904#define STM32_PLLIN_MIN STM32_BOOST_PLLIN_MIN
905#define STM32_PLLVCO_MAX STM32_BOOST_PLLVCO_MAX
906#define STM32_PLLVCO_MIN STM32_BOOST_PLLVCO_MIN
907#define STM32_PLLP_MAX STM32_BOOST_PLLP_MAX
908#define STM32_PLLP_MIN STM32_BOOST_PLLP_MIN
909#define STM32_PLLQ_MAX STM32_BOOST_PLLQ_MAX
910#define STM32_PLLQ_MIN STM32_BOOST_PLLQ_MIN
911#define STM32_PLLR_MAX STM32_BOOST_PLLR_MAX
912#define STM32_PLLR_MIN STM32_BOOST_PLLR_MIN
913#define STM32_PCLK1_MAX STM32_BOOST_PCLK1_MAX
914#define STM32_PCLK2_MAX STM32_BOOST_PCLK2_MAX
915#define STM32_ADCCLK_MAX STM32_BOOST_ADCCLK_MAX
916
917#define STM32_0WS_THRESHOLD STM32_BOOST_0WS_THRESHOLD
918#define STM32_1WS_THRESHOLD STM32_BOOST_1WS_THRESHOLD
919#define STM32_2WS_THRESHOLD STM32_BOOST_2WS_THRESHOLD
920#define STM32_3WS_THRESHOLD STM32_BOOST_3WS_THRESHOLD
921#define STM32_4WS_THRESHOLD STM32_BOOST_4WS_THRESHOLD
922#define STM32_5WS_THRESHOLD STM32_BOOST_5WS_THRESHOLD
923#define STM32_6WS_THRESHOLD STM32_BOOST_6WS_THRESHOLD
924#define STM32_7WS_THRESHOLD STM32_BOOST_7WS_THRESHOLD
925#define STM32_8WS_THRESHOLD STM32_BOOST_8WS_THRESHOLD
926
927#else /* !STM32_PWR_BOOST */
928#define STM32_SYSCLK_MAX STM32_VOS1_SYSCLK_MAX_NOBOOST
929#define STM32_HSECLK_MAX STM32_VOS1_HSECLK_MAX
930#define STM32_HSECLK_BYP_MAX STM32_VOS1_HSECLK_BYP_MAX
931#define STM32_HSECLK_MIN STM32_VOS1_HSECLK_MIN
932#define STM32_HSECLK_BYP_MIN STM32_VOS1_HSECLK_BYP_MIN
933#define STM32_LSECLK_MAX STM32_VOS1_LSECLK_MAX
934#define STM32_LSECLK_BYP_MAX STM32_VOS1_LSECLK_BYP_MAX
935#define STM32_LSECLK_MIN STM32_VOS1_LSECLK_MIN
936#define STM32_LSECLK_BYP_MIN STM32_VOS1_LSECLK_BYP_MIN
937#define STM32_PLLIN_MAX STM32_VOS1_PLLIN_MAX
938#define STM32_PLLIN_MIN STM32_VOS1_PLLIN_MIN
939#define STM32_PLLVCO_MAX STM32_VOS1_PLLVCO_MAX
940#define STM32_PLLVCO_MIN STM32_VOS1_PLLVCO_MIN
941#define STM32_PLLP_MAX STM32_VOS1_PLLP_MAX
942#define STM32_PLLP_MIN STM32_VOS1_PLLP_MIN
943#define STM32_PLLQ_MAX STM32_VOS1_PLLQ_MAX
944#define STM32_PLLQ_MIN STM32_VOS1_PLLQ_MIN
945#define STM32_PLLR_MAX STM32_VOS1_PLLR_MAX
946#define STM32_PLLR_MIN STM32_VOS1_PLLR_MIN
947#define STM32_PCLK1_MAX STM32_VOS1_PCLK1_MAX
948#define STM32_PCLK2_MAX STM32_VOS1_PCLK2_MAX
949#define STM32_ADCCLK_MAX STM32_VOS1_ADCCLK_MAX
950
951#define STM32_0WS_THRESHOLD STM32_VOS1_0WS_THRESHOLD
952#define STM32_1WS_THRESHOLD STM32_VOS1_1WS_THRESHOLD
953#define STM32_2WS_THRESHOLD STM32_VOS1_2WS_THRESHOLD
954#define STM32_3WS_THRESHOLD STM32_VOS1_3WS_THRESHOLD
955#define STM32_4WS_THRESHOLD STM32_VOS1_4WS_THRESHOLD
956#define STM32_5WS_THRESHOLD STM32_VOS1_5WS_THRESHOLD
957#define STM32_6WS_THRESHOLD STM32_VOS1_6WS_THRESHOLD
958#define STM32_7WS_THRESHOLD STM32_VOS1_7WS_THRESHOLD
959#define STM32_8WS_THRESHOLD STM32_VOS1_8WS_THRESHOLD
960#endif /* !STM32_PWR_BOOST */
961
962#elif STM32_VOS == STM32_VOS_RANGE2
963#define STM32_SYSCLK_MAX STM32_VOS2_SYSCLK_MAX
964#define STM32_SYSCLK_MAX_NOBOOST STM32_VOS2_SYSCLK_MAX_NOBOOST
965#define STM32_HSECLK_MAX STM32_VOS2_HSECLK_MAX
966#define STM32_HSECLK_BYP_MAX STM32_VOS2_HSECLK_BYP_MAX
967#define STM32_HSECLK_MIN STM32_VOS2_HSECLK_MIN
968#define STM32_HSECLK_BYP_MIN STM32_VOS2_HSECLK_BYP_MIN
969#define STM32_LSECLK_MAX STM32_VOS2_LSECLK_MAX
970#define STM32_LSECLK_BYP_MAX STM32_VOS2_LSECLK_BYP_MAX
971#define STM32_LSECLK_MIN STM32_VOS2_LSECLK_MIN
972#define STM32_LSECLK_BYP_MIN STM32_VOS2_LSECLK_BYP_MIN
973#define STM32_PLLIN_MAX STM32_VOS2_PLLIN_MAX
974#define STM32_PLLIN_MIN STM32_VOS2_PLLIN_MIN
975#define STM32_PLLVCO_MAX STM32_VOS2_PLLVCO_MAX
976#define STM32_PLLVCO_MIN STM32_VOS2_PLLVCO_MIN
977#define STM32_PLLP_MAX STM32_VOS2_PLLP_MAX
978#define STM32_PLLP_MIN STM32_VOS2_PLLP_MIN
979#define STM32_PLLQ_MAX STM32_VOS2_PLLQ_MAX
980#define STM32_PLLQ_MIN STM32_VOS2_PLLQ_MIN
981#define STM32_PLLR_MAX STM32_VOS2_PLLR_MAX
982#define STM32_PLLR_MIN STM32_VOS2_PLLR_MIN
983#define STM32_PCLK1_MAX STM32_VOS2_PCLK1_MAX
984#define STM32_PCLK2_MAX STM32_VOS2_PCLK2_MAX
985#define STM32_ADCCLK_MAX STM32_VOS2_ADCCLK_MAX
986
987#define STM32_0WS_THRESHOLD STM32_VOS2_0WS_THRESHOLD
988#define STM32_1WS_THRESHOLD STM32_VOS2_1WS_THRESHOLD
989#define STM32_2WS_THRESHOLD STM32_VOS2_2WS_THRESHOLD
990#define STM32_3WS_THRESHOLD STM32_VOS2_3WS_THRESHOLD
991#define STM32_4WS_THRESHOLD STM32_VOS2_4WS_THRESHOLD
992#define STM32_5WS_THRESHOLD STM32_VOS2_5WS_THRESHOLD
993#define STM32_6WS_THRESHOLD STM32_VOS2_6WS_THRESHOLD
994#define STM32_7WS_THRESHOLD STM32_VOS2_7WS_THRESHOLD
995#define STM32_8WS_THRESHOLD STM32_VOS2_8WS_THRESHOLD
996
997#else
998#error "invalid STM32_VOS value specified"
999#endif
1000
1001/*
1002 * HSI16 related checks.
1003 */
1004#if STM32_HSI16_ENABLED
1005#else /* !STM32_HSI16_ENABLED */
1006
1007 #if STM32_SW == STM32_SW_HSI16
1008 #error "HSI16 not enabled, required by STM32_SW"
1009 #endif
1010
1011 #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
1012 #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
1013 #endif
1014
1015 #if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
1016 ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
1017 (STM32_PLLSRC == STM32_PLLSRC_HSI16))
1018 #error "HSI16 not enabled, required by STM32_MCOSEL"
1019 #endif
1020
1021 #if (STM32_USART1SEL == STM32_USART1SEL_HSI16)
1022 #error "HSI16 not enabled, required by STM32_USART1SEL"
1023 #endif
1024 #if (STM32_USART2SEL == STM32_USART2SEL_HSI16)
1025 #error "HSI16 not enabled, required by STM32_USART2SEL"
1026 #endif
1027 #if (STM32_USART3SEL == STM32_USART3SEL_HSI16)
1028 #error "HSI16 not enabled, required by STM32_USART3SEL"
1029 #endif
1030 #if (STM32_UART4SEL == STM32_UART4SEL_HSI16)
1031 #error "HSI16 not enabled, required by STM32_UART4SEL_HSI16"
1032 #endif
1033 #if (STM32_UART5SEL == STM32_UART5SEL_HSI16)
1034 #error "HSI16 not enabled, required by STM32_UART5SEL_HSI16"
1035 #endif
1036 #if (STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16)
1037 #error "HSI16 not enabled, required by STM32_LPUART1SEL"
1038 #endif
1039
1040 #if (STM32_I2C1SEL == STM32_I2C1SEL_HSI16)
1041 #error "HSI16 not enabled, required by STM32_I2C1SEL"
1042 #endif
1043 #if (STM32_I2C2SEL == STM32_I2C2SEL_HSI16)
1044 #error "HSI16 not enabled, required by STM32_I2C2SEL"
1045 #endif
1046 #if (STM32_I2C3SEL == STM32_I2C3SEL_HSI16)
1047 #error "HSI16 not enabled, required by STM32_I2C3SEL"
1048 #endif
1049 #if (STM32_I2C4SEL == STM32_I2C4SEL_HSI16)
1050 #error "HSI16 not enabled, required by STM32_I2C4SEL"
1051 #endif
1052
1053 #if (STM32_SAI1SEL == STM32_SAI1SEL_HSI16)
1054 #error "HSI16 not enabled, required by STM32_SAI1SEL"
1055 #endif
1056 #if (STM32_I2S23SEL == STM32_I2S23SEL_HSI16)
1057 #error "HSI16 not enabled, required by STM32_I2S23SEL"
1058 #endif
1059
1060 #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16)
1061 #error "HSI16 not enabled, required by STM32_LPTIM1SEL"
1062 #endif
1063
1064 #if (STM32_QSPISEL == STM32_QSPISEL_HSI16)
1065 #error "HSI16 not enabled, required by STM32_QSPISEL_HSI16"
1066 #endif
1067
1068#endif /* !STM32_HSI16_ENABLED */
1069
1070/*
1071 * HSI48 related checks.
1072 */
1073#if STM32_HSI48_ENABLED
1074#else /* !STM32_HSI48_ENABLED */
1075
1076 #if STM32_MCOSEL == STM32_MCOSEL_HSI48
1077 #error "HSI48 not enabled, required by STM32_MCOSEL"
1078 #endif
1079
1080 #if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
1081 #error "HSI48 not enabled, required by STM32_CLK48SEL"
1082 #endif
1083
1084#endif /* !STM32_HSI48_ENABLED */
1085
1086/*
1087 * HSE related checks.
1088 */
1089#if STM32_HSE_ENABLED
1090
1091#else /* !STM32_HSE_ENABLED */
1092
1093 #if STM32_SW == STM32_SW_HSE
1094 #error "HSE not enabled, required by STM32_SW"
1095 #endif
1096
1097 #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
1098 #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
1099 #endif
1100
1101 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
1102 ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
1103 (STM32_PLLSRC == STM32_PLLSRC_HSE))
1104 #error "HSE not enabled, required by STM32_MCOSEL"
1105 #endif
1106
1107 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1108 #error "HSE not enabled, required by STM32_RTCSEL"
1109 #endif
1110
1111#endif /* !STM32_HSE_ENABLED */
1112
1113/*
1114 * LSI related checks.
1115 */
1116#if STM32_LSI_ENABLED
1117#else /* !STM32_LSI_ENABLED */
1118
1119 #if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
1120 #error "LSI not enabled, required by STM32_RTCSEL"
1121 #endif
1122
1123 #if STM32_MCOSEL == STM32_MCOSEL_LSI
1124 #error "LSI not enabled, required by STM32_MCOSEL"
1125 #endif
1126
1127 #if STM32_LSCOSEL == STM32_LSCOSEL_LSI
1128 #error "LSI not enabled, required by STM32_LSCOSEL"
1129 #endif
1130
1131#endif /* !STM32_LSI_ENABLED */
1132
1133/*
1134 * LSE related checks.
1135 */
1136#if STM32_LSE_ENABLED
1137
1138 #if (STM32_LSECLK == 0)
1139 #error "LSE frequency not defined"
1140 #endif
1141
1142 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
1143 #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
1144 #endif
1145
1146#else /* !STM32_LSE_ENABLED */
1147
1148 #if STM32_RTCSEL == STM32_RTCSEL_LSE
1149 #error "LSE not enabled, required by STM32_RTCSEL"
1150 #endif
1151
1152 #if STM32_MCOSEL == STM32_MCOSEL_LSE
1153 #error "LSE not enabled, required by STM32_MCOSEL"
1154 #endif
1155
1156 #if STM32_LSCOSEL == STM32_LSCOSEL_LSE
1157 #error "LSE not enabled, required by STM32_LSCOSEL"
1158 #endif
1159
1160#endif /* !STM32_LSE_ENABLED */
1161
1162/**
1163 * @brief STM32_PLLM field.
1164 */
1165#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
1166 defined(__DOXYGEN__)
1167 #define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
1168#else
1169 #error "invalid STM32_PLLM_VALUE value specified"
1170#endif
1171
1172/**
1173 * @brief PLL input clock frequency.
1174 */
1175#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
1176 #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
1177
1178#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
1179 #define STM32_PLLCLKIN (STM32_HSI16CLK / STM32_PLLM_VALUE)
1180
1181#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
1182 #define STM32_PLLCLKIN 0
1183
1184#else
1185 #error "invalid STM32_PLLSRC value specified"
1186#endif
1187
1188/*
1189 * PLL input frequency range check.
1190 */
1191#if (STM32_PLLCLKIN != 0) && \
1192 ((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
1193 #error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
1194#endif
1195
1196/*
1197 * PLL enable check.
1198 */
1199#if (STM32_SW == STM32_SW_PLLRCLK) || \
1200 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
1201 (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
1202 (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
1203 (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
1204 (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
1205 (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
1206 (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
1207 (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
1208 defined(__DOXYGEN__)
1209
1210 #if STM32_PLLCLKIN == 0
1211 #error "PLL activation required but no PLL clock selected"
1212 #endif
1213
1214 /**
1215 * @brief PLL activation flag.
1216 */
1217 #define STM32_ACTIVATE_PLL TRUE
1218#else
1219
1220 #define STM32_ACTIVATE_PLL FALSE
1221#endif
1222
1223/**
1224 * @brief STM32_PLLN field.
1225 */
1226#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
1227 defined(__DOXYGEN__)
1228 #define STM32_PLLN (STM32_PLLN_VALUE << 8)
1229#else
1230 #error "invalid STM32_PLLN_VALUE value specified"
1231#endif
1232
1233/**
1234 * @brief STM32_PLLP field.
1235 */
1236#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
1237 #define STM32_PLLP (0 << 17)
1238
1239#elif STM32_PLLP_VALUE == 17
1240 #define STM32_PLLP (1 << 17)
1241
1242#else
1243 #error "invalid STM32_PLLP_VALUE value specified"
1244#endif
1245
1246/**
1247 * @brief STM32_PLLQ field.
1248 */
1249#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
1250 #define STM32_PLLQ (0 << 21)
1251
1252#elif STM32_PLLQ_VALUE == 4
1253 #define STM32_PLLQ (1 << 21)
1254
1255#elif STM32_PLLQ_VALUE == 6
1256 #define STM32_PLLQ (2 << 21)
1257
1258#elif STM32_PLLQ_VALUE == 8
1259 #define STM32_PLLQ (3 << 21)
1260
1261#else
1262 #error "invalid STM32_PLLQ_VALUE value specified"
1263#endif
1264
1265/**
1266 * @brief STM32_PLLR field.
1267 */
1268#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
1269 #define STM32_PLLR (0 << 25)
1270
1271#elif STM32_PLLR_VALUE == 4
1272 #define STM32_PLLR (1 << 25)
1273
1274#elif STM32_PLLR_VALUE == 6
1275 #define STM32_PLLR (2 << 25)
1276
1277#elif STM32_PLLR_VALUE == 8
1278 #define STM32_PLLR (3 << 25)
1279
1280#else
1281 #error "invalid STM32_PLLR_VALUE value specified"
1282#endif
1283
1284/**
1285 * @brief STM32_PLLPDIV field.
1286 */
1287#if (STM32_PLLPDIV_VALUE == 0) || \
1288 ((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
1289 defined(__DOXYGEN__)
1290#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
1291#else
1292#error "invalid STM32_PLLPDIV_VALUE value specified"
1293#endif
1294
1295/**
1296 * @brief STM32_PLLPEN field.
1297 */
1298#if (STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK) || \
1299 (STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK) || \
1300 defined(__DOXYGEN__)
1301 #define STM32_PLLPEN (1 << 16)
1302
1303#else
1304 #define STM32_PLLPEN (0 << 16)
1305#endif
1306
1307/**
1308 * @brief STM32_PLLQEN field.
1309 */
1310#if (STM32_QSPISEL == STM32_QSPISEL_PLLQCLK) || \
1311 (STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK) || \
1312 (STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK) || \
1313 (STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK) || \
1314 (STM32_I2S23SEL == STM32_I2S23SEL_PLLQCLK) || \
1315 defined(__DOXYGEN__)
1316 #define STM32_PLLQEN (1 << 20)
1317
1318#else
1319 #define STM32_PLLQEN (0 << 20)
1320#endif
1321
1322/**
1323 * @brief STM32_PLLREN field.
1324 */
1325#if (STM32_SW == STM32_SW_PLLRCLK) || \
1326 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
1327 defined(__DOXYGEN__)
1328 #define STM32_PLLREN (1 << 24)
1329
1330#else
1331 #define STM32_PLLREN (0 << 24)
1332#endif
1333
1334/**
1335 * @brief PLL VCO frequency.
1336 */
1337#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
1338
1339/*
1340 * PLL VCO frequency range check.
1341 */
1342#if STM32_ACTIVATE_PLL && \
1343 ((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
1344 #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
1345#endif
1346
1347/**
1348 * @brief PLL P output clock frequency.
1349 */
1350#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
1351 #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
1352#else
1353 #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
1354#endif
1355
1356/**
1357 * @brief PLL Q output clock frequency.
1358 */
1359#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
1360
1361/**
1362 * @brief PLL R output clock frequency.
1363 */
1364#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
1365
1366/*
1367 * PLL-P output frequency range check.
1368 */
1369#if STM32_ACTIVATE_PLL && \
1370 ((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
1371 #error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
1372#endif
1373
1374/*
1375 * PLL-Q output frequency range check.
1376 */
1377#if STM32_ACTIVATE_PLL && \
1378 ((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
1379 #error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
1380#endif
1381
1382/*
1383 * PLL-R output frequency range check.
1384 */
1385#if STM32_ACTIVATE_PLL && \
1386 ((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
1387 #error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
1388#endif
1389
1390/**
1391 * @brief System clock source.
1392 */
1393#if STM32_NO_INIT || defined(__DOXYGEN__)
1394 #define STM32_SYSCLK STM32_HSI16CLK
1395
1396#elif (STM32_SW == STM32_SW_HSI16)
1397 #define STM32_SYSCLK STM32_HSI16CLK
1398
1399#elif (STM32_SW == STM32_SW_HSE)
1400 #define STM32_SYSCLK STM32_HSECLK
1401
1402#elif (STM32_SW == STM32_SW_PLLRCLK)
1403 #define STM32_SYSCLK STM32_PLL_R_CLKOUT
1404
1405#else
1406 #error "invalid STM32_SW value specified"
1407#endif
1408
1409/*
1410 * Check on the system clock.
1411 */
1412#if STM32_SYSCLK > STM32_SYSCLK_MAX
1413 #error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
1414#endif
1415
1416/**
1417 * @brief AHB frequency.
1418 */
1419#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
1420 #define STM32_HCLK (STM32_SYSCLK / 1)
1421
1422#elif STM32_HPRE == STM32_HPRE_DIV2
1423 #define STM32_HCLK (STM32_SYSCLK / 2)
1424
1425#elif STM32_HPRE == STM32_HPRE_DIV4
1426 #define STM32_HCLK (STM32_SYSCLK / 4)
1427
1428#elif STM32_HPRE == STM32_HPRE_DIV8
1429 #define STM32_HCLK (STM32_SYSCLK / 8)
1430
1431#elif STM32_HPRE == STM32_HPRE_DIV16
1432 #define STM32_HCLK (STM32_SYSCLK / 16)
1433
1434#elif STM32_HPRE == STM32_HPRE_DIV64
1435 #define STM32_HCLK (STM32_SYSCLK / 64)
1436
1437#elif STM32_HPRE == STM32_HPRE_DIV128
1438 #define STM32_HCLK (STM32_SYSCLK / 128)
1439
1440#elif STM32_HPRE == STM32_HPRE_DIV256
1441 #define STM32_HCLK (STM32_SYSCLK / 256)
1442
1443#elif STM32_HPRE == STM32_HPRE_DIV512
1444 #define STM32_HCLK (STM32_SYSCLK / 512)
1445
1446#else
1447 #error "invalid STM32_HPRE value specified"
1448#endif
1449
1450/*
1451 * AHB frequency check.
1452 */
1453#if STM32_HCLK > STM32_SYSCLK_MAX
1454 #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
1455#endif
1456
1457/**
1458 * @brief APB1 frequency.
1459 */
1460#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1461 #define STM32_PCLK1 (STM32_HCLK / 1)
1462
1463#elif STM32_PPRE1 == STM32_PPRE1_DIV2
1464 #define STM32_PCLK1 (STM32_HCLK / 2)
1465
1466#elif STM32_PPRE1 == STM32_PPRE1_DIV4
1467 #define STM32_PCLK1 (STM32_HCLK / 4)
1468
1469#elif STM32_PPRE1 == STM32_PPRE1_DIV8
1470 #define STM32_PCLK1 (STM32_HCLK / 8)
1471
1472#elif STM32_PPRE1 == STM32_PPRE1_DIV16
1473 #define STM32_PCLK1 (STM32_HCLK / 16)
1474
1475#else
1476 #error "invalid STM32_PPRE1 value specified"
1477#endif
1478
1479/*
1480 * APB1 frequency check.
1481 */
1482#if STM32_PCLK1 > STM32_PCLK1_MAX
1483#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
1484#endif
1485
1486/**
1487 * @brief APB2 frequency.
1488 */
1489#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1490 #define STM32_PCLK2 (STM32_HCLK / 1)
1491
1492#elif STM32_PPRE2 == STM32_PPRE2_DIV2
1493 #define STM32_PCLK2 (STM32_HCLK / 2)
1494
1495#elif STM32_PPRE2 == STM32_PPRE2_DIV4
1496 #define STM32_PCLK2 (STM32_HCLK / 4)
1497
1498#elif STM32_PPRE2 == STM32_PPRE2_DIV8
1499 #define STM32_PCLK2 (STM32_HCLK / 8)
1500
1501#elif STM32_PPRE2 == STM32_PPRE2_DIV16
1502 #define STM32_PCLK2 (STM32_HCLK / 16)
1503
1504#else
1505 #error "invalid STM32_PPRE2 value specified"
1506#endif
1507
1508/*
1509 * APB2 frequency check.
1510 */
1511#if STM32_PCLK2 > STM32_PCLK2_MAX
1512#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
1513#endif
1514
1515/**
1516 * @brief MCO divider clock frequency.
1517 */
1518#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
1519 #define STM32_MCODIVCLK 0
1520
1521#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
1522 #define STM32_MCODIVCLK STM32_SYSCLK
1523
1524#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
1525 #define STM32_MCODIVCLK STM32_HSI16CLK
1526
1527#elif STM32_MCOSEL == STM32_MCOSEL_HSE
1528 #define STM32_MCODIVCLK STM32_HSECLK
1529
1530#elif STM32_MCOSEL == STM32_MCOSEL_PLLRCLK
1531 #define STM32_MCODIVCLK STM32_PLL_R_CLKOUT
1532
1533#elif STM32_MCOSEL == STM32_MCOSEL_LSI
1534 #define STM32_MCODIVCLK STM32_LSICLK
1535
1536#elif STM32_MCOSEL == STM32_MCOSEL_LSE
1537 #define STM32_MCODIVCLK STM32_LSECLK
1538
1539#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
1540 #define STM32_MCODIVCLK STM32_HSI48CLK
1541
1542#else
1543 #error "invalid STM32_MCOSEL value specified"
1544#endif
1545
1546/**
1547 * @brief MCO output pin clock frequency.
1548 */
1549#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
1550 #define STM32_MCOCLK STM32_MCODIVCLK
1551
1552#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
1553 #define STM32_MCOCLK (STM32_MCODIVCLK / 2)
1554
1555#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
1556 #define STM32_MCOCLK (STM32_MCODIVCLK / 4)
1557
1558#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
1559 #define STM32_MCOCLK (STM32_MCODIVCLK / 8)
1560
1561#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
1562 #define STM32_MCOCLK (STM32_MCODIVCLK / 16)
1563
1564#else
1565#error "invalid STM32_MCOPRE value specified"
1566#endif
1567
1568/**
1569 * @brief RTC clock frequency.
1570 */
1571#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
1572 #define STM32_RTCCLK 0
1573
1574#elif STM32_RTCSEL == STM32_RTCSEL_LSE
1575 #define STM32_RTCCLK STM32_LSECLK
1576
1577#elif STM32_RTCSEL == STM32_RTCSEL_LSI
1578 #define STM32_RTCCLK STM32_LSICLK
1579
1580#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
1581 #define STM32_RTCCLK (STM32_HSECLK / 32)
1582
1583#else
1584 #error "invalid STM32_RTCSEL value specified"
1585#endif
1586
1587/**
1588 * @brief USART1 clock frequency.
1589 */
1590#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
1591 #define STM32_USART1CLK STM32_PCLK2
1592
1593#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
1594 #define STM32_USART1CLK STM32_SYSCLK
1595
1596#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
1597 #define STM32_USART1CLK STM32_HSI16CLK
1598
1599#elif STM32_USART1SEL == STM32_USART1SEL_LSE
1600 #define STM32_USART1CLK STM32_LSECLK
1601
1602#else
1603 #error "invalid source selected for USART1 clock"
1604#endif
1605
1606 /**
1607 * @brief USART2 clock frequency.
1608 */
1609 #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
1610 #define STM32_USART2CLK STM32_PCLK1
1611
1612 #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
1613 #define STM32_USART2CLK STM32_SYSCLK
1614
1615 #elif STM32_USART2SEL == STM32_USART2SEL_HSI16
1616 #define STM32_USART2CLK STM32_HSI16CLK
1617
1618 #elif STM32_USART2SEL == STM32_USART2SEL_LSE
1619 #define STM32_USART2CLK STM32_LSECLK
1620
1621 #else
1622 #error "invalid source selected for USART2 clock"
1623 #endif
1624
1625 /**
1626 * @brief USART3 clock frequency.
1627 */
1628 #if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
1629 #define STM32_USART3CLK STM32_PCLK1
1630
1631 #elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
1632 #define STM32_USART3CLK STM32_SYSCLK
1633
1634 #elif STM32_USART3SEL == STM32_USART3SEL_HSI16
1635 #define STM32_USART3CLK STM32_HSI16CLK
1636
1637 #elif STM32_USART3SEL == STM32_USART3SEL_LSE
1638 #define STM32_USART3CLK STM32_LSECLK
1639
1640 #else
1641 #error "invalid source selected for USART3 clock"
1642 #endif
1643
1644/**
1645 * @brief UART4 clock frequency.
1646 */
1647#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
1648 #define STM32_UART4CLK STM32_PCLK1
1649
1650#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
1651 #define STM32_UART4CLK STM32_SYSCLK
1652
1653#elif STM32_UART4SEL == STM32_UART4SEL_HSI16
1654 #define STM32_UART4CLK STM32_HSI16CLK
1655
1656#elif STM32_UART4SEL == STM32_UART4SEL_LSE
1657 #define STM32_UART4CLK STM32_LSECLK
1658
1659#else
1660 #error "invalid source selected for UART4 clock"
1661#endif
1662
1663/**
1664 * @brief UART5 clock frequency.
1665 */
1666#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
1667 #define STM32_UART5CLK STM32_PCLK1
1668
1669#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
1670 #define STM32_UART5CLK STM32_SYSCLK
1671
1672#elif STM32_UART5SEL == STM32_UART5SEL_HSI16
1673 #define STM32_UART5CLK STM32_HSI16CLK
1674
1675#elif STM32_UART5SEL == STM32_UART5SEL_LSE
1676 #define STM32_UART5CLK STM32_LSECLK
1677
1678#else
1679 #error "invalid source selected for UART5 clock"
1680#endif
1681
1682/**
1683 * @brief LPUART1 clock frequency.
1684 */
1685#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
1686 #define STM32_LPUART1CLK STM32_PCLK1
1687
1688#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
1689 #define STM32_LPUART1CLK STM32_SYSCLK
1690
1691#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
1692 #define STM32_LPUART1CLK STM32_HSI16CLK
1693
1694#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
1695 #define STM32_LPUART1CLK STM32_LSECLK
1696
1697#else
1698#error "invalid source selected for LPUART1 clock"
1699#endif
1700
1701/**
1702 * @brief I2C1 clock frequency.
1703 */
1704#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
1705 #define STM32_I2C1CLK STM32_PCLK1
1706
1707#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
1708 #define STM32_I2C1CLK STM32_SYSCLK
1709
1710#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
1711 #define STM32_I2C1CLK STM32_HSI16CLK
1712
1713#else
1714 #error "invalid source selected for I2C1 clock"
1715#endif
1716
1717/**
1718 * @brief I2C2 clock frequency.
1719 */
1720#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
1721 #define STM32_I2C2CLK STM32_PCLK1
1722
1723#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
1724 #define STM32_I2C2CLK STM32_SYSCLK
1725
1726#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI16
1727 #define STM32_I2C2CLK STM32_HSI16CLK
1728
1729#else
1730 #error "invalid source selected for I2C1 clock"
1731#endif
1732
1733/**
1734 * @brief I2C3 clock frequency.
1735 */
1736#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
1737 #define STM32_I2C3CLK STM32_PCLK1
1738
1739#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
1740 #define STM32_I2C3CLK STM32_SYSCLK
1741
1742#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI16
1743 #define STM32_I2C3CLK STM32_HSI16CLK
1744
1745#else
1746 #error "invalid source selected for I2C3 clock"
1747#endif
1748
1749/**
1750 * @brief I2C4 clock frequency.
1751 */
1752#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
1753 #define STM32_I2C4CLK STM32_PCLK1
1754
1755#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
1756 #define STM32_I2C4CLK STM32_SYSCLK
1757
1758#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI16
1759 #define STM32_I2C4CLK STM32_HSI16CLK
1760
1761#else
1762 #error "invalid source selected for I2C4 clock"
1763#endif
1764
1765/**
1766 * @brief LPTIM1 clock frequency.
1767 */
1768#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
1769 #define STM32_LPTIM1CLK STM32_PCLK1
1770
1771#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
1772 #define STM32_LPTIM1CLK STM32_LSICLK
1773
1774#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
1775 #define STM32_LPTIM1CLK STM32_HSI16CLK
1776
1777#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
1778 #define STM32_LPTIM1CLK STM32_LSECLK
1779
1780#else
1781 #error "invalid source selected for LPTIM1 clock"
1782#endif
1783
1784/**
1785 * @brief SAI1 clock frequency.
1786 */
1787#if (STM32_SAI1SEL == STM32_SAI1SEL_SYSCLK) || defined(__DOXYGEN__)
1788 #define STM32_SAI1CLK STM32_SYSCLK
1789
1790#elif STM32_SAI1SEL == STM32_SAI1SEL_PLLQCLK
1791 #define STM32_SAI1CLK STM32_PLL_Q_CLKOUT
1792
1793#elif STM32_SAI1SEL == STM32_SAI1SEL_HSI16
1794 #define STM32_SAI1CLK STM32_HSI16CLK
1795
1796#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN
1797 #define STM32_SAI1CLK 0 /* Unknown, would require a board value */
1798
1799#else
1800 #error "invalid source selected for SAI1 clock"
1801#endif
1802
1803/**
1804 * @brief I2S23 clock frequency.
1805 */
1806#if (STM32_I2S23SEL == STM32_I2S23SEL_SYSCLK) || defined(__DOXYGEN__)
1807 #define STM32_I2S23CLK STM32_SYSCLK
1808
1809#elif STM32_I2S23SEL == STM32_I2S23SEL_PLLPCLK
1810 #define STM32_I2S23CLK STM32_PLL_P_CLKOUT
1811
1812#elif STM32_I2S23SEL == STM32_I2S23SEL_HSI16
1813 #define STM32_I2S23CLK STM32_HSI16CLK
1814
1815#elif STM32_I2S23SEL == STM32_I2S23SEL_CKIN
1816 #define STM32_I2S23CLK 0 /* Unknown, would require a board value */
1817
1818#else
1819 #error "invalid source selected for SAI1 clock"
1820#endif
1821
1822/**
1823 * @brief FDCAN clock frequency.
1824 */
1825#if (STM32_FDCANSEL == STM32_FDCANSEL_HSE) || defined(__DOXYGEN__)
1826 #define STM32_FDCANCLK STM32_HSECLK
1827
1828#elif STM32_FDCANSEL == STM32_FDCANSEL_PLLQCLK
1829 #define STM32_FDCANCLK STM32_PLL_Q_CLKOUT
1830
1831#elif STM32_FDCANSEL == STM32_FDCANSEL_PCLK1
1832 #define STM32_FDCANCLK STM32_PCLK1
1833
1834#else
1835 #error "invalid source selected for FDCAN clock"
1836#endif
1837
1838/**
1839 * @brief 48MHz clock frequency.
1840 */
1841#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
1842 #define STM32_48CLK STM32_HSI48CLK
1843
1844#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLQCLK
1845 #define STM32_48CLK STM32_PLL_Q_CLKOUT
1846
1847#else
1848 #error "invalid source selected for 48MHz clock"
1849#endif
1850
1851/**
1852 * @brief ADC clock frequency.
1853 */
1854#if (STM32_ADC12SEL == STM32_ADC12SEL_NOCLK) || defined(__DOXYGEN__)
1855 #define STM32_ADC12CLK 0
1856
1857#elif STM32_ADC12SEL == STM32_ADC12SEL_PLLPCLK
1858 #define STM32_ADC12CLK STM32_PLL_P_CLKOUT
1859
1860#elif STM32_ADC12SEL == STM32_ADC12SEL_SYSCLK
1861 #define STM32_ADC12CLK STM32_SYSCLK
1862
1863#else
1864 #error "invalid source selected for ADC clock"
1865#endif
1866
1867/**
1868 * @brief ADC clock frequency.
1869 */
1870#if (STM32_ADC345SEL == STM32_ADC345SEL_NOCLK) || defined(__DOXYGEN__)
1871 #define STM32_ADC345CLK 0
1872
1873#elif STM32_ADC345SEL == STM32_ADC345SEL_PLLPCLK
1874 #define STM32_ADC345CLK STM32_PLL_P_CLKOUT
1875
1876#elif STM32_ADC345SEL == STM32_ADC345SEL_SYSCLK
1877 #define STM32_ADC345CLK STM32_SYSCLK
1878
1879#else
1880 #error "invalid source selected for ADC clock"
1881#endif
1882
1883/**
1884 * @brief TIMP1CLK clock frequency.
1885 */
1886#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
1887 #define STM32_TIMP1CLK (STM32_PCLK1 * 1)
1888#else
1889 #define STM32_TIMP1CLK (STM32_PCLK1 * 2)
1890#endif
1891
1892/**
1893 * @brief TIMP2CLK clock frequency.
1894 */
1895#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
1896 #define STM32_TIMP2CLK (STM32_PCLK2 * 1)
1897#else
1898 #define STM32_TIMP2CLK (STM32_PCLK2 * 2)
1899#endif
1900
1901/**
1902 * @brief Clock of timers connected to APB1.
1903 */
1904#define STM32_TIMCLK1 STM32_TIMP1CLK
1905
1906/**
1907 * @brief Clock of timers connected to APB2.
1908 */
1909#define STM32_TIMCLK2 STM32_TIMP2CLK
1910
1911/**
1912 * @brief RNG clock point.
1913 */
1914#define STM32_RNGCLK STM32_48CLK
1915
1916/**
1917 * @brief USB clock point.
1918 */
1919#define STM32_USBCLK STM32_48CLK
1920
1921/**
1922 * @brief Voltage boost settings.
1923 */
1924#if STM32_PWR_BOOST || defined(__DOXYGEN__)
1925#define STM32_CR5BITS PWR_CR5_R1MODE
1926#else
1927#define STM32_CR5BITS 0U
1928#endif
1929
1930/**
1931 * @brief Flash settings.
1932 */
1933#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
1934 #define STM32_FLASHBITS FLASH_ACR_LATENCY_0WS
1935
1936#elif STM32_HCLK <= STM32_1WS_THRESHOLD
1937 #define STM32_FLASHBITS FLASH_ACR_LATENCY_1WS
1938
1939#elif STM32_HCLK <= STM32_2WS_THRESHOLD
1940 #define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
1941
1942#elif STM32_HCLK <= STM32_3WS_THRESHOLD
1943 #define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
1944
1945#elif STM32_HCLK <= STM32_4WS_THRESHOLD
1946 #define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
1947
1948#else
1949 #define STM32_FLASHBITS FLASH_ACR_LATENCY_5WS
1950#endif
1951
1952/*===========================================================================*/
1953/* Driver data structures and types. */
1954/*===========================================================================*/
1955
1956/*===========================================================================*/
1957/* Driver macros. */
1958/*===========================================================================*/
1959
1960/*===========================================================================*/
1961/* External declarations. */
1962/*===========================================================================*/
1963
1964/* Various helpers.*/
1965#include "nvic.h"
1966#include "cache.h"
1967#include "mpu_v7m.h"
1968#include "stm32_isr.h"
1969#include "stm32_dma.h"
1970#include "stm32_exti.h"
1971#include "stm32_rcc.h"
1972#include "stm32_tim.h"
1973
1974#ifdef __cplusplus
1975extern "C" {
1976#endif
1977 void hal_lld_init(void);
1978 void stm32_clock_init(void);
1979#ifdef __cplusplus
1980}
1981#endif
1982
1983#endif /* HAL_LLD_H */
1984
1985/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/platform.mk b/lib/chibios/os/hal/ports/STM32/STM32G4xx/platform.mk
new file mode 100644
index 000000000..4b3b0db19
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/platform.mk
@@ -0,0 +1,46 @@
1# Required platform files.
2PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
3 $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/stm32_isr.c \
4 $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/hal_lld.c
5
6# Required include directories.
7PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
8 $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx
9
10# Optional platform files.
11ifeq ($(USE_SMART_BUILD),yes)
12
13# Configuration files directory
14ifeq ($(HALCONFDIR),)
15 ifeq ($(CONFDIR),)
16 HALCONFDIR = .
17 else
18 HALCONFDIR := $(CONFDIR)
19 endif
20endif
21
22HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
23
24else
25endif
26
27# Drivers compatible with the platform.
28include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
29include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
30include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
31include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
32include $(CHIBIOS)/os/hal/ports/STM32/LLD/FDCANv1/driver.mk
33include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
34include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
35include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
36include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
37include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
38include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
39include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
40include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
41include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
42include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
43
44# Shared variables
45ALLCSRC += $(PLATFORMSRC)
46ALLINC += $(PLATFORMINC)
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h
new file mode 100644
index 000000000..c8a0ed320
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_dmamux.h
@@ -0,0 +1,183 @@
1/*
2 ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_dmamux.h
19 * @brief STM32G4xx DMAMUX handler header.
20 *
21 * @addtogroup STM32G4xx_DMAMUX
22 * @{
23 */
24
25#ifndef STM32_DMAMUX_H
26#define STM32_DMAMUX_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name DMAMUX1 request sources
34 * @{
35 */
36#define STM32_DMAMUX1_REQ_GEN0 1
37#define STM32_DMAMUX1_REQ_GEN1 2
38#define STM32_DMAMUX1_REQ_GEN2 3
39#define STM32_DMAMUX1_REQ_GEN3 4
40#define STM32_DMAMUX1_ADC1 5
41#define STM32_DMAMUX1_DAC1_CH1 6
42#define STM32_DMAMUX1_DAC1_CH2 7
43#define STM32_DMAMUX1_TIM6_UP 8
44#define STM32_DMAMUX1_TIM7_UP 9
45#define STM32_DMAMUX1_SPI1_RX 10
46#define STM32_DMAMUX1_SPI1_TX 11
47#define STM32_DMAMUX1_SPI2_RX 12
48#define STM32_DMAMUX1_SPI2_TX 13
49#define STM32_DMAMUX1_SPI3_RX 14
50#define STM32_DMAMUX1_SPI3_TX 15
51#define STM32_DMAMUX1_I2C1_RX 16
52#define STM32_DMAMUX1_I2C1_TX 17
53#define STM32_DMAMUX1_I2C2_RX 18
54#define STM32_DMAMUX1_I2C2_TX 19
55#define STM32_DMAMUX1_I2C3_RX 20
56#define STM32_DMAMUX1_I2C3_TX 21
57#define STM32_DMAMUX1_I2C4_RX 22
58#define STM32_DMAMUX1_I2C4_TX 23
59#define STM32_DMAMUX1_USART1_RX 24
60#define STM32_DMAMUX1_USART1_TX 25
61#define STM32_DMAMUX1_USART2_RX 26
62#define STM32_DMAMUX1_USART2_TX 27
63#define STM32_DMAMUX1_USART3_RX 28
64#define STM32_DMAMUX1_USART3_TX 29
65#define STM32_DMAMUX1_UART4_RX 30
66#define STM32_DMAMUX1_UART4_TX 31
67#define STM32_DMAMUX1_UART5_RX 32
68#define STM32_DMAMUX1_UART5_TX 33
69#define STM32_DMAMUX1_LPUART1_RX 34
70#define STM32_DMAMUX1_LPUART1_TX 35
71#define STM32_DMAMUX1_ADC2 36
72#define STM32_DMAMUX1_ADC3 37
73#define STM32_DMAMUX1_ADC4 38
74#define STM32_DMAMUX1_ADC5 39
75#define STM32_DMAMUX1_QUADSPI 40
76#define STM32_DMAMUX1_DAC2_CH1 41
77#define STM32_DMAMUX1_TIM1_CH1 42
78#define STM32_DMAMUX1_TIM1_CH2 43
79#define STM32_DMAMUX1_TIM1_CH3 44
80#define STM32_DMAMUX1_TIM1_CH4 45
81#define STM32_DMAMUX1_TIM1_UP 46
82#define STM32_DMAMUX1_TIM1_TRIG 47
83#define STM32_DMAMUX1_TIM1_COM 48
84#define STM32_DMAMUX1_TIM8_CH1 49
85#define STM32_DMAMUX1_TIM8_CH2 50
86#define STM32_DMAMUX1_TIM8_CH3 51
87#define STM32_DMAMUX1_TIM8_CH4 52
88#define STM32_DMAMUX1_TIM8_UP 53
89#define STM32_DMAMUX1_TIM8_TRIG 54
90#define STM32_DMAMUX1_TIM8_COM 55
91#define STM32_DMAMUX1_TIM2_CH1 56
92#define STM32_DMAMUX1_TIM2_CH2 57
93#define STM32_DMAMUX1_TIM2_CH3 58
94#define STM32_DMAMUX1_TIM2_CH4 59
95#define STM32_DMAMUX1_TIM2_UP 60
96#define STM32_DMAMUX1_TIM3_CH1 61
97#define STM32_DMAMUX1_TIM3_CH2 62
98#define STM32_DMAMUX1_TIM3_CH3 63
99#define STM32_DMAMUX1_TIM3_CH4 64
100#define STM32_DMAMUX1_TIM3_UP 65
101#define STM32_DMAMUX1_TIM3_TRIG 66
102#define STM32_DMAMUX1_TIM4_CH1 67
103#define STM32_DMAMUX1_TIM4_CH2 68
104#define STM32_DMAMUX1_TIM4_CH3 69
105#define STM32_DMAMUX1_TIM4_CH4 70
106#define STM32_DMAMUX1_TIM4_UP 71
107#define STM32_DMAMUX1_TIM5_CH1 72
108#define STM32_DMAMUX1_TIM5_CH2 73
109#define STM32_DMAMUX1_TIM5_CH3 74
110#define STM32_DMAMUX1_TIM5_CH4 75
111#define STM32_DMAMUX1_TIM5_UP 76
112#define STM32_DMAMUX1_TIM5_TRIG 77
113#define STM32_DMAMUX1_TIM15_CH1 78
114#define STM32_DMAMUX1_TIM15_UP 79
115#define STM32_DMAMUX1_TIM15_TRIG 80
116#define STM32_DMAMUX1_TIM15_COM 81
117#define STM32_DMAMUX1_TIM16_CH1 82
118#define STM32_DMAMUX1_TIM16_UP 83
119#define STM32_DMAMUX1_TIM17_CH1 84
120#define STM32_DMAMUX1_TIM17_UP 85
121#define STM32_DMAMUX1_TIM20_CH1 86
122#define STM32_DMAMUX1_TIM20_CH2 87
123#define STM32_DMAMUX1_TIM20_CH3 88
124#define STM32_DMAMUX1_TIM20_CH4 89
125#define STM32_DMAMUX1_TIM20_UP 90
126#define STM32_DMAMUX1_AES_IN 91
127#define STM32_DMAMUX1_AES_OUT 92
128#define STM32_DMAMUX1_TIM20_TRIG 93
129#define STM32_DMAMUX1_TIM20_COM 94
130#define STM32_DMAMUX1_HRTIM_MASTER 95
131#define STM32_DMAMUX1_HRTIM_TIMA 96
132#define STM32_DMAMUX1_HRTIM_TIMB 97
133#define STM32_DMAMUX1_HRTIM_TIMC 98
134#define STM32_DMAMUX1_HRTIM_TIMD 99
135#define STM32_DMAMUX1_HRTIM_TIME 100
136#define STM32_DMAMUX1_HRTIM_TIMF 101
137#define STM32_DMAMUX1_DAC3_CH1 102
138#define STM32_DMAMUX1_DAC3_CH2 103
139#define STM32_DMAMUX1_DAC4_CH1 104
140#define STM32_DMAMUX1_DAC4_CH2 105
141#define STM32_DMAMUX1_SPI4_RX 106
142#define STM32_DMAMUX1_SPI4_TX 107
143#define STM32_DMAMUX1_SAI1_A 108
144#define STM32_DMAMUX1_SAI1_B 109
145#define STM32_DMAMUX1_FMAC_READ 110
146#define STM32_DMAMUX1_FMAC_WRITE 111
147#define STM32_DMAMUX1_CORDIC_READ 112
148#define STM32_DMAMUX1_CORDIC_WRITE 113
149#define STM32_DMAMUX1_UCPD1_RX 114
150#define STM32_DMAMUX1_UCPD1_TX 115
151/** @} */
152
153/*===========================================================================*/
154/* Driver pre-compile time settings. */
155/*===========================================================================*/
156
157/*===========================================================================*/
158/* Derived constants and error checks. */
159/*===========================================================================*/
160
161/*===========================================================================*/
162/* Driver data structures and types. */
163/*===========================================================================*/
164
165/*===========================================================================*/
166/* Driver macros. */
167/*===========================================================================*/
168
169/*===========================================================================*/
170/* External declarations. */
171/*===========================================================================*/
172
173#ifdef __cplusplus
174extern "C" {
175#endif
176
177#ifdef __cplusplus
178}
179#endif
180
181#endif /* STM32_DMAMUX_H */
182
183/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.c b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.c
new file mode 100644
index 000000000..53c0de59e
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.c
@@ -0,0 +1,183 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_isr.c
19 * @brief STM32G4xx ISR handler code.
20 *
21 * @addtogroup STM32G4xx_ISR
22 * @{
23 */
24
25#include "hal.h"
26
27/*===========================================================================*/
28/* Driver local definitions. */
29/*===========================================================================*/
30
31#define exti_serve_irq(pr, channel) { \
32 \
33 if ((pr) & (1U << (channel))) { \
34 _pal_isr_code(channel); \
35 } \
36}
37
38/*===========================================================================*/
39/* Driver exported variables. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Driver local variables. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Driver local functions. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Driver interrupt handlers. */
52/*===========================================================================*/
53
54#include "stm32_exti0.inc"
55#include "stm32_exti1.inc"
56#include "stm32_exti2.inc"
57#include "stm32_exti3.inc"
58#include "stm32_exti4.inc"
59#include "stm32_exti5_9.inc"
60#include "stm32_exti10_15.inc"
61#include "stm32_exti16-40_41.inc"
62#include "stm32_exti17.inc"
63#include "stm32_exti18.inc"
64#include "stm32_exti19.inc"
65#include "stm32_exti20.inc"
66#include "stm32_exti21_22-29.inc"
67#include "stm32_exti30_32.inc"
68#include "stm32_exti33.inc"
69
70#include "stm32_fdcan1.inc"
71#include "stm32_fdcan2.inc"
72#include "stm32_fdcan3.inc"
73
74#include "stm32_usart1.inc"
75#include "stm32_usart2.inc"
76#include "stm32_usart3.inc"
77#include "stm32_uart4.inc"
78#include "stm32_uart5.inc"
79#include "stm32_lpuart1.inc"
80
81#include "stm32_tim1_15_16_17.inc"
82#include "stm32_tim2.inc"
83#include "stm32_tim3.inc"
84#include "stm32_tim4.inc"
85#include "stm32_tim5.inc"
86#include "stm32_tim6.inc"
87#include "stm32_tim7.inc"
88#include "stm32_tim8.inc"
89#include "stm32_tim20.inc"
90
91/*===========================================================================*/
92/* Driver exported functions. */
93/*===========================================================================*/
94
95/**
96 * @brief Enables IRQ sources.
97 *
98 * @notapi
99 */
100void irqInit(void) {
101
102 exti0_irq_init();
103 exti1_irq_init();
104 exti2_irq_init();
105 exti3_irq_init();
106 exti4_irq_init();
107 exti5_9_irq_init();
108 exti10_15_irq_init();
109 exti16_exti40_exti41_irq_init();
110 exti17_irq_init();
111 exti18_irq_init();
112 exti19_irq_init();
113 exti21_exti22_exti29_irq_init();
114 exti30_32_irq_init();
115 exti33_irq_init();
116
117 fdcan1_irq_init();
118 fdcan2_irq_init();
119 fdcan3_irq_init();
120
121 tim1_tim15_tim16_tim17_irq_init();
122 tim2_irq_init();
123 tim3_irq_init();
124 tim4_irq_init();
125 tim5_irq_init();
126 tim6_irq_init();
127 tim7_irq_init();
128 tim8_irq_init();
129 tim20_irq_init();
130
131 usart1_irq_init();
132 usart2_irq_init();
133 usart3_irq_init();
134 uart4_irq_init();
135 uart5_irq_init();
136 lpuart1_irq_init();
137}
138
139/**
140 * @brief Disables IRQ sources.
141 *
142 * @notapi
143 */
144void irqDeinit(void) {
145
146 exti0_irq_deinit();
147 exti1_irq_deinit();
148 exti2_irq_deinit();
149 exti3_irq_deinit();
150 exti4_irq_deinit();
151 exti5_9_irq_deinit();
152 exti10_15_irq_deinit();
153 exti16_exti40_exti41_irq_deinit();
154 exti17_irq_deinit();
155 exti18_irq_deinit();
156 exti19_irq_deinit();
157 exti21_exti22_exti29_irq_deinit();
158 exti30_32_irq_deinit();
159 exti33_irq_deinit();
160
161 fdcan1_irq_deinit();
162 fdcan2_irq_deinit();
163 fdcan3_irq_deinit();
164
165 tim1_tim15_tim16_tim17_irq_deinit();
166 tim2_irq_deinit();
167 tim3_irq_deinit();
168 tim4_irq_deinit();
169 tim5_irq_deinit();
170 tim6_irq_deinit();
171 tim7_irq_deinit();
172 tim8_irq_deinit();
173 tim20_irq_deinit();
174
175 usart1_irq_deinit();
176 usart2_irq_deinit();
177 usart3_irq_deinit();
178 uart4_irq_deinit();
179 uart5_irq_deinit();
180 lpuart1_irq_deinit();
181}
182
183/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.h b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.h
new file mode 100644
index 000000000..d1dfdd066
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_isr.h
@@ -0,0 +1,298 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_isr.h
19 * @brief STM32G4xx ISR handler header.
20 *
21 * @addtogroup STM32G4xx_ISR
22 * @{
23 */
24
25#ifndef STM32_ISR_H
26#define STM32_ISR_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name ISRs suppressed in standard drivers
34 * @{
35 */
36#define STM32_TIM1_SUPPRESS_ISR
37#define STM32_TIM2_SUPPRESS_ISR
38#define STM32_TIM3_SUPPRESS_ISR
39#define STM32_TIM4_SUPPRESS_ISR
40#define STM32_TIM5_SUPPRESS_ISR
41#define STM32_TIM6_SUPPRESS_ISR
42#define STM32_TIM7_SUPPRESS_ISR
43#define STM32_TIM8_SUPPRESS_ISR
44#define STM32_TIM15_SUPPRESS_ISR
45#define STM32_TIM16_SUPPRESS_ISR
46#define STM32_TIM17_SUPPRESS_ISR
47#define STM32_TIM20_SUPPRESS_ISR
48
49#define STM32_USART1_SUPPRESS_ISR
50#define STM32_USART2_SUPPRESS_ISR
51#define STM32_USART3_SUPPRESS_ISR
52#define STM32_UART4_SUPPRESS_ISR
53#define STM32_UART5_SUPPRESS_ISR
54#define STM32_LPUART1_SUPPRESS_ISR
55/** @} */
56
57/**
58 * @name ISR names and numbers
59 * @{
60 */
61/*
62 * ADC unit.
63 */
64#define STM32_ADC1_HANDLER Vector88
65#define STM32_ADC2_HANDLER Vector88
66#define STM32_ADC3_HANDLER VectorFC
67#define STM32_ADC4_HANDLER Vector134
68#define STM32_ADC5_HANDLER Vector138
69
70#define STM32_ADC1_NUMBER 18
71#define STM32_ADC2_NUMBER 18
72#define STM32_ADC3_NUMBER 47
73#define STM32_ADC4_NUMBER 61
74#define STM32_ADC5_NUMBER 62
75
76/*
77 * DMA unit.
78 */
79#define STM32_DMA1_CH1_HANDLER Vector6C
80#define STM32_DMA1_CH2_HANDLER Vector70
81#define STM32_DMA1_CH3_HANDLER Vector74
82#define STM32_DMA1_CH4_HANDLER Vector78
83#define STM32_DMA1_CH5_HANDLER Vector7C
84#define STM32_DMA1_CH6_HANDLER Vector80
85#if !defined(STM32G431xx) && !defined(STM32G441xx)
86#define STM32_DMA1_CH7_HANDLER Vector84
87#define STM32_DMA1_CH8_HANDLER Vector1C0
88#endif
89#define STM32_DMA2_CH1_HANDLER Vector120
90#define STM32_DMA2_CH2_HANDLER Vector124
91#define STM32_DMA2_CH3_HANDLER Vector128
92#define STM32_DMA2_CH4_HANDLER Vector12C
93#define STM32_DMA2_CH5_HANDLER Vector130
94#define STM32_DMA2_CH6_HANDLER Vector1C4
95#if !defined(STM32G431xx) && !defined(STM32G441xx)
96#define STM32_DMA2_CH7_HANDLER Vector1C8
97#define STM32_DMA2_CH8_HANDLER Vector1CC
98#endif
99
100#define STM32_DMA1_CH1_NUMBER 11
101#define STM32_DMA1_CH2_NUMBER 12
102#define STM32_DMA1_CH3_NUMBER 13
103#define STM32_DMA1_CH4_NUMBER 14
104#define STM32_DMA1_CH5_NUMBER 15
105#define STM32_DMA1_CH6_NUMBER 16
106#if !defined(STM32G431xx) && !defined(STM32G441xx)
107#define STM32_DMA1_CH7_NUMBER 17
108#define STM32_DMA1_CH8_NUMBER 96
109#endif
110#define STM32_DMA2_CH1_NUMBER 56
111#define STM32_DMA2_CH2_NUMBER 57
112#define STM32_DMA2_CH3_NUMBER 58
113#define STM32_DMA2_CH4_NUMBER 59
114#define STM32_DMA2_CH5_NUMBER 60
115#define STM32_DMA2_CH6_NUMBER 97
116#if !defined(STM32G431xx) && !defined(STM32G441xx)
117#define STM32_DMA2_CH7_NUMBER 98
118#define STM32_DMA2_CH8_NUMBER 99
119#endif
120
121/*
122 * EXTI unit.
123 */
124#define STM32_EXTI0_HANDLER Vector58
125#define STM32_EXTI1_HANDLER Vector5C
126#define STM32_EXTI2_HANDLER Vector60
127#define STM32_EXTI3_HANDLER Vector64
128#define STM32_EXTI4_HANDLER Vector68
129#define STM32_EXTI5_9_HANDLER Vector9C
130#define STM32_EXTI10_15_HANDLER VectorE0
131#define STM32_EXTI164041_HANDLER Vector44 /* PVD PVM */
132#define STM32_EXTI17_HANDLER VectorE4 /* RTC ALARM */
133#define STM32_EXTI18_HANDLER VectorE8 /* USB WAKEUP */
134#define STM32_EXTI19_HANDLER Vector48 /* RTC TAMP CSS */
135#define STM32_EXTI20_HANDLER Vector4C /* RTC WAKEUP */
136#define STM32_EXTI212229_HANDLER Vector140 /* COMP1..3 */
137#define STM32_EXTI30_32_HANDLER Vector144 /* COMP4..6 */
138#define STM32_EXTI33_HANDLER Vector148 /* COMP7 */
139
140#define STM32_EXTI0_NUMBER 6
141#define STM32_EXTI1_NUMBER 7
142#define STM32_EXTI2_NUMBER 8
143#define STM32_EXTI3_NUMBER 9
144#define STM32_EXTI4_NUMBER 10
145#define STM32_EXTI5_9_NUMBER 23
146#define STM32_EXTI10_15_NUMBER 40
147#define STM32_EXTI164041_NUMBER 1
148#define STM32_EXTI17_NUMBER 41
149#define STM32_EXTI18_NUMBER 42
150#define STM32_EXTI19_NUMBER 2
151#define STM32_EXTI20_NUMBER 3
152#define STM32_EXTI212229_NUMBER 64
153#define STM32_EXTI30_32_NUMBER 65
154#define STM32_EXTI33_NUMBER 66
155
156/*
157 * FDCAN units.
158 */
159#define STM32_FDCAN1_IT0_HANDLER Vector94
160#define STM32_FDCAN1_IT1_HANDLER Vector98
161#define STM32_FDCAN2_IT0_HANDLER Vector198
162#define STM32_FDCAN2_IT1_HANDLER Vector19C
163#define STM32_FDCAN3_IT0_HANDLER Vector1A0
164#define STM32_FDCAN3_IT1_HANDLER Vector1A4
165
166#define STM32_FDCAN1_IT0_NUMBER 21
167#define STM32_FDCAN1_IT1_NUMBER 22
168#define STM32_FDCAN2_IT0_NUMBER 86
169#define STM32_FDCAN2_IT1_NUMBER 87
170#define STM32_FDCAN3_IT0_NUMBER 88
171#define STM32_FDCAN3_IT1_NUMBER 89
172
173/*
174 * I2C units.
175 */
176#define STM32_I2C1_EVENT_HANDLER VectorBC
177#define STM32_I2C1_ERROR_HANDLER VectorC0
178#define STM32_I2C2_EVENT_HANDLER VectorC4
179#define STM32_I2C2_ERROR_HANDLER VectorC8
180#define STM32_I2C3_EVENT_HANDLER Vector1B0
181#define STM32_I2C3_ERROR_HANDLER Vector1B4
182#define STM32_I2C4_EVENT_HANDLER Vector188
183#define STM32_I2C4_ERROR_HANDLER Vector18C
184
185#define STM32_I2C1_EVENT_NUMBER 31
186#define STM32_I2C1_ERROR_NUMBER 32
187#define STM32_I2C2_EVENT_NUMBER 33
188#define STM32_I2C2_ERROR_NUMBER 34
189#define STM32_I2C3_EVENT_NUMBER 92
190#define STM32_I2C3_ERROR_NUMBER 93
191#define STM32_I2C4_EVENT_NUMBER 82
192#define STM32_I2C4_ERROR_NUMBER 83
193
194/*
195 * QUADSPI unit.
196 */
197#define STM32_QUADSPI1_HANDLER Vector1BC
198#define STM32_QUADSPI1_NUMBER 95
199
200/*
201 * TIM units.
202 */
203#define STM32_TIM1_BRK_TIM15_HANDLER VectorA0
204#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
205#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
206#define STM32_TIM1_CC_HANDLER VectorAC
207#define STM32_TIM2_HANDLER VectorB0
208#define STM32_TIM3_HANDLER VectorB4
209#define STM32_TIM4_HANDLER VectorB8
210#define STM32_TIM5_HANDLER Vector108
211#define STM32_TIM6_HANDLER Vector118
212#define STM32_TIM7_HANDLER Vector11C
213#define STM32_TIM8_BRK_HANDLER VectorEC
214#define STM32_TIM8_UP_HANDLER VectorF0
215#define STM32_TIM8_TRGCO_HANDLER VectorF4
216#define STM32_TIM8_CC_HANDLER VectorF8
217#define STM32_TIM20_BRK_HANDLER Vector174
218#define STM32_TIM20_UP_HANDLER Vector178
219#define STM32_TIM20_TRGCO_HANDLER Vector17C
220#define STM32_TIM20_CC_HANDLER Vector180
221
222#define STM32_TIM1_BRK_TIM15_NUMBER 24
223#define STM32_TIM1_UP_TIM16_NUMBER 25
224#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
225#define STM32_TIM1_CC_NUMBER 27
226#define STM32_TIM2_NUMBER 28
227#define STM32_TIM3_NUMBER 29
228#define STM32_TIM4_NUMBER 30
229#define STM32_TIM5_NUMBER 50
230#define STM32_TIM6_NUMBER 54
231#define STM32_TIM7_NUMBER 55
232#define STM32_TIM8_BRK_NUMBER 43
233#define STM32_TIM8_UP_NUMBER 44
234#define STM32_TIM8_TRGCO_NUMBER 45
235#define STM32_TIM8_CC_NUMBER 46
236#define STM32_TIM20_BRK_NUMBER 77
237#define STM32_TIM20_UP_NUMBER 78
238#define STM32_TIM20_TRGCO_NUMBER 79
239#define STM32_TIM20_CC_NUMBER 80
240
241/*
242 * USART/UART units.
243 */
244#define STM32_USART1_HANDLER VectorD4
245#define STM32_USART2_HANDLER VectorD8
246#define STM32_USART3_HANDLER VectorDC
247#define STM32_UART4_HANDLER Vector110
248#define STM32_UART5_HANDLER Vector114
249#define STM32_LPUART1_HANDLER Vector1AC
250
251#define STM32_USART1_NUMBER 37
252#define STM32_USART2_NUMBER 38
253#define STM32_USART3_NUMBER 39
254#define STM32_UART4_NUMBER 52
255#define STM32_UART5_NUMBER 53
256#define STM32_LPUART1_NUMBER 91
257
258/*
259 * USB units.
260 */
261#define STM32_USB1_HP_HANDLER Vector8C
262#define STM32_USB1_LP_HANDLER Vector90
263#define STM32_USB1_HP_NUMBER 19
264#define STM32_USB1_LP_NUMBER 20
265/** @} */
266
267/*===========================================================================*/
268/* Driver pre-compile time settings. */
269/*===========================================================================*/
270
271/*===========================================================================*/
272/* Derived constants and error checks. */
273/*===========================================================================*/
274
275/*===========================================================================*/
276/* Driver data structures and types. */
277/*===========================================================================*/
278
279/*===========================================================================*/
280/* Driver macros. */
281/*===========================================================================*/
282
283/*===========================================================================*/
284/* External declarations. */
285/*===========================================================================*/
286
287#ifdef __cplusplus
288extern "C" {
289#endif
290 void irqInit(void);
291 void irqDeinit(void);
292#ifdef __cplusplus
293}
294#endif
295
296#endif /* STM32_ISR_H */
297
298/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h
new file mode 100644
index 000000000..ba79dd899
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_rcc.h
@@ -0,0 +1,1366 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32g4xx.h.
22 *
23 * @addtogroup STM32G4xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
55 *
56 * @param[in] mask APB1 R1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1R1(mask, lp) { \
62 RCC->APB1ENR1 |= (mask); \
63 if (lp) \
64 RCC->APB1SMENR1 |= (mask); \
65 else \
66 RCC->APB1SMENR1 &= ~(mask); \
67 (void)RCC->APB1SMENR1; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
72 *
73 * @param[in] mask APB1 R1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1R1(mask) { \
78 RCC->APB1ENR1 &= ~(mask); \
79 RCC->APB1SMENR1 &= ~(mask); \
80 (void)RCC->APB1SMENR1; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus (R1).
85 *
86 * @param[in] mask APB1 R1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1R1(mask) { \
91 RCC->APB1RSTR1 |= (mask); \
92 RCC->APB1RSTR1 &= ~(mask); \
93 (void)RCC->APB1RSTR1; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
98 *
99 * @param[in] mask APB1 R2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB1R2(mask, lp) { \
105 RCC->APB1ENR2 |= (mask); \
106 if (lp) \
107 RCC->APB1SMENR2 |= (mask); \
108 else \
109 RCC->APB1SMENR2 &= ~(mask); \
110 (void)RCC->APB1SMENR2; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
115 *
116 * @param[in] mask APB1 R2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB1R2(mask) { \
121 RCC->APB1ENR2 &= ~(mask); \
122 RCC->APB1SMENR2 &= ~(mask); \
123 (void)RCC->APB1SMENR2; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB1 bus (R2).
128 *
129 * @param[in] mask APB1 R2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB1R2(mask) { \
134 RCC->APB1RSTR2 |= (mask); \
135 RCC->APB1RSTR2 &= ~(mask); \
136 (void)RCC->APB1RSTR2; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the APB2 bus.
141 *
142 * @param[in] mask APB2 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAPB2(mask, lp) { \
148 RCC->APB2ENR |= (mask); \
149 if (lp) \
150 RCC->APB2SMENR |= (mask); \
151 else \
152 RCC->APB2SMENR &= ~(mask); \
153 (void)RCC->APB2SMENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the APB2 bus.
158 *
159 * @param[in] mask APB2 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAPB2(mask) { \
164 RCC->APB2ENR &= ~(mask); \
165 RCC->APB2SMENR &= ~(mask); \
166 (void)RCC->APB2SMENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the APB2 bus.
171 *
172 * @param[in] mask APB2 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAPB2(mask) { \
177 RCC->APB2RSTR |= (mask); \
178 RCC->APB2RSTR &= ~(mask); \
179 (void)RCC->APB2RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
184 *
185 * @param[in] mask AHB1 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB1(mask, lp) { \
191 RCC->AHB1ENR |= (mask); \
192 if (lp) \
193 RCC->AHB1SMENR |= (mask); \
194 else \
195 RCC->AHB1SMENR &= ~(mask); \
196 (void)RCC->AHB1SMENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
201 *
202 * @param[in] mask AHB1 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB1(mask) { \
207 RCC->AHB1ENR &= ~(mask); \
208 RCC->AHB1SMENR &= ~(mask); \
209 (void)RCC->AHB1SMENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB1 bus.
214 *
215 * @param[in] mask AHB1 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB1(mask) { \
220 RCC->AHB1RSTR |= (mask); \
221 RCC->AHB1RSTR &= ~(mask); \
222 (void)RCC->AHB1RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
227 *
228 * @param[in] mask AHB2 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB2(mask, lp) { \
234 RCC->AHB2ENR |= (mask); \
235 if (lp) \
236 RCC->AHB2SMENR |= (mask); \
237 else \
238 RCC->AHB2SMENR &= ~(mask); \
239 (void)RCC->AHB2SMENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
244 *
245 * @param[in] mask AHB2 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB2(mask) { \
250 RCC->AHB2ENR &= ~(mask); \
251 RCC->AHB2SMENR &= ~(mask); \
252 (void)RCC->AHB2SMENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB2 bus.
257 *
258 * @param[in] mask AHB2 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB2(mask) { \
263 RCC->AHB2RSTR |= (mask); \
264 RCC->AHB2RSTR &= ~(mask); \
265 (void)RCC->AHB2RSTR; \
266}
267
268/**
269 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
270 *
271 * @param[in] mask AHB3 peripherals mask
272 * @param[in] lp low power enable flag
273 *
274 * @api
275 */
276#define rccEnableAHB3(mask, lp) { \
277 RCC->AHB3ENR |= (mask); \
278 if (lp) \
279 RCC->AHB3SMENR |= (mask); \
280 else \
281 RCC->AHB3SMENR &= ~(mask); \
282 (void)RCC->AHB3SMENR; \
283}
284
285/**
286 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
287 *
288 * @param[in] mask AHB3 peripherals mask
289 *
290 * @api
291 */
292#define rccDisableAHB3(mask) { \
293 RCC->AHB3ENR &= ~(mask); \
294 RCC->AHB3SMENR &= ~(mask); \
295 (void)RCC->AHB3SMENR; \
296}
297
298/**
299 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
300 *
301 * @param[in] mask AHB3 peripherals mask
302 *
303 * @api
304 */
305#define rccResetAHB3(mask) { \
306 RCC->AHB3RSTR |= (mask); \
307 RCC->AHB3RSTR &= ~(mask); \
308 (void)RCC->AHB3RSTR; \
309}
310/** @} */
311
312/**
313 * @name ADC peripherals specific RCC operations
314 * @{
315 */
316/**
317 * @brief Enables the ADC1/ADC2 peripheral clock.
318 *
319 * @param[in] lp low power enable flag
320 *
321 * @api
322 */
323#define rccEnableADC12(lp) rccEnableAHB2(RCC_AHB2ENR_ADC12EN, lp)
324
325/**
326 * @brief Disables the ADC1/ADC2 peripheral clock.
327 *
328 * @api
329 */
330#define rccDisableADC12() rccDisableAHB2(RCC_AHB2ENR_ADC12EN)
331
332/**
333 * @brief Resets the ADC1/ADC2 peripheral.
334 *
335 * @api
336 */
337#define rccResetADC12() rccResetAHB2(RCC_AHB2RSTR_ADC12RST)
338
339/**
340 * @brief Enables the ADC3/ADC4/ADC5 peripheral clock.
341 *
342 * @param[in] lp low power enable flag
343 *
344 * @api
345 */
346#define rccEnableADC345(lp) rccEnableAHB2(RCC_AHB2ENR_ADC345EN, lp)
347
348/**
349 * @brief Disables the ADC3/ADC4/ADC5 peripheral clock.
350 *
351 * @api
352 */
353#define rccDisableADC345() rccDisableAHB2(RCC_AHB2ENR_ADC345EN)
354
355/**
356 * @brief Resets the ADC3/ADC4/ADC5 peripheral.
357 *
358 * @api
359 */
360#define rccResetADC345() rccResetAHB2(RCC_AHB2RSTR_ADC345RST)
361/** @} */
362
363/**
364 * @name DAC peripheral specific RCC operations
365 * @{
366 */
367/**
368 * @brief Enables the DAC1 peripheral clock.
369 *
370 * @param[in] lp low power enable flag
371 *
372 * @api
373 */
374#define rccEnableDAC1(lp) rccEnableAHB2(RCC_AHB2ENR_DAC1EN, lp)
375
376/**
377 * @brief Disables the DAC1 peripheral clock.
378 *
379 * @api
380 */
381#define rccDisableDAC1() rccDisableAHB2(RCC_AHB2ENR_DAC1EN)
382
383/**
384 * @brief Resets the DAC1 peripheral.
385 *
386 * @api
387 */
388#define rccResetDAC1() rccResetAHB2(RCC_AHB2RSTR_DAC1RST)
389
390/**
391 * @brief Enables the DAC2 peripheral clock.
392 *
393 * @param[in] lp low power enable flag
394 *
395 * @api
396 */
397#define rccEnableDAC2(lp) rccEnableAHB2(RCC_AHB2ENR_DAC2EN, lp)
398
399/**
400 * @brief Disables the DAC2 peripheral clock.
401 *
402 * @api
403 */
404#define rccDisableDAC2() rccDisableAHB2(RCC_AHB2ENR_DAC2EN)
405
406/**
407 * @brief Resets the DAC2 peripheral.
408 *
409 * @api
410 */
411#define rccResetDAC2() rccResetAHB2(RCC_AHB2RSTR_DAC2RST)
412
413/**
414 * @brief Enables the DAC3 peripheral clock.
415 *
416 * @param[in] lp low power enable flag
417 *
418 * @api
419 */
420#define rccEnableDAC3(lp) rccEnableAHB2(RCC_AHB2ENR_DAC3EN, lp)
421
422/**
423 * @brief Disables the DAC3 peripheral clock.
424 *
425 * @api
426 */
427#define rccDisableDAC3() rccDisableAHB2(RCC_AHB2ENR_DAC3EN)
428
429/**
430 * @brief Resets the DAC3 peripheral.
431 *
432 * @api
433 */
434#define rccResetDAC3() rccResetAHB2(RCC_AHB2RSTR_DAC3RST)
435
436/**
437 * @brief Enables the DAC4 peripheral clock.
438 *
439 * @param[in] lp low power enable flag
440 *
441 * @api
442 */
443#define rccEnableDAC4(lp) rccEnableAHB2(RCC_AHB2ENR_DAC4EN, lp)
444
445/**
446 * @brief Disables the DAC4 peripheral clock.
447 *
448 * @api
449 */
450#define rccDisableDAC4() rccDisableAHB2(RCC_AHB2ENR_DAC4EN)
451
452/**
453 * @brief Resets the DAC4 peripheral.
454 *
455 * @api
456 */
457#define rccResetDAC4() rccResetAHB2(RCC_AHB2RSTR_DAC4RST)
458/** @} */
459
460/**
461 * @name DMA peripheral specific RCC operations
462 * @{
463 */
464/**
465 * @brief Enables the DMA1 peripheral clock.
466 *
467 * @param[in] lp low power enable flag
468 *
469 * @api
470 */
471#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
472
473/**
474 * @brief Disables the DMA1 peripheral clock.
475 *
476 * @api
477 */
478#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
479
480/**
481 * @brief Resets the DMA1 peripheral.
482 *
483 * @api
484 */
485#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
486
487/**
488 * @brief Enables the DMA2 peripheral clock.
489 *
490 * @param[in] lp low power enable flag
491 *
492 * @api
493 */
494#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
495
496/**
497 * @brief Disables the DMA2 peripheral clock.
498 *
499 * @api
500 */
501#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
502
503/**
504 * @brief Resets the DMA2 peripheral.
505 *
506 * @api
507 */
508#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
509/** @} */
510
511/**
512 * @name DMAMUX peripheral specific RCC operations
513 * @{
514 */
515/**
516 * @brief Enables the DMAMUX peripheral clock.
517 *
518 * @param[in] lp low power enable flag
519 *
520 * @api
521 */
522#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
523
524/**
525 * @brief Disables the DMAMUX peripheral clock.
526 *
527 * @api
528 */
529#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
530
531/**
532 * @brief Resets the DMAMUX peripheral.
533 *
534 * @api
535 */
536#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
537/** @} */
538
539/**
540 * @name FDCAN peripherals specific RCC operations
541 * @{
542 */
543/**
544 * @brief Enables the FDCAN peripheral clock.
545 *
546 * @param[in] lp low power enable flag
547 *
548 * @api
549 */
550#define rccEnableFDCAN(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
551
552/**
553 * @brief Disables the FDCAN peripheral clock.
554 *
555 * @api
556 */
557#define rccDisableFDCAN() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
558
559/**
560 * @brief Resets the FDCAN peripheral.
561 *
562 * @api
563 */
564#define rccResetFDCAN() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
565/** @} */
566
567/**
568 * @name PWR interface specific RCC operations
569 * @{
570 */
571/**
572 * @brief Enables the PWR interface clock.
573 *
574 * @param[in] lp low power enable flag
575 *
576 * @api
577 */
578#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
579
580/**
581 * @brief Disables PWR interface clock.
582 *
583 * @api
584 */
585#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
586
587/**
588 * @brief Resets the PWR interface.
589 *
590 * @api
591 */
592#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
593/** @} */
594
595/**
596 * @name FDCAN peripherals specific RCC operations
597 * @{
598 */
599/**
600 * @brief Enables the FDCAN1 peripheral clock.
601 *
602 * @param[in] lp low power enable flag
603 *
604 * @api
605 */
606#define rccEnableFDCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
607
608/**
609 * @brief Disables the FDCAN1 peripheral clock.
610 *
611 * @api
612 */
613#define rccDisableFDCAN1() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
614
615/**
616 * @brief Resets the FDCAN1 peripheral.
617 *
618 * @api
619 */
620#define rccResetFDCAN1() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
621/** @} */
622
623/**
624 * @name I2C peripherals specific RCC operations
625 * @{
626 */
627/**
628 * @brief Enables the I2C1 peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
635
636/**
637 * @brief Disables the I2C1 peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
642
643/**
644 * @brief Resets the I2C1 peripheral.
645 *
646 * @api
647 */
648#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
649
650/**
651 * @brief Enables the I2C2 peripheral clock.
652 *
653 * @param[in] lp low power enable flag
654 *
655 * @api
656 */
657#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
658
659/**
660 * @brief Disables the I2C2 peripheral clock.
661 *
662 * @api
663 */
664#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
665
666/**
667 * @brief Resets the I2C2 peripheral.
668 *
669 * @api
670 */
671#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
672
673/**
674 * @brief Enables the I2C3 peripheral clock.
675 *
676 * @param[in] lp low power enable flag
677 *
678 * @api
679 */
680#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
681
682/**
683 * @brief Disables the I2C3 peripheral clock.
684 *
685 * @api
686 */
687#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
688
689/**
690 * @brief Resets the I2C3 peripheral.
691 *
692 * @api
693 */
694#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
695
696/**
697 * @brief Enables the I2C4 peripheral clock.
698 *
699 * @param[in] lp low power enable flag
700 *
701 * @api
702 */
703#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
704
705/**
706 * @brief Disables the I2C4 peripheral clock.
707 *
708 * @api
709 */
710#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
711
712/**
713 * @brief Resets the I2C4 peripheral.
714 *
715 * @api
716 */
717#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
718/** @} */
719
720/**
721 * @name QUADSPI peripherals specific RCC operations
722 * @{
723 */
724/**
725 * @brief Enables the QUADSPI1 peripheral clock.
726 *
727 * @param[in] lp low power enable flag
728 *
729 * @api
730 */
731#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
732
733/**
734 * @brief Disables the QUADSPI1 peripheral clock.
735 *
736 * @api
737 */
738#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
739
740/**
741 * @brief Resets the QUADSPI1 peripheral.
742 *
743 * @api
744 */
745#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
746/** @} */
747
748/**
749 * @name RNG peripherals specific RCC operations
750 * @{
751 */
752/**
753 * @brief Enables the RNG peripheral clock.
754 *
755 * @param[in] lp low power enable flag
756 *
757 * @api
758 */
759#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
760
761/**
762 * @brief Disables the RNG peripheral clock.
763 *
764 * @api
765 */
766#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
767
768/**
769 * @brief Resets the RNG peripheral.
770 *
771 * @api
772 */
773#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
774/** @} */
775
776/**
777 * @name SPI peripherals specific RCC operations
778 * @{
779 */
780/**
781 * @brief Enables the SPI1 peripheral clock.
782 *
783 * @param[in] lp low power enable flag
784 *
785 * @api
786 */
787#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
788
789/**
790 * @brief Disables the SPI1 peripheral clock.
791 *
792 * @api
793 */
794#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
795
796/**
797 * @brief Resets the SPI1 peripheral.
798 *
799 * @api
800 */
801#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
802
803/**
804 * @brief Enables the SPI2 peripheral clock.
805 *
806 * @param[in] lp low power enable flag
807 *
808 * @api
809 */
810#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
811
812/**
813 * @brief Disables the SPI2 peripheral clock.
814 *
815 * @api
816 */
817#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
818
819/**
820 * @brief Resets the SPI2 peripheral.
821 *
822 * @api
823 */
824#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
825
826/**
827 * @brief Enables the SPI3 peripheral clock.
828 *
829 * @param[in] lp low power enable flag
830 *
831 * @api
832 */
833#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
834
835/**
836 * @brief Disables the SPI3 peripheral clock.
837 *
838 * @api
839 */
840#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
841
842/**
843 * @brief Resets the SPI3 peripheral.
844 *
845 * @api
846 */
847#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
848
849/**
850 * @brief Enables the SPI4 peripheral clock.
851 *
852 * @param[in] lp low power enable flag
853 *
854 * @api
855 */
856#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
857
858/**
859 * @brief Disables the SPI4 peripheral clock.
860 *
861 * @api
862 */
863#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
864
865/**
866 * @brief Resets the SPI4 peripheral.
867 *
868 * @api
869 */
870#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
871/** @} */
872
873/**
874 * @name TIM peripherals specific RCC operations
875 * @{
876 */
877/**
878 * @brief Enables the TIM1 peripheral clock.
879 *
880 * @param[in] lp low power enable flag
881 *
882 * @api
883 */
884#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
885
886/**
887 * @brief Disables the TIM1 peripheral clock.
888 *
889 * @api
890 */
891#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
892
893/**
894 * @brief Resets the TIM1 peripheral.
895 *
896 * @api
897 */
898#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
899
900/**
901 * @brief Enables the TIM2 peripheral clock.
902 *
903 * @param[in] lp low power enable flag
904 *
905 * @api
906 */
907#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
908
909/**
910 * @brief Disables the TIM2 peripheral clock.
911 *
912 * @api
913 */
914#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
915
916/**
917 * @brief Resets the TIM2 peripheral.
918 *
919 * @api
920 */
921#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
922
923/**
924 * @brief Enables the TIM3 peripheral clock.
925 *
926 * @param[in] lp low power enable flag
927 *
928 * @api
929 */
930#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
931
932/**
933 * @brief Disables the TIM3 peripheral clock.
934 *
935 * @api
936 */
937#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
938
939/**
940 * @brief Resets the TIM3 peripheral.
941 *
942 * @api
943 */
944#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
945
946/**
947 * @brief Enables the TIM4 peripheral clock.
948 *
949 * @param[in] lp low power enable flag
950 *
951 * @api
952 */
953#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
954
955/**
956 * @brief Disables the TIM4 peripheral clock.
957 *
958 * @api
959 */
960#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
961
962/**
963 * @brief Resets the TIM4 peripheral.
964 *
965 * @api
966 */
967#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
968
969/**
970 * @brief Enables the TIM5 peripheral clock.
971 *
972 * @param[in] lp low power enable flag
973 *
974 * @api
975 */
976#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
977
978/**
979 * @brief Disables the TIM5 peripheral clock.
980 *
981 * @api
982 */
983#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
984
985/**
986 * @brief Resets the TIM5 peripheral.
987 *
988 * @api
989 */
990#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
991
992/**
993 * @brief Enables the TIM6 peripheral clock.
994 *
995 * @param[in] lp low power enable flag
996 *
997 * @api
998 */
999#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
1000
1001/**
1002 * @brief Disables the TIM6 peripheral clock.
1003 *
1004 * @api
1005 */
1006#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
1007
1008/**
1009 * @brief Resets the TIM6 peripheral.
1010 *
1011 * @api
1012 */
1013#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
1014
1015/**
1016 * @brief Enables the TIM7 peripheral clock.
1017 *
1018 * @param[in] lp low power enable flag
1019 *
1020 * @api
1021 */
1022#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
1023
1024/**
1025 * @brief Disables the TIM7 peripheral clock.
1026 *
1027 * @api
1028 */
1029#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
1030
1031/**
1032 * @brief Resets the TIM7 peripheral.
1033 *
1034 * @api
1035 */
1036#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
1037
1038/**
1039 * @brief Enables the TIM8 peripheral clock.
1040 *
1041 * @param[in] lp low power enable flag
1042 *
1043 * @api
1044 */
1045#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1046
1047/**
1048 * @brief Disables the TIM8 peripheral clock.
1049 *
1050 * @api
1051 */
1052#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1053
1054/**
1055 * @brief Resets the TIM8 peripheral.
1056 *
1057 * @api
1058 */
1059#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1060
1061/**
1062 * @brief Enables the TIM15 peripheral clock.
1063 *
1064 * @param[in] lp low power enable flag
1065 *
1066 * @api
1067 */
1068#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
1069
1070/**
1071 * @brief Disables the TIM15 peripheral clock.
1072 *
1073 * @api
1074 */
1075#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
1076
1077/**
1078 * @brief Resets the TIM15 peripheral.
1079 *
1080 * @api
1081 */
1082#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
1083
1084/**
1085 * @brief Enables the TIM16 peripheral clock.
1086 *
1087 * @param[in] lp low power enable flag
1088 *
1089 * @api
1090 */
1091#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
1092
1093/**
1094 * @brief Disables the TIM16 peripheral clock.
1095 *
1096 * @api
1097 */
1098#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
1099
1100/**
1101 * @brief Resets the TIM16 peripheral.
1102 *
1103 * @api
1104 */
1105#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
1106
1107/**
1108 * @brief Enables the TIM17 peripheral clock.
1109 *
1110 * @param[in] lp low power enable flag
1111 *
1112 * @api
1113 */
1114#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
1115
1116/**
1117 * @brief Disables the TIM17 peripheral clock.
1118 *
1119 * @api
1120 */
1121#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
1122
1123/**
1124 * @brief Resets the TIM17 peripheral.
1125 *
1126 * @api
1127 */
1128#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
1129
1130/**
1131 * @brief Enables the TIM20 peripheral clock.
1132 *
1133 * @param[in] lp low power enable flag
1134 *
1135 * @api
1136 */
1137#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
1138
1139/**
1140 * @brief Disables the TIM20 peripheral clock.
1141 *
1142 * @api
1143 */
1144#define rccDisableTIM20() rccDisableAPB2(RCC_APB2ENR_TIM20EN)
1145
1146/**
1147 * @brief Resets the TIM20 peripheral.
1148 *
1149 * @api
1150 */
1151#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
1152/** @} */
1153
1154/**
1155 * @name USART/UART peripherals specific RCC operations
1156 * @{
1157 */
1158/**
1159 * @brief Enables the USART1 peripheral clock.
1160 *
1161 * @param[in] lp low power enable flag
1162 *
1163 * @api
1164 */
1165#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1166
1167/**
1168 * @brief Disables the USART1 peripheral clock.
1169 *
1170 * @api
1171 */
1172#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1173
1174/**
1175 * @brief Resets the USART1 peripheral.
1176 *
1177 * @api
1178 */
1179#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1180
1181/**
1182 * @brief Enables the USART2 peripheral clock.
1183 *
1184 * @param[in] lp low power enable flag
1185 *
1186 * @api
1187 */
1188#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
1189
1190/**
1191 * @brief Disables the USART2 peripheral clock.
1192 *
1193 * @api
1194 */
1195#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
1196
1197/**
1198 * @brief Resets the USART2 peripheral.
1199 *
1200 * @api
1201 */
1202#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
1203
1204/**
1205 * @brief Enables the USART3 peripheral clock.
1206 *
1207 * @param[in] lp low power enable flag
1208 *
1209 * @api
1210 */
1211#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
1212
1213/**
1214 * @brief Disables the USART3 peripheral clock.
1215 *
1216 * @api
1217 */
1218#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
1219
1220/**
1221 * @brief Resets the USART3 peripheral.
1222 *
1223 * @api
1224 */
1225#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
1226
1227/**
1228 * @brief Enables the UART4 peripheral clock.
1229 *
1230 * @param[in] lp low power enable flag
1231 *
1232 * @api
1233 */
1234#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
1235
1236/**
1237 * @brief Disables the UART4 peripheral clock.
1238 *
1239 * @api
1240 */
1241#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
1242
1243/**
1244 * @brief Resets the UART4 peripheral.
1245 *
1246 * @api
1247 */
1248#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
1249
1250/**
1251 * @brief Enables the UART5 peripheral clock.
1252 *
1253 * @param[in] lp low power enable flag
1254 *
1255 * @api
1256 */
1257#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
1258
1259/**
1260 * @brief Disables the UART5 peripheral clock.
1261 *
1262 * @api
1263 */
1264#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
1265
1266/**
1267 * @brief Resets the UART5 peripheral.
1268 *
1269 * @api
1270 */
1271#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
1272
1273/**
1274 * @brief Enables the LPUART1 peripheral clock.
1275 *
1276 * @param[in] lp low power enable flag
1277 *
1278 * @api
1279 */
1280#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
1281
1282/**
1283 * @brief Disables the LPUART1 peripheral clock.
1284 *
1285 * @api
1286 */
1287#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
1288
1289/**
1290 * @brief Resets the USART1 peripheral.
1291 *
1292 * @api
1293 */
1294#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
1295/** @} */
1296
1297/**
1298 * @name USB peripheral specific RCC operations
1299 * @{
1300 */
1301/**
1302 * @brief Enables the USB peripheral clock.
1303 *
1304 * @param[in] lp low power enable flag
1305 *
1306 * @api
1307 */
1308#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp)
1309
1310/**
1311 * @brief Disables the USB peripheral clock.
1312 *
1313 * @api
1314 */
1315#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN)
1316
1317/**
1318 * @brief Resets the USB peripheral.
1319 *
1320 * @api
1321 */
1322#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST)
1323/** @} */
1324
1325/**
1326 * @name CRC peripheral specific RCC operations
1327 * @{
1328 */
1329/**
1330 * @brief Enables the CRC peripheral clock.
1331 *
1332 * @param[in] lp low power enable flag
1333 *
1334 * @api
1335 */
1336#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1337
1338/**
1339 * @brief Disables the CRC peripheral clock.
1340 *
1341 * @api
1342 */
1343#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1344
1345/**
1346 * @brief Resets the CRC peripheral.
1347 *
1348 * @api
1349 */
1350#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1351/** @} */
1352
1353/*===========================================================================*/
1354/* External declarations. */
1355/*===========================================================================*/
1356
1357#ifdef __cplusplus
1358extern "C" {
1359#endif
1360#ifdef __cplusplus
1361}
1362#endif
1363
1364#endif /* STM32_RCC_H */
1365
1366/** @} */
diff --git a/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_registry.h b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_registry.h
new file mode 100644
index 000000000..b9dd413da
--- /dev/null
+++ b/lib/chibios/os/hal/ports/STM32/STM32G4xx/stm32_registry.h
@@ -0,0 +1,524 @@
1/*
2 ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_registry.h
19 * @brief STM32G4xx capabilities registry.
20 *
21 * @addtogroup HAL
22 * @{
23 */
24
25#ifndef STM32_REGISTRY_H
26#define STM32_REGISTRY_H
27
28/*===========================================================================*/
29/* Platform capabilities. */
30/*===========================================================================*/
31
32/**
33 * @name STM32G4xx capabilities
34 * @{
35 */
36
37/*===========================================================================*/
38/* Common. */
39/*===========================================================================*/
40
41/* RNG attributes.*/
42#define STM32_HAS_RNG1 TRUE
43
44/* RTC attributes.*/
45#define STM32_HAS_RTC TRUE
46#define STM32_RTC_HAS_SUBSECONDS TRUE
47#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
48#define STM32_RTC_NUM_ALARMS 2
49#define STM32_RTC_STORAGE_SIZE 128
50#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
51#define STM32_RTC_WKUP_HANDLER Vector4C
52#define STM32_RTC_ALARM_HANDLER VectorE4
53#define STM32_RTC_TAMP_STAMP_NUMBER 2
54#define STM32_RTC_WKUP_NUMBER 3
55#define STM32_RTC_ALARM_NUMBER 41
56#define STM32_RTC_ALARM_EXTI 18
57#define STM32_RTC_TAMP_STAMP_EXTI 19
58#define STM32_RTC_WKUP_EXTI 20
59#define STM32_RTC_IRQ_ENABLE() do { \
60 nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
61 nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
62 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
63} while (false)
64
65 /* Enabling RTC-related EXTI lines.*/
66#define STM32_RTC_ENABLE_ALL_EXTI() do { \
67 extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
68 EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
69 EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
70 EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
71} while (false)
72
73/* Clearing EXTI interrupts. */
74#define STM32_RTC_CLEAR_ALL_EXTI() do { \
75 extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
76 EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
77 EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
78} while (false)
79
80/* Masks used to preserve state of RTC and TAMP register reserved bits. */
81#define STM32_RTC_CR_MASK 0xE7FFFF7F
82#define STM32_RTC_PRER_MASK 0x007F7FFF
83#define STM32_TAMP_CR1_MASK 0x003C0007
84#define STM32_TAMP_CR2_MASK 0x07070007
85#define STM32_TAMP_FLTCR_MASK 0x000000FF
86#define STM32_TAMP_IER_MASK 0x003C0007
87
88#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
89 defined(__DOXYGEN__)
90#define STM32_HAS_HASH1 TRUE
91#define STM32_HAS_CRYP1 TRUE
92#else
93#define STM32_HAS_HASH1 FALSE
94#define STM32_HAS_CRYP1 FALSE
95#endif
96
97/*===========================================================================*/
98/* STM32G473xx, STM32G4843xx, STM32G474xx, STM32G484xx. */
99/*===========================================================================*/
100
101#if defined(STM32G473xx) || defined(STM32G483xx) || \
102 defined(STM32G474xx) || defined(STM32G484xx) || \
103 defined(__DOXYGEN__)
104
105/* ADC attributes.*/
106#define STM32_HAS_ADC1 TRUE
107#define STM32_HAS_ADC2 TRUE
108#define STM32_HAS_ADC3 TRUE
109#define STM32_HAS_ADC4 TRUE
110#define STM32_HAS_ADC5 TRUE
111
112/* CAN attributes.*/
113#define STM32_HAS_FDCAN1 TRUE
114#define STM32_HAS_FDCAN2 TRUE
115#define STM32_HAS_FDCAN3 TRUE
116#define STM32_FDCAN_FLS_NBR 28U
117#define STM32_FDCAN_FLE_NBR 8U
118#define STM32_FDCAN_RF0_NBR 3U
119#define STM32_FDCAN_RF1_NBR 3U
120#define STM32_FDCAN_RB_NBR 0U
121#define STM32_FDCAN_TEF_NBR 3U
122#define STM32_FDCAN_TB_NBR 3U
123#define STM32_FDCAN_TM_NBR 0U
124
125/* DAC attributes.*/
126#define STM32_HAS_DAC1_CH1 TRUE
127#define STM32_HAS_DAC1_CH2 TRUE
128#define STM32_HAS_DAC2_CH1 TRUE
129#define STM32_HAS_DAC2_CH2 FALSE
130#define STM32_HAS_DAC3_CH1 TRUE
131#define STM32_HAS_DAC3_CH2 TRUE
132#define STM32_HAS_DAC4_CH1 TRUE
133#define STM32_HAS_DAC4_CH2 TRUE
134
135/* DMA attributes.*/
136#define STM32_ADVANCED_DMA TRUE
137#define STM32_DMA_SUPPORTS_DMAMUX TRUE
138#define STM32_DMA_SUPPORTS_CSELR FALSE
139#define STM32_DMA1_NUM_CHANNELS 8
140#define STM32_DMA2_NUM_CHANNELS 8
141
142/* ETH attributes.*/
143#define STM32_HAS_ETH FALSE
144
145/* EXTI attributes.*/
146#define STM32_EXTI_HAS_CR FALSE
147#define STM32_EXTI_SEPARATE_RF FALSE
148#define STM32_EXTI_NUM_LINES 44
149#define STM32_EXTI_IMR1_MASK 0x1F840000U
150#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
151
152
153/* Flash attributes.*/
154#define STM32_FLASH_NUMBER_OF_BANKS 2
155
156/* GPIO attributes.*/
157#define STM32_HAS_GPIOA TRUE
158#define STM32_HAS_GPIOB TRUE
159#define STM32_HAS_GPIOC TRUE
160#define STM32_HAS_GPIOD TRUE
161#define STM32_HAS_GPIOE TRUE
162#define STM32_HAS_GPIOF TRUE
163#define STM32_HAS_GPIOG TRUE
164#define STM32_HAS_GPIOH FALSE
165#define STM32_HAS_GPIOI FALSE
166#define STM32_HAS_GPIOJ FALSE
167#define STM32_HAS_GPIOK FALSE
168#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
169 RCC_AHB2ENR_GPIOBEN | \
170 RCC_AHB2ENR_GPIOCEN | \
171 RCC_AHB2ENR_GPIODEN | \
172 RCC_AHB2ENR_GPIOEEN | \
173 RCC_AHB2ENR_GPIOFEN | \
174 RCC_AHB2ENR_GPIOGEN)
175
176/* I2C attributes.*/
177#define STM32_HAS_I2C1 TRUE
178#define STM32_HAS_I2C2 TRUE
179#define STM32_HAS_I2C3 TRUE
180#define STM32_HAS_I2C4 TRUE
181
182/* OCTOSPI attributes.*/
183#define STM32_HAS_OCTOSPI1 FALSE
184#define STM32_HAS_OCTOSPI2 FALSE
185
186/* QUADSPI attributes.*/
187#define STM32_HAS_QUADSPI1 TRUE
188
189/* SDMMC attributes.*/
190#define STM32_HAS_SDMMC1 FALSE
191#define STM32_HAS_SDMMC2 FALSE
192
193/* SPI attributes.*/
194#define STM32_HAS_SPI1 TRUE
195#define STM32_SPI1_SUPPORTS_I2S FALSE
196
197#define STM32_HAS_SPI2 TRUE
198#define STM32_SPI2_SUPPORTS_I2S TRUE
199
200#define STM32_HAS_SPI3 TRUE
201#define STM32_SPI3_SUPPORTS_I2S TRUE
202
203#define STM32_HAS_SPI4 TRUE
204#define STM32_SPI4_SUPPORTS_I2S FALSE
205
206#define STM32_HAS_SPI5 FALSE
207#define STM32_HAS_SPI6 FALSE
208
209/* TIM attributes.*/
210#define STM32_TIM_MAX_CHANNELS 6
211
212#define STM32_HAS_TIM1 TRUE
213#define STM32_TIM1_IS_32BITS FALSE
214#define STM32_TIM1_CHANNELS 6
215
216#define STM32_HAS_TIM2 TRUE
217#define STM32_TIM2_IS_32BITS TRUE
218#define STM32_TIM2_CHANNELS 4
219
220#define STM32_HAS_TIM3 TRUE
221#define STM32_TIM3_IS_32BITS FALSE
222#define STM32_TIM3_CHANNELS 4
223
224#define STM32_HAS_TIM4 TRUE
225#define STM32_TIM4_IS_32BITS FALSE
226#define STM32_TIM4_CHANNELS 4
227
228#define STM32_HAS_TIM5 TRUE
229#define STM32_TIM5_IS_32BITS TRUE
230#define STM32_TIM5_CHANNELS 4
231
232#define STM32_HAS_TIM6 TRUE
233#define STM32_TIM6_IS_32BITS FALSE
234#define STM32_TIM6_CHANNELS 0
235
236#define STM32_HAS_TIM7 TRUE
237#define STM32_TIM7_IS_32BITS FALSE
238#define STM32_TIM7_CHANNELS 0
239
240#define STM32_HAS_TIM8 TRUE
241#define STM32_TIM8_IS_32BITS FALSE
242#define STM32_TIM8_CHANNELS 6
243
244#define STM32_HAS_TIM15 TRUE
245#define STM32_TIM15_IS_32BITS FALSE
246#define STM32_TIM15_CHANNELS 2
247
248#define STM32_HAS_TIM16 TRUE
249#define STM32_TIM16_IS_32BITS FALSE
250#define STM32_TIM16_CHANNELS 1
251
252#define STM32_HAS_TIM17 TRUE
253#define STM32_TIM17_IS_32BITS FALSE
254#define STM32_TIM17_CHANNELS 1
255
256#define STM32_HAS_TIM20 TRUE
257#define STM32_TIM20_IS_32BITS FALSE
258#define STM32_TIM20_CHANNELS 6
259
260#define STM32_HAS_TIM9 FALSE
261#define STM32_HAS_TIM10 FALSE
262#define STM32_HAS_TIM11 FALSE
263#define STM32_HAS_TIM12 FALSE
264#define STM32_HAS_TIM13 FALSE
265#define STM32_HAS_TIM14 FALSE
266#define STM32_HAS_TIM18 FALSE
267#define STM32_HAS_TIM19 FALSE
268#define STM32_HAS_TIM21 FALSE
269#define STM32_HAS_TIM22 FALSE
270
271/* USART attributes.*/
272#define STM32_HAS_USART1 TRUE
273#define STM32_HAS_USART2 TRUE
274#define STM32_HAS_USART3 TRUE
275#define STM32_HAS_UART4 TRUE
276#define STM32_HAS_UART5 TRUE
277#define STM32_HAS_LPUART1 TRUE
278#define STM32_HAS_USART6 FALSE
279#define STM32_HAS_UART7 FALSE
280#define STM32_HAS_UART8 FALSE
281
282/* OTG/USB attributes.*/
283#define STM32_HAS_OTG1 FALSE
284#define STM32_HAS_OTG2 FALSE
285
286#define STM32_HAS_USB TRUE
287#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
288#define STM32_USB_PMA_SIZE 1024
289#define STM32_USB_HAS_BCDR TRUE
290
291/* IWDG attributes.*/
292#define STM32_HAS_IWDG TRUE
293#define STM32_IWDG_IS_WINDOWED TRUE
294
295/* LTDC attributes.*/
296#define STM32_HAS_LTDC FALSE
297
298/* DMA2D attributes.*/
299#define STM32_HAS_DMA2D FALSE
300
301/* FSMC attributes.*/
302#define STM32_HAS_FSMC FALSE
303
304/* CRC attributes.*/
305#define STM32_HAS_CRC TRUE
306#define STM32_CRC_PROGRAMMABLE TRUE
307
308/* DCMI attributes.*/
309#define STM32_HAS_DCMI FALSE
310
311#endif /* defined(STM32G474xx) || defined(STM32G484xx) */
312
313/*===========================================================================*/
314/* STM32G431xx, STM32G441xx, STM32G471xx. */
315/*===========================================================================*/
316
317#if defined(STM32G431xx) || defined(STM32G441xx) || \
318 defined(__DOXYGEN__)
319
320/* ADC attributes.*/
321#define STM32_HAS_ADC1 TRUE
322#define STM32_HAS_ADC2 TRUE
323#define STM32_HAS_ADC3 FALSE
324#define STM32_HAS_ADC4 FALSE
325#define STM32_HAS_ADC5 FALSE
326
327/* CAN attributes.*/
328#define STM32_HAS_FDCAN1 TRUE
329#define STM32_HAS_FDCAN2 FALSE
330#define STM32_HAS_FDCAN3 FALSE
331#define STM32_FDCAN_FLS_NBR 28U
332#define STM32_FDCAN_FLE_NBR 8U
333#define STM32_FDCAN_RF0_NBR 3U
334#define STM32_FDCAN_RF1_NBR 3U
335#define STM32_FDCAN_RB_NBR 0U
336#define STM32_FDCAN_TEF_NBR 3U
337#define STM32_FDCAN_TB_NBR 3U
338#define STM32_FDCAN_TM_NBR 0U
339
340/* DAC attributes.*/
341#define STM32_HAS_DAC1_CH1 TRUE
342#define STM32_HAS_DAC1_CH2 TRUE
343#define STM32_HAS_DAC2_CH1 FALSE
344#define STM32_HAS_DAC2_CH2 FALSE
345#define STM32_HAS_DAC3_CH1 TRUE
346#define STM32_HAS_DAC3_CH2 TRUE
347#define STM32_HAS_DAC4_CH1 FALSE
348#define STM32_HAS_DAC4_CH2 FALSE
349
350/* DMA attributes.*/
351#define STM32_ADVANCED_DMA TRUE
352#define STM32_DMA_SUPPORTS_DMAMUX TRUE
353#define STM32_DMA_SUPPORTS_CSELR FALSE
354#define STM32_DMA1_NUM_CHANNELS 6
355#define STM32_DMA2_NUM_CHANNELS 6
356
357/* ETH attributes.*/
358#define STM32_HAS_ETH FALSE
359
360/* EXTI attributes.*/
361#define STM32_EXTI_HAS_CR FALSE
362#define STM32_EXTI_SEPARATE_RF FALSE
363#define STM32_EXTI_NUM_LINES 44
364#define STM32_EXTI_IMR1_MASK 0x1F840000U
365#define STM32_EXTI_IMR2_MASK 0xFFFFFF3CU
366
367
368/* Flash attributes.*/
369#define STM32_FLASH_NUMBER_OF_BANKS 2
370
371/* GPIO attributes.*/
372#define STM32_HAS_GPIOA TRUE
373#define STM32_HAS_GPIOB TRUE
374#define STM32_HAS_GPIOC TRUE
375#define STM32_HAS_GPIOD TRUE
376#define STM32_HAS_GPIOE TRUE
377#define STM32_HAS_GPIOF TRUE
378#define STM32_HAS_GPIOG TRUE
379#define STM32_HAS_GPIOH FALSE
380#define STM32_HAS_GPIOI FALSE
381#define STM32_HAS_GPIOJ FALSE
382#define STM32_HAS_GPIOK FALSE
383#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
384 RCC_AHB2ENR_GPIOBEN | \
385 RCC_AHB2ENR_GPIOCEN | \
386 RCC_AHB2ENR_GPIODEN | \
387 RCC_AHB2ENR_GPIOEEN | \
388 RCC_AHB2ENR_GPIOFEN | \
389 RCC_AHB2ENR_GPIOGEN)
390
391/* I2C attributes.*/
392#define STM32_HAS_I2C1 TRUE
393#define STM32_HAS_I2C2 TRUE
394#define STM32_HAS_I2C3 TRUE
395#define STM32_HAS_I2C4 FALSE
396
397/* OCTOSPI attributes.*/
398#define STM32_HAS_OCTOSPI1 FALSE
399#define STM32_HAS_OCTOSPI2 FALSE
400
401/* QUADSPI attributes.*/
402#define STM32_HAS_QUADSPI1 FALSE
403
404/* SDMMC attributes.*/
405#define STM32_HAS_SDMMC1 FALSE
406#define STM32_HAS_SDMMC2 FALSE
407
408/* SPI attributes.*/
409#define STM32_HAS_SPI1 TRUE
410#define STM32_SPI1_SUPPORTS_I2S FALSE
411
412#define STM32_HAS_SPI2 TRUE
413#define STM32_SPI2_SUPPORTS_I2S TRUE
414
415#define STM32_HAS_SPI3 TRUE
416#define STM32_SPI3_SUPPORTS_I2S TRUE
417
418#define STM32_HAS_SPI4 FALSE
419#define STM32_HAS_SPI5 FALSE
420#define STM32_HAS_SPI6 FALSE
421
422/* TIM attributes.*/
423#define STM32_TIM_MAX_CHANNELS 6
424
425#define STM32_HAS_TIM1 TRUE
426#define STM32_TIM1_IS_32BITS FALSE
427#define STM32_TIM1_CHANNELS 6
428
429#define STM32_HAS_TIM2 TRUE
430#define STM32_TIM2_IS_32BITS TRUE
431#define STM32_TIM2_CHANNELS 4
432
433#define STM32_HAS_TIM3 TRUE
434#define STM32_TIM3_IS_32BITS FALSE
435#define STM32_TIM3_CHANNELS 4
436
437#define STM32_HAS_TIM4 TRUE
438#define STM32_TIM4_IS_32BITS FALSE
439#define STM32_TIM4_CHANNELS 4
440
441#define STM32_HAS_TIM6 TRUE
442#define STM32_TIM6_IS_32BITS FALSE
443#define STM32_TIM6_CHANNELS 0
444
445#define STM32_HAS_TIM7 TRUE
446#define STM32_TIM7_IS_32BITS FALSE
447#define STM32_TIM7_CHANNELS 0
448
449#define STM32_HAS_TIM8 TRUE
450#define STM32_TIM8_IS_32BITS FALSE
451#define STM32_TIM8_CHANNELS 6
452
453#define STM32_HAS_TIM15 TRUE
454#define STM32_TIM15_IS_32BITS FALSE
455#define STM32_TIM15_CHANNELS 2
456
457#define STM32_HAS_TIM16 TRUE
458#define STM32_TIM16_IS_32BITS FALSE
459#define STM32_TIM16_CHANNELS 1
460
461#define STM32_HAS_TIM17 TRUE
462#define STM32_TIM17_IS_32BITS FALSE
463#define STM32_TIM17_CHANNELS 1
464
465#define STM32_HAS_TIM5 FALSE
466#define STM32_HAS_TIM9 FALSE
467#define STM32_HAS_TIM10 FALSE
468#define STM32_HAS_TIM11 FALSE
469#define STM32_HAS_TIM12 FALSE
470#define STM32_HAS_TIM13 FALSE
471#define STM32_HAS_TIM14 FALSE
472#define STM32_HAS_TIM18 FALSE
473#define STM32_HAS_TIM19 FALSE
474#define STM32_HAS_TIM20 FALSE
475#define STM32_HAS_TIM21 FALSE
476#define STM32_HAS_TIM22 FALSE
477
478/* USART attributes.*/
479#define STM32_HAS_USART1 TRUE
480#define STM32_HAS_USART2 TRUE
481#define STM32_HAS_USART3 TRUE
482#define STM32_HAS_UART4 TRUE
483#define STM32_HAS_UART5 FALSE
484#define STM32_HAS_LPUART1 TRUE
485#define STM32_HAS_USART6 FALSE
486#define STM32_HAS_UART7 FALSE
487#define STM32_HAS_UART8 FALSE
488
489/* OTG/USB attributes.*/
490#define STM32_HAS_OTG1 FALSE
491#define STM32_HAS_OTG2 FALSE
492
493#define STM32_HAS_USB TRUE
494#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
495#define STM32_USB_PMA_SIZE 1024
496#define STM32_USB_HAS_BCDR TRUE
497
498/* IWDG attributes.*/
499#define STM32_HAS_IWDG TRUE
500#define STM32_IWDG_IS_WINDOWED TRUE
501
502/* LTDC attributes.*/
503#define STM32_HAS_LTDC FALSE
504
505/* DMA2D attributes.*/
506#define STM32_HAS_DMA2D FALSE
507
508/* FSMC attributes.*/
509#define STM32_HAS_FSMC FALSE
510
511/* CRC attributes.*/
512#define STM32_HAS_CRC TRUE
513#define STM32_CRC_PROGRAMMABLE TRUE
514
515/* DCMI attributes.*/
516#define STM32_HAS_DCMI FALSE
517
518#endif /* defined(STM32G431xx) || defined(STM32G441xx) */
519
520/** @} */
521
522#endif /* STM32_REGISTRY_H */
523
524/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:50:46 +0100