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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file STM32G4xx/stm32_rcc.h
19 * @brief RCC helper driver header.
20 * @note This file requires definitions from the ST header file
21 * @p stm32g4xx.h.
22 *
23 * @addtogroup STM32G4xx_RCC
24 * @{
25 */
26#ifndef STM32_RCC_H
27#define STM32_RCC_H
28
29/*===========================================================================*/
30/* Driver constants. */
31/*===========================================================================*/
32
33/*===========================================================================*/
34/* Driver pre-compile time settings. */
35/*===========================================================================*/
36
37/*===========================================================================*/
38/* Derived constants and error checks. */
39/*===========================================================================*/
40
41/*===========================================================================*/
42/* Driver data structures and types. */
43/*===========================================================================*/
44
45/*===========================================================================*/
46/* Driver macros. */
47/*===========================================================================*/
48
49/**
50 * @name Generic RCC operations
51 * @{
52 */
53/**
54 * @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
55 *
56 * @param[in] mask APB1 R1 peripherals mask
57 * @param[in] lp low power enable flag
58 *
59 * @api
60 */
61#define rccEnableAPB1R1(mask, lp) { \
62 RCC->APB1ENR1 |= (mask); \
63 if (lp) \
64 RCC->APB1SMENR1 |= (mask); \
65 else \
66 RCC->APB1SMENR1 &= ~(mask); \
67 (void)RCC->APB1SMENR1; \
68}
69
70/**
71 * @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
72 *
73 * @param[in] mask APB1 R1 peripherals mask
74 *
75 * @api
76 */
77#define rccDisableAPB1R1(mask) { \
78 RCC->APB1ENR1 &= ~(mask); \
79 RCC->APB1SMENR1 &= ~(mask); \
80 (void)RCC->APB1SMENR1; \
81}
82
83/**
84 * @brief Resets one or more peripheral on the APB1 bus (R1).
85 *
86 * @param[in] mask APB1 R1 peripherals mask
87 *
88 * @api
89 */
90#define rccResetAPB1R1(mask) { \
91 RCC->APB1RSTR1 |= (mask); \
92 RCC->APB1RSTR1 &= ~(mask); \
93 (void)RCC->APB1RSTR1; \
94}
95
96/**
97 * @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
98 *
99 * @param[in] mask APB1 R2 peripherals mask
100 * @param[in] lp low power enable flag
101 *
102 * @api
103 */
104#define rccEnableAPB1R2(mask, lp) { \
105 RCC->APB1ENR2 |= (mask); \
106 if (lp) \
107 RCC->APB1SMENR2 |= (mask); \
108 else \
109 RCC->APB1SMENR2 &= ~(mask); \
110 (void)RCC->APB1SMENR2; \
111}
112
113/**
114 * @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
115 *
116 * @param[in] mask APB1 R2 peripherals mask
117 *
118 * @api
119 */
120#define rccDisableAPB1R2(mask) { \
121 RCC->APB1ENR2 &= ~(mask); \
122 RCC->APB1SMENR2 &= ~(mask); \
123 (void)RCC->APB1SMENR2; \
124}
125
126/**
127 * @brief Resets one or more peripheral on the APB1 bus (R2).
128 *
129 * @param[in] mask APB1 R2 peripherals mask
130 *
131 * @api
132 */
133#define rccResetAPB1R2(mask) { \
134 RCC->APB1RSTR2 |= (mask); \
135 RCC->APB1RSTR2 &= ~(mask); \
136 (void)RCC->APB1RSTR2; \
137}
138
139/**
140 * @brief Enables the clock of one or more peripheral on the APB2 bus.
141 *
142 * @param[in] mask APB2 peripherals mask
143 * @param[in] lp low power enable flag
144 *
145 * @api
146 */
147#define rccEnableAPB2(mask, lp) { \
148 RCC->APB2ENR |= (mask); \
149 if (lp) \
150 RCC->APB2SMENR |= (mask); \
151 else \
152 RCC->APB2SMENR &= ~(mask); \
153 (void)RCC->APB2SMENR; \
154}
155
156/**
157 * @brief Disables the clock of one or more peripheral on the APB2 bus.
158 *
159 * @param[in] mask APB2 peripherals mask
160 *
161 * @api
162 */
163#define rccDisableAPB2(mask) { \
164 RCC->APB2ENR &= ~(mask); \
165 RCC->APB2SMENR &= ~(mask); \
166 (void)RCC->APB2SMENR; \
167}
168
169/**
170 * @brief Resets one or more peripheral on the APB2 bus.
171 *
172 * @param[in] mask APB2 peripherals mask
173 *
174 * @api
175 */
176#define rccResetAPB2(mask) { \
177 RCC->APB2RSTR |= (mask); \
178 RCC->APB2RSTR &= ~(mask); \
179 (void)RCC->APB2RSTR; \
180}
181
182/**
183 * @brief Enables the clock of one or more peripheral on the AHB1 bus.
184 *
185 * @param[in] mask AHB1 peripherals mask
186 * @param[in] lp low power enable flag
187 *
188 * @api
189 */
190#define rccEnableAHB1(mask, lp) { \
191 RCC->AHB1ENR |= (mask); \
192 if (lp) \
193 RCC->AHB1SMENR |= (mask); \
194 else \
195 RCC->AHB1SMENR &= ~(mask); \
196 (void)RCC->AHB1SMENR; \
197}
198
199/**
200 * @brief Disables the clock of one or more peripheral on the AHB1 bus.
201 *
202 * @param[in] mask AHB1 peripherals mask
203 *
204 * @api
205 */
206#define rccDisableAHB1(mask) { \
207 RCC->AHB1ENR &= ~(mask); \
208 RCC->AHB1SMENR &= ~(mask); \
209 (void)RCC->AHB1SMENR; \
210}
211
212/**
213 * @brief Resets one or more peripheral on the AHB1 bus.
214 *
215 * @param[in] mask AHB1 peripherals mask
216 *
217 * @api
218 */
219#define rccResetAHB1(mask) { \
220 RCC->AHB1RSTR |= (mask); \
221 RCC->AHB1RSTR &= ~(mask); \
222 (void)RCC->AHB1RSTR; \
223}
224
225/**
226 * @brief Enables the clock of one or more peripheral on the AHB2 bus.
227 *
228 * @param[in] mask AHB2 peripherals mask
229 * @param[in] lp low power enable flag
230 *
231 * @api
232 */
233#define rccEnableAHB2(mask, lp) { \
234 RCC->AHB2ENR |= (mask); \
235 if (lp) \
236 RCC->AHB2SMENR |= (mask); \
237 else \
238 RCC->AHB2SMENR &= ~(mask); \
239 (void)RCC->AHB2SMENR; \
240}
241
242/**
243 * @brief Disables the clock of one or more peripheral on the AHB2 bus.
244 *
245 * @param[in] mask AHB2 peripherals mask
246 *
247 * @api
248 */
249#define rccDisableAHB2(mask) { \
250 RCC->AHB2ENR &= ~(mask); \
251 RCC->AHB2SMENR &= ~(mask); \
252 (void)RCC->AHB2SMENR; \
253}
254
255/**
256 * @brief Resets one or more peripheral on the AHB2 bus.
257 *
258 * @param[in] mask AHB2 peripherals mask
259 *
260 * @api
261 */
262#define rccResetAHB2(mask) { \
263 RCC->AHB2RSTR |= (mask); \
264 RCC->AHB2RSTR &= ~(mask); \
265 (void)RCC->AHB2RSTR; \
266}
267
268/**
269 * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
270 *
271 * @param[in] mask AHB3 peripherals mask
272 * @param[in] lp low power enable flag
273 *
274 * @api
275 */
276#define rccEnableAHB3(mask, lp) { \
277 RCC->AHB3ENR |= (mask); \
278 if (lp) \
279 RCC->AHB3SMENR |= (mask); \
280 else \
281 RCC->AHB3SMENR &= ~(mask); \
282 (void)RCC->AHB3SMENR; \
283}
284
285/**
286 * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
287 *
288 * @param[in] mask AHB3 peripherals mask
289 *
290 * @api
291 */
292#define rccDisableAHB3(mask) { \
293 RCC->AHB3ENR &= ~(mask); \
294 RCC->AHB3SMENR &= ~(mask); \
295 (void)RCC->AHB3SMENR; \
296}
297
298/**
299 * @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
300 *
301 * @param[in] mask AHB3 peripherals mask
302 *
303 * @api
304 */
305#define rccResetAHB3(mask) { \
306 RCC->AHB3RSTR |= (mask); \
307 RCC->AHB3RSTR &= ~(mask); \
308 (void)RCC->AHB3RSTR; \
309}
310/** @} */
311
312/**
313 * @name ADC peripherals specific RCC operations
314 * @{
315 */
316/**
317 * @brief Enables the ADC1/ADC2 peripheral clock.
318 *
319 * @param[in] lp low power enable flag
320 *
321 * @api
322 */
323#define rccEnableADC12(lp) rccEnableAHB2(RCC_AHB2ENR_ADC12EN, lp)
324
325/**
326 * @brief Disables the ADC1/ADC2 peripheral clock.
327 *
328 * @api
329 */
330#define rccDisableADC12() rccDisableAHB2(RCC_AHB2ENR_ADC12EN)
331
332/**
333 * @brief Resets the ADC1/ADC2 peripheral.
334 *
335 * @api
336 */
337#define rccResetADC12() rccResetAHB2(RCC_AHB2RSTR_ADC12RST)
338
339/**
340 * @brief Enables the ADC3/ADC4/ADC5 peripheral clock.
341 *
342 * @param[in] lp low power enable flag
343 *
344 * @api
345 */
346#define rccEnableADC345(lp) rccEnableAHB2(RCC_AHB2ENR_ADC345EN, lp)
347
348/**
349 * @brief Disables the ADC3/ADC4/ADC5 peripheral clock.
350 *
351 * @api
352 */
353#define rccDisableADC345() rccDisableAHB2(RCC_AHB2ENR_ADC345EN)
354
355/**
356 * @brief Resets the ADC3/ADC4/ADC5 peripheral.
357 *
358 * @api
359 */
360#define rccResetADC345() rccResetAHB2(RCC_AHB2RSTR_ADC345RST)
361/** @} */
362
363/**
364 * @name DAC peripheral specific RCC operations
365 * @{
366 */
367/**
368 * @brief Enables the DAC1 peripheral clock.
369 *
370 * @param[in] lp low power enable flag
371 *
372 * @api
373 */
374#define rccEnableDAC1(lp) rccEnableAHB2(RCC_AHB2ENR_DAC1EN, lp)
375
376/**
377 * @brief Disables the DAC1 peripheral clock.
378 *
379 * @api
380 */
381#define rccDisableDAC1() rccDisableAHB2(RCC_AHB2ENR_DAC1EN)
382
383/**
384 * @brief Resets the DAC1 peripheral.
385 *
386 * @api
387 */
388#define rccResetDAC1() rccResetAHB2(RCC_AHB2RSTR_DAC1RST)
389
390/**
391 * @brief Enables the DAC2 peripheral clock.
392 *
393 * @param[in] lp low power enable flag
394 *
395 * @api
396 */
397#define rccEnableDAC2(lp) rccEnableAHB2(RCC_AHB2ENR_DAC2EN, lp)
398
399/**
400 * @brief Disables the DAC2 peripheral clock.
401 *
402 * @api
403 */
404#define rccDisableDAC2() rccDisableAHB2(RCC_AHB2ENR_DAC2EN)
405
406/**
407 * @brief Resets the DAC2 peripheral.
408 *
409 * @api
410 */
411#define rccResetDAC2() rccResetAHB2(RCC_AHB2RSTR_DAC2RST)
412
413/**
414 * @brief Enables the DAC3 peripheral clock.
415 *
416 * @param[in] lp low power enable flag
417 *
418 * @api
419 */
420#define rccEnableDAC3(lp) rccEnableAHB2(RCC_AHB2ENR_DAC3EN, lp)
421
422/**
423 * @brief Disables the DAC3 peripheral clock.
424 *
425 * @api
426 */
427#define rccDisableDAC3() rccDisableAHB2(RCC_AHB2ENR_DAC3EN)
428
429/**
430 * @brief Resets the DAC3 peripheral.
431 *
432 * @api
433 */
434#define rccResetDAC3() rccResetAHB2(RCC_AHB2RSTR_DAC3RST)
435
436/**
437 * @brief Enables the DAC4 peripheral clock.
438 *
439 * @param[in] lp low power enable flag
440 *
441 * @api
442 */
443#define rccEnableDAC4(lp) rccEnableAHB2(RCC_AHB2ENR_DAC4EN, lp)
444
445/**
446 * @brief Disables the DAC4 peripheral clock.
447 *
448 * @api
449 */
450#define rccDisableDAC4() rccDisableAHB2(RCC_AHB2ENR_DAC4EN)
451
452/**
453 * @brief Resets the DAC4 peripheral.
454 *
455 * @api
456 */
457#define rccResetDAC4() rccResetAHB2(RCC_AHB2RSTR_DAC4RST)
458/** @} */
459
460/**
461 * @name DMA peripheral specific RCC operations
462 * @{
463 */
464/**
465 * @brief Enables the DMA1 peripheral clock.
466 *
467 * @param[in] lp low power enable flag
468 *
469 * @api
470 */
471#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
472
473/**
474 * @brief Disables the DMA1 peripheral clock.
475 *
476 * @api
477 */
478#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
479
480/**
481 * @brief Resets the DMA1 peripheral.
482 *
483 * @api
484 */
485#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
486
487/**
488 * @brief Enables the DMA2 peripheral clock.
489 *
490 * @param[in] lp low power enable flag
491 *
492 * @api
493 */
494#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
495
496/**
497 * @brief Disables the DMA2 peripheral clock.
498 *
499 * @api
500 */
501#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
502
503/**
504 * @brief Resets the DMA2 peripheral.
505 *
506 * @api
507 */
508#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
509/** @} */
510
511/**
512 * @name DMAMUX peripheral specific RCC operations
513 * @{
514 */
515/**
516 * @brief Enables the DMAMUX peripheral clock.
517 *
518 * @param[in] lp low power enable flag
519 *
520 * @api
521 */
522#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
523
524/**
525 * @brief Disables the DMAMUX peripheral clock.
526 *
527 * @api
528 */
529#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
530
531/**
532 * @brief Resets the DMAMUX peripheral.
533 *
534 * @api
535 */
536#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
537/** @} */
538
539/**
540 * @name FDCAN peripherals specific RCC operations
541 * @{
542 */
543/**
544 * @brief Enables the FDCAN peripheral clock.
545 *
546 * @param[in] lp low power enable flag
547 *
548 * @api
549 */
550#define rccEnableFDCAN(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
551
552/**
553 * @brief Disables the FDCAN peripheral clock.
554 *
555 * @api
556 */
557#define rccDisableFDCAN() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
558
559/**
560 * @brief Resets the FDCAN peripheral.
561 *
562 * @api
563 */
564#define rccResetFDCAN() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
565/** @} */
566
567/**
568 * @name PWR interface specific RCC operations
569 * @{
570 */
571/**
572 * @brief Enables the PWR interface clock.
573 *
574 * @param[in] lp low power enable flag
575 *
576 * @api
577 */
578#define rccEnablePWRInterface(lp) rccEnableAPB1R1(RCC_APB1ENR1_PWREN, lp)
579
580/**
581 * @brief Disables PWR interface clock.
582 *
583 * @api
584 */
585#define rccDisablePWRInterface() rccDisableAPB1R1(RCC_APB1ENR1_PWREN)
586
587/**
588 * @brief Resets the PWR interface.
589 *
590 * @api
591 */
592#define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
593/** @} */
594
595/**
596 * @name FDCAN peripherals specific RCC operations
597 * @{
598 */
599/**
600 * @brief Enables the FDCAN1 peripheral clock.
601 *
602 * @param[in] lp low power enable flag
603 *
604 * @api
605 */
606#define rccEnableFDCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
607
608/**
609 * @brief Disables the FDCAN1 peripheral clock.
610 *
611 * @api
612 */
613#define rccDisableFDCAN1() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
614
615/**
616 * @brief Resets the FDCAN1 peripheral.
617 *
618 * @api
619 */
620#define rccResetFDCAN1() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
621/** @} */
622
623/**
624 * @name I2C peripherals specific RCC operations
625 * @{
626 */
627/**
628 * @brief Enables the I2C1 peripheral clock.
629 *
630 * @param[in] lp low power enable flag
631 *
632 * @api
633 */
634#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
635
636/**
637 * @brief Disables the I2C1 peripheral clock.
638 *
639 * @api
640 */
641#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
642
643/**
644 * @brief Resets the I2C1 peripheral.
645 *
646 * @api
647 */
648#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
649
650/**
651 * @brief Enables the I2C2 peripheral clock.
652 *
653 * @param[in] lp low power enable flag
654 *
655 * @api
656 */
657#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
658
659/**
660 * @brief Disables the I2C2 peripheral clock.
661 *
662 * @api
663 */
664#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
665
666/**
667 * @brief Resets the I2C2 peripheral.
668 *
669 * @api
670 */
671#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
672
673/**
674 * @brief Enables the I2C3 peripheral clock.
675 *
676 * @param[in] lp low power enable flag
677 *
678 * @api
679 */
680#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
681
682/**
683 * @brief Disables the I2C3 peripheral clock.
684 *
685 * @api
686 */
687#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
688
689/**
690 * @brief Resets the I2C3 peripheral.
691 *
692 * @api
693 */
694#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
695
696/**
697 * @brief Enables the I2C4 peripheral clock.
698 *
699 * @param[in] lp low power enable flag
700 *
701 * @api
702 */
703#define rccEnableI2C4(lp) rccEnableAPB1R2(RCC_APB1ENR2_I2C4EN, lp)
704
705/**
706 * @brief Disables the I2C4 peripheral clock.
707 *
708 * @api
709 */
710#define rccDisableI2C4() rccDisableAPB1R1(RCC_APB1ENR2_I2C4EN)
711
712/**
713 * @brief Resets the I2C4 peripheral.
714 *
715 * @api
716 */
717#define rccResetI2C4() rccResetAPB1R1(RCC_APB1RSTR2_I2C4RST)
718/** @} */
719
720/**
721 * @name QUADSPI peripherals specific RCC operations
722 * @{
723 */
724/**
725 * @brief Enables the QUADSPI1 peripheral clock.
726 *
727 * @param[in] lp low power enable flag
728 *
729 * @api
730 */
731#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
732
733/**
734 * @brief Disables the QUADSPI1 peripheral clock.
735 *
736 * @api
737 */
738#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
739
740/**
741 * @brief Resets the QUADSPI1 peripheral.
742 *
743 * @api
744 */
745#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
746/** @} */
747
748/**
749 * @name RNG peripherals specific RCC operations
750 * @{
751 */
752/**
753 * @brief Enables the RNG peripheral clock.
754 *
755 * @param[in] lp low power enable flag
756 *
757 * @api
758 */
759#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp)
760
761/**
762 * @brief Disables the RNG peripheral clock.
763 *
764 * @api
765 */
766#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN)
767
768/**
769 * @brief Resets the RNG peripheral.
770 *
771 * @api
772 */
773#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
774/** @} */
775
776/**
777 * @name SPI peripherals specific RCC operations
778 * @{
779 */
780/**
781 * @brief Enables the SPI1 peripheral clock.
782 *
783 * @param[in] lp low power enable flag
784 *
785 * @api
786 */
787#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
788
789/**
790 * @brief Disables the SPI1 peripheral clock.
791 *
792 * @api
793 */
794#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
795
796/**
797 * @brief Resets the SPI1 peripheral.
798 *
799 * @api
800 */
801#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
802
803/**
804 * @brief Enables the SPI2 peripheral clock.
805 *
806 * @param[in] lp low power enable flag
807 *
808 * @api
809 */
810#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
811
812/**
813 * @brief Disables the SPI2 peripheral clock.
814 *
815 * @api
816 */
817#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
818
819/**
820 * @brief Resets the SPI2 peripheral.
821 *
822 * @api
823 */
824#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
825
826/**
827 * @brief Enables the SPI3 peripheral clock.
828 *
829 * @param[in] lp low power enable flag
830 *
831 * @api
832 */
833#define rccEnableSPI3(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI3EN, lp)
834
835/**
836 * @brief Disables the SPI3 peripheral clock.
837 *
838 * @api
839 */
840#define rccDisableSPI3() rccDisableAPB1R1(RCC_APB1ENR1_SPI3EN)
841
842/**
843 * @brief Resets the SPI3 peripheral.
844 *
845 * @api
846 */
847#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
848
849/**
850 * @brief Enables the SPI4 peripheral clock.
851 *
852 * @param[in] lp low power enable flag
853 *
854 * @api
855 */
856#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
857
858/**
859 * @brief Disables the SPI4 peripheral clock.
860 *
861 * @api
862 */
863#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
864
865/**
866 * @brief Resets the SPI4 peripheral.
867 *
868 * @api
869 */
870#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
871/** @} */
872
873/**
874 * @name TIM peripherals specific RCC operations
875 * @{
876 */
877/**
878 * @brief Enables the TIM1 peripheral clock.
879 *
880 * @param[in] lp low power enable flag
881 *
882 * @api
883 */
884#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
885
886/**
887 * @brief Disables the TIM1 peripheral clock.
888 *
889 * @api
890 */
891#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
892
893/**
894 * @brief Resets the TIM1 peripheral.
895 *
896 * @api
897 */
898#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
899
900/**
901 * @brief Enables the TIM2 peripheral clock.
902 *
903 * @param[in] lp low power enable flag
904 *
905 * @api
906 */
907#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
908
909/**
910 * @brief Disables the TIM2 peripheral clock.
911 *
912 * @api
913 */
914#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
915
916/**
917 * @brief Resets the TIM2 peripheral.
918 *
919 * @api
920 */
921#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
922
923/**
924 * @brief Enables the TIM3 peripheral clock.
925 *
926 * @param[in] lp low power enable flag
927 *
928 * @api
929 */
930#define rccEnableTIM3(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM3EN, lp)
931
932/**
933 * @brief Disables the TIM3 peripheral clock.
934 *
935 * @api
936 */
937#define rccDisableTIM3() rccDisableAPB1R1(RCC_APB1ENR1_TIM3EN)
938
939/**
940 * @brief Resets the TIM3 peripheral.
941 *
942 * @api
943 */
944#define rccResetTIM3() rccResetAPB1R1(RCC_APB1RSTR1_TIM3RST)
945
946/**
947 * @brief Enables the TIM4 peripheral clock.
948 *
949 * @param[in] lp low power enable flag
950 *
951 * @api
952 */
953#define rccEnableTIM4(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM4EN, lp)
954
955/**
956 * @brief Disables the TIM4 peripheral clock.
957 *
958 * @api
959 */
960#define rccDisableTIM4() rccDisableAPB1R1(RCC_APB1ENR1_TIM4EN)
961
962/**
963 * @brief Resets the TIM4 peripheral.
964 *
965 * @api
966 */
967#define rccResetTIM4() rccResetAPB1R1(RCC_APB1RSTR1_TIM4RST)
968
969/**
970 * @brief Enables the TIM5 peripheral clock.
971 *
972 * @param[in] lp low power enable flag
973 *
974 * @api
975 */
976#define rccEnableTIM5(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM5EN, lp)
977
978/**
979 * @brief Disables the TIM5 peripheral clock.
980 *
981 * @api
982 */
983#define rccDisableTIM5() rccDisableAPB1R1(RCC_APB1ENR1_TIM5EN)
984
985/**
986 * @brief Resets the TIM5 peripheral.
987 *
988 * @api
989 */
990#define rccResetTIM5() rccResetAPB1R1(RCC_APB1RSTR1_TIM5RST)
991
992/**
993 * @brief Enables the TIM6 peripheral clock.
994 *
995 * @param[in] lp low power enable flag
996 *
997 * @api
998 */
999#define rccEnableTIM6(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM6EN, lp)
1000
1001/**
1002 * @brief Disables the TIM6 peripheral clock.
1003 *
1004 * @api
1005 */
1006#define rccDisableTIM6() rccDisableAPB1R1(RCC_APB1ENR1_TIM6EN)
1007
1008/**
1009 * @brief Resets the TIM6 peripheral.
1010 *
1011 * @api
1012 */
1013#define rccResetTIM6() rccResetAPB1R1(RCC_APB1RSTR1_TIM6RST)
1014
1015/**
1016 * @brief Enables the TIM7 peripheral clock.
1017 *
1018 * @param[in] lp low power enable flag
1019 *
1020 * @api
1021 */
1022#define rccEnableTIM7(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM7EN, lp)
1023
1024/**
1025 * @brief Disables the TIM7 peripheral clock.
1026 *
1027 * @api
1028 */
1029#define rccDisableTIM7() rccDisableAPB1R1(RCC_APB1ENR1_TIM7EN)
1030
1031/**
1032 * @brief Resets the TIM7 peripheral.
1033 *
1034 * @api
1035 */
1036#define rccResetTIM7() rccResetAPB1R1(RCC_APB1RSTR1_TIM7RST)
1037
1038/**
1039 * @brief Enables the TIM8 peripheral clock.
1040 *
1041 * @param[in] lp low power enable flag
1042 *
1043 * @api
1044 */
1045#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
1046
1047/**
1048 * @brief Disables the TIM8 peripheral clock.
1049 *
1050 * @api
1051 */
1052#define rccDisableTIM8() rccDisableAPB2(RCC_APB2ENR_TIM8EN)
1053
1054/**
1055 * @brief Resets the TIM8 peripheral.
1056 *
1057 * @api
1058 */
1059#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
1060
1061/**
1062 * @brief Enables the TIM15 peripheral clock.
1063 *
1064 * @param[in] lp low power enable flag
1065 *
1066 * @api
1067 */
1068#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
1069
1070/**
1071 * @brief Disables the TIM15 peripheral clock.
1072 *
1073 * @api
1074 */
1075#define rccDisableTIM15() rccDisableAPB2(RCC_APB2ENR_TIM15EN)
1076
1077/**
1078 * @brief Resets the TIM15 peripheral.
1079 *
1080 * @api
1081 */
1082#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
1083
1084/**
1085 * @brief Enables the TIM16 peripheral clock.
1086 *
1087 * @param[in] lp low power enable flag
1088 *
1089 * @api
1090 */
1091#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
1092
1093/**
1094 * @brief Disables the TIM16 peripheral clock.
1095 *
1096 * @api
1097 */
1098#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
1099
1100/**
1101 * @brief Resets the TIM16 peripheral.
1102 *
1103 * @api
1104 */
1105#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
1106
1107/**
1108 * @brief Enables the TIM17 peripheral clock.
1109 *
1110 * @param[in] lp low power enable flag
1111 *
1112 * @api
1113 */
1114#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
1115
1116/**
1117 * @brief Disables the TIM17 peripheral clock.
1118 *
1119 * @api
1120 */
1121#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
1122
1123/**
1124 * @brief Resets the TIM17 peripheral.
1125 *
1126 * @api
1127 */
1128#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
1129
1130/**
1131 * @brief Enables the TIM20 peripheral clock.
1132 *
1133 * @param[in] lp low power enable flag
1134 *
1135 * @api
1136 */
1137#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
1138
1139/**
1140 * @brief Disables the TIM20 peripheral clock.
1141 *
1142 * @api
1143 */
1144#define rccDisableTIM20() rccDisableAPB2(RCC_APB2ENR_TIM20EN)
1145
1146/**
1147 * @brief Resets the TIM20 peripheral.
1148 *
1149 * @api
1150 */
1151#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
1152/** @} */
1153
1154/**
1155 * @name USART/UART peripherals specific RCC operations
1156 * @{
1157 */
1158/**
1159 * @brief Enables the USART1 peripheral clock.
1160 *
1161 * @param[in] lp low power enable flag
1162 *
1163 * @api
1164 */
1165#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
1166
1167/**
1168 * @brief Disables the USART1 peripheral clock.
1169 *
1170 * @api
1171 */
1172#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
1173
1174/**
1175 * @brief Resets the USART1 peripheral.
1176 *
1177 * @api
1178 */
1179#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
1180
1181/**
1182 * @brief Enables the USART2 peripheral clock.
1183 *
1184 * @param[in] lp low power enable flag
1185 *
1186 * @api
1187 */
1188#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
1189
1190/**
1191 * @brief Disables the USART2 peripheral clock.
1192 *
1193 * @api
1194 */
1195#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
1196
1197/**
1198 * @brief Resets the USART2 peripheral.
1199 *
1200 * @api
1201 */
1202#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
1203
1204/**
1205 * @brief Enables the USART3 peripheral clock.
1206 *
1207 * @param[in] lp low power enable flag
1208 *
1209 * @api
1210 */
1211#define rccEnableUSART3(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART3EN, lp)
1212
1213/**
1214 * @brief Disables the USART3 peripheral clock.
1215 *
1216 * @api
1217 */
1218#define rccDisableUSART3() rccDisableAPB1R1(RCC_APB1ENR1_USART3EN)
1219
1220/**
1221 * @brief Resets the USART3 peripheral.
1222 *
1223 * @api
1224 */
1225#define rccResetUSART3() rccResetAPB1R1(RCC_APB1RSTR1_USART3RST)
1226
1227/**
1228 * @brief Enables the UART4 peripheral clock.
1229 *
1230 * @param[in] lp low power enable flag
1231 *
1232 * @api
1233 */
1234#define rccEnableUART4(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART4EN, lp)
1235
1236/**
1237 * @brief Disables the UART4 peripheral clock.
1238 *
1239 * @api
1240 */
1241#define rccDisableUART4() rccDisableAPB1R1(RCC_APB1ENR1_UART4EN)
1242
1243/**
1244 * @brief Resets the UART4 peripheral.
1245 *
1246 * @api
1247 */
1248#define rccResetUART4() rccResetAPB1R1(RCC_APB1RSTR1_UART4RST)
1249
1250/**
1251 * @brief Enables the UART5 peripheral clock.
1252 *
1253 * @param[in] lp low power enable flag
1254 *
1255 * @api
1256 */
1257#define rccEnableUART5(lp) rccEnableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
1258
1259/**
1260 * @brief Disables the UART5 peripheral clock.
1261 *
1262 * @api
1263 */
1264#define rccDisableUART5() rccDisableAPB1R1(RCC_APB1ENR1_UART5EN)
1265
1266/**
1267 * @brief Resets the UART5 peripheral.
1268 *
1269 * @api
1270 */
1271#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
1272
1273/**
1274 * @brief Enables the LPUART1 peripheral clock.
1275 *
1276 * @param[in] lp low power enable flag
1277 *
1278 * @api
1279 */
1280#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
1281
1282/**
1283 * @brief Disables the LPUART1 peripheral clock.
1284 *
1285 * @api
1286 */
1287#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
1288
1289/**
1290 * @brief Resets the USART1 peripheral.
1291 *
1292 * @api
1293 */
1294#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
1295/** @} */
1296
1297/**
1298 * @name USB peripheral specific RCC operations
1299 * @{
1300 */
1301/**
1302 * @brief Enables the USB peripheral clock.
1303 *
1304 * @param[in] lp low power enable flag
1305 *
1306 * @api
1307 */
1308#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp)
1309
1310/**
1311 * @brief Disables the USB peripheral clock.
1312 *
1313 * @api
1314 */
1315#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN)
1316
1317/**
1318 * @brief Resets the USB peripheral.
1319 *
1320 * @api
1321 */
1322#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST)
1323/** @} */
1324
1325/**
1326 * @name CRC peripheral specific RCC operations
1327 * @{
1328 */
1329/**
1330 * @brief Enables the CRC peripheral clock.
1331 *
1332 * @param[in] lp low power enable flag
1333 *
1334 * @api
1335 */
1336#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
1337
1338/**
1339 * @brief Disables the CRC peripheral clock.
1340 *
1341 * @api
1342 */
1343#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
1344
1345/**
1346 * @brief Resets the CRC peripheral.
1347 *
1348 * @api
1349 */
1350#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
1351/** @} */
1352
1353/*===========================================================================*/
1354/* External declarations. */
1355/*===========================================================================*/
1356
1357#ifdef __cplusplus
1358extern "C" {
1359#endif
1360#ifdef __cplusplus
1361}
1362#endif
1363
1364#endif /* STM32_RCC_H */
1365
1366/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 16:58:51 +0100