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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.c381
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.h215
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.c496
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.h122
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.c315
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.c381
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.h215
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.c471
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.h119
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.c315
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.c48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/pin_mux.c1094
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/pin_mux.h938
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/xip/driver_xip_board.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/xip/evkbimxrt1050_flexspi_nor_config.c55
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/xip/evkbimxrt1050_flexspi_nor_config.h267
19 files changed, 5546 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.c
new file mode 100644
index 000000000..0f4335c31
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.c
@@ -0,0 +1,381 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15/*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19/*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23/* Get debug console frequency. */
24uint32_t BOARD_DebugConsoleSrcFreq(void)
25{
26 uint32_t freq;
27
28 /* To make it simple, we assume default PLL and divider settings, and the only variable
29 from application is use PLL3 source or OSC source */
30 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
31 {
32 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
33 }
34 else
35 {
36 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
37 }
38
39 return freq;
40}
41
42/* Initialize debug console. */
43void BOARD_InitDebugConsole(void)
44{
45 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
46
47 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
48}
49
50#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
51void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
52{
53 lpi2c_master_config_t lpi2cConfig = {0};
54
55 /*
56 * lpi2cConfig.debugEnable = false;
57 * lpi2cConfig.ignoreAck = false;
58 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
59 * lpi2cConfig.baudRate_Hz = 100000U;
60 * lpi2cConfig.busIdleTimeout_ns = 0;
61 * lpi2cConfig.pinLowTimeout_ns = 0;
62 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
63 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
64 */
65 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
66 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
67}
68
69status_t BOARD_LPI2C_Send(LPI2C_Type *base,
70 uint8_t deviceAddress,
71 uint32_t subAddress,
72 uint8_t subAddressSize,
73 uint8_t *txBuff,
74 uint8_t txBuffSize)
75{
76 lpi2c_master_transfer_t xfer;
77
78 xfer.flags = kLPI2C_TransferDefaultFlag;
79 xfer.slaveAddress = deviceAddress;
80 xfer.direction = kLPI2C_Write;
81 xfer.subaddress = subAddress;
82 xfer.subaddressSize = subAddressSize;
83 xfer.data = txBuff;
84 xfer.dataSize = txBuffSize;
85
86 return LPI2C_MasterTransferBlocking(base, &xfer);
87}
88
89status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
90 uint8_t deviceAddress,
91 uint32_t subAddress,
92 uint8_t subAddressSize,
93 uint8_t *rxBuff,
94 uint8_t rxBuffSize)
95{
96 lpi2c_master_transfer_t xfer;
97
98 xfer.flags = kLPI2C_TransferDefaultFlag;
99 xfer.slaveAddress = deviceAddress;
100 xfer.direction = kLPI2C_Read;
101 xfer.subaddress = subAddress;
102 xfer.subaddressSize = subAddressSize;
103 xfer.data = rxBuff;
104 xfer.dataSize = rxBuffSize;
105
106 return LPI2C_MasterTransferBlocking(base, &xfer);
107}
108
109status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
110 uint8_t deviceAddress,
111 uint32_t subAddress,
112 uint8_t subAddressSize,
113 uint8_t *txBuff,
114 uint8_t txBuffSize)
115{
116 lpi2c_master_transfer_t xfer;
117
118 xfer.flags = kLPI2C_TransferDefaultFlag;
119 xfer.slaveAddress = deviceAddress;
120 xfer.direction = kLPI2C_Write;
121 xfer.subaddress = subAddress;
122 xfer.subaddressSize = subAddressSize;
123 xfer.data = txBuff;
124 xfer.dataSize = txBuffSize;
125
126 return LPI2C_MasterTransferBlocking(base, &xfer);
127}
128
129status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subAddressSize,
133 uint8_t *rxBuff,
134 uint8_t rxBuffSize)
135{
136 status_t status;
137 lpi2c_master_transfer_t xfer;
138
139 xfer.flags = kLPI2C_TransferDefaultFlag;
140 xfer.slaveAddress = deviceAddress;
141 xfer.direction = kLPI2C_Write;
142 xfer.subaddress = subAddress;
143 xfer.subaddressSize = subAddressSize;
144 xfer.data = NULL;
145 xfer.dataSize = 0;
146
147 status = LPI2C_MasterTransferBlocking(base, &xfer);
148
149 if (kStatus_Success == status)
150 {
151 xfer.subaddressSize = 0;
152 xfer.direction = kLPI2C_Read;
153 xfer.data = rxBuff;
154 xfer.dataSize = rxBuffSize;
155
156 status = LPI2C_MasterTransferBlocking(base, &xfer);
157 }
158
159 return status;
160}
161
162void BOARD_Accel_I2C_Init(void)
163{
164 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
165}
166
167status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
168{
169 uint8_t data = (uint8_t)txBuff;
170
171 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
172}
173
174status_t BOARD_Accel_I2C_Receive(
175 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
176{
177 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
178}
179
180void BOARD_Codec_I2C_Init(void)
181{
182 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
183}
184
185status_t BOARD_Codec_I2C_Send(
186 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
187{
188 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
189 txBuffSize);
190}
191
192status_t BOARD_Codec_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
194{
195 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
196}
197
198void BOARD_Camera_I2C_Init(void)
199{
200 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
201 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
202 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
203}
204
205status_t BOARD_Camera_I2C_Send(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
207{
208 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
209 txBuffSize);
210}
211
212status_t BOARD_Camera_I2C_Receive(
213 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
214{
215 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
216 rxBuffSize);
217}
218
219status_t BOARD_Camera_I2C_SendSCCB(
220 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
221{
222 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
223 txBuffSize);
224}
225
226status_t BOARD_Camera_I2C_ReceiveSCCB(
227 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
228{
229 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
230 rxBuffSize);
231}
232#endif /* SDK_I2C_BASED_COMPONENT_USED */
233
234/* MPU configuration. */
235void BOARD_ConfigMPU(void)
236{
237#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
238 extern uint32_t Image$$RW_m_ncache$$Base[];
239 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
240 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
241 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
242 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
243 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
244 0 :
245 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
246#elif defined(__MCUXPRESSO)
247 extern uint32_t __base_NCACHE_REGION;
248 extern uint32_t __top_NCACHE_REGION;
249 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
250 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
251#elif defined(__ICCARM__) || defined(__GNUC__)
252 extern uint32_t __NCACHE_REGION_START[];
253 extern uint32_t __NCACHE_REGION_SIZE[];
254 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
255 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
256#endif
257 volatile uint32_t i = 0;
258
259 /* Disable I cache and D cache */
260 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
261 {
262 SCB_DisableICache();
263 }
264 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
265 {
266 SCB_DisableDCache();
267 }
268
269 /* Disable MPU */
270 ARM_MPU_Disable();
271
272 /* MPU configure:
273 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
274 * SubRegionDisable, Size)
275 * API in mpu_armv7.h.
276 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
277 * disabled.
278 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
279 * Privileged mode.
280 * Use MACROS defined in mpu_armv7.h:
281 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
282 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
283 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
284 * 0 x 0 0 Strongly Ordered shareable
285 * 0 x 0 1 Device shareable
286 * 0 0 1 0 Normal not shareable Outer and inner write
287 * through no write allocate
288 * 0 0 1 1 Normal not shareable Outer and inner write
289 * back no write allocate
290 * 0 1 1 0 Normal shareable Outer and inner write
291 * through no write allocate
292 * 0 1 1 1 Normal shareable Outer and inner write
293 * back no write allocate
294 * 1 0 0 0 Normal not shareable outer and inner
295 * noncache
296 * 1 1 0 0 Normal shareable outer and inner
297 * noncache
298 * 1 0 1 1 Normal not shareable outer and inner write
299 * back write/read acllocate
300 * 1 1 1 1 Normal shareable outer and inner write
301 * back write/read acllocate
302 * 2 x 0 0 Device not shareable
303 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
304 * policy.
305 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
306 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
307 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
308 * mpu_armv7.h.
309 */
310
311 /*
312 * Add default region to deny access to whole address space to workaround speculative prefetch.
313 * Refer to Arm errata 1013783-B for more details.
314 *
315 */
316 /* Region 0 setting: Instruction access disabled, No data access permission. */
317 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
318 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
319
320 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
321 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
322 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
323
324 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
325 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
326 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
327
328#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
329 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
330 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
332#endif
333
334 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
335 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
336 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
337
338 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
339 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
340 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
341
342 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
343 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
345
346 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
347 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
348 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
349
350 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
351 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
352 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
353
354 while ((size >> i) > 0x1U)
355 {
356 i++;
357 }
358
359 if (i != 0)
360 {
361 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
362 assert(!(nonCacheStart % size));
363 assert(size == (uint32_t)(1 << i));
364 assert(i >= 5);
365
366 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
367 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
368 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
369 }
370
371 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
372 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
373 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
374
375 /* Enable MPU */
376 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
377
378 /* Enable I cache and D cache */
379 SCB_EnableDCache();
380 SCB_EnableICache();
381}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.h
new file mode 100644
index 000000000..6f77eea30
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/board.h
@@ -0,0 +1,215 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14#include "fsl_clock.h"
15
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19/*! @brief The board name */
20#define BOARD_NAME "IMXRT1050-EVKB"
21
22/* The UART to use for debug messages. */
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
25#define BOARD_DEBUG_UART_INSTANCE 1U
26
27#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
28
29#define BOARD_UART_IRQ LPUART1_IRQn
30#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
31
32#ifndef BOARD_DEBUG_UART_BAUDRATE
33#define BOARD_DEBUG_UART_BAUDRATE (115200U)
34#endif /* BOARD_DEBUG_UART_BAUDRATE */
35
36/*! @brief The USER_LED used for board */
37#define LOGIC_LED_ON (0U)
38#define LOGIC_LED_OFF (1U)
39#ifndef BOARD_USER_LED_GPIO
40#define BOARD_USER_LED_GPIO GPIO1
41#endif
42#ifndef BOARD_USER_LED_GPIO_PIN
43#define BOARD_USER_LED_GPIO_PIN (9U)
44#endif
45
46#define USER_LED_INIT(output) \
47 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
48 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
49#define USER_LED_ON() \
50 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
51#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
52#define USER_LED_TOGGLE() \
53 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
54 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
55
56/*! @brief Define the port interrupt number for the board switches */
57#ifndef BOARD_USER_BUTTON_GPIO
58#define BOARD_USER_BUTTON_GPIO GPIO5
59#endif
60#ifndef BOARD_USER_BUTTON_GPIO_PIN
61#define BOARD_USER_BUTTON_GPIO_PIN (0U)
62#endif
63#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
64#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
65#define BOARD_USER_BUTTON_NAME "SW8"
66
67/*! @brief The hyper flash size */
68#define BOARD_FLASH_SIZE (0x4000000U)
69
70/*! @brief The ENET PHY address. */
71#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
72
73/* USB PHY condfiguration */
74#define BOARD_USB_PHY_D_CAL (0x0CU)
75#define BOARD_USB_PHY_TXCAL45DP (0x06U)
76#define BOARD_USB_PHY_TXCAL45DM (0x06U)
77
78#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
79#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
80#define BOARD_ARDUINO_I2C_INDEX (1)
81
82#define BOARD_HAS_SDCARD (1U)
83
84/*! @brief The WIFI-QCA shield pin. */
85#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
86#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
87#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
88#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
89#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
90#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
91#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
92
93#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
94#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
95#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
96#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
97#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
98#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
99#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
100
101/*! @brief The WIFI-QCA Silex 2401 shield pin. */
102#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
103#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
104#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
105#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
106#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
107#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
108#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
109
110#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
111#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
112#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
113#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
114#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
115#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
116#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
117
118/* @Brief Board accelerator sensor configuration */
119#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
120/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
121#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
122/* Clock divider for LPI2C clock source */
123#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
124#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
125
126#define BOARD_CODEC_I2C_BASEADDR LPI2C1
127#define BOARD_CODEC_I2C_INSTANCE 1U
128#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
129#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
130#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
131
132/* @Brief Board CAMERA configuration */
133#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
134#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
135#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
136#define BOARD_CAMERA_I2C_CLOCK_FREQ \
137 (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
138
139#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
140#define BOARD_CAMERA_I2C_SCL_PIN 16
141#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
142#define BOARD_CAMERA_I2C_SDA_PIN 17
143#define BOARD_CAMERA_PWDN_GPIO GPIO1
144#define BOARD_CAMERA_PWDN_PIN 4
145
146/* @Brief Board Bluetooth HCI UART configuration */
147#define BOARD_BT_UART_BASEADDR LPUART3
148#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
149#define BOARD_BT_UART_IRQ LPUART3_IRQn
150#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
151
152#if defined(__cplusplus)
153extern "C" {
154#endif /* __cplusplus */
155
156/*******************************************************************************
157 * API
158 ******************************************************************************/
159uint32_t BOARD_DebugConsoleSrcFreq(void);
160
161void BOARD_InitDebugConsole(void);
162
163void BOARD_ConfigMPU(void);
164#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
165void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
166status_t BOARD_LPI2C_Send(LPI2C_Type *base,
167 uint8_t deviceAddress,
168 uint32_t subAddress,
169 uint8_t subaddressSize,
170 uint8_t *txBuff,
171 uint8_t txBuffSize);
172status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
173 uint8_t deviceAddress,
174 uint32_t subAddress,
175 uint8_t subaddressSize,
176 uint8_t *rxBuff,
177 uint8_t rxBuffSize);
178status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
179 uint8_t deviceAddress,
180 uint32_t subAddress,
181 uint8_t subaddressSize,
182 uint8_t *txBuff,
183 uint8_t txBuffSize);
184status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
185 uint8_t deviceAddress,
186 uint32_t subAddress,
187 uint8_t subaddressSize,
188 uint8_t *rxBuff,
189 uint8_t rxBuffSize);
190void BOARD_Accel_I2C_Init(void);
191status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
192status_t BOARD_Accel_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
194void BOARD_Codec_I2C_Init(void);
195status_t BOARD_Codec_I2C_Send(
196 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
197status_t BOARD_Codec_I2C_Receive(
198 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
199void BOARD_Camera_I2C_Init(void);
200status_t BOARD_Camera_I2C_Send(
201 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
202status_t BOARD_Camera_I2C_Receive(
203 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
204
205status_t BOARD_Camera_I2C_SendSCCB(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
207status_t BOARD_Camera_I2C_ReceiveSCCB(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
209#endif /* SDK_I2C_BASED_COMPONENT_USED */
210
211#if defined(__cplusplus)
212}
213#endif /* __cplusplus */
214
215#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.c
new file mode 100644
index 000000000..349dc091f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.c
@@ -0,0 +1,496 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7/*
8 * How to setup clock using clock driver functions:
9 *
10 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
11 *
12 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
13 *
14 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
15 *
16 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
17 *
18 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
19 *
20 */
21
22/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23!!GlobalInfo
24product: Clocks v7.0
25processor: MIMXRT1052xxxxB
26package_id: MIMXRT1052DVL6B
27mcu_data: ksdk2_0
28processor_version: 0.7.9
29board: IMXRT1050-EVKB
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32#include "clock_config.h"
33#include "fsl_iomuxc.h"
34
35/*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39/*******************************************************************************
40 * Variables
41 ******************************************************************************/
42/* System clock frequency. */
43extern uint32_t SystemCoreClock;
44
45/*******************************************************************************
46 ************************ BOARD_InitBootClocks function ************************
47 ******************************************************************************/
48void BOARD_InitBootClocks(void)
49{
50 BOARD_BootClockRUN();
51}
52
53/*******************************************************************************
54 ********************** Configuration BOARD_BootClockRUN ***********************
55 ******************************************************************************/
56/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57!!Configuration
58name: BOARD_BootClockRUN
59called_from_default_init: true
60outputs:
61- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
62- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
67- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
68- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
70- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
71- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
72- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
73- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
74- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
75- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
76- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
77- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
78- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
79- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
80- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
81- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
82- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
83- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
84- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
85- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
86- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
87- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
88- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
89- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
90- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
91- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
92- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
93- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
94- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
95- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
96- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
97- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
98- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
99settings:
100- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
101- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
102- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
103- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
104- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
105- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
106- {id: CCM.SEMC_PODF.scale, value: '8'}
107- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
108- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
109- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
110- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
111- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
112- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
113- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
114- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
115- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
116- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
117- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
118- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
119- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
120- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
121- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
122- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
123- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
124- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
125- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL5.denom, value: '1'}
129- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
130- {id: CCM_ANALOG.PLL5.num, value: '0'}
131- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
132- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
133- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
134- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
135- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
136- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
137sources:
138- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
139 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
140
141/*******************************************************************************
142 * Variables for BOARD_BootClockRUN configuration
143 ******************************************************************************/
144const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
145 {
146 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
147 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
148 };
149const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
150 {
151 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
152 .numerator = 0, /* 30 bit numerator of fractional loop divider */
153 .denominator = 1, /* 30 bit denominator of fractional loop divider */
154 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
155 };
156const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
157 {
158 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
159 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
160 };
161const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
162 {
163 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
164 .postDivider = 8, /* Divider after PLL */
165 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
166 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
167 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
168 };
169/*******************************************************************************
170 * Code for BOARD_BootClockRUN configuration
171 ******************************************************************************/
172void BOARD_BootClockRUN(void)
173{
174 /* Init RTC OSC clock frequency. */
175 CLOCK_SetRtcXtalFreq(32768U);
176 /* Enable 1MHz clock output. */
177 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
178 /* Use free 1MHz clock output. */
179 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
180 /* Set XTAL 24MHz clock frequency. */
181 CLOCK_SetXtalFreq(24000000U);
182 /* Enable XTAL 24MHz clock source. */
183 CLOCK_InitExternalClk(0);
184 /* Enable internal RC. */
185 CLOCK_InitRcOsc24M();
186 /* Switch clock source to external OSC. */
187 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
188 /* Set Oscillator ready counter value. */
189 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
190 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
191 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
192 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
193 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
194 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
195 /* Waiting for DCDC_STS_DC_OK bit is asserted */
196 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
197 {
198 }
199 /* Set AHB_PODF. */
200 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
201 /* Disable IPG clock gate. */
202 CLOCK_DisableClock(kCLOCK_Adc1);
203 CLOCK_DisableClock(kCLOCK_Adc2);
204 CLOCK_DisableClock(kCLOCK_Xbar1);
205 CLOCK_DisableClock(kCLOCK_Xbar2);
206 CLOCK_DisableClock(kCLOCK_Xbar3);
207 /* Set IPG_PODF. */
208 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
209 /* Set ARM_PODF. */
210 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
211 /* Set PERIPH_CLK2_PODF. */
212 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
213 /* Disable PERCLK clock gate. */
214 CLOCK_DisableClock(kCLOCK_Gpt1);
215 CLOCK_DisableClock(kCLOCK_Gpt1S);
216 CLOCK_DisableClock(kCLOCK_Gpt2);
217 CLOCK_DisableClock(kCLOCK_Gpt2S);
218 CLOCK_DisableClock(kCLOCK_Pit);
219 /* Set PERCLK_PODF. */
220 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
221 /* Disable USDHC1 clock gate. */
222 CLOCK_DisableClock(kCLOCK_Usdhc1);
223 /* Set USDHC1_PODF. */
224 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
225 /* Set Usdhc1 clock source. */
226 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
227 /* Disable USDHC2 clock gate. */
228 CLOCK_DisableClock(kCLOCK_Usdhc2);
229 /* Set USDHC2_PODF. */
230 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
231 /* Set Usdhc2 clock source. */
232 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
233 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
234 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
235 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
236#ifndef SKIP_SYSCLK_INIT
237 /* Disable Semc clock gate. */
238 CLOCK_DisableClock(kCLOCK_Semc);
239 /* Set SEMC_PODF. */
240 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
241 /* Set Semc alt clock source. */
242 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
243 /* Set Semc clock source. */
244 CLOCK_SetMux(kCLOCK_SemcMux, 0);
245#endif
246 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
247 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
248 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
249#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
250 /* Disable Flexspi clock gate. */
251 CLOCK_DisableClock(kCLOCK_FlexSpi);
252 /* Set FLEXSPI_PODF. */
253 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
254 /* Set Flexspi clock source. */
255 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
256#endif
257 /* Disable CSI clock gate. */
258 CLOCK_DisableClock(kCLOCK_Csi);
259 /* Set CSI_PODF. */
260 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
261 /* Set Csi clock source. */
262 CLOCK_SetMux(kCLOCK_CsiMux, 0);
263 /* Disable LPSPI clock gate. */
264 CLOCK_DisableClock(kCLOCK_Lpspi1);
265 CLOCK_DisableClock(kCLOCK_Lpspi2);
266 CLOCK_DisableClock(kCLOCK_Lpspi3);
267 CLOCK_DisableClock(kCLOCK_Lpspi4);
268 /* Set LPSPI_PODF. */
269 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
270 /* Set Lpspi clock source. */
271 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
272 /* Disable TRACE clock gate. */
273 CLOCK_DisableClock(kCLOCK_Trace);
274 /* Set TRACE_PODF. */
275 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
276 /* Set Trace clock source. */
277 CLOCK_SetMux(kCLOCK_TraceMux, 0);
278 /* Disable SAI1 clock gate. */
279 CLOCK_DisableClock(kCLOCK_Sai1);
280 /* Set SAI1_CLK_PRED. */
281 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
282 /* Set SAI1_CLK_PODF. */
283 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
284 /* Set Sai1 clock source. */
285 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
286 /* Disable SAI2 clock gate. */
287 CLOCK_DisableClock(kCLOCK_Sai2);
288 /* Set SAI2_CLK_PRED. */
289 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
290 /* Set SAI2_CLK_PODF. */
291 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
292 /* Set Sai2 clock source. */
293 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
294 /* Disable SAI3 clock gate. */
295 CLOCK_DisableClock(kCLOCK_Sai3);
296 /* Set SAI3_CLK_PRED. */
297 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
298 /* Set SAI3_CLK_PODF. */
299 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
300 /* Set Sai3 clock source. */
301 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
302 /* Disable Lpi2c clock gate. */
303 CLOCK_DisableClock(kCLOCK_Lpi2c1);
304 CLOCK_DisableClock(kCLOCK_Lpi2c2);
305 CLOCK_DisableClock(kCLOCK_Lpi2c3);
306 /* Set LPI2C_CLK_PODF. */
307 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
308 /* Set Lpi2c clock source. */
309 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
310 /* Disable CAN clock gate. */
311 CLOCK_DisableClock(kCLOCK_Can1);
312 CLOCK_DisableClock(kCLOCK_Can2);
313 CLOCK_DisableClock(kCLOCK_Can1S);
314 CLOCK_DisableClock(kCLOCK_Can2S);
315 /* Set CAN_CLK_PODF. */
316 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
317 /* Set Can clock source. */
318 CLOCK_SetMux(kCLOCK_CanMux, 2);
319 /* Disable UART clock gate. */
320 CLOCK_DisableClock(kCLOCK_Lpuart1);
321 CLOCK_DisableClock(kCLOCK_Lpuart2);
322 CLOCK_DisableClock(kCLOCK_Lpuart3);
323 CLOCK_DisableClock(kCLOCK_Lpuart4);
324 CLOCK_DisableClock(kCLOCK_Lpuart5);
325 CLOCK_DisableClock(kCLOCK_Lpuart6);
326 CLOCK_DisableClock(kCLOCK_Lpuart7);
327 CLOCK_DisableClock(kCLOCK_Lpuart8);
328 /* Set UART_CLK_PODF. */
329 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
330 /* Set Uart clock source. */
331 CLOCK_SetMux(kCLOCK_UartMux, 0);
332 /* Disable LCDIF clock gate. */
333 CLOCK_DisableClock(kCLOCK_LcdPixel);
334 /* Set LCDIF_PRED. */
335 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
336 /* Set LCDIF_CLK_PODF. */
337 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
338 /* Set Lcdif pre clock source. */
339 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
340 /* Disable SPDIF clock gate. */
341 CLOCK_DisableClock(kCLOCK_Spdif);
342 /* Set SPDIF0_CLK_PRED. */
343 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
344 /* Set SPDIF0_CLK_PODF. */
345 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
346 /* Set Spdif clock source. */
347 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
348 /* Disable Flexio1 clock gate. */
349 CLOCK_DisableClock(kCLOCK_Flexio1);
350 /* Set FLEXIO1_CLK_PRED. */
351 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
352 /* Set FLEXIO1_CLK_PODF. */
353 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
354 /* Set Flexio1 clock source. */
355 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
356 /* Disable Flexio2 clock gate. */
357 CLOCK_DisableClock(kCLOCK_Flexio2);
358 /* Set FLEXIO2_CLK_PRED. */
359 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
360 /* Set FLEXIO2_CLK_PODF. */
361 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
362 /* Set Flexio2 clock source. */
363 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
364 /* Set Pll3 sw clock source. */
365 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
366 /* Init ARM PLL. */
367 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
368 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
369 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
370 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
371#ifndef SKIP_SYSCLK_INIT
372#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
373 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
374#endif
375 /* Init System PLL. */
376 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
377 /* Init System pfd0. */
378 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
379 /* Init System pfd1. */
380 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
381 /* Init System pfd2. */
382 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
383 /* Init System pfd3. */
384 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
385 /* Disable pfd offset. */
386 CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
387#endif
388 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
389 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
390 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
391#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
392 /* Init Usb1 PLL. */
393 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
394 /* Init Usb1 pfd0. */
395 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
396 /* Init Usb1 pfd1. */
397 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
398 /* Init Usb1 pfd2. */
399 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
400 /* Init Usb1 pfd3. */
401 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
402 /* Disable Usb1 PLL output for USBPHY1. */
403 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
404#endif
405 /* DeInit Audio PLL. */
406 CLOCK_DeinitAudioPll();
407 /* Bypass Audio PLL. */
408 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
409 /* Set divider for Audio PLL. */
410 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
411 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
412 /* Enable Audio PLL output. */
413 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
414 /* Init Video PLL. */
415 uint32_t pllVideo;
416 /* Disable Video PLL output before initial Video PLL. */
417 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
418 /* Bypass PLL first */
419 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
420 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
421 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
422 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
423 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
424 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
425 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
426 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
427 CCM_ANALOG->PLL_VIDEO = pllVideo;
428 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
429 {
430 }
431 /* Disable pfd offset. */
432 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK;
433 /* Disable bypass for Video PLL. */
434 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
435 /* DeInit Enet PLL. */
436 CLOCK_DeinitEnetPll();
437 /* Bypass Enet PLL. */
438 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
439 /* Set Enet output divider. */
440 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
441 /* Enable Enet output. */
442 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
443 /* Enable Enet25M output. */
444 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
445 /* DeInit Usb2 PLL. */
446 CLOCK_DeinitUsb2Pll();
447 /* Bypass Usb2 PLL. */
448 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
449 /* Enable Usb2 PLL output. */
450 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
451 /* Set preperiph clock source. */
452 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
453 /* Set periph clock source. */
454 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
455 /* Set periph clock2 clock source. */
456 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
457 /* Set per clock source. */
458 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
459 /* Set lvds1 clock source. */
460 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
461 /* Set clock out1 divider. */
462 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
463 /* Set clock out1 source. */
464 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
465 /* Set clock out2 divider. */
466 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
467 /* Set clock out2 source. */
468 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
469 /* Set clock out1 drives clock out1. */
470 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
471 /* Disable clock out1. */
472 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
473 /* Disable clock out2. */
474 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
475 /* Set SAI1 MCLK1 clock source. */
476 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
477 /* Set SAI1 MCLK2 clock source. */
478 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
479 /* Set SAI1 MCLK3 clock source. */
480 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
481 /* Set SAI2 MCLK3 clock source. */
482 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
483 /* Set SAI3 MCLK3 clock source. */
484 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
485 /* Set MQS configuration. */
486 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
487 /* Set ENET Tx clock source. */
488 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
489 /* Set GPT1 High frequency reference clock source. */
490 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
491 /* Set GPT2 High frequency reference clock source. */
492 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
493 /* Set SystemCoreClock variable. */
494 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
495}
496
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.h
new file mode 100644
index 000000000..d03437b8d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/clock_config.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _CLOCK_CONFIG_H_
8#define _CLOCK_CONFIG_H_
9
10#include "fsl_common.h"
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
16
17#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
18/*******************************************************************************
19 ************************ BOARD_InitBootClocks function ************************
20 ******************************************************************************/
21
22#if defined(__cplusplus)
23extern "C" {
24#endif /* __cplusplus*/
25
26/*!
27 * @brief This function executes default configuration of clocks.
28 *
29 */
30void BOARD_InitBootClocks(void);
31
32#if defined(__cplusplus)
33}
34#endif /* __cplusplus*/
35
36/*******************************************************************************
37 ********************** Configuration BOARD_BootClockRUN ***********************
38 ******************************************************************************/
39/*******************************************************************************
40 * Definitions for BOARD_BootClockRUN configuration
41 ******************************************************************************/
42#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
43
44/* Clock outputs (values are in Hz): */
45#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
46#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
47#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
48#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
49#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
51#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
52#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
53#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
54#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
55#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
56#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
57#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
58#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
59#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
60#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
61#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
62#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
63#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
64#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
65#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
66#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
67#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
68#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
69#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
70#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
71#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
72#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
73#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
74#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
76#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
77#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
78#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
79#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
80#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
81#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
82#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
83#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
84#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
85#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
86#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
87#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
88#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
89#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
90
91/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
92 */
93extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
94/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
95 */
96extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
97/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
98 */
99extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
100/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
101 */
102extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
103
104/*******************************************************************************
105 * API for BOARD_BootClockRUN configuration
106 ******************************************************************************/
107#if defined(__cplusplus)
108extern "C" {
109#endif /* __cplusplus*/
110
111/*!
112 * @brief This function executes configuration of clocks.
113 *
114 */
115void BOARD_BootClockRUN(void);
116
117#if defined(__cplusplus)
118}
119#endif /* __cplusplus*/
120
121#endif /* _CLOCK_CONFIG_H_ */
122
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.c
new file mode 100644
index 000000000..c3b2132a4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.c
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#include "dcd.h"
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.xip_board"
18#endif
19
20#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
21#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
22#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
23__attribute__((section(".boot_hdr.dcd_data"), used))
24#elif defined(__ICCARM__)
25#pragma location = ".boot_hdr.dcd_data"
26#endif
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29!!GlobalInfo
30product: DCDx V2.0
31processor: MIMXRT1052xxxxB
32package_id: MIMXRT1052DVL6B
33mcu_data: ksdk2_0
34processor_version: 0.0.0
35board: IMXRT1050-EVKB
36output_format: c_array
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
39const uint8_t dcd_data[] = {
40 /* HEADER */
41 /* Tag */
42 0xD2,
43 /* Image Length */
44 0x04, 0x10,
45 /* Version */
46 0x41,
47
48 /* COMMANDS */
49
50 /* group: 'Imported Commands' */
51 /* #1.1-113, command header bytes for merged 'Write - value' command */
52 0xCC, 0x03, 0x8C, 0x04,
53 /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
54 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
55 /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
56 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
57 /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
58 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
59 /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
60 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
61 /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
62 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
63 /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
64 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
65 /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
66 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
67 /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
68 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
69 /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
70 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
71 /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
72 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
73 /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
74 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
75 /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
76 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
77 /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
78 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
79 /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
80 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
81 /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
82 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
83 /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
84 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
85 /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
86 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
87 /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
88 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
89 /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
90 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
91 /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
92 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
93 /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
94 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
95 /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
96 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
97 /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
98 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
99 /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
100 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
101 /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
102 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
103 /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
104 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
105 /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
106 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
107 /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
108 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
109 /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
110 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
111 /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
112 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
113 /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
114 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
115 /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
116 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
117 /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
118 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
119 /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
120 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
121 /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
122 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
123 /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
124 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
125 /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
126 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
127 /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
128 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
129 /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
130 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
131 /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
132 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
133 /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
134 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
135 /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
136 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
137 /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
138 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
139 /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
140 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
141 /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
142 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
143 /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
144 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
145 /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
146 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
147 /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
148 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
149 /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
150 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
151 /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
152 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
153 /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
154 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
155 /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
156 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
157 /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
158 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
159 /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
160 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
161 /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
162 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
163 /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
164 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
165 /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
166 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
167 /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
168 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
169 /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
170 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
171 /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
172 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
173 /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
174 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
175 /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
176 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
177 /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
178 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
179 /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
180 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
181 /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
182 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
183 /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
184 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
185 /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
186 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
187 /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
188 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
189 /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
190 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
191 /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
192 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
193 /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
194 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
195 /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
196 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
197 /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
198 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
199 /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
200 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
201 /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
202 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
203 /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
204 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
205 /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
206 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
207 /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
208 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
209 /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
210 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
211 /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
212 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
213 /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
214 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
215 /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
216 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
217 /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
218 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
219 /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
220 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
221 /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
222 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
223 /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
224 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
225 /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
226 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
227 /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
228 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
229 /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
230 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
231 /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
232 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
233 /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
234 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
235 /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
236 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
237 /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
238 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
239 /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
240 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
241 /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
242 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
243 /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
244 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
245 /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
246 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
247 /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
248 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
249 /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
250 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
251 /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
252 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
253 /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
254 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
255 /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
256 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
257 /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
258 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
259 /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
260 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
261 /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
262 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
263 /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
264 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
265 /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
266 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
267 /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
268 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
269 /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
270 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
271 /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
272 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
273 /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
274 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
275 /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
276 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
277 /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
278 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
279 /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
280 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
281 /* #3.1-2, command header bytes for merged 'Write - value' command */
282 0xCC, 0x00, 0x14, 0x04,
283 /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
284 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
285 /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
286 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
287 /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
288 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
289 /* #5.1-2, command header bytes for merged 'Write - value' command */
290 0xCC, 0x00, 0x14, 0x04,
291 /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
292 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
293 /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
294 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
295 /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
296 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
297 /* #7.1-3, command header bytes for merged 'Write - value' command */
298 0xCC, 0x00, 0x1C, 0x04,
299 /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
300 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
301 /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
302 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
303 /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
304 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
305 /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
306 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
307 /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
308 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
309 };
310/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
311
312#else
313const uint8_t dcd_data[] = {0x00};
314#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
315#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.h
new file mode 100644
index 000000000..185b0ecd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/dcd.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef __DCD__
14#define __DCD__
15
16#include <stdint.h>
17
18/*! @name Driver version */
19/*@{*/
20/*! @brief XIP_BOARD driver version 2.0.1. */
21#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22/*@}*/
23
24/*************************************
25 * DCD Data
26 *************************************/
27#define DCD_TAG_HEADER (0xD2)
28#define DCD_VERSION (0x41)
29#define DCD_TAG_HEADER_SHIFT (24)
30#define DCD_ARRAY_SIZE 1
31
32#endif /* __DCD__ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.c
new file mode 100644
index 000000000..0f4335c31
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.c
@@ -0,0 +1,381 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15/*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19/*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23/* Get debug console frequency. */
24uint32_t BOARD_DebugConsoleSrcFreq(void)
25{
26 uint32_t freq;
27
28 /* To make it simple, we assume default PLL and divider settings, and the only variable
29 from application is use PLL3 source or OSC source */
30 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
31 {
32 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
33 }
34 else
35 {
36 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
37 }
38
39 return freq;
40}
41
42/* Initialize debug console. */
43void BOARD_InitDebugConsole(void)
44{
45 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
46
47 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
48}
49
50#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
51void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
52{
53 lpi2c_master_config_t lpi2cConfig = {0};
54
55 /*
56 * lpi2cConfig.debugEnable = false;
57 * lpi2cConfig.ignoreAck = false;
58 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
59 * lpi2cConfig.baudRate_Hz = 100000U;
60 * lpi2cConfig.busIdleTimeout_ns = 0;
61 * lpi2cConfig.pinLowTimeout_ns = 0;
62 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
63 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
64 */
65 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
66 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
67}
68
69status_t BOARD_LPI2C_Send(LPI2C_Type *base,
70 uint8_t deviceAddress,
71 uint32_t subAddress,
72 uint8_t subAddressSize,
73 uint8_t *txBuff,
74 uint8_t txBuffSize)
75{
76 lpi2c_master_transfer_t xfer;
77
78 xfer.flags = kLPI2C_TransferDefaultFlag;
79 xfer.slaveAddress = deviceAddress;
80 xfer.direction = kLPI2C_Write;
81 xfer.subaddress = subAddress;
82 xfer.subaddressSize = subAddressSize;
83 xfer.data = txBuff;
84 xfer.dataSize = txBuffSize;
85
86 return LPI2C_MasterTransferBlocking(base, &xfer);
87}
88
89status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
90 uint8_t deviceAddress,
91 uint32_t subAddress,
92 uint8_t subAddressSize,
93 uint8_t *rxBuff,
94 uint8_t rxBuffSize)
95{
96 lpi2c_master_transfer_t xfer;
97
98 xfer.flags = kLPI2C_TransferDefaultFlag;
99 xfer.slaveAddress = deviceAddress;
100 xfer.direction = kLPI2C_Read;
101 xfer.subaddress = subAddress;
102 xfer.subaddressSize = subAddressSize;
103 xfer.data = rxBuff;
104 xfer.dataSize = rxBuffSize;
105
106 return LPI2C_MasterTransferBlocking(base, &xfer);
107}
108
109status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
110 uint8_t deviceAddress,
111 uint32_t subAddress,
112 uint8_t subAddressSize,
113 uint8_t *txBuff,
114 uint8_t txBuffSize)
115{
116 lpi2c_master_transfer_t xfer;
117
118 xfer.flags = kLPI2C_TransferDefaultFlag;
119 xfer.slaveAddress = deviceAddress;
120 xfer.direction = kLPI2C_Write;
121 xfer.subaddress = subAddress;
122 xfer.subaddressSize = subAddressSize;
123 xfer.data = txBuff;
124 xfer.dataSize = txBuffSize;
125
126 return LPI2C_MasterTransferBlocking(base, &xfer);
127}
128
129status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subAddressSize,
133 uint8_t *rxBuff,
134 uint8_t rxBuffSize)
135{
136 status_t status;
137 lpi2c_master_transfer_t xfer;
138
139 xfer.flags = kLPI2C_TransferDefaultFlag;
140 xfer.slaveAddress = deviceAddress;
141 xfer.direction = kLPI2C_Write;
142 xfer.subaddress = subAddress;
143 xfer.subaddressSize = subAddressSize;
144 xfer.data = NULL;
145 xfer.dataSize = 0;
146
147 status = LPI2C_MasterTransferBlocking(base, &xfer);
148
149 if (kStatus_Success == status)
150 {
151 xfer.subaddressSize = 0;
152 xfer.direction = kLPI2C_Read;
153 xfer.data = rxBuff;
154 xfer.dataSize = rxBuffSize;
155
156 status = LPI2C_MasterTransferBlocking(base, &xfer);
157 }
158
159 return status;
160}
161
162void BOARD_Accel_I2C_Init(void)
163{
164 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
165}
166
167status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
168{
169 uint8_t data = (uint8_t)txBuff;
170
171 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
172}
173
174status_t BOARD_Accel_I2C_Receive(
175 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
176{
177 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
178}
179
180void BOARD_Codec_I2C_Init(void)
181{
182 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
183}
184
185status_t BOARD_Codec_I2C_Send(
186 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
187{
188 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
189 txBuffSize);
190}
191
192status_t BOARD_Codec_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
194{
195 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
196}
197
198void BOARD_Camera_I2C_Init(void)
199{
200 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
201 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
202 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
203}
204
205status_t BOARD_Camera_I2C_Send(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
207{
208 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
209 txBuffSize);
210}
211
212status_t BOARD_Camera_I2C_Receive(
213 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
214{
215 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
216 rxBuffSize);
217}
218
219status_t BOARD_Camera_I2C_SendSCCB(
220 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
221{
222 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
223 txBuffSize);
224}
225
226status_t BOARD_Camera_I2C_ReceiveSCCB(
227 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
228{
229 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
230 rxBuffSize);
231}
232#endif /* SDK_I2C_BASED_COMPONENT_USED */
233
234/* MPU configuration. */
235void BOARD_ConfigMPU(void)
236{
237#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
238 extern uint32_t Image$$RW_m_ncache$$Base[];
239 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
240 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
241 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
242 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
243 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
244 0 :
245 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
246#elif defined(__MCUXPRESSO)
247 extern uint32_t __base_NCACHE_REGION;
248 extern uint32_t __top_NCACHE_REGION;
249 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
250 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
251#elif defined(__ICCARM__) || defined(__GNUC__)
252 extern uint32_t __NCACHE_REGION_START[];
253 extern uint32_t __NCACHE_REGION_SIZE[];
254 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
255 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
256#endif
257 volatile uint32_t i = 0;
258
259 /* Disable I cache and D cache */
260 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
261 {
262 SCB_DisableICache();
263 }
264 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
265 {
266 SCB_DisableDCache();
267 }
268
269 /* Disable MPU */
270 ARM_MPU_Disable();
271
272 /* MPU configure:
273 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
274 * SubRegionDisable, Size)
275 * API in mpu_armv7.h.
276 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
277 * disabled.
278 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
279 * Privileged mode.
280 * Use MACROS defined in mpu_armv7.h:
281 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
282 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
283 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
284 * 0 x 0 0 Strongly Ordered shareable
285 * 0 x 0 1 Device shareable
286 * 0 0 1 0 Normal not shareable Outer and inner write
287 * through no write allocate
288 * 0 0 1 1 Normal not shareable Outer and inner write
289 * back no write allocate
290 * 0 1 1 0 Normal shareable Outer and inner write
291 * through no write allocate
292 * 0 1 1 1 Normal shareable Outer and inner write
293 * back no write allocate
294 * 1 0 0 0 Normal not shareable outer and inner
295 * noncache
296 * 1 1 0 0 Normal shareable outer and inner
297 * noncache
298 * 1 0 1 1 Normal not shareable outer and inner write
299 * back write/read acllocate
300 * 1 1 1 1 Normal shareable outer and inner write
301 * back write/read acllocate
302 * 2 x 0 0 Device not shareable
303 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
304 * policy.
305 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
306 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
307 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
308 * mpu_armv7.h.
309 */
310
311 /*
312 * Add default region to deny access to whole address space to workaround speculative prefetch.
313 * Refer to Arm errata 1013783-B for more details.
314 *
315 */
316 /* Region 0 setting: Instruction access disabled, No data access permission. */
317 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
318 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
319
320 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
321 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
322 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
323
324 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
325 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
326 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
327
328#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
329 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
330 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
332#endif
333
334 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
335 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
336 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
337
338 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
339 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
340 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
341
342 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
343 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
345
346 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
347 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
348 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
349
350 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
351 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
352 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
353
354 while ((size >> i) > 0x1U)
355 {
356 i++;
357 }
358
359 if (i != 0)
360 {
361 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
362 assert(!(nonCacheStart % size));
363 assert(size == (uint32_t)(1 << i));
364 assert(i >= 5);
365
366 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
367 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
368 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
369 }
370
371 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
372 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
373 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
374
375 /* Enable MPU */
376 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
377
378 /* Enable I cache and D cache */
379 SCB_EnableDCache();
380 SCB_EnableICache();
381}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.h
new file mode 100644
index 000000000..6f77eea30
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/board.h
@@ -0,0 +1,215 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14#include "fsl_clock.h"
15
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19/*! @brief The board name */
20#define BOARD_NAME "IMXRT1050-EVKB"
21
22/* The UART to use for debug messages. */
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
25#define BOARD_DEBUG_UART_INSTANCE 1U
26
27#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
28
29#define BOARD_UART_IRQ LPUART1_IRQn
30#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
31
32#ifndef BOARD_DEBUG_UART_BAUDRATE
33#define BOARD_DEBUG_UART_BAUDRATE (115200U)
34#endif /* BOARD_DEBUG_UART_BAUDRATE */
35
36/*! @brief The USER_LED used for board */
37#define LOGIC_LED_ON (0U)
38#define LOGIC_LED_OFF (1U)
39#ifndef BOARD_USER_LED_GPIO
40#define BOARD_USER_LED_GPIO GPIO1
41#endif
42#ifndef BOARD_USER_LED_GPIO_PIN
43#define BOARD_USER_LED_GPIO_PIN (9U)
44#endif
45
46#define USER_LED_INIT(output) \
47 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
48 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
49#define USER_LED_ON() \
50 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
51#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
52#define USER_LED_TOGGLE() \
53 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
54 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
55
56/*! @brief Define the port interrupt number for the board switches */
57#ifndef BOARD_USER_BUTTON_GPIO
58#define BOARD_USER_BUTTON_GPIO GPIO5
59#endif
60#ifndef BOARD_USER_BUTTON_GPIO_PIN
61#define BOARD_USER_BUTTON_GPIO_PIN (0U)
62#endif
63#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
64#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
65#define BOARD_USER_BUTTON_NAME "SW8"
66
67/*! @brief The hyper flash size */
68#define BOARD_FLASH_SIZE (0x4000000U)
69
70/*! @brief The ENET PHY address. */
71#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
72
73/* USB PHY condfiguration */
74#define BOARD_USB_PHY_D_CAL (0x0CU)
75#define BOARD_USB_PHY_TXCAL45DP (0x06U)
76#define BOARD_USB_PHY_TXCAL45DM (0x06U)
77
78#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
79#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
80#define BOARD_ARDUINO_I2C_INDEX (1)
81
82#define BOARD_HAS_SDCARD (1U)
83
84/*! @brief The WIFI-QCA shield pin. */
85#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
86#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
87#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
88#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
89#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
90#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
91#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
92
93#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
94#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
95#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
96#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
97#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
98#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
99#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
100
101/*! @brief The WIFI-QCA Silex 2401 shield pin. */
102#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
103#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
104#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
105#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
106#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
107#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
108#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
109
110#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
111#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
112#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
113#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
114#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
115#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
116#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
117
118/* @Brief Board accelerator sensor configuration */
119#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
120/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
121#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
122/* Clock divider for LPI2C clock source */
123#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
124#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
125
126#define BOARD_CODEC_I2C_BASEADDR LPI2C1
127#define BOARD_CODEC_I2C_INSTANCE 1U
128#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
129#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
130#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
131
132/* @Brief Board CAMERA configuration */
133#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
134#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
135#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
136#define BOARD_CAMERA_I2C_CLOCK_FREQ \
137 (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
138
139#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
140#define BOARD_CAMERA_I2C_SCL_PIN 16
141#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
142#define BOARD_CAMERA_I2C_SDA_PIN 17
143#define BOARD_CAMERA_PWDN_GPIO GPIO1
144#define BOARD_CAMERA_PWDN_PIN 4
145
146/* @Brief Board Bluetooth HCI UART configuration */
147#define BOARD_BT_UART_BASEADDR LPUART3
148#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
149#define BOARD_BT_UART_IRQ LPUART3_IRQn
150#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
151
152#if defined(__cplusplus)
153extern "C" {
154#endif /* __cplusplus */
155
156/*******************************************************************************
157 * API
158 ******************************************************************************/
159uint32_t BOARD_DebugConsoleSrcFreq(void);
160
161void BOARD_InitDebugConsole(void);
162
163void BOARD_ConfigMPU(void);
164#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
165void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
166status_t BOARD_LPI2C_Send(LPI2C_Type *base,
167 uint8_t deviceAddress,
168 uint32_t subAddress,
169 uint8_t subaddressSize,
170 uint8_t *txBuff,
171 uint8_t txBuffSize);
172status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
173 uint8_t deviceAddress,
174 uint32_t subAddress,
175 uint8_t subaddressSize,
176 uint8_t *rxBuff,
177 uint8_t rxBuffSize);
178status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
179 uint8_t deviceAddress,
180 uint32_t subAddress,
181 uint8_t subaddressSize,
182 uint8_t *txBuff,
183 uint8_t txBuffSize);
184status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
185 uint8_t deviceAddress,
186 uint32_t subAddress,
187 uint8_t subaddressSize,
188 uint8_t *rxBuff,
189 uint8_t rxBuffSize);
190void BOARD_Accel_I2C_Init(void);
191status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
192status_t BOARD_Accel_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
194void BOARD_Codec_I2C_Init(void);
195status_t BOARD_Codec_I2C_Send(
196 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
197status_t BOARD_Codec_I2C_Receive(
198 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
199void BOARD_Camera_I2C_Init(void);
200status_t BOARD_Camera_I2C_Send(
201 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
202status_t BOARD_Camera_I2C_Receive(
203 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
204
205status_t BOARD_Camera_I2C_SendSCCB(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
207status_t BOARD_Camera_I2C_ReceiveSCCB(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
209#endif /* SDK_I2C_BASED_COMPONENT_USED */
210
211#if defined(__cplusplus)
212}
213#endif /* __cplusplus */
214
215#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.c
new file mode 100644
index 000000000..2ed6638cb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.c
@@ -0,0 +1,471 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1052xxxxB
27package_id: MIMXRT1052DVL6B
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: IMXRT1050-EVKB
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
70- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
71- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
72- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
73- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
74- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
75- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
76- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
77- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
78- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
79- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
80- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
81- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
82- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
83- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
84- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
85- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
86- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
87- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
88- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
89- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
90- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
94- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
95- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
96- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
97- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
98- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
99- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
100settings:
101- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
102- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
103- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
104- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
105- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
106- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
107- {id: CCM.SEMC_PODF.scale, value: '8'}
108- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
109- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
110- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
111- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
112- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
113- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
114- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
115- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
116- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
117- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
118- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
119- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
120- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
121- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
122- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
123- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
124- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
125- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL5.denom, value: '1'}
129- {id: CCM_ANALOG.PLL5.div, value: '40'}
130- {id: CCM_ANALOG.PLL5.num, value: '0'}
131- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
132- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
133sources:
134- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
135- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
136 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
137
138/*******************************************************************************
139 * Variables for BOARD_BootClockRUN configuration
140 ******************************************************************************/
141const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
142 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
143 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
144};
145const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
146 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
147 .numerator = 0, /* 30 bit numerator of fractional loop divider */
148 .denominator = 1, /* 30 bit denominator of fractional loop divider */
149 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
150};
151const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
152 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
153 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
154};
155/*******************************************************************************
156 * Code for BOARD_BootClockRUN configuration
157 ******************************************************************************/
158void BOARD_BootClockRUN(void)
159{
160 /* Init RTC OSC clock frequency. */
161 CLOCK_SetRtcXtalFreq(32768U);
162 /* Enable 1MHz clock output. */
163 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
164 /* Use free 1MHz clock output. */
165 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
166 /* Set XTAL 24MHz clock frequency. */
167 CLOCK_SetXtalFreq(24000000U);
168 /* Enable XTAL 24MHz clock source. */
169 CLOCK_InitExternalClk(0);
170 /* Enable internal RC. */
171 CLOCK_InitRcOsc24M();
172 /* Switch clock source to external OSC. */
173 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
174 /* Set Oscillator ready counter value. */
175 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
176 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
177 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
178 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
179 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
180 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
181 /* Waiting for DCDC_STS_DC_OK bit is asserted */
182 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
183 {
184 }
185 /* Set AHB_PODF. */
186 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
187 /* Disable IPG clock gate. */
188 CLOCK_DisableClock(kCLOCK_Adc1);
189 CLOCK_DisableClock(kCLOCK_Adc2);
190 CLOCK_DisableClock(kCLOCK_Xbar1);
191 CLOCK_DisableClock(kCLOCK_Xbar2);
192 CLOCK_DisableClock(kCLOCK_Xbar3);
193 /* Set IPG_PODF. */
194 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
195 /* Set ARM_PODF. */
196 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
197 /* Set PERIPH_CLK2_PODF. */
198 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
199 /* Disable PERCLK clock gate. */
200 CLOCK_DisableClock(kCLOCK_Gpt1);
201 CLOCK_DisableClock(kCLOCK_Gpt1S);
202 CLOCK_DisableClock(kCLOCK_Gpt2);
203 CLOCK_DisableClock(kCLOCK_Gpt2S);
204 CLOCK_DisableClock(kCLOCK_Pit);
205 /* Set PERCLK_PODF. */
206 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
207 /* Disable USDHC1 clock gate. */
208 CLOCK_DisableClock(kCLOCK_Usdhc1);
209 /* Set USDHC1_PODF. */
210 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
211 /* Set Usdhc1 clock source. */
212 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
213 /* Disable USDHC2 clock gate. */
214 CLOCK_DisableClock(kCLOCK_Usdhc2);
215 /* Set USDHC2_PODF. */
216 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
217 /* Set Usdhc2 clock source. */
218 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
219/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
220 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
221 * unchanged.
222 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
223#ifndef SKIP_SYSCLK_INIT
224 /* Disable Semc clock gate. */
225 CLOCK_DisableClock(kCLOCK_Semc);
226 /* Set SEMC_PODF. */
227 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
228 /* Set Semc alt clock source. */
229 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
230 /* Set Semc clock source. */
231 CLOCK_SetMux(kCLOCK_SemcMux, 0);
232#endif
233/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
234 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
235 * unchanged.
236 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
237#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
238 /* Disable Flexspi clock gate. */
239 CLOCK_DisableClock(kCLOCK_FlexSpi);
240 /* Set FLEXSPI_PODF. */
241 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
242 /* Set Flexspi clock source. */
243 CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
244#endif
245 /* Disable CSI clock gate. */
246 CLOCK_DisableClock(kCLOCK_Csi);
247 /* Set CSI_PODF. */
248 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
249 /* Set Csi clock source. */
250 CLOCK_SetMux(kCLOCK_CsiMux, 0);
251 /* Disable LPSPI clock gate. */
252 CLOCK_DisableClock(kCLOCK_Lpspi1);
253 CLOCK_DisableClock(kCLOCK_Lpspi2);
254 CLOCK_DisableClock(kCLOCK_Lpspi3);
255 CLOCK_DisableClock(kCLOCK_Lpspi4);
256 /* Set LPSPI_PODF. */
257 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
258 /* Set Lpspi clock source. */
259 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
260 /* Disable TRACE clock gate. */
261 CLOCK_DisableClock(kCLOCK_Trace);
262 /* Set TRACE_PODF. */
263 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
264 /* Set Trace clock source. */
265 CLOCK_SetMux(kCLOCK_TraceMux, 2);
266 /* Disable SAI1 clock gate. */
267 CLOCK_DisableClock(kCLOCK_Sai1);
268 /* Set SAI1_CLK_PRED. */
269 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
270 /* Set SAI1_CLK_PODF. */
271 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
272 /* Set Sai1 clock source. */
273 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
274 /* Disable SAI2 clock gate. */
275 CLOCK_DisableClock(kCLOCK_Sai2);
276 /* Set SAI2_CLK_PRED. */
277 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
278 /* Set SAI2_CLK_PODF. */
279 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
280 /* Set Sai2 clock source. */
281 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
282 /* Disable SAI3 clock gate. */
283 CLOCK_DisableClock(kCLOCK_Sai3);
284 /* Set SAI3_CLK_PRED. */
285 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
286 /* Set SAI3_CLK_PODF. */
287 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
288 /* Set Sai3 clock source. */
289 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
290 /* Disable Lpi2c clock gate. */
291 CLOCK_DisableClock(kCLOCK_Lpi2c1);
292 CLOCK_DisableClock(kCLOCK_Lpi2c2);
293 CLOCK_DisableClock(kCLOCK_Lpi2c3);
294 /* Set LPI2C_CLK_PODF. */
295 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
296 /* Set Lpi2c clock source. */
297 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
298 /* Disable CAN clock gate. */
299 CLOCK_DisableClock(kCLOCK_Can1);
300 CLOCK_DisableClock(kCLOCK_Can2);
301 CLOCK_DisableClock(kCLOCK_Can1S);
302 CLOCK_DisableClock(kCLOCK_Can2S);
303 /* Set CAN_CLK_PODF. */
304 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
305 /* Set Can clock source. */
306 CLOCK_SetMux(kCLOCK_CanMux, 2);
307 /* Disable UART clock gate. */
308 CLOCK_DisableClock(kCLOCK_Lpuart1);
309 CLOCK_DisableClock(kCLOCK_Lpuart2);
310 CLOCK_DisableClock(kCLOCK_Lpuart3);
311 CLOCK_DisableClock(kCLOCK_Lpuart4);
312 CLOCK_DisableClock(kCLOCK_Lpuart5);
313 CLOCK_DisableClock(kCLOCK_Lpuart6);
314 CLOCK_DisableClock(kCLOCK_Lpuart7);
315 CLOCK_DisableClock(kCLOCK_Lpuart8);
316 /* Set UART_CLK_PODF. */
317 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
318 /* Set Uart clock source. */
319 CLOCK_SetMux(kCLOCK_UartMux, 0);
320 /* Disable LCDIF clock gate. */
321 CLOCK_DisableClock(kCLOCK_LcdPixel);
322 /* Set LCDIF_PRED. */
323 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
324 /* Set LCDIF_CLK_PODF. */
325 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
326 /* Set Lcdif pre clock source. */
327 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
328 /* Disable SPDIF clock gate. */
329 CLOCK_DisableClock(kCLOCK_Spdif);
330 /* Set SPDIF0_CLK_PRED. */
331 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
332 /* Set SPDIF0_CLK_PODF. */
333 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
334 /* Set Spdif clock source. */
335 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
336 /* Disable Flexio1 clock gate. */
337 CLOCK_DisableClock(kCLOCK_Flexio1);
338 /* Set FLEXIO1_CLK_PRED. */
339 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
340 /* Set FLEXIO1_CLK_PODF. */
341 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
342 /* Set Flexio1 clock source. */
343 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
344 /* Disable Flexio2 clock gate. */
345 CLOCK_DisableClock(kCLOCK_Flexio2);
346 /* Set FLEXIO2_CLK_PRED. */
347 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
348 /* Set FLEXIO2_CLK_PODF. */
349 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
350 /* Set Flexio2 clock source. */
351 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
352 /* Set Pll3 sw clock source. */
353 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
354 /* Init ARM PLL. */
355 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
356 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
357 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
358 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
359 * well.*/
360#ifndef SKIP_SYSCLK_INIT
361 /* Init System PLL. */
362 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
363 /* Init System pfd0. */
364 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
365 /* Init System pfd1. */
366 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
367 /* Init System pfd2. */
368 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
369 /* Init System pfd3. */
370 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
371 /* Disable pfd offset. */
372 CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
373#endif
374 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
375 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
376 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
377 * well.*/
378#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
379 /* Init Usb1 PLL. */
380 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
381 /* Init Usb1 pfd0. */
382 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
383 /* Init Usb1 pfd1. */
384 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
385 /* Init Usb1 pfd2. */
386 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
387 /* Init Usb1 pfd3. */
388 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
389 /* Disable Usb1 PLL output for USBPHY1. */
390 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
391#endif
392 /* DeInit Audio PLL. */
393 CLOCK_DeinitAudioPll();
394 /* Bypass Audio PLL. */
395 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
396 /* Set divider for Audio PLL. */
397 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
398 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
399 /* Enable Audio PLL output. */
400 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
401 /* DeInit Video PLL. */
402 CLOCK_DeinitVideoPll();
403 /* Bypass Video PLL. */
404 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
405 /* Set divider for Video PLL. */
406 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
407 /* Enable Video PLL output. */
408 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
409 /* DeInit Enet PLL. */
410 CLOCK_DeinitEnetPll();
411 /* Bypass Enet PLL. */
412 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
413 /* Set Enet output divider. */
414 CCM_ANALOG->PLL_ENET =
415 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
416 /* Enable Enet output. */
417 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
418 /* Enable Enet25M output. */
419 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
420 /* DeInit Usb2 PLL. */
421 CLOCK_DeinitUsb2Pll();
422 /* Bypass Usb2 PLL. */
423 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
424 /* Enable Usb2 PLL output. */
425 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
426 /* Set preperiph clock source. */
427 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
428 /* Set periph clock source. */
429 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
430 /* Set periph clock2 clock source. */
431 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
432 /* Set per clock source. */
433 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
434 /* Set lvds1 clock source. */
435 CCM_ANALOG->MISC1 =
436 (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
437 /* Set clock out1 divider. */
438 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
439 /* Set clock out1 source. */
440 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
441 /* Set clock out2 divider. */
442 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
443 /* Set clock out2 source. */
444 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
445 /* Set clock out1 drives clock out1. */
446 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
447 /* Disable clock out1. */
448 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
449 /* Disable clock out2. */
450 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
451 /* Set SAI1 MCLK1 clock source. */
452 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
453 /* Set SAI1 MCLK2 clock source. */
454 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
455 /* Set SAI1 MCLK3 clock source. */
456 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
457 /* Set SAI2 MCLK3 clock source. */
458 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
459 /* Set SAI3 MCLK3 clock source. */
460 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
461 /* Set MQS configuration. */
462 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
463 /* Set ENET Tx clock source. */
464 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
465 /* Set GPT1 High frequency reference clock source. */
466 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
467 /* Set GPT2 High frequency reference clock source. */
468 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
469 /* Set SystemCoreClock variable. */
470 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
471}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.h
new file mode 100644
index 000000000..f213ac7e2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/clock_config.h
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
47#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
48#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
49#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
51#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
52#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
53#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
54#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
55#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
56#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
57#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
58#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
59#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
60#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
61#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
62#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
63#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
64#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
65#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
66#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
67#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
68#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
69#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
70#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
71#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
72#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
73#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
74#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
76#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
77#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
78#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
79#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
80#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
81#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
82#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
83#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
84#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
85#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
86#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
87#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
88#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
89#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
90#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
91
92/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
93 */
94extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
95/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
96 */
97extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
98/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
99 */
100extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
101
102/*******************************************************************************
103 * API for BOARD_BootClockRUN configuration
104 ******************************************************************************/
105#if defined(__cplusplus)
106extern "C" {
107#endif /* __cplusplus*/
108
109/*!
110 * @brief This function executes configuration of clocks.
111 *
112 */
113void BOARD_BootClockRUN(void);
114
115#if defined(__cplusplus)
116}
117#endif /* __cplusplus*/
118
119#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.c
new file mode 100644
index 000000000..c3b2132a4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.c
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#include "dcd.h"
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.xip_board"
18#endif
19
20#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
21#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
22#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
23__attribute__((section(".boot_hdr.dcd_data"), used))
24#elif defined(__ICCARM__)
25#pragma location = ".boot_hdr.dcd_data"
26#endif
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29!!GlobalInfo
30product: DCDx V2.0
31processor: MIMXRT1052xxxxB
32package_id: MIMXRT1052DVL6B
33mcu_data: ksdk2_0
34processor_version: 0.0.0
35board: IMXRT1050-EVKB
36output_format: c_array
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
39const uint8_t dcd_data[] = {
40 /* HEADER */
41 /* Tag */
42 0xD2,
43 /* Image Length */
44 0x04, 0x10,
45 /* Version */
46 0x41,
47
48 /* COMMANDS */
49
50 /* group: 'Imported Commands' */
51 /* #1.1-113, command header bytes for merged 'Write - value' command */
52 0xCC, 0x03, 0x8C, 0x04,
53 /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
54 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
55 /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
56 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
57 /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
58 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
59 /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
60 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
61 /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
62 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
63 /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
64 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
65 /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
66 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
67 /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
68 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
69 /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
70 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
71 /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
72 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
73 /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
74 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
75 /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
76 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
77 /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
78 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
79 /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
80 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
81 /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
82 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
83 /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
84 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
85 /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
86 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
87 /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
88 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
89 /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
90 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
91 /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
92 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
93 /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
94 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
95 /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
96 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
97 /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
98 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
99 /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
100 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
101 /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
102 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
103 /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
104 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
105 /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
106 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
107 /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
108 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
109 /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
110 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
111 /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
112 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
113 /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
114 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
115 /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
116 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
117 /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
118 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
119 /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
120 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
121 /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
122 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
123 /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
124 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
125 /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
126 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
127 /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
128 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
129 /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
130 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
131 /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
132 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
133 /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
134 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
135 /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
136 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
137 /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
138 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
139 /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
140 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
141 /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
142 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
143 /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
144 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
145 /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
146 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
147 /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
148 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
149 /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
150 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
151 /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
152 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
153 /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
154 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
155 /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
156 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
157 /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
158 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
159 /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
160 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
161 /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
162 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
163 /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
164 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
165 /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
166 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
167 /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
168 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
169 /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
170 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
171 /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
172 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
173 /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
174 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
175 /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
176 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
177 /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
178 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
179 /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
180 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
181 /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
182 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
183 /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
184 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
185 /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
186 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
187 /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
188 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
189 /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
190 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
191 /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
192 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
193 /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
194 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
195 /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
196 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
197 /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
198 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
199 /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
200 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
201 /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
202 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
203 /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
204 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
205 /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
206 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
207 /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
208 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
209 /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
210 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
211 /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
212 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
213 /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
214 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
215 /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
216 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
217 /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
218 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
219 /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
220 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
221 /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
222 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
223 /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
224 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
225 /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
226 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
227 /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
228 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
229 /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
230 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
231 /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
232 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
233 /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
234 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
235 /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
236 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
237 /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
238 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
239 /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
240 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
241 /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
242 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
243 /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
244 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
245 /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
246 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
247 /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
248 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
249 /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
250 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
251 /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
252 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
253 /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
254 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
255 /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
256 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
257 /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
258 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
259 /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
260 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
261 /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
262 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
263 /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
264 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
265 /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
266 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
267 /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
268 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
269 /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
270 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
271 /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
272 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
273 /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
274 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
275 /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
276 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
277 /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
278 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
279 /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
280 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
281 /* #3.1-2, command header bytes for merged 'Write - value' command */
282 0xCC, 0x00, 0x14, 0x04,
283 /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
284 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
285 /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
286 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
287 /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
288 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
289 /* #5.1-2, command header bytes for merged 'Write - value' command */
290 0xCC, 0x00, 0x14, 0x04,
291 /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
292 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
293 /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
294 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
295 /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
296 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
297 /* #7.1-3, command header bytes for merged 'Write - value' command */
298 0xCC, 0x00, 0x1C, 0x04,
299 /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
300 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
301 /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
302 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
303 /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
304 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
305 /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
306 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
307 /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
308 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
309 };
310/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
311
312#else
313const uint8_t dcd_data[] = {0x00};
314#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
315#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.h
new file mode 100644
index 000000000..185b0ecd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/dcd.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef __DCD__
14#define __DCD__
15
16#include <stdint.h>
17
18/*! @name Driver version */
19/*@{*/
20/*! @brief XIP_BOARD driver version 2.0.1. */
21#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22/*@}*/
23
24/*************************************
25 * DCD Data
26 *************************************/
27#define DCD_TAG_HEADER (0xD2)
28#define DCD_VERSION (0x41)
29#define DCD_TAG_HEADER_SHIFT (24)
30#define DCD_ARRAY_SIZE 1
31
32#endif /* __DCD__ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.c
new file mode 100644
index 000000000..66899c2f7
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v8.0
17processor: MIMXRT1052xxxxB
18package_id: MIMXRT1052DVL6B
19mcu_data: ksdk2_0
20processor_version: 0.8.2
21board: IMXRT1050-EVKB
22functionalGroups:
23- name: BOARD_InitPeripherals
24 UUID: a7525270-2da6-4556-8d91-4ab9d0edc0e2
25 called_from_default_init: true
26 selectedCore: core0
27 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
28/* clang-format on */
29
30/***********************************************************************************************************************
31 * Included files
32 **********************************************************************************************************************/
33#include "peripherals.h"
34
35/***********************************************************************************************************************
36 * Initialization functions
37 **********************************************************************************************************************/
38void BOARD_InitPeripherals(void)
39{
40}
41
42/***********************************************************************************************************************
43 * BOARD_InitBootPeripherals function
44 **********************************************************************************************************************/
45void BOARD_InitBootPeripherals(void)
46{
47 BOARD_InitPeripherals();
48}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.h
new file mode 100644
index 000000000..c2a309bb5
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/pin_mux.c
new file mode 100644
index 000000000..8e3021afc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkbimxrt1050/project_template/pin_mux.c
@@ -0,0 +1,1094 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v4.1
17processor: MIMXRT1052xxxxB
18package_id: MIMXRT1052DVL6B
19mcu_data: ksdk2_0
20processor_version: 4.0.0
21board: IMXRT1050-EVKB
22pin_labels:
23- {pin_num: E3, pin_signal: GPIO_EMC_00, label: SEMC_D0, identifier: SEMC_D0}
24- {pin_num: F3, pin_signal: GPIO_EMC_01, label: SEMC_D1, identifier: SEMC_D1}
25- {pin_num: F4, pin_signal: GPIO_EMC_02, label: SEMC_D2, identifier: SEMC_D2}
26- {pin_num: F2, pin_signal: GPIO_EMC_04, label: SEMC_D4, identifier: SEMC_D4}
27- {pin_num: G4, pin_signal: GPIO_EMC_03, label: SEMC_D3, identifier: SEMC_D3}
28- {pin_num: G5, pin_signal: GPIO_EMC_05, label: SEMC_D5, identifier: SEMC_D5}
29- {pin_num: H5, pin_signal: GPIO_EMC_06, label: SEMC_D6, identifier: SEMC_D6}
30- {pin_num: H4, pin_signal: GPIO_EMC_07, label: SEMC_D7, identifier: SEMC_D7}
31- {pin_num: H3, pin_signal: GPIO_EMC_08, label: SEMC_DM0, identifier: SEMC_DM0}
32- {pin_num: C2, pin_signal: GPIO_EMC_09, label: SEMC_A0, identifier: SEMC_A0}
33- {pin_num: G1, pin_signal: GPIO_EMC_10, label: SEMC_A1, identifier: SEMC_A1}
34- {pin_num: G3, pin_signal: GPIO_EMC_11, label: SEMC_A2, identifier: SEMC_A2}
35- {pin_num: H1, pin_signal: GPIO_EMC_12, label: SEMC_A3, identifier: SEMC_A3}
36- {pin_num: A6, pin_signal: GPIO_EMC_13, label: SEMC_A4, identifier: SEMC_A4}
37- {pin_num: B6, pin_signal: GPIO_EMC_14, label: SEMC_A5, identifier: SEMC_A5}
38- {pin_num: B1, pin_signal: GPIO_EMC_15, label: SEMC_A6, identifier: SEMC_A6}
39- {pin_num: A5, pin_signal: GPIO_EMC_16, label: SEMC_A7, identifier: SEMC_A7}
40- {pin_num: A4, pin_signal: GPIO_EMC_17, label: SEMC_A8, identifier: SEMC_A8}
41- {pin_num: B2, pin_signal: GPIO_EMC_18, label: SEMC_A9, identifier: SEMC_A9}
42- {pin_num: B4, pin_signal: GPIO_EMC_19, label: SEMC_A11, identifier: SEMC_A11}
43- {pin_num: G2, pin_signal: GPIO_EMC_23, label: SEMC_A10, identifier: SEMC_A10}
44- {pin_num: A3, pin_signal: GPIO_EMC_20, label: SEMC_A12, identifier: SEMC_A12}
45- {pin_num: C1, pin_signal: GPIO_EMC_21, label: SEMC_BA0, identifier: SEMC_BA0}
46- {pin_num: F1, pin_signal: GPIO_EMC_22, label: SEMC_BA1, identifier: SEMC_BA1}
47- {pin_num: D3, pin_signal: GPIO_EMC_24, label: SEMC_CAS, identifier: SEMC_CAS}
48- {pin_num: D2, pin_signal: GPIO_EMC_25, label: SEMC_RAS, identifier: SEMC_RAS}
49- {pin_num: B3, pin_signal: GPIO_EMC_26, label: SEMC_CLK, identifier: SEMC_CLK}
50- {pin_num: A2, pin_signal: GPIO_EMC_27, label: SEMC_CKE, identifier: SEMC_CKE}
51- {pin_num: D1, pin_signal: GPIO_EMC_28, label: SEMC_WE, identifier: SEMC_WE}
52- {pin_num: E1, pin_signal: GPIO_EMC_29, label: SEMC_CS0, identifier: SEMC_CS0}
53- {pin_num: C6, pin_signal: GPIO_EMC_30, label: SEMC_D8, identifier: SEMC_D8}
54- {pin_num: C5, pin_signal: GPIO_EMC_31, label: SEMC_D9, identifier: SEMC_D9}
55- {pin_num: D5, pin_signal: GPIO_EMC_32, label: SEMC_D10, identifier: SEMC_D10}
56- {pin_num: C4, pin_signal: GPIO_EMC_33, label: SEMC_D11, identifier: SEMC_D11}
57- {pin_num: D4, pin_signal: GPIO_EMC_34, label: SEMC_D12, identifier: SEMC_D12}
58- {pin_num: E5, pin_signal: GPIO_EMC_35, label: SEMC_D13, identifier: SEMC_D13}
59- {pin_num: C3, pin_signal: GPIO_EMC_36, label: SEMC_D14, identifier: SEMC_D14}
60- {pin_num: E4, pin_signal: GPIO_EMC_37, label: SEMC_D15, identifier: SEMC_D15}
61- {pin_num: D6, pin_signal: GPIO_EMC_38, label: SEMC_DM1, identifier: SEMC_DM1}
62- {pin_num: B7, pin_signal: GPIO_EMC_39, label: SEMC_DQS, identifier: SEMC_DQS}
63- {pin_num: A7, pin_signal: GPIO_EMC_40, label: ENET_MDC, identifier: ENET_MDC}
64- {pin_num: C7, pin_signal: GPIO_EMC_41, label: ENET_MDIO, identifier: ENET_MDIO}
65- {pin_num: D7, pin_signal: GPIO_B0_00, label: LCDIF_CLK, identifier: LCDIF_CLK}
66- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: LCDIF_ENABLE}
67- {pin_num: E8, pin_signal: GPIO_B0_02, label: LCDIF_HSYNC, identifier: LCDIF_HSYNC}
68- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: LCDIF_VSYNC}
69- {pin_num: C8, pin_signal: GPIO_B0_04, label: 'LCDIF_D0/BT_CFG[0]', identifier: LCDIF_D0}
70- {pin_num: B8, pin_signal: GPIO_B0_05, label: 'LCDIF_D1/BT_CFG[1]', identifier: LCDIF_D1}
71- {pin_num: A8, pin_signal: GPIO_B0_06, label: 'LCDIF_D2/BT_CFG[2]', identifier: LCDIF_D2}
72- {pin_num: A9, pin_signal: GPIO_B0_07, label: 'LCDIF_D3/BT_CFG[3]', identifier: LCDIF_D3}
73- {pin_num: B9, pin_signal: GPIO_B0_08, label: 'LCDIF_D4/BT_CFG[4]', identifier: LCDIF_D4}
74- {pin_num: C9, pin_signal: GPIO_B0_09, label: 'LCDIF_D5/BT_CFG[5]', identifier: LCDIF_D5}
75- {pin_num: D9, pin_signal: GPIO_B0_10, label: 'LCDIF_D6/BT_CFG[6]', identifier: LCDIF_D6}
76- {pin_num: A10, pin_signal: GPIO_B0_11, label: 'LCDIF_D7/BT_CFG[7]', identifier: LCDIF_D7}
77- {pin_num: C10, pin_signal: GPIO_B0_12, label: 'LCDIF_D8/BT_CFG[8]', identifier: LCDIF_D8}
78- {pin_num: D10, pin_signal: GPIO_B0_13, label: 'LCDIF_D9/BT_CFG[9]', identifier: LCDIF_D9}
79- {pin_num: E10, pin_signal: GPIO_B0_14, label: 'LCDIF_D10/BT_CFG[10]', identifier: LCDIF_D10}
80- {pin_num: E11, pin_signal: GPIO_B0_15, label: 'LCDIF_D11/BT_CFG[11]', identifier: LCDIF_D11}
81- {pin_num: A11, pin_signal: GPIO_B1_00, label: LCDIF_D12, identifier: LCDIF_D12}
82- {pin_num: B11, pin_signal: GPIO_B1_01, label: LCDIF_D13, identifier: LCDIF_D13}
83- {pin_num: C11, pin_signal: GPIO_B1_02, label: LCDIF_D14, identifier: LCDIF_D14}
84- {pin_num: D11, pin_signal: GPIO_B1_03, label: LCDIF_D15, identifier: LCDIF_D15}
85- {pin_num: E12, pin_signal: GPIO_B1_04, label: ENET_RXD0, identifier: ENET_RXD0}
86- {pin_num: D12, pin_signal: GPIO_B1_05, label: ENET_RXD1, identifier: ENET_RXD1}
87- {pin_num: C12, pin_signal: GPIO_B1_06, label: ENET_CRS_DV, identifier: ENET_CRS_DV}
88- {pin_num: B12, pin_signal: GPIO_B1_07, label: ENET_TXD0, identifier: ENET_TXD0}
89- {pin_num: A12, pin_signal: GPIO_B1_08, label: ENET_TXD1, identifier: ENET_TXD1}
90- {pin_num: A13, pin_signal: GPIO_B1_09, label: ENET_TXEN, identifier: ENET_TXEN}
91- {pin_num: B13, pin_signal: GPIO_B1_10, label: ENET_TX_CLK, identifier: ENET_TX_CLK}
92- {pin_num: C13, pin_signal: GPIO_B1_11, label: ENET_RXER, identifier: ENET_RXER}
93- {pin_num: D13, pin_signal: GPIO_B1_12, label: SD_CD_SW, identifier: SD_CD_SW}
94- {pin_num: D14, pin_signal: GPIO_B1_13, label: WDOG_B, identifier: WDOG_B}
95- {pin_num: C14, pin_signal: GPIO_B1_14, label: SD0_VSELECT, identifier: SD0_VSELECT}
96- {pin_num: B14, pin_signal: GPIO_B1_15, label: USB_HOST_PWR/BACKLIGHT_CTL, identifier: BACKLIGHT_CTL}
97- {pin_num: E9, pin_signal: NVCC_GPIO0, label: DCDC_3V3/NVCC_GPIO_3V3}
98- {pin_num: F10, pin_signal: NVCC_GPIO1, label: DCDC_3V3/NVCC_GPIO_3V3}
99- {pin_num: J10, pin_signal: NVCC_GPIO2, label: DCDC_3V3/NVCC_GPIO_3V3}
100- {pin_num: M14, pin_signal: GPIO_AD_B0_00, label: 'USB_HOST_OC/J24[10]'}
101- {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: 'USB_OTG1_ID/J24[9]'}
102- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: 'USB_OTG1_PWR/J24[2]'}
103- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: 'USB_OTG1_OC/J24[1]'}
104- {pin_num: F11, pin_signal: GPIO_AD_B0_04, label: 'CSI_PWDN/J35[17]/BOOT_MODE[0]', identifier: CSI_PWDN}
105- {pin_num: G14, pin_signal: GPIO_AD_B0_05, label: 'CAN_STBY/BOOT_MODE[1]/Flash_RST/U12[8]', identifier: CAN_STBY}
106- {pin_num: E14, pin_signal: GPIO_AD_B0_06, label: 'JTAG_TMS/J21[7]/SWD_DIO'}
107- {pin_num: F12, pin_signal: GPIO_AD_B0_07, label: 'JTAG_TCK/J21[9]/SWD_CLK'}
108- {pin_num: F13, pin_signal: GPIO_AD_B0_08, label: JTAG_MOD}
109- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]'}
110- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: 'JTAG_TDO/J21[13]/INT1_COMBO/ENET_INT/J22[6]/U32[11]', identifier: INT1_COMBO}
111- {pin_num: G10, pin_signal: GPIO_AD_B0_11, label: 'JTAG_nTRST/J21[3]/INT2_COMBO/LCD_TOUCH_INT/J22[3]/U32[9]', identifier: INT2_COMBO}
112- {pin_num: K14, pin_signal: GPIO_AD_B0_12, label: UART1_TXD, identifier: UART1_TXD}
113- {pin_num: L14, pin_signal: GPIO_AD_B0_13, label: UART1_RXD, identifier: UART1_RXD}
114- {pin_num: H14, pin_signal: GPIO_AD_B0_14, label: 'CAN2_TX/U12[1]', identifier: CAN2_TX}
115- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: 'CAN2_RX/U12[4]', identifier: CAN2_RX}
116- {pin_num: J11, pin_signal: GPIO_AD_B1_00, label: 'I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4]', identifier: I2C_SCL_FXOS8700CQ;CSI_I2C_SCL}
117- {pin_num: K11, pin_signal: GPIO_AD_B1_01, label: 'I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6]', identifier: I2C_SDA_FXOS8700CQ;CSI_I2C_SDA}
118- {pin_num: L11, pin_signal: GPIO_AD_B1_02, label: 'SPDIF_OUT/J22[7]', identifier: SPDIF_OUT}
119- {pin_num: M12, pin_signal: GPIO_AD_B1_03, label: 'SPDIF_IN/J22[8]', identifier: SPDIF_IN}
120- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: 'AUD_INT/CSI_D9//J35[13]/J22[4]', identifier: CSI_D9}
121- {pin_num: M13, pin_signal: GPIO_AD_B1_09, label: 'SAI1_MCLK/CSI_D8/J35[11]', identifier: CSI_D8}
122- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: 'SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1]', identifier: CSI_D7}
123- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: 'SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2]', identifier: CSI_D6}
124- {pin_num: H12, pin_signal: GPIO_AD_B1_12, label: 'SAI1_RXD/CSI_D5/J35[5]/U13[16]', identifier: CSI_D5}
125- {pin_num: H11, pin_signal: GPIO_AD_B1_13, label: 'SAI1_TXD/CSI_D4/J35[3]/U13[14]', identifier: CSI_D4}
126- {pin_num: G12, pin_signal: GPIO_AD_B1_14, label: 'SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12]', identifier: CSI_D3}
127- {pin_num: J14, pin_signal: GPIO_AD_B1_15, label: 'SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13]', identifier: CSI_D2}
128- {pin_num: J4, pin_signal: GPIO_SD_B0_00, label: 'SD1_CMD/J24[6]', identifier: SD1_CMD}
129- {pin_num: J3, pin_signal: GPIO_SD_B0_01, label: 'SD1_CLK/J24[3]', identifier: SD1_CLK}
130- {pin_num: J1, pin_signal: GPIO_SD_B0_02, label: 'SD1_D0/J24[4]/SPI_MOSI/PWM', identifier: SD1_D0}
131- {pin_num: K1, pin_signal: GPIO_SD_B0_03, label: 'SD1_D1/J24[5]/SPI_MISO', identifier: SD1_D1}
132- {pin_num: H2, pin_signal: GPIO_SD_B0_04, label: SD1_D2, identifier: SD1_D2}
133- {pin_num: J2, pin_signal: GPIO_SD_B0_05, label: SD1_D3, identifier: SD1_D3}
134- {pin_num: L5, pin_signal: GPIO_SD_B1_00, label: FlexSPI_D3_B, identifier: FlexSPI_D3_B}
135- {pin_num: M5, pin_signal: GPIO_SD_B1_01, label: FlexSPI_D2_B, identifier: FlexSPI_D2_B}
136- {pin_num: M3, pin_signal: GPIO_SD_B1_02, label: FlexSPI_D1_B, identifier: FlexSPI_D1_B}
137- {pin_num: M4, pin_signal: GPIO_SD_B1_03, label: FlexSPI_D0_B, identifier: FlexSPI_D0_B}
138- {pin_num: P2, pin_signal: GPIO_SD_B1_04, label: FlexSPI_CLK_B, identifier: FlexSPI_CLK_B}
139- {pin_num: N3, pin_signal: GPIO_SD_B1_05, label: FlexSPI_DQS, identifier: FlexSPI_DQS}
140- {pin_num: L3, pin_signal: GPIO_SD_B1_06, label: FlexSPI_SS0, identifier: FlexSPI_SS0}
141- {pin_num: L4, pin_signal: GPIO_SD_B1_07, label: FlexSPI_CLK, identifier: FlexSPI_CLK}
142- {pin_num: P3, pin_signal: GPIO_SD_B1_08, label: FlexSPI_D0_A, identifier: FlexSPI_D0_A}
143- {pin_num: N4, pin_signal: GPIO_SD_B1_09, label: FlexSPI_D1_A, identifier: FlexSPI_D1_A}
144- {pin_num: P4, pin_signal: GPIO_SD_B1_10, label: FlexSPI_D2_A, identifier: FlexSPI_D2_A}
145- {pin_num: P5, pin_signal: GPIO_SD_B1_11, label: FlexSPI_D3_A, identifier: FlexSPI_D3_A}
146- {pin_num: M8, pin_signal: USB_OTG1_DN, label: OTG1_DN, identifier: OTG1_DN}
147- {pin_num: L8, pin_signal: USB_OTG1_DP, label: OTG1_DP, identifier: OTG1_DP}
148- {pin_num: N7, pin_signal: USB_OTG2_DN, label: OTG2_DN, identifier: OTG2_DN}
149- {pin_num: P7, pin_signal: USB_OTG2_DP, label: OTG2_DP, identifier: OTG2_DP}
150- {pin_num: K8, pin_signal: VDD_USB_CAP, label: VDD_USB_3V}
151- {pin_num: N6, pin_signal: USB_OTG1_VBUS, label: 5V_USB_OTG}
152- {pin_num: P6, pin_signal: USB_OTG2_VBUS, label: 5V_USB_HS}
153- {pin_num: L12, pin_signal: GPIO_AD_B1_04, label: 'CSI_PIXCLK/J35[8]/J23[3]', identifier: CSI_PIXCLK}
154- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: 'CSI_MCLK/J35[12]/J23[4]', identifier: CSI_MCLK}
155- {pin_num: J12, pin_signal: GPIO_AD_B1_06, label: 'CSI_VSYNC/J35[18]/J22[2]/UART_TX', identifier: CSI_VSYNC}
156- {pin_num: K10, pin_signal: GPIO_AD_B1_07, label: 'CSI_HSYNC/J35[16]/J22[1]/UART_RX', identifier: CSI_HSYNC}
157- {pin_num: M7, pin_signal: POR_B, label: 'RST_TGTMCU_B/POR_B/J21[15]', identifier: RST_TGTMCU_B;POR_B}
158- {pin_num: N14, pin_signal: VDDA_ADC_3P3, label: VDDA_ADC_3P3_MCU}
159- {pin_num: P12, pin_signal: VDD_HIGH_IN, label: VDD_HIGH_IN_MCU}
160- {pin_num: M9, pin_signal: VDD_SNVS_IN, label: VDD_SNVS_IN}
161- {pin_num: F6, pin_signal: VDD_SOC_IN0, label: VDD_SOC_IN}
162- {pin_num: H6, pin_signal: VDD_SOC_IN2, label: VDD_SOC_IN}
163- {pin_num: G6, pin_signal: VDD_SOC_IN1, label: VDD_SOC_IN}
164- {pin_num: F7, pin_signal: VDD_SOC_IN3, label: VDD_SOC_IN}
165- {pin_num: F8, pin_signal: VDD_SOC_IN4, label: VDD_SOC_IN}
166- {pin_num: F9, pin_signal: VDD_SOC_IN5, label: VDD_SOC_IN}
167- {pin_num: G9, pin_signal: VDD_SOC_IN6, label: VDD_SOC_IN}
168- {pin_num: H9, pin_signal: VDD_SOC_IN7, label: VDD_SOC_IN}
169- {pin_num: J9, pin_signal: VDD_SOC_IN8, label: VDD_SOC_IN}
170- {pin_num: P1, pin_signal: VSS1, label: GND}
171- {pin_num: E2, pin_signal: VSS2, label: GND}
172- {pin_num: K2, pin_signal: VSS3, label: GND}
173- {pin_num: B5, pin_signal: VSS4, label: GND}
174- {pin_num: N5, pin_signal: VSS5, label: GND}
175- {pin_num: G7, pin_signal: VSS6, label: GND}
176- {pin_num: H7, pin_signal: VSS7, label: GND}
177- {pin_num: J7, pin_signal: VSS8, label: GND}
178- {pin_num: G8, pin_signal: VSS9, label: GND}
179- {pin_num: H8, pin_signal: VSS10, label: GND}
180- {pin_num: J8, pin_signal: VSS11, label: GND}
181- {pin_num: N8, pin_signal: VSS12, label: GND}
182- {pin_num: L9, pin_signal: VSS13, label: GND}
183- {pin_num: B10, pin_signal: VSS14, label: GND}
184- {pin_num: E13, pin_signal: VSS15, label: GND}
185- {pin_num: K13, pin_signal: VSS16, label: GND}
186- {pin_num: A14, pin_signal: VSS17, label: GND}
187- {pin_num: P14, pin_signal: VSS18, label: GND}
188- {pin_num: A1, pin_signal: VSS0, label: GND}
189- {pin_num: J6, pin_signal: NVCC_SD0, label: NVCC_SD, identifier: NVCC_SD}
190- {pin_num: K5, pin_signal: NVCC_SD1, label: FLASH_VCC, identifier: FLASH_VCC}
191- {pin_num: F5, pin_signal: NVCC_EMC0, label: DCDC_3V3}
192- {pin_num: E6, pin_signal: NVCC_EMC1, label: DCDC_3V3}
193- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: SD_PWREN}
194- {pin_num: L1, pin_signal: DCDC_IN0, label: MCU_DCDC_IN_3V3}
195- {pin_num: L2, pin_signal: DCDC_IN1, label: MCU_DCDC_IN_3V3}
196- {pin_num: K4, pin_signal: DCDC_IN_Q, label: MCU_DCDC_IN_3V3}
197- {pin_num: M1, pin_signal: DCDC_LP0, label: VDD_SOC_IN}
198- {pin_num: M2, pin_signal: DCDC_LP1, label: VDD_SOC_IN}
199- {pin_num: P11, pin_signal: XTALI, label: XTALI, identifier: XTALI}
200- {pin_num: N11, pin_signal: XTALO, label: XTALO, identifier: XTALO}
201- {pin_num: N9, pin_signal: RTC_XTALI, label: RTC_XTALI, identifier: RTC_XTALI}
202- {pin_num: P9, pin_signal: RTC_XTALO, label: RTC_XTALO, identifier: RTC_XTALO}
203- {pin_num: N1, pin_signal: DCDC_GND0, label: GND}
204- {pin_num: N2, pin_signal: DCDC_GND1, label: GND}
205- {pin_num: J5, pin_signal: DCDC_SENSE, label: VDD_SOC_IN}
206- {pin_num: K3, pin_signal: DCDC_PSWITCH, label: MCU_DCDC_IN_3V3}
207- {pin_num: K7, pin_signal: PMIC_ON_REQ, label: PMIC_ON_REQ, identifier: PMIC_ON_REQ}
208- {pin_num: L7, pin_signal: PMIC_STBY_REQ, label: PERI_PWREN, identifier: PERI_PWREN}
209- {pin_num: M6, pin_signal: ONOFF, label: ONOFF, identifier: ONOFF}
210- {pin_num: K6, pin_signal: TEST_MODE, label: GND}
211- {pin_num: P10, pin_signal: NVCC_PLL, label: VDDA_1P1_CAP}
212- {pin_num: P8, pin_signal: VDD_HIGH_CAP, label: VDDA_2P5_CAP}
213- {pin_num: K9, pin_signal: NGND_KEL0, label: GND}
214- {pin_num: M10, pin_signal: VDD_SNVS_CAP, label: GND}
215 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
216 */
217
218#include "fsl_common.h"
219#include "fsl_iomuxc.h"
220#include "pin_mux.h"
221
222/* FUNCTION ************************************************************************************************************
223 *
224 * Function Name : BOARD_InitBootPins
225 * Description : Calls initialization functions.
226 *
227 * END ****************************************************************************************************************/
228void BOARD_InitBootPins(void) {
229 BOARD_InitPins();
230 BOARD_InitDEBUG_UARTPins();
231}
232
233/*
234 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
235BOARD_InitPins:
236- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
237- pin_list: []
238 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
239 */
240
241/* FUNCTION ************************************************************************************************************
242 *
243 * Function Name : BOARD_InitPins
244 * Description : Configures pin routing and optionally pin electrical features.
245 *
246 * END ****************************************************************************************************************/
247void BOARD_InitPins(void) {
248}
249
250
251/*
252 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
253BOARD_InitDEBUG_UARTPins:
254- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
255- pin_list:
256 - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
257 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
258 - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
259 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
260 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
261 */
262
263/* FUNCTION ************************************************************************************************************
264 *
265 * Function Name : BOARD_InitDEBUG_UARTPins
266 * Description : Configures pin routing and optionally pin electrical features.
267 *
268 * END ****************************************************************************************************************/
269void BOARD_InitDEBUG_UARTPins(void) {
270 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
271
272 IOMUXC_SetPinMux(
273 IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
274 0U); /* Software Input On Field: Input Path is determined by functionality */
275 IOMUXC_SetPinMux(
276 IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
277 0U); /* Software Input On Field: Input Path is determined by functionality */
278 IOMUXC_SetPinConfig(
279 IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
280 0x10B0u); /* Slew Rate Field: Slow Slew Rate
281 Drive Strength Field: R0/6
282 Speed Field: medium(100MHz)
283 Open Drain Enable Field: Open Drain Disabled
284 Pull / Keep Enable Field: Pull/Keeper Enabled
285 Pull / Keep Select Field: Keeper
286 Pull Up / Down Config. Field: 100K Ohm Pull Down
287 Hyst. Enable Field: Hysteresis Disabled */
288 IOMUXC_SetPinConfig(
289 IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
290 0x10B0u); /* Slew Rate Field: Slow Slew Rate
291 Drive Strength Field: R0/6
292 Speed Field: medium(100MHz)
293 Open Drain Enable Field: Open Drain Disabled
294 Pull / Keep Enable Field: Pull/Keeper Enabled
295 Pull / Keep Select Field: Keeper
296 Pull Up / Down Config. Field: 100K Ohm Pull Down
297 Hyst. Enable Field: Hysteresis Disabled */
298}
299
300
301/*
302 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
303BOARD_InitSDRAMPins:
304- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
305- pin_list:
306 - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
307 - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
308 - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
309 - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
310 - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
311 - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
312 - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
313 - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
314 - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
315 - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
316 - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
317 - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
318 - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
319 - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
320 - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
321 - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
322 - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
323 - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
324 - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
325 - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
326 - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
327 - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
328 - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
329 - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
330 - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
331 - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
332 - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
333 - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
334 - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
335 - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
336 - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
337 - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
338 - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
339 - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
340 - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
341 - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
342 - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
343 - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
344 - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
345 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
346 */
347
348/* FUNCTION ************************************************************************************************************
349 *
350 * Function Name : BOARD_InitSDRAMPins
351 * Description : Configures pin routing and optionally pin electrical features.
352 *
353 * END ****************************************************************************************************************/
354void BOARD_InitSDRAMPins(void) {
355 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
356
357 IOMUXC_SetPinMux(
358 IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
359 0U); /* Software Input On Field: Input Path is determined by functionality */
360 IOMUXC_SetPinMux(
361 IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
362 0U); /* Software Input On Field: Input Path is determined by functionality */
363 IOMUXC_SetPinMux(
364 IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
365 0U); /* Software Input On Field: Input Path is determined by functionality */
366 IOMUXC_SetPinMux(
367 IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
368 0U); /* Software Input On Field: Input Path is determined by functionality */
369 IOMUXC_SetPinMux(
370 IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
371 0U); /* Software Input On Field: Input Path is determined by functionality */
372 IOMUXC_SetPinMux(
373 IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
374 0U); /* Software Input On Field: Input Path is determined by functionality */
375 IOMUXC_SetPinMux(
376 IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
377 0U); /* Software Input On Field: Input Path is determined by functionality */
378 IOMUXC_SetPinMux(
379 IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
380 0U); /* Software Input On Field: Input Path is determined by functionality */
381 IOMUXC_SetPinMux(
382 IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
383 0U); /* Software Input On Field: Input Path is determined by functionality */
384 IOMUXC_SetPinMux(
385 IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */
386 0U); /* Software Input On Field: Input Path is determined by functionality */
387 IOMUXC_SetPinMux(
388 IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */
389 0U); /* Software Input On Field: Input Path is determined by functionality */
390 IOMUXC_SetPinMux(
391 IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */
392 0U); /* Software Input On Field: Input Path is determined by functionality */
393 IOMUXC_SetPinMux(
394 IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */
395 0U); /* Software Input On Field: Input Path is determined by functionality */
396 IOMUXC_SetPinMux(
397 IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */
398 0U); /* Software Input On Field: Input Path is determined by functionality */
399 IOMUXC_SetPinMux(
400 IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */
401 0U); /* Software Input On Field: Input Path is determined by functionality */
402 IOMUXC_SetPinMux(
403 IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */
404 0U); /* Software Input On Field: Input Path is determined by functionality */
405 IOMUXC_SetPinMux(
406 IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */
407 0U); /* Software Input On Field: Input Path is determined by functionality */
408 IOMUXC_SetPinMux(
409 IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */
410 0U); /* Software Input On Field: Input Path is determined by functionality */
411 IOMUXC_SetPinMux(
412 IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */
413 0U); /* Software Input On Field: Input Path is determined by functionality */
414 IOMUXC_SetPinMux(
415 IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */
416 0U); /* Software Input On Field: Input Path is determined by functionality */
417 IOMUXC_SetPinMux(
418 IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */
419 0U); /* Software Input On Field: Input Path is determined by functionality */
420 IOMUXC_SetPinMux(
421 IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */
422 0U); /* Software Input On Field: Input Path is determined by functionality */
423 IOMUXC_SetPinMux(
424 IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */
425 0U); /* Software Input On Field: Input Path is determined by functionality */
426 IOMUXC_SetPinMux(
427 IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */
428 0U); /* Software Input On Field: Input Path is determined by functionality */
429 IOMUXC_SetPinMux(
430 IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */
431 0U); /* Software Input On Field: Input Path is determined by functionality */
432 IOMUXC_SetPinMux(
433 IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */
434 0U); /* Software Input On Field: Input Path is determined by functionality */
435 IOMUXC_SetPinMux(
436 IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */
437 0U); /* Software Input On Field: Input Path is determined by functionality */
438 IOMUXC_SetPinMux(
439 IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */
440 0U); /* Software Input On Field: Input Path is determined by functionality */
441 IOMUXC_SetPinMux(
442 IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */
443 0U); /* Software Input On Field: Input Path is determined by functionality */
444 IOMUXC_SetPinMux(
445 IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */
446 0U); /* Software Input On Field: Input Path is determined by functionality */
447 IOMUXC_SetPinMux(
448 IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */
449 0U); /* Software Input On Field: Input Path is determined by functionality */
450 IOMUXC_SetPinMux(
451 IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */
452 0U); /* Software Input On Field: Input Path is determined by functionality */
453 IOMUXC_SetPinMux(
454 IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */
455 0U); /* Software Input On Field: Input Path is determined by functionality */
456 IOMUXC_SetPinMux(
457 IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */
458 0U); /* Software Input On Field: Input Path is determined by functionality */
459 IOMUXC_SetPinMux(
460 IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */
461 0U); /* Software Input On Field: Input Path is determined by functionality */
462 IOMUXC_SetPinMux(
463 IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */
464 0U); /* Software Input On Field: Input Path is determined by functionality */
465 IOMUXC_SetPinMux(
466 IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */
467 0U); /* Software Input On Field: Input Path is determined by functionality */
468 IOMUXC_SetPinMux(
469 IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */
470 0U); /* Software Input On Field: Input Path is determined by functionality */
471 IOMUXC_SetPinMux(
472 IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
473 0U); /* Software Input On Field: Input Path is determined by functionality */
474}
475
476
477/*
478 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
479BOARD_InitCSIPins:
480- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
481- pin_list:
482 - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
483 - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
484 - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
485 - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
486 - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
487 - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
488 - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
489 - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
490 - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
491 - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
492 - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
493 - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
494 - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
495 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
496 - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
497 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
498 - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
499 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
500 */
501
502/* FUNCTION ************************************************************************************************************
503 *
504 * Function Name : BOARD_InitCSIPins
505 * Description : Configures pin routing and optionally pin electrical features.
506 *
507 * END ****************************************************************************************************************/
508void BOARD_InitCSIPins(void) {
509 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
510
511 IOMUXC_SetPinMux(
512 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
513 0U); /* Software Input On Field: Input Path is determined by functionality */
514 IOMUXC_SetPinMux(
515 IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
516 0U); /* Software Input On Field: Input Path is determined by functionality */
517 IOMUXC_SetPinMux(
518 IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
519 0U); /* Software Input On Field: Input Path is determined by functionality */
520 IOMUXC_SetPinMux(
521 IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, /* GPIO_AD_B1_04 is configured as CSI_PIXCLK */
522 0U); /* Software Input On Field: Input Path is determined by functionality */
523 IOMUXC_SetPinMux(
524 IOMUXC_GPIO_AD_B1_05_CSI_MCLK, /* GPIO_AD_B1_05 is configured as CSI_MCLK */
525 0U); /* Software Input On Field: Input Path is determined by functionality */
526 IOMUXC_SetPinMux(
527 IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, /* GPIO_AD_B1_06 is configured as CSI_VSYNC */
528 0U); /* Software Input On Field: Input Path is determined by functionality */
529 IOMUXC_SetPinMux(
530 IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, /* GPIO_AD_B1_07 is configured as CSI_HSYNC */
531 0U); /* Software Input On Field: Input Path is determined by functionality */
532 IOMUXC_SetPinMux(
533 IOMUXC_GPIO_AD_B1_08_CSI_DATA09, /* GPIO_AD_B1_08 is configured as CSI_DATA09 */
534 0U); /* Software Input On Field: Input Path is determined by functionality */
535 IOMUXC_SetPinMux(
536 IOMUXC_GPIO_AD_B1_09_CSI_DATA08, /* GPIO_AD_B1_09 is configured as CSI_DATA08 */
537 0U); /* Software Input On Field: Input Path is determined by functionality */
538 IOMUXC_SetPinMux(
539 IOMUXC_GPIO_AD_B1_10_CSI_DATA07, /* GPIO_AD_B1_10 is configured as CSI_DATA07 */
540 0U); /* Software Input On Field: Input Path is determined by functionality */
541 IOMUXC_SetPinMux(
542 IOMUXC_GPIO_AD_B1_11_CSI_DATA06, /* GPIO_AD_B1_11 is configured as CSI_DATA06 */
543 0U); /* Software Input On Field: Input Path is determined by functionality */
544 IOMUXC_SetPinMux(
545 IOMUXC_GPIO_AD_B1_12_CSI_DATA05, /* GPIO_AD_B1_12 is configured as CSI_DATA05 */
546 0U); /* Software Input On Field: Input Path is determined by functionality */
547 IOMUXC_SetPinMux(
548 IOMUXC_GPIO_AD_B1_13_CSI_DATA04, /* GPIO_AD_B1_13 is configured as CSI_DATA04 */
549 0U); /* Software Input On Field: Input Path is determined by functionality */
550 IOMUXC_SetPinMux(
551 IOMUXC_GPIO_AD_B1_14_CSI_DATA03, /* GPIO_AD_B1_14 is configured as CSI_DATA03 */
552 0U); /* Software Input On Field: Input Path is determined by functionality */
553 IOMUXC_SetPinMux(
554 IOMUXC_GPIO_AD_B1_15_CSI_DATA02, /* GPIO_AD_B1_15 is configured as CSI_DATA02 */
555 0U); /* Software Input On Field: Input Path is determined by functionality */
556 IOMUXC_SetPinConfig(
557 IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
558 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
559 Drive Strength Field: R0/6
560 Speed Field: medium(100MHz)
561 Open Drain Enable Field: Open Drain Enabled
562 Pull / Keep Enable Field: Pull/Keeper Enabled
563 Pull / Keep Select Field: Keeper
564 Pull Up / Down Config. Field: 22K Ohm Pull Up
565 Hyst. Enable Field: Hysteresis Disabled */
566 IOMUXC_SetPinConfig(
567 IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
568 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
569 Drive Strength Field: R0/6
570 Speed Field: medium(100MHz)
571 Open Drain Enable Field: Open Drain Enabled
572 Pull / Keep Enable Field: Pull/Keeper Enabled
573 Pull / Keep Select Field: Keeper
574 Pull Up / Down Config. Field: 22K Ohm Pull Up
575 Hyst. Enable Field: Hysteresis Disabled */
576}
577
578
579/*
580 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
581BOARD_InitLCDPins:
582- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
583- pin_list:
584 - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
585 - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
586 - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
587 - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
588 - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
589 - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
590 - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
591 - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
592 - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
593 - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
594 - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
595 - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down