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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.c303
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.h155
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c348
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.h105
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.c303
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.h155
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.c345
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.h104
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.c61
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.c139
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.h111
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/driver_xip_board.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.c48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.h267
15 files changed, 2494 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.c
new file mode 100644
index 000000000..3282a7b0b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.c
@@ -0,0 +1,303 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51/* MPU configuration. */
52void BOARD_ConfigMPU(void)
53{
54#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
55 extern uint32_t Image$$RW_m_ncache$$Base[];
56 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
58 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
61 0 :
62 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
63#elif defined(__MCUXPRESSO)
64 extern uint32_t __base_NCACHE_REGION;
65 extern uint32_t __top_NCACHE_REGION;
66 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
67 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
68#elif defined(__ICCARM__) || defined(__GNUC__)
69 extern uint32_t __NCACHE_REGION_START[];
70 extern uint32_t __NCACHE_REGION_SIZE[];
71 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
72 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
73#endif
74 volatile uint32_t i = 0;
75
76 /* Disable I cache and D cache */
77 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
78 {
79 SCB_DisableICache();
80 }
81 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
82 {
83 SCB_DisableDCache();
84 }
85
86 /* Disable MPU */
87 ARM_MPU_Disable();
88
89 /* MPU configure:
90 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
91 * SubRegionDisable, Size)
92 * API in mpu_armv7.h.
93 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
94 * disabled.
95 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
96 * Privileged mode.
97 * Use MACROS defined in mpu_armv7.h:
98 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
99 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
100 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
101 * 0 x 0 0 Strongly Ordered shareable
102 * 0 x 0 1 Device shareable
103 * 0 0 1 0 Normal not shareable Outer and inner write
104 * through no write allocate
105 * 0 0 1 1 Normal not shareable Outer and inner write
106 * back no write allocate
107 * 0 1 1 0 Normal shareable Outer and inner write
108 * through no write allocate
109 * 0 1 1 1 Normal shareable Outer and inner write
110 * back no write allocate
111 * 1 0 0 0 Normal not shareable outer and inner
112 * noncache
113 * 1 1 0 0 Normal shareable outer and inner
114 * noncache
115 * 1 0 1 1 Normal not shareable outer and inner write
116 * back write/read acllocate
117 * 1 1 1 1 Normal shareable outer and inner write
118 * back write/read acllocate
119 * 2 x 0 0 Device not shareable
120 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
121 * policy.
122 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
123 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
124 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
125 * mpu_armv7.h.
126 */
127
128 /*
129 * Add default region to deny access to whole address space to workaround speculative prefetch.
130 * Refer to Arm errata 1013783-B for more details.
131 *
132 */
133 /* Region 0 setting: Instruction access disabled, No data access permission. */
134 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
136
137 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
138 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
140
141 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
142 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
144
145#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
146 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
147 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
148 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
149#endif
150
151 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
152 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
153 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
154
155 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
156 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
157 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
158
159 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
160 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
161 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
162
163 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
164 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
165 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
166
167 while ((size >> i) > 0x1U)
168 {
169 i++;
170 }
171
172 if (i != 0)
173 {
174 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
175 assert(!(nonCacheStart % size));
176 assert(size == (uint32_t)(1 << i));
177 assert(i >= 5);
178
179 /* Region 8 setting: Memory with Normal type, not shareable, non-cacheable */
180 MPU->RBAR = ARM_MPU_RBAR(8, nonCacheStart);
181 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
182 }
183
184 /* Region 9 setting: Memory with Device type, not shareable, non-cacheable */
185 MPU->RBAR = ARM_MPU_RBAR(9, 0x40000000);
186 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
187
188 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
189 MPU->RBAR = ARM_MPU_RBAR(10, 0x42000000);
190 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_32MB);
191
192 /* Enable MPU */
193 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
194
195 /* Enable I cache and D cache */
196 SCB_EnableDCache();
197 SCB_EnableICache();
198}
199
200#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
201void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
202{
203 lpi2c_master_config_t lpi2cConfig = {0};
204
205 /*
206 * lpi2cConfig.debugEnable = false;
207 * lpi2cConfig.ignoreAck = false;
208 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
209 * lpi2cConfig.baudRate_Hz = 100000U;
210 * lpi2cConfig.busIdleTimeout_ns = 0;
211 * lpi2cConfig.pinLowTimeout_ns = 0;
212 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
213 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
214 */
215 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
216 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
217}
218
219status_t BOARD_LPI2C_Send(LPI2C_Type *base,
220 uint8_t deviceAddress,
221 uint32_t subAddress,
222 uint8_t subAddressSize,
223 uint8_t *txBuff,
224 uint8_t txBuffSize)
225{
226 lpi2c_master_transfer_t xfer;
227
228 xfer.flags = kLPI2C_TransferDefaultFlag;
229 xfer.slaveAddress = deviceAddress;
230 xfer.direction = kLPI2C_Write;
231 xfer.subaddress = subAddress;
232 xfer.subaddressSize = subAddressSize;
233 xfer.data = txBuff;
234 xfer.dataSize = txBuffSize;
235
236 return LPI2C_MasterTransferBlocking(base, &xfer);
237}
238
239status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
240 uint8_t deviceAddress,
241 uint32_t subAddress,
242 uint8_t subAddressSize,
243 uint8_t *rxBuff,
244 uint8_t rxBuffSize)
245{
246 lpi2c_master_transfer_t xfer;
247
248 xfer.flags = kLPI2C_TransferDefaultFlag;
249 xfer.slaveAddress = deviceAddress;
250 xfer.direction = kLPI2C_Read;
251 xfer.subaddress = subAddress;
252 xfer.subaddressSize = subAddressSize;
253 xfer.data = rxBuff;
254 xfer.dataSize = rxBuffSize;
255
256 return LPI2C_MasterTransferBlocking(base, &xfer);
257}
258
259void BOARD_Accel_I2C_Init(void)
260{
261 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
262}
263
264status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
265{
266 uint8_t data = (uint8_t)txBuff;
267
268 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
269}
270
271status_t BOARD_Accel_I2C_Receive(
272 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
273{
274 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
275}
276
277void BOARD_Codec_I2C_Init(void)
278{
279 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
280}
281
282status_t BOARD_Codec_I2C_Send(
283 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
284{
285 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
286 txBuffSize);
287}
288
289status_t BOARD_Codec_I2C_Receive(
290 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
291{
292 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
293}
294#endif /*SDK_I2C_BASED_COMPONENT_USED */
295
296#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
297/* SystemInitHook */
298void SystemInitHook(void)
299{
300 /* When set this bit, FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. */
301 FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK;
302}
303#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.h
new file mode 100644
index 000000000..44f74dcb0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/board.h
@@ -0,0 +1,155 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1010-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_INSTANCE 1U
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
44#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
45#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (0U)
49#define LOGIC_LED_OFF (1U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO1
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (11U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_OFF() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO2
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (5U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO2_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO2_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The flash size */
79#define BOARD_FLASH_SIZE (0x1000000U)
80
81/* USB PHY condfiguration */
82#define BOARD_USB_PHY_D_CAL (0x0CU)
83#define BOARD_USB_PHY_TXCAL45DP (0x06U)
84#define BOARD_USB_PHY_TXCAL45DM (0x06U)
85
86#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
87#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
88#define BOARD_ARDUINO_I2C_INDEX (1)
89
90/*! @brief The WIFI-QCA shield pin. */
91#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
92#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
93#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 8U /*!< PIO1 pin index: 8 */
94#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_08 /*!< Pin name */
95#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
96#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
97#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
98
99#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
100#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
101#define BOARD_INITSILEX2401SHIELD_IRQ_PIN 4U /*!< PIO1 pin index: 4 */
102#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_04 /*!< Pin name */
103#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
104#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
105#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
106
107/* Serial MWM WIFI */
108#define BOARD_SERIAL_MWM_PORT_CLK_FREQ BOARD_DebugConsoleSrcFreq()
109#define BOARD_SERIAL_MWM_PORT LPUART1
110#define BOARD_SERIAL_MWM_PORT_IRQn LPUART1_IRQn
111#define BOARD_SERIAL_MWM_RST_GPIO GPIO1
112#define BOARD_SERIAL_MWM_RST_PIN 24
113#define BOARD_SERIAL_MWM_RST_WRITE(output) GPIO_PinWrite(BOARD_SERIAL_MWM_RST_GPIO, BOARD_SERIAL_MWM_RST_PIN, output)
114
115#if defined(__cplusplus)
116extern "C" {
117#endif /* __cplusplus */
118
119/*******************************************************************************
120 * API
121 ******************************************************************************/
122uint32_t BOARD_DebugConsoleSrcFreq(void);
123
124void BOARD_InitDebugConsole(void);
125void BOARD_ConfigMPU(void);
126#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
127void BOARD_InitDebugConsole(void);
128void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
129status_t BOARD_LPI2C_Send(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subaddressSize,
133 uint8_t *txBuff,
134 uint8_t txBuffSize);
135status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
136 uint8_t deviceAddress,
137 uint32_t subAddress,
138 uint8_t subaddressSize,
139 uint8_t *rxBuff,
140 uint8_t rxBuffSize);
141void BOARD_Accel_I2C_Init(void);
142status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
143status_t BOARD_Accel_I2C_Receive(
144 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
145void BOARD_Codec_I2C_Init(void);
146status_t BOARD_Codec_I2C_Send(
147 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
148status_t BOARD_Codec_I2C_Receive(
149 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
150#endif /* SDK_I2C_BASED_COMPONENT_USED */
151#if defined(__cplusplus)
152}
153#endif /* __cplusplus */
154
155#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c
new file mode 100644
index 000000000..33c821bef
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c
@@ -0,0 +1,348 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v7.0
26processor: MIMXRT1011xxxxx
27package_id: MIMXRT1011DAE5A
28mcu_data: ksdk2_0
29processor_version: 0.7.7
30board: MIMXRT1010-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
84- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
85- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
86- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
87settings:
88- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
89- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
90- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
91- {id: CCM.IPG_PODF.scale, value: '4'}
92- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
93- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
94- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
95- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
96- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
97- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
98- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
99- {id: CCM_ANALOG.PLL2.denom, value: '1'}
100- {id: CCM_ANALOG.PLL2.div, value: '22'}
101- {id: CCM_ANALOG.PLL2.num, value: '0'}
102- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
103- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
104- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
105- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
106- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
108- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
109- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
111- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
112- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
113- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
115- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
116- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
117- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
118- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
120- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
121- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
122sources:
123- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
124- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
125 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
126
127/*******************************************************************************
128 * Variables for BOARD_BootClockRUN configuration
129 ******************************************************************************/
130const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
131 {
132 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
133 .numerator = 0, /* 30 bit numerator of fractional loop divider */
134 .denominator = 1, /* 30 bit denominator of fractional loop divider */
135 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
136 };
137const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
138 {
139 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
140 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
141 };
142const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
143 {
144 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
145 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
146 };
147/*******************************************************************************
148 * Code for BOARD_BootClockRUN configuration
149 ******************************************************************************/
150void BOARD_BootClockRUN(void)
151{
152 /* Init RTC OSC clock frequency. */
153 CLOCK_SetRtcXtalFreq(32768U);
154 /* Enable 1MHz clock output. */
155 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
156 /* Use free 1MHz clock output. */
157 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
158 /* Set XTAL 24MHz clock frequency. */
159 CLOCK_SetXtalFreq(24000000U);
160 /* Enable XTAL 24MHz clock source. */
161 CLOCK_InitExternalClk(0);
162 /* Enable internal RC. */
163 CLOCK_InitRcOsc24M();
164 /* Switch clock source to external OSC. */
165 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
166 /* Set Oscillator ready counter value. */
167 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
168 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
169 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
170 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
171 /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
172 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
173 /* Waiting for DCDC_STS_DC_OK bit is asserted */
174 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
175 {
176 }
177 /* Set AHB_PODF. */
178 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
179 /* Disable IPG clock gate. */
180 CLOCK_DisableClock(kCLOCK_Adc1);
181 CLOCK_DisableClock(kCLOCK_Xbar1);
182 /* Set IPG_PODF. */
183 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
184 /* Disable PERCLK clock gate. */
185 CLOCK_DisableClock(kCLOCK_Gpt1);
186 CLOCK_DisableClock(kCLOCK_Gpt1S);
187 CLOCK_DisableClock(kCLOCK_Gpt2);
188 CLOCK_DisableClock(kCLOCK_Gpt2S);
189 CLOCK_DisableClock(kCLOCK_Pit);
190 /* Set PERCLK_PODF. */
191 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
192 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
193 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
194 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
195#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
196 /* Disable Flexspi clock gate. */
197 CLOCK_DisableClock(kCLOCK_FlexSpi);
198 /* Set FLEXSPI_PODF. */
199 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
200 /* Set Flexspi clock source. */
201 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
202 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
203#endif
204 /* Disable ADC_ACLK_EN clock gate. */
205 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
206 /* Set ADC_ACLK_PODF. */
207 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
208 /* Disable LPSPI clock gate. */
209 CLOCK_DisableClock(kCLOCK_Lpspi1);
210 CLOCK_DisableClock(kCLOCK_Lpspi2);
211 /* Set LPSPI_PODF. */
212 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
213 /* Set Lpspi clock source. */
214 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
215 /* Disable TRACE clock gate. */
216 CLOCK_DisableClock(kCLOCK_Trace);
217 /* Set TRACE_PODF. */
218 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
219 /* Set Trace clock source. */
220 CLOCK_SetMux(kCLOCK_TraceMux, 0);
221 /* Disable SAI1 clock gate. */
222 CLOCK_DisableClock(kCLOCK_Sai1);
223 /* Set SAI1_CLK_PRED. */
224 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
225 /* Set SAI1_CLK_PODF. */
226 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
227 /* Set Sai1 clock source. */
228 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
229 /* Disable SAI3 clock gate. */
230 CLOCK_DisableClock(kCLOCK_Sai3);
231 /* Set SAI3_CLK_PRED. */
232 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
233 /* Set SAI3_CLK_PODF. */
234 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
235 /* Set Sai3 clock source. */
236 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
237 /* Disable Lpi2c clock gate. */
238 CLOCK_DisableClock(kCLOCK_Lpi2c1);
239 CLOCK_DisableClock(kCLOCK_Lpi2c2);
240 /* Set LPI2C_CLK_PODF. */
241 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
242 /* Set Lpi2c clock source. */
243 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
244 /* Disable UART clock gate. */
245 CLOCK_DisableClock(kCLOCK_Lpuart1);
246 CLOCK_DisableClock(kCLOCK_Lpuart2);
247 CLOCK_DisableClock(kCLOCK_Lpuart3);
248 CLOCK_DisableClock(kCLOCK_Lpuart4);
249 /* Set UART_CLK_PODF. */
250 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
251 /* Set Uart clock source. */
252 CLOCK_SetMux(kCLOCK_UartMux, 0);
253 /* Disable SPDIF clock gate. */
254 CLOCK_DisableClock(kCLOCK_Spdif);
255 /* Set SPDIF0_CLK_PRED. */
256 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
257 /* Set SPDIF0_CLK_PODF. */
258 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
259 /* Set Spdif clock source. */
260 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
261 /* Disable Flexio1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Flexio1);
263 /* Set FLEXIO1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
265 /* Set FLEXIO1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
267 /* Set Flexio1 clock source. */
268 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
269 /* Set Pll3 sw clock source. */
270 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
271 /* Init System PLL. */
272 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
273 /* Init System pfd0. */
274 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
275 /* Init System pfd1. */
276 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
277 /* Init System pfd2. */
278 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
279 /* Init System pfd3. */
280 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
281 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
282 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
283 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
284#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
285 /* Init Usb1 PLL. */
286 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
287 /* Init Usb1 pfd0. */
288 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
289 /* Init Usb1 pfd1. */
290 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
291 /* Init Usb1 pfd2. */
292 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
293 /* Init Usb1 pfd3. */
294 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
295 /* Disable Usb1 PLL output for USBPHY1. */
296 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
297#endif
298 /* DeInit Audio PLL. */
299 CLOCK_DeinitAudioPll();
300 /* Bypass Audio PLL. */
301 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
302 /* Set divider for Audio PLL. */
303 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
304 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
305 /* Enable Audio PLL output. */
306 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
307 /* Init Enet PLL. */
308 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
309 /* Set preperiph clock source. */
310 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
311 /* Set periph clock source. */
312 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
313 /* Set periph clock2 clock source. */
314 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
315 /* Set per clock source. */
316 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
317 /* Set clock out1 divider. */
318 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
319 /* Set clock out1 source. */
320 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
321 /* Set clock out2 divider. */
322 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
323 /* Set clock out2 source. */
324 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
325 /* Set clock out1 drives clock out1. */
326 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
327 /* Disable clock out1. */
328 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
329 /* Disable clock out2. */
330 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
331 /* Set SAI1 MCLK1 clock source. */
332 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
333 /* Set SAI1 MCLK2 clock source. */
334 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
335 /* Set SAI1 MCLK3 clock source. */
336 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
337 /* Set SAI3 MCLK3 clock source. */
338 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
339 /* Set MQS configuration. */
340 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
341 /* Set GPT1 High frequency reference clock source. */
342 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
343 /* Set GPT2 High frequency reference clock source. */
344 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
345 /* Set SystemCoreClock variable. */
346 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
347}
348
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.h
new file mode 100644
index 000000000..127d2e99b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
47#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
48#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
49#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
51#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
52#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
53#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
54#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
55#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
56#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
57#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
58#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
59#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
60#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
61#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
62#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
63#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
64#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
65#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
66#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
67#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
68#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
69#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
70#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
71#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
72#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
73#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
74#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
75#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL
76
77/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
78 */
79extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
80/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
81 */
82extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
83/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
84 */
85extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
86
87/*******************************************************************************
88 * API for BOARD_BootClockRUN configuration
89 ******************************************************************************/
90#if defined(__cplusplus)
91extern "C" {
92#endif /* __cplusplus*/
93
94/*!
95 * @brief This function executes configuration of clocks.
96 *
97 */
98void BOARD_BootClockRUN(void);
99
100#if defined(__cplusplus)
101}
102#endif /* __cplusplus*/
103
104#endif /* _CLOCK_CONFIG_H_ */
105
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.c
new file mode 100644
index 000000000..3282a7b0b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.c
@@ -0,0 +1,303 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51/* MPU configuration. */
52void BOARD_ConfigMPU(void)
53{
54#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
55 extern uint32_t Image$$RW_m_ncache$$Base[];
56 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
58 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
61 0 :
62 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
63#elif defined(__MCUXPRESSO)
64 extern uint32_t __base_NCACHE_REGION;
65 extern uint32_t __top_NCACHE_REGION;
66 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
67 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
68#elif defined(__ICCARM__) || defined(__GNUC__)
69 extern uint32_t __NCACHE_REGION_START[];
70 extern uint32_t __NCACHE_REGION_SIZE[];
71 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
72 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
73#endif
74 volatile uint32_t i = 0;
75
76 /* Disable I cache and D cache */
77 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
78 {
79 SCB_DisableICache();
80 }
81 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
82 {
83 SCB_DisableDCache();
84 }
85
86 /* Disable MPU */
87 ARM_MPU_Disable();
88
89 /* MPU configure:
90 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
91 * SubRegionDisable, Size)
92 * API in mpu_armv7.h.
93 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
94 * disabled.
95 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
96 * Privileged mode.
97 * Use MACROS defined in mpu_armv7.h:
98 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
99 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
100 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
101 * 0 x 0 0 Strongly Ordered shareable
102 * 0 x 0 1 Device shareable
103 * 0 0 1 0 Normal not shareable Outer and inner write
104 * through no write allocate
105 * 0 0 1 1 Normal not shareable Outer and inner write
106 * back no write allocate
107 * 0 1 1 0 Normal shareable Outer and inner write
108 * through no write allocate
109 * 0 1 1 1 Normal shareable Outer and inner write
110 * back no write allocate
111 * 1 0 0 0 Normal not shareable outer and inner
112 * noncache
113 * 1 1 0 0 Normal shareable outer and inner
114 * noncache
115 * 1 0 1 1 Normal not shareable outer and inner write
116 * back write/read acllocate
117 * 1 1 1 1 Normal shareable outer and inner write
118 * back write/read acllocate
119 * 2 x 0 0 Device not shareable
120 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
121 * policy.
122 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
123 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
124 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
125 * mpu_armv7.h.
126 */
127
128 /*
129 * Add default region to deny access to whole address space to workaround speculative prefetch.
130 * Refer to Arm errata 1013783-B for more details.
131 *
132 */
133 /* Region 0 setting: Instruction access disabled, No data access permission. */
134 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
136
137 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
138 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
140
141 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
142 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
144
145#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
146 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
147 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
148 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
149#endif
150
151 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
152 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
153 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
154
155 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
156 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
157 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
158
159 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
160 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
161 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
162
163 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
164 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
165 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
166
167 while ((size >> i) > 0x1U)
168 {
169 i++;
170 }
171
172 if (i != 0)
173 {
174 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
175 assert(!(nonCacheStart % size));
176 assert(size == (uint32_t)(1 << i));
177 assert(i >= 5);
178
179 /* Region 8 setting: Memory with Normal type, not shareable, non-cacheable */
180 MPU->RBAR = ARM_MPU_RBAR(8, nonCacheStart);
181 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
182 }
183
184 /* Region 9 setting: Memory with Device type, not shareable, non-cacheable */
185 MPU->RBAR = ARM_MPU_RBAR(9, 0x40000000);
186 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
187
188 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
189 MPU->RBAR = ARM_MPU_RBAR(10, 0x42000000);
190 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_32MB);
191
192 /* Enable MPU */
193 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
194
195 /* Enable I cache and D cache */
196 SCB_EnableDCache();
197 SCB_EnableICache();
198}
199
200#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
201void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
202{
203 lpi2c_master_config_t lpi2cConfig = {0};
204
205 /*
206 * lpi2cConfig.debugEnable = false;
207 * lpi2cConfig.ignoreAck = false;
208 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
209 * lpi2cConfig.baudRate_Hz = 100000U;
210 * lpi2cConfig.busIdleTimeout_ns = 0;
211 * lpi2cConfig.pinLowTimeout_ns = 0;
212 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
213 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
214 */
215 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
216 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
217}
218
219status_t BOARD_LPI2C_Send(LPI2C_Type *base,
220 uint8_t deviceAddress,
221 uint32_t subAddress,
222 uint8_t subAddressSize,
223 uint8_t *txBuff,
224 uint8_t txBuffSize)
225{
226 lpi2c_master_transfer_t xfer;
227
228 xfer.flags = kLPI2C_TransferDefaultFlag;
229 xfer.slaveAddress = deviceAddress;
230 xfer.direction = kLPI2C_Write;
231 xfer.subaddress = subAddress;
232 xfer.subaddressSize = subAddressSize;
233 xfer.data = txBuff;
234 xfer.dataSize = txBuffSize;
235
236 return LPI2C_MasterTransferBlocking(base, &xfer);
237}
238
239status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
240 uint8_t deviceAddress,
241 uint32_t subAddress,
242 uint8_t subAddressSize,
243 uint8_t *rxBuff,
244 uint8_t rxBuffSize)
245{
246 lpi2c_master_transfer_t xfer;
247
248 xfer.flags = kLPI2C_TransferDefaultFlag;
249 xfer.slaveAddress = deviceAddress;
250 xfer.direction = kLPI2C_Read;
251 xfer.subaddress = subAddress;
252 xfer.subaddressSize = subAddressSize;
253 xfer.data = rxBuff;
254 xfer.dataSize = rxBuffSize;
255
256 return LPI2C_MasterTransferBlocking(base, &xfer);
257}
258
259void BOARD_Accel_I2C_Init(void)
260{
261 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
262}
263
264status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
265{
266 uint8_t data = (uint8_t)txBuff;
267
268 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
269}
270
271status_t BOARD_Accel_I2C_Receive(
272 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
273{
274 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
275}
276
277void BOARD_Codec_I2C_Init(void)
278{
279 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
280}
281
282status_t BOARD_Codec_I2C_Send(
283 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
284{
285 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
286 txBuffSize);
287}
288
289status_t BOARD_Codec_I2C_Receive(
290 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
291{
292 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
293}
294#endif /*SDK_I2C_BASED_COMPONENT_USED */
295
296#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
297/* SystemInitHook */
298void SystemInitHook(void)
299{
300 /* When set this bit, FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. */
301 FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK;
302}
303#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.h
new file mode 100644
index 000000000..44f74dcb0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/board.h
@@ -0,0 +1,155 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1010-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_INSTANCE 1U
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
44#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
45#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (0U)
49#define LOGIC_LED_OFF (1U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO1
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (11U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_OFF() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO2
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (5U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO2_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO2_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The flash size */
79#define BOARD_FLASH_SIZE (0x1000000U)
80
81/* USB PHY condfiguration */
82#define BOARD_USB_PHY_D_CAL (0x0CU)
83#define BOARD_USB_PHY_TXCAL45DP (0x06U)
84#define BOARD_USB_PHY_TXCAL45DM (0x06U)
85
86#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
87#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
88#define BOARD_ARDUINO_I2C_INDEX (1)
89
90/*! @brief The WIFI-QCA shield pin. */
91#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
92#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
93#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 8U /*!< PIO1 pin index: 8 */
94#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_08 /*!< Pin name */
95#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
96#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
97#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
98
99#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
100#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
101#define BOARD_INITSILEX2401SHIELD_IRQ_PIN 4U /*!< PIO1 pin index: 4 */
102#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_04 /*!< Pin name */
103#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
104#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
105#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
106
107/* Serial MWM WIFI */
108#define BOARD_SERIAL_MWM_PORT_CLK_FREQ BOARD_DebugConsoleSrcFreq()
109#define BOARD_SERIAL_MWM_PORT LPUART1
110#define BOARD_SERIAL_MWM_PORT_IRQn LPUART1_IRQn
111#define BOARD_SERIAL_MWM_RST_GPIO GPIO1
112#define BOARD_SERIAL_MWM_RST_PIN 24
113#define BOARD_SERIAL_MWM_RST_WRITE(output) GPIO_PinWrite(BOARD_SERIAL_MWM_RST_GPIO, BOARD_SERIAL_MWM_RST_PIN, output)
114
115#if defined(__cplusplus)
116extern "C" {
117#endif /* __cplusplus */
118
119/*******************************************************************************
120 * API
121 ******************************************************************************/
122uint32_t BOARD_DebugConsoleSrcFreq(void);
123
124void BOARD_InitDebugConsole(void);
125void BOARD_ConfigMPU(void);
126#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
127void BOARD_InitDebugConsole(void);
128void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
129status_t BOARD_LPI2C_Send(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subaddressSize,
133 uint8_t *txBuff,
134 uint8_t txBuffSize);
135status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
136 uint8_t deviceAddress,
137 uint32_t subAddress,
138 uint8_t subaddressSize,
139 uint8_t *rxBuff,
140 uint8_t rxBuffSize);
141void BOARD_Accel_I2C_Init(void);
142status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
143status_t BOARD_Accel_I2C_Receive(
144 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
145void BOARD_Codec_I2C_Init(void);
146status_t BOARD_Codec_I2C_Send(
147 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
148status_t BOARD_Codec_I2C_Receive(
149 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
150#endif /* SDK_I2C_BASED_COMPONENT_USED */
151#if defined(__cplusplus)
152}
153#endif /* __cplusplus */
154
155#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.c
new file mode 100644
index 000000000..178d62a84
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.c
@@ -0,0 +1,345 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v6.0
26processor: MIMXRT1011xxxxx
27package_id: MIMXRT1011DAE5A
28mcu_data: ksdk2_0
29processor_version: 0.0.1
30board: MIMXRT1010-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
84- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
85- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
86- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
87settings:
88- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
89- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
90- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
91- {id: CCM.IPG_PODF.scale, value: '4'}
92- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
93- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
94- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
95- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
96- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
97- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
98- {id: CCM_ANALOG.PLL2.denom, value: '1'}
99- {id: CCM_ANALOG.PLL2.div, value: '22'}
100- {id: CCM_ANALOG.PLL2.num, value: '0'}
101- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
102- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
103- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
104- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
105- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
106- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
108- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
109- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
111- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
112- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
113- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
115- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
116- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
117- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
118- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
120- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
121sources:
122- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
123- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
124 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
125
126/*******************************************************************************
127 * Variables for BOARD_BootClockRUN configuration
128 ******************************************************************************/
129const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
130 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
131 .numerator = 0, /* 30 bit numerator of fractional loop divider */
132 .denominator = 1, /* 30 bit denominator of fractional loop divider */
133 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
134};
135const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
136 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
137 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
138};
139const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
140 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
141 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
142};
143/*******************************************************************************
144 * Code for BOARD_BootClockRUN configuration
145 ******************************************************************************/
146void BOARD_BootClockRUN(void)
147{
148 /* Init RTC OSC clock frequency. */
149 CLOCK_SetRtcXtalFreq(32768U);
150 /* Enable 1MHz clock output. */
151 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
152 /* Use free 1MHz clock output. */
153 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
154 /* Set XTAL 24MHz clock frequency. */
155 CLOCK_SetXtalFreq(24000000U);
156 /* Enable XTAL 24MHz clock source. */
157 CLOCK_InitExternalClk(0);
158 /* Enable internal RC. */
159 CLOCK_InitRcOsc24M();
160 /* Switch clock source to external OSC. */
161 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
162 /* Set Oscillator ready counter value. */
163 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
164 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
165 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
166 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
167 /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
168 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
169 /* Waiting for DCDC_STS_DC_OK bit is asserted */
170 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
171 {
172 }
173 /* Set AHB_PODF. */
174 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
175 /* Disable IPG clock gate. */
176 CLOCK_DisableClock(kCLOCK_Adc1);
177 CLOCK_DisableClock(kCLOCK_Xbar1);
178 /* Set IPG_PODF. */
179 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
180 /* Disable PERCLK clock gate. */
181 CLOCK_DisableClock(kCLOCK_Gpt1);
182 CLOCK_DisableClock(kCLOCK_Gpt1S);
183 CLOCK_DisableClock(kCLOCK_Gpt2);
184 CLOCK_DisableClock(kCLOCK_Gpt2S);
185 CLOCK_DisableClock(kCLOCK_Pit);
186 /* Set PERCLK_PODF. */
187 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
188 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
189 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
190 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
191 * well.*/
192#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
193 /* Disable Flexspi clock gate. */
194 CLOCK_DisableClock(kCLOCK_FlexSpi);
195 /* Set FLEXSPI_PODF. */
196 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
197 /* Set Flexspi clock source. */
198 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
199 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
200#endif
201 /* Disable ADC_ACLK_EN clock gate. */
202 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
203 /* Set ADC_ACLK_PODF. */
204 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
205 /* Disable LPSPI clock gate. */
206 CLOCK_DisableClock(kCLOCK_Lpspi1);
207 CLOCK_DisableClock(kCLOCK_Lpspi2);
208 /* Set LPSPI_PODF. */
209 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
210 /* Set Lpspi clock source. */
211 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
212 /* Disable TRACE clock gate. */
213 CLOCK_DisableClock(kCLOCK_Trace);
214 /* Set TRACE_PODF. */
215 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
216 /* Set Trace clock source. */
217 CLOCK_SetMux(kCLOCK_TraceMux, 2);
218 /* Disable SAI1 clock gate. */
219 CLOCK_DisableClock(kCLOCK_Sai1);
220 /* Set SAI1_CLK_PRED. */
221 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
222 /* Set SAI1_CLK_PODF. */
223 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
224 /* Set Sai1 clock source. */
225 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
226 /* Disable SAI3 clock gate. */
227 CLOCK_DisableClock(kCLOCK_Sai3);
228 /* Set SAI3_CLK_PRED. */
229 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
230 /* Set SAI3_CLK_PODF. */
231 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
232 /* Set Sai3 clock source. */
233 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
234 /* Disable Lpi2c clock gate. */
235 CLOCK_DisableClock(kCLOCK_Lpi2c1);
236 CLOCK_DisableClock(kCLOCK_Lpi2c2);
237 /* Set LPI2C_CLK_PODF. */
238 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
239 /* Set Lpi2c clock source. */
240 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
241 /* Disable UART clock gate. */
242 CLOCK_DisableClock(kCLOCK_Lpuart1);
243 CLOCK_DisableClock(kCLOCK_Lpuart2);
244 CLOCK_DisableClock(kCLOCK_Lpuart3);
245 CLOCK_DisableClock(kCLOCK_Lpuart4);
246 /* Set UART_CLK_PODF. */
247 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
248 /* Set Uart clock source. */
249 CLOCK_SetMux(kCLOCK_UartMux, 0);
250 /* Disable SPDIF clock gate. */
251 CLOCK_DisableClock(kCLOCK_Spdif);
252 /* Set SPDIF0_CLK_PRED. */
253 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
254 /* Set SPDIF0_CLK_PODF. */
255 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
256 /* Set Spdif clock source. */
257 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
258 /* Disable Flexio1 clock gate. */
259 CLOCK_DisableClock(kCLOCK_Flexio1);
260 /* Set FLEXIO1_CLK_PRED. */
261 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
262 /* Set FLEXIO1_CLK_PODF. */
263 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
264 /* Set Flexio1 clock source. */
265 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
266 /* Set Pll3 sw clock source. */
267 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
268 /* Init System PLL. */
269 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
270 /* Init System pfd0. */
271 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
272 /* Init System pfd1. */
273 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
274 /* Init System pfd2. */
275 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
276 /* Init System pfd3. */
277 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
278 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
279 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
280 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
281 * well.*/
282#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
283 /* Init Usb1 PLL. */
284 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
285 /* Init Usb1 pfd0. */
286 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
287 /* Init Usb1 pfd1. */
288 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
289 /* Init Usb1 pfd2. */
290 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
291 /* Init Usb1 pfd3. */
292 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
293 /* Disable Usb1 PLL output for USBPHY1. */
294 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
295#endif
296 /* DeInit Audio PLL. */
297 CLOCK_DeinitAudioPll();
298 /* Bypass Audio PLL. */
299 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
300 /* Set divider for Audio PLL. */
301 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
302 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
303 /* Enable Audio PLL output. */
304 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
305 /* Init Enet PLL. */
306 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
307 /* Set preperiph clock source. */
308 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
309 /* Set periph clock source. */
310 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
311 /* Set periph clock2 clock source. */
312 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
313 /* Set per clock source. */
314 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
315 /* Set clock out1 divider. */
316 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
317 /* Set clock out1 source. */
318 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
319 /* Set clock out2 divider. */
320 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
321 /* Set clock out2 source. */
322 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
323 /* Set clock out1 drives clock out1. */
324 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
325 /* Disable clock out1. */
326 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
327 /* Disable clock out2. */
328 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
329 /* Set SAI1 MCLK1 clock source. */
330 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
331 /* Set SAI1 MCLK2 clock source. */
332 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
333 /* Set SAI1 MCLK3 clock source. */
334 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
335 /* Set SAI3 MCLK3 clock source. */
336 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
337 /* Set MQS configuration. */
338 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
339 /* Set GPT1 High frequency reference clock source. */
340 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
341 /* Set GPT2 High frequency reference clock source. */
342 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
343 /* Set SystemCoreClock variable. */
344 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
345}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.h
new file mode 100644
index 000000000..76f3df422
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/clock_config.h
@@ -0,0 +1,104 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
47#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
48#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
49#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
51#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
52#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
53#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
54#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
55#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
56#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
57#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
58#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
59#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
60#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
61#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
62#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
63#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
64#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
65#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
66#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
67#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
68#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
69#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
70#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
71#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
72#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
73#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
74#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
75#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL
76
77/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
78 */
79extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
80/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
81 */
82extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
83/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
84 */
85extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
86
87/*******************************************************************************
88 * API for BOARD_BootClockRUN configuration
89 ******************************************************************************/
90#if defined(__cplusplus)
91extern "C" {
92#endif /* __cplusplus*/
93
94/*!
95 * @brief This function executes configuration of clocks.
96 *
97 */
98void BOARD_BootClockRUN(void);
99
100#if defined(__cplusplus)
101}
102#endif /* __cplusplus*/
103
104#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.c
new file mode 100644
index 000000000..8fa06598a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.c
@@ -0,0 +1,61 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v6.0
17processor: MIMXRT1011xxxxx
18package_id: MIMXRT1011DAE5A
19mcu_data: ksdk2_0
20processor_version: 0.0.1
21board: MIMXRT1010-EVK
22functionalGroups:
23- name: BOARD_InitPeripherals
24 called_from_default_init: true
25 selectedCore: core0
26 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29component:
30- type: 'system'
31- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
32- global_system_definitions: []
33 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
34
35/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
36component:
37- type: 'msg'
38- type_id: 'msg_6e2baaf3b97dbeef01c0043275f9a0e7'
39- global_messages: []
40 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
41/* clang-format on */
42
43/***********************************************************************************************************************
44 * Included files
45 **********************************************************************************************************************/
46#include "peripherals.h"
47
48/***********************************************************************************************************************
49 * Initialization functions
50 **********************************************************************************************************************/
51void BOARD_InitPeripherals(void)
52{
53}
54
55/***********************************************************************************************************************
56 * BOARD_InitBootPeripherals function
57 **********************************************************************************************************************/
58void BOARD_InitBootPeripherals(void)
59{
60 BOARD_InitPeripherals();
61}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.h
new file mode 100644
index 000000000..96cfdfdd2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.c
new file mode 100644
index 000000000..be0d38d09
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v6.0
17processor: MIMXRT1011xxxxx
18package_id: MIMXRT1011DAE5A
19mcu_data: ksdk2_0
20processor_version: 0.0.4
21pin_labels:
22- {pin_num: '3', pin_signal: GPIO_09, label: UART1_RXD, identifier: UART1_RXD}
23- {pin_num: '2', pin_signal: GPIO_10, label: UART1_TXD, identifier: UART1_TXD}
24- {pin_num: '65', pin_signal: GPIO_SD_10, label: FlexSPI_CLK, identifier: FlexSPI_CLK}
25- {pin_num: '66', pin_signal: GPIO_SD_09, label: FlexSPI_D0_A, identifier: FlexSPI_D0_A}
26- {pin_num: '68', pin_signal: GPIO_SD_07, label: FlexSPI_D1_A, identifier: FlexSPI_D1_A}
27- {pin_num: '67', pin_signal: GPIO_SD_08, label: FlexSPI_D2_A, identifier: FlexSPI_D2_A}
28- {pin_num: '64', pin_signal: GPIO_SD_11, label: FlexSPI_D3_A, identifier: FlexSPI_D3_A}
29- {pin_num: '69', pin_signal: GPIO_SD_06, label: FlexSPI_SS0, identifier: FlexSPI_SS0}
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
31 */
32
33#include "fsl_common.h"
34#include "fsl_iomuxc.h"
35#include "pin_mux.h"
36
37/* FUNCTION ************************************************************************************************************
38 *
39 * Function Name : BOARD_InitBootPins
40 * Description : Calls initialization functions.
41 *
42 * END ****************************************************************************************************************/
43void BOARD_InitBootPins(void) {
44 BOARD_InitPins();
45 BOARD_InitDEBUG_UARTPins();
46}
47
48/*
49 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
50BOARD_InitPins:
51- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
52- pin_list: []
53 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
54 */
55
56/* FUNCTION ************************************************************************************************************
57 *
58 * Function Name : BOARD_InitPins
59 * Description : Configures pin routing and optionally pin electrical features.
60 *
61 * END ****************************************************************************************************************/
62void BOARD_InitPins(void) {
63}
64
65
66/*
67 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
68BOARD_InitDEBUG_UARTPins:
69- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
70- pin_list:
71 - {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
72 - {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
73 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
74 */
75
76/* FUNCTION ************************************************************************************************************
77 *
78 * Function Name : BOARD_InitDEBUG_UARTPins
79 * Description : Configures pin routing and optionally pin electrical features.
80 *
81 * END ****************************************************************************************************************/
82void BOARD_InitDEBUG_UARTPins(void) {
83 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
84
85 IOMUXC_SetPinMux(
86 IOMUXC_GPIO_09_LPUART1_RXD, /* GPIO_09 is configured as LPUART1_RXD */
87 0U); /* Software Input On Field: Input Path is determined by functionality */
88 IOMUXC_SetPinMux(
89 IOMUXC_GPIO_10_LPUART1_TXD, /* GPIO_10 is configured as LPUART1_TXD */
90 0U); /* Software Input On Field: Input Path is determined by functionality */
91}
92
93
94/*
95 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
96BOARD_InitQSPIPins:
97- options: {coreID: core0, enableClock: 'true'}
98- pin_list:
99 - {pin_num: '65', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_10}
100 - {pin_num: '66', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_09}
101 - {pin_num: '68', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_07}
102 - {pin_num: '67', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_08}
103 - {pin_num: '64', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_11}
104 - {pin_num: '69', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_06}
105 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
106 */
107
108/* FUNCTION ************************************************************************************************************
109 *
110 * Function Name : BOARD_InitQSPIPins
111 * Description : Configures pin routing and optionally pin electrical features.
112 *
113 * END ****************************************************************************************************************/
114void BOARD_InitQSPIPins(void) {
115 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
116
117 IOMUXC_SetPinMux(
118 IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, /* GPIO_SD_06 is configured as FLEXSPI_A_SS0_B */
119 0U); /* Software Input On Field: Input Path is determined by functionality */
120 IOMUXC_SetPinMux(
121 IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, /* GPIO_SD_07 is configured as FLEXSPI_A_DATA1 */
122 0U); /* Software Input On Field: Input Path is determined by functionality */
123 IOMUXC_SetPinMux(
124 IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, /* GPIO_SD_08 is configured as FLEXSPI_A_DATA2 */
125 0U); /* Software Input On Field: Input Path is determined by functionality */
126 IOMUXC_SetPinMux(
127 IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, /* GPIO_SD_09 is configured as FLEXSPI_A_DATA0 */
128 0U); /* Software Input On Field: Input Path is determined by functionality */
129 IOMUXC_SetPinMux(
130 IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, /* GPIO_SD_10 is configured as FLEXSPI_A_SCLK */
131 0U); /* Software Input On Field: Input Path is determined by functionality */
132 IOMUXC_SetPinMux(
133 IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, /* GPIO_SD_11 is configured as FLEXSPI_A_DATA3 */
134 0U); /* Software Input On Field: Input Path is determined by functionality */
135}
136
137/***********************************************************************************************************************
138 * EOF
139 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.h
new file mode 100644
index 000000000..a91e7aa41
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/project_template/pin_mux.h
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/***********************************************************************************************************************
17 * Definitions
18 **********************************************************************************************************************/
19
20/*! @brief Direction type */
21typedef enum _pin_mux_direction
22{
23 kPIN_MUX_DirectionInput = 0U, /* Input direction */
24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */
25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
26} pin_mux_direction_t;
27
28/*!
29 * @addtogroup pin_mux
30 * @{
31 */
32
33/***********************************************************************************************************************
34 * API
35 **********************************************************************************************************************/
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41/*!
42 * @brief Calls initialization functions.
43 *
44 */
45void BOARD_InitBootPins(void);
46
47
48/*!
49 * @brief Configures pin routing and optionally pin electrical features.
50 *
51 */
52void BOARD_InitPins(void);
53
54/* GPIO_09 (number 3), UART1_RXD */
55#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
56#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RXD /*!< LPUART1 signal: RXD */
57
58/* GPIO_10 (number 2), UART1_TXD */
59#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
60#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TXD /*!< LPUART1 signal: TXD */
61
62
63/*!
64 * @brief Configures pin routing and optionally pin electrical features.
65 *
66 */
67void BOARD_InitDEBUG_UARTPins(void);
68
69/* GPIO_SD_10 (number 65), FlexSPI_CLK */
70#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
71#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */
72
73/* GPIO_SD_09 (number 66), FlexSPI_D0_A */
74#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
75#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */
76
77/* GPIO_SD_07 (number 68), FlexSPI_D1_A */
78#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
79#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */
80
81/* GPIO_SD_08 (number 67), FlexSPI_D2_A */
82#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
83#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */
84
85/* GPIO_SD_11 (number 64), FlexSPI_D3_A */
86#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
87#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */
88
89/* GPIO_SD_06 (number 69), FlexSPI_SS0 */
90#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
91#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */
92
93
94/*!
95 * @brief Configures pin routing and optionally pin electrical features.
96 *
97 */
98void BOARD_InitQSPIPins(void);
99
100#if defined(__cplusplus)
101}
102#endif
103
104/*!
105 * @}
106 */
107#endif /* _PIN_MUX_H_ */
108
109/***********************************************************************************************************************
110 * EOF
111 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/driver_xip_board.cmake b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/driver_xip_board.cmake
new file mode 100644
index 000000000..db1925153
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/driver_xip_board.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_XIP_BOARD_INCLUDED)
2
3 set(DRIVER_XIP_BOARD_INCLUDED true CACHE BOOL "driver_xip_board component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.c
new file mode 100644
index 000000000..70c05509d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "evkmimxrt1010_flexspi_nor_config.h"
9
10/* Component ID definition, used by tools. */
11#ifndef FSL_COMPONENT_ID
12#define FSL_COMPONENT_ID "platform.drivers.xip_board"
13#endif
14
15/*******************************************************************************
16 * Code
17 ******************************************************************************/
18#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
19#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
20__attribute__((section(".boot_hdr.conf"), used))
21#elif defined(__ICCARM__)
22#pragma location = ".boot_hdr.conf"
23#endif
24
25const flexspi_nor_config_t qspiflash_config = {
26 .memConfig =
27 {
28 .tag = FLEXSPI_CFG_BLK_TAG,
29 .version = FLEXSPI_CFG_BLK_VERSION,
30 .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
31 .csHoldTime = 3u,
32 .csSetupTime = 3u,
33 .sflashPadType = kSerialFlash_4Pads,
34 .serialClkFreq = kFlexSpiSerialClk_100MHz,
35 .sflashA1Size = 16u * 1024u * 1024u,
36 .lookupTable =
37 {
38 // Read LUTs
39 FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
40 FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
41 },
42 },
43 .pageSize = 256u,
44 .sectorSize = 4u * 1024u,
45 .blockSize = 64u * 1024u,
46 .isUniformBlockSize = false,
47};
48#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.h
new file mode 100644
index 000000000..c38a2d951
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.h
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
9#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
10
11#include <stdint.h>
12#include <stdbool.h>
13#include "fsl_common.h"
14
15/*! @name Driver version */
16/*@{*/
17/*! @brief XIP_BOARD driver version 2.0.1. */
18#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
19/*@}*/
20
21/* FLEXSPI memory config block related defintions */
22#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
23#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
24#define FLEXSPI_CFG_BLK_SIZE (512)
25
26/* FLEXSPI Feature related definitions */
27#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
28
29/* Lookup table related defintions */
30#define CMD_INDEX_READ 0
31#define CMD_INDEX_READSTATUS 1
32#define CMD_INDEX_WRITEENABLE 2
33#define CMD_INDEX_WRITE 4
34
35#define CMD_LUT_SEQ_IDX_READ 0
36#define CMD_LUT_SEQ_IDX_READSTATUS 1
37#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
38#define CMD_LUT_SEQ_IDX_WRITE 9
39
40#define CMD_SDR 0x01
41#define CMD_DDR 0x21
42#define RADDR_SDR 0x02
43#define RADDR_DDR 0x22
44#define CADDR_SDR 0x03
45#define CADDR_DDR 0x23
46#define MODE1_SDR 0x04
47#define MODE1_DDR 0x24
48#define MODE2_SDR 0x05
49#define MODE2_DDR 0x25
50#define MODE4_SDR 0x06
51#define MODE4_DDR 0x26
52#define MODE8_SDR 0x07
53#define MODE8_DDR 0x27
54#define WRITE_SDR 0x08
55#define WRITE_DDR 0x28
56#define READ_SDR 0x09
57#define READ_DDR 0x29
58#define LEARN_SDR 0x0A
59#define LEARN_DDR 0x2A
60#define DATSZ_SDR 0x0B
61#define DATSZ_DDR 0x2B
62#define DUMMY_SDR 0x0C
63#define DUMMY_DDR 0x2C
64#define DUMMY_RWDS_SDR 0x0D
65#define DUMMY_RWDS_DDR 0x2D
66#define JMP_ON_CS 0x1F
67#define STOP 0
68
69#define FLEXSPI_1PAD 0
70#define FLEXSPI_2PAD 1
71#define FLEXSPI_4PAD 2
72#define FLEXSPI_8PAD 3
73
74#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
75 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
76 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
77
78//!@brief Definitions for FlexSPI Serial Clock Frequency
79typedef enum _FlexSpiSerialClockFreq
80{
81 kFlexSpiSerialClk_30MHz = 1,
82 kFlexSpiSerialClk_50MHz = 2,
83 kFlexSpiSerialClk_60MHz = 3,
84 kFlexSpiSerialClk_75MHz = 4,
85 kFlexSpiSerialClk_80MHz = 5,
86 kFlexSpiSerialClk_100MHz = 6,
87 kFlexSpiSerialClk_120MHz = 7,
88 kFlexSpiSerialClk_133MHz = 8,
89} flexspi_serial_clk_freq_t;
90
91//!@brief FlexSPI clock configuration type
92enum
93{
94 kFlexSpiClk_SDR, //!< Clock configure for SDR mode
95 kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
96};
97
98//!@brief FlexSPI Read Sample Clock Source definition
99typedef enum _FlashReadSampleClkSource
100{
101 kFlexSPIReadSampleClk_LoopbackInternally = 0,
102 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
103 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
104 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
105} flexspi_read_sample_clk_t;
106
107//!@brief Misc feature bit definitions
108enum
109{
110 kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
111 kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
112 kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
113 kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
114 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
115 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
116 kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
117};
118
119//!@brief Flash Type Definition
120enum
121{
122 kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
123 kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
124 kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
125 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
126 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
127};
128
129//!@brief Flash Pad Definitions
130enum
131{
132 kSerialFlash_1Pad = 1,
133 kSerialFlash_2Pads = 2,
134 kSerialFlash_4Pads = 4,
135 kSerialFlash_8Pads = 8,
136};
137
138//!@brief FlexSPI LUT Sequence structure
139typedef struct _lut_sequence
140{
141 uint8_t seqNum; //!< Sequence Number, valid number: 1-16
142 uint8_t seqId; //!< Sequence Index, valid number: 0-15
143 uint16_t reserved;
144} flexspi_lut_seq_t;
145
146//!@brief Flash Configuration Command Type
147enum
148{
149 kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
150 kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
151 kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
152 kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
153 kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
154 kDeviceConfigCmdType_Reset, //!< Reset device command
155};
156
157//!@brief FlexSPI Memory Configuration Block
158typedef struct _FlexSPIConfig
159{
160 uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
161 uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
162 uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
163 uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
164 uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
165 uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
166 uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
167 //! Serial NAND, need to refer to datasheet
168 uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
169 uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
170 //! Generic configuration, etc.
171 uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
172 //! DPI/QPI/OPI switch or reset command
173 flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
174 //! sequence number, [31:16] Reserved
175 uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
176 uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
177 uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
178 flexspi_lut_seq_t
179 configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
180 uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
181 uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
182 uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
183 uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
184 //! details
185 uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
186 uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
187 uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
188 //! Chapter for more details
189 uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
190 //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
191 uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
192 uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
193 uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
194 uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
195 uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
196 uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
197 uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
198 uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
199 uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
200 uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
201 uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
202 uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
203 uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
204 uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
205 //! busy flag is 0 when flash device is busy
206 uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
207 flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
208 uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
209} flexspi_mem_config_t;
210
211/* */
212#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
213#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
214#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
215#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
216#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
217#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
218#define NOR_CMD_INDEX_DUMMY 6 //!< 6
219#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
220
221#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
222#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
223 CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
224#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
225 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
226#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
227 CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
228#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
229 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
230#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
231#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
232#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
233 CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
234#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
235#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
236#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
237 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
238#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
239 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
240
241/*
242 * Serial NOR configuration block
243 */
244typedef struct _flexspi_nor_config
245{
246 flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
247 uint32_t pageSize; //!< Page size of Serial NOR
248 uint32_t sectorSize; //!< Sector size of Serial NOR
249 uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
250 uint8_t isUniformBlockSize; //!< Sector/Block size is the same
251 uint8_t reserved0[2]; //!< Reserved for future use
252 uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
253 uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
254 uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
255 uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
256 uint32_t blockSize; //!< Block size
257 uint32_t reserve2[11]; //!< Reserved for future use
258} flexspi_nor_config_t;
259
260#ifdef __cplusplus
261extern "C" {
262#endif
263
264#ifdef __cplusplus
265}
266#endif
267#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
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