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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c
new file mode 100644
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+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1010/clock_config.c
@@ -0,0 +1,348 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v7.0
26processor: MIMXRT1011xxxxx
27package_id: MIMXRT1011DAE5A
28mcu_data: ksdk2_0
29processor_version: 0.7.7
30board: MIMXRT1010-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
84- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
85- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
86- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
87settings:
88- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
89- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
90- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
91- {id: CCM.IPG_PODF.scale, value: '4'}
92- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
93- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
94- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
95- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
96- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
97- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
98- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
99- {id: CCM_ANALOG.PLL2.denom, value: '1'}
100- {id: CCM_ANALOG.PLL2.div, value: '22'}
101- {id: CCM_ANALOG.PLL2.num, value: '0'}
102- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
103- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
104- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
105- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
106- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
108- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
109- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
111- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
112- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
113- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
115- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
116- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
117- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
118- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
120- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
121- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
122sources:
123- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
124- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
125 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
126
127/*******************************************************************************
128 * Variables for BOARD_BootClockRUN configuration
129 ******************************************************************************/
130const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
131 {
132 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
133 .numerator = 0, /* 30 bit numerator of fractional loop divider */
134 .denominator = 1, /* 30 bit denominator of fractional loop divider */
135 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
136 };
137const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
138 {
139 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
140 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
141 };
142const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
143 {
144 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
145 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
146 };
147/*******************************************************************************
148 * Code for BOARD_BootClockRUN configuration
149 ******************************************************************************/
150void BOARD_BootClockRUN(void)
151{
152 /* Init RTC OSC clock frequency. */
153 CLOCK_SetRtcXtalFreq(32768U);
154 /* Enable 1MHz clock output. */
155 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
156 /* Use free 1MHz clock output. */
157 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
158 /* Set XTAL 24MHz clock frequency. */
159 CLOCK_SetXtalFreq(24000000U);
160 /* Enable XTAL 24MHz clock source. */
161 CLOCK_InitExternalClk(0);
162 /* Enable internal RC. */
163 CLOCK_InitRcOsc24M();
164 /* Switch clock source to external OSC. */
165 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
166 /* Set Oscillator ready counter value. */
167 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
168 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
169 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
170 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
171 /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
172 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
173 /* Waiting for DCDC_STS_DC_OK bit is asserted */
174 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
175 {
176 }
177 /* Set AHB_PODF. */
178 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
179 /* Disable IPG clock gate. */
180 CLOCK_DisableClock(kCLOCK_Adc1);
181 CLOCK_DisableClock(kCLOCK_Xbar1);
182 /* Set IPG_PODF. */
183 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
184 /* Disable PERCLK clock gate. */
185 CLOCK_DisableClock(kCLOCK_Gpt1);
186 CLOCK_DisableClock(kCLOCK_Gpt1S);
187 CLOCK_DisableClock(kCLOCK_Gpt2);
188 CLOCK_DisableClock(kCLOCK_Gpt2S);
189 CLOCK_DisableClock(kCLOCK_Pit);
190 /* Set PERCLK_PODF. */
191 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
192 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
193 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
194 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
195#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
196 /* Disable Flexspi clock gate. */
197 CLOCK_DisableClock(kCLOCK_FlexSpi);
198 /* Set FLEXSPI_PODF. */
199 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
200 /* Set Flexspi clock source. */
201 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
202 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
203#endif
204 /* Disable ADC_ACLK_EN clock gate. */
205 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
206 /* Set ADC_ACLK_PODF. */
207 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
208 /* Disable LPSPI clock gate. */
209 CLOCK_DisableClock(kCLOCK_Lpspi1);
210 CLOCK_DisableClock(kCLOCK_Lpspi2);
211 /* Set LPSPI_PODF. */
212 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
213 /* Set Lpspi clock source. */
214 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
215 /* Disable TRACE clock gate. */
216 CLOCK_DisableClock(kCLOCK_Trace);
217 /* Set TRACE_PODF. */
218 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
219 /* Set Trace clock source. */
220 CLOCK_SetMux(kCLOCK_TraceMux, 0);
221 /* Disable SAI1 clock gate. */
222 CLOCK_DisableClock(kCLOCK_Sai1);
223 /* Set SAI1_CLK_PRED. */
224 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
225 /* Set SAI1_CLK_PODF. */
226 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
227 /* Set Sai1 clock source. */
228 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
229 /* Disable SAI3 clock gate. */
230 CLOCK_DisableClock(kCLOCK_Sai3);
231 /* Set SAI3_CLK_PRED. */
232 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
233 /* Set SAI3_CLK_PODF. */
234 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
235 /* Set Sai3 clock source. */
236 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
237 /* Disable Lpi2c clock gate. */
238 CLOCK_DisableClock(kCLOCK_Lpi2c1);
239 CLOCK_DisableClock(kCLOCK_Lpi2c2);
240 /* Set LPI2C_CLK_PODF. */
241 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
242 /* Set Lpi2c clock source. */
243 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
244 /* Disable UART clock gate. */
245 CLOCK_DisableClock(kCLOCK_Lpuart1);
246 CLOCK_DisableClock(kCLOCK_Lpuart2);
247 CLOCK_DisableClock(kCLOCK_Lpuart3);
248 CLOCK_DisableClock(kCLOCK_Lpuart4);
249 /* Set UART_CLK_PODF. */
250 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
251 /* Set Uart clock source. */
252 CLOCK_SetMux(kCLOCK_UartMux, 0);
253 /* Disable SPDIF clock gate. */
254 CLOCK_DisableClock(kCLOCK_Spdif);
255 /* Set SPDIF0_CLK_PRED. */
256 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
257 /* Set SPDIF0_CLK_PODF. */
258 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
259 /* Set Spdif clock source. */
260 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
261 /* Disable Flexio1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Flexio1);
263 /* Set FLEXIO1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
265 /* Set FLEXIO1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
267 /* Set Flexio1 clock source. */
268 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
269 /* Set Pll3 sw clock source. */
270 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
271 /* Init System PLL. */
272 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
273 /* Init System pfd0. */
274 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
275 /* Init System pfd1. */
276 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
277 /* Init System pfd2. */
278 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
279 /* Init System pfd3. */
280 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
281 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
282 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
283 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
284#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
285 /* Init Usb1 PLL. */
286 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
287 /* Init Usb1 pfd0. */
288 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
289 /* Init Usb1 pfd1. */
290 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
291 /* Init Usb1 pfd2. */
292 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
293 /* Init Usb1 pfd3. */
294 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
295 /* Disable Usb1 PLL output for USBPHY1. */
296 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
297#endif
298 /* DeInit Audio PLL. */
299 CLOCK_DeinitAudioPll();
300 /* Bypass Audio PLL. */
301 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
302 /* Set divider for Audio PLL. */
303 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
304 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
305 /* Enable Audio PLL output. */
306 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
307 /* Init Enet PLL. */
308 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
309 /* Set preperiph clock source. */
310 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
311 /* Set periph clock source. */
312 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
313 /* Set periph clock2 clock source. */
314 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
315 /* Set per clock source. */
316 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
317 /* Set clock out1 divider. */
318 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
319 /* Set clock out1 source. */
320 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
321 /* Set clock out2 divider. */
322 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
323 /* Set clock out2 source. */
324 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
325 /* Set clock out1 drives clock out1. */
326 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
327 /* Disable clock out1. */
328 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
329 /* Disable clock out2. */
330 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
331 /* Set SAI1 MCLK1 clock source. */
332 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
333 /* Set SAI1 MCLK2 clock source. */
334 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
335 /* Set SAI1 MCLK3 clock source. */
336 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
337 /* Set SAI3 MCLK3 clock source. */
338 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
339 /* Set MQS configuration. */
340 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
341 /* Set GPT1 High frequency reference clock source. */
342 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
343 /* Set GPT2 High frequency reference clock source. */
344 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
345 /* Set SystemCoreClock variable. */
346 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
347}
348
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