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diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c
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1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v7.0
26processor: MIMXRT1064xxxxA
27package_id: MIMXRT1064DVL6A
28mcu_data: ksdk2_0
29processor_version: 0.7.9
30board: MIMXRT1064-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
70- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
71- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
72- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
73- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
74- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
75- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
76- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
77- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
78- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
79- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
80- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
81- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
82- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
83- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
84- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
85- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
86- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
87- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
88- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
89- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
90- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
94- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
95- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
96- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
97- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
98- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
99- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
100- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
101- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
102- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
103settings:
104- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
105- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
106- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
107- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
108- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
109- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
110- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
111- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
112- {id: CCM.SEMC_PODF.scale, value: '8'}
113- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
114- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
115- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
116- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
117- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
118- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
119- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
120- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
121- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
122- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
123- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
124- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
125- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
126- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
127- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
128- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
129- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
130- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
131- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
132- {id: CCM_ANALOG.PLL4.denom, value: '50'}
133- {id: CCM_ANALOG.PLL4.div, value: '47'}
134- {id: CCM_ANALOG.PLL5.denom, value: '1'}
135- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
136- {id: CCM_ANALOG.PLL5.num, value: '0'}
137- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
138- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
139- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
140- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
141- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
142- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
143sources:
144- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
145 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
146
147/*******************************************************************************
148 * Variables for BOARD_BootClockRUN configuration
149 ******************************************************************************/
150const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
151 {
152 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
153 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
154 };
155const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
156 {
157 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
158 .numerator = 0, /* 30 bit numerator of fractional loop divider */
159 .denominator = 1, /* 30 bit denominator of fractional loop divider */
160 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
161 };
162const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
163 {
164 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
165 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
166 };
167const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
168 {
169 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
170 .postDivider = 8, /* Divider after PLL */
171 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
172 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
173 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
174 };
175/*******************************************************************************
176 * Code for BOARD_BootClockRUN configuration
177 ******************************************************************************/
178void BOARD_BootClockRUN(void)
179{
180 /* Init RTC OSC clock frequency. */
181 CLOCK_SetRtcXtalFreq(32768U);
182 /* Enable 1MHz clock output. */
183 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
184 /* Use free 1MHz clock output. */
185 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
186 /* Set XTAL 24MHz clock frequency. */
187 CLOCK_SetXtalFreq(24000000U);
188 /* Enable XTAL 24MHz clock source. */
189 CLOCK_InitExternalClk(0);
190 /* Enable internal RC. */
191 CLOCK_InitRcOsc24M();
192 /* Switch clock source to external OSC. */
193 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
194 /* Set Oscillator ready counter value. */
195 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
196 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
197 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
198 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
199 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
200 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
201 /* Waiting for DCDC_STS_DC_OK bit is asserted */
202 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
203 {
204 }
205 /* Set AHB_PODF. */
206 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
207 /* Disable IPG clock gate. */
208 CLOCK_DisableClock(kCLOCK_Adc1);
209 CLOCK_DisableClock(kCLOCK_Adc2);
210 CLOCK_DisableClock(kCLOCK_Xbar1);
211 CLOCK_DisableClock(kCLOCK_Xbar2);
212 CLOCK_DisableClock(kCLOCK_Xbar3);
213 /* Set IPG_PODF. */
214 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
215 /* Set ARM_PODF. */
216 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
217 /* Set PERIPH_CLK2_PODF. */
218 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
219 /* Disable PERCLK clock gate. */
220 CLOCK_DisableClock(kCLOCK_Gpt1);
221 CLOCK_DisableClock(kCLOCK_Gpt1S);
222 CLOCK_DisableClock(kCLOCK_Gpt2);
223 CLOCK_DisableClock(kCLOCK_Gpt2S);
224 CLOCK_DisableClock(kCLOCK_Pit);
225 /* Set PERCLK_PODF. */
226 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
227 /* Disable USDHC1 clock gate. */
228 CLOCK_DisableClock(kCLOCK_Usdhc1);
229 /* Set USDHC1_PODF. */
230 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
231 /* Set Usdhc1 clock source. */
232 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
233 /* Disable USDHC2 clock gate. */
234 CLOCK_DisableClock(kCLOCK_Usdhc2);
235 /* Set USDHC2_PODF. */
236 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
237 /* Set Usdhc2 clock source. */
238 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
239 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
240 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
241 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
242#ifndef SKIP_SYSCLK_INIT
243 /* Disable Semc clock gate. */
244 CLOCK_DisableClock(kCLOCK_Semc);
245 /* Set SEMC_PODF. */
246 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
247 /* Set Semc alt clock source. */
248 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
249 /* Set Semc clock source. */
250 CLOCK_SetMux(kCLOCK_SemcMux, 0);
251#endif
252 /* Disable Flexspi clock gate. */
253 CLOCK_DisableClock(kCLOCK_FlexSpi);
254 /* Set FLEXSPI_PODF. */
255 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
256 /* Set Flexspi clock source. */
257 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
258 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
259 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
260 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
261#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
262 /* Disable Flexspi2 clock gate. */
263 CLOCK_DisableClock(kCLOCK_FlexSpi2);
264 /* Set FLEXSPI2_PODF. */
265 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
266 /* Set Flexspi2 clock source. */
267 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3);
268#endif
269 /* Disable CSI clock gate. */
270 CLOCK_DisableClock(kCLOCK_Csi);
271 /* Set CSI_PODF. */
272 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
273 /* Set Csi clock source. */
274 CLOCK_SetMux(kCLOCK_CsiMux, 0);
275 /* Disable LPSPI clock gate. */
276 CLOCK_DisableClock(kCLOCK_Lpspi1);
277 CLOCK_DisableClock(kCLOCK_Lpspi2);
278 CLOCK_DisableClock(kCLOCK_Lpspi3);
279 CLOCK_DisableClock(kCLOCK_Lpspi4);
280 /* Set LPSPI_PODF. */
281 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
282 /* Set Lpspi clock source. */
283 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
284 /* Disable TRACE clock gate. */
285 CLOCK_DisableClock(kCLOCK_Trace);
286 /* Set TRACE_PODF. */
287 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
288 /* Set Trace clock source. */
289 CLOCK_SetMux(kCLOCK_TraceMux, 0);
290 /* Disable SAI1 clock gate. */
291 CLOCK_DisableClock(kCLOCK_Sai1);
292 /* Set SAI1_CLK_PRED. */
293 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
294 /* Set SAI1_CLK_PODF. */
295 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
296 /* Set Sai1 clock source. */
297 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
298 /* Disable SAI2 clock gate. */
299 CLOCK_DisableClock(kCLOCK_Sai2);
300 /* Set SAI2_CLK_PRED. */
301 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
302 /* Set SAI2_CLK_PODF. */
303 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
304 /* Set Sai2 clock source. */
305 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
306 /* Disable SAI3 clock gate. */
307 CLOCK_DisableClock(kCLOCK_Sai3);
308 /* Set SAI3_CLK_PRED. */
309 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
310 /* Set SAI3_CLK_PODF. */
311 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
312 /* Set Sai3 clock source. */
313 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
314 /* Disable Lpi2c clock gate. */
315 CLOCK_DisableClock(kCLOCK_Lpi2c1);
316 CLOCK_DisableClock(kCLOCK_Lpi2c2);
317 CLOCK_DisableClock(kCLOCK_Lpi2c3);
318 /* Set LPI2C_CLK_PODF. */
319 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
320 /* Set Lpi2c clock source. */
321 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
322 /* Disable CAN clock gate. */
323 CLOCK_DisableClock(kCLOCK_Can1);
324 CLOCK_DisableClock(kCLOCK_Can2);
325 CLOCK_DisableClock(kCLOCK_Can3);
326 CLOCK_DisableClock(kCLOCK_Can1S);
327 CLOCK_DisableClock(kCLOCK_Can2S);
328 CLOCK_DisableClock(kCLOCK_Can3S);
329 /* Set CAN_CLK_PODF. */
330 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
331 /* Set Can clock source. */
332 CLOCK_SetMux(kCLOCK_CanMux, 2);
333 /* Disable UART clock gate. */
334 CLOCK_DisableClock(kCLOCK_Lpuart1);
335 CLOCK_DisableClock(kCLOCK_Lpuart2);
336 CLOCK_DisableClock(kCLOCK_Lpuart3);
337 CLOCK_DisableClock(kCLOCK_Lpuart4);
338 CLOCK_DisableClock(kCLOCK_Lpuart5);
339 CLOCK_DisableClock(kCLOCK_Lpuart6);
340 CLOCK_DisableClock(kCLOCK_Lpuart7);
341 CLOCK_DisableClock(kCLOCK_Lpuart8);
342 /* Set UART_CLK_PODF. */
343 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
344 /* Set Uart clock source. */
345 CLOCK_SetMux(kCLOCK_UartMux, 0);
346 /* Disable LCDIF clock gate. */
347 CLOCK_DisableClock(kCLOCK_LcdPixel);
348 /* Set LCDIF_PRED. */
349 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
350 /* Set LCDIF_CLK_PODF. */
351 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
352 /* Set Lcdif pre clock source. */
353 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
354 /* Disable SPDIF clock gate. */
355 CLOCK_DisableClock(kCLOCK_Spdif);
356 /* Set SPDIF0_CLK_PRED. */
357 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
358 /* Set SPDIF0_CLK_PODF. */
359 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
360 /* Set Spdif clock source. */
361 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
362 /* Disable Flexio1 clock gate. */
363 CLOCK_DisableClock(kCLOCK_Flexio1);
364 /* Set FLEXIO1_CLK_PRED. */
365 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
366 /* Set FLEXIO1_CLK_PODF. */
367 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
368 /* Set Flexio1 clock source. */
369 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
370 /* Disable Flexio2 clock gate. */
371 CLOCK_DisableClock(kCLOCK_Flexio2);
372 /* Set FLEXIO2_CLK_PRED. */
373 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
374 /* Set FLEXIO2_CLK_PODF. */
375 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
376 /* Set Flexio2 clock source. */
377 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
378 /* Set Pll3 sw clock source. */
379 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
380 /* Init ARM PLL. */
381 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
382 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
383 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
384 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
385#ifndef SKIP_SYSCLK_INIT
386#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
387 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
388#endif
389 /* Init System PLL. */
390 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
391 /* Init System pfd0. */
392 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
393 /* Init System pfd1. */
394 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
395 /* Init System pfd2. */
396 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
397 /* Init System pfd3. */
398 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
399#endif
400 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
401 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
402 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
403#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
404 /* Init Usb1 PLL. */
405 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
406 /* Init Usb1 pfd0. */
407 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
408 /* Init Usb1 pfd1. */
409 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
410 /* Init Usb1 pfd2. */
411 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
412 /* Init Usb1 pfd3. */
413 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
414 /* Disable Usb1 PLL output for USBPHY1. */
415 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
416#endif
417 /* DeInit Audio PLL. */
418 CLOCK_DeinitAudioPll();
419 /* Bypass Audio PLL. */
420 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
421 /* Set divider for Audio PLL. */
422 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
423 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
424 /* Enable Audio PLL output. */
425 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
426 /* Init Video PLL. */
427 uint32_t pllVideo;
428 /* Disable Video PLL output before initial Video PLL. */
429 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
430 /* Bypass PLL first */
431 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
432 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
433 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
434 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
435 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
436 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
437 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
438 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
439 CCM_ANALOG->PLL_VIDEO = pllVideo;
440 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
441 {
442 }
443 /* Disable bypass for Video PLL. */
444 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
445 /* DeInit Enet PLL. */
446 CLOCK_DeinitEnetPll();
447 /* Bypass Enet PLL. */
448 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
449 /* Set Enet output divider. */
450 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
451 /* Enable Enet output. */
452 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
453 /* Set Enet2 output divider. */
454 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
455 /* Enable Enet2 output. */
456 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
457 /* Enable Enet25M output. */
458 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
459 /* DeInit Usb2 PLL. */
460 CLOCK_DeinitUsb2Pll();
461 /* Bypass Usb2 PLL. */
462 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
463 /* Enable Usb2 PLL output. */
464 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
465 /* Set preperiph clock source. */
466 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
467 /* Set periph clock source. */
468 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
469 /* Set periph clock2 clock source. */
470 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
471 /* Set per clock source. */
472 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
473 /* Set lvds1 clock source. */
474 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
475 /* Set clock out1 divider. */
476 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
477 /* Set clock out1 source. */
478 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
479 /* Set clock out2 divider. */
480 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
481 /* Set clock out2 source. */
482 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
483 /* Set clock out1 drives clock out1. */
484 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
485 /* Disable clock out1. */
486 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
487 /* Disable clock out2. */
488 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
489 /* Set SAI1 MCLK1 clock source. */
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
491 /* Set SAI1 MCLK2 clock source. */
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
493 /* Set SAI1 MCLK3 clock source. */
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
495 /* Set SAI2 MCLK3 clock source. */
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
497 /* Set SAI3 MCLK3 clock source. */
498 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
499 /* Set MQS configuration. */
500 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
501 /* Set ENET1 Tx clock source. */
502 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
503 /* Set ENET2 Tx clock source. */
504#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
505 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
506#else
507 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
508#endif
509 /* Set GPT1 High frequency reference clock source. */
510 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
511 /* Set GPT2 High frequency reference clock source. */
512 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
513 /* Set SystemCoreClock variable. */
514 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
515}
516
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:18:36 +0100