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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.c389
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.h218
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c516
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.h126
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.c315
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.c389
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.h218
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.c493
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.h122
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.c315
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.c49
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.c1094
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.h938
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/driver_xip_board.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.c48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.h268
19 files changed, 5612 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.c
new file mode 100644
index 000000000..f7bd55665
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.c
@@ -0,0 +1,389 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
52void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
53{
54 lpi2c_master_config_t lpi2cConfig = {0};
55
56 /*
57 * lpi2cConfig.debugEnable = false;
58 * lpi2cConfig.ignoreAck = false;
59 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
60 * lpi2cConfig.baudRate_Hz = 100000U;
61 * lpi2cConfig.busIdleTimeout_ns = 0;
62 * lpi2cConfig.pinLowTimeout_ns = 0;
63 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
64 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
65 */
66 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
67 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
68}
69
70status_t BOARD_LPI2C_Send(LPI2C_Type *base,
71 uint8_t deviceAddress,
72 uint32_t subAddress,
73 uint8_t subAddressSize,
74 uint8_t *txBuff,
75 uint8_t txBuffSize)
76{
77 lpi2c_master_transfer_t xfer;
78
79 xfer.flags = kLPI2C_TransferDefaultFlag;
80 xfer.slaveAddress = deviceAddress;
81 xfer.direction = kLPI2C_Write;
82 xfer.subaddress = subAddress;
83 xfer.subaddressSize = subAddressSize;
84 xfer.data = txBuff;
85 xfer.dataSize = txBuffSize;
86
87 return LPI2C_MasterTransferBlocking(base, &xfer);
88}
89
90status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
91 uint8_t deviceAddress,
92 uint32_t subAddress,
93 uint8_t subAddressSize,
94 uint8_t *rxBuff,
95 uint8_t rxBuffSize)
96{
97 lpi2c_master_transfer_t xfer;
98
99 xfer.flags = kLPI2C_TransferDefaultFlag;
100 xfer.slaveAddress = deviceAddress;
101 xfer.direction = kLPI2C_Read;
102 xfer.subaddress = subAddress;
103 xfer.subaddressSize = subAddressSize;
104 xfer.data = rxBuff;
105 xfer.dataSize = rxBuffSize;
106
107 return LPI2C_MasterTransferBlocking(base, &xfer);
108}
109
110status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
111 uint8_t deviceAddress,
112 uint32_t subAddress,
113 uint8_t subAddressSize,
114 uint8_t *txBuff,
115 uint8_t txBuffSize)
116{
117 lpi2c_master_transfer_t xfer;
118
119 xfer.flags = kLPI2C_TransferDefaultFlag;
120 xfer.slaveAddress = deviceAddress;
121 xfer.direction = kLPI2C_Write;
122 xfer.subaddress = subAddress;
123 xfer.subaddressSize = subAddressSize;
124 xfer.data = txBuff;
125 xfer.dataSize = txBuffSize;
126
127 return LPI2C_MasterTransferBlocking(base, &xfer);
128}
129
130status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
131 uint8_t deviceAddress,
132 uint32_t subAddress,
133 uint8_t subAddressSize,
134 uint8_t *rxBuff,
135 uint8_t rxBuffSize)
136{
137 status_t status;
138 lpi2c_master_transfer_t xfer;
139
140 xfer.flags = kLPI2C_TransferDefaultFlag;
141 xfer.slaveAddress = deviceAddress;
142 xfer.direction = kLPI2C_Write;
143 xfer.subaddress = subAddress;
144 xfer.subaddressSize = subAddressSize;
145 xfer.data = NULL;
146 xfer.dataSize = 0;
147
148 status = LPI2C_MasterTransferBlocking(base, &xfer);
149
150 if (kStatus_Success == status)
151 {
152 xfer.subaddressSize = 0;
153 xfer.direction = kLPI2C_Read;
154 xfer.data = rxBuff;
155 xfer.dataSize = rxBuffSize;
156
157 status = LPI2C_MasterTransferBlocking(base, &xfer);
158 }
159
160 return status;
161}
162
163void BOARD_Accel_I2C_Init(void)
164{
165 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
166}
167
168status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
169{
170 uint8_t data = (uint8_t)txBuff;
171
172 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
173}
174
175status_t BOARD_Accel_I2C_Receive(
176 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
177{
178 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
179}
180
181void BOARD_Codec_I2C_Init(void)
182{
183 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
184}
185
186status_t BOARD_Codec_I2C_Send(
187 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
188{
189 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
190 txBuffSize);
191}
192
193status_t BOARD_Codec_I2C_Receive(
194 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
195{
196 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
197}
198
199void BOARD_Camera_I2C_Init(void)
200{
201 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
202 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
203 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
204}
205
206status_t BOARD_Camera_I2C_Send(
207 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
208{
209 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
210 txBuffSize);
211}
212
213status_t BOARD_Camera_I2C_Receive(
214 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
215{
216 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
217 rxBuffSize);
218}
219
220status_t BOARD_Camera_I2C_SendSCCB(
221 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
222{
223 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
224 txBuffSize);
225}
226
227status_t BOARD_Camera_I2C_ReceiveSCCB(
228 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
229{
230 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
231 rxBuffSize);
232}
233#endif /* SDK_I2C_BASED_COMPONENT_USED */
234
235/* MPU configuration. */
236void BOARD_ConfigMPU(void)
237{
238#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
239 extern uint32_t Image$$RW_m_ncache$$Base[];
240 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
241 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
242 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
243 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
244 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
245 0 :
246 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
247#elif defined(__MCUXPRESSO)
248 extern uint32_t __base_NCACHE_REGION;
249 extern uint32_t __top_NCACHE_REGION;
250 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
251 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
252#elif defined(__ICCARM__) || defined(__GNUC__)
253 extern uint32_t __NCACHE_REGION_START[];
254 extern uint32_t __NCACHE_REGION_SIZE[];
255 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
256 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
257#endif
258 volatile uint32_t i = 0;
259
260 /* Disable I cache and D cache */
261 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
262 {
263 SCB_DisableICache();
264 }
265 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
266 {
267 SCB_DisableDCache();
268 }
269
270 /* Disable MPU */
271 ARM_MPU_Disable();
272
273 /* MPU configure:
274 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
275 * SubRegionDisable, Size)
276 * API in mpu_armv7.h.
277 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
278 * disabled.
279 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
280 * Privileged mode.
281 * Use MACROS defined in mpu_armv7.h:
282 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
283 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
284 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
285 * 0 x 0 0 Strongly Ordered shareable
286 * 0 x 0 1 Device shareable
287 * 0 0 1 0 Normal not shareable Outer and inner write
288 * through no write allocate
289 * 0 0 1 1 Normal not shareable Outer and inner write
290 * back no write allocate
291 * 0 1 1 0 Normal shareable Outer and inner write
292 * through no write allocate
293 * 0 1 1 1 Normal shareable Outer and inner write
294 * back no write allocate
295 * 1 0 0 0 Normal not shareable outer and inner
296 * noncache
297 * 1 1 0 0 Normal shareable outer and inner
298 * noncache
299 * 1 0 1 1 Normal not shareable outer and inner write
300 * back write/read acllocate
301 * 1 1 1 1 Normal shareable outer and inner write
302 * back write/read acllocate
303 * 2 x 0 0 Device not shareable
304 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
305 * policy.
306 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
307 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
308 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
309 * mpu_armv7.h.
310 */
311 /*
312 * Add default region to deny access to whole address space to workaround speculative prefetch.
313 * Refer to Arm errata 1013783-B for more details.
314 *
315 */
316 /* Region 0 setting: Instruction access disabled, No data access permission. */
317 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
318 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
319
320 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
321 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
322 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
323
324 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
325 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
326 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
327
328#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
329 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
330 MPU->RBAR = ARM_MPU_RBAR(3, 0x70000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
332#endif
333
334 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
335 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
336 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
337
338 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
339 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
340 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
341
342 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
343 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
345
346 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
347 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
348 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
349
350 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
351 MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
352 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
353
354 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
355 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
356 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
357
358 while ((size >> i) > 0x1U)
359 {
360 i++;
361 }
362
363 if (i != 0)
364 {
365 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
366 assert(!(nonCacheStart % size));
367 assert(size == (uint32_t)(1 << i));
368 assert(i >= 5);
369
370 /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
371 MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
372 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
373 }
374
375 /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
376 MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
377 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
378
379 /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
380 MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
381 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
382
383 /* Enable MPU */
384 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
385
386 /* Enable I cache and D cache */
387 SCB_EnableDCache();
388 SCB_EnableICache();
389}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.h
new file mode 100644
index 000000000..641675035
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/board.h
@@ -0,0 +1,218 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14#include "fsl_clock.h"
15
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19/*! @brief The board name */
20#define BOARD_NAME "MIMXRT1064-EVK"
21
22/* The UART to use for debug messages. */
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
25#define BOARD_DEBUG_UART_INSTANCE 1U
26
27#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
28
29#define BOARD_UART_IRQ LPUART1_IRQn
30#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
31
32#ifndef BOARD_DEBUG_UART_BAUDRATE
33#define BOARD_DEBUG_UART_BAUDRATE (115200U)
34#endif /* BOARD_DEBUG_UART_BAUDRATE */
35
36/*! @brief The USER_LED used for board */
37#define LOGIC_LED_ON (0U)
38#define LOGIC_LED_OFF (1U)
39#ifndef BOARD_USER_LED_GPIO
40#define BOARD_USER_LED_GPIO GPIO1
41#endif
42#ifndef BOARD_USER_LED_GPIO_PIN
43#define BOARD_USER_LED_GPIO_PIN (9U)
44#endif
45
46#define USER_LED_INIT(output) \
47 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
48 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
49#define USER_LED_ON() \
50 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
51#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
52#define USER_LED_TOGGLE() \
53 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
54 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
55
56/*! @brief Define the port interrupt number for the board switches */
57#ifndef BOARD_USER_BUTTON_GPIO
58#define BOARD_USER_BUTTON_GPIO GPIO5
59#endif
60#ifndef BOARD_USER_BUTTON_GPIO_PIN
61#define BOARD_USER_BUTTON_GPIO_PIN (0U)
62#endif
63#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
64#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
65#define BOARD_USER_BUTTON_NAME "SW8"
66
67/*! @brief The board flash size */
68#define BOARD_FLASH_SIZE (0x400000U)
69
70/*! @brief The ENET PHY address. */
71#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
72
73/* USB PHY condfiguration */
74#define BOARD_USB_PHY_D_CAL (0x0CU)
75#define BOARD_USB_PHY_TXCAL45DP (0x06U)
76#define BOARD_USB_PHY_TXCAL45DM (0x06U)
77
78#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
79#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
80#define BOARD_ARDUINO_I2C_INDEX (1)
81
82/*! @brief The WIFI-QCA shield pin. */
83#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
84#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
85#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
86#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
87#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
88#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
89#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
90
91#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
92#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
93#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
94#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
95#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
96#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
97#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
98
99#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
100#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
101#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
102#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
103#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
104#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
105#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
106
107#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
108#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
109#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
110#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
111#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
112#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
113#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
114
115/* @Brief Board accelerator sensor configuration */
116#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
117/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
118#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
119/* Clock divider for LPI2C clock source */
120#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
121#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
122
123#define BOARD_CODEC_I2C_BASEADDR LPI2C1
124#define BOARD_CODEC_I2C_INSTANCE 1U
125#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
126#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
127#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
128
129/* @Brief Board CAMERA configuration */
130#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
131#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
132#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
133#define BOARD_CAMERA_I2C_CLOCK_FREQ \
134 (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
135
136#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
137#define BOARD_CAMERA_I2C_SCL_PIN 16
138#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
139#define BOARD_CAMERA_I2C_SDA_PIN 17
140#define BOARD_CAMERA_PWDN_GPIO GPIO1
141#define BOARD_CAMERA_PWDN_PIN 4
142
143/* @Brief Board Bluetooth HCI UART configuration */
144#define BOARD_BT_UART_BASEADDR LPUART3
145#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
146#define BOARD_BT_UART_IRQ LPUART3_IRQn
147#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
148
149/*! @brief board has sdcard */
150#define BOARD_HAS_SDCARD (1U)
151
152#if defined(__cplusplus)
153extern "C" {
154#endif /* __cplusplus */
155
156/*******************************************************************************
157 * API
158 ******************************************************************************/
159uint32_t BOARD_DebugConsoleSrcFreq(void);
160
161void BOARD_InitDebugConsole(void);
162
163void BOARD_ConfigMPU(void);
164#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
165void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
166status_t BOARD_LPI2C_Send(LPI2C_Type *base,
167 uint8_t deviceAddress,
168 uint32_t subAddress,
169 uint8_t subaddressSize,
170 uint8_t *txBuff,
171 uint8_t txBuffSize);
172status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
173 uint8_t deviceAddress,
174 uint32_t subAddress,
175 uint8_t subaddressSize,
176 uint8_t *rxBuff,
177 uint8_t rxBuffSize);
178status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
179 uint8_t deviceAddress,
180 uint32_t subAddress,
181 uint8_t subaddressSize,
182 uint8_t *txBuff,
183 uint8_t txBuffSize);
184status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
185 uint8_t deviceAddress,
186 uint32_t subAddress,
187 uint8_t subaddressSize,
188 uint8_t *rxBuff,
189 uint8_t rxBuffSize);
190void BOARD_Accel_I2C_Init(void);
191status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
192status_t BOARD_Accel_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
194void BOARD_Codec_I2C_Init(void);
195status_t BOARD_Codec_I2C_Send(
196 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
197status_t BOARD_Codec_I2C_Receive(
198 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
199void BOARD_Camera_I2C_Init(void);
200status_t BOARD_Camera_I2C_Send(
201 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
202status_t BOARD_Camera_I2C_Receive(
203 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
204
205status_t BOARD_Camera_I2C_SendSCCB(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
207status_t BOARD_Camera_I2C_ReceiveSCCB(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
209#endif /* SDK_I2C_BASED_COMPONENT_USED */
210
211void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
212void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
213
214#if defined(__cplusplus)
215}
216#endif /* __cplusplus */
217
218#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c
new file mode 100644
index 000000000..0a709a2d4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.c
@@ -0,0 +1,516 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v7.0
26processor: MIMXRT1064xxxxA
27package_id: MIMXRT1064DVL6A
28mcu_data: ksdk2_0
29processor_version: 0.7.9
30board: MIMXRT1064-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
70- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
71- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
72- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
73- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
74- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
75- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
76- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
77- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
78- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
79- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
80- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
81- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
82- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
83- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
84- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
85- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
86- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
87- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
88- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
89- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
90- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
94- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
95- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
96- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
97- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
98- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
99- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
100- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
101- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
102- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
103settings:
104- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
105- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
106- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
107- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
108- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
109- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
110- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
111- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
112- {id: CCM.SEMC_PODF.scale, value: '8'}
113- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
114- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
115- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
116- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
117- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
118- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
119- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
120- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
121- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
122- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
123- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
124- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
125- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
126- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
127- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
128- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
129- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
130- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
131- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
132- {id: CCM_ANALOG.PLL4.denom, value: '50'}
133- {id: CCM_ANALOG.PLL4.div, value: '47'}
134- {id: CCM_ANALOG.PLL5.denom, value: '1'}
135- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
136- {id: CCM_ANALOG.PLL5.num, value: '0'}
137- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
138- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
139- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
140- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
141- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
142- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
143sources:
144- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
145 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
146
147/*******************************************************************************
148 * Variables for BOARD_BootClockRUN configuration
149 ******************************************************************************/
150const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
151 {
152 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
153 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
154 };
155const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
156 {
157 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
158 .numerator = 0, /* 30 bit numerator of fractional loop divider */
159 .denominator = 1, /* 30 bit denominator of fractional loop divider */
160 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
161 };
162const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
163 {
164 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
165 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
166 };
167const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
168 {
169 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
170 .postDivider = 8, /* Divider after PLL */
171 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
172 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
173 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
174 };
175/*******************************************************************************
176 * Code for BOARD_BootClockRUN configuration
177 ******************************************************************************/
178void BOARD_BootClockRUN(void)
179{
180 /* Init RTC OSC clock frequency. */
181 CLOCK_SetRtcXtalFreq(32768U);
182 /* Enable 1MHz clock output. */
183 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
184 /* Use free 1MHz clock output. */
185 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
186 /* Set XTAL 24MHz clock frequency. */
187 CLOCK_SetXtalFreq(24000000U);
188 /* Enable XTAL 24MHz clock source. */
189 CLOCK_InitExternalClk(0);
190 /* Enable internal RC. */
191 CLOCK_InitRcOsc24M();
192 /* Switch clock source to external OSC. */
193 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
194 /* Set Oscillator ready counter value. */
195 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
196 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
197 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
198 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
199 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
200 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
201 /* Waiting for DCDC_STS_DC_OK bit is asserted */
202 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
203 {
204 }
205 /* Set AHB_PODF. */
206 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
207 /* Disable IPG clock gate. */
208 CLOCK_DisableClock(kCLOCK_Adc1);
209 CLOCK_DisableClock(kCLOCK_Adc2);
210 CLOCK_DisableClock(kCLOCK_Xbar1);
211 CLOCK_DisableClock(kCLOCK_Xbar2);
212 CLOCK_DisableClock(kCLOCK_Xbar3);
213 /* Set IPG_PODF. */
214 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
215 /* Set ARM_PODF. */
216 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
217 /* Set PERIPH_CLK2_PODF. */
218 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
219 /* Disable PERCLK clock gate. */
220 CLOCK_DisableClock(kCLOCK_Gpt1);
221 CLOCK_DisableClock(kCLOCK_Gpt1S);
222 CLOCK_DisableClock(kCLOCK_Gpt2);
223 CLOCK_DisableClock(kCLOCK_Gpt2S);
224 CLOCK_DisableClock(kCLOCK_Pit);
225 /* Set PERCLK_PODF. */
226 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
227 /* Disable USDHC1 clock gate. */
228 CLOCK_DisableClock(kCLOCK_Usdhc1);
229 /* Set USDHC1_PODF. */
230 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
231 /* Set Usdhc1 clock source. */
232 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
233 /* Disable USDHC2 clock gate. */
234 CLOCK_DisableClock(kCLOCK_Usdhc2);
235 /* Set USDHC2_PODF. */
236 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
237 /* Set Usdhc2 clock source. */
238 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
239 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
240 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
241 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
242#ifndef SKIP_SYSCLK_INIT
243 /* Disable Semc clock gate. */
244 CLOCK_DisableClock(kCLOCK_Semc);
245 /* Set SEMC_PODF. */
246 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
247 /* Set Semc alt clock source. */
248 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
249 /* Set Semc clock source. */
250 CLOCK_SetMux(kCLOCK_SemcMux, 0);
251#endif
252 /* Disable Flexspi clock gate. */
253 CLOCK_DisableClock(kCLOCK_FlexSpi);
254 /* Set FLEXSPI_PODF. */
255 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
256 /* Set Flexspi clock source. */
257 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
258 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
259 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
260 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
261#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
262 /* Disable Flexspi2 clock gate. */
263 CLOCK_DisableClock(kCLOCK_FlexSpi2);
264 /* Set FLEXSPI2_PODF. */
265 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
266 /* Set Flexspi2 clock source. */
267 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3);
268#endif
269 /* Disable CSI clock gate. */
270 CLOCK_DisableClock(kCLOCK_Csi);
271 /* Set CSI_PODF. */
272 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
273 /* Set Csi clock source. */
274 CLOCK_SetMux(kCLOCK_CsiMux, 0);
275 /* Disable LPSPI clock gate. */
276 CLOCK_DisableClock(kCLOCK_Lpspi1);
277 CLOCK_DisableClock(kCLOCK_Lpspi2);
278 CLOCK_DisableClock(kCLOCK_Lpspi3);
279 CLOCK_DisableClock(kCLOCK_Lpspi4);
280 /* Set LPSPI_PODF. */
281 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
282 /* Set Lpspi clock source. */
283 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
284 /* Disable TRACE clock gate. */
285 CLOCK_DisableClock(kCLOCK_Trace);
286 /* Set TRACE_PODF. */
287 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
288 /* Set Trace clock source. */
289 CLOCK_SetMux(kCLOCK_TraceMux, 0);
290 /* Disable SAI1 clock gate. */
291 CLOCK_DisableClock(kCLOCK_Sai1);
292 /* Set SAI1_CLK_PRED. */
293 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
294 /* Set SAI1_CLK_PODF. */
295 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
296 /* Set Sai1 clock source. */
297 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
298 /* Disable SAI2 clock gate. */
299 CLOCK_DisableClock(kCLOCK_Sai2);
300 /* Set SAI2_CLK_PRED. */
301 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
302 /* Set SAI2_CLK_PODF. */
303 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
304 /* Set Sai2 clock source. */
305 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
306 /* Disable SAI3 clock gate. */
307 CLOCK_DisableClock(kCLOCK_Sai3);
308 /* Set SAI3_CLK_PRED. */
309 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
310 /* Set SAI3_CLK_PODF. */
311 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
312 /* Set Sai3 clock source. */
313 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
314 /* Disable Lpi2c clock gate. */
315 CLOCK_DisableClock(kCLOCK_Lpi2c1);
316 CLOCK_DisableClock(kCLOCK_Lpi2c2);
317 CLOCK_DisableClock(kCLOCK_Lpi2c3);
318 /* Set LPI2C_CLK_PODF. */
319 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
320 /* Set Lpi2c clock source. */
321 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
322 /* Disable CAN clock gate. */
323 CLOCK_DisableClock(kCLOCK_Can1);
324 CLOCK_DisableClock(kCLOCK_Can2);
325 CLOCK_DisableClock(kCLOCK_Can3);
326 CLOCK_DisableClock(kCLOCK_Can1S);
327 CLOCK_DisableClock(kCLOCK_Can2S);
328 CLOCK_DisableClock(kCLOCK_Can3S);
329 /* Set CAN_CLK_PODF. */
330 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
331 /* Set Can clock source. */
332 CLOCK_SetMux(kCLOCK_CanMux, 2);
333 /* Disable UART clock gate. */
334 CLOCK_DisableClock(kCLOCK_Lpuart1);
335 CLOCK_DisableClock(kCLOCK_Lpuart2);
336 CLOCK_DisableClock(kCLOCK_Lpuart3);
337 CLOCK_DisableClock(kCLOCK_Lpuart4);
338 CLOCK_DisableClock(kCLOCK_Lpuart5);
339 CLOCK_DisableClock(kCLOCK_Lpuart6);
340 CLOCK_DisableClock(kCLOCK_Lpuart7);
341 CLOCK_DisableClock(kCLOCK_Lpuart8);
342 /* Set UART_CLK_PODF. */
343 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
344 /* Set Uart clock source. */
345 CLOCK_SetMux(kCLOCK_UartMux, 0);
346 /* Disable LCDIF clock gate. */
347 CLOCK_DisableClock(kCLOCK_LcdPixel);
348 /* Set LCDIF_PRED. */
349 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
350 /* Set LCDIF_CLK_PODF. */
351 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
352 /* Set Lcdif pre clock source. */
353 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
354 /* Disable SPDIF clock gate. */
355 CLOCK_DisableClock(kCLOCK_Spdif);
356 /* Set SPDIF0_CLK_PRED. */
357 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
358 /* Set SPDIF0_CLK_PODF. */
359 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
360 /* Set Spdif clock source. */
361 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
362 /* Disable Flexio1 clock gate. */
363 CLOCK_DisableClock(kCLOCK_Flexio1);
364 /* Set FLEXIO1_CLK_PRED. */
365 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
366 /* Set FLEXIO1_CLK_PODF. */
367 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
368 /* Set Flexio1 clock source. */
369 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
370 /* Disable Flexio2 clock gate. */
371 CLOCK_DisableClock(kCLOCK_Flexio2);
372 /* Set FLEXIO2_CLK_PRED. */
373 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
374 /* Set FLEXIO2_CLK_PODF. */
375 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
376 /* Set Flexio2 clock source. */
377 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
378 /* Set Pll3 sw clock source. */
379 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
380 /* Init ARM PLL. */
381 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
382 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
383 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
384 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
385#ifndef SKIP_SYSCLK_INIT
386#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
387 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
388#endif
389 /* Init System PLL. */
390 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
391 /* Init System pfd0. */
392 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
393 /* Init System pfd1. */
394 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
395 /* Init System pfd2. */
396 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
397 /* Init System pfd3. */
398 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
399#endif
400 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
401 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
402 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
403#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
404 /* Init Usb1 PLL. */
405 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
406 /* Init Usb1 pfd0. */
407 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
408 /* Init Usb1 pfd1. */
409 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
410 /* Init Usb1 pfd2. */
411 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
412 /* Init Usb1 pfd3. */
413 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
414 /* Disable Usb1 PLL output for USBPHY1. */
415 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
416#endif
417 /* DeInit Audio PLL. */
418 CLOCK_DeinitAudioPll();
419 /* Bypass Audio PLL. */
420 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
421 /* Set divider for Audio PLL. */
422 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
423 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
424 /* Enable Audio PLL output. */
425 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
426 /* Init Video PLL. */
427 uint32_t pllVideo;
428 /* Disable Video PLL output before initial Video PLL. */
429 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
430 /* Bypass PLL first */
431 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
432 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
433 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
434 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
435 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
436 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
437 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
438 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
439 CCM_ANALOG->PLL_VIDEO = pllVideo;
440 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
441 {
442 }
443 /* Disable bypass for Video PLL. */
444 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
445 /* DeInit Enet PLL. */
446 CLOCK_DeinitEnetPll();
447 /* Bypass Enet PLL. */
448 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
449 /* Set Enet output divider. */
450 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
451 /* Enable Enet output. */
452 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
453 /* Set Enet2 output divider. */
454 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
455 /* Enable Enet2 output. */
456 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
457 /* Enable Enet25M output. */
458 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
459 /* DeInit Usb2 PLL. */
460 CLOCK_DeinitUsb2Pll();
461 /* Bypass Usb2 PLL. */
462 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
463 /* Enable Usb2 PLL output. */
464 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
465 /* Set preperiph clock source. */
466 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
467 /* Set periph clock source. */
468 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
469 /* Set periph clock2 clock source. */
470 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
471 /* Set per clock source. */
472 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
473 /* Set lvds1 clock source. */
474 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
475 /* Set clock out1 divider. */
476 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
477 /* Set clock out1 source. */
478 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
479 /* Set clock out2 divider. */
480 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
481 /* Set clock out2 source. */
482 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
483 /* Set clock out1 drives clock out1. */
484 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
485 /* Disable clock out1. */
486 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
487 /* Disable clock out2. */
488 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
489 /* Set SAI1 MCLK1 clock source. */
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
491 /* Set SAI1 MCLK2 clock source. */
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
493 /* Set SAI1 MCLK3 clock source. */
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
495 /* Set SAI2 MCLK3 clock source. */
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
497 /* Set SAI3 MCLK3 clock source. */
498 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
499 /* Set MQS configuration. */
500 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
501 /* Set ENET1 Tx clock source. */
502 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
503 /* Set ENET2 Tx clock source. */
504#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
505 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
506#else
507 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
508#endif
509 /* Set GPT1 High frequency reference clock source. */
510 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
511 /* Set GPT2 High frequency reference clock source. */
512 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
513 /* Set SystemCoreClock variable. */
514 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
515}
516
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.h
new file mode 100644
index 000000000..a03f3199e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/clock_config.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
47#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
48#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
49#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
51#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
52#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
53#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
54#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
55#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
56#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
57#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
58#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
59#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
60#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
61#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
62#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
63#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
64#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
65#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
66#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
67#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
68#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
69#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
70#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
71#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
72#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
73#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
74#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
76#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
77#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
78#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
79#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
80#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
81#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
82#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
83#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
84#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
85#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
86#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
87#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
88#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
89#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
90#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
91#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
92#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
93#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
94
95/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
96 */
97extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
98/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
99 */
100extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
101/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
102 */
103extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
104/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
105 */
106extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
107
108/*******************************************************************************
109 * API for BOARD_BootClockRUN configuration
110 ******************************************************************************/
111#if defined(__cplusplus)
112extern "C" {
113#endif /* __cplusplus*/
114
115/*!
116 * @brief This function executes configuration of clocks.
117 *
118 */
119void BOARD_BootClockRUN(void);
120
121#if defined(__cplusplus)
122}
123#endif /* __cplusplus*/
124
125#endif /* _CLOCK_CONFIG_H_ */
126
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.c
new file mode 100644
index 000000000..6f2b63f8d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.c
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#include "dcd.h"
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.xip_board"
18#endif
19
20#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
21#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
22#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
23__attribute__((section(".boot_hdr.dcd_data"), used))
24#elif defined(__ICCARM__)
25#pragma location = ".boot_hdr.dcd_data"
26#endif
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29!!GlobalInfo
30product: DCDx V2.0
31processor: MIMXRT1064xxxxA
32package_id: MIMXRT1064DVL6A
33mcu_data: ksdk2_0
34processor_version: 0.0.0
35board: MIMXRT1064-EVK
36output_format: c_array
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
39const uint8_t dcd_data[] = {
40 /* HEADER */
41 /* Tag */
42 0xD2,
43 /* Image Length */
44 0x04, 0x10,
45 /* Version */
46 0x41,
47
48 /* COMMANDS */
49
50 /* group: 'Imported Commands' */
51 /* #1.1-113, command header bytes for merged 'Write - value' command */
52 0xCC, 0x03, 0x8C, 0x04,
53 /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
54 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
55 /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
56 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
57 /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
58 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
59 /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
60 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
61 /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
62 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
63 /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
64 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
65 /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
66 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
67 /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
68 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
69 /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
70 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
71 /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
72 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
73 /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
74 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
75 /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
76 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
77 /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
78 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
79 /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
80 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
81 /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
82 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
83 /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
84 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
85 /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
86 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
87 /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
88 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
89 /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
90 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
91 /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
92 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
93 /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
94 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
95 /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
96 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
97 /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
98 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
99 /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
100 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
101 /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
102 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
103 /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
104 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
105 /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
106 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
107 /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
108 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
109 /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
110 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
111 /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
112 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
113 /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
114 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
115 /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
116 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
117 /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
118 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
119 /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
120 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
121 /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
122 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
123 /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
124 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
125 /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
126 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
127 /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
128 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
129 /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
130 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
131 /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
132 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
133 /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
134 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
135 /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
136 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
137 /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
138 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
139 /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
140 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
141 /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
142 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
143 /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
144 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
145 /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
146 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
147 /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
148 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
149 /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
150 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
151 /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
152 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
153 /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
154 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
155 /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
156 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
157 /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
158 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
159 /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
160 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
161 /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
162 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
163 /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
164 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
165 /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
166 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
167 /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
168 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
169 /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
170 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
171 /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
172 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
173 /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
174 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
175 /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
176 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
177 /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
178 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
179 /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
180 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
181 /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
182 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
183 /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
184 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
185 /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
186 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
187 /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
188 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
189 /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
190 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
191 /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
192 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
193 /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
194 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
195 /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
196 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
197 /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
198 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
199 /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
200 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
201 /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
202 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
203 /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
204 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
205 /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
206 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
207 /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
208 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
209 /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
210 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
211 /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
212 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
213 /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
214 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
215 /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
216 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
217 /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
218 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
219 /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
220 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
221 /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
222 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
223 /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
224 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
225 /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
226 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
227 /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
228 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
229 /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
230 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
231 /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
232 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
233 /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
234 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
235 /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
236 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
237 /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
238 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
239 /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
240 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
241 /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
242 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
243 /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
244 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
245 /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
246 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
247 /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
248 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
249 /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
250 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
251 /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
252 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
253 /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
254 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
255 /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
256 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
257 /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
258 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
259 /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
260 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
261 /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
262 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
263 /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
264 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
265 /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
266 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
267 /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
268 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
269 /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
270 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
271 /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
272 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
273 /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
274 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
275 /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
276 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
277 /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
278 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
279 /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
280 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
281 /* #3.1-2, command header bytes for merged 'Write - value' command */
282 0xCC, 0x00, 0x14, 0x04,
283 /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
284 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
285 /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
286 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
287 /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
288 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
289 /* #5.1-2, command header bytes for merged 'Write - value' command */
290 0xCC, 0x00, 0x14, 0x04,
291 /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
292 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
293 /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
294 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
295 /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
296 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
297 /* #7.1-3, command header bytes for merged 'Write - value' command */
298 0xCC, 0x00, 0x1C, 0x04,
299 /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
300 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
301 /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
302 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
303 /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
304 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
305 /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
306 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
307 /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
308 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
309 };
310/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
311
312#else
313const uint8_t dcd_data[] = {0x00};
314#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
315#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.h
new file mode 100644
index 000000000..185b0ecd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/dcd.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef __DCD__
14#define __DCD__
15
16#include <stdint.h>
17
18/*! @name Driver version */
19/*@{*/
20/*! @brief XIP_BOARD driver version 2.0.1. */
21#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22/*@}*/
23
24/*************************************
25 * DCD Data
26 *************************************/
27#define DCD_TAG_HEADER (0xD2)
28#define DCD_VERSION (0x41)
29#define DCD_TAG_HEADER_SHIFT (24)
30#define DCD_ARRAY_SIZE 1
31
32#endif /* __DCD__ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.c
new file mode 100644
index 000000000..f7bd55665
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.c
@@ -0,0 +1,389 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
52void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
53{
54 lpi2c_master_config_t lpi2cConfig = {0};
55
56 /*
57 * lpi2cConfig.debugEnable = false;
58 * lpi2cConfig.ignoreAck = false;
59 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
60 * lpi2cConfig.baudRate_Hz = 100000U;
61 * lpi2cConfig.busIdleTimeout_ns = 0;
62 * lpi2cConfig.pinLowTimeout_ns = 0;
63 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
64 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
65 */
66 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
67 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
68}
69
70status_t BOARD_LPI2C_Send(LPI2C_Type *base,
71 uint8_t deviceAddress,
72 uint32_t subAddress,
73 uint8_t subAddressSize,
74 uint8_t *txBuff,
75 uint8_t txBuffSize)
76{
77 lpi2c_master_transfer_t xfer;
78
79 xfer.flags = kLPI2C_TransferDefaultFlag;
80 xfer.slaveAddress = deviceAddress;
81 xfer.direction = kLPI2C_Write;
82 xfer.subaddress = subAddress;
83 xfer.subaddressSize = subAddressSize;
84 xfer.data = txBuff;
85 xfer.dataSize = txBuffSize;
86
87 return LPI2C_MasterTransferBlocking(base, &xfer);
88}
89
90status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
91 uint8_t deviceAddress,
92 uint32_t subAddress,
93 uint8_t subAddressSize,
94 uint8_t *rxBuff,
95 uint8_t rxBuffSize)
96{
97 lpi2c_master_transfer_t xfer;
98
99 xfer.flags = kLPI2C_TransferDefaultFlag;
100 xfer.slaveAddress = deviceAddress;
101 xfer.direction = kLPI2C_Read;
102 xfer.subaddress = subAddress;
103 xfer.subaddressSize = subAddressSize;
104 xfer.data = rxBuff;
105 xfer.dataSize = rxBuffSize;
106
107 return LPI2C_MasterTransferBlocking(base, &xfer);
108}
109
110status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
111 uint8_t deviceAddress,
112 uint32_t subAddress,
113 uint8_t subAddressSize,
114 uint8_t *txBuff,
115 uint8_t txBuffSize)
116{
117 lpi2c_master_transfer_t xfer;
118
119 xfer.flags = kLPI2C_TransferDefaultFlag;
120 xfer.slaveAddress = deviceAddress;
121 xfer.direction = kLPI2C_Write;
122 xfer.subaddress = subAddress;
123 xfer.subaddressSize = subAddressSize;
124 xfer.data = txBuff;
125 xfer.dataSize = txBuffSize;
126
127 return LPI2C_MasterTransferBlocking(base, &xfer);
128}
129
130status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
131 uint8_t deviceAddress,
132 uint32_t subAddress,
133 uint8_t subAddressSize,
134 uint8_t *rxBuff,
135 uint8_t rxBuffSize)
136{
137 status_t status;
138 lpi2c_master_transfer_t xfer;
139
140 xfer.flags = kLPI2C_TransferDefaultFlag;
141 xfer.slaveAddress = deviceAddress;
142 xfer.direction = kLPI2C_Write;
143 xfer.subaddress = subAddress;
144 xfer.subaddressSize = subAddressSize;
145 xfer.data = NULL;
146 xfer.dataSize = 0;
147
148 status = LPI2C_MasterTransferBlocking(base, &xfer);
149
150 if (kStatus_Success == status)
151 {
152 xfer.subaddressSize = 0;
153 xfer.direction = kLPI2C_Read;
154 xfer.data = rxBuff;
155 xfer.dataSize = rxBuffSize;
156
157 status = LPI2C_MasterTransferBlocking(base, &xfer);
158 }
159
160 return status;
161}
162
163void BOARD_Accel_I2C_Init(void)
164{
165 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
166}
167
168status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
169{
170 uint8_t data = (uint8_t)txBuff;
171
172 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
173}
174
175status_t BOARD_Accel_I2C_Receive(
176 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
177{
178 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
179}
180
181void BOARD_Codec_I2C_Init(void)
182{
183 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
184}
185
186status_t BOARD_Codec_I2C_Send(
187 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
188{
189 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
190 txBuffSize);
191}
192
193status_t BOARD_Codec_I2C_Receive(
194 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
195{
196 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
197}
198
199void BOARD_Camera_I2C_Init(void)
200{
201 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
202 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
203 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
204}
205
206status_t BOARD_Camera_I2C_Send(
207 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
208{
209 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
210 txBuffSize);
211}
212
213status_t BOARD_Camera_I2C_Receive(
214 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
215{
216 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
217 rxBuffSize);
218}
219
220status_t BOARD_Camera_I2C_SendSCCB(
221 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
222{
223 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
224 txBuffSize);
225}
226
227status_t BOARD_Camera_I2C_ReceiveSCCB(
228 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
229{
230 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
231 rxBuffSize);
232}
233#endif /* SDK_I2C_BASED_COMPONENT_USED */
234
235/* MPU configuration. */
236void BOARD_ConfigMPU(void)
237{
238#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
239 extern uint32_t Image$$RW_m_ncache$$Base[];
240 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
241 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
242 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
243 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
244 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
245 0 :
246 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
247#elif defined(__MCUXPRESSO)
248 extern uint32_t __base_NCACHE_REGION;
249 extern uint32_t __top_NCACHE_REGION;
250 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
251 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
252#elif defined(__ICCARM__) || defined(__GNUC__)
253 extern uint32_t __NCACHE_REGION_START[];
254 extern uint32_t __NCACHE_REGION_SIZE[];
255 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
256 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
257#endif
258 volatile uint32_t i = 0;
259
260 /* Disable I cache and D cache */
261 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
262 {
263 SCB_DisableICache();
264 }
265 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
266 {
267 SCB_DisableDCache();
268 }
269
270 /* Disable MPU */
271 ARM_MPU_Disable();
272
273 /* MPU configure:
274 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
275 * SubRegionDisable, Size)
276 * API in mpu_armv7.h.
277 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
278 * disabled.
279 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
280 * Privileged mode.
281 * Use MACROS defined in mpu_armv7.h:
282 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
283 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
284 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
285 * 0 x 0 0 Strongly Ordered shareable
286 * 0 x 0 1 Device shareable
287 * 0 0 1 0 Normal not shareable Outer and inner write
288 * through no write allocate
289 * 0 0 1 1 Normal not shareable Outer and inner write
290 * back no write allocate
291 * 0 1 1 0 Normal shareable Outer and inner write
292 * through no write allocate
293 * 0 1 1 1 Normal shareable Outer and inner write
294 * back no write allocate
295 * 1 0 0 0 Normal not shareable outer and inner
296 * noncache
297 * 1 1 0 0 Normal shareable outer and inner
298 * noncache
299 * 1 0 1 1 Normal not shareable outer and inner write
300 * back write/read acllocate
301 * 1 1 1 1 Normal shareable outer and inner write
302 * back write/read acllocate
303 * 2 x 0 0 Device not shareable
304 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
305 * policy.
306 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
307 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
308 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
309 * mpu_armv7.h.
310 */
311 /*
312 * Add default region to deny access to whole address space to workaround speculative prefetch.
313 * Refer to Arm errata 1013783-B for more details.
314 *
315 */
316 /* Region 0 setting: Instruction access disabled, No data access permission. */
317 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
318 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
319
320 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
321 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
322 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
323
324 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
325 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
326 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
327
328#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
329 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
330 MPU->RBAR = ARM_MPU_RBAR(3, 0x70000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
332#endif
333
334 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
335 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
336 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
337
338 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
339 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
340 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
341
342 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
343 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
345
346 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
347 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
348 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
349
350 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
351 MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
352 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
353
354 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
355 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
356 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
357
358 while ((size >> i) > 0x1U)
359 {
360 i++;
361 }
362
363 if (i != 0)
364 {
365 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
366 assert(!(nonCacheStart % size));
367 assert(size == (uint32_t)(1 << i));
368 assert(i >= 5);
369
370 /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
371 MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
372 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
373 }
374
375 /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
376 MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
377 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
378
379 /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
380 MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
381 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
382
383 /* Enable MPU */
384 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
385
386 /* Enable I cache and D cache */
387 SCB_EnableDCache();
388 SCB_EnableICache();
389}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.h
new file mode 100644
index 000000000..641675035
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/board.h
@@ -0,0 +1,218 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14#include "fsl_clock.h"
15
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19/*! @brief The board name */
20#define BOARD_NAME "MIMXRT1064-EVK"
21
22/* The UART to use for debug messages. */
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
25#define BOARD_DEBUG_UART_INSTANCE 1U
26
27#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
28
29#define BOARD_UART_IRQ LPUART1_IRQn
30#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
31
32#ifndef BOARD_DEBUG_UART_BAUDRATE
33#define BOARD_DEBUG_UART_BAUDRATE (115200U)
34#endif /* BOARD_DEBUG_UART_BAUDRATE */
35
36/*! @brief The USER_LED used for board */
37#define LOGIC_LED_ON (0U)
38#define LOGIC_LED_OFF (1U)
39#ifndef BOARD_USER_LED_GPIO
40#define BOARD_USER_LED_GPIO GPIO1
41#endif
42#ifndef BOARD_USER_LED_GPIO_PIN
43#define BOARD_USER_LED_GPIO_PIN (9U)
44#endif
45
46#define USER_LED_INIT(output) \
47 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
48 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
49#define USER_LED_ON() \
50 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
51#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
52#define USER_LED_TOGGLE() \
53 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
54 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
55
56/*! @brief Define the port interrupt number for the board switches */
57#ifndef BOARD_USER_BUTTON_GPIO
58#define BOARD_USER_BUTTON_GPIO GPIO5
59#endif
60#ifndef BOARD_USER_BUTTON_GPIO_PIN
61#define BOARD_USER_BUTTON_GPIO_PIN (0U)
62#endif
63#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
64#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
65#define BOARD_USER_BUTTON_NAME "SW8"
66
67/*! @brief The board flash size */
68#define BOARD_FLASH_SIZE (0x400000U)
69
70/*! @brief The ENET PHY address. */
71#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
72
73/* USB PHY condfiguration */
74#define BOARD_USB_PHY_D_CAL (0x0CU)
75#define BOARD_USB_PHY_TXCAL45DP (0x06U)
76#define BOARD_USB_PHY_TXCAL45DM (0x06U)
77
78#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
79#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
80#define BOARD_ARDUINO_I2C_INDEX (1)
81
82/*! @brief The WIFI-QCA shield pin. */
83#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
84#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
85#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
86#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
87#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
88#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
89#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
90
91#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
92#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
93#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
94#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
95#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
96#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
97#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
98
99#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
100#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
101#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
102#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
103#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
104#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
105#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
106
107#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
108#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
109#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
110#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
111#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
112#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
113#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
114
115/* @Brief Board accelerator sensor configuration */
116#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
117/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
118#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
119/* Clock divider for LPI2C clock source */
120#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
121#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
122
123#define BOARD_CODEC_I2C_BASEADDR LPI2C1
124#define BOARD_CODEC_I2C_INSTANCE 1U
125#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
126#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
127#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
128
129/* @Brief Board CAMERA configuration */
130#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
131#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
132#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
133#define BOARD_CAMERA_I2C_CLOCK_FREQ \
134 (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
135
136#define BOARD_CAMERA_I2C_SCL_GPIO GPIO1
137#define BOARD_CAMERA_I2C_SCL_PIN 16
138#define BOARD_CAMERA_I2C_SDA_GPIO GPIO1
139#define BOARD_CAMERA_I2C_SDA_PIN 17
140#define BOARD_CAMERA_PWDN_GPIO GPIO1
141#define BOARD_CAMERA_PWDN_PIN 4
142
143/* @Brief Board Bluetooth HCI UART configuration */
144#define BOARD_BT_UART_BASEADDR LPUART3
145#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
146#define BOARD_BT_UART_IRQ LPUART3_IRQn
147#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
148
149/*! @brief board has sdcard */
150#define BOARD_HAS_SDCARD (1U)
151
152#if defined(__cplusplus)
153extern "C" {
154#endif /* __cplusplus */
155
156/*******************************************************************************
157 * API
158 ******************************************************************************/
159uint32_t BOARD_DebugConsoleSrcFreq(void);
160
161void BOARD_InitDebugConsole(void);
162
163void BOARD_ConfigMPU(void);
164#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
165void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
166status_t BOARD_LPI2C_Send(LPI2C_Type *base,
167 uint8_t deviceAddress,
168 uint32_t subAddress,
169 uint8_t subaddressSize,
170 uint8_t *txBuff,
171 uint8_t txBuffSize);
172status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
173 uint8_t deviceAddress,
174 uint32_t subAddress,
175 uint8_t subaddressSize,
176 uint8_t *rxBuff,
177 uint8_t rxBuffSize);
178status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
179 uint8_t deviceAddress,
180 uint32_t subAddress,
181 uint8_t subaddressSize,
182 uint8_t *txBuff,
183 uint8_t txBuffSize);
184status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
185 uint8_t deviceAddress,
186 uint32_t subAddress,
187 uint8_t subaddressSize,
188 uint8_t *rxBuff,
189 uint8_t rxBuffSize);
190void BOARD_Accel_I2C_Init(void);
191status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
192status_t BOARD_Accel_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
194void BOARD_Codec_I2C_Init(void);
195status_t BOARD_Codec_I2C_Send(
196 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
197status_t BOARD_Codec_I2C_Receive(
198 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
199void BOARD_Camera_I2C_Init(void);
200status_t BOARD_Camera_I2C_Send(
201 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
202status_t BOARD_Camera_I2C_Receive(
203 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
204
205status_t BOARD_Camera_I2C_SendSCCB(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
207status_t BOARD_Camera_I2C_ReceiveSCCB(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
209#endif /* SDK_I2C_BASED_COMPONENT_USED */
210
211void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
212void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
213
214#if defined(__cplusplus)
215}
216#endif /* __cplusplus */
217
218#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.c
new file mode 100644
index 000000000..9a22cd4b8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.c
@@ -0,0 +1,493 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1064xxxxA
27package_id: MIMXRT1064DVL6A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1064-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
70- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
71- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
72- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
73- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
74- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
75- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
76- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
77- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
78- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
79- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
80- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
81- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
82- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
83- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
84- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
85- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
86- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
87- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
88- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
89- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
90- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
94- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
95- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
96- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
97- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
98- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
99- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
100- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
101- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
102- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
103settings:
104- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
105- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
106- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
107- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
108- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
109- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
110- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
111- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
112- {id: CCM.SEMC_PODF.scale, value: '8'}
113- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
114- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
115- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
116- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
117- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
118- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
119- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
120- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
121- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
122- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
123- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
124- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
125- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
126- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
127- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
128- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
129- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
130- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
131- {id: CCM_ANALOG.PLL4.denom, value: '50'}
132- {id: CCM_ANALOG.PLL4.div, value: '47'}
133- {id: CCM_ANALOG.PLL5.denom, value: '1'}
134- {id: CCM_ANALOG.PLL5.div, value: '40'}
135- {id: CCM_ANALOG.PLL5.num, value: '0'}
136- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
137- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
138sources:
139- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
140- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
141 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
142
143/*******************************************************************************
144 * Variables for BOARD_BootClockRUN configuration
145 ******************************************************************************/
146const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
147 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
148 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149};
150const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
151 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
152 .numerator = 0, /* 30 bit numerator of fractional loop divider */
153 .denominator = 1, /* 30 bit denominator of fractional loop divider */
154 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
155};
156const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
157 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
158 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
159};
160/*******************************************************************************
161 * Code for BOARD_BootClockRUN configuration
162 ******************************************************************************/
163void BOARD_BootClockRUN(void)
164{
165 /* Init RTC OSC clock frequency. */
166 CLOCK_SetRtcXtalFreq(32768U);
167 /* Enable 1MHz clock output. */
168 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
169 /* Use free 1MHz clock output. */
170 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
171 /* Set XTAL 24MHz clock frequency. */
172 CLOCK_SetXtalFreq(24000000U);
173 /* Enable XTAL 24MHz clock source. */
174 CLOCK_InitExternalClk(0);
175 /* Enable internal RC. */
176 CLOCK_InitRcOsc24M();
177 /* Switch clock source to external OSC. */
178 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
179 /* Set Oscillator ready counter value. */
180 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
181 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
182 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
183 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
184 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
185 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
186 /* Waiting for DCDC_STS_DC_OK bit is asserted */
187 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
188 {
189 }
190 /* Set AHB_PODF. */
191 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
192 /* Disable IPG clock gate. */
193 CLOCK_DisableClock(kCLOCK_Adc1);
194 CLOCK_DisableClock(kCLOCK_Adc2);
195 CLOCK_DisableClock(kCLOCK_Xbar1);
196 CLOCK_DisableClock(kCLOCK_Xbar2);
197 CLOCK_DisableClock(kCLOCK_Xbar3);
198 /* Set IPG_PODF. */
199 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
200 /* Set ARM_PODF. */
201 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
202 /* Set PERIPH_CLK2_PODF. */
203 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
204 /* Disable PERCLK clock gate. */
205 CLOCK_DisableClock(kCLOCK_Gpt1);
206 CLOCK_DisableClock(kCLOCK_Gpt1S);
207 CLOCK_DisableClock(kCLOCK_Gpt2);
208 CLOCK_DisableClock(kCLOCK_Gpt2S);
209 CLOCK_DisableClock(kCLOCK_Pit);
210 /* Set PERCLK_PODF. */
211 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
212 /* Disable USDHC1 clock gate. */
213 CLOCK_DisableClock(kCLOCK_Usdhc1);
214 /* Set USDHC1_PODF. */
215 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
216 /* Set Usdhc1 clock source. */
217 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
218 /* Disable USDHC2 clock gate. */
219 CLOCK_DisableClock(kCLOCK_Usdhc2);
220 /* Set USDHC2_PODF. */
221 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
222 /* Set Usdhc2 clock source. */
223 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
224 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
225 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
226 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
227 * well.*/
228#ifndef SKIP_SYSCLK_INIT
229 /* Disable Semc clock gate. */
230 CLOCK_DisableClock(kCLOCK_Semc);
231 /* Set SEMC_PODF. */
232 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
233 /* Set Semc alt clock source. */
234 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
235 /* Set Semc clock source. */
236 CLOCK_SetMux(kCLOCK_SemcMux, 0);
237#endif
238 /* Disable Flexspi clock gate. */
239 CLOCK_DisableClock(kCLOCK_FlexSpi);
240 /* Set FLEXSPI_PODF. */
241 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
242 /* Set Flexspi clock source. */
243 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
244 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
245 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left
246 * unchanged.
247 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
248#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
249 /* Disable Flexspi2 clock gate. */
250 CLOCK_DisableClock(kCLOCK_FlexSpi2);
251 /* Set FLEXSPI2_PODF. */
252 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
253 /* Set Flexspi2 clock source. */
254 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
255#endif
256 /* Disable CSI clock gate. */
257 CLOCK_DisableClock(kCLOCK_Csi);
258 /* Set CSI_PODF. */
259 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
260 /* Set Csi clock source. */
261 CLOCK_SetMux(kCLOCK_CsiMux, 0);
262 /* Disable LPSPI clock gate. */
263 CLOCK_DisableClock(kCLOCK_Lpspi1);
264 CLOCK_DisableClock(kCLOCK_Lpspi2);
265 CLOCK_DisableClock(kCLOCK_Lpspi3);
266 CLOCK_DisableClock(kCLOCK_Lpspi4);
267 /* Set LPSPI_PODF. */
268 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
269 /* Set Lpspi clock source. */
270 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
271 /* Disable TRACE clock gate. */
272 CLOCK_DisableClock(kCLOCK_Trace);
273 /* Set TRACE_PODF. */
274 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
275 /* Set Trace clock source. */
276 CLOCK_SetMux(kCLOCK_TraceMux, 2);
277 /* Disable SAI1 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai1);
279 /* Set SAI1_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
281 /* Set SAI1_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
283 /* Set Sai1 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
285 /* Disable SAI2 clock gate. */
286 CLOCK_DisableClock(kCLOCK_Sai2);
287 /* Set SAI2_CLK_PRED. */
288 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
289 /* Set SAI2_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
291 /* Set Sai2 clock source. */
292 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
293 /* Disable SAI3 clock gate. */
294 CLOCK_DisableClock(kCLOCK_Sai3);
295 /* Set SAI3_CLK_PRED. */
296 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
297 /* Set SAI3_CLK_PODF. */
298 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
299 /* Set Sai3 clock source. */
300 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
301 /* Disable Lpi2c clock gate. */
302 CLOCK_DisableClock(kCLOCK_Lpi2c1);
303 CLOCK_DisableClock(kCLOCK_Lpi2c2);
304 CLOCK_DisableClock(kCLOCK_Lpi2c3);
305 /* Set LPI2C_CLK_PODF. */
306 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
307 /* Set Lpi2c clock source. */
308 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
309 /* Disable CAN clock gate. */
310 CLOCK_DisableClock(kCLOCK_Can1);
311 CLOCK_DisableClock(kCLOCK_Can2);
312 CLOCK_DisableClock(kCLOCK_Can3);
313 CLOCK_DisableClock(kCLOCK_Can1S);
314 CLOCK_DisableClock(kCLOCK_Can2S);
315 CLOCK_DisableClock(kCLOCK_Can3S);
316 /* Set CAN_CLK_PODF. */
317 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
318 /* Set Can clock source. */
319 CLOCK_SetMux(kCLOCK_CanMux, 2);
320 /* Disable UART clock gate. */
321 CLOCK_DisableClock(kCLOCK_Lpuart1);
322 CLOCK_DisableClock(kCLOCK_Lpuart2);
323 CLOCK_DisableClock(kCLOCK_Lpuart3);
324 CLOCK_DisableClock(kCLOCK_Lpuart4);
325 CLOCK_DisableClock(kCLOCK_Lpuart5);
326 CLOCK_DisableClock(kCLOCK_Lpuart6);
327 CLOCK_DisableClock(kCLOCK_Lpuart7);
328 CLOCK_DisableClock(kCLOCK_Lpuart8);
329 /* Set UART_CLK_PODF. */
330 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
331 /* Set Uart clock source. */
332 CLOCK_SetMux(kCLOCK_UartMux, 0);
333 /* Disable LCDIF clock gate. */
334 CLOCK_DisableClock(kCLOCK_LcdPixel);
335 /* Set LCDIF_PRED. */
336 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
337 /* Set LCDIF_CLK_PODF. */
338 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
339 /* Set Lcdif pre clock source. */
340 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
341 /* Disable SPDIF clock gate. */
342 CLOCK_DisableClock(kCLOCK_Spdif);
343 /* Set SPDIF0_CLK_PRED. */
344 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
345 /* Set SPDIF0_CLK_PODF. */
346 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
347 /* Set Spdif clock source. */
348 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
349 /* Disable Flexio1 clock gate. */
350 CLOCK_DisableClock(kCLOCK_Flexio1);
351 /* Set FLEXIO1_CLK_PRED. */
352 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
353 /* Set FLEXIO1_CLK_PODF. */
354 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
355 /* Set Flexio1 clock source. */
356 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
357 /* Disable Flexio2 clock gate. */
358 CLOCK_DisableClock(kCLOCK_Flexio2);
359 /* Set FLEXIO2_CLK_PRED. */
360 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
361 /* Set FLEXIO2_CLK_PODF. */
362 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
363 /* Set Flexio2 clock source. */
364 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
365 /* Set Pll3 sw clock source. */
366 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
367 /* Init ARM PLL. */
368 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
369 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
370 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
371 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
372 * well.*/
373#ifndef SKIP_SYSCLK_INIT
374 /* Init System PLL. */
375 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
376 /* Init System pfd0. */
377 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
378 /* Init System pfd1. */
379 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
380 /* Init System pfd2. */
381 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
382 /* Init System pfd3. */
383 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
384#endif
385 /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
386 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left
387 * unchanged.
388 * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
389#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
390 /* Init Usb1 PLL. */
391 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
392 /* Init Usb1 pfd0. */
393 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
394 /* Init Usb1 pfd1. */
395 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
396 /* Init Usb1 pfd2. */
397 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
398 /* Init Usb1 pfd3. */
399 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
400 /* Disable Usb1 PLL output for USBPHY1. */
401 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
402#endif
403 /* DeInit Audio PLL. */
404 CLOCK_DeinitAudioPll();
405 /* Bypass Audio PLL. */
406 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
407 /* Set divider for Audio PLL. */
408 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
409 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
410 /* Enable Audio PLL output. */
411 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
412 /* DeInit Video PLL. */
413 CLOCK_DeinitVideoPll();
414 /* Bypass Video PLL. */
415 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
416 /* Set divider for Video PLL. */
417 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
418 /* Enable Video PLL output. */
419 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
420 /* DeInit Enet PLL. */
421 CLOCK_DeinitEnetPll();
422 /* Bypass Enet PLL. */
423 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
424 /* Set Enet output divider. */
425 CCM_ANALOG->PLL_ENET =
426 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
427 /* Enable Enet output. */
428 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
429 /* Set Enet2 output divider. */
430 CCM_ANALOG->PLL_ENET =
431 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
432 /* Enable Enet2 output. */
433 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
434 /* Enable Enet25M output. */
435 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
436 /* DeInit Usb2 PLL. */
437 CLOCK_DeinitUsb2Pll();
438 /* Bypass Usb2 PLL. */
439 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
440 /* Enable Usb2 PLL output. */
441 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
442 /* Set preperiph clock source. */
443 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
444 /* Set periph clock source. */
445 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
446 /* Set periph clock2 clock source. */
447 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
448 /* Set per clock source. */
449 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
450 /* Set lvds1 clock source. */
451 CCM_ANALOG->MISC1 =
452 (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
453 /* Set clock out1 divider. */
454 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
455 /* Set clock out1 source. */
456 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
457 /* Set clock out2 divider. */
458 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
459 /* Set clock out2 source. */
460 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
461 /* Set clock out1 drives clock out1. */
462 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
463 /* Disable clock out1. */
464 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
465 /* Disable clock out2. */
466 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
467 /* Set SAI1 MCLK1 clock source. */
468 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
469 /* Set SAI1 MCLK2 clock source. */
470 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
471 /* Set SAI1 MCLK3 clock source. */
472 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
473 /* Set SAI2 MCLK3 clock source. */
474 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
475 /* Set SAI3 MCLK3 clock source. */
476 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
477 /* Set MQS configuration. */
478 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
479 /* Set ENET1 Tx clock source. */
480 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
481 /* Set ENET2 Tx clock source. */
482#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
483 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
484#else
485 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
486#endif
487 /* Set GPT1 High frequency reference clock source. */
488 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
489 /* Set GPT2 High frequency reference clock source. */
490 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
491 /* Set SystemCoreClock variable. */
492 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
493}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.h
new file mode 100644
index 000000000..13bc925a1
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/clock_config.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
47#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
48#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
49#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
51#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
52#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
53#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
54#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
55#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
56#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
57#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
58#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
59#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
60#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
61#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
62#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
63#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
64#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
65#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
66#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
67#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
68#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
69#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
70#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
71#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
72#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
73#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
74#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
76#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
77#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
78#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
79#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
80#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
81#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
82#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
83#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
84#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
85#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
86#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
87#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
88#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
89#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
90#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
91#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
92#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
93#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
94
95/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
96 */
97extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
98/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
99 */
100extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
101/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
102 */
103extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
104
105/*******************************************************************************
106 * API for BOARD_BootClockRUN configuration
107 ******************************************************************************/
108#if defined(__cplusplus)
109extern "C" {
110#endif /* __cplusplus*/
111
112/*!
113 * @brief This function executes configuration of clocks.
114 *
115 */
116void BOARD_BootClockRUN(void);
117
118#if defined(__cplusplus)
119}
120#endif /* __cplusplus*/
121
122#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.c
new file mode 100644
index 000000000..6f2b63f8d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.c
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#include "dcd.h"
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.xip_board"
18#endif
19
20#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
21#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
22#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
23__attribute__((section(".boot_hdr.dcd_data"), used))
24#elif defined(__ICCARM__)
25#pragma location = ".boot_hdr.dcd_data"
26#endif
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29!!GlobalInfo
30product: DCDx V2.0
31processor: MIMXRT1064xxxxA
32package_id: MIMXRT1064DVL6A
33mcu_data: ksdk2_0
34processor_version: 0.0.0
35board: MIMXRT1064-EVK
36output_format: c_array
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
39const uint8_t dcd_data[] = {
40 /* HEADER */
41 /* Tag */
42 0xD2,
43 /* Image Length */
44 0x04, 0x10,
45 /* Version */
46 0x41,
47
48 /* COMMANDS */
49
50 /* group: 'Imported Commands' */
51 /* #1.1-113, command header bytes for merged 'Write - value' command */
52 0xCC, 0x03, 0x8C, 0x04,
53 /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
54 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
55 /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
56 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
57 /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
58 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
59 /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
60 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
61 /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
62 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
63 /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
64 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
65 /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
66 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
67 /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
68 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
69 /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
70 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
71 /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
72 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
73 /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
74 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
75 /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
76 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
77 /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
78 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
79 /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
80 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
81 /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
82 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
83 /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
84 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
85 /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
86 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
87 /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
88 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
89 /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
90 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
91 /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
92 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
93 /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
94 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
95 /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
96 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
97 /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
98 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
99 /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
100 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
101 /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
102 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
103 /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
104 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
105 /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
106 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
107 /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
108 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
109 /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
110 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
111 /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
112 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
113 /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
114 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
115 /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
116 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
117 /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
118 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
119 /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
120 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
121 /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
122 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
123 /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
124 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
125 /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
126 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
127 /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
128 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
129 /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
130 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
131 /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
132 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
133 /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
134 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
135 /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
136 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
137 /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
138 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
139 /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
140 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
141 /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
142 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
143 /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
144 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
145 /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
146 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
147 /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
148 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
149 /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
150 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
151 /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
152 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
153 /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
154 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
155 /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
156 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
157 /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
158 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
159 /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
160 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
161 /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
162 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
163 /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
164 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
165 /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
166 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
167 /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
168 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
169 /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
170 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
171 /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
172 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
173 /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
174 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
175 /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
176 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
177 /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
178 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
179 /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
180 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
181 /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
182 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
183 /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
184 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
185 /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
186 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
187 /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
188 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
189 /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
190 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
191 /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
192 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
193 /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
194 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
195 /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
196 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
197 /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
198 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
199 /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
200 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
201 /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
202 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
203 /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
204 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
205 /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
206 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
207 /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
208 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
209 /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
210 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
211 /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
212 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
213 /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
214 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
215 /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
216 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
217 /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
218 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
219 /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
220 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
221 /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
222 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
223 /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
224 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
225 /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
226 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
227 /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
228 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
229 /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
230 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
231 /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
232 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
233 /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
234 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
235 /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
236 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
237 /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
238 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
239 /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
240 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
241 /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
242 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
243 /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
244 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
245 /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
246 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
247 /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
248 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
249 /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
250 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
251 /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
252 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
253 /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
254 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
255 /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
256 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
257 /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
258 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
259 /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
260 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
261 /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
262 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
263 /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
264 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
265 /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
266 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
267 /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
268 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
269 /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
270 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
271 /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
272 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
273 /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
274 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
275 /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
276 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
277 /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
278 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
279 /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
280 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
281 /* #3.1-2, command header bytes for merged 'Write - value' command */
282 0xCC, 0x00, 0x14, 0x04,
283 /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
284 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
285 /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
286 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
287 /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
288 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
289 /* #5.1-2, command header bytes for merged 'Write - value' command */
290 0xCC, 0x00, 0x14, 0x04,
291 /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
292 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
293 /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
294 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
295 /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
296 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
297 /* #7.1-3, command header bytes for merged 'Write - value' command */
298 0xCC, 0x00, 0x1C, 0x04,
299 /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
300 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
301 /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
302 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
303 /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
304 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
305 /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
306 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
307 /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
308 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
309 };
310/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
311
312#else
313const uint8_t dcd_data[] = {0x00};
314#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
315#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.h
new file mode 100644
index 000000000..185b0ecd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/dcd.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef __DCD__
14#define __DCD__
15
16#include <stdint.h>
17
18/*! @name Driver version */
19/*@{*/
20/*! @brief XIP_BOARD driver version 2.0.1. */
21#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22/*@}*/
23
24/*************************************
25 * DCD Data
26 *************************************/
27#define DCD_TAG_HEADER (0xD2)
28#define DCD_VERSION (0x41)
29#define DCD_TAG_HEADER_SHIFT (24)
30#define DCD_ARRAY_SIZE 1
31
32#endif /* __DCD__ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.c
new file mode 100644
index 000000000..0c977a5e3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v8.0
17processor: MIMXRT1064xxxxA
18package_id: MIMXRT1064DVL6A
19mcu_data: ksdk2_0
20processor_version: 0.8.2
21board: MIMXRT1064-EVK
22functionalGroups:
23- name: BOARD_InitPeripherals
24 UUID: 1c6563a6-c68b-40e5-8828-2853c99f95fa
25 called_from_default_init: true
26 id_prefix: BOARD_
27 selectedCore: core0
28 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
29/* clang-format on */
30
31/***********************************************************************************************************************
32 * Included files
33 **********************************************************************************************************************/
34#include "peripherals.h"
35
36/***********************************************************************************************************************
37 * Initialization functions
38 **********************************************************************************************************************/
39void BOARD_InitPeripherals(void)
40{
41}
42
43/***********************************************************************************************************************
44 * BOARD_InitBootPeripherals function
45 **********************************************************************************************************************/
46void BOARD_InitBootPeripherals(void)
47{
48 BOARD_InitPeripherals();
49}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.h
new file mode 100644
index 000000000..3dd597994
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.c
new file mode 100644
index 000000000..206b5e1e3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.c
@@ -0,0 +1,1094 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v4.1
17processor: MIMXRT1064xxxxA
18package_id: MIMXRT1064DVL6A
19mcu_data: ksdk2_0
20processor_version: 0.0.0
21board: MIMXRT1064-EVK
22pin_labels:
23- {pin_num: E3, pin_signal: GPIO_EMC_00, label: SEMC_D0, identifier: SEMC_D0}
24- {pin_num: F3, pin_signal: GPIO_EMC_01, label: SEMC_D1, identifier: SEMC_D1}
25- {pin_num: F4, pin_signal: GPIO_EMC_02, label: SEMC_D2, identifier: SEMC_D2}
26- {pin_num: F2, pin_signal: GPIO_EMC_04, label: SEMC_D4, identifier: SEMC_D4}
27- {pin_num: G4, pin_signal: GPIO_EMC_03, label: SEMC_D3, identifier: SEMC_D3}
28- {pin_num: G5, pin_signal: GPIO_EMC_05, label: SEMC_D5, identifier: SEMC_D5}
29- {pin_num: H5, pin_signal: GPIO_EMC_06, label: SEMC_D6, identifier: SEMC_D6}
30- {pin_num: H4, pin_signal: GPIO_EMC_07, label: SEMC_D7, identifier: SEMC_D7}
31- {pin_num: H3, pin_signal: GPIO_EMC_08, label: SEMC_DM0, identifier: SEMC_DM0}
32- {pin_num: C2, pin_signal: GPIO_EMC_09, label: SEMC_A0, identifier: SEMC_A0}
33- {pin_num: G1, pin_signal: GPIO_EMC_10, label: SEMC_A1, identifier: SEMC_A1}
34- {pin_num: G3, pin_signal: GPIO_EMC_11, label: SEMC_A2, identifier: SEMC_A2}
35- {pin_num: H1, pin_signal: GPIO_EMC_12, label: SEMC_A3, identifier: SEMC_A3}
36- {pin_num: A6, pin_signal: GPIO_EMC_13, label: SEMC_A4, identifier: SEMC_A4}
37- {pin_num: B6, pin_signal: GPIO_EMC_14, label: SEMC_A5, identifier: SEMC_A5}
38- {pin_num: B1, pin_signal: GPIO_EMC_15, label: SEMC_A6, identifier: SEMC_A6}
39- {pin_num: A5, pin_signal: GPIO_EMC_16, label: SEMC_A7, identifier: SEMC_A7}
40- {pin_num: A4, pin_signal: GPIO_EMC_17, label: SEMC_A8, identifier: SEMC_A8}
41- {pin_num: B2, pin_signal: GPIO_EMC_18, label: SEMC_A9, identifier: SEMC_A9}
42- {pin_num: B4, pin_signal: GPIO_EMC_19, label: SEMC_A11, identifier: SEMC_A11}
43- {pin_num: G2, pin_signal: GPIO_EMC_23, label: SEMC_A10, identifier: SEMC_A10}
44- {pin_num: A3, pin_signal: GPIO_EMC_20, label: SEMC_A12, identifier: SEMC_A12}
45- {pin_num: C1, pin_signal: GPIO_EMC_21, label: SEMC_BA0, identifier: SEMC_BA0}
46- {pin_num: F1, pin_signal: GPIO_EMC_22, label: SEMC_BA1, identifier: SEMC_BA1}
47- {pin_num: D3, pin_signal: GPIO_EMC_24, label: SEMC_CAS, identifier: SEMC_CAS}
48- {pin_num: D2, pin_signal: GPIO_EMC_25, label: SEMC_RAS, identifier: SEMC_RAS}
49- {pin_num: B3, pin_signal: GPIO_EMC_26, label: SEMC_CLK, identifier: SEMC_CLK}
50- {pin_num: A2, pin_signal: GPIO_EMC_27, label: SEMC_CKE, identifier: SEMC_CKE}
51- {pin_num: D1, pin_signal: GPIO_EMC_28, label: SEMC_WE, identifier: SEMC_WE}
52- {pin_num: E1, pin_signal: GPIO_EMC_29, label: SEMC_CS0, identifier: SEMC_CS0}
53- {pin_num: C6, pin_signal: GPIO_EMC_30, label: SEMC_D8, identifier: SEMC_D8}
54- {pin_num: C5, pin_signal: GPIO_EMC_31, label: SEMC_D9, identifier: SEMC_D9}
55- {pin_num: D5, pin_signal: GPIO_EMC_32, label: SEMC_D10, identifier: SEMC_D10}
56- {pin_num: C4, pin_signal: GPIO_EMC_33, label: SEMC_D11, identifier: SEMC_D11}
57- {pin_num: D4, pin_signal: GPIO_EMC_34, label: SEMC_D12, identifier: SEMC_D12}
58- {pin_num: E5, pin_signal: GPIO_EMC_35, label: SEMC_D13, identifier: SEMC_D13}
59- {pin_num: C3, pin_signal: GPIO_EMC_36, label: SEMC_D14, identifier: SEMC_D14}
60- {pin_num: E4, pin_signal: GPIO_EMC_37, label: SEMC_D15, identifier: SEMC_D15}
61- {pin_num: D6, pin_signal: GPIO_EMC_38, label: SEMC_DM1, identifier: SEMC_DM1}
62- {pin_num: B7, pin_signal: GPIO_EMC_39, label: SEMC_DQS, identifier: SEMC_DQS}
63- {pin_num: A7, pin_signal: GPIO_EMC_40, label: ENET_MDC, identifier: ENET_MDC}
64- {pin_num: C7, pin_signal: GPIO_EMC_41, label: ENET_MDIO, identifier: ENET_MDIO}
65- {pin_num: D7, pin_signal: GPIO_B0_00, label: LCDIF_CLK, identifier: LCDIF_CLK}
66- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: LCDIF_ENABLE}
67- {pin_num: E8, pin_signal: GPIO_B0_02, label: LCDIF_HSYNC, identifier: LCDIF_HSYNC}
68- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: LCDIF_VSYNC}
69- {pin_num: C8, pin_signal: GPIO_B0_04, label: 'LCDIF_D0/BT_CFG[0]', identifier: LCDIF_D0}
70- {pin_num: B8, pin_signal: GPIO_B0_05, label: 'LCDIF_D1/BT_CFG[1]', identifier: LCDIF_D1}
71- {pin_num: A8, pin_signal: GPIO_B0_06, label: 'LCDIF_D2/BT_CFG[2]', identifier: LCDIF_D2}
72- {pin_num: A9, pin_signal: GPIO_B0_07, label: 'LCDIF_D3/BT_CFG[3]', identifier: LCDIF_D3}
73- {pin_num: B9, pin_signal: GPIO_B0_08, label: 'LCDIF_D4/BT_CFG[4]', identifier: LCDIF_D4}
74- {pin_num: C9, pin_signal: GPIO_B0_09, label: 'LCDIF_D5/BT_CFG[5]', identifier: LCDIF_D5}
75- {pin_num: D9, pin_signal: GPIO_B0_10, label: 'LCDIF_D6/BT_CFG[6]', identifier: LCDIF_D6}
76- {pin_num: A10, pin_signal: GPIO_B0_11, label: 'LCDIF_D7/BT_CFG[7]', identifier: LCDIF_D7}
77- {pin_num: C10, pin_signal: GPIO_B0_12, label: 'LCDIF_D8/BT_CFG[8]', identifier: LCDIF_D8}
78- {pin_num: D10, pin_signal: GPIO_B0_13, label: 'LCDIF_D9/BT_CFG[9]', identifier: LCDIF_D9}
79- {pin_num: E10, pin_signal: GPIO_B0_14, label: 'LCDIF_D10/BT_CFG[10]', identifier: LCDIF_D10}
80- {pin_num: E11, pin_signal: GPIO_B0_15, label: 'LCDIF_D11/BT_CFG[11]', identifier: LCDIF_D11}
81- {pin_num: A11, pin_signal: GPIO_B1_00, label: LCDIF_D12, identifier: LCDIF_D12}
82- {pin_num: B11, pin_signal: GPIO_B1_01, label: LCDIF_D13, identifier: LCDIF_D13}
83- {pin_num: C11, pin_signal: GPIO_B1_02, label: LCDIF_D14, identifier: LCDIF_D14}
84- {pin_num: D11, pin_signal: GPIO_B1_03, label: LCDIF_D15, identifier: LCDIF_D15}
85- {pin_num: E12, pin_signal: GPIO_B1_04, label: ENET_RXD0, identifier: ENET_RXD0}
86- {pin_num: D12, pin_signal: GPIO_B1_05, label: ENET_RXD1, identifier: ENET_RXD1}
87- {pin_num: C12, pin_signal: GPIO_B1_06, label: ENET_CRS_DV, identifier: ENET_CRS_DV}
88- {pin_num: B12, pin_signal: GPIO_B1_07, label: ENET_TXD0, identifier: ENET_TXD0}
89- {pin_num: A12, pin_signal: GPIO_B1_08, label: ENET_TXD1, identifier: ENET_TXD1}
90- {pin_num: A13, pin_signal: GPIO_B1_09, label: ENET_TXEN, identifier: ENET_TXEN}
91- {pin_num: B13, pin_signal: GPIO_B1_10, label: ENET_TX_CLK, identifier: ENET_TX_CLK}
92- {pin_num: C13, pin_signal: GPIO_B1_11, label: ENET_RXER, identifier: ENET_RXER}
93- {pin_num: D13, pin_signal: GPIO_B1_12, label: SD_CD_SW, identifier: SD_CD_SW}
94- {pin_num: D14, pin_signal: GPIO_B1_13, label: WDOG_B, identifier: WDOG_B}
95- {pin_num: C14, pin_signal: GPIO_B1_14, label: SD0_VSELECT, identifier: SD0_VSELECT}
96- {pin_num: B14, pin_signal: GPIO_B1_15, label: USB_HOST_PWR/BACKLIGHT_CTL, identifier: BACKLIGHT_CTL}
97- {pin_num: E9, pin_signal: NVCC_GPIO0, label: DCDC_3V3/NVCC_GPIO_3V3}
98- {pin_num: F10, pin_signal: NVCC_GPIO1, label: DCDC_3V3/NVCC_GPIO_3V3}
99- {pin_num: J10, pin_signal: NVCC_GPIO2, label: DCDC_3V3/NVCC_GPIO_3V3}
100- {pin_num: M14, pin_signal: GPIO_AD_B0_00, label: 'USB_HOST_OC/J24[10]'}
101- {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: 'USB_OTG1_ID/J24[9]'}
102- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: 'USB_OTG1_PWR/J24[2]'}
103- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: 'USB_OTG1_OC/J24[1]'}
104- {pin_num: F11, pin_signal: GPIO_AD_B0_04, label: 'CSI_PWDN/J35[17]/BOOT_MODE[0]', identifier: CSI_PWDN}
105- {pin_num: G14, pin_signal: GPIO_AD_B0_05, label: 'CAN_STBY/BOOT_MODE[1]/Flash_RST/U12[8]', identifier: CAN_STBY}
106- {pin_num: E14, pin_signal: GPIO_AD_B0_06, label: 'JTAG_TMS/J21[7]/SWD_DIO'}
107- {pin_num: F12, pin_signal: GPIO_AD_B0_07, label: 'JTAG_TCK/J21[9]/SWD_CLK'}
108- {pin_num: F13, pin_signal: GPIO_AD_B0_08, label: JTAG_MOD}
109- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]'}
110- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: 'JTAG_TDO/J21[13]/INT1_COMBO/ENET_INT/J22[6]/U32[11]', identifier: INT1_COMBO}
111- {pin_num: G10, pin_signal: GPIO_AD_B0_11, label: 'JTAG_nTRST/J21[3]/INT2_COMBO/LCD_TOUCH_INT/J22[3]/U32[9]', identifier: INT2_COMBO}
112- {pin_num: K14, pin_signal: GPIO_AD_B0_12, label: UART1_TXD, identifier: UART1_TXD}
113- {pin_num: L14, pin_signal: GPIO_AD_B0_13, label: UART1_RXD, identifier: UART1_RXD}
114- {pin_num: H14, pin_signal: GPIO_AD_B0_14, label: 'CAN2_TX/U12[1]', identifier: CAN2_TX}
115- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: 'CAN2_RX/U12[4]', identifier: CAN2_RX}
116- {pin_num: J11, pin_signal: GPIO_AD_B1_00, label: 'I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4]', identifier: I2C_SCL_FXOS8700CQ;CSI_I2C_SCL}
117- {pin_num: K11, pin_signal: GPIO_AD_B1_01, label: 'I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6]', identifier: I2C_SDA_FXOS8700CQ;CSI_I2C_SDA}
118- {pin_num: L11, pin_signal: GPIO_AD_B1_02, label: 'SPDIF_OUT/J22[7]', identifier: SPDIF_OUT}
119- {pin_num: M12, pin_signal: GPIO_AD_B1_03, label: 'SPDIF_IN/J22[8]', identifier: SPDIF_IN}
120- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: 'AUD_INT/CSI_D9//J35[13]/J22[4]', identifier: CSI_D9}
121- {pin_num: M13, pin_signal: GPIO_AD_B1_09, label: 'SAI1_MCLK/CSI_D8/J35[11]', identifier: CSI_D8}
122- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: 'SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1]', identifier: CSI_D7}
123- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: 'SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2]', identifier: CSI_D6}
124- {pin_num: H12, pin_signal: GPIO_AD_B1_12, label: 'SAI1_RXD/CSI_D5/J35[5]/U13[16]', identifier: CSI_D5}
125- {pin_num: H11, pin_signal: GPIO_AD_B1_13, label: 'SAI1_TXD/CSI_D4/J35[3]/U13[14]', identifier: CSI_D4}
126- {pin_num: G12, pin_signal: GPIO_AD_B1_14, label: 'SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12]', identifier: CSI_D3}
127- {pin_num: J14, pin_signal: GPIO_AD_B1_15, label: 'SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13]', identifier: CSI_D2}
128- {pin_num: J4, pin_signal: GPIO_SD_B0_00, label: 'SD1_CMD/J24[6]', identifier: SD1_CMD}
129- {pin_num: J3, pin_signal: GPIO_SD_B0_01, label: 'SD1_CLK/J24[3]', identifier: SD1_CLK}
130- {pin_num: J1, pin_signal: GPIO_SD_B0_02, label: 'SD1_D0/J24[4]/SPI_MOSI/PWM', identifier: SD1_D0}
131- {pin_num: K1, pin_signal: GPIO_SD_B0_03, label: 'SD1_D1/J24[5]/SPI_MISO', identifier: SD1_D1}
132- {pin_num: H2, pin_signal: GPIO_SD_B0_04, label: SD1_D2, identifier: SD1_D2}
133- {pin_num: J2, pin_signal: GPIO_SD_B0_05, label: SD1_D3, identifier: SD1_D3}
134- {pin_num: L5, pin_signal: GPIO_SD_B1_00, label: FlexSPI_D3_B, identifier: FlexSPI_D3_B}
135- {pin_num: M5, pin_signal: GPIO_SD_B1_01, label: FlexSPI_D2_B, identifier: FlexSPI_D2_B}
136- {pin_num: M3, pin_signal: GPIO_SD_B1_02, label: FlexSPI_D1_B, identifier: FlexSPI_D1_B}
137- {pin_num: M4, pin_signal: GPIO_SD_B1_03, label: FlexSPI_D0_B, identifier: FlexSPI_D0_B}
138- {pin_num: P2, pin_signal: GPIO_SD_B1_04, label: FlexSPI_CLK_B, identifier: FlexSPI_CLK_B}
139- {pin_num: N3, pin_signal: GPIO_SD_B1_05, label: FlexSPI_DQS, identifier: FlexSPI_DQS}
140- {pin_num: L3, pin_signal: GPIO_SD_B1_06, label: FlexSPI_SS0, identifier: FlexSPI_SS0}
141- {pin_num: L4, pin_signal: GPIO_SD_B1_07, label: FlexSPI_CLK, identifier: FlexSPI_CLK}
142- {pin_num: P3, pin_signal: GPIO_SD_B1_08, label: FlexSPI_D0_A, identifier: FlexSPI_D0_A}
143- {pin_num: N4, pin_signal: GPIO_SD_B1_09, label: FlexSPI_D1_A, identifier: FlexSPI_D1_A}
144- {pin_num: P4, pin_signal: GPIO_SD_B1_10, label: FlexSPI_D2_A, identifier: FlexSPI_D2_A}
145- {pin_num: P5, pin_signal: GPIO_SD_B1_11, label: FlexSPI_D3_A, identifier: FlexSPI_D3_A}
146- {pin_num: M8, pin_signal: USB_OTG1_DN, label: OTG1_DN, identifier: OTG1_DN}
147- {pin_num: L8, pin_signal: USB_OTG1_DP, label: OTG1_DP, identifier: OTG1_DP}
148- {pin_num: N7, pin_signal: USB_OTG2_DN, label: OTG2_DN, identifier: OTG2_DN}
149- {pin_num: P7, pin_signal: USB_OTG2_DP, label: OTG2_DP, identifier: OTG2_DP}
150- {pin_num: K8, pin_signal: VDD_USB_CAP, label: VDD_USB_3V}
151- {pin_num: N6, pin_signal: USB_OTG1_VBUS, label: 5V_USB_OTG}
152- {pin_num: P6, pin_signal: USB_OTG2_VBUS, label: 5V_USB_HS}
153- {pin_num: L12, pin_signal: GPIO_AD_B1_04, label: 'CSI_PIXCLK/J35[8]/J23[3]', identifier: CSI_PIXCLK}
154- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: 'CSI_MCLK/J35[12]/J23[4]', identifier: CSI_MCLK}
155- {pin_num: J12, pin_signal: GPIO_AD_B1_06, label: 'CSI_VSYNC/J35[18]/J22[2]/UART_TX', identifier: CSI_VSYNC}
156- {pin_num: K10, pin_signal: GPIO_AD_B1_07, label: 'CSI_HSYNC/J35[16]/J22[1]/UART_RX', identifier: CSI_HSYNC}
157- {pin_num: M7, pin_signal: POR_B, label: 'RST_TGTMCU_B/POR_B/J21[15]', identifier: RST_TGTMCU_B;POR_B}
158- {pin_num: N14, pin_signal: VDDA_ADC_3P3, label: VDDA_ADC_3P3_MCU}
159- {pin_num: P12, pin_signal: VDD_HIGH_IN, label: VDD_HIGH_IN_MCU}
160- {pin_num: M9, pin_signal: VDD_SNVS_IN, label: VDD_SNVS_IN}
161- {pin_num: F6, pin_signal: VDD_SOC_IN0, label: VDD_SOC_IN}
162- {pin_num: H6, pin_signal: VDD_SOC_IN2, label: VDD_SOC_IN}
163- {pin_num: G6, pin_signal: VDD_SOC_IN1, label: VDD_SOC_IN}
164- {pin_num: F7, pin_signal: VDD_SOC_IN3, label: VDD_SOC_IN}
165- {pin_num: F8, pin_signal: VDD_SOC_IN4, label: VDD_SOC_IN}
166- {pin_num: F9, pin_signal: VDD_SOC_IN5, label: VDD_SOC_IN}
167- {pin_num: G9, pin_signal: VDD_SOC_IN6, label: VDD_SOC_IN}
168- {pin_num: H9, pin_signal: VDD_SOC_IN7, label: VDD_SOC_IN}
169- {pin_num: J9, pin_signal: VDD_SOC_IN8, label: VDD_SOC_IN}
170- {pin_num: P1, pin_signal: VSS1, label: GND}
171- {pin_num: E2, pin_signal: VSS2, label: GND}
172- {pin_num: K2, pin_signal: VSS3, label: GND}
173- {pin_num: B5, pin_signal: VSS4, label: GND}
174- {pin_num: N5, pin_signal: VSS5, label: GND}
175- {pin_num: G7, pin_signal: VSS6, label: GND}
176- {pin_num: H7, pin_signal: VSS7, label: GND}
177- {pin_num: J7, pin_signal: VSS8, label: GND}
178- {pin_num: G8, pin_signal: VSS9, label: GND}
179- {pin_num: H8, pin_signal: VSS10, label: GND}
180- {pin_num: J8, pin_signal: VSS11, label: GND}
181- {pin_num: N8, pin_signal: VSS12, label: GND}
182- {pin_num: L9, pin_signal: VSS13, label: GND}
183- {pin_num: B10, pin_signal: VSS14, label: GND}
184- {pin_num: E13, pin_signal: VSS15, label: GND}
185- {pin_num: K13, pin_signal: VSS16, label: GND}
186- {pin_num: A14, pin_signal: VSS17, label: GND}
187- {pin_num: P14, pin_signal: VSS18, label: GND}
188- {pin_num: A1, pin_signal: VSS0, label: GND}
189- {pin_num: J6, pin_signal: NVCC_SD0, label: NVCC_SD, identifier: NVCC_SD}
190- {pin_num: K5, pin_signal: NVCC_SD1, label: FLASH_VCC, identifier: FLASH_VCC}
191- {pin_num: F5, pin_signal: NVCC_EMC0, label: DCDC_3V3}
192- {pin_num: E6, pin_signal: NVCC_EMC1, label: DCDC_3V3}
193- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: SD_PWREN}
194- {pin_num: L1, pin_signal: DCDC_IN0, label: MCU_DCDC_IN_3V3}
195- {pin_num: L2, pin_signal: DCDC_IN1, label: MCU_DCDC_IN_3V3}
196- {pin_num: K4, pin_signal: DCDC_IN_Q, label: MCU_DCDC_IN_3V3}
197- {pin_num: M1, pin_signal: DCDC_LP0, label: VDD_SOC_IN}
198- {pin_num: M2, pin_signal: DCDC_LP1, label: VDD_SOC_IN}
199- {pin_num: P11, pin_signal: XTALI, label: XTALI, identifier: XTALI}
200- {pin_num: N11, pin_signal: XTALO, label: XTALO, identifier: XTALO}
201- {pin_num: N9, pin_signal: RTC_XTALI, label: RTC_XTALI, identifier: RTC_XTALI}
202- {pin_num: P9, pin_signal: RTC_XTALO, label: RTC_XTALO, identifier: RTC_XTALO}
203- {pin_num: N1, pin_signal: DCDC_GND0, label: GND}
204- {pin_num: N2, pin_signal: DCDC_GND1, label: GND}
205- {pin_num: J5, pin_signal: DCDC_SENSE, label: VDD_SOC_IN}
206- {pin_num: K3, pin_signal: DCDC_PSWITCH, label: MCU_DCDC_IN_3V3}
207- {pin_num: K7, pin_signal: PMIC_ON_REQ, label: PMIC_ON_REQ, identifier: PMIC_ON_REQ}
208- {pin_num: L7, pin_signal: PMIC_STBY_REQ, label: PERI_PWREN, identifier: PERI_PWREN}
209- {pin_num: M6, pin_signal: ONOFF, label: ONOFF, identifier: ONOFF}
210- {pin_num: K6, pin_signal: TEST_MODE, label: GND}
211- {pin_num: P10, pin_signal: NVCC_PLL, label: VDDA_1P1_CAP}
212- {pin_num: P8, pin_signal: VDD_HIGH_CAP, label: VDDA_2P5_CAP}
213- {pin_num: K9, pin_signal: NGND_KEL0, label: GND}
214- {pin_num: M10, pin_signal: VDD_SNVS_CAP, label: GND}
215 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
216 */
217
218#include "fsl_common.h"
219#include "fsl_iomuxc.h"
220#include "pin_mux.h"
221
222/* FUNCTION ************************************************************************************************************
223 *
224 * Function Name : BOARD_InitBootPins
225 * Description : Calls initialization functions.
226 *
227 * END ****************************************************************************************************************/
228void BOARD_InitBootPins(void) {
229 BOARD_InitPins();
230 BOARD_InitDEBUG_UART();
231}
232
233/*
234 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
235BOARD_InitPins:
236- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
237- pin_list: []
238 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
239 */
240
241/* FUNCTION ************************************************************************************************************
242 *
243 * Function Name : BOARD_InitPins
244 * Description : Configures pin routing and optionally pin electrical features.
245 *
246 * END ****************************************************************************************************************/
247void BOARD_InitPins(void) {
248}
249
250
251/*
252 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
253BOARD_InitDEBUG_UART:
254- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
255- pin_list:
256 - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
257 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
258 - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
259 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
260 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
261 */
262
263/* FUNCTION ************************************************************************************************************
264 *
265 * Function Name : BOARD_InitDEBUG_UART
266 * Description : Configures pin routing and optionally pin electrical features.
267 *
268 * END ****************************************************************************************************************/
269void BOARD_InitDEBUG_UART(void) {
270 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
271
272 IOMUXC_SetPinMux(
273 IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
274 0U); /* Software Input On Field: Input Path is determined by functionality */
275 IOMUXC_SetPinMux(
276 IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
277 0U); /* Software Input On Field: Input Path is determined by functionality */
278 IOMUXC_SetPinConfig(
279 IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
280 0x10B0u); /* Slew Rate Field: Slow Slew Rate
281 Drive Strength Field: R0/6
282 Speed Field: medium(100MHz)
283 Open Drain Enable Field: Open Drain Disabled
284 Pull / Keep Enable Field: Pull/Keeper Enabled
285 Pull / Keep Select Field: Keeper
286 Pull Up / Down Config. Field: 100K Ohm Pull Down
287 Hyst. Enable Field: Hysteresis Disabled */
288 IOMUXC_SetPinConfig(
289 IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
290 0x10B0u); /* Slew Rate Field: Slow Slew Rate
291 Drive Strength Field: R0/6
292 Speed Field: medium(100MHz)
293 Open Drain Enable Field: Open Drain Disabled
294 Pull / Keep Enable Field: Pull/Keeper Enabled
295 Pull / Keep Select Field: Keeper
296 Pull Up / Down Config. Field: 100K Ohm Pull Down
297 Hyst. Enable Field: Hysteresis Disabled */
298}
299
300
301/*
302 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
303BOARD_InitSDRAM:
304- options: {coreID: core0, enableClock: 'true'}
305- pin_list:
306 - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
307 - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
308 - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
309 - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
310 - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
311 - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
312 - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
313 - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
314 - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
315 - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
316 - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
317 - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
318 - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
319 - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
320 - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
321 - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
322 - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
323 - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
324 - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
325 - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
326 - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
327 - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
328 - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
329 - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
330 - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
331 - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
332 - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
333 - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
334 - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
335 - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
336 - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
337 - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
338 - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
339 - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
340 - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
341 - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
342 - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
343 - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
344 - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
345 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
346 */
347
348/* FUNCTION ************************************************************************************************************
349 *
350 * Function Name : BOARD_InitSDRAM
351 * Description : Configures pin routing and optionally pin electrical features.
352 *
353 * END ****************************************************************************************************************/
354void BOARD_InitSDRAM(void) {
355 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
356
357 IOMUXC_SetPinMux(
358 IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
359 0U); /* Software Input On Field: Input Path is determined by functionality */
360 IOMUXC_SetPinMux(
361 IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
362 0U); /* Software Input On Field: Input Path is determined by functionality */
363 IOMUXC_SetPinMux(
364 IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
365 0U); /* Software Input On Field: Input Path is determined by functionality */
366 IOMUXC_SetPinMux(
367 IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
368 0U); /* Software Input On Field: Input Path is determined by functionality */
369 IOMUXC_SetPinMux(
370 IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
371 0U); /* Software Input On Field: Input Path is determined by functionality */
372 IOMUXC_SetPinMux(
373 IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
374 0U); /* Software Input On Field: Input Path is determined by functionality */
375 IOMUXC_SetPinMux(
376 IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
377 0U); /* Software Input On Field: Input Path is determined by functionality */
378 IOMUXC_SetPinMux(
379 IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
380 0U); /* Software Input On Field: Input Path is determined by functionality */
381 IOMUXC_SetPinMux(
382 IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
383 0U); /* Software Input On Field: Input Path is determined by functionality */
384 IOMUXC_SetPinMux(
385 IOMUXC_GPIO_EMC_09_SEMC_ADDR00, /* GPIO_EMC_09 is configured as SEMC_ADDR00 */
386 0U); /* Software Input On Field: Input Path is determined by functionality */
387 IOMUXC_SetPinMux(
388 IOMUXC_GPIO_EMC_10_SEMC_ADDR01, /* GPIO_EMC_10 is configured as SEMC_ADDR01 */
389 0U); /* Software Input On Field: Input Path is determined by functionality */
390 IOMUXC_SetPinMux(
391 IOMUXC_GPIO_EMC_11_SEMC_ADDR02, /* GPIO_EMC_11 is configured as SEMC_ADDR02 */
392 0U); /* Software Input On Field: Input Path is determined by functionality */
393 IOMUXC_SetPinMux(
394 IOMUXC_GPIO_EMC_12_SEMC_ADDR03, /* GPIO_EMC_12 is configured as SEMC_ADDR03 */
395 0U); /* Software Input On Field: Input Path is determined by functionality */
396 IOMUXC_SetPinMux(
397 IOMUXC_GPIO_EMC_13_SEMC_ADDR04, /* GPIO_EMC_13 is configured as SEMC_ADDR04 */
398 0U); /* Software Input On Field: Input Path is determined by functionality */
399 IOMUXC_SetPinMux(
400 IOMUXC_GPIO_EMC_14_SEMC_ADDR05, /* GPIO_EMC_14 is configured as SEMC_ADDR05 */
401 0U); /* Software Input On Field: Input Path is determined by functionality */
402 IOMUXC_SetPinMux(
403 IOMUXC_GPIO_EMC_15_SEMC_ADDR06, /* GPIO_EMC_15 is configured as SEMC_ADDR06 */
404 0U); /* Software Input On Field: Input Path is determined by functionality */
405 IOMUXC_SetPinMux(
406 IOMUXC_GPIO_EMC_16_SEMC_ADDR07, /* GPIO_EMC_16 is configured as SEMC_ADDR07 */
407 0U); /* Software Input On Field: Input Path is determined by functionality */
408 IOMUXC_SetPinMux(
409 IOMUXC_GPIO_EMC_17_SEMC_ADDR08, /* GPIO_EMC_17 is configured as SEMC_ADDR08 */
410 0U); /* Software Input On Field: Input Path is determined by functionality */
411 IOMUXC_SetPinMux(
412 IOMUXC_GPIO_EMC_18_SEMC_ADDR09, /* GPIO_EMC_18 is configured as SEMC_ADDR09 */
413 0U); /* Software Input On Field: Input Path is determined by functionality */
414 IOMUXC_SetPinMux(
415 IOMUXC_GPIO_EMC_19_SEMC_ADDR11, /* GPIO_EMC_19 is configured as SEMC_ADDR11 */
416 0U); /* Software Input On Field: Input Path is determined by functionality */
417 IOMUXC_SetPinMux(
418 IOMUXC_GPIO_EMC_20_SEMC_ADDR12, /* GPIO_EMC_20 is configured as SEMC_ADDR12 */
419 0U); /* Software Input On Field: Input Path is determined by functionality */
420 IOMUXC_SetPinMux(
421 IOMUXC_GPIO_EMC_21_SEMC_BA0, /* GPIO_EMC_21 is configured as SEMC_BA0 */
422 0U); /* Software Input On Field: Input Path is determined by functionality */
423 IOMUXC_SetPinMux(
424 IOMUXC_GPIO_EMC_22_SEMC_BA1, /* GPIO_EMC_22 is configured as SEMC_BA1 */
425 0U); /* Software Input On Field: Input Path is determined by functionality */
426 IOMUXC_SetPinMux(
427 IOMUXC_GPIO_EMC_23_SEMC_ADDR10, /* GPIO_EMC_23 is configured as SEMC_ADDR10 */
428 0U); /* Software Input On Field: Input Path is determined by functionality */
429 IOMUXC_SetPinMux(
430 IOMUXC_GPIO_EMC_24_SEMC_CAS, /* GPIO_EMC_24 is configured as SEMC_CAS */
431 0U); /* Software Input On Field: Input Path is determined by functionality */
432 IOMUXC_SetPinMux(
433 IOMUXC_GPIO_EMC_25_SEMC_RAS, /* GPIO_EMC_25 is configured as SEMC_RAS */
434 0U); /* Software Input On Field: Input Path is determined by functionality */
435 IOMUXC_SetPinMux(
436 IOMUXC_GPIO_EMC_26_SEMC_CLK, /* GPIO_EMC_26 is configured as SEMC_CLK */
437 0U); /* Software Input On Field: Input Path is determined by functionality */
438 IOMUXC_SetPinMux(
439 IOMUXC_GPIO_EMC_27_SEMC_CKE, /* GPIO_EMC_27 is configured as SEMC_CKE */
440 0U); /* Software Input On Field: Input Path is determined by functionality */
441 IOMUXC_SetPinMux(
442 IOMUXC_GPIO_EMC_28_SEMC_WE, /* GPIO_EMC_28 is configured as SEMC_WE */
443 0U); /* Software Input On Field: Input Path is determined by functionality */
444 IOMUXC_SetPinMux(
445 IOMUXC_GPIO_EMC_30_SEMC_DATA08, /* GPIO_EMC_30 is configured as SEMC_DATA08 */
446 0U); /* Software Input On Field: Input Path is determined by functionality */
447 IOMUXC_SetPinMux(
448 IOMUXC_GPIO_EMC_31_SEMC_DATA09, /* GPIO_EMC_31 is configured as SEMC_DATA09 */
449 0U); /* Software Input On Field: Input Path is determined by functionality */
450 IOMUXC_SetPinMux(
451 IOMUXC_GPIO_EMC_32_SEMC_DATA10, /* GPIO_EMC_32 is configured as SEMC_DATA10 */
452 0U); /* Software Input On Field: Input Path is determined by functionality */
453 IOMUXC_SetPinMux(
454 IOMUXC_GPIO_EMC_33_SEMC_DATA11, /* GPIO_EMC_33 is configured as SEMC_DATA11 */
455 0U); /* Software Input On Field: Input Path is determined by functionality */
456 IOMUXC_SetPinMux(
457 IOMUXC_GPIO_EMC_34_SEMC_DATA12, /* GPIO_EMC_34 is configured as SEMC_DATA12 */
458 0U); /* Software Input On Field: Input Path is determined by functionality */
459 IOMUXC_SetPinMux(
460 IOMUXC_GPIO_EMC_35_SEMC_DATA13, /* GPIO_EMC_35 is configured as SEMC_DATA13 */
461 0U); /* Software Input On Field: Input Path is determined by functionality */
462 IOMUXC_SetPinMux(
463 IOMUXC_GPIO_EMC_36_SEMC_DATA14, /* GPIO_EMC_36 is configured as SEMC_DATA14 */
464 0U); /* Software Input On Field: Input Path is determined by functionality */
465 IOMUXC_SetPinMux(
466 IOMUXC_GPIO_EMC_37_SEMC_DATA15, /* GPIO_EMC_37 is configured as SEMC_DATA15 */
467 0U); /* Software Input On Field: Input Path is determined by functionality */
468 IOMUXC_SetPinMux(
469 IOMUXC_GPIO_EMC_38_SEMC_DM01, /* GPIO_EMC_38 is configured as SEMC_DM01 */
470 0U); /* Software Input On Field: Input Path is determined by functionality */
471 IOMUXC_SetPinMux(
472 IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
473 0U); /* Software Input On Field: Input Path is determined by functionality */
474}
475
476
477/*
478 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
479BOARD_InitCSI:
480- options: {coreID: core0, enableClock: 'true'}
481- pin_list:
482 - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
483 - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
484 - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
485 - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
486 - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
487 - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
488 - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
489 - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
490 - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
491 - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
492 - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
493 - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
494 - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
495 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
496 - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
497 pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
498 - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
499 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
500 */
501
502/* FUNCTION ************************************************************************************************************
503 *
504 * Function Name : BOARD_InitCSI
505 * Description : Configures pin routing and optionally pin electrical features.
506 *
507 * END ****************************************************************************************************************/
508void BOARD_InitCSI(void) {
509 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
510
511 IOMUXC_SetPinMux(
512 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
513 0U); /* Software Input On Field: Input Path is determined by functionality */
514 IOMUXC_SetPinMux(
515 IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
516 0U); /* Software Input On Field: Input Path is determined by functionality */
517 IOMUXC_SetPinMux(
518 IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
519 0U); /* Software Input On Field: Input Path is determined by functionality */
520 IOMUXC_SetPinMux(
521 IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, /* GPIO_AD_B1_04 is configured as CSI_PIXCLK */
522 0U); /* Software Input On Field: Input Path is determined by functionality */
523 IOMUXC_SetPinMux(
524 IOMUXC_GPIO_AD_B1_05_CSI_MCLK, /* GPIO_AD_B1_05 is configured as CSI_MCLK */
525 0U); /* Software Input On Field: Input Path is determined by functionality */
526 IOMUXC_SetPinMux(
527 IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, /* GPIO_AD_B1_06 is configured as CSI_VSYNC */
528 0U); /* Software Input On Field: Input Path is determined by functionality */
529 IOMUXC_SetPinMux(
530 IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, /* GPIO_AD_B1_07 is configured as CSI_HSYNC */
531 0U); /* Software Input On Field: Input Path is determined by functionality */
532 IOMUXC_SetPinMux(
533 IOMUXC_GPIO_AD_B1_08_CSI_DATA09, /* GPIO_AD_B1_08 is configured as CSI_DATA09 */
534 0U); /* Software Input On Field: Input Path is determined by functionality */
535 IOMUXC_SetPinMux(
536 IOMUXC_GPIO_AD_B1_09_CSI_DATA08, /* GPIO_AD_B1_09 is configured as CSI_DATA08 */
537 0U); /* Software Input On Field: Input Path is determined by functionality */
538 IOMUXC_SetPinMux(
539 IOMUXC_GPIO_AD_B1_10_CSI_DATA07, /* GPIO_AD_B1_10 is configured as CSI_DATA07 */
540 0U); /* Software Input On Field: Input Path is determined by functionality */
541 IOMUXC_SetPinMux(
542 IOMUXC_GPIO_AD_B1_11_CSI_DATA06, /* GPIO_AD_B1_11 is configured as CSI_DATA06 */
543 0U); /* Software Input On Field: Input Path is determined by functionality */
544 IOMUXC_SetPinMux(
545 IOMUXC_GPIO_AD_B1_12_CSI_DATA05, /* GPIO_AD_B1_12 is configured as CSI_DATA05 */
546 0U); /* Software Input On Field: Input Path is determined by functionality */
547 IOMUXC_SetPinMux(
548 IOMUXC_GPIO_AD_B1_13_CSI_DATA04, /* GPIO_AD_B1_13 is configured as CSI_DATA04 */
549 0U); /* Software Input On Field: Input Path is determined by functionality */
550 IOMUXC_SetPinMux(
551 IOMUXC_GPIO_AD_B1_14_CSI_DATA03, /* GPIO_AD_B1_14 is configured as CSI_DATA03 */
552 0U); /* Software Input On Field: Input Path is determined by functionality */
553 IOMUXC_SetPinMux(
554 IOMUXC_GPIO_AD_B1_15_CSI_DATA02, /* GPIO_AD_B1_15 is configured as CSI_DATA02 */
555 0U); /* Software Input On Field: Input Path is determined by functionality */
556 IOMUXC_SetPinConfig(
557 IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
558 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
559 Drive Strength Field: R0/6
560 Speed Field: medium(100MHz)
561 Open Drain Enable Field: Open Drain Enabled
562 Pull / Keep Enable Field: Pull/Keeper Enabled
563 Pull / Keep Select Field: Keeper
564 Pull Up / Down Config. Field: 22K Ohm Pull Up
565 Hyst. Enable Field: Hysteresis Disabled */
566 IOMUXC_SetPinConfig(
567 IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
568 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
569 Drive Strength Field: R0/6
570 Speed Field: medium(100MHz)
571 Open Drain Enable Field: Open Drain Enabled
572 Pull / Keep Enable Field: Pull/Keeper Enabled
573 Pull / Keep Select Field: Keeper
574 Pull Up / Down Config. Field: 22K Ohm Pull Up
575 Hyst. Enable Field: Hysteresis Disabled */
576}
577
578
579/*
580 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
581BOARD_InitLCD:
582- options: {coreID: core0, enableClock: 'true'}
583- pin_list:
584 - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
585 - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
586 - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
587 - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
588 - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
589 - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
590 - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
591 - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
592 - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
593 - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
594 - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
595 - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
596 - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
597 - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
598 - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
599 - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
600 - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
601 - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
602 - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
603 - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
604 - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
605 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
606 */
607
608/* FUNCTION ************************************************************************************************************
609 *
610 * Function Name : BOARD_InitLCD
611 * Description : Configures pin routing and optionally pin electrical features.
612 *
613 * END ****************************************************************************************************************/
614void BOARD_InitLCD(void) {
615 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
616
617 IOMUXC_SetPinMux(
618 IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 is configured as LCD_CLK */
619 0U); /* Software Input On Field: Input Path is determined by functionality */
620 IOMUXC_SetPinMux(
621 IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 is configured as LCD_ENABLE */
622 0U); /* Software Input On Field: Input Path is determined by functionality */
623 IOMUXC_SetPinMux(
624 IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 is configured as LCD_HSYNC */
625 0U); /* Software Input On Field: Input Path is determined by functionality */
626 IOMUXC_SetPinMux(
627 IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 is configured as LCD_VSYNC */
628 0U); /* Software Input On Field: Input Path is determined by functionality */
629 IOMUXC_SetPinMux(
630 IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 is configured as LCD_DATA00 */
631 0U); /* Software Input On Field: Input Path is determined by functionality */
632 IOMUXC_SetPinMux(
633 IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 is configured as LCD_DATA01 */
634 0U); /* Software Input On Field: Input Path is determined by functionality */
635 IOMUXC_SetPinMux(
636 IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 is configured as LCD_DATA02 */
637 0U); /* Software Input On Field: Input Path is determined by functionality */
638 IOMUXC_SetPinMux(
639 IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 is configured as LCD_DATA03 */
640 0U); /* Software Input On Field: Input Path is determined by functionality */
641 IOMUXC_SetPinMux(
642 IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 is configured as LCD_DATA04 */
643 0U); /* Software Input On Field: Input Path is determined by functionality */
644 IOMUXC_SetPinMux(
645 IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 is configured as LCD_DATA05 */
646 0U); /* Software Input On Field: Input Path is determined by functionality */
647 IOMUXC_SetPinMux(
648 IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 is configured as LCD_DATA06 */
649 0U); /* Software Input On Field: Input Path is determined by functionality */
650 IOMUXC_SetPinMux(
651 IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 is configured as LCD_DATA07 */
652 0U); /* Software Input On Field: Input Path is determined by functionality */
653 IOMUXC_SetPinMux(
654 IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 is configured as LCD_DATA08 */
655 0U); /* Software Input On Field: Input Path is determined by functionality */
656 IOMUXC_SetPinMux(
657 IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 is configured as LCD_DATA09 */
658 0U); /* Software Input On Field: Input Path is determined by functionality */
659 IOMUXC_SetPinMux(
660 IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 is configured as LCD_DATA10 */
661 0U); /* Software Input On Field: Input Path is determined by functionality */
662 IOMUXC_SetPinMux(
663 IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 is configured as LCD_DATA11 */
664 0U); /* Software Input On Field: Input Path is determined by functionality */
665 IOMUXC_SetPinMux(
666 IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 is configured as LCD_DATA12 */
667 0U); /* Software Input On Field: Input Path is determined by functionality */
668 IOMUXC_SetPinMux(
669 IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 is configured as LCD_DATA13 */
670 0U); /* Software Input On Field: Input Path is determined by functionality */
671 IOMUXC_SetPinMux(
672 IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 is configured as LCD_DATA14 */
673 0U); /* Software Input On Field: Input Path is determined by functionality */
674 IOMUXC_SetPinMux(
675 IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 is configured as LCD_DATA15 */
676 0U); /* Software Input On Field: Input Path is determined by functionality */
677 IOMUXC_SetPinMux(
678 IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 is configured as GPIO2_IO31 */
679 0U); /* Software Input On Field: Input Path is determined by functionality */
680 IOMUXC_SetPinConfig(
681 IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 PAD functional properties : */
682 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
683 Drive Strength Field: R0/6
684 Speed Field: medium(100MHz)
685 Open Drain Enable Field: Open Drain Disabled
686 Pull / Keep Enable Field: Pull/Keeper Enabled
687 Pull / Keep Select Field: Pull
688 Pull Up / Down Config. Field: 100K Ohm Pull Up
689 Hyst. Enable Field: Hysteresis Enabled */
690 IOMUXC_SetPinConfig(
691 IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 PAD functional properties : */
692 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
693 Drive Strength Field: R0/6
694 Speed Field: medium(100MHz)
695 Open Drain Enable Field: Open Drain Disabled
696 Pull / Keep Enable Field: Pull/Keeper Enabled
697 Pull / Keep Select Field: Pull
698 Pull Up / Down Config. Field: 100K Ohm Pull Up
699 Hyst. Enable Field: Hysteresis Enabled */
700 IOMUXC_SetPinConfig(
701 IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 PAD functional properties : */
702 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
703 Drive Strength Field: R0/6
704 Speed Field: medium(100MHz)
705 Open Drain Enable Field: Open Drain Disabled
706 Pull / Keep Enable Field: Pull/Keeper Enabled
707 Pull / Keep Select Field: Pull
708 Pull Up / Down Config. Field: 100K Ohm Pull Up
709 Hyst. Enable Field: Hysteresis Enabled */
710 IOMUXC_SetPinConfig(
711 IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 PAD functional properties : */
712 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
713 Drive Strength Field: R0/6
714 Speed Field: medium(100MHz)
715 Open Drain Enable Field: Open Drain Disabled
716 Pull / Keep Enable Field: Pull/Keeper Enabled
717 Pull / Keep Select Field: Pull
718 Pull Up / Down Config. Field: 100K Ohm Pull Up
719 Hyst. Enable Field: Hysteresis Enabled */
720 IOMUXC_SetPinConfig(
721 IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 PAD functional properties : */
722 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
723 Drive Strength Field: R0/6
724 Speed Field: medium(100MHz)
725 Open Drain Enable Field: Open Drain Disabled
726 Pull / Keep Enable Field: Pull/Keeper Enabled
727 Pull / Keep Select Field: Pull
728 Pull Up / Down Config. Field: 100K Ohm Pull Up
729 Hyst. Enable Field: Hysteresis Enabled */
730 IOMUXC_SetPinConfig(
731 IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 PAD functional properties : */
732 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
733 Drive Strength Field: R0/6
734 Speed Field: medium(100MHz)
735 Open Drain Enable Field: Open Drain Disabled
736 Pull / Keep Enable Field: Pull/Keeper Enabled
737 Pull / Keep Select Field: Pull
738 Pull Up / Down Config. Field: 100K Ohm Pull Up
739 Hyst. Enable Field: Hysteresis Enabled */
740 IOMUXC_SetPinConfig(
741 IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 PAD functional properties : */
742 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
743 Drive Strength Field: R0/6
744 Speed Field: medium(100MHz)
745 Open Drain Enable Field: Open Drain Disabled
746 Pull / Keep Enable Field: Pull/Keeper Enabled
747 Pull / Keep Select Field: Pull
748 Pull Up / Down Config. Field: 100K Ohm Pull Up
749 Hyst. Enable Field: Hysteresis Enabled */
750 IOMUXC_SetPinConfig(
751 IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 PAD functional properties : */
752 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
753 Drive Strength Field: R0/6
754 Speed Field: medium(100MHz)
755 Open Drain Enable Field: Open Drain Disabled
756 Pull / Keep Enable Field: Pull/Keeper Enabled
757 Pull / Keep Select Field: Pull
758 Pull Up / Down Config. Field: 100K Ohm Pull Up
759 Hyst. Enable Field: Hysteresis Enabled */
760 IOMUXC_SetPinConfig(
761 IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 PAD functional properties : */
762 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
763 Drive Strength Field: R0/6
764 Speed Field: medium(100MHz)
765 Open Drain Enable Field: Open Drain Disabled
766 Pull / Keep Enable Field: Pull/Keeper Enabled
767 Pull / Keep Select Field: Pull
768 Pull Up / Down Config. Field: 100K Ohm Pull Up
769 Hyst. Enable Field: Hysteresis Enabled */
770 IOMUXC_SetPinConfig(
771 IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 PAD functional properties : */
772 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
773 Drive Strength Field: R0/6
774 Speed Field: medium(100MHz)
775 Open Drain Enable Field: Open Drain Disabled
776 Pull / Keep Enable Field: Pull/Keeper Enabled
777 Pull / Keep Select Field: Pull
778 Pull Up / Down Config. Field: 100K Ohm Pull Up
779 Hyst. Enable Field: Hysteresis Enabled */
780 IOMUXC_SetPinConfig(
781 IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 PAD functional properties : */
782 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
783 Drive Strength Field: R0/6
784 Speed Field: medium(100MHz)
785 Open Drain Enable Field: Open Drain Disabled
786 Pull / Keep Enable Field: Pull/Keeper Enabled
787 Pull / Keep Select Field: Pull
788 Pull Up / Down Config. Field: 100K Ohm Pull Up
789 Hyst. Enable Field: Hysteresis Enabled */
790 IOMUXC_SetPinConfig(
791 IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 PAD functional properties : */
792 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
793 Drive Strength Field: R0/6
794 Speed Field: medium(100MHz)
795 Open Drain Enable Field: Open Drain Disabled
796 Pull / Keep Enable Field: Pull/Keeper Enabled
797 Pull / Keep Select Field: Pull
798 Pull Up / Down Config. Field: 100K Ohm Pull Up
799 Hyst. Enable Field: Hysteresis Enabled */
800 IOMUXC_SetPinConfig(
801 IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 PAD functional properties : */
802 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
803 Drive Strength Field: R0/6
804 Speed Field: medium(100MHz)
805 Open Drain Enable Field: Open Drain Disabled
806 Pull / Keep Enable Field: Pull/Keeper Enabled
807 Pull / Keep Select Field: Pull
808 Pull Up / Down Config. Field: 100K Ohm Pull Up
809 Hyst. Enable Field: Hysteresis Enabled */
810 IOMUXC_SetPinConfig(
811 IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 PAD functional properties : */
812 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
813 Drive Strength Field: R0/6
814 Speed Field: medium(100MHz)
815 Open Drain Enable Field: Open Drain Disabled
816 Pull / Keep Enable Field: Pull/Keeper Enabled
817 Pull / Keep Select Field: Pull
818 Pull Up / Down Config. Field: 100K Ohm Pull Up
819 Hyst. Enable Field: Hysteresis Enabled */
820 IOMUXC_SetPinConfig(
821 IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 PAD functional properties : */
822 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
823 Drive Strength Field: R0/6
824 Speed Field: medium(100MHz)
825 Open Drain Enable Field: Open Drain Disabled
826 Pull / Keep Enable Field: Pull/Keeper Enabled
827 Pull / Keep Select Field: Pull
828 Pull Up / Down Config. Field: 100K Ohm Pull Up
829 Hyst. Enable Field: Hysteresis Enabled */
830 IOMUXC_SetPinConfig(
831 IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 PAD functional properties : */
832 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
833 Drive Strength Field: R0/6
834 Speed Field: medium(100MHz)
835 Open Drain Enable Field: Open Drain Disabled
836 Pull / Keep Enable Field: Pull/Keeper Enabled
837 Pull / Keep Select Field: Pull
838 Pull Up / Down Config. Field: 100K Ohm Pull Up
839 Hyst. Enable Field: Hysteresis Enabled */
840 IOMUXC_SetPinConfig(
841 IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 PAD functional properties : */
842 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
843 Drive Strength Field: R0/6
844 Speed Field: medium(100MHz)
845 Open Drain Enable Field: Open Drain Disabled
846 Pull / Keep Enable Field: Pull/Keeper Enabled
847 Pull / Keep Select Field: Pull
848 Pull Up / Down Config. Field: 100K Ohm Pull Up
849 Hyst. Enable Field: Hysteresis Enabled */
850 IOMUXC_SetPinConfig(
851 IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 PAD functional properties : */
852 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
853 Drive Strength Field: R0/6
854 Speed Field: medium(100MHz)
855 Open Drain Enable Field: Open Drain Disabled
856 Pull / Keep Enable Field: Pull/Keeper Enabled
857 Pull / Keep Select Field: Pull
858 Pull Up / Down Config. Field: 100K Ohm Pull Up
859 Hyst. Enable Field: Hysteresis Enabled */
860 IOMUXC_SetPinConfig(
861 IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 PAD functional properties : */
862 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
863 Drive Strength Field: R0/6
864 Speed Field: medium(100MHz)
865 Open Drain Enable Field: Open Drain Disabled
866 Pull / Keep Enable Field: Pull/Keeper Enabled
867 Pull / Keep Select Field: Pull
868 Pull Up / Down Config. Field: 100K Ohm Pull Up
869 Hyst. Enable Field: Hysteresis Enabled */
870 IOMUXC_SetPinConfig(
871 IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 PAD functional properties : */
872 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
873 Drive Strength Field: R0/6
874 Speed Field: medium(100MHz)
875 Open Drain Enable Field: Open Drain Disabled
876 Pull / Keep Enable Field: Pull/Keeper Enabled
877 Pull / Keep Select Field: Pull
878 Pull Up / Down Config. Field: 100K Ohm Pull Up
879 Hyst. Enable Field: Hysteresis Enabled */
880 IOMUXC_SetPinConfig(
881 IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 PAD functional properties : */
882 0x10B0u); /* Slew Rate Field: Slow Slew Rate
883 Drive Strength Field: R0/6
884 Speed Field: medium(100MHz)
885 Open Drain Enable Field: Open Drain Disabled
886 Pull / Keep Enable Field: Pull/Keeper Enabled
887 Pull / Keep Select Field: Keeper
888 Pull Up / Down Config. Field: 100K Ohm Pull Down
889 Hyst. Enable Field: Hysteresis Disabled */
890}
891
892
893/*
894 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
895BOARD_InitCAN:
896- options: {coreID: core0, enableClock: 'true'}
897- pin_list:
898 - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
899 - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
900 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
901 */
902
903/* FUNCTION ************************************************************************************************************
904 *
905 * Function Name : BOARD_InitCAN
906 * Description : Configures pin routing and optionally pin electrical features.
907 *
908 * END ****************************************************************************************************************/
909void BOARD_InitCAN(void) {
910 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
911
912 IOMUXC_SetPinMux(
913 IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, /* GPIO_AD_B0_14 is configured as FLEXCAN2_TX */
914 0U); /* Software Input On Field: Input Path is determined by functionality */
915 IOMUXC_SetPinMux(
916 IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, /* GPIO_AD_B0_15 is configured as FLEXCAN2_RX */
917 0U); /* Software Input On Field: Input Path is determined by functionality */
918}
919
920
921/*
922 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
923BOARD_InitENET:
924- options: {coreID: core0, enableClock: 'true'}
925- pin_list:
926 - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
927 - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
928 - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
929 - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
930 - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
931 - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
932 - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
933 - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
934 - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
935 - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
936 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
937 */
938
939/* FUNCTION ************************************************************************************************************
940 *
941 * Function Name : BOARD_InitENET
942 * Description : Configures pin routing and optionally pin electrical features.
943 *
944 * END ****************************************************************************************************************/
945void BOARD_InitENET(void) {
946 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
947
948 IOMUXC_SetPinMux(
949 IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
950 0U); /* Software Input On Field: Input Path is determined by functionality */
951 IOMUXC_SetPinMux(
952 IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
953 0U); /* Software Input On Field: Input Path is determined by functionality */
954 IOMUXC_SetPinMux(
955 IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
956 0U); /* Software Input On Field: Input Path is determined by functionality */
957 IOMUXC_SetPinMux(
958 IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
959 0U); /* Software Input On Field: Input Path is determined by functionality */
960 IOMUXC_SetPinMux(
961 IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
962 0U); /* Software Input On Field: Input Path is determined by functionality */
963 IOMUXC_SetPinMux(
964 IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
965 0U); /* Software Input On Field: Input Path is determined by functionality */
966 IOMUXC_SetPinMux(
967 IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
968 0U); /* Software Input On Field: Input Path is determined by functionality */
969 IOMUXC_SetPinMux(
970 IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
971 0U); /* Software Input On Field: Input Path is determined by functionality */
972 IOMUXC_SetPinMux(
973 IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
974 0U); /* Software Input On Field: Input Path is determined by functionality */
975 IOMUXC_SetPinMux(
976 IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
977 0U); /* Software Input On Field: Input Path is determined by functionality */
978}
979
980
981/*
982 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
983BOARD_InitUSDHC:
984- options: {coreID: core0, enableClock: 'true'}
985- pin_list:
986 - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
987 - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
988 - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
989 - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
990 - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
991 - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
992 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
993 */
994
995/* FUNCTION ************************************************************************************************************
996 *
997 * Function Name : BOARD_InitUSDHC
998 * Description : Configures pin routing and optionally pin electrical features.
999 *
1000 * END ****************************************************************************************************************/
1001void BOARD_InitUSDHC(void) {
1002 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
1003
1004 IOMUXC_SetPinMux(
1005 IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, /* GPIO_SD_B0_00 is configured as USDHC1_CMD */
1006 0U); /* Software Input On Field: Input Path is determined by functionality */
1007 IOMUXC_SetPinMux(
1008 IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, /* GPIO_SD_B0_01 is configured as USDHC1_CLK */
1009 0U); /* Software Input On Field: Input Path is determined by functionality */
1010 IOMUXC_SetPinMux(
1011 IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, /* GPIO_SD_B0_02 is configured as USDHC1_DATA0 */
1012 0U); /* Software Input On Field: Input Path is determined by functionality */
1013 IOMUXC_SetPinMux(
1014 IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, /* GPIO_SD_B0_03 is configured as USDHC1_DATA1 */
1015 0U); /* Software Input On Field: Input Path is determined by functionality */
1016 IOMUXC_SetPinMux(
1017 IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, /* GPIO_SD_B0_04 is configured as USDHC1_DATA2 */
1018 0U); /* Software Input On Field: Input Path is determined by functionality */
1019 IOMUXC_SetPinMux(
1020 IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, /* GPIO_SD_B0_05 is configured as USDHC1_DATA3 */
1021 0U); /* Software Input On Field: Input Path is determined by functionality */
1022}
1023
1024
1025/*
1026 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
1027BOARD_InitHyperFlash:
1028- options: {coreID: core0, enableClock: 'true'}
1029- pin_list:
1030 - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
1031 - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
1032 - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
1033 - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
1034 - {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00}
1035 - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01}
1036 - {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02}
1037 - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03}
1038 - {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04}
1039 - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
1040 - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
1041 - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
1042 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
1043 */
1044
1045/* FUNCTION ************************************************************************************************************
1046 *
1047 * Function Name : BOARD_InitHyperFlash
1048 * Description : Configures pin routing and optionally pin electrical features.
1049 *
1050 * END ****************************************************************************************************************/
1051void BOARD_InitHyperFlash(void) {
1052 CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
1053
1054 IOMUXC_SetPinMux(
1055 IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, /* GPIO_SD_B1_00 is configured as FLEXSPIB_DATA03 */
1056 0U); /* Software Input On Field: Input Path is determined by functionality */
1057 IOMUXC_SetPinMux(
1058 IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, /* GPIO_SD_B1_01 is configured as FLEXSPIB_DATA02 */
1059 0U); /* Software Input On Field: Input Path is determined by functionality */
1060 IOMUXC_SetPinMux(
1061 IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, /* GPIO_SD_B1_02 is configured as FLEXSPIB_DATA01 */
1062 0U); /* Software Input On Field: Input Path is determined by functionality */
1063 IOMUXC_SetPinMux(
1064 IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, /* GPIO_SD_B1_03 is configured as FLEXSPIB_DATA00 */
1065 0U); /* Software Input On Field: Input Path is determined by functionality */
1066 IOMUXC_SetPinMux(
1067 IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, /* GPIO_SD_B1_04 is configured as FLEXSPIB_SCLK */
1068 0U); /* Software Input On Field: Input Path is determined by functionality */
1069 IOMUXC_SetPinMux(
1070 IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, /* GPIO_SD_B1_05 is configured as FLEXSPIA_DQS */
1071 0U); /* Software Input On Field: Input Path is determined by functionality */
1072 IOMUXC_SetPinMux(
1073 IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, /* GPIO_SD_B1_06 is configured as FLEXSPIA_SS0_B */
1074 0U); /* Software Input On Field: Input Path is determined by functionality */
1075 IOMUXC_SetPinMux(
1076 IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, /* GPIO_SD_B1_07 is configured as FLEXSPIA_SCLK */
1077 0U); /* Software Input On Field: Input Path is determined by functionality */
1078 IOMUXC_SetPinMux(
1079 IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, /* GPIO_SD_B1_08 is configured as FLEXSPIA_DATA00 */
1080 0U); /* Software Input On Field: Input Path is determined by functionality */
1081 IOMUXC_SetPinMux(
1082 IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, /* GPIO_SD_B1_09 is configured as FLEXSPIA_DATA01 */
1083 0U); /* Software Input On Field: Input Path is determined by functionality */
1084 IOMUXC_SetPinMux(
1085 IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, /* GPIO_SD_B1_10 is configured as FLEXSPIA_DATA02 */
1086 0U); /* Software Input On Field: Input Path is determined by functionality */
1087 IOMUXC_SetPinMux(
1088 IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, /* GPIO_SD_B1_11 is configured as FLEXSPIA_DATA03 */
1089 0U); /* Software Input On Field: Input Path is determined by functionality */
1090}
1091
1092/***********************************************************************************************************************
1093 * EOF
1094 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.h
new file mode 100644
index 000000000..aa4d55343
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/project_template/pin_mux.h
@@ -0,0 +1,938 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/***********************************************************************************************************************
17 * Definitions
18 **********************************************************************************************************************/
19
20/*! @brief Direction type */
21typedef enum _pin_mux_direction
22{
23 kPIN_MUX_DirectionInput = 0U, /* Input direction */
24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */
25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
26} pin_mux_direction_t;
27
28/*!
29 * @addtogroup pin_mux
30 * @{
31 */
32
33/***********************************************************************************************************************
34 * API
35 **********************************************************************************************************************/
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41/*!
42 * @brief Calls initialization functions.
43 *
44 */
45void BOARD_InitBootPins(void);
46
47
48/*!
49 * @brief Configures pin routing and optionally pin electrical features.
50 *
51 */
52void BOARD_InitPins(void);
53
54/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
55#define BOARD_INITDEBUG_UART_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
56#define BOARD_INITDEBUG_UART_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
57#define BOARD_INITDEBUG_UART_UART1_TXD_PIN_NAME GPIO_AD_B0_12 /*!< Pin name */
58#define BOARD_INITDEBUG_UART_UART1_TXD_LABEL "UART1_TXD" /*!< Label */
59#define BOARD_INITDEBUG_UART_UART1_TXD_NAME "UART1_TXD" /*!< Identifier name */
60
61/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
62#define BOARD_INITDEBUG_UART_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
63#define BOARD_INITDEBUG_UART_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
64#define BOARD_INITDEBUG_UART_UART1_RXD_PIN_NAME GPIO_AD_B0_13 /*!< Pin name */
65#define BOARD_INITDEBUG_UART_UART1_RXD_LABEL "UART1_RXD" /*!< Label */
66#define BOARD_INITDEBUG_UART_UART1_RXD_NAME "UART1_RXD" /*!< Identifier name */
67
68
69/*!
70 * @brief Configures pin routing and optionally pin electrical features.
71 *
72 */
73void BOARD_InitDEBUG_UART(void);
74
75/* GPIO_EMC_09 (coord C2), SEMC_A0 */
76#define BOARD_INITSDRAM_SEMC_A0_PERIPHERAL SEMC /*!< Device name: SEMC */
77#define BOARD_INITSDRAM_SEMC_A0_SIGNAL ADDR /*!< SEMC signal: ADDR */
78#define BOARD_INITSDRAM_SEMC_A0_CHANNEL 0U /*!< SEMC ADDR channel: 00 */
79#define BOARD_INITSDRAM_SEMC_A0_PIN_NAME GPIO_EMC_09 /*!< Pin name */
80#define BOARD_INITSDRAM_SEMC_A0_LABEL "SEMC_A0" /*!< Label */
81#define BOARD_INITSDRAM_SEMC_A0_NAME "SEMC_A0" /*!< Identifier name */
82
83/* GPIO_EMC_10 (coord G1), SEMC_A1 */
84#define BOARD_INITSDRAM_SEMC_A1_PERIPHERAL SEMC /*!< Device name: SEMC */
85#define BOARD_INITSDRAM_SEMC_A1_SIGNAL ADDR /*!< SEMC signal: ADDR */
86#define BOARD_INITSDRAM_SEMC_A1_CHANNEL 1U /*!< SEMC ADDR channel: 01 */
87#define BOARD_INITSDRAM_SEMC_A1_PIN_NAME GPIO_EMC_10 /*!< Pin name */
88#define BOARD_INITSDRAM_SEMC_A1_LABEL "SEMC_A1" /*!< Label */
89#define BOARD_INITSDRAM_SEMC_A1_NAME "SEMC_A1" /*!< Identifier name */
90
91/* GPIO_EMC_11 (coord G3), SEMC_A2 */
92#define BOARD_INITSDRAM_SEMC_A2_PERIPHERAL SEMC /*!< Device name: SEMC */
93#define BOARD_INITSDRAM_SEMC_A2_SIGNAL ADDR /*!< SEMC signal: ADDR */
94#define BOARD_INITSDRAM_SEMC_A2_CHANNEL 2U /*!< SEMC ADDR channel: 02 */
95#define BOARD_INITSDRAM_SEMC_A2_PIN_NAME GPIO_EMC_11 /*!< Pin name */
96#define BOARD_INITSDRAM_SEMC_A2_LABEL "SEMC_A2" /*!< Label */
97#define BOARD_INITSDRAM_SEMC_A2_NAME "SEMC_A2" /*!< Identifier name */
98
99/* GPIO_EMC_12 (coord H1), SEMC_A3 */
100#define BOARD_INITSDRAM_SEMC_A3_PERIPHERAL SEMC /*!< Device name: SEMC */
101#define BOARD_INITSDRAM_SEMC_A3_SIGNAL ADDR /*!< SEMC signal: ADDR */
102#define BOARD_INITSDRAM_SEMC_A3_CHANNEL 3U /*!< SEMC ADDR channel: 03 */
103#define BOARD_INITSDRAM_SEMC_A3_PIN_NAME GPIO_EMC_12 /*!< Pin name */
104#define BOARD_INITSDRAM_SEMC_A3_LABEL "SEMC_A3" /*!< Label */
105#define BOARD_INITSDRAM_SEMC_A3_NAME "SEMC_A3" /*!< Identifier name */
106
107/* GPIO_EMC_13 (coord A6), SEMC_A4 */
108#define BOARD_INITSDRAM_SEMC_A4_PERIPHERAL SEMC /*!< Device name: SEMC */
109#define BOARD_INITSDRAM_SEMC_A4_SIGNAL ADDR /*!< SEMC signal: ADDR */
110#define BOARD_INITSDRAM_SEMC_A4_CHANNEL 4U /*!< SEMC ADDR channel: 04 */
111#define BOARD_INITSDRAM_SEMC_A4_PIN_NAME GPIO_EMC_13 /*!< Pin name */
112#define BOARD_INITSDRAM_SEMC_A4_LABEL "SEMC_A4" /*!< Label */
113#define BOARD_INITSDRAM_SEMC_A4_NAME "SEMC_A4" /*!< Identifier name */
114
115/* GPIO_EMC_14 (coord B6), SEMC_A5 */
116#define BOARD_INITSDRAM_SEMC_A5_PERIPHERAL SEMC /*!< Device name: SEMC */
117#define BOARD_INITSDRAM_SEMC_A5_SIGNAL ADDR /*!< SEMC signal: ADDR */
118#define BOARD_INITSDRAM_SEMC_A5_CHANNEL 5U /*!< SEMC ADDR channel: 05 */
119#define BOARD_INITSDRAM_SEMC_A5_PIN_NAME GPIO_EMC_14 /*!< Pin name */
120#define BOARD_INITSDRAM_SEMC_A5_LABEL "SEMC_A5" /*!< Label */
121#define BOARD_INITSDRAM_SEMC_A5_NAME "SEMC_A5" /*!< Identifier name */
122
123/* GPIO_EMC_15 (coord B1), SEMC_A6 */
124#define BOARD_INITSDRAM_SEMC_A6_PERIPHERAL SEMC /*!< Device name: SEMC */
125#define BOARD_INITSDRAM_SEMC_A6_SIGNAL ADDR /*!< SEMC signal: ADDR */
126#define BOARD_INITSDRAM_SEMC_A6_CHANNEL 6U /*!< SEMC ADDR channel: 06 */
127#define BOARD_INITSDRAM_SEMC_A6_PIN_NAME GPIO_EMC_15 /*!< Pin name */
128#define BOARD_INITSDRAM_SEMC_A6_LABEL "SEMC_A6" /*!< Label */
129#define BOARD_INITSDRAM_SEMC_A6_NAME "SEMC_A6" /*!< Identifier name */
130
131/* GPIO_EMC_16 (coord A5), SEMC_A7 */
132#define BOARD_INITSDRAM_SEMC_A7_PERIPHERAL SEMC /*!< Device name: SEMC */
133#define BOARD_INITSDRAM_SEMC_A7_SIGNAL ADDR /*!< SEMC signal: ADDR */
134#define BOARD_INITSDRAM_SEMC_A7_CHANNEL 7U /*!< SEMC ADDR channel: 07 */
135#define BOARD_INITSDRAM_SEMC_A7_PIN_NAME GPIO_EMC_16 /*!< Pin name */
136#define BOARD_INITSDRAM_SEMC_A7_LABEL "SEMC_A7" /*!< Label */
137#define BOARD_INITSDRAM_SEMC_A7_NAME "SEMC_A7" /*!< Identifier name */
138
139/* GPIO_EMC_17 (coord A4), SEMC_A8 */
140#define BOARD_INITSDRAM_SEMC_A8_PERIPHERAL SEMC /*!< Device name: SEMC */
141#define BOARD_INITSDRAM_SEMC_A8_SIGNAL ADDR /*!< SEMC signal: ADDR */
142#define BOARD_INITSDRAM_SEMC_A8_CHANNEL 8U /*!< SEMC ADDR channel: 08 */
143#define BOARD_INITSDRAM_SEMC_A8_PIN_NAME GPIO_EMC_17 /*!< Pin name */
144#define BOARD_INITSDRAM_SEMC_A8_LABEL "SEMC_A8" /*!< Label */
145#define BOARD_INITSDRAM_SEMC_A8_NAME "SEMC_A8" /*!< Identifier name */
146
147/* GPIO_EMC_18 (coord B2), SEMC_A9 */
148#define BOARD_INITSDRAM_SEMC_A9_PERIPHERAL SEMC /*!< Device name: SEMC */
149#define BOARD_INITSDRAM_SEMC_A9_SIGNAL ADDR /*!< SEMC signal: ADDR */
150#define BOARD_INITSDRAM_SEMC_A9_CHANNEL 9U /*!< SEMC ADDR channel: 09 */
151#define BOARD_INITSDRAM_SEMC_A9_PIN_NAME GPIO_EMC_18 /*!< Pin name */
152#define BOARD_INITSDRAM_SEMC_A9_LABEL "SEMC_A9" /*!< Label */
153#define BOARD_INITSDRAM_SEMC_A9_NAME "SEMC_A9" /*!< Identifier name */
154
155/* GPIO_EMC_23 (coord G2), SEMC_A10 */
156#define BOARD_INITSDRAM_SEMC_A10_PERIPHERAL SEMC /*!< Device name: SEMC */
157#define BOARD_INITSDRAM_SEMC_A10_SIGNAL ADDR /*!< SEMC signal: ADDR */
158#define BOARD_INITSDRAM_SEMC_A10_CHANNEL 10U /*!< SEMC ADDR channel: 10 */
159#define BOARD_INITSDRAM_SEMC_A10_PIN_NAME GPIO_EMC_23 /*!< Pin name */
160#define BOARD_INITSDRAM_SEMC_A10_LABEL "SEMC_A10" /*!< Label */
161#define BOARD_INITSDRAM_SEMC_A10_NAME "SEMC_A10" /*!< Identifier name */
162
163/* GPIO_EMC_19 (coord B4), SEMC_A11 */
164#define BOARD_INITSDRAM_SEMC_A11_PERIPHERAL SEMC /*!< Device name: SEMC */
165#define BOARD_INITSDRAM_SEMC_A11_SIGNAL ADDR /*!< SEMC signal: ADDR */
166#define BOARD_INITSDRAM_SEMC_A11_CHANNEL 11U /*!< SEMC ADDR channel: 11 */
167#define BOARD_INITSDRAM_SEMC_A11_PIN_NAME GPIO_EMC_19 /*!< Pin name */
168#define BOARD_INITSDRAM_SEMC_A11_LABEL "SEMC_A11" /*!< Label */
169#define BOARD_INITSDRAM_SEMC_A11_NAME "SEMC_A11" /*!< Identifier name */
170
171/* GPIO_EMC_20 (coord A3), SEMC_A12 */
172#define BOARD_INITSDRAM_SEMC_A12_PERIPHERAL SEMC /*!< Device name: SEMC */
173#define BOARD_INITSDRAM_SEMC_A12_SIGNAL ADDR /*!< SEMC signal: ADDR */
174#define BOARD_INITSDRAM_SEMC_A12_CHANNEL 12U /*!< SEMC ADDR channel: 12 */
175#define BOARD_INITSDRAM_SEMC_A12_PIN_NAME GPIO_EMC_20 /*!< Pin name */
176#define BOARD_INITSDRAM_SEMC_A12_LABEL "SEMC_A12" /*!< Label */
177#define BOARD_INITSDRAM_SEMC_A12_NAME "SEMC_A12" /*!< Identifier name */
178
179/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
180#define BOARD_INITSDRAM_SEMC_BA0_PERIPHERAL SEMC /*!< Device name: SEMC */
181#define BOARD_INITSDRAM_SEMC_BA0_SIGNAL BA /*!< SEMC signal: BA */
182#define BOARD_INITSDRAM_SEMC_BA0_CHANNEL 0U /*!< SEMC BA channel: 0 */
183#define BOARD_INITSDRAM_SEMC_BA0_PIN_NAME GPIO_EMC_21 /*!< Pin name */
184#define BOARD_INITSDRAM_SEMC_BA0_LABEL "SEMC_BA0" /*!< Label */
185#define BOARD_INITSDRAM_SEMC_BA0_NAME "SEMC_BA0" /*!< Identifier name */
186
187/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
188#define BOARD_INITSDRAM_SEMC_BA1_PERIPHERAL SEMC /*!< Device name: SEMC */
189#define BOARD_INITSDRAM_SEMC_BA1_SIGNAL BA /*!< SEMC signal: BA */
190#define BOARD_INITSDRAM_SEMC_BA1_CHANNEL 1U /*!< SEMC BA channel: 1 */
191#define BOARD_INITSDRAM_SEMC_BA1_PIN_NAME GPIO_EMC_22 /*!< Pin name */
192#define BOARD_INITSDRAM_SEMC_BA1_LABEL "SEMC_BA1" /*!< Label */
193#define BOARD_INITSDRAM_SEMC_BA1_NAME "SEMC_BA1" /*!< Identifier name */
194
195/* GPIO_EMC_24 (coord D3), SEMC_CAS */
196#define BOARD_INITSDRAM_SEMC_CAS_PERIPHERAL SEMC /*!< Device name: SEMC */
197#define BOARD_INITSDRAM_SEMC_CAS_SIGNAL semc_cas /*!< SEMC signal: semc_cas */
198#define BOARD_INITSDRAM_SEMC_CAS_PIN_NAME GPIO_EMC_24 /*!< Pin name */
199#define BOARD_INITSDRAM_SEMC_CAS_LABEL "SEMC_CAS" /*!< Label */
200#define BOARD_INITSDRAM_SEMC_CAS_NAME "SEMC_CAS" /*!< Identifier name */
201
202/* GPIO_EMC_27 (coord A2), SEMC_CKE */
203#define BOARD_INITSDRAM_SEMC_CKE_PERIPHERAL SEMC /*!< Device name: SEMC */
204#define BOARD_INITSDRAM_SEMC_CKE_SIGNAL semc_cke /*!< SEMC signal: semc_cke */
205#define BOARD_INITSDRAM_SEMC_CKE_PIN_NAME GPIO_EMC_27 /*!< Pin name */
206#define BOARD_INITSDRAM_SEMC_CKE_LABEL "SEMC_CKE" /*!< Label */
207#define BOARD_INITSDRAM_SEMC_CKE_NAME "SEMC_CKE" /*!< Identifier name */
208
209/* GPIO_EMC_26 (coord B3), SEMC_CLK */
210#define BOARD_INITSDRAM_SEMC_CLK_PERIPHERAL SEMC /*!< Device name: SEMC */
211#define BOARD_INITSDRAM_SEMC_CLK_SIGNAL semc_clk /*!< SEMC signal: semc_clk */
212#define BOARD_INITSDRAM_SEMC_CLK_PIN_NAME GPIO_EMC_26 /*!< Pin name */
213#define BOARD_INITSDRAM_SEMC_CLK_LABEL "SEMC_CLK" /*!< Label */
214#define BOARD_INITSDRAM_SEMC_CLK_NAME "SEMC_CLK" /*!< Identifier name */
215
216/* GPIO_EMC_00 (coord E3), SEMC_D0 */
217#define BOARD_INITSDRAM_SEMC_D0_PERIPHERAL SEMC /*!< Device name: SEMC */
218#define BOARD_INITSDRAM_SEMC_D0_SIGNAL DATA /*!< SEMC signal: DATA */
219#define BOARD_INITSDRAM_SEMC_D0_CHANNEL 0U /*!< SEMC DATA channel: 00 */
220#define BOARD_INITSDRAM_SEMC_D0_PIN_NAME GPIO_EMC_00 /*!< Pin name */
221#define BOARD_INITSDRAM_SEMC_D0_LABEL "SEMC_D0" /*!< Label */
222#define BOARD_INITSDRAM_SEMC_D0_NAME "SEMC_D0" /*!< Identifier name */
223
224/* GPIO_EMC_01 (coord F3), SEMC_D1 */
225#define BOARD_INITSDRAM_SEMC_D1_PERIPHERAL SEMC /*!< Device name: SEMC */
226#define BOARD_INITSDRAM_SEMC_D1_SIGNAL DATA /*!< SEMC signal: DATA */
227#define BOARD_INITSDRAM_SEMC_D1_CHANNEL 1U /*!< SEMC DATA channel: 01 */
228#define BOARD_INITSDRAM_SEMC_D1_PIN_NAME GPIO_EMC_01 /*!< Pin name */
229#define BOARD_INITSDRAM_SEMC_D1_LABEL "SEMC_D1" /*!< Label */
230#define BOARD_INITSDRAM_SEMC_D1_NAME "SEMC_D1" /*!< Identifier name */
231
232/* GPIO_EMC_02 (coord F4), SEMC_D2 */
233#define BOARD_INITSDRAM_SEMC_D2_PERIPHERAL SEMC /*!< Device name: SEMC */
234#define BOARD_INITSDRAM_SEMC_D2_SIGNAL DATA /*!< SEMC signal: DATA */
235#define BOARD_INITSDRAM_SEMC_D2_CHANNEL 2U /*!< SEMC DATA channel: 02 */
236#define BOARD_INITSDRAM_SEMC_D2_PIN_NAME GPIO_EMC_02 /*!< Pin name */
237#define BOARD_INITSDRAM_SEMC_D2_LABEL "SEMC_D2" /*!< Label */
238#define BOARD_INITSDRAM_SEMC_D2_NAME "SEMC_D2" /*!< Identifier name */
239
240/* GPIO_EMC_03 (coord G4), SEMC_D3 */
241#define BOARD_INITSDRAM_SEMC_D3_PERIPHERAL SEMC /*!< Device name: SEMC */
242#define BOARD_INITSDRAM_SEMC_D3_SIGNAL DATA /*!< SEMC signal: DATA */
243#define BOARD_INITSDRAM_SEMC_D3_CHANNEL 3U /*!< SEMC DATA channel: 03 */
244#define BOARD_INITSDRAM_SEMC_D3_PIN_NAME GPIO_EMC_03 /*!< Pin name */
245#define BOARD_INITSDRAM_SEMC_D3_LABEL "SEMC_D3" /*!< Label */
246#define BOARD_INITSDRAM_SEMC_D3_NAME "SEMC_D3" /*!< Identifier name */
247
248/* GPIO_EMC_04 (coord F2), SEMC_D4 */
249#define BOARD_INITSDRAM_SEMC_D4_PERIPHERAL SEMC /*!< Device name: SEMC */
250#define BOARD_INITSDRAM_SEMC_D4_SIGNAL DATA /*!< SEMC signal: DATA */
251#define BOARD_INITSDRAM_SEMC_D4_CHANNEL 4U /*!< SEMC DATA channel: 04 */
252#define BOARD_INITSDRAM_SEMC_D4_PIN_NAME GPIO_EMC_04 /*!< Pin name */
253#define BOARD_INITSDRAM_SEMC_D4_LABEL "SEMC_D4" /*!< Label */
254#define BOARD_INITSDRAM_SEMC_D4_NAME "SEMC_D4" /*!< Identifier name */
255
256/* GPIO_EMC_05 (coord G5), SEMC_D5 */
257#define BOARD_INITSDRAM_SEMC_D5_PERIPHERAL SEMC /*!< Device name: SEMC */
258#define BOARD_INITSDRAM_SEMC_D5_SIGNAL DATA /*!< SEMC signal: DATA */
259#define BOARD_INITSDRAM_SEMC_D5_CHANNEL 5U /*!< SEMC DATA channel: 05 */
260#define BOARD_INITSDRAM_SEMC_D5_PIN_NAME GPIO_EMC_05 /*!< Pin name */
261#define BOARD_INITSDRAM_SEMC_D5_LABEL "SEMC_D5" /*!< Label */
262#define BOARD_INITSDRAM_SEMC_D5_NAME "SEMC_D5" /*!< Identifier name */
263
264/* GPIO_EMC_06 (coord H5), SEMC_D6 */
265#define BOARD_INITSDRAM_SEMC_D6_PERIPHERAL SEMC /*!< Device name: SEMC */
266#define BOARD_INITSDRAM_SEMC_D6_SIGNAL DATA /*!< SEMC signal: DATA */
267#define BOARD_INITSDRAM_SEMC_D6_CHANNEL 6U /*!< SEMC DATA channel: 06 */
268#define BOARD_INITSDRAM_SEMC_D6_PIN_NAME GPIO_EMC_06 /*!< Pin name */
269#define BOARD_INITSDRAM_SEMC_D6_LABEL "SEMC_D6" /*!< Label */
270#define BOARD_INITSDRAM_SEMC_D6_NAME "SEMC_D6" /*!< Identifier name */
271
272/* GPIO_EMC_07 (coord H4), SEMC_D7 */
273#define BOARD_INITSDRAM_SEMC_D7_PERIPHERAL SEMC /*!< Device name: SEMC */
274#define BOARD_INITSDRAM_SEMC_D7_SIGNAL DATA /*!< SEMC signal: DATA */
275#define BOARD_INITSDRAM_SEMC_D7_CHANNEL 7U /*!< SEMC DATA channel: 07 */
276#define BOARD_INITSDRAM_SEMC_D7_PIN_NAME GPIO_EMC_07 /*!< Pin name */
277#define BOARD_INITSDRAM_SEMC_D7_LABEL "SEMC_D7" /*!< Label */
278#define BOARD_INITSDRAM_SEMC_D7_NAME "SEMC_D7" /*!< Identifier name */
279
280/* GPIO_EMC_30 (coord C6), SEMC_D8 */
281#define BOARD_INITSDRAM_SEMC_D8_PERIPHERAL SEMC /*!< Device name: SEMC */
282#define BOARD_INITSDRAM_SEMC_D8_SIGNAL DATA /*!< SEMC signal: DATA */
283#define BOARD_INITSDRAM_SEMC_D8_CHANNEL 8U /*!< SEMC DATA channel: 08 */
284#define BOARD_INITSDRAM_SEMC_D8_PIN_NAME GPIO_EMC_30 /*!< Pin name */
285#define BOARD_INITSDRAM_SEMC_D8_LABEL "SEMC_D8" /*!< Label */
286#define BOARD_INITSDRAM_SEMC_D8_NAME "SEMC_D8" /*!< Identifier name */
287
288/* GPIO_EMC_31 (coord C5), SEMC_D9 */
289#define BOARD_INITSDRAM_SEMC_D9_PERIPHERAL SEMC /*!< Device name: SEMC */
290#define BOARD_INITSDRAM_SEMC_D9_SIGNAL DATA /*!< SEMC signal: DATA */
291#define BOARD_INITSDRAM_SEMC_D9_CHANNEL 9U /*!< SEMC DATA channel: 09 */
292#define BOARD_INITSDRAM_SEMC_D9_PIN_NAME GPIO_EMC_31 /*!< Pin name */
293#define BOARD_INITSDRAM_SEMC_D9_LABEL "SEMC_D9" /*!< Label */
294#define BOARD_INITSDRAM_SEMC_D9_NAME "SEMC_D9" /*!< Identifier name */
295
296/* GPIO_EMC_32 (coord D5), SEMC_D10 */
297#define BOARD_INITSDRAM_SEMC_D10_PERIPHERAL SEMC /*!< Device name: SEMC */
298#define BOARD_INITSDRAM_SEMC_D10_SIGNAL DATA /*!< SEMC signal: DATA */
299#define BOARD_INITSDRAM_SEMC_D10_CHANNEL 10U /*!< SEMC DATA channel: 10 */
300#define BOARD_INITSDRAM_SEMC_D10_PIN_NAME GPIO_EMC_32 /*!< Pin name */
301#define BOARD_INITSDRAM_SEMC_D10_LABEL "SEMC_D10" /*!< Label */
302#define BOARD_INITSDRAM_SEMC_D10_NAME "SEMC_D10" /*!< Identifier name */
303
304/* GPIO_EMC_33 (coord C4), SEMC_D11 */
305#define BOARD_INITSDRAM_SEMC_D11_PERIPHERAL SEMC /*!< Device name: SEMC */
306#define BOARD_INITSDRAM_SEMC_D11_SIGNAL DATA /*!< SEMC signal: DATA */
307#define BOARD_INITSDRAM_SEMC_D11_CHANNEL 11U /*!< SEMC DATA channel: 11 */
308#define BOARD_INITSDRAM_SEMC_D11_PIN_NAME GPIO_EMC_33 /*!< Pin name */
309#define BOARD_INITSDRAM_SEMC_D11_LABEL "SEMC_D11" /*!< Label */
310#define BOARD_INITSDRAM_SEMC_D11_NAME "SEMC_D11" /*!< Identifier name */
311
312/* GPIO_EMC_34 (coord D4), SEMC_D12 */
313#define BOARD_INITSDRAM_SEMC_D12_PERIPHERAL SEMC /*!< Device name: SEMC */
314#define BOARD_INITSDRAM_SEMC_D12_SIGNAL DATA /*!< SEMC signal: DATA */
315#define BOARD_INITSDRAM_SEMC_D12_CHANNEL 12U /*!< SEMC DATA channel: 12 */
316#define BOARD_INITSDRAM_SEMC_D12_PIN_NAME GPIO_EMC_34 /*!< Pin name */
317#define BOARD_INITSDRAM_SEMC_D12_LABEL "SEMC_D12" /*!< Label */
318#define BOARD_INITSDRAM_SEMC_D12_NAME "SEMC_D12" /*!< Identifier name */
319
320/* GPIO_EMC_35 (coord E5), SEMC_D13 */
321#define BOARD_INITSDRAM_SEMC_D13_PERIPHERAL SEMC /*!< Device name: SEMC */
322#define BOARD_INITSDRAM_SEMC_D13_SIGNAL DATA /*!< SEMC signal: DATA */
323#define BOARD_INITSDRAM_SEMC_D13_CHANNEL 13U /*!< SEMC DATA channel: 13 */
324#define BOARD_INITSDRAM_SEMC_D13_PIN_NAME GPIO_EMC_35 /*!< Pin name */
325#define BOARD_INITSDRAM_SEMC_D13_LABEL "SEMC_D13" /*!< Label */
326#define BOARD_INITSDRAM_SEMC_D13_NAME "SEMC_D13" /*!< Identifier name */
327
328/* GPIO_EMC_36 (coord C3), SEMC_D14 */
329#define BOARD_INITSDRAM_SEMC_D14_PERIPHERAL SEMC /*!< Device name: SEMC */
330#define BOARD_INITSDRAM_SEMC_D14_SIGNAL DATA /*!< SEMC signal: DATA */
331#define BOARD_INITSDRAM_SEMC_D14_CHANNEL 14U /*!< SEMC DATA channel: 14 */
332#define BOARD_INITSDRAM_SEMC_D14_PIN_NAME GPIO_EMC_36 /*!< Pin name */
333#define BOARD_INITSDRAM_SEMC_D14_LABEL "SEMC_D14" /*!< Label */
334#define BOARD_INITSDRAM_SEMC_D14_NAME "SEMC_D14" /*!< Identifier name */
335
336/* GPIO_EMC_37 (coord E4), SEMC_D15 */
337#define BOARD_INITSDRAM_SEMC_D15_PERIPHERAL SEMC /*!< Device name: SEMC */
338#define BOARD_INITSDRAM_SEMC_D15_SIGNAL DATA /*!< SEMC signal: DATA */
339#define BOARD_INITSDRAM_SEMC_D15_CHANNEL 15U /*!< SEMC DATA channel: 15 */
340#define BOARD_INITSDRAM_SEMC_D15_PIN_NAME GPIO_EMC_37 /*!< Pin name */
341#define BOARD_INITSDRAM_SEMC_D15_LABEL "SEMC_D15" /*!< Label */
342#define BOARD_INITSDRAM_SEMC_D15_NAME "SEMC_D15" /*!< Identifier name */
343
344/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
345#define BOARD_INITSDRAM_SEMC_DM0_PERIPHERAL SEMC /*!< Device name: SEMC */
346#define BOARD_INITSDRAM_SEMC_DM0_SIGNAL DM /*!< SEMC signal: DM */
347#define BOARD_INITSDRAM_SEMC_DM0_CHANNEL 0U /*!< SEMC DM channel: 0 */
348#define BOARD_INITSDRAM_SEMC_DM0_PIN_NAME GPIO_EMC_08 /*!< Pin name */
349#define BOARD_INITSDRAM_SEMC_DM0_LABEL "SEMC_DM0" /*!< Label */
350#define BOARD_INITSDRAM_SEMC_DM0_NAME "SEMC_DM0" /*!< Identifier name */
351
352/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
353#define BOARD_INITSDRAM_SEMC_DM1_PERIPHERAL SEMC /*!< Device name: SEMC */
354#define BOARD_INITSDRAM_SEMC_DM1_SIGNAL DM /*!< SEMC signal: DM */
355#define BOARD_INITSDRAM_SEMC_DM1_CHANNEL 1U /*!< SEMC DM channel: 1 */
356#define BOARD_INITSDRAM_SEMC_DM1_PIN_NAME GPIO_EMC_38 /*!< Pin name */
357#define BOARD_INITSDRAM_SEMC_DM1_LABEL "SEMC_DM1" /*!< Label */
358#define BOARD_INITSDRAM_SEMC_DM1_NAME "SEMC_DM1" /*!< Identifier name */
359
360/* GPIO_EMC_25 (coord D2), SEMC_RAS */
361#define BOARD_INITSDRAM_SEMC_RAS_PERIPHERAL SEMC /*!< Device name: SEMC */
362#define BOARD_INITSDRAM_SEMC_RAS_SIGNAL semc_ras /*!< SEMC signal: semc_ras */
363#define BOARD_INITSDRAM_SEMC_RAS_PIN_NAME GPIO_EMC_25 /*!< Pin name */
364#define BOARD_INITSDRAM_SEMC_RAS_LABEL "SEMC_RAS" /*!< Label */
365#define BOARD_INITSDRAM_SEMC_RAS_NAME "SEMC_RAS" /*!< Identifier name */
366
367/* GPIO_EMC_28 (coord D1), SEMC_WE */
368#define BOARD_INITSDRAM_SEMC_WE_PERIPHERAL SEMC /*!< Device name: SEMC */
369#define BOARD_INITSDRAM_SEMC_WE_SIGNAL semc_we /*!< SEMC signal: semc_we */
370#define BOARD_INITSDRAM_SEMC_WE_PIN_NAME GPIO_EMC_28 /*!< Pin name */
371#define BOARD_INITSDRAM_SEMC_WE_LABEL "SEMC_WE" /*!< Label */
372#define BOARD_INITSDRAM_SEMC_WE_NAME "SEMC_WE" /*!< Identifier name */
373
374/* GPIO_EMC_41 (coord C7), ENET_MDIO */
375#define BOARD_INITSDRAM_ENET_MDIO_PERIPHERAL SEMC /*!< Device name: SEMC */
376#define BOARD_INITSDRAM_ENET_MDIO_SIGNAL CSX /*!< SEMC signal: CSX */
377#define BOARD_INITSDRAM_ENET_MDIO_CHANNEL 0U /*!< SEMC CSX channel: 0 */
378#define BOARD_INITSDRAM_ENET_MDIO_PIN_NAME GPIO_EMC_41 /*!< Pin name */
379#define BOARD_INITSDRAM_ENET_MDIO_LABEL "ENET_MDIO" /*!< Label */
380#define BOARD_INITSDRAM_ENET_MDIO_NAME "ENET_MDIO" /*!< Identifier name */
381
382
383/*!
384 * @brief Configures pin routing and optionally pin electrical features.
385 *
386 */
387void BOARD_InitSDRAM(void);
388
389/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
390#define BOARD_INITCSI_CSI_D9_PERIPHERAL CSI /*!< Device name: CSI */
391#define BOARD_INITCSI_CSI_D9_SIGNAL csi_data /*!< CSI signal: csi_data */
392#define BOARD_INITCSI_CSI_D9_CHANNEL 9U /*!< CSI csi_data channel: 09 */
393#define BOARD_INITCSI_CSI_D9_PIN_NAME GPIO_AD_B1_08 /*!< Pin name */
394#define BOARD_INITCSI_CSI_D9_LABEL "AUD_INT/CSI_D9//J35[13]/J22[4]" /*!< Label */
395#define BOARD_INITCSI_CSI_D9_NAME "CSI_D9" /*!< Identifier name */
396
397/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
398#define BOARD_INITCSI_CSI_D8_PERIPHERAL CSI /*!< Device name: CSI */
399#define BOARD_INITCSI_CSI_D8_SIGNAL csi_data /*!< CSI signal: csi_data */
400#define BOARD_INITCSI_CSI_D8_CHANNEL 8U /*!< CSI csi_data channel: 08 */
401#define BOARD_INITCSI_CSI_D8_PIN_NAME GPIO_AD_B1_09 /*!< Pin name */
402#define BOARD_INITCSI_CSI_D8_LABEL "SAI1_MCLK/CSI_D8/J35[11]" /*!< Label */
403#define BOARD_INITCSI_CSI_D8_NAME "CSI_D8" /*!< Identifier name */
404
405/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
406#define BOARD_INITCSI_CSI_D7_PERIPHERAL CSI /*!< Device name: CSI */
407#define BOARD_INITCSI_CSI_D7_SIGNAL csi_data /*!< CSI signal: csi_data */
408#define BOARD_INITCSI_CSI_D7_CHANNEL 7U /*!< CSI csi_data channel: 07 */
409#define BOARD_INITCSI_CSI_D7_PIN_NAME GPIO_AD_B1_10 /*!< Pin name */
410#define BOARD_INITCSI_CSI_D7_LABEL "SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1]" /*!< Label */
411#define BOARD_INITCSI_CSI_D7_NAME "CSI_D7" /*!< Identifier name */
412
413/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
414#define BOARD_INITCSI_CSI_D6_PERIPHERAL CSI /*!< Device name: CSI */
415#define BOARD_INITCSI_CSI_D6_SIGNAL csi_data /*!< CSI signal: csi_data */
416#define BOARD_INITCSI_CSI_D6_CHANNEL 6U /*!< CSI csi_data channel: 06 */
417#define BOARD_INITCSI_CSI_D6_PIN_NAME GPIO_AD_B1_11 /*!< Pin name */
418#define BOARD_INITCSI_CSI_D6_LABEL "SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2]" /*!< Label */
419#define BOARD_INITCSI_CSI_D6_NAME "CSI_D6" /*!< Identifier name */
420
421/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
422#define BOARD_INITCSI_CSI_D5_PERIPHERAL CSI /*!< Device name: CSI */
423#define BOARD_INITCSI_CSI_D5_SIGNAL csi_data /*!< CSI signal: csi_data */
424#define BOARD_INITCSI_CSI_D5_CHANNEL 5U /*!< CSI csi_data channel: 05 */
425#define BOARD_INITCSI_CSI_D5_PIN_NAME GPIO_AD_B1_12 /*!< Pin name */
426#define BOARD_INITCSI_CSI_D5_LABEL "SAI1_RXD/CSI_D5/J35[5]/U13[16]" /*!< Label */
427#define BOARD_INITCSI_CSI_D5_NAME "CSI_D5" /*!< Identifier name */
428
429/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
430#define BOARD_INITCSI_CSI_D4_PERIPHERAL CSI /*!< Device name: CSI */
431#define BOARD_INITCSI_CSI_D4_SIGNAL csi_data /*!< CSI signal: csi_data */
432#define BOARD_INITCSI_CSI_D4_CHANNEL 4U /*!< CSI csi_data channel: 04 */
433#define BOARD_INITCSI_CSI_D4_PIN_NAME GPIO_AD_B1_13 /*!< Pin name */
434#define BOARD_INITCSI_CSI_D4_LABEL "SAI1_TXD/CSI_D4/J35[3]/U13[14]" /*!< Label */
435#define BOARD_INITCSI_CSI_D4_NAME "CSI_D4" /*!< Identifier name */
436
437/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
438#define BOARD_INITCSI_CSI_D2_PERIPHERAL CSI /*!< Device name: CSI */
439#define BOARD_INITCSI_CSI_D2_SIGNAL csi_data /*!< CSI signal: csi_data */
440#define BOARD_INITCSI_CSI_D2_CHANNEL 2U /*!< CSI csi_data channel: 02 */
441#define BOARD_INITCSI_CSI_D2_PIN_NAME GPIO_AD_B1_15 /*!< Pin name */
442#define BOARD_INITCSI_CSI_D2_LABEL "SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13]" /*!< Label */
443#define BOARD_INITCSI_CSI_D2_NAME "CSI_D2" /*!< Identifier name */
444
445/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
446#define BOARD_INITCSI_CSI_D3_PERIPHERAL CSI /*!< Device name: CSI */
447#define BOARD_INITCSI_CSI_D3_SIGNAL csi_data /*!< CSI signal: csi_data */
448#define BOARD_INITCSI_CSI_D3_CHANNEL 3U /*!< CSI csi_data channel: 03 */
449#define BOARD_INITCSI_CSI_D3_PIN_NAME GPIO_AD_B1_14 /*!< Pin name */
450#define BOARD_INITCSI_CSI_D3_LABEL "SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12]" /*!< Label */
451#define BOARD_INITCSI_CSI_D3_NAME "CSI_D3" /*!< Identifier name */
452
453/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
454#define BOARD_INITCSI_CSI_PIXCLK_PERIPHERAL CSI /*!< Device name: CSI */
455#define BOARD_INITCSI_CSI_PIXCLK_SIGNAL csi_pixclk /*!< CSI signal: csi_pixclk */
456#define BOARD_INITCSI_CSI_PIXCLK_PIN_NAME GPIO_AD_B1_04 /*!< Pin name */
457#define BOARD_INITCSI_CSI_PIXCLK_LABEL "CSI_PIXCLK/J35[8]/J23[3]" /*!< Label */
458#define BOARD_INITCSI_CSI_PIXCLK_NAME "CSI_PIXCLK" /*!< Identifier name */
459
460/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
461#define BOARD_INITCSI_CSI_MCLK_PERIPHERAL CSI /*!< Device name: CSI */
462#define BOARD_INITCSI_CSI_MCLK_SIGNAL csi_mclk /*!< CSI signal: csi_mclk */
463#define BOARD_INITCSI_CSI_MCLK_PIN_NAME GPIO_AD_B1_05 /*!< Pin name */
464#define BOARD_INITCSI_CSI_MCLK_LABEL "CSI_MCLK/J35[12]/J23[4]" /*!< Label */
465#define BOARD_INITCSI_CSI_MCLK_NAME "CSI_MCLK" /*!< Identifier name */
466
467/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
468#define BOARD_INITCSI_CSI_VSYNC_PERIPHERAL CSI /*!< Device name: CSI */
469#define BOARD_INITCSI_CSI_VSYNC_SIGNAL csi_vsync /*!< CSI signal: csi_vsync */
470#define BOARD_INITCSI_CSI_VSYNC_PIN_NAME GPIO_AD_B1_06 /*!< Pin name */
471#define BOARD_INITCSI_CSI_VSYNC_LABEL "CSI_VSYNC/J35[18]/J22[2]/UART_TX" /*!< Label */
472#define BOARD_INITCSI_CSI_VSYNC_NAME "CSI_VSYNC" /*!< Identifier name */
473
474/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
475#define BOARD_INITCSI_CSI_HSYNC_PERIPHERAL CSI /*!< Device name: CSI */
476#define BOARD_INITCSI_CSI_HSYNC_SIGNAL csi_hsync /*!< CSI signal: csi_hsync */
477#define BOARD_INITCSI_CSI_HSYNC_PIN_NAME GPIO_AD_B1_07 /*!< Pin name */
478#define BOARD_INITCSI_CSI_HSYNC_LABEL "CSI_HSYNC/J35[16]/J22[1]/UART_RX" /*!< Label */
479#define BOARD_INITCSI_CSI_HSYNC_NAME "CSI_HSYNC" /*!< Identifier name */
480
481/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
482#define BOARD_INITCSI_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Device name: LPI2C1 */
483#define BOARD_INITCSI_CSI_I2C_SCL_SIGNAL SCL /*!< LPI2C1 signal: SCL */
484#define BOARD_INITCSI_CSI_I2C_SCL_PIN_NAME GPIO_AD_B1_00 /*!< Pin name */
485#define BOARD_INITCSI_CSI_I2C_SCL_LABEL "I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4]" /*!< Label */
486#define BOARD_INITCSI_CSI_I2C_SCL_NAME "CSI_I2C_SCL" /*!< Identifier name */
487
488/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
489#define BOARD_INITCSI_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Device name: LPI2C1 */
490#define BOARD_INITCSI_CSI_I2C_SDA_SIGNAL SDA /*!< LPI2C1 signal: SDA */
491#define BOARD_INITCSI_CSI_I2C_SDA_PIN_NAME GPIO_AD_B1_01 /*!< Pin name */
492#define BOARD_INITCSI_CSI_I2C_SDA_LABEL "I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6]" /*!< Label */
493#define BOARD_INITCSI_CSI_I2C_SDA_NAME "CSI_I2C_SDA" /*!< Identifier name */
494
495/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
496#define BOARD_INITCSI_CSI_PWDN_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
497#define BOARD_INITCSI_CSI_PWDN_PORT GPIO1 /*!< PORT device name: GPIO1 */
498#define BOARD_INITCSI_CSI_PWDN_GPIO_PIN 4U /*!< GPIO1 pin index: 4 */
499#define BOARD_INITCSI_CSI_PWDN_PIN_NAME GPIO_AD_B0_04 /*!< Pin name */
500#define BOARD_INITCSI_CSI_PWDN_LABEL "CSI_PWDN/J35[17]/BOOT_MODE[0]" /*!< Label */
501#define BOARD_INITCSI_CSI_PWDN_NAME "CSI_PWDN" /*!< Identifier name */
502
503
504/*!
505 * @brief Configures pin routing and optionally pin electrical features.
506 *
507 */
508void BOARD_InitCSI(void);
509
510/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
511#define BOARD_INITLCD_LCDIF_D0_PERIPHERAL LCDIF /*!< Device name: LCDIF */
512#define BOARD_INITLCD_LCDIF_D0_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
513#define BOARD_INITLCD_LCDIF_D0_CHANNEL 0U /*!< LCDIF lcdif_data channel: 00 */
514#define BOARD_INITLCD_LCDIF_D0_PIN_NAME GPIO_B0_04 /*!< Pin name */
515#define BOARD_INITLCD_LCDIF_D0_LABEL "LCDIF_D0/BT_CFG[0]" /*!< Label */
516#define BOARD_INITLCD_LCDIF_D0_NAME "LCDIF_D0" /*!< Identifier name */
517
518/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
519#define BOARD_INITLCD_LCDIF_D1_PERIPHERAL LCDIF /*!< Device name: LCDIF */
520#define BOARD_INITLCD_LCDIF_D1_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
521#define BOARD_INITLCD_LCDIF_D1_CHANNEL 1U /*!< LCDIF lcdif_data channel: 01 */
522#define BOARD_INITLCD_LCDIF_D1_PIN_NAME GPIO_B0_05 /*!< Pin name */
523#define BOARD_INITLCD_LCDIF_D1_LABEL "LCDIF_D1/BT_CFG[1]" /*!< Label */
524#define BOARD_INITLCD_LCDIF_D1_NAME "LCDIF_D1" /*!< Identifier name */
525
526/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
527#define BOARD_INITLCD_LCDIF_D2_PERIPHERAL LCDIF /*!< Device name: LCDIF */
528#define BOARD_INITLCD_LCDIF_D2_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
529#define BOARD_INITLCD_LCDIF_D2_CHANNEL 2U /*!< LCDIF lcdif_data channel: 02 */
530#define BOARD_INITLCD_LCDIF_D2_PIN_NAME GPIO_B0_06 /*!< Pin name */
531#define BOARD_INITLCD_LCDIF_D2_LABEL "LCDIF_D2/BT_CFG[2]" /*!< Label */
532#define BOARD_INITLCD_LCDIF_D2_NAME "LCDIF_D2" /*!< Identifier name */
533
534/* GPIO_B0_00 (coord D7), LCDIF_CLK */
535#define BOARD_INITLCD_LCDIF_CLK_PERIPHERAL LCDIF /*!< Device name: LCDIF */
536#define BOARD_INITLCD_LCDIF_CLK_SIGNAL lcdif_clk /*!< LCDIF signal: lcdif_clk */
537#define BOARD_INITLCD_LCDIF_CLK_PIN_NAME GPIO_B0_00 /*!< Pin name */
538#define BOARD_INITLCD_LCDIF_CLK_LABEL "LCDIF_CLK" /*!< Label */
539#define BOARD_INITLCD_LCDIF_CLK_NAME "LCDIF_CLK" /*!< Identifier name */
540
541/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
542#define BOARD_INITLCD_LCDIF_D3_PERIPHERAL LCDIF /*!< Device name: LCDIF */
543#define BOARD_INITLCD_LCDIF_D3_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
544#define BOARD_INITLCD_LCDIF_D3_CHANNEL 3U /*!< LCDIF lcdif_data channel: 03 */
545#define BOARD_INITLCD_LCDIF_D3_PIN_NAME GPIO_B0_07 /*!< Pin name */
546#define BOARD_INITLCD_LCDIF_D3_LABEL "LCDIF_D3/BT_CFG[3]" /*!< Label */
547#define BOARD_INITLCD_LCDIF_D3_NAME "LCDIF_D3" /*!< Identifier name */
548
549/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
550#define BOARD_INITLCD_LCDIF_D4_PERIPHERAL LCDIF /*!< Device name: LCDIF */
551#define BOARD_INITLCD_LCDIF_D4_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
552#define BOARD_INITLCD_LCDIF_D4_CHANNEL 4U /*!< LCDIF lcdif_data channel: 04 */
553#define BOARD_INITLCD_LCDIF_D4_PIN_NAME GPIO_B0_08 /*!< Pin name */
554#define BOARD_INITLCD_LCDIF_D4_LABEL "LCDIF_D4/BT_CFG[4]" /*!< Label */
555#define BOARD_INITLCD_LCDIF_D4_NAME "LCDIF_D4" /*!< Identifier name */
556
557/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
558#define BOARD_INITLCD_LCDIF_D5_PERIPHERAL LCDIF /*!< Device name: LCDIF */
559#define BOARD_INITLCD_LCDIF_D5_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
560#define BOARD_INITLCD_LCDIF_D5_CHANNEL 5U /*!< LCDIF lcdif_data channel: 05 */
561#define BOARD_INITLCD_LCDIF_D5_PIN_NAME GPIO_B0_09 /*!< Pin name */
562#define BOARD_INITLCD_LCDIF_D5_LABEL "LCDIF_D5/BT_CFG[5]" /*!< Label */
563#define BOARD_INITLCD_LCDIF_D5_NAME "LCDIF_D5" /*!< Identifier name */
564
565/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
566#define BOARD_INITLCD_LCDIF_D6_PERIPHERAL LCDIF /*!< Device name: LCDIF */
567#define BOARD_INITLCD_LCDIF_D6_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
568#define BOARD_INITLCD_LCDIF_D6_CHANNEL 6U /*!< LCDIF lcdif_data channel: 06 */
569#define BOARD_INITLCD_LCDIF_D6_PIN_NAME GPIO_B0_10 /*!< Pin name */
570#define BOARD_INITLCD_LCDIF_D6_LABEL "LCDIF_D6/BT_CFG[6]" /*!< Label */
571#define BOARD_INITLCD_LCDIF_D6_NAME "LCDIF_D6" /*!< Identifier name */
572
573/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
574#define BOARD_INITLCD_LCDIF_D7_PERIPHERAL LCDIF /*!< Device name: LCDIF */
575#define BOARD_INITLCD_LCDIF_D7_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
576#define BOARD_INITLCD_LCDIF_D7_CHANNEL 7U /*!< LCDIF lcdif_data channel: 07 */
577#define BOARD_INITLCD_LCDIF_D7_PIN_NAME GPIO_B0_11 /*!< Pin name */
578#define BOARD_INITLCD_LCDIF_D7_LABEL "LCDIF_D7/BT_CFG[7]" /*!< Label */
579#define BOARD_INITLCD_LCDIF_D7_NAME "LCDIF_D7" /*!< Identifier name */
580
581/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
582#define BOARD_INITLCD_LCDIF_D8_PERIPHERAL LCDIF /*!< Device name: LCDIF */
583#define BOARD_INITLCD_LCDIF_D8_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
584#define BOARD_INITLCD_LCDIF_D8_CHANNEL 8U /*!< LCDIF lcdif_data channel: 08 */
585#define BOARD_INITLCD_LCDIF_D8_PIN_NAME GPIO_B0_12 /*!< Pin name */
586#define BOARD_INITLCD_LCDIF_D8_LABEL "LCDIF_D8/BT_CFG[8]" /*!< Label */
587#define BOARD_INITLCD_LCDIF_D8_NAME "LCDIF_D8" /*!< Identifier name */
588
589/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
590#define BOARD_INITLCD_LCDIF_D9_PERIPHERAL LCDIF /*!< Device name: LCDIF */
591#define BOARD_INITLCD_LCDIF_D9_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
592#define BOARD_INITLCD_LCDIF_D9_CHANNEL 9U /*!< LCDIF lcdif_data channel: 09 */
593#define BOARD_INITLCD_LCDIF_D9_PIN_NAME GPIO_B0_13 /*!< Pin name */
594#define BOARD_INITLCD_LCDIF_D9_LABEL "LCDIF_D9/BT_CFG[9]" /*!< Label */
595#define BOARD_INITLCD_LCDIF_D9_NAME "LCDIF_D9" /*!< Identifier name */
596
597/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
598#define BOARD_INITLCD_LCDIF_D10_PERIPHERAL LCDIF /*!< Device name: LCDIF */
599#define BOARD_INITLCD_LCDIF_D10_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
600#define BOARD_INITLCD_LCDIF_D10_CHANNEL 10U /*!< LCDIF lcdif_data channel: 10 */
601#define BOARD_INITLCD_LCDIF_D10_PIN_NAME GPIO_B0_14 /*!< Pin name */
602#define BOARD_INITLCD_LCDIF_D10_LABEL "LCDIF_D10/BT_CFG[10]" /*!< Label */
603#define BOARD_INITLCD_LCDIF_D10_NAME "LCDIF_D10" /*!< Identifier name */
604
605/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
606#define BOARD_INITLCD_LCDIF_D11_PERIPHERAL LCDIF /*!< Device name: LCDIF */
607#define BOARD_INITLCD_LCDIF_D11_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
608#define BOARD_INITLCD_LCDIF_D11_CHANNEL 11U /*!< LCDIF lcdif_data channel: 11 */
609#define BOARD_INITLCD_LCDIF_D11_PIN_NAME GPIO_B0_15 /*!< Pin name */
610#define BOARD_INITLCD_LCDIF_D11_LABEL "LCDIF_D11/BT_CFG[11]" /*!< Label */
611#define BOARD_INITLCD_LCDIF_D11_NAME "LCDIF_D11" /*!< Identifier name */
612
613/* GPIO_B1_00 (coord A11), LCDIF_D12 */
614#define BOARD_INITLCD_LCDIF_D12_PERIPHERAL LCDIF /*!< Device name: LCDIF */
615#define BOARD_INITLCD_LCDIF_D12_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
616#define BOARD_INITLCD_LCDIF_D12_CHANNEL 12U /*!< LCDIF lcdif_data channel: 12 */
617#define BOARD_INITLCD_LCDIF_D12_PIN_NAME GPIO_B1_00 /*!< Pin name */
618#define BOARD_INITLCD_LCDIF_D12_LABEL "LCDIF_D12" /*!< Label */
619#define BOARD_INITLCD_LCDIF_D12_NAME "LCDIF_D12" /*!< Identifier name */
620
621/* GPIO_B1_01 (coord B11), LCDIF_D13 */
622#define BOARD_INITLCD_LCDIF_D13_PERIPHERAL LCDIF /*!< Device name: LCDIF */
623#define BOARD_INITLCD_LCDIF_D13_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
624#define BOARD_INITLCD_LCDIF_D13_CHANNEL 13U /*!< LCDIF lcdif_data channel: 13 */
625#define BOARD_INITLCD_LCDIF_D13_PIN_NAME GPIO_B1_01 /*!< Pin name */
626#define BOARD_INITLCD_LCDIF_D13_LABEL "LCDIF_D13" /*!< Label */
627#define BOARD_INITLCD_LCDIF_D13_NAME "LCDIF_D13" /*!< Identifier name */
628
629/* GPIO_B1_02 (coord C11), LCDIF_D14 */
630#define BOARD_INITLCD_LCDIF_D14_PERIPHERAL LCDIF /*!< Device name: LCDIF */
631#define BOARD_INITLCD_LCDIF_D14_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
632#define BOARD_INITLCD_LCDIF_D14_CHANNEL 14U /*!< LCDIF lcdif_data channel: 14 */
633#define BOARD_INITLCD_LCDIF_D14_PIN_NAME GPIO_B1_02 /*!< Pin name */
634#define BOARD_INITLCD_LCDIF_D14_LABEL "LCDIF_D14" /*!< Label */
635#define BOARD_INITLCD_LCDIF_D14_NAME "LCDIF_D14" /*!< Identifier name */
636
637/* GPIO_B1_03 (coord D11), LCDIF_D15 */
638#define BOARD_INITLCD_LCDIF_D15_PERIPHERAL LCDIF /*!< Device name: LCDIF */
639#define BOARD_INITLCD_LCDIF_D15_SIGNAL lcdif_data /*!< LCDIF signal: lcdif_data */
640#define BOARD_INITLCD_LCDIF_D15_CHANNEL 15U /*!< LCDIF lcdif_data channel: 15 */
641#define BOARD_INITLCD_LCDIF_D15_PIN_NAME GPIO_B1_03 /*!< Pin name */
642#define BOARD_INITLCD_LCDIF_D15_LABEL "LCDIF_D15" /*!< Label */
643#define BOARD_INITLCD_LCDIF_D15_NAME "LCDIF_D15" /*!< Identifier name */
644
645/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
646#define BOARD_INITLCD_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Device name: LCDIF */
647#define BOARD_INITLCD_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< LCDIF signal: lcdif_enable */
648#define BOARD_INITLCD_LCDIF_ENABLE_PIN_NAME GPIO_B0_01 /*!< Pin name */
649#define BOARD_INITLCD_LCDIF_ENABLE_LABEL "LCDIF_ENABLE" /*!< Label */
650#define BOARD_INITLCD_LCDIF_ENABLE_NAME "LCDIF_ENABLE" /*!< Identifier name */
651
652/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
653#define BOARD_INITLCD_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Device name: LCDIF */
654#define BOARD_INITLCD_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< LCDIF signal: lcdif_hsync */
655#define BOARD_INITLCD_LCDIF_HSYNC_PIN_NAME GPIO_B0_02 /*!< Pin name */
656#define BOARD_INITLCD_LCDIF_HSYNC_LABEL "LCDIF_HSYNC" /*!< Label */
657#define BOARD_INITLCD_LCDIF_HSYNC_NAME "LCDIF_HSYNC" /*!< Identifier name */
658
659/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
660#define BOARD_INITLCD_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Device name: LCDIF */
661#define BOARD_INITLCD_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< LCDIF signal: lcdif_vsync */
662#define BOARD_INITLCD_LCDIF_VSYNC_PIN_NAME GPIO_B0_03 /*!< Pin name */
663#define BOARD_INITLCD_LCDIF_VSYNC_LABEL "LCDIF_VSYNC" /*!< Label */
664#define BOARD_INITLCD_LCDIF_VSYNC_NAME "LCDIF_VSYNC" /*!< Identifier name */
665
666/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
667#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO device name: GPIO2 */
668#define BOARD_INITLCD_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT device name: GPIO2 */
669#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO2 pin index: 31 */
670#define BOARD_INITLCD_BACKLIGHT_CTL_PIN_NAME GPIO_B1_15 /*!< Pin name */
671#define BOARD_INITLCD_BACKLIGHT_CTL_LABEL "USB_HOST_PWR/BACKLIGHT_CTL" /*!< Label */
672#define BOARD_INITLCD_BACKLIGHT_CTL_NAME "BACKLIGHT_CTL" /*!< Identifier name */
673
674
675/*!
676 * @brief Configures pin routing and optionally pin electrical features.
677 *
678 */
679void BOARD_InitLCD(void);
680
681/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
682#define BOARD_INITCAN_CAN2_TX_PERIPHERAL CAN2 /*!< Device name: CAN2 */
683#define BOARD_INITCAN_CAN2_TX_SIGNAL TX /*!< CAN2 signal: TX */
684#define BOARD_INITCAN_CAN2_TX_PIN_NAME GPIO_AD_B0_14 /*!< Pin name */
685#define BOARD_INITCAN_CAN2_TX_LABEL "CAN2_TX/U12[1]" /*!< Label */
686#define BOARD_INITCAN_CAN2_TX_NAME "CAN2_TX" /*!< Identifier name */
687
688/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
689#define BOARD_INITCAN_CAN2_RX_PERIPHERAL CAN2 /*!< Device name: CAN2 */
690#define BOARD_INITCAN_CAN2_RX_SIGNAL RX /*!< CAN2 signal: RX */
691#define BOARD_INITCAN_CAN2_RX_PIN_NAME GPIO_AD_B0_15 /*!< Pin name */
692#define BOARD_INITCAN_CAN2_RX_LABEL "CAN2_RX/U12[4]" /*!< Label */
693#define BOARD_INITCAN_CAN2_RX_NAME "CAN2_RX" /*!< Identifier name */
694
695
696/*!
697 * @brief Configures pin routing and optionally pin electrical features.
698 *
699 */
700void BOARD_InitCAN(void);
701
702/* GPIO_EMC_40 (coord A7), ENET_MDC */
703#define BOARD_INITENET_ENET_MDC_PERIPHERAL ENET /*!< Device name: ENET */
704#define BOARD_INITENET_ENET_MDC_SIGNAL enet_mdc /*!< ENET signal: enet_mdc */
705#define BOARD_INITENET_ENET_MDC_PIN_NAME GPIO_EMC_40 /*!< Pin name */
706#define BOARD_INITENET_ENET_MDC_LABEL "ENET_MDC" /*!< Label */
707#define BOARD_INITENET_ENET_MDC_NAME "ENET_MDC" /*!< Identifier name */
708
709/* GPIO_EMC_41 (coord C7), ENET_MDIO */
710#define BOARD_INITENET_ENET_MDIO_PERIPHERAL ENET /*!< Device name: ENET */
711#define BOARD_INITENET_ENET_MDIO_SIGNAL enet_mdio /*!< ENET signal: enet_mdio */
712#define BOARD_INITENET_ENET_MDIO_PIN_NAME GPIO_EMC_41 /*!< Pin name */
713#define BOARD_INITENET_ENET_MDIO_LABEL "ENET_MDIO" /*!< Label */
714#define BOARD_INITENET_ENET_MDIO_NAME "ENET_MDIO" /*!< Identifier name */
715
716/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
717#define BOARD_INITENET_ENET_TX_CLK_PERIPHERAL ENET /*!< Device name: ENET */
718#define BOARD_INITENET_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< ENET signal: enet_ref_clk */
719#define BOARD_INITENET_ENET_TX_CLK_PIN_NAME GPIO_B1_10 /*!< Pin name */
720#define BOARD_INITENET_ENET_TX_CLK_LABEL "ENET_TX_CLK" /*!< Label */
721#define BOARD_INITENET_ENET_TX_CLK_NAME "ENET_TX_CLK" /*!< Identifier name */
722
723/* GPIO_B1_04 (coord E12), ENET_RXD0 */
724#define BOARD_INITENET_ENET_RXD0_PERIPHERAL ENET /*!< Device name: ENET */
725#define BOARD_INITENET_ENET_RXD0_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
726#define BOARD_INITENET_ENET_RXD0_CHANNEL 0U /*!< ENET enet_rx_data channel: 0 */
727#define BOARD_INITENET_ENET_RXD0_PIN_NAME GPIO_B1_04 /*!< Pin name */
728#define BOARD_INITENET_ENET_RXD0_LABEL "ENET_RXD0" /*!< Label */
729#define BOARD_INITENET_ENET_RXD0_NAME "ENET_RXD0" /*!< Identifier name */
730
731/* GPIO_B1_05 (coord D12), ENET_RXD1 */
732#define BOARD_INITENET_ENET_RXD1_PERIPHERAL ENET /*!< Device name: ENET */
733#define BOARD_INITENET_ENET_RXD1_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
734#define BOARD_INITENET_ENET_RXD1_CHANNEL 1U /*!< ENET enet_rx_data channel: 1 */
735#define BOARD_INITENET_ENET_RXD1_PIN_NAME GPIO_B1_05 /*!< Pin name */
736#define BOARD_INITENET_ENET_RXD1_LABEL "ENET_RXD1" /*!< Label */
737#define BOARD_INITENET_ENET_RXD1_NAME "ENET_RXD1" /*!< Identifier name */
738
739/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
740#define BOARD_INITENET_ENET_CRS_DV_PERIPHERAL ENET /*!< Device name: ENET */
741#define BOARD_INITENET_ENET_CRS_DV_SIGNAL enet_rx_en /*!< ENET signal: enet_rx_en */
742#define BOARD_INITENET_ENET_CRS_DV_PIN_NAME GPIO_B1_06 /*!< Pin name */
743#define BOARD_INITENET_ENET_CRS_DV_LABEL "ENET_CRS_DV" /*!< Label */
744#define BOARD_INITENET_ENET_CRS_DV_NAME "ENET_CRS_DV" /*!< Identifier name */
745
746/* GPIO_B1_11 (coord C13), ENET_RXER */
747#define BOARD_INITENET_ENET_RXER_PERIPHERAL ENET /*!< Device name: ENET */
748#define BOARD_INITENET_ENET_RXER_SIGNAL enet_rx_er /*!< ENET signal: enet_rx_er */
749#define BOARD_INITENET_ENET_RXER_PIN_NAME GPIO_B1_11 /*!< Pin name */
750#define BOARD_INITENET_ENET_RXER_LABEL "ENET_RXER" /*!< Label */
751#define BOARD_INITENET_ENET_RXER_NAME "ENET_RXER" /*!< Identifier name */
752
753/* GPIO_B1_07 (coord B12), ENET_TXD0 */
754#define BOARD_INITENET_ENET_TXD0_PERIPHERAL ENET /*!< Device name: ENET */
755#define BOARD_INITENET_ENET_TXD0_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
756#define BOARD_INITENET_ENET_TXD0_CHANNEL 0U /*!< ENET enet_tx_data channel: 0 */
757#define BOARD_INITENET_ENET_TXD0_PIN_NAME GPIO_B1_07 /*!< Pin name */
758#define BOARD_INITENET_ENET_TXD0_LABEL "ENET_TXD0" /*!< Label */
759#define BOARD_INITENET_ENET_TXD0_NAME "ENET_TXD0" /*!< Identifier name */
760
761/* GPIO_B1_08 (coord A12), ENET_TXD1 */
762#define BOARD_INITENET_ENET_TXD1_PERIPHERAL ENET /*!< Device name: ENET */
763#define BOARD_INITENET_ENET_TXD1_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
764#define BOARD_INITENET_ENET_TXD1_CHANNEL 1U /*!< ENET enet_tx_data channel: 1 */
765#define BOARD_INITENET_ENET_TXD1_PIN_NAME GPIO_B1_08 /*!< Pin name */
766#define BOARD_INITENET_ENET_TXD1_LABEL "ENET_TXD1" /*!< Label */
767#define BOARD_INITENET_ENET_TXD1_NAME "ENET_TXD1" /*!< Identifier name */
768
769/* GPIO_B1_09 (coord A13), ENET_TXEN */
770#define BOARD_INITENET_ENET_TXEN_PERIPHERAL ENET /*!< Device name: ENET */
771#define BOARD_INITENET_ENET_TXEN_SIGNAL enet_tx_en /*!< ENET signal: enet_tx_en */
772#define BOARD_INITENET_ENET_TXEN_PIN_NAME GPIO_B1_09 /*!< Pin name */
773#define BOARD_INITENET_ENET_TXEN_LABEL "ENET_TXEN" /*!< Label */
774#define BOARD_INITENET_ENET_TXEN_NAME "ENET_TXEN" /*!< Identifier name */
775
776
777/*!
778 * @brief Configures pin routing and optionally pin electrical features.
779 *
780 */
781void BOARD_InitENET(void);
782
783/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
784#define BOARD_INITUSDHC_SD1_D3_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
785#define BOARD_INITUSDHC_SD1_D3_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
786#define BOARD_INITUSDHC_SD1_D3_CHANNEL 3U /*!< USDHC1 usdhc_data channel: 3 */
787#define BOARD_INITUSDHC_SD1_D3_PIN_NAME GPIO_SD_B0_05 /*!< Pin name */
788#define BOARD_INITUSDHC_SD1_D3_LABEL "SD1_D3" /*!< Label */
789#define BOARD_INITUSDHC_SD1_D3_NAME "SD1_D3" /*!< Identifier name */
790
791/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
792#define BOARD_INITUSDHC_SD1_D2_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
793#define BOARD_INITUSDHC_SD1_D2_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
794#define BOARD_INITUSDHC_SD1_D2_CHANNEL 2U /*!< USDHC1 usdhc_data channel: 2 */
795#define BOARD_INITUSDHC_SD1_D2_PIN_NAME GPIO_SD_B0_04 /*!< Pin name */
796#define BOARD_INITUSDHC_SD1_D2_LABEL "SD1_D2" /*!< Label */
797#define BOARD_INITUSDHC_SD1_D2_NAME "SD1_D2" /*!< Identifier name */
798
799/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
800#define BOARD_INITUSDHC_SD1_D1_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
801#define BOARD_INITUSDHC_SD1_D1_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
802#define BOARD_INITUSDHC_SD1_D1_CHANNEL 1U /*!< USDHC1 usdhc_data channel: 1 */
803#define BOARD_INITUSDHC_SD1_D1_PIN_NAME GPIO_SD_B0_03 /*!< Pin name */
804#define BOARD_INITUSDHC_SD1_D1_LABEL "SD1_D1/J24[5]/SPI_MISO" /*!< Label */
805#define BOARD_INITUSDHC_SD1_D1_NAME "SD1_D1" /*!< Identifier name */
806
807/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
808#define BOARD_INITUSDHC_SD1_D0_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
809#define BOARD_INITUSDHC_SD1_D0_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
810#define BOARD_INITUSDHC_SD1_D0_CHANNEL 0U /*!< USDHC1 usdhc_data channel: 0 */
811#define BOARD_INITUSDHC_SD1_D0_PIN_NAME GPIO_SD_B0_02 /*!< Pin name */
812#define BOARD_INITUSDHC_SD1_D0_LABEL "SD1_D0/J24[4]/SPI_MOSI/PWM" /*!< Label */
813#define BOARD_INITUSDHC_SD1_D0_NAME "SD1_D0" /*!< Identifier name */
814
815/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
816#define BOARD_INITUSDHC_SD1_CMD_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
817#define BOARD_INITUSDHC_SD1_CMD_SIGNAL usdhc_cmd /*!< USDHC1 signal: usdhc_cmd */
818#define BOARD_INITUSDHC_SD1_CMD_PIN_NAME GPIO_SD_B0_00 /*!< Pin name */
819#define BOARD_INITUSDHC_SD1_CMD_LABEL "SD1_CMD/J24[6]" /*!< Label */
820#define BOARD_INITUSDHC_SD1_CMD_NAME "SD1_CMD" /*!< Identifier name */
821
822/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
823#define BOARD_INITUSDHC_SD1_CLK_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
824#define BOARD_INITUSDHC_SD1_CLK_SIGNAL usdhc_clk /*!< USDHC1 signal: usdhc_clk */
825#define BOARD_INITUSDHC_SD1_CLK_PIN_NAME GPIO_SD_B0_01 /*!< Pin name */
826#define BOARD_INITUSDHC_SD1_CLK_LABEL "SD1_CLK/J24[3]" /*!< Label */
827#define BOARD_INITUSDHC_SD1_CLK_NAME "SD1_CLK" /*!< Identifier name */
828
829
830/*!
831 * @brief Configures pin routing and optionally pin electrical features.
832 *
833 */
834void BOARD_InitUSDHC(void);
835
836/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
837#define BOARD_INITHYPERFLASH_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
838#define BOARD_INITHYPERFLASH_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */
839#define BOARD_INITHYPERFLASH_FlexSPI_CLK_PIN_NAME GPIO_SD_B1_07 /*!< Pin name */
840#define BOARD_INITHYPERFLASH_FlexSPI_CLK_LABEL "FlexSPI_CLK" /*!< Label */
841#define BOARD_INITHYPERFLASH_FlexSPI_CLK_NAME "FlexSPI_CLK" /*!< Identifier name */
842
843/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
844#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
845#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */
846#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_PIN_NAME GPIO_SD_B1_10 /*!< Pin name */
847#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_LABEL "FlexSPI_D2_A" /*!< Label */
848#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_NAME "FlexSPI_D2_A" /*!< Identifier name */
849
850/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
851#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
852#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */
853#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_PIN_NAME GPIO_SD_B1_08 /*!< Pin name */
854#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_LABEL "FlexSPI_D0_A" /*!< Label */
855#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_NAME "FlexSPI_D0_A" /*!< Identifier name */
856
857/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
858#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
859#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */
860#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_PIN_NAME GPIO_SD_B1_09 /*!< Pin name */
861#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_LABEL "FlexSPI_D1_A" /*!< Label */
862#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_NAME "FlexSPI_D1_A" /*!< Identifier name */
863
864/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
865#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
866#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< FLEXSPI signal: FLEXSPI_B_DATA3 */
867#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_PIN_NAME GPIO_SD_B1_00 /*!< Pin name */
868#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_LABEL "FlexSPI_D3_B" /*!< Label */
869#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_NAME "FlexSPI_D3_B" /*!< Identifier name */
870
871/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
872#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
873#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< FLEXSPI signal: FLEXSPI_B_DATA2 */
874#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_PIN_NAME GPIO_SD_B1_01 /*!< Pin name */
875#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_LABEL "FlexSPI_D2_B" /*!< Label */
876#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_NAME "FlexSPI_D2_B" /*!< Identifier name */
877
878/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */
879#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
880#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< FLEXSPI signal: FLEXSPI_B_DATA1 */
881#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_PIN_NAME GPIO_SD_B1_02 /*!< Pin name */
882#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_LABEL "FlexSPI_D1_B" /*!< Label */
883#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_NAME "FlexSPI_D1_B" /*!< Identifier name */
884
885/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */
886#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
887#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< FLEXSPI signal: FLEXSPI_B_DATA0 */
888#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_PIN_NAME GPIO_SD_B1_03 /*!< Pin name */
889#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_LABEL "FlexSPI_D0_B" /*!< Label */
890#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_NAME "FlexSPI_D0_B" /*!< Identifier name */
891
892/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */
893#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
894#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< FLEXSPI signal: FLEXSPI_B_SCLK */
895#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PIN_NAME GPIO_SD_B1_04 /*!< Pin name */
896#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_LABEL "FlexSPI_CLK_B" /*!< Label */
897#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_NAME "FlexSPI_CLK_B" /*!< Identifier name */
898
899/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
900#define BOARD_INITHYPERFLASH_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
901#define BOARD_INITHYPERFLASH_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */
902#define BOARD_INITHYPERFLASH_FlexSPI_SS0_PIN_NAME GPIO_SD_B1_06 /*!< Pin name */
903#define BOARD_INITHYPERFLASH_FlexSPI_SS0_LABEL "FlexSPI_SS0" /*!< Label */
904#define BOARD_INITHYPERFLASH_FlexSPI_SS0_NAME "FlexSPI_SS0" /*!< Identifier name */
905
906/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
907#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
908#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */
909#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_PIN_NAME GPIO_SD_B1_11 /*!< Pin name */
910#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_LABEL "FlexSPI_D3_A" /*!< Label */
911#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_NAME "FlexSPI_D3_A" /*!< Identifier name */
912
913/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
914#define BOARD_INITHYPERFLASH_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
915#define BOARD_INITHYPERFLASH_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< FLEXSPI signal: FLEXSPI_A_DQS */
916#define BOARD_INITHYPERFLASH_FlexSPI_DQS_PIN_NAME GPIO_SD_B1_05 /*!< Pin name */
917#define BOARD_INITHYPERFLASH_FlexSPI_DQS_LABEL "FlexSPI_DQS" /*!< Label */
918#define BOARD_INITHYPERFLASH_FlexSPI_DQS_NAME "FlexSPI_DQS" /*!< Identifier name */
919
920
921/*!
922 * @brief Configures pin routing and optionally pin electrical features.
923 *
924 */
925void BOARD_InitHyperFlash(void);
926
927#if defined(__cplusplus)
928}
929#endif
930
931/*!
932 * @}
933 */
934#endif /* _PIN_MUX_H_ */
935
936/***********************************************************************************************************************
937 * EOF
938 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/driver_xip_board.cmake b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/driver_xip_board.cmake
new file mode 100644
index 000000000..b24e23ac4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/driver_xip_board.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_XIP_BOARD_INCLUDED)
2
3 set(DRIVER_XIP_BOARD_INCLUDED true CACHE BOOL "driver_xip_board component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1064_flexspi_nor_config.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.c
new file mode 100644
index 000000000..028f63e58
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "evkmimxrt1064_flexspi_nor_config.h"
9
10/* Component ID definition, used by tools. */
11#ifndef FSL_COMPONENT_ID
12#define FSL_COMPONENT_ID "platform.drivers.xip_board"
13#endif
14
15/*******************************************************************************
16 * Code
17 ******************************************************************************/
18#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
19#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
20__attribute__((section(".boot_hdr.conf"), used))
21#elif defined(__ICCARM__)
22#pragma location = ".boot_hdr.conf"
23#endif
24
25const flexspi_nor_config_t qspiflash_config = {
26 .memConfig =
27 {
28 .tag = FLEXSPI_CFG_BLK_TAG,
29 .version = FLEXSPI_CFG_BLK_VERSION,
30 .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
31 .csHoldTime = 3u,
32 .csSetupTime = 3u,
33 .sflashPadType = kSerialFlash_4Pads,
34 .serialClkFreq = kFlexSpiSerialClk_100MHz,
35 .sflashA1Size = 4u * 1024u * 1024u,
36 .lookupTable =
37 {
38 // Read LUTs
39 FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
40 FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
41 },
42 },
43 .pageSize = 256u,
44 .sectorSize = 4u * 1024u,
45 .blockSize = 64u * 1024u,
46 .isUniformBlockSize = false,
47};
48#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.h
new file mode 100644
index 000000000..cac0dfacc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1064/xip/evkmimxrt1064_flexspi_nor_config.h
@@ -0,0 +1,268 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
9#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
10
11#include <stdint.h>
12#include <stdbool.h>
13#include "fsl_common.h"
14
15/*! @name Driver version */
16/*@{*/
17/*! @brief XIP_BOARD driver version 2.0.1. */
18#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
19/*@}*/
20
21/* FLEXSPI memory config block related defintions */
22#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
23#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
24#define FLEXSPI_CFG_BLK_SIZE (512)
25
26/* FLEXSPI Feature related definitions */
27#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
28
29/* Lookup table related defintions */
30#define CMD_INDEX_READ 0
31#define CMD_INDEX_READSTATUS 1
32#define CMD_INDEX_WRITEENABLE 2
33#define CMD_INDEX_WRITE 4
34
35#define CMD_LUT_SEQ_IDX_READ 0
36#define CMD_LUT_SEQ_IDX_READSTATUS 1
37#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
38#define CMD_LUT_SEQ_IDX_WRITE 9
39
40#define CMD_SDR 0x01
41#define CMD_DDR 0x21
42#define RADDR_SDR 0x02
43#define RADDR_DDR 0x22
44#define CADDR_SDR 0x03
45#define CADDR_DDR 0x23
46#define MODE1_SDR 0x04
47#define MODE1_DDR 0x24
48#define MODE2_SDR 0x05
49#define MODE2_DDR 0x25
50#define MODE4_SDR 0x06
51#define MODE4_DDR 0x26
52#define MODE8_SDR 0x07
53#define MODE8_DDR 0x27
54#define WRITE_SDR 0x08
55#define WRITE_DDR 0x28
56#define READ_SDR 0x09
57#define READ_DDR 0x29
58#define LEARN_SDR 0x0A
59#define LEARN_DDR 0x2A
60#define DATSZ_SDR 0x0B
61#define DATSZ_DDR 0x2B
62#define DUMMY_SDR 0x0C
63#define DUMMY_DDR 0x2C
64#define DUMMY_RWDS_SDR 0x0D
65#define DUMMY_RWDS_DDR 0x2D
66#define JMP_ON_CS 0x1F
67#define STOP 0
68
69#define FLEXSPI_1PAD 0
70#define FLEXSPI_2PAD 1
71#define FLEXSPI_4PAD 2
72#define FLEXSPI_8PAD 3
73
74#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
75 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
76 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
77
78//!@brief Definitions for FlexSPI Serial Clock Frequency
79typedef enum _FlexSpiSerialClockFreq
80{
81 kFlexSpiSerialClk_30MHz = 1,
82 kFlexSpiSerialClk_50MHz = 2,
83 kFlexSpiSerialClk_60MHz = 3,
84 kFlexSpiSerialClk_75MHz = 4,
85 kFlexSpiSerialClk_80MHz = 5,
86 kFlexSpiSerialClk_100MHz = 6,
87 kFlexSpiSerialClk_120MHz = 7,
88 kFlexSpiSerialClk_133MHz = 8,
89 kFlexSpiSerialClk_166MHz = 9,
90} flexspi_serial_clk_freq_t;
91
92//!@brief FlexSPI clock configuration type
93enum
94{
95 kFlexSpiClk_SDR, //!< Clock configure for SDR mode
96 kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
97};
98
99//!@brief FlexSPI Read Sample Clock Source definition
100typedef enum _FlashReadSampleClkSource
101{
102 kFlexSPIReadSampleClk_LoopbackInternally = 0,
103 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
104 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
105 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
106} flexspi_read_sample_clk_t;
107
108//!@brief Misc feature bit definitions
109enum
110{
111 kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
112 kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
113 kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
114 kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
115 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
116 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
117 kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
118};
119
120//!@brief Flash Type Definition
121enum
122{
123 kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
124 kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
125 kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
126 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
127 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
128};
129
130//!@brief Flash Pad Definitions
131enum
132{
133 kSerialFlash_1Pad = 1,
134 kSerialFlash_2Pads = 2,
135 kSerialFlash_4Pads = 4,
136 kSerialFlash_8Pads = 8,
137};
138
139//!@brief FlexSPI LUT Sequence structure
140typedef struct _lut_sequence
141{
142 uint8_t seqNum; //!< Sequence Number, valid number: 1-16
143 uint8_t seqId; //!< Sequence Index, valid number: 0-15
144 uint16_t reserved;
145} flexspi_lut_seq_t;
146
147//!@brief Flash Configuration Command Type
148enum
149{
150 kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
151 kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
152 kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
153 kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
154 kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
155 kDeviceConfigCmdType_Reset, //!< Reset device command
156};
157
158//!@brief FlexSPI Memory Configuration Block
159typedef struct _FlexSPIConfig
160{
161 uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
162 uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
163 uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
164 uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
165 uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
166 uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
167 uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
168 //! Serial NAND, need to refer to datasheet
169 uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
170 uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
171 //! Generic configuration, etc.
172 uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
173 //! DPI/QPI/OPI switch or reset command
174 flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
175 //! sequence number, [31:16] Reserved
176 uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
177 uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
178 uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
179 flexspi_lut_seq_t
180 configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
181 uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
182 uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
183 uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
184 uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
185 //! details
186 uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
187 uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
188 uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
189 //! Chapter for more details
190 uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
191 //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
192 uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
193 uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
194 uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
195 uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
196 uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
197 uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
198 uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
199 uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
200 uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
201 uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
202 uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
203 uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
204 uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
205 uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
206 //! busy flag is 0 when flash device is busy
207 uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
208 flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
209 uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
210} flexspi_mem_config_t;
211
212/* */
213#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
214#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
215#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
216#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
217#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
218#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
219#define NOR_CMD_INDEX_DUMMY 6 //!< 6
220#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
221
222#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
223#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
224 CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
225#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
226 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
227#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
228 CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
229#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
230 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
231#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
232#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
233#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
234 CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
235#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
236#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
237#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
238 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
239#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
240 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
241
242/*
243 * Serial NOR configuration block
244 */
245typedef struct _flexspi_nor_config
246{
247 flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
248 uint32_t pageSize; //!< Page size of Serial NOR
249 uint32_t sectorSize; //!< Sector size of Serial NOR
250 uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
251 uint8_t isUniformBlockSize; //!< Sector/Block size is the same
252 uint8_t reserved0[2]; //!< Reserved for future use
253 uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
254 uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
255 uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
256 uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
257 uint32_t blockSize; //!< Block size
258 uint32_t reserve2[11]; //!< Reserved for future use
259} flexspi_nor_config_t;
260
261#ifdef __cplusplus
262extern "C" {
263#endif
264
265#ifdef __cplusplus
266}
267#endif
268#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */
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