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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.c111
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.h256
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.c404
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.h146
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.c111
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.h256
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.c520
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.h112
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.c23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.h23
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/pin_mux.c1745
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/pin_mux.h539
12 files changed, 4246 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.c
new file mode 100644
index 000000000..529e6217b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <stdint.h>
10#include "fsl_common.h"
11#include "fsl_port.h"
12#include "clock_config.h"
13#include "board.h"
14#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
15#include "fsl_i2c.h"
16#endif /* SDK_I2C_BASED_COMPONENT_USED */
17#include "fsl_debug_console.h"
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Code
25 ******************************************************************************/
26/* Initialize debug console. */
27void BOARD_InitDebugConsole(void)
28{
29 uint32_t uartClkSrcFreq;
30
31 /* SIM_SOPT2[27:26]:
32 * 00: Clock Disabled
33 * 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
34 * 10: OSCERCLK
35 * 11: MCGIRCCLK
36 */
37 CLOCK_SetLpuartClock(2);
38
39 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
40
41 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
42}
43#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
44void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
45{
46 i2c_master_config_t i2cConfig = {0};
47
48 I2C_MasterGetDefaultConfig(&i2cConfig);
49 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
50}
51
52status_t BOARD_I2C_Send(I2C_Type *base,
53 uint8_t deviceAddress,
54 uint32_t subAddress,
55 uint8_t subaddressSize,
56 uint8_t *txBuff,
57 uint8_t txBuffSize)
58{
59 i2c_master_transfer_t masterXfer;
60
61 /* Prepare transfer structure. */
62 masterXfer.slaveAddress = deviceAddress;
63 masterXfer.direction = kI2C_Write;
64 masterXfer.subaddress = subAddress;
65 masterXfer.subaddressSize = subaddressSize;
66 masterXfer.data = txBuff;
67 masterXfer.dataSize = txBuffSize;
68 masterXfer.flags = kI2C_TransferDefaultFlag;
69
70 return I2C_MasterTransferBlocking(base, &masterXfer);
71}
72
73status_t BOARD_I2C_Receive(I2C_Type *base,
74 uint8_t deviceAddress,
75 uint32_t subAddress,
76 uint8_t subaddressSize,
77 uint8_t *rxBuff,
78 uint8_t rxBuffSize)
79{
80 i2c_master_transfer_t masterXfer;
81
82 /* Prepare transfer structure. */
83 masterXfer.slaveAddress = deviceAddress;
84 masterXfer.subaddress = subAddress;
85 masterXfer.subaddressSize = subaddressSize;
86 masterXfer.data = rxBuff;
87 masterXfer.dataSize = rxBuffSize;
88 masterXfer.direction = kI2C_Read;
89 masterXfer.flags = kI2C_TransferDefaultFlag;
90
91 return I2C_MasterTransferBlocking(base, &masterXfer);
92}
93
94void BOARD_Accel_I2C_Init(void)
95{
96 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
97}
98
99status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
100{
101 uint8_t data = (uint8_t)txBuff;
102
103 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
104}
105
106status_t BOARD_Accel_I2C_Receive(
107 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
108{
109 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
110}
111#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.h
new file mode 100644
index 000000000..6e983e8b3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/board.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _BOARD_H_
10#define _BOARD_H_
11
12#include "clock_config.h"
13#include "fsl_gpio.h"
14#include "fsl_port.h"
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "FRDM-K28FA"
20
21/*! @brief The UART to use for debug messages. */
22#define BOARD_USE_UART
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
25#define BOARD_DEBUG_UART_INSTANCE 0U
26#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Osc0ErClk
27#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
28#define BOARD_UART_IRQ LPUART0_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE 115200
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/*! @brief The i2c instance used for i2c connection by default */
36#define BOARD_I2C_BASEADDR I2C3
37
38/*! @brief The bubble level demo information */
39#define BOARD_FXOS8700_ADDR 0x1C
40#define BOARD_ACCEL_ADDR BOARD_FXOS8700_ADDR
41#define BOARD_ACCEL_BAUDRATE 100
42#define BOARD_ACCEL_I2C_BASEADDR I2C3
43#define BOARD_ACCEL_I2C_CLOCK_FREQ CLOCK_GetFreq(I2C3_CLK_SRC)
44/*! @brief The TPM instance/channel used for board */
45#define BOARD_TPM_BASEADDR TPM2
46#define BOARD_TPM_CHANNEL 0U
47
48/*! @brief The FlexBus instance used for board.*/
49#define BOARD_FLEXBUS_BASEADDR FB
50
51#define BOARD_TSI_ELECTRODE_CNT 2U
52
53/*! @brief Indexes of the TSI channels for on board electrodes */
54#ifndef BOARD_TSI_ELECTRODE_1
55#define BOARD_TSI_ELECTRODE_1 11U
56#endif
57#ifndef BOARD_TSI_ELECTRODE_2
58#define BOARD_TSI_ELECTRODE_2 12U
59#endif
60
61/*! @brief The SDHC instance/channel used for board */
62#define BOARD_SDHC_BASEADDR SDHC
63
64/*! @brief The CMP instance/channel used for board. */
65#define BOARD_CMP_BASEADDR CMP1
66#define BOARD_CMP_CHANNEL 3U
67
68/*! @brief The i2c instance used for sai demo */
69#define BOARD_SAI_DEMO_I2C_BASEADDR I2C0
70
71/*! @brief The rtc instance used for rtc_func */
72#define BOARD_RTC_FUNC_BASEADDR RTC
73
74/*! @brief If connected the TWR_MEM, this is spi sd card */
75#ifndef BOARD_SDCARD_CARD_DETECTION_GPIO
76#define BOARD_SDCARD_CARD_DETECTION_GPIO GPIOD
77#endif
78#define BOARD_SDCARD_CARD_DETECTION_GPIO_PORT PORTD
79#define SDCARD_CARD_DETECTION_GPIO_PIN 15U
80#define SDCARD_CARD_WRITE_PROTECTION_GPIO GPIOC
81#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PORT PORTC
82#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PIN 13U
83#define SDCARD_SPI_HW_BASEADDR SPI1
84#define SDCARD_CARD_INSERTED 0U
85
86/*! @brief Define the port interrupt number for the board switches */
87#ifndef BOARD_SW2_GPIO
88#define BOARD_SW2_GPIO GPIOA
89#endif
90#ifndef BOARD_SW2_PORT
91#define BOARD_SW2_PORT PORTA
92#endif
93#ifndef BOARD_SW2_GPIO_PIN
94#define BOARD_SW2_GPIO_PIN 4U
95#endif
96#define BOARD_SW2_IRQ PORTA_IRQn
97#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
98#define BOARD_SW2_NAME "SW2"
99
100#ifndef BOARD_SW3_GPIO
101#define BOARD_SW3_GPIO GPIOD
102#endif
103#ifndef BOARD_SW3_PORT
104#define BOARD_SW3_PORT PORTD
105#endif
106#ifndef BOARD_SW3_GPIO_PIN
107#define BOARD_SW3_GPIO_PIN 0U
108#endif
109#define BOARD_SW3_IRQ PORTD_IRQn
110#define BOARD_SW3_IRQ_HANDLER PORTD_IRQHandler
111#define BOARD_SW3_NAME "SW3"
112
113#define LLWU_SW_GPIO BOARD_SW3_GPIO
114#define LLWU_SW_PORT BOARD_SW3_PORT
115#define LLWU_SW_GPIO_PIN BOARD_SW3_GPIO_PIN
116#define LLWU_SW_IRQ BOARD_SW3_IRQ
117#define LLWU_SW_IRQ_HANDLER BOARD_SW3_IRQ_HANDLER
118#define LLWU_SW_NAME BOARD_SW3_NAME
119/* Board led color mapping */
120#define LOGIC_LED_ON 1U
121#define LOGIC_LED_OFF 0U
122#ifndef BOARD_LED_RED_GPIO
123#define BOARD_LED_RED_GPIO GPIOE
124#endif
125#define BOARD_LED_RED_GPIO_PORT PORTE
126#ifndef BOARD_LED_RED_GPIO_PIN
127#define BOARD_LED_RED_GPIO_PIN 6U
128#endif
129#ifndef BOARD_LED_GREEN_GPIO
130#define BOARD_LED_GREEN_GPIO GPIOE
131#endif
132#define BOARD_LED_GREEN_GPIO_PORT PORTE
133#ifndef BOARD_LED_GREEN_GPIO_PIN
134#define BOARD_LED_GREEN_GPIO_PIN 7U
135#endif
136#ifndef BOARD_LED_BLUE_GPIO
137#define BOARD_LED_BLUE_GPIO GPIOE
138#endif
139#define BOARD_LED_BLUE_GPIO_PORT PORTE
140#ifndef BOARD_LED_BLUE_GPIO_PIN
141#define BOARD_LED_BLUE_GPIO_PIN 8U
142#endif
143
144#define LED_RED_INIT(output) \
145 GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
146 BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
147
148#define LED_RED_ON() \
149 GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED \ \ \ \ \
150 */
151#define LED_RED_OFF() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
152#define LED_RED_TOGGLE() \
153 GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
154
155#define LED_GREEN_INIT(output) \
156 GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
157 BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
158#define LED_GREEN_ON() \
159 GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
160#define LED_GREEN_OFF() \
161 GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
162#define LED_GREEN_TOGGLE() \
163 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
164
165#define LED_BLUE_INIT(output) \
166 GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
167 BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */
168#define LED_BLUE_ON() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
169#define LED_BLUE_OFF() \
170 GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
171#define LED_BLUE_TOGGLE() \
172 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
173
174/* FLEXIO */
175#define BOARD_FLEXIO_I2C_INSTANCE (1)
176#define BOARD_FLEXIO_I2C_INSTANCE_BASE (I2C1)
177#define BOARD_FLEXIO_INSTANCE (0)
178#define BOARD_FLEXIO_INSTANCE_BASE (FLEXIO0)
179#define BOARD_FLEXIO_DATA_PINS (8)
180#define BOARD_FLEXIO_DATA_PIN_START_INDEX (16)
181#define BOARD_FLEXIO_DATA_PIN_END_INDEX (23)
182#define BOARD_FLEXIO_PCLK_PIN_INDEX (6)
183#define BOARD_FLEXIO_HREF_PIN_INDEX (7)
184#define BOARD_FLEXIO_VSYNC_PORT_INDEX (0)
185#define BOARD_FLEXIO_VSYNC_PIN_INDEX (20)
186#define BOARD_FLEXIO_CLCK_OUT_PORT_INDEX (0)
187#define BOARD_FLEXIO_CLCK_OUT_PIN_INDEX (6)
188#define BOARD_FLEXIO_RESET_PORT_INDEX (0)
189#define BOARD_FLEXIO_RESET_PIN_INDEX (5)
190
191/* ERPC DSPI configuration */
192#define ERPC_BOARD_SPI_SLAVE_READY_USE_GPIO (1)
193#define ERPC_BOARD_DSPI_BASEADDR SPI0
194#define ERPC_BOARD_DSPI_BAUDRATE 500000U
195#define ERPC_BOARD_DSPI_CLKSRC DSPI0_CLK_SRC
196#define ERPC_BOARD_DSPI_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC)
197#define ERPC_BOARD_DSPI_INT_GPIO GPIOC
198#define ERPC_BOARD_DSPI_INT_PORT PORTC
199#define ERPC_BOARD_DSPI_INT_PIN 11U
200#define ERPC_BOARD_DSPI_INT_PIN_IRQ PORTC_IRQn
201#define ERPC_BOARD_DSPI_INT_PIN_IRQ_HANDLER PORTC_IRQHandler
202
203/* DAC base address */
204#define BOARD_DAC_BASEADDR DAC0
205
206/* Board accelerometer driver */
207#define BOARD_ACCEL_FXOS
208
209/* USB PHY condfiguration */
210#define BOARD_USB_PHY_D_CAL (0x0CU)
211#define BOARD_USB_PHY_TXCAL45DP (0x06U)
212#define BOARD_USB_PHY_TXCAL45DM (0x06U)
213
214/* LCD panel. */
215#define BOARD_LCD_RST_GPIO GPIOA
216#define BOARD_LCD_RST_PIN 5
217#define BOARD_LCD_TE_GPIO GPIOA
218#define BOARD_LCD_TE_PIN 21
219#define BOARD_LCD_CS_GPIO GPIOA
220#define BOARD_LCD_CS_PIN 22
221#define BOARD_LCD_RS_GPIO GPIOA
222#define BOARD_LCD_RS_PIN 6
223
224#if defined(__cplusplus)
225extern "C" {
226#endif /* __cplusplus */
227
228/*******************************************************************************
229 * API
230 ******************************************************************************/
231
232void BOARD_InitDebugConsole(void);
233#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
234void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
235status_t BOARD_I2C_Send(I2C_Type *base,
236 uint8_t deviceAddress,
237 uint32_t subAddress,
238 uint8_t subaddressSize,
239 uint8_t *txBuff,
240 uint8_t txBuffSize);
241status_t BOARD_I2C_Receive(I2C_Type *base,
242 uint8_t deviceAddress,
243 uint32_t subAddress,
244 uint8_t subaddressSize,
245 uint8_t *rxBuff,
246 uint8_t rxBuffSize);
247void BOARD_Accel_I2C_Init(void);
248status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
249status_t BOARD_Accel_I2C_Receive(
250 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
251#endif /* SDK_I2C_BASED_COMPONENT_USED */
252#if defined(__cplusplus)
253}
254#endif /* __cplusplus */
255
256#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.c
new file mode 100644
index 000000000..11771d076
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.c
@@ -0,0 +1,404 @@
1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40/* clang-format off */
41/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42!!GlobalInfo
43product: Clocks v7.0
44processor: MK28FN2M0Axxx15
45package_id: MK28FN2M0AVMI15
46mcu_data: ksdk2_0
47processor_version: 0.7.1
48 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
49/* clang-format on */
50
51#include "fsl_smc.h"
52#include "clock_config.h"
53
54/*******************************************************************************
55 * Definitions
56 ******************************************************************************/
57#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
58#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
59#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
60#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
61#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
62#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
63
64/*******************************************************************************
65 * Variables
66 ******************************************************************************/
67/* System clock frequency. */
68extern uint32_t SystemCoreClock;
69
70/*******************************************************************************
71 * Code
72 ******************************************************************************/
73/*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
76 * Description : Configure FLL external reference divider (FRDIV).
77 * Param frdiv : The value to set FRDIV.
78 *
79 *END**************************************************************************/
80static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
81{
82 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
83}
84
85/*******************************************************************************
86 ************************ BOARD_InitBootClocks function ************************
87 ******************************************************************************/
88void BOARD_InitBootClocks(void)
89{
90 BOARD_BootClockRUN();
91}
92
93/*******************************************************************************
94 ********************** Configuration BOARD_BootClockRUN ***********************
95 ******************************************************************************/
96/* clang-format off */
97/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
98!!Configuration
99name: BOARD_BootClockRUN
100called_from_default_init: true
101outputs:
102- {id: Bus_clock.outFreq, value: 60 MHz}
103- {id: Core_clock.outFreq, value: 120 MHz}
104- {id: Flash_clock.outFreq, value: 24 MHz}
105- {id: FlexBus_clock.outFreq, value: 60 MHz}
106- {id: LPO_clock.outFreq, value: 1 kHz}
107- {id: MCGFFCLK.outFreq, value: 375 kHz}
108- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
109- {id: MCGPLLCLK.outFreq, value: 120 MHz}
110- {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
111- {id: OSCERCLK.outFreq, value: 12 MHz}
112- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
113- {id: PLLFLLCLK.outFreq, value: 120 MHz}
114- {id: System_clock.outFreq, value: 120 MHz}
115settings:
116- {id: MCGMode, value: PEE}
117- {id: MCG.FCRDIV.scale, value: '1', locked: true}
118- {id: MCG.FRDIV.scale, value: '32'}
119- {id: MCG.IREFS.sel, value: MCG.FRDIV}
120- {id: MCG.PLLS.sel, value: MCG.PLLCS}
121- {id: MCG.PRDIV.scale, value: '1', locked: true}
122- {id: MCG.VDIV.scale, value: '20', locked: true}
123- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
124- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
125- {id: MCG_C2_RANGE0_CFG, value: Very_high}
126- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
127- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
128- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
129- {id: RTC_CR_OSCE_CFG, value: Enabled}
130- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
131- {id: SIM.OUTDIV2.scale, value: '2'}
132- {id: SIM.OUTDIV3.scale, value: '2'}
133- {id: SIM.OUTDIV4.scale, value: '5'}
134- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
135sources:
136- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
137 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
138/* clang-format on */
139
140/*******************************************************************************
141 * Variables for BOARD_BootClockRUN configuration
142 ******************************************************************************/
143const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
144 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
145 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
146 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
147 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
148 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
149 .drs = kMCG_DrsLow, /* Low frequency range */
150 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
151 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
152 .pll0Config =
153 {
154 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
155 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
156 .vdiv = 0x4U, /* VCO divider: multiplied by 20 */
157 },
158 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
159};
160const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
161 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
162 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
163 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
164 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
165 .clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
166};
167const osc_config_t oscConfig_BOARD_BootClockRUN = {
168 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
169 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
170 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
171 .oscerConfig = {
172 .enableMode =
173 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
174 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
175 }};
176
177/*******************************************************************************
178 * Code for BOARD_BootClockRUN configuration
179 ******************************************************************************/
180void BOARD_BootClockRUN(void)
181{
182 /* Set the system clock dividers in SIM to safe value. */
183 CLOCK_SetSimSafeDivs();
184 /* Initializes OSC0 according to board configuration. */
185 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
186 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
187 /* Configure the Internal Reference clock (MCGIRCLK). */
188 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
189 mcgConfig_BOARD_BootClockRUN.fcrdiv);
190 /* Configure FLL external reference divider (FRDIV). */
191 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
192 /* Set MCG to PEE mode. */
193 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, mcgConfig_BOARD_BootClockRUN.pllcs,
194 &mcgConfig_BOARD_BootClockRUN.pll0Config);
195 /* Set the clock configuration in SIM module. */
196 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
197 /* Set SystemCoreClock variable. */
198 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
199}
200
201/*******************************************************************************
202 ********************* Configuration BOARD_BootClockVLPR ***********************
203 ******************************************************************************/
204/* clang-format off */
205/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
206!!Configuration
207name: BOARD_BootClockVLPR
208outputs:
209- {id: Bus_clock.outFreq, value: 4 MHz}
210- {id: Core_clock.outFreq, value: 4 MHz}
211- {id: Flash_clock.outFreq, value: 800 kHz}
212- {id: FlexBus_clock.outFreq, value: 4 MHz}
213- {id: LPO_clock.outFreq, value: 1 kHz}
214- {id: MCGIRCLK.outFreq, value: 4 MHz}
215- {id: System_clock.outFreq, value: 4 MHz}
216settings:
217- {id: MCGMode, value: BLPI}
218- {id: powerMode, value: VLPR}
219- {id: MCG.CLKS.sel, value: MCG.IRCS}
220- {id: MCG.FCRDIV.scale, value: '1', locked: true}
221- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
222- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
223- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
224- {id: SIM.OUTDIV2.scale, value: '1', locked: true}
225- {id: SIM.OUTDIV3.scale, value: '1', locked: true}
226- {id: SIM.OUTDIV4.scale, value: '5', locked: true}
227- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
228 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
229/* clang-format on */
230
231/*******************************************************************************
232 * Variables for BOARD_BootClockVLPR configuration
233 ******************************************************************************/
234const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
235 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
236 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
237 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
238 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
239 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
240 .drs = kMCG_DrsLow, /* Low frequency range */
241 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
242 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
243 .pll0Config =
244 {
245 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
246 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
247 .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
248 },
249 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
250};
251const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
252 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
253 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
254 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
255 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
256 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
257};
258const osc_config_t oscConfig_BOARD_BootClockVLPR = {
259 .freq = 0U, /* Oscillator frequency: 0Hz */
260 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
261 .workMode = kOSC_ModeExt, /* Use external clock */
262 .oscerConfig = {
263 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
264 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
265 }};
266
267/*******************************************************************************
268 * Code for BOARD_BootClockVLPR configuration
269 ******************************************************************************/
270void BOARD_BootClockVLPR(void)
271{
272 /* Set the system clock dividers in SIM to safe value. */
273 CLOCK_SetSimSafeDivs();
274 /* Set MCG to BLPI mode. */
275 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
276 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
277 /* Set the clock configuration in SIM module. */
278 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
279 /* Set VLPR power mode. */
280 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
281#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
282 SMC_SetPowerModeVlpr(SMC, false);
283#else
284 SMC_SetPowerModeVlpr(SMC);
285#endif
286 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
287 {
288 }
289 /* Set SystemCoreClock variable. */
290 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
291}
292
293/*******************************************************************************
294 ********************* Configuration BOARD_BootClockHSRUN **********************
295 ******************************************************************************/
296/* clang-format off */
297/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
298!!Configuration
299name: BOARD_BootClockHSRUN
300outputs:
301- {id: Bus_clock.outFreq, value: 75 MHz}
302- {id: Core_clock.outFreq, value: 150 MHz}
303- {id: Flash_clock.outFreq, value: 25 MHz}
304- {id: FlexBus_clock.outFreq, value: 75 MHz}
305- {id: LPO_clock.outFreq, value: 1 kHz}
306- {id: MCGFFCLK.outFreq, value: 375 kHz}
307- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
308- {id: MCGPLLCLK.outFreq, value: 150 MHz}
309- {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
310- {id: OSCERCLK.outFreq, value: 12 MHz}
311- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
312- {id: PLLFLLCLK.outFreq, value: 150 MHz}
313- {id: System_clock.outFreq, value: 150 MHz}
314settings:
315- {id: MCGMode, value: PEE}
316- {id: powerMode, value: HSRUN}
317- {id: MCG.FCRDIV.scale, value: '1', locked: true}
318- {id: MCG.FRDIV.scale, value: '32'}
319- {id: MCG.IREFS.sel, value: MCG.FRDIV}
320- {id: MCG.PLLS.sel, value: MCG.PLLCS}
321- {id: MCG.PRDIV.scale, value: '1', locked: true}
322- {id: MCG.VDIV.scale, value: '25', locked: true}
323- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
324- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
325- {id: MCG_C2_RANGE0_CFG, value: Very_high}
326- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
327- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
328- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
329- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
330- {id: SIM.OUTDIV2.scale, value: '2'}
331- {id: SIM.OUTDIV3.scale, value: '2', locked: true}
332- {id: SIM.OUTDIV4.scale, value: '6'}
333- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
334sources:
335- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
336 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
337/* clang-format on */
338
339/*******************************************************************************
340 * Variables for BOARD_BootClockHSRUN configuration
341 ******************************************************************************/
342const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
343 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
344 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
345 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
346 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
347 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
348 .drs = kMCG_DrsLow, /* Low frequency range */
349 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
350 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
351 .pll0Config =
352 {
353 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
354 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
355 .vdiv = 0x9U, /* VCO divider: multiplied by 25 */
356 },
357 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
358};
359const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
360 .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
361 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
362 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
363 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
364 .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
365};
366const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
367 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
368 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
369 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
370 .oscerConfig = {
371 .enableMode =
372 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
373 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
374 }};
375
376/*******************************************************************************
377 * Code for BOARD_BootClockHSRUN configuration
378 ******************************************************************************/
379void BOARD_BootClockHSRUN(void)
380{
381 /* Set HSRUN power mode */
382 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
383 SMC_SetPowerModeHsrun(SMC);
384 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
385 {
386 }
387 /* Set the system clock dividers in SIM to safe value. */
388 CLOCK_SetSimSafeDivs();
389 /* Initializes OSC0 according to board configuration. */
390 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
391 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
392 /* Configure the Internal Reference clock (MCGIRCLK). */
393 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
394 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
395 /* Configure FLL external reference divider (FRDIV). */
396 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
397 /* Set MCG to PEE mode. */
398 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, mcgConfig_BOARD_BootClockHSRUN.pllcs,
399 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
400 /* Set the clock configuration in SIM module. */
401 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
402 /* Set SystemCoreClock variable. */
403 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
404}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.h
new file mode 100644
index 000000000..f9e7087b0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/clock_config.h
@@ -0,0 +1,146 @@
1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */
22
23/*******************************************************************************
24 ************************ BOARD_InitBootClocks function ************************
25 ******************************************************************************/
26
27#if defined(__cplusplus)
28extern "C" {
29#endif /* __cplusplus*/
30
31/*!
32 * @brief This function executes default configuration of clocks.
33 *
34 */
35void BOARD_InitBootClocks(void);
36
37#if defined(__cplusplus)
38}
39#endif /* __cplusplus*/
40
41/*******************************************************************************
42 ********************** Configuration BOARD_BootClockRUN ***********************
43 ******************************************************************************/
44/*******************************************************************************
45 * Definitions for BOARD_BootClockRUN configuration
46 ******************************************************************************/
47#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */
48
49/*! @brief MCG set for BOARD_BootClockRUN configuration.
50 */
51extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
52/*! @brief SIM module set for BOARD_BootClockRUN configuration.
53 */
54extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
55/*! @brief OSC set for BOARD_BootClockRUN configuration.
56 */
57extern const osc_config_t oscConfig_BOARD_BootClockRUN;
58
59/*******************************************************************************
60 * API for BOARD_BootClockRUN configuration
61 ******************************************************************************/
62#if defined(__cplusplus)
63extern "C" {
64#endif /* __cplusplus*/
65
66/*!
67 * @brief This function executes configuration of clocks.
68 *
69 */
70void BOARD_BootClockRUN(void);
71
72#if defined(__cplusplus)
73}
74#endif /* __cplusplus*/
75
76/*******************************************************************************
77 ********************* Configuration BOARD_BootClockVLPR ***********************
78 ******************************************************************************/
79/*******************************************************************************
80 * Definitions for BOARD_BootClockVLPR configuration
81 ******************************************************************************/
82#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
83
84/*! @brief MCG set for BOARD_BootClockVLPR configuration.
85 */
86extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
87/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
88 */
89extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
90/*! @brief OSC set for BOARD_BootClockVLPR configuration.
91 */
92extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
93
94/*******************************************************************************
95 * API for BOARD_BootClockVLPR configuration
96 ******************************************************************************/
97#if defined(__cplusplus)
98extern "C" {
99#endif /* __cplusplus*/
100
101/*!
102 * @brief This function executes configuration of clocks.
103 *
104 */
105void BOARD_BootClockVLPR(void);
106
107#if defined(__cplusplus)
108}
109#endif /* __cplusplus*/
110
111/*******************************************************************************
112 ********************* Configuration BOARD_BootClockHSRUN **********************
113 ******************************************************************************/
114/*******************************************************************************
115 * Definitions for BOARD_BootClockHSRUN configuration
116 ******************************************************************************/
117#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
118
119/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
120 */
121extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
122/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
123 */
124extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
125/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
126 */
127extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
128
129/*******************************************************************************
130 * API for BOARD_BootClockHSRUN configuration
131 ******************************************************************************/
132#if defined(__cplusplus)
133extern "C" {
134#endif /* __cplusplus*/
135
136/*!
137 * @brief This function executes configuration of clocks.
138 *
139 */
140void BOARD_BootClockHSRUN(void);
141
142#if defined(__cplusplus)
143}
144#endif /* __cplusplus*/
145
146#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.c
new file mode 100644
index 000000000..529e6217b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <stdint.h>
10#include "fsl_common.h"
11#include "fsl_port.h"
12#include "clock_config.h"
13#include "board.h"
14#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
15#include "fsl_i2c.h"
16#endif /* SDK_I2C_BASED_COMPONENT_USED */
17#include "fsl_debug_console.h"
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22
23/*******************************************************************************
24 * Code
25 ******************************************************************************/
26/* Initialize debug console. */
27void BOARD_InitDebugConsole(void)
28{
29 uint32_t uartClkSrcFreq;
30
31 /* SIM_SOPT2[27:26]:
32 * 00: Clock Disabled
33 * 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
34 * 10: OSCERCLK
35 * 11: MCGIRCCLK
36 */
37 CLOCK_SetLpuartClock(2);
38
39 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
40
41 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
42}
43#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
44void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
45{
46 i2c_master_config_t i2cConfig = {0};
47
48 I2C_MasterGetDefaultConfig(&i2cConfig);
49 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
50}
51
52status_t BOARD_I2C_Send(I2C_Type *base,
53 uint8_t deviceAddress,
54 uint32_t subAddress,
55 uint8_t subaddressSize,
56 uint8_t *txBuff,
57 uint8_t txBuffSize)
58{
59 i2c_master_transfer_t masterXfer;
60
61 /* Prepare transfer structure. */
62 masterXfer.slaveAddress = deviceAddress;
63 masterXfer.direction = kI2C_Write;
64 masterXfer.subaddress = subAddress;
65 masterXfer.subaddressSize = subaddressSize;
66 masterXfer.data = txBuff;
67 masterXfer.dataSize = txBuffSize;
68 masterXfer.flags = kI2C_TransferDefaultFlag;
69
70 return I2C_MasterTransferBlocking(base, &masterXfer);
71}
72
73status_t BOARD_I2C_Receive(I2C_Type *base,
74 uint8_t deviceAddress,
75 uint32_t subAddress,
76 uint8_t subaddressSize,
77 uint8_t *rxBuff,
78 uint8_t rxBuffSize)
79{
80 i2c_master_transfer_t masterXfer;
81
82 /* Prepare transfer structure. */
83 masterXfer.slaveAddress = deviceAddress;
84 masterXfer.subaddress = subAddress;
85 masterXfer.subaddressSize = subaddressSize;
86 masterXfer.data = rxBuff;
87 masterXfer.dataSize = rxBuffSize;
88 masterXfer.direction = kI2C_Read;
89 masterXfer.flags = kI2C_TransferDefaultFlag;
90
91 return I2C_MasterTransferBlocking(base, &masterXfer);
92}
93
94void BOARD_Accel_I2C_Init(void)
95{
96 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
97}
98
99status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
100{
101 uint8_t data = (uint8_t)txBuff;
102
103 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
104}
105
106status_t BOARD_Accel_I2C_Receive(
107 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
108{
109 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
110}
111#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.h
new file mode 100644
index 000000000..6e983e8b3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/board.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _BOARD_H_
10#define _BOARD_H_
11
12#include "clock_config.h"
13#include "fsl_gpio.h"
14#include "fsl_port.h"
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "FRDM-K28FA"
20
21/*! @brief The UART to use for debug messages. */
22#define BOARD_USE_UART
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
25#define BOARD_DEBUG_UART_INSTANCE 0U
26#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Osc0ErClk
27#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
28#define BOARD_UART_IRQ LPUART0_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE 115200
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/*! @brief The i2c instance used for i2c connection by default */
36#define BOARD_I2C_BASEADDR I2C3
37
38/*! @brief The bubble level demo information */
39#define BOARD_FXOS8700_ADDR 0x1C
40#define BOARD_ACCEL_ADDR BOARD_FXOS8700_ADDR
41#define BOARD_ACCEL_BAUDRATE 100
42#define BOARD_ACCEL_I2C_BASEADDR I2C3
43#define BOARD_ACCEL_I2C_CLOCK_FREQ CLOCK_GetFreq(I2C3_CLK_SRC)
44/*! @brief The TPM instance/channel used for board */
45#define BOARD_TPM_BASEADDR TPM2
46#define BOARD_TPM_CHANNEL 0U
47
48/*! @brief The FlexBus instance used for board.*/
49#define BOARD_FLEXBUS_BASEADDR FB
50
51#define BOARD_TSI_ELECTRODE_CNT 2U
52
53/*! @brief Indexes of the TSI channels for on board electrodes */
54#ifndef BOARD_TSI_ELECTRODE_1
55#define BOARD_TSI_ELECTRODE_1 11U
56#endif
57#ifndef BOARD_TSI_ELECTRODE_2
58#define BOARD_TSI_ELECTRODE_2 12U
59#endif
60
61/*! @brief The SDHC instance/channel used for board */
62#define BOARD_SDHC_BASEADDR SDHC
63
64/*! @brief The CMP instance/channel used for board. */
65#define BOARD_CMP_BASEADDR CMP1
66#define BOARD_CMP_CHANNEL 3U
67
68/*! @brief The i2c instance used for sai demo */
69#define BOARD_SAI_DEMO_I2C_BASEADDR I2C0
70
71/*! @brief The rtc instance used for rtc_func */
72#define BOARD_RTC_FUNC_BASEADDR RTC
73
74/*! @brief If connected the TWR_MEM, this is spi sd card */
75#ifndef BOARD_SDCARD_CARD_DETECTION_GPIO
76#define BOARD_SDCARD_CARD_DETECTION_GPIO GPIOD
77#endif
78#define BOARD_SDCARD_CARD_DETECTION_GPIO_PORT PORTD
79#define SDCARD_CARD_DETECTION_GPIO_PIN 15U
80#define SDCARD_CARD_WRITE_PROTECTION_GPIO GPIOC
81#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PORT PORTC
82#define SDCARD_CARD_WRITE_PROTECTION_GPIO_PIN 13U
83#define SDCARD_SPI_HW_BASEADDR SPI1
84#define SDCARD_CARD_INSERTED 0U
85
86/*! @brief Define the port interrupt number for the board switches */
87#ifndef BOARD_SW2_GPIO
88#define BOARD_SW2_GPIO GPIOA
89#endif
90#ifndef BOARD_SW2_PORT
91#define BOARD_SW2_PORT PORTA
92#endif
93#ifndef BOARD_SW2_GPIO_PIN
94#define BOARD_SW2_GPIO_PIN 4U
95#endif
96#define BOARD_SW2_IRQ PORTA_IRQn
97#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
98#define BOARD_SW2_NAME "SW2"
99
100#ifndef BOARD_SW3_GPIO
101#define BOARD_SW3_GPIO GPIOD
102#endif
103#ifndef BOARD_SW3_PORT
104#define BOARD_SW3_PORT PORTD
105#endif
106#ifndef BOARD_SW3_GPIO_PIN
107#define BOARD_SW3_GPIO_PIN 0U
108#endif
109#define BOARD_SW3_IRQ PORTD_IRQn
110#define BOARD_SW3_IRQ_HANDLER PORTD_IRQHandler
111#define BOARD_SW3_NAME "SW3"
112
113#define LLWU_SW_GPIO BOARD_SW3_GPIO
114#define LLWU_SW_PORT BOARD_SW3_PORT
115#define LLWU_SW_GPIO_PIN BOARD_SW3_GPIO_PIN
116#define LLWU_SW_IRQ BOARD_SW3_IRQ
117#define LLWU_SW_IRQ_HANDLER BOARD_SW3_IRQ_HANDLER
118#define LLWU_SW_NAME BOARD_SW3_NAME
119/* Board led color mapping */
120#define LOGIC_LED_ON 1U
121#define LOGIC_LED_OFF 0U
122#ifndef BOARD_LED_RED_GPIO
123#define BOARD_LED_RED_GPIO GPIOE
124#endif
125#define BOARD_LED_RED_GPIO_PORT PORTE
126#ifndef BOARD_LED_RED_GPIO_PIN
127#define BOARD_LED_RED_GPIO_PIN 6U
128#endif
129#ifndef BOARD_LED_GREEN_GPIO
130#define BOARD_LED_GREEN_GPIO GPIOE
131#endif
132#define BOARD_LED_GREEN_GPIO_PORT PORTE
133#ifndef BOARD_LED_GREEN_GPIO_PIN
134#define BOARD_LED_GREEN_GPIO_PIN 7U
135#endif
136#ifndef BOARD_LED_BLUE_GPIO
137#define BOARD_LED_BLUE_GPIO GPIOE
138#endif
139#define BOARD_LED_BLUE_GPIO_PORT PORTE
140#ifndef BOARD_LED_BLUE_GPIO_PIN
141#define BOARD_LED_BLUE_GPIO_PIN 8U
142#endif
143
144#define LED_RED_INIT(output) \
145 GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
146 BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
147
148#define LED_RED_ON() \
149 GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED \ \ \ \ \
150 */
151#define LED_RED_OFF() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
152#define LED_RED_TOGGLE() \
153 GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
154
155#define LED_GREEN_INIT(output) \
156 GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
157 BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
158#define LED_GREEN_ON() \
159 GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
160#define LED_GREEN_OFF() \
161 GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
162#define LED_GREEN_TOGGLE() \
163 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
164
165#define LED_BLUE_INIT(output) \
166 GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
167 BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */
168#define LED_BLUE_ON() GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */
169#define LED_BLUE_OFF() \
170 GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */
171#define LED_BLUE_TOGGLE() \
172 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
173
174/* FLEXIO */
175#define BOARD_FLEXIO_I2C_INSTANCE (1)
176#define BOARD_FLEXIO_I2C_INSTANCE_BASE (I2C1)
177#define BOARD_FLEXIO_INSTANCE (0)
178#define BOARD_FLEXIO_INSTANCE_BASE (FLEXIO0)
179#define BOARD_FLEXIO_DATA_PINS (8)
180#define BOARD_FLEXIO_DATA_PIN_START_INDEX (16)
181#define BOARD_FLEXIO_DATA_PIN_END_INDEX (23)
182#define BOARD_FLEXIO_PCLK_PIN_INDEX (6)
183#define BOARD_FLEXIO_HREF_PIN_INDEX (7)
184#define BOARD_FLEXIO_VSYNC_PORT_INDEX (0)
185#define BOARD_FLEXIO_VSYNC_PIN_INDEX (20)
186#define BOARD_FLEXIO_CLCK_OUT_PORT_INDEX (0)
187#define BOARD_FLEXIO_CLCK_OUT_PIN_INDEX (6)
188#define BOARD_FLEXIO_RESET_PORT_INDEX (0)
189#define BOARD_FLEXIO_RESET_PIN_INDEX (5)
190
191/* ERPC DSPI configuration */
192#define ERPC_BOARD_SPI_SLAVE_READY_USE_GPIO (1)
193#define ERPC_BOARD_DSPI_BASEADDR SPI0
194#define ERPC_BOARD_DSPI_BAUDRATE 500000U
195#define ERPC_BOARD_DSPI_CLKSRC DSPI0_CLK_SRC
196#define ERPC_BOARD_DSPI_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC)
197#define ERPC_BOARD_DSPI_INT_GPIO GPIOC
198#define ERPC_BOARD_DSPI_INT_PORT PORTC
199#define ERPC_BOARD_DSPI_INT_PIN 11U
200#define ERPC_BOARD_DSPI_INT_PIN_IRQ PORTC_IRQn
201#define ERPC_BOARD_DSPI_INT_PIN_IRQ_HANDLER PORTC_IRQHandler
202
203/* DAC base address */
204#define BOARD_DAC_BASEADDR DAC0
205
206/* Board accelerometer driver */
207#define BOARD_ACCEL_FXOS
208
209/* USB PHY condfiguration */
210#define BOARD_USB_PHY_D_CAL (0x0CU)
211#define BOARD_USB_PHY_TXCAL45DP (0x06U)
212#define BOARD_USB_PHY_TXCAL45DM (0x06U)
213
214/* LCD panel. */
215#define BOARD_LCD_RST_GPIO GPIOA
216#define BOARD_LCD_RST_PIN 5
217#define BOARD_LCD_TE_GPIO GPIOA
218#define BOARD_LCD_TE_PIN 21
219#define BOARD_LCD_CS_GPIO GPIOA
220#define BOARD_LCD_CS_PIN 22
221#define BOARD_LCD_RS_GPIO GPIOA
222#define BOARD_LCD_RS_PIN 6
223
224#if defined(__cplusplus)
225extern "C" {
226#endif /* __cplusplus */
227
228/*******************************************************************************
229 * API
230 ******************************************************************************/
231
232void BOARD_InitDebugConsole(void);
233#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
234void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
235status_t BOARD_I2C_Send(I2C_Type *base,
236 uint8_t deviceAddress,
237 uint32_t subAddress,
238 uint8_t subaddressSize,
239 uint8_t *txBuff,
240 uint8_t txBuffSize);
241status_t BOARD_I2C_Receive(I2C_Type *base,
242 uint8_t deviceAddress,
243 uint32_t subAddress,
244 uint8_t subaddressSize,
245 uint8_t *rxBuff,
246 uint8_t rxBuffSize);
247void BOARD_Accel_I2C_Init(void);
248status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
249status_t BOARD_Accel_I2C_Receive(
250 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
251#endif /* SDK_I2C_BASED_COMPONENT_USED */
252#if defined(__cplusplus)
253}
254#endif /* __cplusplus */
255
256#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.c
new file mode 100644
index 000000000..a522c380f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.c
@@ -0,0 +1,520 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40/* clang-format off */
41/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42!!GlobalInfo
43product: Clocks v5.0
44processor: MK28FN2M0Axxx15
45package_id: MK28FN2M0AVMI15
46mcu_data: ksdk2_0
47processor_version: 0.0.2
48board: FRDM-K28FA
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50/* clang-format on */
51
52#include "fsl_smc.h"
53#include "fsl_rtc.h"
54#include "clock_config.h"
55
56/*******************************************************************************
57 * Definitions
58 ******************************************************************************/
59#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
60#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
61#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
62#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
63#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */
64#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */
65#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */
66#define SIM_FLEXIO_CLK_SEL_OSCERCLK_CLK 2U /*!< FLEXIO clock select: OSCERCLK clock */
67#define SIM_LPUART_CLK_SEL_OSCERCLK_CLK 2U /*!< LPUART clock select: OSCERCLK clock */
68#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
69#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
70#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
71#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
72#define SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK 0U /*!< RTC clock output select: RTC1HzCLK clock */
73#define SIM_SDHC_CLK_SEL_OSCERCLK_CLK 2U /*!< SDHC clock select: OSCERCLK clock */
74#define SIM_TPM_CLK_SEL_PLLFLLSEL_CLK 1U /*!< TPM clock select: PLLFLLSEL output clock */
75#define SIM_TRACE_CLK_DIV_2 1U /*!< Trace clock divider divisor: divided by 2 */
76#define SIM_TRACE_CLK_FRAC_1 0U /*!< Trace clock divider fraction: multiplied by 1 */
77#define SIM_TRACE_CLK_SEL_MCGOUTCLK_CLK 0U /*!< Trace clock select: FlexBus clock */
78#define SIM_USB_CLK_48000000HZ 48000000U /*!< Input SIM frequency for USB: 48000000Hz */
79#define SIM_USB_SLOW_CLK_SEL_MCGIRCLK_CLK 0U /*!< USB slow clock select: MCGIRCLK clock */
80#define USBPHY_PFD_CLK_SEL_PFD_CLK_DIV_2 2U /*!< PFD clock select: pfd_clk clock divided by 2 */
81#define USBPHY_PFD_FRAC_DIV_24 24U /*!< PFD fractional divider: divided by 24 */
82
83/*******************************************************************************
84 * Variables
85 ******************************************************************************/
86/* System clock frequency. */
87extern uint32_t SystemCoreClock;
88
89/*******************************************************************************
90 * Code
91 ******************************************************************************/
92/*FUNCTION**********************************************************************
93 *
94 * Function Name : CLOCK_CONFIG_SetRtcClock
95 * Description : This function is used to configuring RTC clock including
96 * enabling RTC oscillator.
97 * Param capLoad : RTC oscillator capacity load
98 * Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals
99 *
100 *END**************************************************************************/
101static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph)
102{
103 /* RTC clock gate enable */
104 CLOCK_EnableClock(kCLOCK_Rtc0);
105 if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u)
106 { /* Only if the Rtc oscillator is not already enabled */
107 /* Set the specified capacitor configuration for the RTC oscillator */
108 RTC_SetOscCapLoad(RTC, capLoad);
109 /* Enable the RTC 32KHz oscillator */
110 RTC->CR |= RTC_CR_OSCE_MASK;
111 }
112 /* Output to other peripherals */
113 if (enableOutPeriph)
114 {
115 RTC->CR &= ~RTC_CR_CLKO_MASK;
116 }
117 else
118 {
119 RTC->CR |= RTC_CR_CLKO_MASK;
120 }
121 /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */
122 CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
123 /* Set RTC_TSR if there is fault value in RTC */
124 if (RTC->SR & RTC_SR_TIF_MASK)
125 {
126 RTC->TSR = RTC->TSR;
127 }
128 /* RTC clock gate disable */
129 CLOCK_DisableClock(kCLOCK_Rtc0);
130}
131
132/*FUNCTION**********************************************************************
133 *
134 * Function Name : CLOCK_CONFIG_EnableUsbhs0PhyPllClock
135 * Description : This function enables the internal 480MHz USB PHY PLL clock.
136 * Param src : USB HS PHY PLL clock source.
137 * Param freq : The frequency specified by src.
138 *
139 *END**************************************************************************/
140static void CLOCK_CONFIG_EnableUsbhs0PhyPllClock(uint32_t freq)
141{
142 volatile uint32_t i;
143 uint32_t phyPllDiv = 0U;
144
145 if (24000000U == freq)
146 {
147 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
148 }
149 else if (16000000U == freq)
150 {
151 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
152 }
153 else if (12000000U == freq)
154 {
155 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
156 }
157
158 SIM->SCGC3 |= SIM_SCGC3_USBHSPHY_MASK;
159 SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK;
160
161 i = 500000U;
162 while (i--)
163 {
164 __NOP();
165 }
166
167 USBPHY->TRIM_OVERRIDE_EN = 0x01U; /* Override the trim. */
168 USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
169 USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
170 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv;
171 USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */
172 USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
173
174 /* Wait for lock. */
175 while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
176 {
177 }
178}
179
180/*FUNCTION**********************************************************************
181 *
182 * Function Name : CLOCK_CONFIG_EnableUsbhs0PfdClock
183 * Description : This function enables USB HS PFD clock.
184 * Param frac : The value set to PFD_FRAC, it must be in the range of 18 to 35.
185 * Param src : Source of the USB HS PFD clock (USB1PFDCLK).
186 *
187 *END**************************************************************************/
188static void CLOCK_CONFIG_EnableUsbhs0PfdClock(uint8_t frac, uint8_t src)
189{
190 uint32_t fracFreq = (480000U * 18U / frac) * 1000U;
191
192 USBPHY->ANACTRL = (USBPHY->ANACTRL & ~(USBPHY_ANACTRL_PFD_FRAC_MASK | USBPHY_ANACTRL_PFD_CLK_SEL_MASK)) |
193 (USBPHY_ANACTRL_PFD_FRAC(frac) | USBPHY_ANACTRL_PFD_CLK_SEL(src));
194
195 USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
196 while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
197 {
198 }
199
200 if (0U == src)
201 {
202 CLOCK_SetExtPllFreq(g_xtal0Freq);
203 }
204 else if (1U == src)
205 {
206 CLOCK_SetExtPllFreq(fracFreq / 4U);
207 }
208 else if (2U == src)
209 {
210 CLOCK_SetExtPllFreq(fracFreq / 2U);
211 }
212 else
213 {
214 CLOCK_SetExtPllFreq(fracFreq);
215 }
216}
217
218/*FUNCTION**********************************************************************
219 *
220 * Function Name : CLOCK_CONFIG_SetUsbSlowClock
221 * Description : Set USB slow clock source.
222 * Param src : The value to set USB slow clock source.
223 *
224 *END**************************************************************************/
225static void CLOCK_CONFIG_SetUsbSlowClock(uint8_t src)
226{
227 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_USBSLSRC_MASK) | SIM_SOPT2_USBSLSRC(src));
228}
229
230/*FUNCTION**********************************************************************
231 *
232 * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
233 * Description : Configure FLL external reference divider (FRDIV).
234 * Param frdiv : The value to set FRDIV.
235 *
236 *END**************************************************************************/
237static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
238{
239 MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
240}
241
242/*******************************************************************************
243 ************************ BOARD_InitBootClocks function ************************
244 ******************************************************************************/
245void BOARD_InitBootClocks(void)
246{
247 BOARD_BootClockHSRUN();
248}
249
250/*******************************************************************************
251 ********************* Configuration BOARD_BootClockHSRUN **********************
252 ******************************************************************************/
253/* clang-format off */
254/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
255!!Configuration
256name: BOARD_BootClockHSRUN
257called_from_default_init: true
258outputs:
259- {id: Bus_clock.outFreq, value: 75 MHz}
260- {id: CLKOUT.outFreq, value: 75 MHz}
261- {id: Core_clock.outFreq, value: 150 MHz}
262- {id: ERCLK32K.outFreq, value: 32.768 kHz}
263- {id: FLEXIOCLK.outFreq, value: 12 MHz}
264- {id: Flash_clock.outFreq, value: 25 MHz}
265- {id: FlexBus_clock.outFreq, value: 75 MHz}
266- {id: IRC48MCLK.outFreq, value: 48 MHz}
267- {id: LPO_clock.outFreq, value: 1 kHz}
268- {id: LPUARTCLK.outFreq, value: 12 MHz}
269- {id: MCGFFCLK.outFreq, value: 375 kHz}
270- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
271- {id: MCGPLLCLK.outFreq, value: 150 MHz}
272- {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
273- {id: OSCERCLK.outFreq, value: 12 MHz}
274- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
275- {id: PLLFLLCLK.outFreq, value: 48 MHz}
276- {id: RTC_CLKOUT.outFreq, value: 1 Hz}
277- {id: SDHCCLK.outFreq, value: 12 MHz}
278- {id: System_clock.outFreq, value: 150 MHz}
279- {id: TPMCLK.outFreq, value: 48 MHz}
280- {id: TRACECLKIN.outFreq, value: 75 MHz}
281- {id: USB1PFDCLK.outFreq, value: 180 MHz}
282- {id: USB48MCLK.outFreq, value: 48 MHz}
283- {id: USBPHYPLLCLK.outFreq, value: 480 MHz}
284- {id: USBSLCLK.outFreq, value: 32.768 kHz}
285settings:
286- {id: MCGMode, value: PEE}
287- {id: USBPHYConfig, value: PLL_PFD}
288- {id: powerMode, value: HSRUN}
289- {id: CLKOUTConfig, value: 'yes'}
290- {id: FLEXIOClkConfig, value: 'yes'}
291- {id: LPUARTClkConfig, value: 'yes'}
292- {id: MCG.FRDIV.scale, value: '32', locked: true}
293- {id: MCG.IREFS.sel, value: MCG.FRDIV}
294- {id: MCG.PLLS.sel, value: MCG.PLLCS}
295- {id: MCG.PRDIV.scale, value: '1', locked: true}
296- {id: MCG.VDIV.scale, value: '25', locked: true}
297- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
298- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
299- {id: MCG_C2_RANGE0_CFG, value: Very_high}
300- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
301- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled}
302- {id: MCG_C5_PLLSTEN0_CFG, value: Enabled}
303- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
304- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
305- {id: RTCCLKOUTConfig, value: 'yes'}
306- {id: RTC_CR_OSCE_CFG, value: Enabled}
307- {id: SDHCClkConfig, value: 'yes'}
308- {id: SIM.FLEXIOSRCSEL.sel, value: OSC.OSCERCLK}
309- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
310- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
311- {id: SIM.OUTDIV2.scale, value: '2', locked: true}
312- {id: SIM.OUTDIV3.scale, value: '2', locked: true}
313- {id: SIM.OUTDIV4.scale, value: '6', locked: true}
314- {id: SIM.PLLFLLDIV.scale, value: '1', locked: true}
315- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
316- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
317- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLDIV}
318- {id: SIM.TRACECLKSEL.sel, value: SIM.TRACEDIV}
319- {id: SIM.TRACEDIV.scale, value: '2', locked: true}
320- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
321- {id: TPMClkConfig, value: 'yes'}
322- {id: TraceClkConfig, value: 'yes'}
323- {id: USBClkConfig, value: 'yes'}
324- {id: USBPHY.DIV.scale, value: '40', locked: true}
325- {id: USBPHY.NO_DIV.scale, value: '1', locked: true}
326- {id: USBPHY.PFD_CLK_SEL.sel, value: USBPHY.PFD_CLK_DIV2}
327- {id: USBPHY.PFD_FRAC_DIV.scale, value: '24', locked: true}
328sources:
329- {id: IRC48M.IRC48M.outFreq, value: 48 MHz}
330- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
331- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true}
332- {id: SIM.USBCLK_EXT.outFreq, value: 48 MHz, enabled: true}
333 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
334/* clang-format on */
335
336/*******************************************************************************
337 * Variables for BOARD_BootClockHSRUN configuration
338 ******************************************************************************/
339const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
340 .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
341 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
342 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
343 .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
344 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
345 .drs = kMCG_DrsLow, /* Low frequency range */
346 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
347 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
348 .pll0Config =
349 {
350 .enableMode =
351 kMCG_PllEnableIndependent |
352 kMCG_PllEnableInStop, /* MCGPLLCLK enabled independently of MCG clock mode as well as in STOP mode */
353 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
354 .vdiv = 0x9U, /* VCO divider: multiplied by 25 */
355 },
356 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
357};
358const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
359 .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
360 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
361 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
362 .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
363 .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
364};
365const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
366 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
367 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
368 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
369 .oscerConfig = {
370 .enableMode =
371 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
372 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
373 }};
374
375/*******************************************************************************
376 * Code for BOARD_BootClockHSRUN configuration
377 ******************************************************************************/
378void BOARD_BootClockHSRUN(void)
379{
380 /* Set HSRUN power mode */
381 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
382 SMC_SetPowerModeHsrun(SMC);
383 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
384 {
385 }
386 /* Set the system clock dividers in SIM to safe value. */
387 CLOCK_SetSimSafeDivs();
388 /* Configure RTC clock including enabling RTC oscillator. */
389 CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
390 /* Initializes OSC0 according to board configuration. */
391 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
392 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
393 /* Configure the Internal Reference clock (MCGIRCLK). */
394 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
395 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
396 /* Set USB slow clock. */
397 CLOCK_CONFIG_SetUsbSlowClock(SIM_USB_SLOW_CLK_SEL_MCGIRCLK_CLK);
398 /* Configure USBPHY PLL. */
399 CLOCK_CONFIG_EnableUsbhs0PhyPllClock(oscConfig_BOARD_BootClockHSRUN.freq);
400 /* Configure USB PFD clock. */
401 CLOCK_CONFIG_EnableUsbhs0PfdClock(USBPHY_PFD_FRAC_DIV_24, USBPHY_PFD_CLK_SEL_PFD_CLK_DIV_2);
402 /* Configure FLL external reference divider (FRDIV). */
403 CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
404 /* Set MCG to PEE mode. */
405 CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, mcgConfig_BOARD_BootClockHSRUN.pllcs,
406 &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
407 /* Set the clock configuration in SIM module. */
408 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
409 /* Set SystemCoreClock variable. */
410 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
411 /* Set RTC_CLKOUT source. */
412 CLOCK_SetRtcClkOutClock(SIM_RTC_CLKOUT_SEL_RTC1HZCLK_CLK);
413 /* Enable USB FS clock. */
414 CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, SIM_USB_CLK_48000000HZ);
415 /* Set SDHC clock source. */
416 CLOCK_SetSdhc0Clock(SIM_SDHC_CLK_SEL_OSCERCLK_CLK);
417 /* Set LPUART clock source. */
418 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_OSCERCLK_CLK);
419 /* Set FLEXIO clock source. */
420 CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_OSCERCLK_CLK);
421 /* Set TPM clock source. */
422 CLOCK_SetTpmClock(SIM_TPM_CLK_SEL_PLLFLLSEL_CLK);
423 /* Set CLKOUT source. */
424 CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
425 /* Set debug trace clock source. */
426 CLOCK_SetTraceClock(SIM_TRACE_CLK_SEL_MCGOUTCLK_CLK, SIM_TRACE_CLK_DIV_2, SIM_TRACE_CLK_FRAC_1);
427}
428
429/*******************************************************************************
430 ********************* Configuration BOARD_BootClockVLPR ***********************
431 ******************************************************************************/
432/* clang-format off */
433/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
434!!Configuration
435name: BOARD_BootClockVLPR
436outputs:
437- {id: Bus_clock.outFreq, value: 4 MHz}
438- {id: Core_clock.outFreq, value: 4 MHz}
439- {id: Flash_clock.outFreq, value: 800 kHz}
440- {id: FlexBus_clock.outFreq, value: 4 MHz}
441- {id: LPO_clock.outFreq, value: 1 kHz}
442- {id: System_clock.outFreq, value: 4 MHz}
443settings:
444- {id: MCGMode, value: BLPI}
445- {id: powerMode, value: VLPR}
446- {id: MCG.CLKS.sel, value: MCG.IRCS}
447- {id: MCG.FCRDIV.scale, value: '1', locked: true}
448- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
449- {id: SIM.OUTDIV4.scale, value: '5'}
450sources:
451- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
452 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
453/* clang-format on */
454
455/*******************************************************************************
456 * Variables for BOARD_BootClockVLPR configuration
457 ******************************************************************************/
458const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
459 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
460 .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
461 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
462 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
463 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
464 .drs = kMCG_DrsLow, /* Low frequency range */
465 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
466 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
467 .pll0Config =
468 {
469 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
470 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
471 .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
472 },
473 .pllcs = kMCG_PllClkSelPll0, /* PLL0 output clock is selected */
474};
475const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
476 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
477 .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
478 .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
479 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
480 .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
481};
482const osc_config_t oscConfig_BOARD_BootClockVLPR = {
483 .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
484 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
485 .workMode = kOSC_ModeExt, /* Use external clock */
486 .oscerConfig = {
487 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
488 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
489 }};
490
491/*******************************************************************************
492 * Code for BOARD_BootClockVLPR configuration
493 ******************************************************************************/
494void BOARD_BootClockVLPR(void)
495{
496 /* Set the system clock dividers in SIM to safe value. */
497 CLOCK_SetSimSafeDivs();
498 /* Initializes OSC0 according to board configuration. */
499 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockVLPR);
500 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockVLPR.freq);
501 /* Set MCG to BLPI mode. */
502 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
503 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
504 /* Select the MCG external reference clock. */
505 CLOCK_SetExternalRefClkConfig(mcgConfig_BOARD_BootClockVLPR.oscsel);
506 /* Set the clock configuration in SIM module. */
507 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
508 /* Set VLPR power mode. */
509 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
510#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
511 SMC_SetPowerModeVlpr(SMC, false);
512#else
513 SMC_SetPowerModeVlpr(SMC);
514#endif
515 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
516 {
517 }
518 /* Set SystemCoreClock variable. */
519 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
520}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.h
new file mode 100644
index 000000000..e7b378105
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/clock_config.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */
22#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */
23
24/*******************************************************************************
25 ************************ BOARD_InitBootClocks function ************************
26 ******************************************************************************/
27
28#if defined(__cplusplus)
29extern "C" {
30#endif /* __cplusplus*/
31
32/*!
33 * @brief This function executes default configuration of clocks.
34 *
35 */
36void BOARD_InitBootClocks(void);
37
38#if defined(__cplusplus)
39}
40#endif /* __cplusplus*/
41
42/*******************************************************************************
43 ********************* Configuration BOARD_BootClockHSRUN **********************
44 ******************************************************************************/
45/*******************************************************************************
46 * Definitions for BOARD_BootClockHSRUN configuration
47 ******************************************************************************/
48#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
49
50/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
51 */
52extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
53/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
54 */
55extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
56/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
57 */
58extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
59
60/*******************************************************************************
61 * API for BOARD_BootClockHSRUN configuration
62 ******************************************************************************/
63#if defined(__cplusplus)
64extern "C" {
65#endif /* __cplusplus*/
66
67/*!
68 * @brief This function executes configuration of clocks.
69 *
70 */
71void BOARD_BootClockHSRUN(void);
72
73#if defined(__cplusplus)
74}
75#endif /* __cplusplus*/
76
77/*******************************************************************************
78 ********************* Configuration BOARD_BootClockVLPR ***********************
79 ******************************************************************************/
80/*******************************************************************************
81 * Definitions for BOARD_BootClockVLPR configuration
82 ******************************************************************************/
83#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
84
85/*! @brief MCG set for BOARD_BootClockVLPR configuration.
86 */
87extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
88/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
89 */
90extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
91/*! @brief OSC set for BOARD_BootClockVLPR configuration.
92 */
93extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
94
95/*******************************************************************************
96 * API for BOARD_BootClockVLPR configuration
97 ******************************************************************************/
98#if defined(__cplusplus)
99extern "C" {
100#endif /* __cplusplus*/
101
102/*!
103 * @brief This function executes configuration of clocks.
104 *
105 */
106void BOARD_BootClockVLPR(void);
107
108#if defined(__cplusplus)
109}
110#endif /* __cplusplus*/
111
112#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.c
new file mode 100644
index 000000000..69af4a74c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
9!!GlobalInfo
10product: Peripherals v1.0
11 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
12
13/*******************************************************************************
14 * Included files
15 ******************************************************************************/
16#include "peripherals.h"
17
18/*******************************************************************************
19 * BOARD_InitBootPeripherals function
20 ******************************************************************************/
21void BOARD_InitBootPeripherals(void)
22{
23}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.h
new file mode 100644
index 000000000..36b2e05a7
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/peripherals.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PERIPHERALS_H_
9#define _PERIPHERALS_H_
10
11#if defined(__cplusplus)
12extern "C" {
13#endif /*_cplusplus. */
14/*******************************************************************************
15 * BOARD_InitBootPeripherals function
16 ******************************************************************************/
17void BOARD_InitBootPeripherals(void);
18
19#if defined(__cplusplus)
20}
21#endif /*_cplusplus. */
22
23#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/pin_mux.c
new file mode 100644
index 000000000..0554472ba
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/frdmk28fa/project_template/pin_mux.c
@@ -0,0 +1,1745 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* clang-format off */
9/*
10 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11!!GlobalInfo
12product: Pins v5.0
13processor: MK28FN2M0Axxx15
14package_id: MK28FN2M0AVMI15
15mcu_data: ksdk2_0
16processor_version: 0.0.8
17board: FRDM-K28FA
18pin_labels:
19- {pin_num: L9, pin_signal: PTA4/LLWU_P3/FTM0_CH1/FXIO0_D14/NMI_b, label: SW2, identifier: SW2}
20- {pin_num: A6, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/LPUART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/FXIO0_D22, label: SW3, identifier: SW3}
21- {pin_num: N13, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/TPM_CLKIN0, label: 'Y2[1]/EXTAL', identifier: EXTAL0}
22- {pin_num: M13, pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1/LPTMR1_ALT1/TPM_CLKIN1, label: 'Y2[3]/XTAL', identifier: XTAL0}
23- {pin_num: N5, pin_signal: XTAL32, label: 'Y1[1]/XTAL32_RTC', identifier: XTAL32K}
24- {pin_num: N6, pin_signal: EXTAL32, label: 'Y1[2]/EXTAL32_RTC', identifier: EXTAL32K}
25- {pin_num: E2, pin_signal: PTE6/LLWU_P16/FXIO0_D12/LPUART3_CTS_b/I2S0_MCLK/QSPI0B_DATA3/FTM3_CH1/SDHC0_D4, label: 'J1[7]/D1[1]/LEDRGB_RED', identifier: LED_RED}
26- {pin_num: E3, pin_signal: PTE7/FXIO0_D13/LPUART3_RTS_b/I2S0_RXD0/QSPI0B_SCLK/FTM3_CH2/QSPI0A_SS1_B, label: 'J1[15]/D1[4]/LEDRGB_GREEN', identifier: LED_GREEN}
27- {pin_num: E4, pin_signal: PTE8/I2S0_RXD1/FXIO0_D14/I2S0_RX_FS/QSPI0B_DATA0/FTM3_CH3/SDHC0_D5, label: 'J1[13]/D1[3]/LEDRGB_BLUE', identifier: LED_BLUE}
28- {pin_num: A7, pin_signal: PTC25/LPUART0_RX/FB_A4/SDRAM_D4/QSPI0A_SCLK, label: LPUART0_RX_TGTMCU, identifier: DEBUG_UART_RX}
29- {pin_num: J9, pin_signal: PTA31/I2C3_SCL/LPUART3_RTS_b/FB_A10/SDRAM_D10/I2S1_RX_BCLK, label: 'J1[3]/I2S0_TX_FS'}
30- {pin_num: H10, pin_signal: PTA30/I2C3_SDA/LPUART3_CTS_b/FB_A11/SDRAM_D11/I2S1_RX_FS, label: 'J1[1]/I2S0_TX_BCLK'}
31- {pin_num: C6, pin_signal: PTC28/I2C3_SDA/FB_A1/SDRAM_D1/QSPI0A_DATA1, label: 'U6[6]/I2C SDA', identifier: I2C_SDA}
32- {pin_num: B6, pin_signal: PTC29/I2C3_SCL/FB_A0/SDRAM_D0/QSPI0A_SS0_B, label: 'U6[4]/I2C_SCL', identifier: I2C_SCL}
33- {pin_num: E6, pin_signal: PTC26/LPUART0_CTS_b/FB_A3/SDRAM_D3/QSPI0A_DATA0, label: 'U6[11]/INT1_FXOS8700CQ_R', identifier: ACCEL_INT1}
34- {pin_num: C1, pin_signal: PTE2/LLWU_P1/SPI1_SOUT/LPUART1_CTS_b/SDHC0_DCLK/QSPI0A_DATA0/FXIO0_D0/SPI1_SCK, label: 'U11[5]/QSPIA_DATA0', identifier: QSPIA_DATA0}
35- {pin_num: E1, pin_signal: PTE4/LLWU_P2/SPI1_SIN/LPUART3_TX/SDHC0_D3/QSPI0A_DATA1, label: 'U11[2]/QSPIA_DATA1', identifier: QSPIA_DATA1}
36- {pin_num: D1, pin_signal: PTE3/SPI1_PCS2/LPUART1_RTS_b/SDHC0_CMD/QSPI0A_DATA2/FXIO0_D1/SPI1_SOUT, label: 'U11[3]/QSPIA_DATA2', identifier: QSPIA_DATA2}
37- {pin_num: A1, pin_signal: PTE0/SPI1_PCS1/LPUART1_TX/SDHC0_D1/QSPI0A_DATA3/I2C1_SDA/RTC_CLKOUT, label: 'U11[7]/QSPIA_DATA3', identifier: QSPIA_DATA3}
38- {pin_num: B1, pin_signal: PTE1/LLWU_P0/SPI1_SCK/LPUART1_RX/SDHC0_D0/QSPI0A_SCLK/I2C1_SCL/SPI1_SIN, label: 'U11[6]/QSPIA_SCLK', identifier: QSPIA_SCLK}
39- {pin_num: D2, pin_signal: PTE5/SPI1_PCS0/LPUART3_RX/SDHC0_D2/QSPI0A_SS0_B/FTM3_CH0/USB0_SOF_OUT, label: 'U11[1]/QSPIA_SS', identifier: QSPIA_SS}
40- {pin_num: H1, pin_signal: USB1_DM, label: 'J24[2]USB_CONN_DN', identifier: K28_MICRO_USB_DM_DCD;K28_MICRO_USB_DM_PHY;K28_MICRO_USB_DM_HS}
41- {pin_num: J1, pin_signal: USB1_DP, label: 'J24[3]USB_CONN_DP', identifier: K28_MICRO_USB_DP_DCD;K28_MICRO_USB_DP_PHY;K28_MICRO_USB_DP_HS}
42- {pin_num: H12, pin_signal: PTA28/LPUART3_TX/SDHC0_D3/FB_A25/I2S1_RXD1, label: 'J19[P2]/SDHC0_D3', identifier: SDHC0_D3}
43- {pin_num: J11, pin_signal: PTA25/LPUART2_RX/SDHC0_D0/FB_A14/SDRAM_D14/FB_A28/I2S1_TX_FS, label: 'J19[P7]/SDHC0_D0', identifier: SDHC0_D0}
44- {pin_num: H11, pin_signal: PTA29/LPUART3_RX/SDHC0_D2/FB_A24/I2S1_RXD0, label: 'J19[P1]/SDHC0_D2', identifier: SDHC0_D2}
45- {pin_num: K11, pin_signal: PTA24/LPUART2_TX/SDHC0_D1/FB_A15/SDRAM_D15/FB_A29/I2S1_TX_BCLK, label: 'J19[P8]/SDHC0_D1', identifier: SDHC0_D1}
46- {pin_num: J10, pin_signal: PTA26/LPUART2_CTS_b/SDHC0_DCLK/FB_A13/SDRAM_D13/FB_A27/I2S1_TXD0, label: 'J19[P5]/SDHC0_DCLK', identifier: SDHC0_DCLK}
47- {pin_num: H13, pin_signal: PTA27/LPUART2_RTS_b/SDHC0_CMD/FB_A12/SDRAM_D12/FB_A26/I2S1_TXD1, label: 'J19[P3]/SDHC0_CMD', identifier: SDHC0_CMD}
48- {pin_num: F13, pin_signal: PTB5/FTM2_FLT0, label: 'J19[G1]/SD_CARD_DETECT', identifier: SDCARD_CARD_DETECTION}
49- {pin_num: N4, pin_signal: ADC0_SE16, label: 'Q5[2]/LIGHT_SENSOR', identifier: LIGHT_SENSOR}
50- {pin_num: C9, pin_signal: CMP0_IN3/PTC9/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/SDRAM_A14/FTM2_FLT0/FXIO0_D17, label: 'U13[J8]/SDRAM_A14', identifier: SDRAM_A14}
51- {pin_num: A8, pin_signal: PTC10/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5/SDRAM_A13/FXIO0_D18, label: 'U13[J7]/SDRAM_A13', identifier: SDRAM_A13}
52- {pin_num: A4, pin_signal: PTD2/LLWU_P13/SPI0_SOUT/LPUART2_RX/FTM3_CH2/FB_AD4/SDRAM_A12/I2C0_SCL, label: 'U13[J3]/SDRAM_A12', identifier: SDRAM_A12}
53- {pin_num: B4, pin_signal: PTD3/SPI0_SIN/LPUART2_TX/FTM3_CH3/FB_AD3/SDRAM_A11/I2C0_SDA, label: 'U13[J2]/SDRAM_A11', identifier: SDRAM_A11}
54- {pin_num: B5, pin_signal: PTD4/LLWU_P14/SPI0_PCS1/LPUART0_RTS_b/FTM0_CH4/FB_AD2/SDRAM_A10/EWM_IN/SPI1_PCS0, label: 'U13[H3]/SDRAM_A10', identifier: SDRAM_A10}
55- {pin_num: C4, pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/LPUART0_CTS_b/FTM0_CH5/FB_AD1/SDRAM_A9/EWM_OUT_b/SPI1_SCK, label: 'U13[H2]/SDRAM_A9', identifier: SDRAM_A9}
56- {pin_num: A11, pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/I2S0_RXD0/FB_AD10/SDRAM_A18/CMP0_OUT/FTM0_CH2, label: 'U13[H1]/SDRAM_A18', identifier: SDRAM_A18}
57- {pin_num: B11, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/LPUART1_TX/FTM0_CH3/FB_AD11/SDRAM_A19/CMP1_OUT, label: 'U13[G3]/SDRAM_A19', identifier: SDRAM_A19}
58- {pin_num: E5, pin_signal: PTD7/CMT_IRO/LPUART0_TX/FTM0_CH7/SDRAM_CKE/FTM0_FLT1/SPI1_SIN, label: 'U13[F3]/SDRAM_CKE', identifier: SDRAM_CKE}
59- {pin_num: E7, pin_signal: PTC17/LPUART3_TX/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b/SDRAM_DQM3, label: 'U13[F1]/SDRAM_DQM3', identifier: SDRAM_DQM3}
60- {pin_num: B8, pin_signal: PTC13/LPUART4_CTS_b/FTM_CLKIN1/FB_AD26/SDRAM_D26/TPM_CLKIN1, label: 'U13[D1]/SDRAM_D26', identifier: SDRAM_D26}
61- {pin_num: C8, pin_signal: PTC14/LPUART4_RX/FB_AD25/SDRAM_D25/FXIO0_D20, label: 'U13[D2]/SDRAM_D25', identifier: SDRAM_D25}
62- {pin_num: D8, pin_signal: PTC15/LPUART4_TX/FB_AD24/SDRAM_D24/FXIO0_D21, label: 'U13[E1]/SDRAM_D24', identifier: SDRAM_D24}
63- {pin_num: E8, pin_signal: PTC16/LPUART3_RX/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b/SDRAM_DQM2, label: 'U13[E8]/SDRAM_DQM2', identifier: SDRAM_DQM2}
64- {pin_num: F8, pin_signal: PTB16/SPI1_SOUT/LPUART0_RX/FTM_CLKIN0/FB_AD17/SDRAM_D17/EWM_IN/TPM_CLKIN0, label: 'U13[B9]/SDRAM_D17', identifier: SDRAM_D17}
65- {pin_num: B9, pin_signal: PTC12/LPUART4_RTS_b/FTM_CLKIN0/FB_AD27/SDRAM_D27/FTM3_FLT0/TPM_CLKIN0, label: 'U13[C2]/SDRAM_D27', identifier: SDRAM_D27}
66- {pin_num: D9, pin_signal: PTB21/SPI2_SCK/FB_AD30/SDRAM_D30/CMP1_OUT/FXIO0_D9, label: 'U13[B1]/SDRAM_D30', identifier: SDRAM_D30}
67- {pin_num: F9, pin_signal: PTB9/SPI1_PCS1/LPUART3_CTS_b/FB_AD20/SDRAM_D20, label: 'U13[C8]/SDRAM_D20', identifier: SDRAM_D20}
68- {pin_num: G9, pin_signal: PTB10/SPI1_PCS0/LPUART3_RX/I2C2_SCL/FB_AD19/SDRAM_D19/FTM0_FLT1/FXIO0_D4, label: 'U13[C9]/SDRAM_D19', identifier: SDRAM_D19}
69- {pin_num: B10, pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB0_SOF_OUT/I2S0_RX_FS/FB_AD8/SDRAM_A16/FXIO0_D15, label: 'U13[H7]/SDRAM_A16', identifier: SDRAM_A16}
70- {pin_num: C10, pin_signal: CMP0_IN2/PTC8/FTM3_CH4/I2S0_MCLK/FB_AD7/SDRAM_A15/FXIO0_D16, label: 'U13[H8]/SDRAM_A15', identifier: SDRAM_A15}
71- {pin_num: D10, pin_signal: PTB20/SPI2_PCS0/FB_AD31/SDRAM_D31/CMP0_OUT/FXIO0_D8, label: 'U13[A2]/SDRAM_D31', identifier: SDRAM_D31}
72- {pin_num: F10, pin_signal: PTB8/LPUART3_RTS_b/FB_AD21/SDRAM_D21, label: 'U13[D9]/SDRAM_D21', identifier: SDRAM_D21}
73- {pin_num: G10, pin_signal: ADC0_SE13/PTB3/I2C0_SDA/LPUART0_CTS_b/SDRAM_CS0_b/FTM0_FLT0/FXIO0_D3, label: 'U13[G9]/SDRAM_CS0_b', identifier: SDRAM_CS0_b}
74- {pin_num: F11, pin_signal: PTB7/FB_AD22/SDRAM_D22, label: 'U13[D8]/SDRAM_D22', identifier: SDRAM_D22}
75- {pin_num: G11, pin_signal: ADC0_SE12/PTB2/I2C0_SCL/LPUART0_RTS_b/SDRAM_WE_b/FTM0_FLT3/FXIO0_D2, label: 'U13[F9]/SDRAM_WE_b', identifier: SDRAM_WE_b}
76- {pin_num: B12, pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/LPUART1_RTS_b/FTM0_CH0/FB_AD13/SDRAM_A21/I2S0_TXD0/FXIO0_D13, label: 'U13[G2]/SDRAM_A21', identifier: SDRAM_A21}
77- {pin_num: C12, pin_signal: PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28/SDRAM_D28/FXIO0_D11, label: 'U13[C1]/SDRAM_D28', identifier: SDRAM_D28}
78- {pin_num: D12, pin_signal: PTB18/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/SDRAM_A23/FTM2_QD_PHA/TPM2_CH0/FXIO0_D6, label: 'U13[G8]/SDRAM_A23', identifier: SDRAM_A23}
79- {pin_num: F12, pin_signal: PTB6/FB_AD23/SDRAM_D23, label: 'U13[E9]/SDRAM_D23', identifier: SDRAM_D23}
80- {pin_num: G12, pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/SDRAM_RAS_b/FTM1_QD_PHB/TPM1_CH1/FXIO0_D1, label: 'U13[F8]/SDRAM_RAS_b', identifier: SDRAM_RAS_b}
81- {pin_num: A12, pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/LPUART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK, label: 'U13[F2]/CLKOUT', identifier: CLKOUT}
82- {pin_num: A13, pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/LPUART1_CTS_b/FTM0_CH1/FB_AD12/SDRAM_A20/I2S0_TX_FS, label: 'U13[H9]/SDRAM_A20', identifier: SDRAM_A20}
83- {pin_num: B13, pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/USB0_SOF_OUT/FB_AD14/SDRAM_A22/I2S0_TXD1/FXIO0_D12, label: 'U13[G7]/SDRAM_A22', identifier: SDRAM_A22}
84- {pin_num: C13, pin_signal: PTB22/SPI2_SOUT/FB_AD29/SDRAM_D29/FXIO0_D10, label: 'U13[B2]/SDRAM_D29', identifier: SDRAM_D29}
85- {pin_num: D13, pin_signal: PTB17/SPI1_SIN/LPUART0_TX/FTM_CLKIN1/FB_AD16/SDRAM_D16/EWM_OUT_b/TPM_CLKIN1, label: 'U13[A8]/SDRAM_D16', identifier: SDRAM_D16}
86- {pin_num: E13, pin_signal: PTB11/SPI1_SCK/LPUART3_TX/I2C2_SDA/FB_AD18/SDRAM_D18/FTM0_FLT2/FXIO0_D5, label: 'U13[B8]/SDRAM_D18', identifier: SDRAM_D18}
87- {pin_num: G13, pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/SDRAM_CAS_b/FTM1_QD_PHA/TPM1_CH0/FXIO0_D0, label: 'U13[F7]/SDRAM_CAS_b', identifier: SDRAM_CAS_b}
88- {pin_num: J2, pin_signal: USB1_VBUS, label: 'J24[1]P5V0_USB_CONN_VBUS', identifier: P5V_K28_USB}
89- {pin_num: M11, pin_signal: PTA11/LLWU_P23/I2C2_SCL/FTM2_CH1/FXIO0_D17/FTM2_QD_PHB/TPM2_CH1/USB1_ID, label: 'J24[4]TC_USB_ID', identifier: USB_ID}
90- {pin_num: F2, pin_signal: VREG_IN0, label: VREG_IN0, identifier: VREG_IN0}
91- {pin_num: B7, pin_signal: PTC24/LPUART0_TX/FB_A5/SDRAM_D5/QSPI0A_DATA3, label: LPUART0_TX_TGTMCU, identifier: DEBUG_UART_TX}
92- {pin_num: K1, pin_signal: USB1_VSS, label: GND}
93- {pin_num: L1, pin_signal: ADC0_DM1, label: 'J3[1]/ADC0_DM1'}
94- {pin_num: M1, pin_signal: ADC0_DP1, label: 'J3[3]/ADC0_DP1'}
95- {pin_num: A2, pin_signal: PTD14/SPI2_SIN/FB_A22/FXIO0_D30, label: 'J27[25]/FXIO0_D30/J2[10]/Arduino_D12_SPI2_SIN'}
96- {pin_num: B2, pin_signal: PTD12/SPI2_SCK/FTM3_FLT0/FB_A20/FXIO0_D28, label: 'J27[23]/FXIO0_D28/J2[12]/Arduino_D13_SPI2_SCK'}
97- {pin_num: C2, pin_signal: PTD11/LLWU_P25/SPI2_PCS0/LPUART1_CTS_b/FB_A19/FXIO0_D27, label: 'J27[22]/FXIO0_D27'}
98- {pin_num: G2, pin_signal: VREG_OUT, label: GND}
99- {pin_num: H2, pin_signal: VREG_IN1, label: VREG_IN0}
100- {pin_num: A3, pin_signal: PTD15/SPI2_PCS1/FB_A23/FXIO0_D31, label: 'J27[26]/FXIO0_D31/J2[6]/Arduino_D10_SPI2_PCS1'}
101- {pin_num: B3, pin_signal: PTD13/SPI2_SOUT/FB_A21/FXIO0_D29, label: 'J27[24]/FXIO0_D29/J2[8]/ Arduino_D11_SPI2_SOUT '}
102- {pin_num: C3, pin_signal: VSS5, label: GND}
103- {pin_num: D3, pin_signal: PTD10/LPUART1_RTS_b/FB_A18/FXIO0_D26, label: 'J27[21]/FXIO0_D26'}
104- {pin_num: F3, pin_signal: PTE9/LLWU_P17/I2S0_TXD1/FXIO0_D15/I2S0_RX_BCLK/QSPI0B_DATA2/FTM3_CH4/SDHC0_D6, label: 'J1[9]/I2S0_RX_BCLK'}
105- {pin_num: G3, pin_signal: VSS28, label: GND}
106- {pin_num: J3, pin_signal: VDDA, label: VDD_K28F}
107- {pin_num: K3, pin_signal: VREFH, label: VREFH}
108- {pin_num: L3, pin_signal: VSSA46, label: GND}
109- {pin_num: N3, pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC0_SE22, label: 'J3[5]/VREF_OUT'}
110- {pin_num: D4, pin_signal: PTD9/I2C0_SDA/LPUART1_TX/FB_A17/FXIO0_D25, label: 'J27[20]/FXIO0_D25'}
111- {pin_num: F4, pin_signal: PTE10/LLWU_P18/I2C3_SDA/FXIO0_D16/I2S0_TXD0/QSPI0B_DATA1/FTM3_CH5/SDHC0_D7, label: 'J1[5]/I2S0_TXD0'}
112- {pin_num: G4, pin_signal: PTE11/I2C3_SCL/FXIO0_D17/I2S0_TX_FS/QSPI0B_SS0_B/FTM3_CH6/QSPI0A_DQS, label: 'J1[3]/I2S0_TX_FS'}
113- {pin_num: H4, pin_signal: PTE12/LPUART2_TX/I2S0_TX_BCLK/QSPI0B_DQS/FTM3_CH7/FXIO0_D2, label: 'J1[1]/I2S0_TX_BCLK'}
114- {pin_num: J4, pin_signal: VSSA45, label: GND}
115- {pin_num: K4, pin_signal: VREFL, label: GND}
116- {pin_num: L4, pin_signal: VSS184, label: GND}
117- {pin_num: M4, pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23, label: 'J3[13]/DAC0OUT'}
118- {pin_num: A5, pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/LPUART2_CTS_b/FTM3_CH1/FB_CS0_b/FXIO0_D23, label: 'J4[6]/Arduino_D16_ADC0_SE5b'}
119- {pin_num: C5, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/LPUART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, label: 'J4[8]/Arduino_D17_ADC0_SE7b'}
120- {pin_num: D5, pin_signal: PTD8/LLWU_P24/I2C0_SCL/LPUART1_RX/FB_A16/FXIO0_D24, label: 'J27[19]/FXIO0_D24'}
121- {pin_num: G5, pin_signal: VDDIO_E6, label: VDDIO_E_1V8}
122- {pin_num: H5, pin_signal: VDDIO_E17, label: VDDIO_E_1V8}
123- {pin_num: J5, pin_signal: VSS185, label: GND}
124- {pin_num: K5, pin_signal: VDD_CORE135, label: VDDCORE_1V2}
125- {pin_num: L5, pin_signal: VDD_CORE159, label: VDDCORE_1V2}
126- {pin_num: M5, pin_signal: RTC_WAKEUP_B, label: 'J3[7]/RTC_WAKEUP_B'}
127- {pin_num: D6, pin_signal: PTC27/LPUART0_RTS_b/FB_A2/SDRAM_D2/QSPI0A_DATA2, label: 'U6[16]/RST_FXOS8700CQ'}
128- {pin_num: G6, pin_signal: VDD72, label: VDD_K28F}
129- {pin_num: H6, pin_signal: VDD136, label: VDD_K28F}
130- {pin_num: M6, pin_signal: VBAT, label: VBAT}
131- {pin_num: C7, pin_signal: PTC19/LPUART3_CTS_b/FB_CS3_b/FB_BE7_0_BLS31_24_b/SDRAM_DQM0/FB_TA_b/QSPI0A_SS1_B, label: 'J2[2]/Arduino_D8'}
132- {pin_num: D7, pin_signal: PTC18/LPUART3_RTS_b/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b/SDRAM_DQM1, label: 'J1[16]/Arduino_D7'}
133- {pin_num: G7, pin_signal: VDD58, label: VDD_K28F}
134- {pin_num: H7, pin_signal: VDD105, label: VDD_K28F}
135- {pin_num: K7, pin_signal: PTA21/LLWU_P21/I2C0_SDA/LPUART4_RX/FXIO0_D9/EWM_IN, label: 'J27[18]/PDWN/TE'}
136- {pin_num: L7, pin_signal: PTA20/I2C0_SCL/LPUART4_TX/FTM_CLKIN1/FXIO0_D8/EWM_OUT_b/TPM_CLKIN1, label: 'J27[5]/FXIO_D8/VSync'}
137- {pin_num: N7, pin_signal: VSS/CORE_BYPASS, label: GND}
138- {pin_num: G8, pin_signal: VSS18, label: GND}
139- {pin_num: H8, pin_signal: VSS73, label: GND}
140- {pin_num: J8, pin_signal: VSS104, label: GND}
141- {pin_num: K8, pin_signal: PTA22/LPUART4_CTS_b/FXIO0_D6/RTC_CLKOUT/USB0_CLKIN, label: 'J27[7]/FXIO0_D6/PCLK', identifier: USB0_CLKIN}
142- {pin_num: L8, pin_signal: PTA23/LPUART4_RTS_b/FXIO0_D7, label: 'J27[6]/FXIO_D7/HREF'}
143- {pin_num: M8, pin_signal: PTA3/LPUART0_RTS_b/FTM0_CH0/FXIO0_D13/JTAG_TMS/SWD_DIO, label: 'J23[2]/SWD_DIO_TGTMCU'}
144- {pin_num: N8, pin_signal: PTA0/LPUART0_CTS_b/FTM0_CH5/FXIO0_D10/JTAG_TCLK/SWD_CLK, label: 'J17[1]/K28F_SWD_CLK'}
145- {pin_num: A9, pin_signal: PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/I2S0_RXD1/FB_RW_b/FXIO0_D19, label: 'J1[8]/Arduino_D3_FTM3_CH7'}
146- {pin_num: H9, pin_signal: PTB4/SDRAM_CS1_b/FTM1_FLT0, label: 'J1[6]/Arduino_D2'}
147- {pin_num: K9, pin_signal: ADC0_SE11/PTA8/I2C1_SCL/FTM1_CH0/FTM1_QD_PHA/TPM1_CH0/TRACE_D2, label: 'J4[4]/Arduino_D15_ADC0_SE11/J27[3]/I2C1_SCL'}
148- {pin_num: M9, pin_signal: PTA2/LPUART0_TX/FTM0_CH7/I2C3_SCL/FXIO0_D12/JTAG_TDO/TRACE_SWO, label: 'J23[6]/TRACE_SWO /J27[28]/INT'}
149- {pin_num: N9, pin_signal: PTA1/LPUART0_RX/FTM0_CH6/I2C3_SDA/FXIO0_D11/JTAG_TDI, label: 'J27[27]/GPIO0'}
150- {pin_num: A10, pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/SDRAM_A17/I2S0_MCLK/FXIO0_D14, label: 'J1[10]/Arduino_D4'}
151- {pin_num: E10, pin_signal: PTB14/LPUART0_RX/FB_A7/SDRAM_D7, label: 'U12[3]'}
152- {pin_num: K10, pin_signal: PTA9/I2C1_SDA/FTM1_CH1/FTM1_QD_PHB/TPM1_CH1/TRACE_D1, label: 'J27[4]/I2C1_SDA'}
153- {pin_num: L10, pin_signal: ADC0_SE10/PTA7/I2C2_SDA/FTM0_CH4/TRACE_D3, label: 'J4[2]/Arduino_D14_ADC0_SE10'}
154- {pin_num: M10, pin_signal: PTA6/I2C2_SCL/FTM0_CH3/CLKOUT/TRACE_CLKOUT, label: 'J27[8]/CLKOUT/XCLK'}
155- {pin_num: N10, pin_signal: PTA5/USB0_CLKIN/FTM0_CH2/FXIO0_D15/I2S0_TX_BCLK/JTAG_TRST_b, label: 'J27[17]/Camera_Reset'}
156- {pin_num: C11, pin_signal: VSS133, label: GND}
157- {pin_num: D11, pin_signal: PTB19/SDRAM_CKE/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB/TPM2_CH1/FXIO0_D7, label: 'J2[4]/Arduino_D9_FTM2_CH1'}
158- {pin_num: E11, pin_signal: PTB13/LPUART0_CTS_b/FTM1_CH1/FTM0_CH5/FB_A8/SDRAM_D8/FTM1_QD_PHB/TPM1_CH1, label: 'J1[14]/Arduino_D6_FTM1_CH1/FTM0_CH5'}
159- {pin_num: L11, pin_signal: PTA13/LLWU_P4/FTM1_CH1/TRACE_D3/FXIO0_D19/I2S0_TX_FS/FTM1_QD_PHB/TPM1_CH1, label: 'J27[13]/FXIO0_D19/CAM_D3'}
160- {pin_num: N11, pin_signal: PTA10/LLWU_P22/I2C2_SDA/FTM2_CH0/FXIO0_D16/FTM2_QD_PHA/TPM2_CH0/TRACE_D0, label: 'J27[16]/FXIO0_D16/CAM_D0'}
161- {pin_num: E12, pin_signal: PTB12/LPUART0_RTS_b/FTM1_CH0/FTM0_CH4/FB_A9/SDRAM_D9/FTM1_QD_PHA/TPM1_CH0, label: 'J1[12]/Arduino_D5_FTM1_CH0/FTM0_CH4'}
162- {pin_num: J12, pin_signal: PTA17/SPI0_SIN/LPUART0_RTS_b/FXIO0_D23/I2S0_MCLK/I2S1_MCLK, label: 'J27[9]/FXIO0_D23/CAM_D7'}
163- {pin_num: K12, pin_signal: PTA15/SPI0_SCK/LPUART0_RX/TRACE_D1/FXIO0_D21/I2S0_RXD0, label: 'J27[11]/FXIO0_D21/CAM_D5'}
164- {pin_num: L12, pin_signal: PTA12/FTM1_CH0/TRACE_CLKOUT/FXIO0_D18/I2S0_TXD0/FTM1_QD_PHA/TPM1_CH0, label: 'J27[14]/FXIO0_D18/CAM_D2'}
165- {pin_num: M12, pin_signal: VSS88, label: GND}
166- {pin_num: N12, pin_signal: VDD86, label: VDD_K28F}
167- {pin_num: J13, pin_signal: PTA16/SPI0_SOUT/LPUART0_CTS_b/TRACE_D0/FXIO0_D22/I2S0_RX_FS/I2S0_RXD1, label: 'J27[10]/FXIO0_D22/CAM_D6'}
168- {pin_num: K13, pin_signal: PTA14/SPI0_PCS0/LPUART0_TX/TRACE_D2/FXIO0_D20/I2S0_RX_BCLK/I2S0_TXD1, label: 'J27[12]/FXIO0_D20/CAM_D4'}
169- {pin_num: L13, pin_signal: RESET_b, label: 'J23[10]/J3[6]/RST_TGTMCU_b'}
170 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
171 */
172/* clang-format on */
173
174#include "fsl_common.h"
175#include "fsl_port.h"
176#include "fsl_gpio.h"
177#include "pin_mux.h"
178
179/* FUNCTION ************************************************************************************************************
180 *
181 * Function Name : BOARD_InitBootPins
182 * Description : Calls initialization functions.
183 *
184 * END ****************************************************************************************************************/
185void BOARD_InitBootPins(void)
186{
187 BOARD_InitPins();
188 BOARD_InitDEBUG_UARTPins();
189}
190
191/* clang-format off */
192/*
193 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
194BOARD_InitPins:
195- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
196- pin_list:
197 - {pin_num: M9, peripheral: TPIU, signal: SWO, pin_signal: PTA2/LPUART0_TX/FTM0_CH7/I2C3_SCL/FXIO0_D12/JTAG_TDO/TRACE_SWO, pull_select: down, pull_enable: disable}
198 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
199 */
200/* clang-format on */
201
202/* FUNCTION ************************************************************************************************************
203 *
204 * Function Name : BOARD_InitPins
205 * Description : Configures pin routing and optionally pin electrical features.
206 *
207 * END ****************************************************************************************************************/
208void BOARD_InitPins(void)
209{
210 /* Port A Clock Gate Control: Clock enabled */
211 CLOCK_EnableClock(kCLOCK_PortA);
212
213 /* PORTA2 (pin M9) is configured as TRACE_SWO */
214 PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt7);
215
216 PORTA->PCR[2] = ((PORTA->PCR[2] &
217 /* Mask bits to zero which are setting */
218 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
219
220 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
221 * corresponding PE field is set. */
222 | PORT_PCR_PS(kPORT_PullDown)
223
224 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
225 | PORT_PCR_PE(kPORT_PullDisable));
226}
227
228/* clang-format off */
229/*
230 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
231BOARD_InitButtonsPins:
232- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
233- pin_list:
234 - {pin_num: L9, peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FXIO0_D14/NMI_b, direction: INPUT, slew_rate: fast, open_drain: disable,
235 pull_select: up, pull_enable: enable, passive_filter: disable}
236 - {pin_num: A6, peripheral: GPIOD, signal: 'GPIO, 0', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/LPUART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/FXIO0_D22, direction: INPUT,
237 slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable, digital_filter: disable}
238 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
239 */
240/* clang-format on */
241
242/* FUNCTION ************************************************************************************************************
243 *
244 * Function Name : BOARD_InitButtonsPins
245 * Description : Configures pin routing and optionally pin electrical features.
246 *
247 * END ****************************************************************************************************************/
248void BOARD_InitButtonsPins(void)
249{
250 /* Port A Clock Gate Control: Clock enabled */
251 CLOCK_EnableClock(kCLOCK_PortA);
252 /* Port D Clock Gate Control: Clock enabled */
253 CLOCK_EnableClock(kCLOCK_PortD);
254
255 gpio_pin_config_t SW2_config = {
256 .pinDirection = kGPIO_DigitalInput,
257 .outputLogic = 0U
258 };
259 /* Initialize GPIO functionality on pin PTA4 (pin L9) */
260 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
261
262 gpio_pin_config_t SW3_config = {
263 .pinDirection = kGPIO_DigitalInput,
264 .outputLogic = 0U
265 };
266 /* Initialize GPIO functionality on pin PTD0 (pin A6) */
267 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
268
269 const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */
270 kPORT_PullUp,
271 /* Fast slew rate is configured */
272 kPORT_FastSlewRate,
273 /* Passive filter is disabled */
274 kPORT_PassiveFilterDisable,
275 /* Open drain is disabled */
276 kPORT_OpenDrainDisable,
277 /* Low drive strength is configured */
278 kPORT_LowDriveStrength,
279 /* Pin is configured as PTA4 */
280 kPORT_MuxAsGpio,
281 /* Pin Control Register fields [15:0] are not locked */
282 kPORT_UnlockRegister};
283 /* PORTA4 (pin L9) is configured as PTA4 */
284 PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
285 /* Configure digital filter */
286 PORT_EnablePinsDigitalFilter(
287 /* Digital filter is configured on port D */
288 PORTD,
289 /* Digital filter is configured for PORTD0 */
290 PORT_DFER_DFE_0_MASK,
291 /* Disable digital filter */
292 false);
293
294 const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
295 kPORT_PullUp,
296 /* Fast slew rate is configured */
297 kPORT_FastSlewRate,
298 /* Passive filter is disabled */
299 kPORT_PassiveFilterDisable,
300 /* Open drain is disabled */
301 kPORT_OpenDrainDisable,
302 /* Low drive strength is configured */
303 kPORT_LowDriveStrength,
304 /* Pin is configured as PTD0 */
305 kPORT_MuxAsGpio,
306 /* Pin Control Register fields [15:0] are not locked */
307 kPORT_UnlockRegister};
308 /* PORTD0 (pin A6) is configured as PTD0 */
309 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
310}
311
312/* clang-format off */
313/*
314 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
315BOARD_InitOSCPins:
316- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
317- pin_list:
318 - {pin_num: N13, peripheral: OSC, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/TPM_CLKIN0, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
319 pull_enable: no_init}
320 - {pin_num: M13, peripheral: OSC, signal: XTAL0, pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1/LPTMR1_ALT1/TPM_CLKIN1, slew_rate: no_init, open_drain: no_init,
321 pull_select: no_init, pull_enable: no_init}
322 - {pin_num: N5, peripheral: RTC, signal: XTAL32, pin_signal: XTAL32}
323 - {pin_num: N6, peripheral: RTC, signal: EXTAL32, pin_signal: EXTAL32}
324 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
325 */
326/* clang-format on */
327
328/* FUNCTION ************************************************************************************************************
329 *
330 * Function Name : BOARD_InitOSCPins
331 * Description : Configures pin routing and optionally pin electrical features.
332 *
333 * END ****************************************************************************************************************/
334void BOARD_InitOSCPins(void)
335{
336 /* Port A Clock Gate Control: Clock enabled */
337 CLOCK_EnableClock(kCLOCK_PortA);
338
339 /* PORTA18 (pin N13) is configured as EXTAL0 */
340 PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
341
342 /* PORTA19 (pin M13) is configured as XTAL0 */
343 PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
344}
345
346/* clang-format off */
347/*
348 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
349BOARD_InitLEDsPins:
350- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
351- pin_list:
352 - {pin_num: E2, peripheral: GPIOE, signal: 'GPIO, 6', pin_signal: PTE6/LLWU_P16/FXIO0_D12/LPUART3_CTS_b/I2S0_MCLK/QSPI0B_DATA3/FTM3_CH1/SDHC0_D4, direction: OUTPUT,
353 gpio_init_state: 'true', slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
354 - {pin_num: E3, peripheral: GPIOE, signal: 'GPIO, 7', pin_signal: PTE7/FXIO0_D13/LPUART3_RTS_b/I2S0_RXD0/QSPI0B_SCLK/FTM3_CH2/QSPI0A_SS1_B, direction: OUTPUT, gpio_init_state: 'true',
355 slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
356 - {pin_num: E4, peripheral: GPIOE, signal: 'GPIO, 8', pin_signal: PTE8/I2S0_RXD1/FXIO0_D14/I2S0_RX_FS/QSPI0B_DATA0/FTM3_CH3/SDHC0_D5, direction: OUTPUT, gpio_init_state: 'true',
357 slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
358 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
359 */
360/* clang-format on */
361
362/* FUNCTION ************************************************************************************************************
363 *
364 * Function Name : BOARD_InitLEDsPins
365 * Description : Configures pin routing and optionally pin electrical features.
366 *
367 * END ****************************************************************************************************************/
368void BOARD_InitLEDsPins(void)
369{
370 /* Port E Clock Gate Control: Clock enabled */
371 CLOCK_EnableClock(kCLOCK_PortE);
372
373 gpio_pin_config_t LED_RED_config = {
374 .pinDirection = kGPIO_DigitalOutput,
375 .outputLogic = 1U
376 };
377 /* Initialize GPIO functionality on pin PTE6 (pin E2) */
378 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
379
380 gpio_pin_config_t LED_GREEN_config = {
381 .pinDirection = kGPIO_DigitalOutput,
382 .outputLogic = 1U
383 };
384 /* Initialize GPIO functionality on pin PTE7 (pin E3) */
385 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
386
387 gpio_pin_config_t LED_BLUE_config = {
388 .pinDirection = kGPIO_DigitalOutput,
389 .outputLogic = 1U
390 };
391 /* Initialize GPIO functionality on pin PTE8 (pin E4) */
392 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
393
394 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
395 kPORT_PullDisable,
396 /* Fast slew rate is configured */
397 kPORT_FastSlewRate,
398 /* Passive filter is disabled */
399 kPORT_PassiveFilterDisable,
400 /* Open drain is disabled */
401 kPORT_OpenDrainDisable,
402 /* Low drive strength is configured */
403 kPORT_LowDriveStrength,
404 /* Pin is configured as PTE6 */
405 kPORT_MuxAsGpio,
406 /* Pin Control Register fields [15:0] are not locked */
407 kPORT_UnlockRegister};
408 /* PORTE6 (pin E2) is configured as PTE6 */
409 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
410
411 const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
412 kPORT_PullDisable,
413 /* Fast slew rate is configured */
414 kPORT_FastSlewRate,
415 /* Passive filter is disabled */
416 kPORT_PassiveFilterDisable,
417 /* Open drain is disabled */
418 kPORT_OpenDrainDisable,
419 /* Low drive strength is configured */
420 kPORT_LowDriveStrength,
421 /* Pin is configured as PTE7 */
422 kPORT_MuxAsGpio,
423 /* Pin Control Register fields [15:0] are not locked */
424 kPORT_UnlockRegister};
425 /* PORTE7 (pin E3) is configured as PTE7 */
426 PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
427
428 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
429 kPORT_PullDisable,
430 /* Fast slew rate is configured */
431 kPORT_FastSlewRate,
432 /* Passive filter is disabled */
433 kPORT_PassiveFilterDisable,
434 /* Open drain is disabled */
435 kPORT_OpenDrainDisable,
436 /* Low drive strength is configured */
437 kPORT_LowDriveStrength,
438 /* Pin is configured as PTE8 */
439 kPORT_MuxAsGpio,
440 /* Pin Control Register fields [15:0] are not locked */
441 kPORT_UnlockRegister};
442 /* PORTE8 (pin E4) is configured as PTE8 */
443 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
444}
445
446/* clang-format off */
447/*
448 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
449BOARD_InitDEBUG_UARTPins:
450- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
451- pin_list:
452 - {pin_num: B7, peripheral: LPUART0, signal: TX, pin_signal: PTC24/LPUART0_TX/FB_A5/SDRAM_D5/QSPI0A_DATA3, direction: OUTPUT, slew_rate: fast, open_drain: disable,
453 pull_select: down, pull_enable: disable}
454 - {pin_num: A7, peripheral: LPUART0, signal: RX, pin_signal: PTC25/LPUART0_RX/FB_A4/SDRAM_D4/QSPI0A_SCLK, slew_rate: fast, open_drain: disable, pull_select: down,
455 pull_enable: disable}
456 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
457 */
458/* clang-format on */
459
460/* FUNCTION ************************************************************************************************************
461 *
462 * Function Name : BOARD_InitDEBUG_UARTPins
463 * Description : Configures pin routing and optionally pin electrical features.
464 *
465 * END ****************************************************************************************************************/
466void BOARD_InitDEBUG_UARTPins(void)
467{
468 /* Port C Clock Gate Control: Clock enabled */
469 CLOCK_EnableClock(kCLOCK_PortC);
470
471 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
472 kPORT_PullDisable,
473 /* Fast slew rate is configured */
474 kPORT_FastSlewRate,
475 /* Passive filter is disabled */
476 kPORT_PassiveFilterDisable,
477 /* Open drain is disabled */
478 kPORT_OpenDrainDisable,
479 /* Low drive strength is configured */
480 kPORT_LowDriveStrength,
481 /* Pin is configured as LPUART0_TX */
482 kPORT_MuxAlt3,
483 /* Pin Control Register fields [15:0] are not locked */
484 kPORT_UnlockRegister};
485 /* PORTC24 (pin B7) is configured as LPUART0_TX */
486 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
487
488 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
489 kPORT_PullDisable,
490 /* Fast slew rate is configured */
491 kPORT_FastSlewRate,
492 /* Passive filter is disabled */
493 kPORT_PassiveFilterDisable,
494 /* Open drain is disabled */
495 kPORT_OpenDrainDisable,
496 /* Low drive strength is configured */
497 kPORT_LowDriveStrength,
498 /* Pin is configured as LPUART0_RX */
499 kPORT_MuxAlt3,
500 /* Pin Control Register fields [15:0] are not locked */
501 kPORT_UnlockRegister};
502 /* PORTC25 (pin A7) is configured as LPUART0_RX */
503 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
504
505 SIM->SOPT5 = ((SIM->SOPT5 &
506 /* Mask bits to zero which are setting */
507 (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
508
509 /* LPUART0 transmit data source select: LPUART0_TX pin. */
510 | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
511
512 /* LPUART0 receive data source select: LPUART0_RX pin. */
513 | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
514}
515
516/* clang-format off */
517/*
518 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
519BOARD_InitACCELPins:
520- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
521- pin_list:
522 - {pin_num: B6, peripheral: I2C3, signal: SCL, pin_signal: PTC29/I2C3_SCL/FB_A0/SDRAM_D0/QSPI0A_SS0_B, slew_rate: fast, open_drain: enable, pull_select: down, pull_enable: disable}
523 - {pin_num: C6, peripheral: I2C3, signal: SDA, pin_signal: PTC28/I2C3_SDA/FB_A1/SDRAM_D1/QSPI0A_DATA1, slew_rate: fast, open_drain: enable, pull_select: down, pull_enable: disable}
524 - {pin_num: E6, peripheral: GPIOC, signal: 'GPIO, 26', pin_signal: PTC26/LPUART0_CTS_b/FB_A3/SDRAM_D3/QSPI0A_DATA0, direction: INPUT, slew_rate: fast, open_drain: disable,
525 pull_select: up, pull_enable: enable}
526 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
527 */
528/* clang-format on */
529
530/* FUNCTION ************************************************************************************************************
531 *
532 * Function Name : BOARD_InitACCELPins
533 * Description : Configures pin routing and optionally pin electrical features.
534 *
535 * END ****************************************************************************************************************/
536void BOARD_InitACCELPins(void)
537{
538 /* Port C Clock Gate Control: Clock enabled */
539 CLOCK_EnableClock(kCLOCK_PortC);
540
541 gpio_pin_config_t ACCEL_INT1_config = {
542 .pinDirection = kGPIO_DigitalInput,
543 .outputLogic = 0U
544 };
545 /* Initialize GPIO functionality on pin PTC26 (pin E6) */
546 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
547
548 const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */
549 kPORT_PullUp,
550 /* Fast slew rate is configured */
551 kPORT_FastSlewRate,
552 /* Passive filter is disabled */
553 kPORT_PassiveFilterDisable,
554 /* Open drain is disabled */
555 kPORT_OpenDrainDisable,
556 /* Low drive strength is configured */
557 kPORT_LowDriveStrength,
558 /* Pin is configured as PTC26 */
559 kPORT_MuxAsGpio,
560 /* Pin Control Register fields [15:0] are not locked */
561 kPORT_UnlockRegister};
562 /* PORTC26 (pin E6) is configured as PTC26 */
563 PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
564
565 const port_pin_config_t I2C_SDA = {/* Internal pull-up/down resistor is disabled */
566 kPORT_PullDisable,
567 /* Fast slew rate is configured */
568 kPORT_FastSlewRate,
569 /* Passive filter is disabled */
570 kPORT_PassiveFilterDisable,
571 /* Open drain is enabled */
572 kPORT_OpenDrainEnable,
573 /* Low drive strength is configured */
574 kPORT_LowDriveStrength,
575 /* Pin is configured as I2C3_SDA */
576 kPORT_MuxAlt2,
577 /* Pin Control Register fields [15:0] are not locked */
578 kPORT_UnlockRegister};
579 /* PORTC28 (pin C6) is configured as I2C3_SDA */
580 PORT_SetPinConfig(BOARD_I2C_SDA_PORT, BOARD_I2C_SDA_PIN, &I2C_SDA);
581
582 const port_pin_config_t I2C_SCL = {/* Internal pull-up/down resistor is disabled */
583 kPORT_PullDisable,
584 /* Fast slew rate is configured */
585 kPORT_FastSlewRate,
586 /* Passive filter is disabled */
587 kPORT_PassiveFilterDisable,
588 /* Open drain is enabled */
589 kPORT_OpenDrainEnable,
590 /* Low drive strength is configured */
591 kPORT_LowDriveStrength,
592 /* Pin is configured as I2C3_SCL */
593 kPORT_MuxAlt2,
594 /* Pin Control Register fields [15:0] are not locked */
595 kPORT_UnlockRegister};
596 /* PORTC29 (pin B6) is configured as I2C3_SCL */
597 PORT_SetPinConfig(BOARD_I2C_SCL_PORT, BOARD_I2C_SCL_PIN, &I2C_SCL);
598}
599
600/* clang-format off */
601/*
602 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
603BOARD_InitQSPI_FLASHPins:
604- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
605- pin_list:
606 - {pin_num: C1, peripheral: QuadSPI0, signal: 'DATA0, A', pin_signal: PTE2/LLWU_P1/SPI1_SOUT/LPUART1_CTS_b/SDHC0_DCLK/QSPI0A_DATA0/FXIO0_D0/SPI1_SCK, slew_rate: fast,
607 open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
608 - {pin_num: E1, peripheral: QuadSPI0, signal: 'DATA1, A', pin_signal: PTE4/LLWU_P2/SPI1_SIN/LPUART3_TX/SDHC0_D3/QSPI0A_DATA1, slew_rate: fast, open_drain: disable,
609 drive_strength: low, pull_select: down, pull_enable: disable}
610 - {pin_num: D1, peripheral: QuadSPI0, signal: 'DATA2, A', pin_signal: PTE3/SPI1_PCS2/LPUART1_RTS_b/SDHC0_CMD/QSPI0A_DATA2/FXIO0_D1/SPI1_SOUT, slew_rate: fast, open_drain: disable,
611 drive_strength: low, pull_select: down, pull_enable: disable}
612 - {pin_num: A1, peripheral: QuadSPI0, signal: 'DATA3, A', pin_signal: PTE0/SPI1_PCS1/LPUART1_TX/SDHC0_D1/QSPI0A_DATA3/I2C1_SDA/RTC_CLKOUT, slew_rate: fast, open_drain: disable,
613 drive_strength: low, pull_select: down, pull_enable: disable}
614 - {pin_num: B1, peripheral: QuadSPI0, signal: 'SCLK, A', pin_signal: PTE1/LLWU_P0/SPI1_SCK/LPUART1_RX/SDHC0_D0/QSPI0A_SCLK/I2C1_SCL/SPI1_SIN, slew_rate: fast, open_drain: disable,
615 drive_strength: low, pull_select: down, pull_enable: disable}
616 - {pin_num: D2, peripheral: QuadSPI0, signal: 'SS0, A', pin_signal: PTE5/SPI1_PCS0/LPUART3_RX/SDHC0_D2/QSPI0A_SS0_B/FTM3_CH0/USB0_SOF_OUT, slew_rate: fast, open_drain: disable,
617 drive_strength: low, pull_select: down, pull_enable: disable}
618 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
619 */
620/* clang-format on */
621
622/* FUNCTION ************************************************************************************************************
623 *
624 * Function Name : BOARD_InitQSPI_FLASHPins
625 * Description : Configures pin routing and optionally pin electrical features.
626 *
627 * END ****************************************************************************************************************/
628void BOARD_InitQSPI_FLASHPins(void)
629{
630 /* Port E Clock Gate Control: Clock enabled */
631 CLOCK_EnableClock(kCLOCK_PortE);
632
633 const port_pin_config_t QSPIA_DATA3 = {/* Internal pull-up/down resistor is disabled */
634 kPORT_PullDisable,
635 /* Fast slew rate is configured */
636 kPORT_FastSlewRate,
637 /* Passive filter is disabled */
638 kPORT_PassiveFilterDisable,
639 /* Open drain is disabled */
640 kPORT_OpenDrainDisable,
641 /* Low drive strength is configured */
642 kPORT_LowDriveStrength,
643 /* Pin is configured as QSPI0A_DATA3 */
644 kPORT_MuxAlt5,
645 /* Pin Control Register fields [15:0] are not locked */
646 kPORT_UnlockRegister};
647 /* PORTE0 (pin A1) is configured as QSPI0A_DATA3 */
648 PORT_SetPinConfig(BOARD_QSPIA_DATA3_PORT, BOARD_QSPIA_DATA3_PIN, &QSPIA_DATA3);
649
650 const port_pin_config_t QSPIA_SCLK = {/* Internal pull-up/down resistor is disabled */
651 kPORT_PullDisable,
652 /* Fast slew rate is configured */
653 kPORT_FastSlewRate,
654 /* Passive filter is disabled */
655 kPORT_PassiveFilterDisable,
656 /* Open drain is disabled */
657 kPORT_OpenDrainDisable,
658 /* Low drive strength is configured */
659 kPORT_LowDriveStrength,
660 /* Pin is configured as QSPI0A_SCLK */
661 kPORT_MuxAlt5,
662 /* Pin Control Register fields [15:0] are not locked */
663 kPORT_UnlockRegister};
664 /* PORTE1 (pin B1) is configured as QSPI0A_SCLK */
665 PORT_SetPinConfig(BOARD_QSPIA_SCLK_PORT, BOARD_QSPIA_SCLK_PIN, &QSPIA_SCLK);
666
667 const port_pin_config_t QSPIA_DATA0 = {/* Internal pull-up/down resistor is disabled */
668 kPORT_PullDisable,
669 /* Fast slew rate is configured */
670 kPORT_FastSlewRate,
671 /* Passive filter is disabled */
672 kPORT_PassiveFilterDisable,
673 /* Open drain is disabled */
674 kPORT_OpenDrainDisable,
675 /* Low drive strength is configured */
676 kPORT_LowDriveStrength,
677 /* Pin is configured as QSPI0A_DATA0 */
678 kPORT_MuxAlt5,
679 /* Pin Control Register fields [15:0] are not locked */
680 kPORT_UnlockRegister};
681 /* PORTE2 (pin C1) is configured as QSPI0A_DATA0 */
682 PORT_SetPinConfig(BOARD_QSPIA_DATA0_PORT, BOARD_QSPIA_DATA0_PIN, &QSPIA_DATA0);
683
684 const port_pin_config_t QSPIA_DATA2 = {/* Internal pull-up/down resistor is disabled */
685 kPORT_PullDisable,
686 /* Fast slew rate is configured */
687 kPORT_FastSlewRate,
688 /* Passive filter is disabled */
689 kPORT_PassiveFilterDisable,
690 /* Open drain is disabled */
691 kPORT_OpenDrainDisable,
692 /* Low drive strength is configured */
693 kPORT_LowDriveStrength,
694 /* Pin is configured as QSPI0A_DATA2 */
695 kPORT_MuxAlt5,
696 /* Pin Control Register fields [15:0] are not locked */
697 kPORT_UnlockRegister};
698 /* PORTE3 (pin D1) is configured as QSPI0A_DATA2 */
699 PORT_SetPinConfig(BOARD_QSPIA_DATA2_PORT, BOARD_QSPIA_DATA2_PIN, &QSPIA_DATA2);
700
701 const port_pin_config_t QSPIA_DATA1 = {/* Internal pull-up/down resistor is disabled */
702 kPORT_PullDisable,
703 /* Fast slew rate is configured */
704 kPORT_FastSlewRate,
705 /* Passive filter is disabled */
706 kPORT_PassiveFilterDisable,
707 /* Open drain is disabled */
708 kPORT_OpenDrainDisable,
709 /* Low drive strength is configured */
710 kPORT_LowDriveStrength,
711 /* Pin is configured as QSPI0A_DATA1 */
712 kPORT_MuxAlt5,
713 /* Pin Control Register fields [15:0] are not locked */
714 kPORT_UnlockRegister};
715 /* PORTE4 (pin E1) is configured as QSPI0A_DATA1 */
716 PORT_SetPinConfig(BOARD_QSPIA_DATA1_PORT, BOARD_QSPIA_DATA1_PIN, &QSPIA_DATA1);
717
718 const port_pin_config_t QSPIA_SS = {/* Internal pull-up/down resistor is disabled */
719 kPORT_PullDisable,
720 /* Fast slew rate is configured */
721 kPORT_FastSlewRate,
722 /* Passive filter is disabled */
723 kPORT_PassiveFilterDisable,
724 /* Open drain is disabled */
725 kPORT_OpenDrainDisable,
726 /* Low drive strength is configured */
727 kPORT_LowDriveStrength,
728 /* Pin is configured as QSPI0A_SS0_B */
729 kPORT_MuxAlt5,
730 /* Pin Control Register fields [15:0] are not locked */
731 kPORT_UnlockRegister};
732 /* PORTE5 (pin D2) is configured as QSPI0A_SS0_B */
733 PORT_SetPinConfig(BOARD_QSPIA_SS_PORT, BOARD_QSPIA_SS_PIN, &QSPIA_SS);
734}
735
736/* clang-format off */
737/*
738 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
739BOARD_InitUSBPins:
740- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
741- pin_list:
742 - {pin_num: H1, peripheral: USBPHY, signal: DM, pin_signal: USB1_DM, identifier: K28_MICRO_USB_DM_PHY}
743 - {pin_num: J1, peripheral: USBPHY, signal: DP, pin_signal: USB1_DP, identifier: K28_MICRO_USB_DP_PHY}
744 - {pin_num: J2, peripheral: USBPHY, signal: VBUS, pin_signal: USB1_VBUS}
745 - {pin_num: M11, peripheral: USBPHY, signal: ID, pin_signal: PTA11/LLWU_P23/I2C2_SCL/FTM2_CH1/FXIO0_D17/FTM2_QD_PHB/TPM2_CH1/USB1_ID, slew_rate: fast, open_drain: disable,
746 pull_select: down, pull_enable: disable}
747 - {pin_num: K8, peripheral: USB0, signal: CLKIN, pin_signal: PTA22/LPUART4_CTS_b/FXIO0_D6/RTC_CLKOUT/USB0_CLKIN, slew_rate: fast, open_drain: disable, pull_select: down,
748 pull_enable: disable}
749 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
750 */
751/* clang-format on */
752
753/* FUNCTION ************************************************************************************************************
754 *
755 * Function Name : BOARD_InitUSBPins
756 * Description : Configures pin routing and optionally pin electrical features.
757 *
758 * END ****************************************************************************************************************/
759void BOARD_InitUSBPins(void)
760{
761 /* Port A Clock Gate Control: Clock enabled */
762 CLOCK_EnableClock(kCLOCK_PortA);
763
764 const port_pin_config_t USB_ID = {/* Internal pull-up/down resistor is disabled */
765 kPORT_PullDisable,
766 /* Fast slew rate is configured */
767 kPORT_FastSlewRate,
768 /* Passive filter is disabled */
769 kPORT_PassiveFilterDisable,
770 /* Open drain is disabled */
771 kPORT_OpenDrainDisable,
772 /* Low drive strength is configured */
773 kPORT_LowDriveStrength,
774 /* Pin is configured as USB1_ID */
775 kPORT_MuxAlt7,
776 /* Pin Control Register fields [15:0] are not locked */
777 kPORT_UnlockRegister};
778 /* PORTA11 (pin M11) is configured as USB1_ID */
779 PORT_SetPinConfig(BOARD_USB_ID_PORT, BOARD_USB_ID_PIN, &USB_ID);
780
781 const port_pin_config_t USB0_CLKIN = {/* Internal pull-up/down resistor is disabled */
782 kPORT_PullDisable,
783 /* Fast slew rate is configured */
784 kPORT_FastSlewRate,
785 /* Passive filter is disabled */
786 kPORT_PassiveFilterDisable,
787 /* Open drain is disabled */
788 kPORT_OpenDrainDisable,
789 /* Low drive strength is configured */
790 kPORT_LowDriveStrength,
791 /* Pin is configured as USB0_CLKIN */
792 kPORT_MuxAlt7,
793 /* Pin Control Register fields [15:0] are not locked */
794 kPORT_UnlockRegister};
795 /* PORTA22 (pin K8) is configured as USB0_CLKIN */
796 PORT_SetPinConfig(BOARD_USB0_CLKIN_PORT, BOARD_USB0_CLKIN_PIN, &USB0_CLKIN);
797}
798
799/* clang-format off */
800/*
801 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
802BOARD_InitSDHC0Pins:
803- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
804- pin_list:
805 - {pin_num: H11, peripheral: SDHC, signal: 'D, 2', pin_signal: PTA29/LPUART3_RX/SDHC0_D2/FB_A24/I2S1_RXD0, slew_rate: fast, open_drain: disable, pull_select: down,
806 pull_enable: disable}
807 - {pin_num: H12, peripheral: SDHC, signal: 'D, 3', pin_signal: PTA28/LPUART3_TX/SDHC0_D3/FB_A25/I2S1_RXD1, slew_rate: fast, open_drain: disable, pull_select: down,
808 pull_enable: disable}
809 - {pin_num: J11, peripheral: SDHC, signal: 'D, 0', pin_signal: PTA25/LPUART2_RX/SDHC0_D0/FB_A14/SDRAM_D14/FB_A28/I2S1_TX_FS, slew_rate: fast, open_drain: disable,
810 pull_select: down, pull_enable: disable}
811 - {pin_num: K11, peripheral: SDHC, signal: 'D, 1', pin_signal: PTA24/LPUART2_TX/SDHC0_D1/FB_A15/SDRAM_D15/FB_A29/I2S1_TX_BCLK, slew_rate: fast, open_drain: disable,
812 pull_select: down, pull_enable: disable}
813 - {pin_num: J10, peripheral: SDHC, signal: DCLK, pin_signal: PTA26/LPUART2_CTS_b/SDHC0_DCLK/FB_A13/SDRAM_D13/FB_A27/I2S1_TXD0, slew_rate: fast, open_drain: disable,
814 pull_select: down, pull_enable: disable}
815 - {pin_num: H13, peripheral: SDHC, signal: CMD, pin_signal: PTA27/LPUART2_RTS_b/SDHC0_CMD/FB_A12/SDRAM_D12/FB_A26/I2S1_TXD1, slew_rate: fast, open_drain: disable,
816 pull_select: down, pull_enable: disable}
817 - {pin_num: F13, peripheral: GPIOB, signal: 'GPIO, 5', pin_signal: PTB5/FTM2_FLT0, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
818 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
819 */
820/* clang-format on */
821
822/* FUNCTION ************************************************************************************************************
823 *
824 * Function Name : BOARD_InitSDHC0Pins
825 * Description : Configures pin routing and optionally pin electrical features.
826 *
827 * END ****************************************************************************************************************/
828void BOARD_InitSDHC0Pins(void)
829{
830 /* Port A Clock Gate Control: Clock enabled */
831 CLOCK_EnableClock(kCLOCK_PortA);
832 /* Port B Clock Gate Control: Clock enabled */
833 CLOCK_EnableClock(kCLOCK_PortB);
834
835 gpio_pin_config_t SDCARD_CARD_DETECTION_config = {
836 .pinDirection = kGPIO_DigitalInput,
837 .outputLogic = 0U
838 };
839 /* Initialize GPIO functionality on pin PTB5 (pin F13) */
840 GPIO_PinInit(BOARD_SDCARD_CARD_DETECTION_GPIO, BOARD_SDCARD_CARD_DETECTION_PIN, &SDCARD_CARD_DETECTION_config);
841
842 const port_pin_config_t SDHC0_D1 = {/* Internal pull-up/down resistor is disabled */
843 kPORT_PullDisable,
844 /* Fast slew rate is configured */
845 kPORT_FastSlewRate,
846 /* Passive filter is disabled */
847 kPORT_PassiveFilterDisable,
848 /* Open drain is disabled */
849 kPORT_OpenDrainDisable,
850 /* Low drive strength is configured */
851 kPORT_LowDriveStrength,
852 /* Pin is configured as SDHC0_D1 */
853 kPORT_MuxAlt4,
854 /* Pin Control Register fields [15:0] are not locked */
855 kPORT_UnlockRegister};
856 /* PORTA24 (pin K11) is configured as SDHC0_D1 */
857 PORT_SetPinConfig(BOARD_SDHC0_D1_PORT, BOARD_SDHC0_D1_PIN, &SDHC0_D1);
858
859 const port_pin_config_t SDHC0_D0 = {/* Internal pull-up/down resistor is disabled */
860 kPORT_PullDisable,
861 /* Fast slew rate is configured */
862 kPORT_FastSlewRate,
863 /* Passive filter is disabled */
864 kPORT_PassiveFilterDisable,
865 /* Open drain is disabled */
866 kPORT_OpenDrainDisable,
867 /* Low drive strength is configured */
868 kPORT_LowDriveStrength,
869 /* Pin is configured as SDHC0_D0 */
870 kPORT_MuxAlt4,
871 /* Pin Control Register fields [15:0] are not locked */
872 kPORT_UnlockRegister};
873 /* PORTA25 (pin J11) is configured as SDHC0_D0 */
874 PORT_SetPinConfig(BOARD_SDHC0_D0_PORT, BOARD_SDHC0_D0_PIN, &SDHC0_D0);
875
876 const port_pin_config_t SDHC0_DCLK = {/* Internal pull-up/down resistor is disabled */
877 kPORT_PullDisable,
878 /* Fast slew rate is configured */
879 kPORT_FastSlewRate,
880 /* Passive filter is disabled */
881 kPORT_PassiveFilterDisable,
882 /* Open drain is disabled */
883 kPORT_OpenDrainDisable,
884 /* Low drive strength is configured */
885 kPORT_LowDriveStrength,
886 /* Pin is configured as SDHC0_DCLK */
887 kPORT_MuxAlt4,
888 /* Pin Control Register fields [15:0] are not locked */
889 kPORT_UnlockRegister};
890 /* PORTA26 (pin J10) is configured as SDHC0_DCLK */
891 PORT_SetPinConfig(BOARD_SDHC0_DCLK_PORT, BOARD_SDHC0_DCLK_PIN, &SDHC0_DCLK);
892
893 const port_pin_config_t SDHC0_CMD = {/* Internal pull-up/down resistor is disabled */
894 kPORT_PullDisable,
895 /* Fast slew rate is configured */
896 kPORT_FastSlewRate,
897 /* Passive filter is disabled */
898 kPORT_PassiveFilterDisable,
899 /* Open drain is disabled */
900 kPORT_OpenDrainDisable,
901 /* Low drive strength is configured */
902 kPORT_LowDriveStrength,
903 /* Pin is configured as SDHC0_CMD */
904 kPORT_MuxAlt4,
905 /* Pin Control Register fields [15:0] are not locked */
906 kPORT_UnlockRegister};
907 /* PORTA27 (pin H13) is configured as SDHC0_CMD */
908 PORT_SetPinConfig(BOARD_SDHC0_CMD_PORT, BOARD_SDHC0_CMD_PIN, &SDHC0_CMD);
909
910 const port_pin_config_t SDHC0_D3 = {/* Internal pull-up/down resistor is disabled */
911 kPORT_PullDisable,
912 /* Fast slew rate is configured */
913 kPORT_FastSlewRate,
914 /* Passive filter is disabled */
915 kPORT_PassiveFilterDisable,
916 /* Open drain is disabled */
917 kPORT_OpenDrainDisable,
918 /* Low drive strength is configured */
919 kPORT_LowDriveStrength,
920 /* Pin is configured as SDHC0_D3 */
921 kPORT_MuxAlt4,
922 /* Pin Control Register fields [15:0] are not locked */
923 kPORT_UnlockRegister};
924 /* PORTA28 (pin H12) is configured as SDHC0_D3 */
925 PORT_SetPinConfig(BOARD_SDHC0_D3_PORT, BOARD_SDHC0_D3_PIN, &SDHC0_D3);
926
927 const port_pin_config_t SDHC0_D2 = {/* Internal pull-up/down resistor is disabled */
928 kPORT_PullDisable,
929 /* Fast slew rate is configured */
930 kPORT_FastSlewRate,
931 /* Passive filter is disabled */
932 kPORT_PassiveFilterDisable,
933 /* Open drain is disabled */
934 kPORT_OpenDrainDisable,
935 /* Low drive strength is configured */
936 kPORT_LowDriveStrength,
937 /* Pin is configured as SDHC0_D2 */
938 kPORT_MuxAlt4,
939 /* Pin Control Register fields [15:0] are not locked */
940 kPORT_UnlockRegister};
941 /* PORTA29 (pin H11) is configured as SDHC0_D2 */
942 PORT_SetPinConfig(BOARD_SDHC0_D2_PORT, BOARD_SDHC0_D2_PIN, &SDHC0_D2);
943
944 const port_pin_config_t SDCARD_CARD_DETECTION = {/* Internal pull-up resistor is enabled */
945 kPORT_PullUp,
946 /* Fast slew rate is configured */
947 kPORT_FastSlewRate,
948 /* Passive filter is disabled */
949 kPORT_PassiveFilterDisable,
950 /* Open drain is disabled */
951 kPORT_OpenDrainDisable,
952 /* Low drive strength is configured */
953 kPORT_LowDriveStrength,
954 /* Pin is configured as PTB5 */
955 kPORT_MuxAsGpio,
956 /* Pin Control Register fields [15:0] are not locked */
957 kPORT_UnlockRegister};
958 /* PORTB5 (pin F13) is configured as PTB5 */
959 PORT_SetPinConfig(BOARD_SDCARD_CARD_DETECTION_PORT, BOARD_SDCARD_CARD_DETECTION_PIN, &SDCARD_CARD_DETECTION);
960}
961
962/* clang-format off */
963/*
964 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
965BOARD_Init_visible_lightPins:
966- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
967- pin_list:
968 - {pin_num: N4, peripheral: ADC0, signal: 'SE, 16', pin_signal: ADC0_SE16}
969 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
970 */
971/* clang-format on */
972
973/* FUNCTION ************************************************************************************************************
974 *
975 * Function Name : BOARD_Init_visible_lightPins
976 * Description : Configures pin routing and optionally pin electrical features.
977 *
978 * END ****************************************************************************************************************/
979void BOARD_Init_visible_lightPins(void)
980{
981}
982
983/* clang-format off */
984/*
985 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
986BOARD_InitSDRAMPins:
987- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
988- pin_list:
989 - {pin_num: B10, peripheral: SDRAM, signal: A16, pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB0_SOF_OUT/I2S0_RX_FS/FB_AD8/SDRAM_A16/FXIO0_D15, slew_rate: fast, open_drain: disable,
990 pull_select: down, pull_enable: disable}
991 - {pin_num: C10, peripheral: SDRAM, signal: A15, pin_signal: CMP0_IN2/PTC8/FTM3_CH4/I2S0_MCLK/FB_AD7/SDRAM_A15/FXIO0_D16, slew_rate: fast, open_drain: disable,
992 pull_select: down, pull_enable: disable}
993 - {pin_num: C9, peripheral: SDRAM, signal: A14, pin_signal: CMP0_IN3/PTC9/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/SDRAM_A14/FTM2_FLT0/FXIO0_D17, slew_rate: fast, open_drain: disable,
994 pull_select: down, pull_enable: disable}
995 - {pin_num: A8, peripheral: SDRAM, signal: A13, pin_signal: PTC10/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5/SDRAM_A13/FXIO0_D18, slew_rate: fast, open_drain: disable,
996 pull_select: down, pull_enable: disable}
997 - {pin_num: A4, peripheral: SDRAM, signal: A12, pin_signal: PTD2/LLWU_P13/SPI0_SOUT/LPUART2_RX/FTM3_CH2/FB_AD4/SDRAM_A12/I2C0_SCL, slew_rate: fast, open_drain: disable,
998 pull_select: down, pull_enable: disable, digital_filter: disable}
999 - {pin_num: B4, peripheral: SDRAM, signal: A11, pin_signal: PTD3/SPI0_SIN/LPUART2_TX/FTM3_CH3/FB_AD3/SDRAM_A11/I2C0_SDA, slew_rate: fast, open_drain: disable, pull_select: down,
1000 pull_enable: disable, digital_filter: disable}
1001 - {pin_num: B5, peripheral: SDRAM, signal: A10, pin_signal: PTD4/LLWU_P14/SPI0_PCS1/LPUART0_RTS_b/FTM0_CH4/FB_AD2/SDRAM_A10/EWM_IN/SPI1_PCS0, slew_rate: fast, open_drain: disable,
1002 drive_strength: low, pull_select: down, pull_enable: disable, digital_filter: disable}
1003 - {pin_num: C4, peripheral: SDRAM, signal: A9, pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/LPUART0_CTS_b/FTM0_CH5/FB_AD1/SDRAM_A9/EWM_OUT_b/SPI1_SCK, slew_rate: fast,
1004 open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, digital_filter: disable}
1005 - {pin_num: A11, peripheral: SDRAM, signal: A18, pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/I2S0_RXD0/FB_AD10/SDRAM_A18/CMP0_OUT/FTM0_CH2, slew_rate: fast,
1006 open_drain: disable, pull_select: down, pull_enable: disable}
1007 - {pin_num: B11, peripheral: SDRAM, signal: A19, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/LPUART1_TX/FTM0_CH3/FB_AD11/SDRAM_A19/CMP1_OUT, slew_rate: fast, open_drain: disable,
1008 drive_strength: low, pull_select: down, pull_enable: disable}
1009 - {pin_num: A13, peripheral: SDRAM, signal: A20, pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/LPUART1_CTS_b/FTM0_CH1/FB_AD12/SDRAM_A20/I2S0_TX_FS, slew_rate: fast,
1010 open_drain: disable, pull_select: down, pull_enable: disable}
1011 - {pin_num: B12, peripheral: SDRAM, signal: A21, pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/LPUART1_RTS_b/FTM0_CH0/FB_AD13/SDRAM_A21/I2S0_TXD0/FXIO0_D13, slew_rate: fast,
1012 open_drain: disable, pull_select: down, pull_enable: disable}
1013 - {pin_num: B13, peripheral: SDRAM, signal: A22, pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/USB0_SOF_OUT/FB_AD14/SDRAM_A22/I2S0_TXD1/FXIO0_D12, slew_rate: fast,
1014 open_drain: disable, pull_select: down, pull_enable: disable}
1015 - {pin_num: D12, peripheral: SDRAM, signal: A23, pin_signal: PTB18/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/SDRAM_A23/FTM2_QD_PHA/TPM2_CH0/FXIO0_D6, slew_rate: fast, open_drain: disable,
1016 pull_select: down, pull_enable: disable}
1017 - {pin_num: G12, peripheral: SDRAM, signal: RAS, pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/SDRAM_RAS_b/FTM1_QD_PHB/TPM1_CH1/FXIO0_D1, slew_rate: fast, open_drain: disable,
1018 drive_strength: low, pull_select: down, pull_enable: disable}
1019 - {pin_num: G13, peripheral: SDRAM, signal: CAS, pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/SDRAM_CAS_b/FTM1_QD_PHA/TPM1_CH0/FXIO0_D0, slew_rate: fast,
1020 open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
1021 - {pin_num: G11, peripheral: SDRAM, signal: WE, pin_signal: ADC0_SE12/PTB2/I2C0_SCL/LPUART0_RTS_b/SDRAM_WE_b/FTM0_FLT3/FXIO0_D2, slew_rate: fast, open_drain: disable,
1022 pull_select: down, pull_enable: disable}
1023 - {pin_num: G10, peripheral: SDRAM, signal: CS0, pin_signal: ADC0_SE13/PTB3/I2C0_SDA/LPUART0_CTS_b/SDRAM_CS0_b/FTM0_FLT0/FXIO0_D3, slew_rate: fast, open_drain: disable,
1024 pull_select: down, pull_enable: disable}
1025 - {pin_num: E7, peripheral: SDRAM, signal: DQM3, pin_signal: PTC17/LPUART3_TX/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b/SDRAM_DQM3, slew_rate: fast, open_drain: disable,
1026 pull_select: down, pull_enable: disable}
1027 - {pin_num: E8, peripheral: SDRAM, signal: DQM2, pin_signal: PTC16/LPUART3_RX/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b/SDRAM_DQM2, slew_rate: fast, open_drain: disable,
1028 pull_select: down, pull_enable: disable}
1029 - {pin_num: A12, peripheral: SDRAM, signal: CLKOUT, pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/LPUART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK, slew_rate: fast, open_drain: disable,
1030 drive_strength: low, pull_select: down, pull_enable: disable}
1031 - {pin_num: E5, peripheral: SDRAM, signal: CKE, pin_signal: PTD7/CMT_IRO/LPUART0_TX/FTM0_CH7/SDRAM_CKE/FTM0_FLT1/SPI1_SIN, slew_rate: fast, open_drain: disable,
1032 drive_strength: low, pull_select: down, pull_enable: disable, digital_filter: disable}
1033 - {pin_num: D10, peripheral: SDRAM, signal: D31, pin_signal: PTB20/SPI2_PCS0/FB_AD31/SDRAM_D31/CMP0_OUT/FXIO0_D8, slew_rate: fast, open_drain: disable, pull_select: down,
1034 pull_enable: disable}
1035 - {pin_num: D9, peripheral: SDRAM, signal: D30, pin_signal: PTB21/SPI2_SCK/FB_AD30/SDRAM_D30/CMP1_OUT/FXIO0_D9, slew_rate: fast, open_drain: disable, pull_select: down,
1036 pull_enable: disable}
1037 - {pin_num: D13, peripheral: SDRAM, signal: D16, pin_signal: PTB17/SPI1_SIN/LPUART0_TX/FTM_CLKIN1/FB_AD16/SDRAM_D16/EWM_OUT_b/TPM_CLKIN1, slew_rate: fast, open_drain: disable,
1038 pull_select: down, pull_enable: disable}
1039 - {pin_num: F8, peripheral: SDRAM, signal: D17, pin_signal: PTB16/SPI1_SOUT/LPUART0_RX/FTM_CLKIN0/FB_AD17/SDRAM_D17/EWM_IN/TPM_CLKIN0, slew_rate: fast, open_drain: disable,
1040 pull_select: down, pull_enable: disable}
1041 - {pin_num: E13, peripheral: SDRAM, signal: D18, pin_signal: PTB11/SPI1_SCK/LPUART3_TX/I2C2_SDA/FB_AD18/SDRAM_D18/FTM0_FLT2/FXIO0_D5, slew_rate: fast, open_drain: disable,
1042 pull_select: down, pull_enable: disable}
1043 - {pin_num: G9, peripheral: SDRAM, signal: D19, pin_signal: PTB10/SPI1_PCS0/LPUART3_RX/I2C2_SCL/FB_AD19/SDRAM_D19/FTM0_FLT1/FXIO0_D4, slew_rate: fast, open_drain: disable,
1044 pull_select: down, pull_enable: disable}
1045 - {pin_num: F9, peripheral: SDRAM, signal: D20, pin_signal: PTB9/SPI1_PCS1/LPUART3_CTS_b/FB_AD20/SDRAM_D20, slew_rate: fast, open_drain: disable, pull_select: down,
1046 pull_enable: disable}
1047 - {pin_num: F10, peripheral: SDRAM, signal: D21, pin_signal: PTB8/LPUART3_RTS_b/FB_AD21/SDRAM_D21, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
1048 - {pin_num: F11, peripheral: SDRAM, signal: D22, pin_signal: PTB7/FB_AD22/SDRAM_D22, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
1049 - {pin_num: F12, peripheral: SDRAM, signal: D23, pin_signal: PTB6/FB_AD23/SDRAM_D23, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
1050 - {pin_num: D8, peripheral: SDRAM, signal: D24, pin_signal: PTC15/LPUART4_TX/FB_AD24/SDRAM_D24/FXIO0_D21, slew_rate: fast, open_drain: disable, pull_select: down,
1051 pull_enable: disable}
1052 - {pin_num: C8, peripheral: SDRAM, signal: D25, pin_signal: PTC14/LPUART4_RX/FB_AD25/SDRAM_D25/FXIO0_D20, slew_rate: fast, open_drain: disable, pull_select: down,
1053 pull_enable: disable}
1054 - {pin_num: B8, peripheral: SDRAM, signal: D26, pin_signal: PTC13/LPUART4_CTS_b/FTM_CLKIN1/FB_AD26/SDRAM_D26/TPM_CLKIN1, slew_rate: fast, open_drain: disable, pull_select: down,
1055 pull_enable: disable}
1056 - {pin_num: B9, peripheral: SDRAM, signal: D27, pin_signal: PTC12/LPUART4_RTS_b/FTM_CLKIN0/FB_AD27/SDRAM_D27/FTM3_FLT0/TPM_CLKIN0, slew_rate: fast, open_drain: disable,
1057 pull_select: down, pull_enable: disable}
1058 - {pin_num: C12, peripheral: SDRAM, signal: D28, pin_signal: PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28/SDRAM_D28/FXIO0_D11, slew_rate: fast, open_drain: disable, pull_select: down,
1059 pull_enable: disable}
1060 - {pin_num: C13, peripheral: SDRAM, signal: D29, pin_signal: PTB22/SPI2_SOUT/FB_AD29/SDRAM_D29/FXIO0_D10, slew_rate: fast, open_drain: disable, pull_select: down,
1061 pull_enable: disable}
1062 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
1063 */
1064/* clang-format on */
1065
1066/* FUNCTION ************************************************************************************************************
1067 *
1068 * Function Name : BOARD_InitSDRAMPins
1069 * Description : Configures pin routing and optionally pin electrical features.
1070 *
1071 * END ****************************************************************************************************************/
1072void BOARD_InitSDRAMPins(void)
1073{
1074 /* Port B Clock Gate Control: Clock enabled */
1075 CLOCK_EnableClock(kCLOCK_PortB);
1076 /* Port C Clock Gate Control: Clock enabled */
1077 CLOCK_EnableClock(kCLOCK_PortC);
1078 /* Port D Clock Gate Control: Clock enabled */
1079 CLOCK_EnableClock(kCLOCK_PortD);
1080
1081 const port_pin_config_t SDRAM_CAS_b = {/* Internal pull-up/down resistor is disabled */
1082 kPORT_PullDisable,
1083 /* Fast slew rate is configured */
1084 kPORT_FastSlewRate,
1085 /* Passive filter is disabled */
1086 kPORT_PassiveFilterDisable,
1087 /* Open drain is disabled */
1088 kPORT_OpenDrainDisable,
1089 /* Low drive strength is configured */
1090 kPORT_LowDriveStrength,
1091 /* Pin is configured as SDRAM_CAS_b */
1092 kPORT_MuxAlt5,
1093 /* Pin Control Register fields [15:0] are not locked */
1094 kPORT_UnlockRegister};
1095 /* PORTB0 (pin G13) is configured as SDRAM_CAS_b */
1096 PORT_SetPinConfig(BOARD_SDRAM_CAS_b_PORT, BOARD_SDRAM_CAS_b_PIN, &SDRAM_CAS_b);
1097
1098 const port_pin_config_t SDRAM_RAS_b = {/* Internal pull-up/down resistor is disabled */
1099 kPORT_PullDisable,
1100 /* Fast slew rate is configured */
1101 kPORT_FastSlewRate,
1102 /* Passive filter is disabled */
1103 kPORT_PassiveFilterDisable,
1104 /* Open drain is disabled */
1105 kPORT_OpenDrainDisable,
1106 /* Low drive strength is configured */
1107 kPORT_LowDriveStrength,
1108 /* Pin is configured as SDRAM_RAS_b */
1109 kPORT_MuxAlt5,
1110 /* Pin Control Register fields [15:0] are not locked */
1111 kPORT_UnlockRegister};
1112 /* PORTB1 (pin G12) is configured as SDRAM_RAS_b */
1113 PORT_SetPinConfig(BOARD_SDRAM_RAS_b_PORT, BOARD_SDRAM_RAS_b_PIN, &SDRAM_RAS_b);
1114
1115 const port_pin_config_t SDRAM_D19 = {/* Internal pull-up/down resistor is disabled */
1116 kPORT_PullDisable,
1117 /* Fast slew rate is configured */
1118 kPORT_FastSlewRate,
1119 /* Passive filter is disabled */
1120 kPORT_PassiveFilterDisable,
1121 /* Open drain is disabled */
1122 kPORT_OpenDrainDisable,
1123 /* Low drive strength is configured */
1124 kPORT_LowDriveStrength,
1125 /* Pin is configured as SDRAM_D19 */
1126 kPORT_MuxAlt5,
1127 /* Pin Control Register fields [15:0] are not locked */
1128 kPORT_UnlockRegister};
1129 /* PORTB10 (pin G9) is configured as SDRAM_D19 */
1130 PORT_SetPinConfig(BOARD_SDRAM_D19_PORT, BOARD_SDRAM_D19_PIN, &SDRAM_D19);
1131
1132 const port_pin_config_t SDRAM_D18 = {/* Internal pull-up/down resistor is disabled */
1133 kPORT_PullDisable,
1134 /* Fast slew rate is configured */
1135 kPORT_FastSlewRate,
1136 /* Passive filter is disabled */
1137 kPORT_PassiveFilterDisable,
1138 /* Open drain is disabled */
1139 kPORT_OpenDrainDisable,
1140 /* Low drive strength is configured */
1141 kPORT_LowDriveStrength,
1142 /* Pin is configured as SDRAM_D18 */
1143 kPORT_MuxAlt5,
1144 /* Pin Control Register fields [15:0] are not locked */
1145 kPORT_UnlockRegister};
1146 /* PORTB11 (pin E13) is configured as SDRAM_D18 */
1147 PORT_SetPinConfig(BOARD_SDRAM_D18_PORT, BOARD_SDRAM_D18_PIN, &SDRAM_D18);
1148
1149 const port_pin_config_t SDRAM_D17 = {/* Internal pull-up/down resistor is disabled */
1150 kPORT_PullDisable,
1151 /* Fast slew rate is configured */
1152 kPORT_FastSlewRate,
1153 /* Passive filter is disabled */
1154 kPORT_PassiveFilterDisable,
1155 /* Open drain is disabled */
1156 kPORT_OpenDrainDisable,
1157 /* Low drive strength is configured */
1158 kPORT_LowDriveStrength,
1159 /* Pin is configured as SDRAM_D17 */
1160 kPORT_MuxAlt5,
1161 /* Pin Control Register fields [15:0] are not locked */
1162 kPORT_UnlockRegister};
1163 /* PORTB16 (pin F8) is configured as SDRAM_D17 */
1164 PORT_SetPinConfig(BOARD_SDRAM_D17_PORT, BOARD_SDRAM_D17_PIN, &SDRAM_D17);
1165
1166 const port_pin_config_t SDRAM_D16 = {/* Internal pull-up/down resistor is disabled */
1167 kPORT_PullDisable,
1168 /* Fast slew rate is configured */
1169 kPORT_FastSlewRate,
1170 /* Passive filter is disabled */
1171 kPORT_PassiveFilterDisable,
1172 /* Open drain is disabled */
1173 kPORT_OpenDrainDisable,
1174 /* Low drive strength is configured */
1175 kPORT_LowDriveStrength,
1176 /* Pin is configured as SDRAM_D16 */
1177 kPORT_MuxAlt5,
1178 /* Pin Control Register fields [15:0] are not locked */
1179 kPORT_UnlockRegister};
1180 /* PORTB17 (pin D13) is configured as SDRAM_D16 */
1181 PORT_SetPinConfig(BOARD_SDRAM_D16_PORT, BOARD_SDRAM_D16_PIN, &SDRAM_D16);
1182
1183 const port_pin_config_t SDRAM_A23 = {/* Internal pull-up/down resistor is disabled */
1184 kPORT_PullDisable,
1185 /* Fast slew rate is configured */
1186 kPORT_FastSlewRate,
1187 /* Passive filter is disabled */
1188 kPORT_PassiveFilterDisable,
1189 /* Open drain is disabled */
1190 kPORT_OpenDrainDisable,
1191 /* Low drive strength is configured */
1192 kPORT_LowDriveStrength,
1193 /* Pin is configured as SDRAM_A23 */
1194 kPORT_MuxAlt5,
1195 /* Pin Control Register fields [15:0] are not locked */
1196 kPORT_UnlockRegister};
1197 /* PORTB18 (pin D12) is configured as SDRAM_A23 */
1198 PORT_SetPinConfig(BOARD_SDRAM_A23_PORT, BOARD_SDRAM_A23_PIN, &SDRAM_A23);
1199
1200 const port_pin_config_t SDRAM_WE_b = {/* Internal pull-up/down resistor is disabled */
1201 kPORT_PullDisable,
1202 /* Fast slew rate is configured */
1203 kPORT_FastSlewRate,
1204 /* Passive filter is disabled */
1205 kPORT_PassiveFilterDisable,
1206 /* Open drain is disabled */
1207 kPORT_OpenDrainDisable,
1208 /* Low drive strength is configured */
1209 kPORT_LowDriveStrength,
1210 /* Pin is configured as SDRAM_WE_b */
1211 kPORT_MuxAlt5,
1212 /* Pin Control Register fields [15:0] are not locked */
1213 kPORT_UnlockRegister};
1214 /* PORTB2 (pin G11) is configured as SDRAM_WE_b */
1215 PORT_SetPinConfig(BOARD_SDRAM_WE_b_PORT, BOARD_SDRAM_WE_b_PIN, &SDRAM_WE_b);
1216
1217 const port_pin_config_t SDRAM_D31 = {/* Internal pull-up/down resistor is disabled */
1218 kPORT_PullDisable,
1219 /* Fast slew rate is configured */
1220 kPORT_FastSlewRate,
1221 /* Passive filter is disabled */
1222 kPORT_PassiveFilterDisable,
1223 /* Open drain is disabled */
1224 kPORT_OpenDrainDisable,
1225 /* Low drive strength is configured */
1226 kPORT_LowDriveStrength,
1227 /* Pin is configured as SDRAM_D31 */
1228 kPORT_MuxAlt5,
1229 /* Pin Control Register fields [15:0] are not locked */
1230 kPORT_UnlockRegister};
1231 /* PORTB20 (pin D10) is configured as SDRAM_D31 */
1232 PORT_SetPinConfig(BOARD_SDRAM_D31_PORT, BOARD_SDRAM_D31_PIN, &SDRAM_D31);
1233
1234 const port_pin_config_t SDRAM_D30 = {/* Internal pull-up/down resistor is disabled */
1235 kPORT_PullDisable,
1236 /* Fast slew rate is configured */
1237 kPORT_FastSlewRate,
1238 /* Passive filter is disabled */
1239 kPORT_PassiveFilterDisable,
1240 /* Open drain is disabled */
1241 kPORT_OpenDrainDisable,
1242 /* Low drive strength is configured */
1243 kPORT_LowDriveStrength,
1244 /* Pin is configured as SDRAM_D30 */
1245 kPORT_MuxAlt5,
1246 /* Pin Control Register fields [15:0] are not locked */
1247 kPORT_UnlockRegister};
1248 /* PORTB21 (pin D9) is configured as SDRAM_D30 */
1249 PORT_SetPinConfig(BOARD_SDRAM_D30_PORT, BOARD_SDRAM_D30_PIN, &SDRAM_D30);
1250
1251 const port_pin_config_t SDRAM_D29 = {/* Internal pull-up/down resistor is disabled */
1252 kPORT_PullDisable,
1253 /* Fast slew rate is configured */
1254 kPORT_FastSlewRate,
1255 /* Passive filter is disabled */
1256 kPORT_PassiveFilterDisable,
1257 /* Open drain is disabled */
1258 kPORT_OpenDrainDisable,
1259 /* Low drive strength is configured */
1260 kPORT_LowDriveStrength,
1261 /* Pin is configured as SDRAM_D29 */
1262 kPORT_MuxAlt5,
1263 /* Pin Control Register fields [15:0] are not locked */
1264 kPORT_UnlockRegister};
1265 /* PORTB22 (pin C13) is configured as SDRAM_D29 */
1266 PORT_SetPinConfig(BOARD_SDRAM_D29_PORT, BOARD_SDRAM_D29_PIN, &SDRAM_D29);
1267
1268 const port_pin_config_t SDRAM_D28 = {/* Internal pull-up/down resistor is disabled */
1269 kPORT_PullDisable,
1270 /* Fast slew rate is configured */
1271 kPORT_FastSlewRate,
1272 /* Passive filter is disabled */
1273 kPORT_PassiveFilterDisable,
1274 /* Open drain is disabled */
1275 kPORT_OpenDrainDisable,
1276 /* Low drive strength is configured */
1277 kPORT_LowDriveStrength,
1278 /* Pin is configured as SDRAM_D28 */
1279 kPORT_MuxAlt5,
1280 /* Pin Control Register fields [15:0] are not locked */
1281 kPORT_UnlockRegister};
1282 /* PORTB23 (pin C12) is configured as SDRAM_D28 */
1283 PORT_SetPinConfig(BOARD_SDRAM_D28_PORT, BOARD_SDRAM_D28_PIN, &SDRAM_D28);
1284
1285 const port_pin_config_t SDRAM_CS0_b = {/* Internal pull-up/down resistor is disabled */
1286 kPORT_PullDisable,
1287 /* Fast slew rate is configured */
1288 kPORT_FastSlewRate,
1289 /* Passive filter is disabled */
1290 kPORT_PassiveFilterDisable,
1291 /* Open drain is disabled */
1292 kPORT_OpenDrainDisable,
1293 /* Low drive strength is configured */
1294 kPORT_LowDriveStrength,
1295 /* Pin is configured as SDRAM_CS0_b */
1296 kPORT_MuxAlt5,
1297 /* Pin Control Register fields [15:0] are not locked */
1298 kPORT_UnlockRegister};
1299 /* PORTB3 (pin G10) is configured as SDRAM_CS0_b */
1300 PORT_SetPinConfig(BOARD_SDRAM_CS0_b_PORT, BOARD_SDRAM_CS0_b_PIN, &SDRAM_CS0_b);
1301
1302 const port_pin_config_t SDRAM_D23 = {/* Internal pull-up/down resistor is disabled */
1303 kPORT_PullDisable,
1304 /* Fast slew rate is configured */
1305 kPORT_FastSlewRate,
1306 /* Passive filter is disabled */
1307 kPORT_PassiveFilterDisable,
1308 /* Open drain is disabled */
1309 kPORT_OpenDrainDisable,
1310 /* Low drive strength is configured */
1311 kPORT_LowDriveStrength,
1312 /* Pin is configured as SDRAM_D23 */
1313 kPORT_MuxAlt5,
1314 /* Pin Control Register fields [15:0] are not locked */
1315 kPORT_UnlockRegister};
1316 /* PORTB6 (pin F12) is configured as SDRAM_D23 */
1317 PORT_SetPinConfig(BOARD_SDRAM_D23_PORT, BOARD_SDRAM_D23_PIN, &SDRAM_D23);
1318
1319 const port_pin_config_t SDRAM_D22 = {/* Internal pull-up/down resistor is disabled */
1320 kPORT_PullDisable,
1321 /* Fast slew rate is configured */
1322 kPORT_FastSlewRate,
1323 /* Passive filter is disabled */
1324 kPORT_PassiveFilterDisable,
1325 /* Open drain is disabled */
1326 kPORT_OpenDrainDisable,
1327 /* Low drive strength is configured */
1328 kPORT_LowDriveStrength,
1329 /* Pin is configured as SDRAM_D22 */
1330 kPORT_MuxAlt5,
1331 /* Pin Control Register fields [15:0] are not locked */
1332 kPORT_UnlockRegister};
1333 /* PORTB7 (pin F11) is configured as SDRAM_D22 */
1334 PORT_SetPinConfig(BOARD_SDRAM_D22_PORT, BOARD_SDRAM_D22_PIN, &SDRAM_D22);
1335
1336 const port_pin_config_t SDRAM_D21 = {/* Internal pull-up/down resistor is disabled */
1337 kPORT_PullDisable,
1338 /* Fast slew rate is configured */
1339 kPORT_FastSlewRate,
1340 /* Passive filter is disabled */
1341 kPORT_PassiveFilterDisable,
1342 /* Open drain is disabled */
1343 kPORT_OpenDrainDisable,
1344 /* Low drive strength is configured */
1345 kPORT_LowDriveStrength,
1346 /* Pin is configured as SDRAM_D21 */
1347 kPORT_MuxAlt5,
1348 /* Pin Control Register fields [15:0] are not locked */
1349 kPORT_UnlockRegister};
1350 /* PORTB8 (pin F10) is configured as SDRAM_D21 */
1351 PORT_SetPinConfig(BOARD_SDRAM_D21_PORT, BOARD_SDRAM_D21_PIN, &SDRAM_D21);
1352
1353 const port_pin_config_t SDRAM_D20 = {/* Internal pull-up/down resistor is disabled */
1354 kPORT_PullDisable,
1355 /* Fast slew rate is configured */
1356 kPORT_FastSlewRate,
1357 /* Passive filter is disabled */
1358 kPORT_PassiveFilterDisable,
1359 /* Open drain is disabled */
1360 kPORT_OpenDrainDisable,
1361 /* Low drive strength is configured */
1362 kPORT_LowDriveStrength,
1363 /* Pin is configured as SDRAM_D20 */
1364 kPORT_MuxAlt5,
1365 /* Pin Control Register fields [15:0] are not locked */
1366 kPORT_UnlockRegister};
1367 /* PORTB9 (pin F9) is configured as SDRAM_D20 */
1368 PORT_SetPinConfig(BOARD_SDRAM_D20_PORT, BOARD_SDRAM_D20_PIN, &SDRAM_D20);
1369
1370 const port_pin_config_t SDRAM_A22 = {/* Internal pull-up/down resistor is disabled */
1371 kPORT_PullDisable,
1372 /* Fast slew rate is configured */
1373 kPORT_FastSlewRate,
1374 /* Passive filter is disabled */
1375 kPORT_PassiveFilterDisable,
1376 /* Open drain is disabled */
1377 kPORT_OpenDrainDisable,
1378 /* Low drive strength is configured */
1379 kPORT_LowDriveStrength,
1380 /* Pin is configured as SDRAM_A22 */
1381 kPORT_MuxAlt5,
1382 /* Pin Control Register fields [15:0] are not locked */
1383 kPORT_UnlockRegister};
1384 /* PORTC0 (pin B13) is configured as SDRAM_A22 */
1385 PORT_SetPinConfig(BOARD_SDRAM_A22_PORT, BOARD_SDRAM_A22_PIN, &SDRAM_A22);
1386
1387 const port_pin_config_t SDRAM_A21 = {/* Internal pull-up/down resistor is disabled */
1388 kPORT_PullDisable,
1389 /* Fast slew rate is configured */
1390 kPORT_FastSlewRate,
1391 /* Passive filter is disabled */
1392 kPORT_PassiveFilterDisable,
1393 /* Open drain is disabled */
1394 kPORT_OpenDrainDisable,
1395 /* Low drive strength is configured */
1396 kPORT_LowDriveStrength,
1397 /* Pin is configured as SDRAM_A21 */
1398 kPORT_MuxAlt5,
1399 /* Pin Control Register fields [15:0] are not locked */
1400 kPORT_UnlockRegister};
1401 /* PORTC1 (pin B12) is configured as SDRAM_A21 */
1402 PORT_SetPinConfig(BOARD_SDRAM_A21_PORT, BOARD_SDRAM_A21_PIN, &SDRAM_A21);
1403
1404 const port_pin_config_t SDRAM_A13 = {/* Internal pull-up/down resistor is disabled */
1405 kPORT_PullDisable,
1406 /* Fast slew rate is configured */
1407 kPORT_FastSlewRate,
1408 /* Passive filter is disabled */
1409 kPORT_PassiveFilterDisable,
1410 /* Open drain is disabled */
1411 kPORT_OpenDrainDisable,
1412 /* Low drive strength is configured */
1413 kPORT_LowDriveStrength,
1414 /* Pin is configured as SDRAM_A13 */
1415 kPORT_MuxAlt5,
1416 /* Pin Control Register fields [15:0] are not locked */
1417 kPORT_UnlockRegister};
1418 /* PORTC10 (pin A8) is configured as SDRAM_A13 */
1419 PORT_SetPinConfig(BOARD_SDRAM_A13_PORT, BOARD_SDRAM_A13_PIN, &SDRAM_A13);
1420
1421 const port_pin_config_t SDRAM_D27 = {/* Internal pull-up/down resistor is disabled */
1422 kPORT_PullDisable,
1423 /* Fast slew rate is configured */
1424 kPORT_FastSlewRate,
1425 /* Passive filter is disabled */
1426 kPORT_PassiveFilterDisable,
1427 /* Open drain is disabled */
1428 kPORT_OpenDrainDisable,
1429 /* Low drive strength is configured */
1430 kPORT_LowDriveStrength,
1431 /* Pin is configured as SDRAM_D27 */
1432 kPORT_MuxAlt5,
1433 /* Pin Control Register fields [15:0] are not locked */
1434 kPORT_UnlockRegister};
1435 /* PORTC12 (pin B9) is configured as SDRAM_D27 */
1436 PORT_SetPinConfig(BOARD_SDRAM_D27_PORT, BOARD_SDRAM_D27_PIN, &SDRAM_D27);
1437
1438 const port_pin_config_t SDRAM_D26 = {/* Internal pull-up/down resistor is disabled */
1439 kPORT_PullDisable,
1440 /* Fast slew rate is configured */
1441 kPORT_FastSlewRate,
1442 /* Passive filter is disabled */
1443 kPORT_PassiveFilterDisable,
1444 /* Open drain is disabled */
1445 kPORT_OpenDrainDisable,
1446 /* Low drive strength is configured */
1447 kPORT_LowDriveStrength,
1448 /* Pin is configured as SDRAM_D26 */
1449 kPORT_MuxAlt5,
1450 /* Pin Control Register fields [15:0] are not locked */
1451 kPORT_UnlockRegister};
1452 /* PORTC13 (pin B8) is configured as SDRAM_D26 */
1453 PORT_SetPinConfig(BOARD_SDRAM_D26_PORT, BOARD_SDRAM_D26_PIN, &SDRAM_D26);
1454
1455 const port_pin_config_t SDRAM_D25 = {/* Internal pull-up/down resistor is disabled */
1456 kPORT_PullDisable,
1457 /* Fast slew rate is configured */
1458 kPORT_FastSlewRate,
1459 /* Passive filter is disabled */
1460 kPORT_PassiveFilterDisable,
1461 /* Open drain is disabled */
1462 kPORT_OpenDrainDisable,
1463 /* Low drive strength is configured */
1464 kPORT_LowDriveStrength,
1465 /* Pin is configured as SDRAM_D25 */
1466 kPORT_MuxAlt5,
1467 /* Pin Control Register fields [15:0] are not locked */
1468 kPORT_UnlockRegister};
1469 /* PORTC14 (pin C8) is configured as SDRAM_D25 */
1470 PORT_SetPinConfig(BOARD_SDRAM_D25_PORT, BOARD_SDRAM_D25_PIN, &SDRAM_D25);
1471
1472 const port_pin_config_t SDRAM_D24 = {/* Internal pull-up/down resistor is disabled */
1473 kPORT_PullDisable,
1474 /* Fast slew rate is configured */
1475 kPORT_FastSlewRate,
1476 /* Passive filter is disabled */
1477 kPORT_PassiveFilterDisable,
1478 /* Open drain is disabled */
1479 kPORT_OpenDrainDisable,
1480 /* Low drive strength is configured */
1481 kPORT_LowDriveStrength,
1482 /* Pin is configured as SDRAM_D24 */
1483 kPORT_MuxAlt5,
1484 /* Pin Control Register fields [15:0] are not locked */
1485 kPORT_UnlockRegister};
1486 /* PORTC15 (pin D8) is configured as SDRAM_D24 */
1487 PORT_SetPinConfig(BOARD_SDRAM_D24_PORT, BOARD_SDRAM_D24_PIN, &SDRAM_D24);
1488
1489 const port_pin_config_t SDRAM_DQM2 = {/* Internal pull-up/down resistor is disabled */
1490 kPORT_PullDisable,
1491 /* Fast slew rate is configured */
1492 kPORT_FastSlewRate,
1493 /* Passive filter is disabled */
1494 kPORT_PassiveFilterDisable,
1495 /* Open drain is disabled */
1496 kPORT_OpenDrainDisable,
1497 /* Low drive strength is configured */
1498 kPORT_LowDriveStrength,
1499 /* Pin is configured as SDRAM_DQM2 */
1500 kPORT_MuxAlt5,
1501 /* Pin Control Register fields [15:0] are not locked */
1502 kPORT_UnlockRegister};
1503 /* PORTC16 (pin E8) is configured as SDRAM_DQM2 */
1504 PORT_SetPinConfig(BOARD_SDRAM_DQM2_PORT, BOARD_SDRAM_DQM2_PIN, &SDRAM_DQM2);
1505
1506 const port_pin_config_t SDRAM_DQM3 = {/* Internal pull-up/down resistor is disabled */
1507 kPORT_PullDisable,
1508 /* Fast slew rate is configured */
1509 kPORT_FastSlewRate,
1510 /* Passive filter is disabled */
1511 kPORT_PassiveFilterDisable,
1512 /* Open drain is disabled */
1513 kPORT_OpenDrainDisable,
1514 /* Low drive strength is configured */
1515 kPORT_LowDriveStrength,
1516 /* Pin is configured as SDRAM_DQM3 */
1517 kPORT_MuxAlt5,
1518 /* Pin Control Register fields [15:0] are not locked */
1519 kPORT_UnlockRegister};
1520 /* PORTC17 (pin E7) is configured as SDRAM_DQM3 */
1521 PORT_SetPinConfig(BOARD_SDRAM_DQM3_PORT, BOARD_SDRAM_DQM3_PIN, &SDRAM_DQM3);
1522
1523 const port_pin_config_t SDRAM_A20 = {/* Internal pull-up/down resistor is disabled */
1524 kPORT_PullDisable,
1525 /* Fast slew rate is configured */
1526 kPORT_FastSlewRate,
1527 /* Passive filter is disabled */
1528 kPORT_PassiveFilterDisable,
1529 /* Open drain is disabled */
1530 kPORT_OpenDrainDisable,
1531 /* Low drive strength is configured */
1532 kPORT_LowDriveStrength,
1533 /* Pin is configured as SDRAM_A20 */
1534 kPORT_MuxAlt5,
1535 /* Pin Control Register fields [15:0] are not locked */
1536 kPORT_UnlockRegister};
1537 /* PORTC2 (pin A13) is configured as SDRAM_A20 */
1538 PORT_SetPinConfig(BOARD_SDRAM_A20_PORT, BOARD_SDRAM_A20_PIN, &SDRAM_A20);
1539
1540 const port_pin_config_t CLKOUT = {/* Internal pull-up/down resistor is disabled */
1541 kPORT_PullDisable,
1542 /* Fast slew rate is configured */
1543 kPORT_FastSlewRate,
1544 /* Passive filter is disabled */
1545 kPORT_PassiveFilterDisable,
1546 /* Open drain is disabled */
1547 kPORT_OpenDrainDisable,
1548 /* Low drive strength is configured */
1549 kPORT_LowDriveStrength,
1550 /* Pin is configured as CLKOUT */
1551 kPORT_MuxAlt5,
1552 /* Pin Control Register fields [15:0] are not locked */
1553 kPORT_UnlockRegister};
1554 /* PORTC3 (pin A12) is configured as CLKOUT */
1555 PORT_SetPinConfig(BOARD_CLKOUT_PORT, BOARD_CLKOUT_PIN, &CLKOUT);
1556
1557 const port_pin_config_t SDRAM_A19 = {/* Internal pull-up/down resistor is disabled */
1558 kPORT_PullDisable,
1559 /* Fast slew rate is configured */
1560 kPORT_FastSlewRate,
1561 /* Passive filter is disabled */
1562 kPORT_PassiveFilterDisable,
1563 /* Open drain is disabled */
1564 kPORT_OpenDrainDisable,
1565 /* Low drive strength is configured */
1566 kPORT_LowDriveStrength,
1567 /* Pin is configured as SDRAM_A19 */
1568 kPORT_MuxAlt5,
1569 /* Pin Control Register fields [15:0] are not locked */
1570 kPORT_UnlockRegister};
1571 /* PORTC4 (pin B11) is configured as SDRAM_A19 */
1572 PORT_SetPinConfig(BOARD_SDRAM_A19_PORT, BOARD_SDRAM_A19_PIN, &SDRAM_A19);
1573
1574 const port_pin_config_t SDRAM_A18 = {/* Internal pull-up/down resistor is disabled */
1575 kPORT_PullDisable,
1576 /* Fast slew rate is configured */
1577 kPORT_FastSlewRate,
1578 /* Passive filter is disabled */
1579 kPORT_PassiveFilterDisable,
1580 /* Open drain is disabled */
1581 kPORT_OpenDrainDisable,
1582 /* Low drive strength is configured */
1583 kPORT_LowDriveStrength,
1584 /* Pin is configured as SDRAM_A18 */
1585 kPORT_MuxAlt5,
1586 /* Pin Control Register fields [15:0] are not locked */
1587 kPORT_UnlockRegister};
1588 /* PORTC5 (pin A11) is configured as SDRAM_A18 */
1589 PORT_SetPinConfig(BOARD_SDRAM_A18_PORT, BOARD_SDRAM_A18_PIN, &SDRAM_A18);
1590
1591 const port_pin_config_t SDRAM_A16 = {/* Internal pull-up/down resistor is disabled */
1592 kPORT_PullDisable,
1593 /* Fast slew rate is configured */
1594 kPORT_FastSlewRate,
1595 /* Passive filter is disabled */
1596 kPORT_PassiveFilterDisable,
1597 /* Open drain is disabled */
1598 kPORT_OpenDrainDisable,
1599 /* Low drive strength is configured */
1600 kPORT_LowDriveStrength,
1601 /* Pin is configured as SDRAM_A16 */
1602 kPORT_MuxAlt5,
1603 /* Pin Control Register fields [15:0] are not locked */
1604 kPORT_UnlockRegister};
1605 /* PORTC7 (pin B10) is configured as SDRAM_A16 */
1606 PORT_SetPinConfig(BOARD_SDRAM_A16_PORT, BOARD_SDRAM_A16_PIN, &SDRAM_A16);
1607
1608 const port_pin_config_t SDRAM_A15 = {/* Internal pull-up/down resistor is disabled */
1609 kPORT_PullDisable,
1610 /* Fast slew rate is configured */
1611 kPORT_FastSlewRate,
1612 /* Passive filter is disabled */
1613 kPORT_PassiveFilterDisable,
1614 /* Open drain is disabled */
1615 kPORT_OpenDrainDisable,
1616 /* Low drive strength is configured */
1617 kPORT_LowDriveStrength,
1618 /* Pin is configured as SDRAM_A15 */
1619 kPORT_MuxAlt5,
1620 /* Pin Control Register fields [15:0] are not locked */
1621 kPORT_UnlockRegister};
1622 /* PORTC8 (pin C10) is configured as SDRAM_A15 */
1623 PORT_SetPinConfig(BOARD_SDRAM_A15_PORT, BOARD_SDRAM_A15_PIN, &SDRAM_A15);
1624
1625 const port_pin_config_t SDRAM_A14 = {/* Internal pull-up/down resistor is disabled */
1626 kPORT_PullDisable,
1627 /* Fast slew rate is configured */
1628 kPORT_FastSlewRate,
1629 /* Passive filter is disabled */
1630 kPORT_PassiveFilterDisable,
1631 /* Open drain is disabled */
1632 kPORT_OpenDrainDisable,
1633 /* Low drive strength is configured */
1634 kPORT_LowDriveStrength,
1635 /* Pin is configured as SDRAM_A14 */
1636 kPORT_MuxAlt5,
1637 /* Pin Control Register fields [15:0] are not locked */
1638 kPORT_UnlockRegister};
1639 /* PORTC9 (pin C9) is configured as SDRAM_A14 */
1640 PORT_SetPinConfig(BOARD_SDRAM_A14_PORT, BOARD_SDRAM_A14_PIN, &SDRAM_A14);
1641 /* Configure digital filter */
1642 PORT_EnablePinsDigitalFilter(
1643 /* Digital filter is configured on port D */
1644 PORTD,
1645 /* Digital filter is configured for PORTD0 */
1646 PORT_DFER_DFE_2_MASK
1647 /* Digital filter is configured for PORTD1 */
1648 | PORT_DFER_DFE_3_MASK
1649 /* Digital filter is configured for PORTD2 */
1650 | PORT_DFER_DFE_4_MASK
1651 /* Digital filter is configured for PORTD3 */
1652 | PORT_DFER_DFE_5_MASK
1653 /* Digital filter is configured for PORTD4 */
1654 | PORT_DFER_DFE_7_MASK,
1655 /* Disable digital filter */
1656 false);
1657
1658 const port_pin_config_t SDRAM_A12 = {/* Internal pull-up/down resistor is disabled */
1659 kPORT_PullDisable,
1660 /* Fast slew rate is configured */
1661 kPORT_FastSlewRate,
1662 /* Passive filter is disabled */
1663 kPORT_PassiveFilterDisable,
1664 /* Open drain is disabled */
1665 kPORT_OpenDrainDisable,
1666 /* Low drive strength is configured */
1667 kPORT_LowDriveStrength,
1668 /* Pin is configured as SDRAM_A12 */
1669 kPORT_MuxAlt5,
1670 /* Pin Control Register fields [15:0] are not locked */
1671 kPORT_UnlockRegister};
1672 /* PORTD2 (pin A4) is configured as SDRAM_A12 */
1673 PORT_SetPinConfig(BOARD_SDRAM_A12_PORT, BOARD_SDRAM_A12_PIN, &SDRAM_A12);
1674
1675 const port_pin_config_t SDRAM_A11 = {/* Internal pull-up/down resistor is disabled */
1676 kPORT_PullDisable,
1677 /* Fast slew rate is configured */
1678 kPORT_FastSlewRate,
1679 /* Passive filter is disabled */
1680 kPORT_PassiveFilterDisable,
1681 /* Open drain is disabled */
1682 kPORT_OpenDrainDisable,
1683 /* Low drive strength is configured */
1684 kPORT_LowDriveStrength,
1685 /* Pin is configured as SDRAM_A11 */
1686 kPORT_MuxAlt5,
1687 /* Pin Control Register fields [15:0] are not locked */
1688 kPORT_UnlockRegister};
1689 /* PORTD3 (pin B4) is configured as SDRAM_A11 */
1690 PORT_SetPinConfig(BOARD_SDRAM_A11_PORT, BOARD_SDRAM_A11_PIN, &SDRAM_A11);
1691
1692 const port_pin_config_t SDRAM_A10 = {/* Internal pull-up/down resistor is disabled */
1693 kPORT_PullDisable,
1694 /* Fast slew rate is configured */
1695 kPORT_FastSlewRate,
1696 /* Passive filter is disabled */
1697 kPORT_PassiveFilterDisable,
1698 /* Open drain is disabled */
1699 kPORT_OpenDrainDisable,
1700 /* Low drive strength is configured */
1701 kPORT_LowDriveStrength,
1702 /* Pin is configured as SDRAM_A10 */
1703 kPORT_MuxAlt5,
1704 /* Pin Control Register fields [15:0] are not locked */
1705 kPORT_UnlockRegister};
1706 /* PORTD4 (pin B5) is configured as SDRAM_A10 */
1707 PORT_SetPinConfig(BOARD_SDRAM_A10_PORT, BOARD_SDRAM_A10_PIN, &SDRAM_A10);
1708
1709 const port_pin_config_t SDRAM_A9 = {/* Internal pull-up/down resistor is disabled */
1710 kPORT_PullDisable,
1711 /* Fast slew rate is configured */
1712 kPORT_FastSlewRate,
1713 /* Passive filter is disabled */
1714 kPORT_PassiveFilterDisable,
1715 /* Open drain is disabled */
1716 kPORT_OpenDrainDisable,