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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.c27
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.h85
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c372
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.h145
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.c54
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.c658
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.h358
8 files changed, 1733 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.c
new file mode 100644
index 000000000..acd8c59f3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.c
@@ -0,0 +1,27 @@
1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <stdint.h>
10#include "fsl_common.h"
11#include "fsl_debug_console.h"
12#include "board.h"
13
14/*******************************************************************************
15 * Variables
16 ******************************************************************************/
17
18/*******************************************************************************
19 * Code
20 ******************************************************************************/
21/* Initialize debug console. */
22void BOARD_InitDebugConsole(void)
23{
24 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
25
26 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
27}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.h
new file mode 100644
index 000000000..3494ac1a1
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/board.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _BOARD_H_
10#define _BOARD_H_
11
12#include "clock_config.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "HVP-KV31F120M"
20
21/*! @brief The UART to use for debug messages. */
22#define BOARD_USE_UART
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0
25#define BOARD_DEBUG_UART_INSTANCE 0U
26#define BOARD_DEBUG_UART_CLKSRC kCLOCK_CoreSysClk
27#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetCoreSysClkFreq()
28#define BOARD_UART_IRQ UART0_RX_TX_IRQn
29#define BOARD_UART_IRQ_HANDLER UART0_RX_TX_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE 115200
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* Board led color mapping */
36#define LOGIC_LED_ON 0U
37#define LOGIC_LED_OFF 1U
38#ifndef BOARD_LED_RED_GPIO
39#define BOARD_LED_RED_GPIO GPIOA
40#endif
41#define BOARD_LED_RED_GPIO_PORT PORTA
42#ifndef BOARD_LED_RED_GPIO_PIN
43#define BOARD_LED_RED_GPIO_PIN 5U
44#endif
45#ifndef BOARD_LED_GREEN_GPIO
46#define BOARD_LED_GREEN_GPIO GPIOB
47#endif
48#define BOARD_LED_GREEN_GPIO_PORT PORTB
49#ifndef BOARD_LED_GREEN_GPIO_PIN
50#define BOARD_LED_GREEN_GPIO_PIN 19U
51#endif
52
53#define LED_RED_INIT(output) \
54 GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
55 BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
56#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
57#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
58#define LED_RED_TOGGLE() \
59 GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
60
61#define LED_GREEN_INIT(output) \
62 GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
63 BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
64#define LED_GREEN_ON() \
65 GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
66#define LED_GREEN_OFF() \
67 GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
68#define LED_GREEN_TOGGLE() \
69 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
70
71#if defined(__cplusplus)
72extern "C" {
73#endif /* __cplusplus */
74
75/*******************************************************************************
76 * API
77 ******************************************************************************/
78
79void BOARD_InitDebugConsole(void);
80
81#if defined(__cplusplus)
82}
83#endif /* __cplusplus */
84
85#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c
new file mode 100644
index 000000000..7934a5f0d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c
@@ -0,0 +1,372 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40/* clang-format off */
41/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42!!GlobalInfo
43product: Clocks v4.1
44processor: MKV31F512xxx12
45package_id: MKV31F512VLL12
46mcu_data: ksdk2_0
47processor_version: 4.0.0
48board: HVP-KV31F120M
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50/* clang-format on */
51
52#include "fsl_smc.h"
53#include "clock_config.h"
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
59#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
60#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
61#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
62#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
63#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
64
65/*******************************************************************************
66 * Variables
67 ******************************************************************************/
68/* System clock frequency. */
69extern uint32_t SystemCoreClock;
70
71/*******************************************************************************
72 * Code
73 ******************************************************************************/
74/*FUNCTION**********************************************************************
75 *
76 * Function Name : CLOCK_CONFIG_FllStableDelay
77 * Description : This function is used to delay for FLL stable.
78 *
79 *END**************************************************************************/
80static void CLOCK_CONFIG_FllStableDelay(void)
81{
82 uint32_t i = 30000U;
83 while (i--)
84 {
85 __NOP();
86 }
87}
88
89/*******************************************************************************
90 ************************ BOARD_InitBootClocks function ************************
91 ******************************************************************************/
92void BOARD_InitBootClocks(void)
93{
94 BOARD_BootClockRUN();
95}
96
97/*******************************************************************************
98 ********************** Configuration BOARD_BootClockRUN ***********************
99 ******************************************************************************/
100/* clang-format off */
101/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
102!!Configuration
103name: BOARD_BootClockRUN
104called_from_default_init: true
105outputs:
106- {id: Bus_clock.outFreq, value: 31.45728 MHz}
107- {id: Core_clock.outFreq, value: 62.91456 MHz}
108- {id: Flash_clock.outFreq, value: 15.72864 MHz}
109- {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
110- {id: LPO_clock.outFreq, value: 1 kHz}
111- {id: LPUARTCLK.outFreq, value: 4 MHz}
112- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
113- {id: MCGIRCLK.outFreq, value: 4 MHz}
114- {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
115- {id: System_clock.outFreq, value: 62.91456 MHz}
116settings:
117- {id: LPUARTClkConfig, value: 'yes'}
118- {id: MCG.FCRDIV.scale, value: '1'}
119- {id: MCG.FLL_mul.scale, value: '1920', locked: true}
120- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
121- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
122- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
123- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
124- {id: SIM.OUTDIV2.scale, value: '2'}
125- {id: SIM.OUTDIV3.scale, value: '4'}
126- {id: SIM.OUTDIV4.scale, value: '4'}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128/* clang-format on */
129
130/*******************************************************************************
131 * Variables for BOARD_BootClockRUN configuration
132 ******************************************************************************/
133const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
134 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
135 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
136 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
137 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
138 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
139 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
140 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
141 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
142 .pll0Config =
143 {
144 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
145 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
146 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
147 },
148};
149const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
150 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
151 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
152 .clkdiv1 = 0x1330000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
153};
154const osc_config_t oscConfig_BOARD_BootClockRUN = {
155 .freq = 0U, /* Oscillator frequency: 0Hz */
156 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
157 .workMode = kOSC_ModeExt, /* Use external clock */
158 .oscerConfig = {
159 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
160 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
161 }};
162
163/*******************************************************************************
164 * Code for BOARD_BootClockRUN configuration
165 ******************************************************************************/
166void BOARD_BootClockRUN(void)
167{
168 /* Set the system clock dividers in SIM to safe value. */
169 CLOCK_SetSimSafeDivs();
170 /* Configure the Internal Reference clock (MCGIRCLK). */
171 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
172 mcgConfig_BOARD_BootClockRUN.fcrdiv);
173 /* Set MCG to FEI mode. */
174#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
175 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
176 CLOCK_CONFIG_FllStableDelay);
177#else
178 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
179#endif
180 /* Set the clock configuration in SIM module. */
181 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
182 /* Set SystemCoreClock variable. */
183 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
184 /* Set LPUART clock source. */
185 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
186}
187
188/*******************************************************************************
189 ********************* Configuration BOARD_BootClockHSRUN **********************
190 ******************************************************************************/
191/* clang-format off */
192/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
193!!Configuration
194name: BOARD_BootClockHSRUN
195outputs:
196- {id: Bus_clock.outFreq, value: 41.94304 MHz}
197- {id: Core_clock.outFreq, value: 83.88608 MHz}
198- {id: Flash_clock.outFreq, value: 20.97152 MHz}
199- {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
200- {id: LPO_clock.outFreq, value: 1 kHz}
201- {id: LPUARTCLK.outFreq, value: 4 MHz}
202- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
203- {id: MCGIRCLK.outFreq, value: 4 MHz}
204- {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
205- {id: System_clock.outFreq, value: 83.88608 MHz}
206settings:
207- {id: powerMode, value: HSRUN}
208- {id: LPUARTClkConfig, value: 'yes'}
209- {id: MCG.FCRDIV.scale, value: '1'}
210- {id: MCG.FLL_mul.scale, value: '2560'}
211- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
212- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
213- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
214- {id: SIM.OUTDIV2.scale, value: '2'}
215- {id: SIM.OUTDIV3.scale, value: '3'}
216- {id: SIM.OUTDIV4.scale, value: '4'}
217 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
218/* clang-format on */
219
220/*******************************************************************************
221 * Variables for BOARD_BootClockHSRUN configuration
222 ******************************************************************************/
223const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
224 .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
225 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
226 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
227 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
228 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
229 .drs = kMCG_DrsHigh, /* High frequency range */
230 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
231 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
232 .pll0Config =
233 {
234 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
235 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
236 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
237 },
238};
239const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
240 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
241 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
242 .clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
243};
244const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
245 .freq = 0U, /* Oscillator frequency: 0Hz */
246 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
247 .workMode = kOSC_ModeExt, /* Use external clock */
248 .oscerConfig = {
249 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
250 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
251 }};
252
253/*******************************************************************************
254 * Code for BOARD_BootClockHSRUN configuration
255 ******************************************************************************/
256void BOARD_BootClockHSRUN(void)
257{
258 /* Set HSRUN power mode */
259 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
260 SMC_SetPowerModeHsrun(SMC);
261 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
262 {
263 }
264 /* Set the system clock dividers in SIM to safe value. */
265 CLOCK_SetSimSafeDivs();
266 /* Configure the Internal Reference clock (MCGIRCLK). */
267 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
268 mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
269 /* Set MCG to FEI mode. */
270#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
271 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32, mcgConfig_BOARD_BootClockHSRUN.drs,
272 CLOCK_CONFIG_FllStableDelay);
273#else
274 CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs, CLOCK_CONFIG_FllStableDelay);
275#endif
276 /* Set the clock configuration in SIM module. */
277 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
278 /* Set SystemCoreClock variable. */
279 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
280 /* Set LPUART clock source. */
281 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
282}
283
284/*******************************************************************************
285 ********************* Configuration BOARD_BootClockVLPR ***********************
286 ******************************************************************************/
287/* clang-format off */
288/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
289!!Configuration
290name: BOARD_BootClockVLPR
291outputs:
292- {id: Bus_clock.outFreq, value: 4 MHz}
293- {id: Core_clock.outFreq, value: 4 MHz}
294- {id: Flash_clock.outFreq, value: 800 kHz}
295- {id: FlexBus_clock.outFreq, value: 2 MHz}
296- {id: LPO_clock.outFreq, value: 1 kHz}
297- {id: LPUARTCLK.outFreq, value: 4 MHz}
298- {id: MCGIRCLK.outFreq, value: 4 MHz}
299- {id: System_clock.outFreq, value: 4 MHz}
300settings:
301- {id: MCGMode, value: BLPI}
302- {id: powerMode, value: VLPR}
303- {id: LPUARTClkConfig, value: 'yes'}
304- {id: MCG.CLKS.sel, value: MCG.IRCS}
305- {id: MCG.FCRDIV.scale, value: '1'}
306- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
307- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
308- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
309- {id: SIM.OUTDIV4.scale, value: '5'}
310 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
311/* clang-format on */
312
313/*******************************************************************************
314 * Variables for BOARD_BootClockVLPR configuration
315 ******************************************************************************/
316const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
317 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
318 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
319 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
320 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
321 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
322 .drs = kMCG_DrsLow, /* Low frequency range */
323 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
324 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
325 .pll0Config =
326 {
327 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
328 .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
329 .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
330 },
331};
332const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
333 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
334 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
335 .clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
336};
337const osc_config_t oscConfig_BOARD_BootClockVLPR = {
338 .freq = 0U, /* Oscillator frequency: 0Hz */
339 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
340 .workMode = kOSC_ModeExt, /* Use external clock */
341 .oscerConfig = {
342 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
343 .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
344 }};
345
346/*******************************************************************************
347 * Code for BOARD_BootClockVLPR configuration
348 ******************************************************************************/
349void BOARD_BootClockVLPR(void)
350{
351 /* Set the system clock dividers in SIM to safe value. */
352 CLOCK_SetSimSafeDivs();
353 /* Set MCG to BLPI mode. */
354 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
355 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
356 /* Set the clock configuration in SIM module. */
357 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
358 /* Set VLPR power mode. */
359 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
360#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
361 SMC_SetPowerModeVlpr(SMC, false);
362#else
363 SMC_SetPowerModeVlpr(SMC);
364#endif
365 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
366 {
367 }
368 /* Set SystemCoreClock variable. */
369 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
370 /* Set LPUART clock source. */
371 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
372}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.h
new file mode 100644
index 000000000..8e4cd9b8f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22/*******************************************************************************
23 ************************ BOARD_InitBootClocks function ************************
24 ******************************************************************************/
25
26#if defined(__cplusplus)
27extern "C" {
28#endif /* __cplusplus*/
29
30/*!
31 * @brief This function executes default configuration of clocks.
32 *
33 */
34void BOARD_InitBootClocks(void);
35
36#if defined(__cplusplus)
37}
38#endif /* __cplusplus*/
39
40/*******************************************************************************
41 ********************** Configuration BOARD_BootClockRUN ***********************
42 ******************************************************************************/
43/*******************************************************************************
44 * Definitions for BOARD_BootClockRUN configuration
45 ******************************************************************************/
46#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 62914560U /*!< Core clock frequency: 62914560Hz */
47
48/*! @brief MCG set for BOARD_BootClockRUN configuration.
49 */
50extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
51/*! @brief SIM module set for BOARD_BootClockRUN configuration.
52 */
53extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
54/*! @brief OSC set for BOARD_BootClockRUN configuration.
55 */
56extern const osc_config_t oscConfig_BOARD_BootClockRUN;
57
58/*******************************************************************************
59 * API for BOARD_BootClockRUN configuration
60 ******************************************************************************/
61#if defined(__cplusplus)
62extern "C" {
63#endif /* __cplusplus*/
64
65/*!
66 * @brief This function executes configuration of clocks.
67 *
68 */
69void BOARD_BootClockRUN(void);
70
71#if defined(__cplusplus)
72}
73#endif /* __cplusplus*/
74
75/*******************************************************************************
76 ********************* Configuration BOARD_BootClockHSRUN **********************
77 ******************************************************************************/
78/*******************************************************************************
79 * Definitions for BOARD_BootClockHSRUN configuration
80 ******************************************************************************/
81#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 83886080U /*!< Core clock frequency: 83886080Hz */
82
83/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
84 */
85extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
86/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
87 */
88extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
89/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
90 */
91extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
92
93/*******************************************************************************
94 * API for BOARD_BootClockHSRUN configuration
95 ******************************************************************************/
96#if defined(__cplusplus)
97extern "C" {
98#endif /* __cplusplus*/
99
100/*!
101 * @brief This function executes configuration of clocks.
102 *
103 */
104void BOARD_BootClockHSRUN(void);
105
106#if defined(__cplusplus)
107}
108#endif /* __cplusplus*/
109
110/*******************************************************************************
111 ********************* Configuration BOARD_BootClockVLPR ***********************
112 ******************************************************************************/
113/*******************************************************************************
114 * Definitions for BOARD_BootClockVLPR configuration
115 ******************************************************************************/
116#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
117
118/*! @brief MCG set for BOARD_BootClockVLPR configuration.
119 */
120extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
121/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
122 */
123extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
124/*! @brief OSC set for BOARD_BootClockVLPR configuration.
125 */
126extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
127
128/*******************************************************************************
129 * API for BOARD_BootClockVLPR configuration
130 ******************************************************************************/
131#if defined(__cplusplus)
132extern "C" {
133#endif /* __cplusplus*/
134
135/*!
136 * @brief This function executes configuration of clocks.
137 *
138 */
139void BOARD_BootClockVLPR(void);
140
141#if defined(__cplusplus)
142}
143#endif /* __cplusplus*/
144
145#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.c
new file mode 100644
index 000000000..ebb3f4bbf
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.c
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v4.1
17processor: MKV31F512xxx12
18package_id: MKV31F512VLL12
19mcu_data: ksdk2_0
20processor_version: 4.0.0
21board: HVP-KV31F120M
22functionalGroups:
23- name: BOARD_InitPeripherals
24 called_from_default_init: true
25 selectedCore: core0
26 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29component:
30- type: 'system'
31- type_id: 'system'
32- global_system_definitions: []
33 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
34/* clang-format on */
35
36/***********************************************************************************************************************
37 * Included files
38 **********************************************************************************************************************/
39#include "peripherals.h"
40
41/***********************************************************************************************************************
42 * Initialization functions
43 **********************************************************************************************************************/
44void BOARD_InitPeripherals(void)
45{
46}
47
48/***********************************************************************************************************************
49 * BOARD_InitBootPeripherals function
50 **********************************************************************************************************************/
51void BOARD_InitBootPeripherals(void)
52{
53 BOARD_InitPeripherals();
54}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.h
new file mode 100644
index 000000000..321b18acb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.c
new file mode 100644
index 000000000..c3730c9a8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.c
@@ -0,0 +1,658 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* clang-format off */
9/*
10 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11!!GlobalInfo
12product: Pins v5.0
13processor: MKV31F512xxx12
14package_id: MKV31F512VLL12
15mcu_data: ksdk2_0
16processor_version: 0.0.18
17board: HVP-KV31F120M
18pin_labels:
19- {pin_num: '39', pin_signal: PTA5/FTM0_CH2/JTAG_TRST_b, label: USER_LED_2, identifier: LED_RED}
20- {pin_num: '8', pin_signal: VDD8, label: 3.3V}
21- {pin_num: '9', pin_signal: VSS9, label: GND}
22- {pin_num: '22', pin_signal: VDDA, label: 3.3VA}
23- {pin_num: '23', pin_signal: VREFH, label: 3.3VA}
24- {pin_num: '24', pin_signal: VREFL, label: GNDA}
25- {pin_num: '25', pin_signal: VSSA, label: GNDA}
26- {pin_num: '29', pin_signal: VSS29, label: GND}
27- {pin_num: '30', pin_signal: VDD30, label: 3.3V}
28- {pin_num: '40', pin_signal: VDD40, label: 3.3V}
29- {pin_num: '41', pin_signal: VSS41, label: GND}
30- {pin_num: '48', pin_signal: VDD48, label: 3.3V}
31- {pin_num: '49', pin_signal: VSS49, label: GND}
32- {pin_num: '60', pin_signal: VSS60, label: GND}
33- {pin_num: '61', pin_signal: VDD61, label: 3.3V}
34- {pin_num: '75', pin_signal: VDD75, label: 3.3V}
35- {pin_num: '89', pin_signal: VDD89, label: 3.3V}
36- {pin_num: '88', pin_signal: VSS88, label: GND}
37- {pin_num: '74', pin_signal: VSS74, label: GND}
38- {pin_num: '34', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/EWM_IN/JTAG_TCLK/SWD_CLK/EZP_CLK, label: 'J3[4]/U4[11]/U5[13]/SWCLK/SWDCLK_ISOLATED'}
39- {pin_num: '37', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/FTM2_FLT0/EWM_OUT_b/JTAG_TMS/SWD_DIO, label: 'J3[2]/U4[3]/U5[14]/SWDIO/SWDIO_ISOLATED'}
40- {pin_num: '36', pin_signal: PTA2/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/JTAG_TDO/TRACE_SWO/EZP_DO, label: 'J3[6]/U5[12]/SWO/SWO_ISOLATED'}
41- {pin_num: '52', pin_signal: RESET_b, label: 'J3[10]/U5[11]/SW1/''/RESET''/''RESET_ISOLATED'''}
42- {pin_num: '62', pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, label: 'U2[24]/U6[13]/TxD_sda/UART_TX_TGTMCU', identifier: UART_TX_TGTMCU}
43- {pin_num: '63', pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, label: 'U2[25]/U6[14]/RxD_sda/UART_RX_TGTMCU', identifier: UART_RX_TGTMCU}
44- {pin_num: '12', pin_signal: ADC0_SE6a/PTE18/SPI0_SOUT/UART2_CTS_b/I2C0_SDA, label: MOSI/TP21}
45- {pin_num: '11', pin_signal: ADC0_SE5a/PTE17/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3, label: 'MB_J3[2]/MB_J11[B27]/MB_U1[12]/MB_U3[26]/MB_TP2/MB_TP10/MB_RxD/J4[B27]/RxD/MISO/TP19',
46 identifier: RXD}
47- {pin_num: '93', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b, label: '''/SS''/TP18'}
48- {pin_num: '94', pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, label: SCK/TP20}
49- {pin_num: '95', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/LPUART0_RX/I2C0_SCL, label: SCL0/TP23}
50- {pin_num: '96', pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/LPUART0_TX/I2C0_SDA, label: SDA0/TP22}
51- {pin_num: '65', pin_signal: PTB19/FTM2_CH1/FB_OE_b/FTM2_QD_PHB, label: 'MB_J11[B20]/MB_U9[4]/MB_USER_LED/J4[B20]/USER_LED', identifier: LED_GREEN}
52- {pin_num: '1', pin_signal: ADC1_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/I2C1_SDA, label: 'MB_J1[1]/MB_J2[3]/MB_J11[A31]/MB_TxD_1/MB_TxD_EXT/J4[A31]/TxD1', identifier: TXD_1}
53- {pin_num: '2', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN, label: 'MB_J2[4]/MB_J3[4]/MB_J11[A32]/MB_RxD_1/MB_RxD_EXT/J4[A32]/RxD1',
54 identifier: RXD_1}
55- {pin_num: '3', pin_signal: ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b, label: NC}
56- {pin_num: '4', pin_signal: ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SPI1_SOUT, label: NC}
57- {pin_num: '5', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/LPUART0_TX, label: NC}
58- {pin_num: '6', pin_signal: PTE5/SPI1_PCS2/LPUART0_RX/FTM3_CH0, label: 'MB_J11[A22]/MB_U14[4]/MB_TP15/MB_PWM_PFC2/J4[A22]/PWM8', identifier: PWM_PFC2}
59- {pin_num: '7', pin_signal: PTE6/SPI1_PCS3/LPUART0_CTS_b/FTM3_CH1, label: 'MB_J11[A23]/MB_U14[2]/MB_TP12/MB_PWM_PFC1/J4[A23]/PWM9', identifier: PWM_PFC1}
60- {pin_num: '10', pin_signal: ADC0_SE4a/PTE16/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3, label: 'MB_J1[3]/MB_J11[B26]/MB_U1[13]/MB_U3[25]/MB_TP3/MB_TP7/MB_TxD/J4[B26]/TxD',
61 identifier: TXD}
62- {pin_num: '13', pin_signal: ADC0_SE7a/PTE19/SPI0_SIN/UART2_RTS_b/I2C0_SCL, label: MISO/TP19}
63- {pin_num: '14', pin_signal: ADC0_DP1, label: NC}
64- {pin_num: '15', pin_signal: ADC0_DM1, label: TP24}
65- {pin_num: '16', pin_signal: ADC1_DP1/ADC0_DP2, label: NC}
66- {pin_num: '17', pin_signal: ADC1_DM1/ADC0_DM2, label: 'MB_J11[B8]/MB_TP41/MB_BEMF_sense_C/MB_Phase_C/J4[B8]/BEMF_C', identifier: BEMF_C}
67- {pin_num: '18', pin_signal: ADC0_DP0/ADC1_DP3, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC', identifier: I_PH_C_2}
68- {pin_num: '54', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX, label: 'MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC',
69 identifier: I_PH_C}
70- {pin_num: '19', pin_signal: ADC0_DM0/ADC1_DM3, label: 'MB_J11[B6]/MB_TP44/MB_BEMF_sense_A/MB_Phase_A/J4[B6]/BEMF_A', identifier: BEMF_A}
71- {pin_num: '20', pin_signal: ADC1_DP0/ADC0_DP3, label: 'MB_J11[A4]/MB_U11B[7]/MB_TP40/MB_I_sense_B/J4[A4]/I_phB', identifier: I_PH_B}
72- {pin_num: '21', pin_signal: ADC1_DM0/ADC0_DM3, label: 'MB_J11[B7]/MB_TP43/MB_BEMF_sense_B/MB_Phase_B/J4[B7]/BEMF_B', identifier: BEMF_B}
73- {pin_num: '26', pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18, label: 'MB_J11[B3]/MB_U8B[7]/MB_TP34/MB_I_sense_DCB/J4[B3]/I_dcb', identifier: I_DCB}
74- {pin_num: '27', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23, label: 'MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in', identifier: V_IN}
75- {pin_num: '28', pin_signal: DAC1_OUT/CMP0_IN4/ADC1_SE23, label: 'MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in', identifier: V_IN_2}
76- {pin_num: '31', pin_signal: ADC0_SE17/PTE24/FTM0_CH0/I2C0_SCL/EWM_OUT_b, label: 'MB_J11[B17]/J4[B17]/MB_TP_29'}
77- {pin_num: '32', pin_signal: ADC0_SE18/PTE25/FTM0_CH1/I2C0_SDA/EWM_IN, label: NC}
78- {pin_num: '33', pin_signal: PTE26/CLKOUT32K, label: NC}
79- {pin_num: '35', pin_signal: PTA1/UART0_RX/FTM0_CH6/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/JTAG_TDI/EZP_DI, label: NC}
80- {pin_num: '38', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM0_FLT3/NMI_b/EZP_CS_b, label: nmi, identifier: NMI}
81- {pin_num: '42', pin_signal: PTA12/FTM1_CH0/FTM1_QD_PHA, label: 'MB_J9[3]/MB_J11[B14]/MB_TP13/MB_ENC_PhaseA/J4[B14]/TM0', identifier: ENC_PHASE_A}
82- {pin_num: '43', pin_signal: PTA13/LLWU_P4/FTM1_CH1/FTM1_QD_PHB, label: 'MB_J9[4]/MB_J11[B15]/MB_TP17/MB_ENC_PhaseB/J4[B15]/TM1', identifier: ENC_PHASE_B}
83- {pin_num: '44', pin_signal: PTA14/SPI0_PCS0/UART0_TX, label: NC}
84- {pin_num: '45', pin_signal: PTA15/SPI0_SCK/UART0_RX, label: NC}
85- {pin_num: '46', pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b, label: NC}
86- {pin_num: '47', pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b, label: NC}
87- {pin_num: '50', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, label: NC}
88- {pin_num: '51', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'MB_J11[A25]/MB_U12[11]/MB_TP28/MB_FAULT/MB_FAULT_1/MB_PFC_overcurrent/J4[A25]/FAULT_1',
89 identifier: FAULT_1}
90- {pin_num: '53', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, label: 'MB_J11[A3]/MB_U11A[1]/MB_TP45/MB_I_sense_A/J4[A3]/I_phA',
91 identifier: I_PH_A}
92- {pin_num: '55', pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, label: 'MB_J11[B4]/MB_TP31/MB_V_sense_DCB/MB_DCB_Pos/J4[B4]/U_dcb', identifier: U_DCB}
93- {pin_num: '56', pin_signal: ADC0_SE13/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: NC}
94- {pin_num: '57', pin_signal: PTB9/SPI1_PCS1/LPUART0_CTS_b/FB_AD20, label: NC}
95- {pin_num: '58', pin_signal: ADC1_SE14/PTB10/SPI1_PCS0/LPUART0_RX/FB_AD19/FTM0_FLT1, label: 'MB_J11[A30]/MB_TP22/J4[A30]/MB_TP_22'}
96- {pin_num: '59', pin_signal: ADC1_SE15/PTB11/SPI1_SCK/LPUART0_TX/FB_AD18/FTM0_FLT2, label: 'MB_J11[A29]/MB_TP24/J4[A29]/MB_TP_24'}
97- {pin_num: '64', pin_signal: PTB18/FTM2_CH0/FB_AD15/FTM2_QD_PHA, label: NC}
98- {pin_num: '66', pin_signal: PTB20/FB_AD31/CMP0_OUT, label: NC}
99- {pin_num: '67', pin_signal: PTB21/FB_AD30/CMP1_OUT, label: NC}
100- {pin_num: '68', pin_signal: PTB22/FB_AD29, label: NC}
101- {pin_num: '69', pin_signal: PTB23/SPI0_PCS5/FB_AD28, label: NC}
102- {pin_num: '70', pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/FB_AD14/FTM0_FLT1/SPI0_PCS0, label: 'MB_J11[B25]/MB_U9[2]/MB_TP_35/MB_MCU_BRAKE/J4[B25]/MCU_BRAKE',
103 identifier: MCU_BRAKE}
104- {pin_num: '71', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/LPUART0_RTS_b, label: 'MB_J11[A14]/MB_U12[18]/MB_PWM_AT/J4[A14]/PWM0',
105 identifier: PWM_AT}
106- {pin_num: '72', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/LPUART0_CTS_b, label: 'MB_J11[A15]/MB_U12[12]/MB_PWM_AB/J4[A15]/PWM1',
107 identifier: PWM_AB}
108- {pin_num: '73', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/LPUART0_RX, label: 'MB_J11[A6]/MB_TP16/MB_TACHO/J4[A6]/TACHO', identifier: TACHO}
109- {pin_num: '76', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX, label: 'MB_J11[A17]/MB_U12[13]/MB_PWM_BB/J4[A17]/PWM3', identifier: PWM_BB}
110- {pin_num: '77', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/FB_AD10/CMP0_OUT/FTM0_CH2, label: 'MB_J11[A16]/MB_U12[19]/MB_PWM_BT/J4[A16]/PWM2', identifier: PWM_BT}
111- {pin_num: '78', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/FB_AD9/I2C0_SCL, label: 'MB_J11[B21]/MB_PFC_zc_2/J4[B21]/MB_TP_27', identifier: PFC_ZC_2}
112- {pin_num: '79', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/FB_AD8/I2C0_SDA, label: 'MB_J11[B22]/MB_PFC_zc_1/J4[B22]/MB_TP_26', identifier: PFC_ZC_1}
113- {pin_num: '80', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/FTM3_CH4/FB_AD7, label: 'MB_J11[A8]/MB_U2B[7]/MB_TP14/MB_Ipfc1/J4[A8]/I_pfc1', identifier: I_PFC1}
114- {pin_num: '81', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/FB_AD6/FTM2_FLT0, label: 'MB_J11[A9]/MB_U2A[1]/MB_TP5/MB_Ipfc2/J4[A9]/I_pfc2', identifier: I_PFC2}
115- {pin_num: '82', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/FB_AD5, label: 'MB_J11[B5]/MB_TP33/''MB_V_sense_DCB/2''/J4[B5]/''U_dcb/2''', identifier: U_DCB_HALF}
116- {pin_num: '83', pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/FB_RW_b, label: 'MB_J11[B9]/MB_U12[2]/MB_TP38/MB_IPM_temp/J4[B9]/Temp_IPM', identifier: TEMP_IPM}
117- {pin_num: '84', pin_signal: PTC12/FB_AD27/FTM3_FLT0, label: 'MB_J11[A26]/MB_U9[2]/MB_TP35/MB_FAULT_2/MB_Over-voltage_FAULT/J4[A26]/FAULT_2', identifier: FAULT_2}
118- {pin_num: '85', pin_signal: PTC13/FB_AD26, label: 'MB_J11[B28]/MB_Q3[1]/MB_Relay/J4[B28]/Relay', identifier: RELAY}
119- {pin_num: '86', pin_signal: PTC14/FB_AD25, label: NC}
120- {pin_num: '87', pin_signal: PTC15/FB_AD24, label: NC}
121- {pin_num: '90', pin_signal: PTC16/LPUART0_RX/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b, label: NC}
122- {pin_num: '91', pin_signal: PTC17/LPUART0_TX/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b, label: NC}
123- {pin_num: '92', pin_signal: PTC18/LPUART0_RTS_b/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b, label: NC}
124- {pin_num: '97', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN/SPI1_PCS0, label: 'MB_J11[A18]/MB_U12[20]/MB_PWM_CT/J4[A18]/PWM4', identifier: PWM_CT}
125- {pin_num: '98', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK, label: 'MB_J11[A19]/MB_U12[14]/MB_PWM_CB/J4[A19]/PWM5', identifier: PWM_CB}
126- {pin_num: '99', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, label: 'MB_J9[5]/MB_J11[B16]/MB_TP19/MB_ENC_Index/J4[B16]/TM2',
127 identifier: ENC_INDEX}
128- {pin_num: '100', pin_signal: PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN, label: NC}
129 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
130 */
131/* clang-format on */
132
133#include "fsl_common.h"
134#include "fsl_port.h"
135#include "fsl_gpio.h"
136#include "pin_mux.h"
137
138/* FUNCTION ************************************************************************************************************
139 *
140 * Function Name : BOARD_InitBootPins
141 * Description : Calls initialization functions.
142 *
143 * END ****************************************************************************************************************/
144void BOARD_InitBootPins(void)
145{
146 BOARD_InitPins();
147 BOARD_InitDEBUG_UARTPins();
148}
149
150/* clang-format off */
151/*
152 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
153MB_InitMC_PWMPins:
154- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
155- pin_list:
156 - {pin_num: '71', peripheral: FTM0, signal: 'CH, 0', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/LPUART0_RTS_b, direction: OUTPUT}
157 - {pin_num: '72', peripheral: FTM0, signal: 'CH, 1', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/LPUART0_CTS_b, direction: OUTPUT}
158 - {pin_num: '76', peripheral: FTM0, signal: 'CH, 3', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX, direction: OUTPUT}
159 - {pin_num: '77', peripheral: FTM0, signal: 'CH, 2', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/FB_AD10/CMP0_OUT/FTM0_CH2, direction: OUTPUT}
160 - {pin_num: '97', peripheral: FTM0, signal: 'CH, 4', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN/SPI1_PCS0, direction: OUTPUT}
161 - {pin_num: '98', peripheral: FTM0, signal: 'CH, 5', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK, direction: OUTPUT}
162 - {pin_num: '51', peripheral: FTM0, signal: 'FLT, 0', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1}
163 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
164 */
165/* clang-format on */
166
167/* FUNCTION ************************************************************************************************************
168 *
169 * Function Name : MB_InitMC_PWMPins
170 * Description : Configures pin routing and optionally pin electrical features.
171 *
172 * END ****************************************************************************************************************/
173void MB_InitMC_PWMPins(void)
174{
175 /* Port A Clock Gate Control: Clock enabled */
176 CLOCK_EnableClock(kCLOCK_PortA);
177 /* Port C Clock Gate Control: Clock enabled */
178 CLOCK_EnableClock(kCLOCK_PortC);
179 /* Port D Clock Gate Control: Clock enabled */
180 CLOCK_EnableClock(kCLOCK_PortD);
181
182 /* PORTA19 (pin 51) is configured as FTM0_FLT0 */
183 PORT_SetPinMux(MB_FAULT_1_PORT, MB_FAULT_1_PIN, kPORT_MuxAlt2);
184
185 /* PORTC1 (pin 71) is configured as FTM0_CH0 */
186 PORT_SetPinMux(MB_PWM_AT_PORT, MB_PWM_AT_PIN, kPORT_MuxAlt4);
187
188 /* PORTC2 (pin 72) is configured as FTM0_CH1 */
189 PORT_SetPinMux(MB_PWM_AB_PORT, MB_PWM_AB_PIN, kPORT_MuxAlt4);
190
191 /* PORTC4 (pin 76) is configured as FTM0_CH3 */
192 PORT_SetPinMux(MB_PWM_BB_PORT, MB_PWM_BB_PIN, kPORT_MuxAlt4);
193
194 /* PORTC5 (pin 77) is configured as FTM0_CH2 */
195 PORT_SetPinMux(MB_PWM_BT_PORT, MB_PWM_BT_PIN, kPORT_MuxAlt7);
196
197 /* PORTD4 (pin 97) is configured as FTM0_CH4 */
198 PORT_SetPinMux(MB_PWM_CT_PORT, MB_PWM_CT_PIN, kPORT_MuxAlt4);
199
200 /* PORTD5 (pin 98) is configured as FTM0_CH5 */
201 PORT_SetPinMux(MB_PWM_CB_PORT, MB_PWM_CB_PIN, kPORT_MuxAlt4);
202
203 SIM->SOPT4 = ((SIM->SOPT4 &
204 /* Mask bits to zero which are setting */
205 (~(SIM_SOPT4_FTM0FLT0_MASK)))
206
207 /* FTM0 Fault 0 Select: FTM0_FLT0 pin. */
208 | SIM_SOPT4_FTM0FLT0(SOPT4_FTM0FLT0_FTM));
209}
210
211/* clang-format off */
212/*
213 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
214MB_InitPFCPins:
215- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
216- pin_list:
217 - {pin_num: '78', peripheral: CMP0, signal: 'IN, 0', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/FB_AD9/I2C0_SCL}
218 - {pin_num: '79', peripheral: CMP0, signal: 'IN, 1', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/FB_AD8/I2C0_SDA}
219 - {pin_num: '85', peripheral: GPIOC, signal: 'GPIO, 13', pin_signal: PTC13/FB_AD26, direction: OUTPUT}
220 - {pin_num: '6', peripheral: FTM3, signal: 'CH, 0', pin_signal: PTE5/SPI1_PCS2/LPUART0_RX/FTM3_CH0, direction: OUTPUT}
221 - {pin_num: '7', peripheral: FTM3, signal: 'CH, 1', pin_signal: PTE6/SPI1_PCS3/LPUART0_CTS_b/FTM3_CH1, direction: OUTPUT}
222 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
223 */
224/* clang-format on */
225
226/* FUNCTION ************************************************************************************************************
227 *
228 * Function Name : MB_InitPFCPins
229 * Description : Configures pin routing and optionally pin electrical features.
230 *
231 * END ****************************************************************************************************************/
232void MB_InitPFCPins(void)
233{
234 /* Port C Clock Gate Control: Clock enabled */
235 CLOCK_EnableClock(kCLOCK_PortC);
236 /* Port E Clock Gate Control: Clock enabled */
237 CLOCK_EnableClock(kCLOCK_PortE);
238
239 gpio_pin_config_t RELAY_config = {
240 .pinDirection = kGPIO_DigitalOutput,
241 .outputLogic = 0U
242 };
243 /* Initialize GPIO functionality on pin PTC13 (pin 85) */
244 GPIO_PinInit(MB_RELAY_GPIO, MB_RELAY_PIN, &RELAY_config);
245
246 /* PORTC13 (pin 85) is configured as PTC13 */
247 PORT_SetPinMux(MB_RELAY_PORT, MB_RELAY_PIN, kPORT_MuxAsGpio);
248
249 /* PORTC6 (pin 78) is configured as CMP0_IN0 */
250 PORT_SetPinMux(MB_PFC_ZC_2_PORT, MB_PFC_ZC_2_PIN, kPORT_PinDisabledOrAnalog);
251
252 /* PORTC7 (pin 79) is configured as CMP0_IN1 */
253 PORT_SetPinMux(MB_PFC_ZC_1_PORT, MB_PFC_ZC_1_PIN, kPORT_PinDisabledOrAnalog);
254
255 /* PORTE5 (pin 6) is configured as FTM3_CH0 */
256 PORT_SetPinMux(MB_PWM_PFC2_PORT, MB_PWM_PFC2_PIN, kPORT_MuxAlt6);
257
258 /* PORTE6 (pin 7) is configured as FTM3_CH1 */
259 PORT_SetPinMux(MB_PWM_PFC1_PORT, MB_PWM_PFC1_PIN, kPORT_MuxAlt6);
260}
261
262/* clang-format off */
263/*
264 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
265MB_InitANA_SENSPins:
266- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
267- pin_list:
268 - {pin_num: '26', peripheral: ADC1, signal: 'SE, 18', pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18}
269 - {pin_num: '55', peripheral: ADC0, signal: 'SE, 12', pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3}
270 - {pin_num: '82', peripheral: ADC1, signal: 'SE, 6b', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/FB_AD5}
271 - {pin_num: '83', peripheral: ADC1, signal: 'SE, 7b', pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/FB_RW_b}
272 - {pin_num: '53', peripheral: ADC0, signal: 'SE, 8', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX}
273 - {pin_num: '54', peripheral: ADC0, signal: 'SE, 9', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX}
274 - {pin_num: '20', peripheral: ADC1, signal: 'SE, 0', pin_signal: ADC1_DP0/ADC0_DP3}
275 - {pin_num: '18', peripheral: ADC1, signal: 'SE, 3', pin_signal: ADC0_DP0/ADC1_DP3}
276 - {pin_num: '27', peripheral: ADC0, signal: 'SE, 23', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23}
277 - {pin_num: '28', peripheral: ADC1, signal: 'SE, 23', pin_signal: DAC1_OUT/CMP0_IN4/ADC1_SE23}
278 - {pin_num: '80', peripheral: ADC1, signal: 'SE, 4b', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/FTM3_CH4/FB_AD7}
279 - {pin_num: '81', peripheral: ADC1, signal: 'SE, 5b', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/FB_AD6/FTM2_FLT0}
280 - {pin_num: '73', peripheral: CMP1, signal: 'IN, 1', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/LPUART0_RX}
281 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
282 */
283/* clang-format on */
284
285/* FUNCTION ************************************************************************************************************
286 *
287 * Function Name : MB_InitANA_SENSPins
288 * Description : Configures pin routing and optionally pin electrical features.
289 *
290 * END ****************************************************************************************************************/
291void MB_InitANA_SENSPins(void)
292{
293 /* Port B Clock Gate Control: Clock enabled */
294 CLOCK_EnableClock(kCLOCK_PortB);
295 /* Port C Clock Gate Control: Clock enabled */
296 CLOCK_EnableClock(kCLOCK_PortC);
297
298 /* PORTB0 (pin 53) is configured as ADC0_SE8 */
299 PORT_SetPinMux(MB_I_PH_A_PORT, MB_I_PH_A_PIN, kPORT_PinDisabledOrAnalog);
300
301 /* PORTB1 (pin 54) is configured as ADC0_SE9 */
302 PORT_SetPinMux(MB_I_PH_C_PORT, MB_I_PH_C_PIN, kPORT_PinDisabledOrAnalog);
303
304 /* PORTB2 (pin 55) is configured as ADC0_SE12 */
305 PORT_SetPinMux(MB_U_DCB_PORT, MB_U_DCB_PIN, kPORT_PinDisabledOrAnalog);
306
307 /* PORTC10 (pin 82) is configured as ADC1_SE6b */
308 PORT_SetPinMux(MB_U_DCB_HALF_PORT, MB_U_DCB_HALF_PIN, kPORT_PinDisabledOrAnalog);
309
310 /* PORTC11 (pin 83) is configured as ADC1_SE7b */
311 PORT_SetPinMux(MB_TEMP_IPM_PORT, MB_TEMP_IPM_PIN, kPORT_PinDisabledOrAnalog);
312
313 /* PORTC3 (pin 73) is configured as CMP1_IN1 */
314 PORT_SetPinMux(MB_TACHO_PORT, MB_TACHO_PIN, kPORT_PinDisabledOrAnalog);
315
316 /* PORTC8 (pin 80) is configured as ADC1_SE4b */
317 PORT_SetPinMux(MB_I_PFC1_PORT, MB_I_PFC1_PIN, kPORT_PinDisabledOrAnalog);
318
319 /* PORTC9 (pin 81) is configured as ADC1_SE5b */
320 PORT_SetPinMux(MB_I_PFC2_PORT, MB_I_PFC2_PIN, kPORT_PinDisabledOrAnalog);
321}
322
323/* clang-format off */
324/*
325 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
326MB_InitBEMFPins:
327- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
328- pin_list:
329 - {pin_num: '19', peripheral: ADC0, signal: 'SE, 19', pin_signal: ADC0_DM0/ADC1_DM3}
330 - {pin_num: '21', peripheral: ADC1, signal: 'SE, 19', pin_signal: ADC1_DM0/ADC0_DM3}
331 - {pin_num: '17', peripheral: ADC1, signal: 'SE, 20', pin_signal: ADC1_DM1/ADC0_DM2}
332 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
333 */
334/* clang-format on */
335
336/* FUNCTION ************************************************************************************************************
337 *
338 * Function Name : MB_InitBEMFPins
339 * Description : Configures pin routing and optionally pin electrical features.
340 *
341 * END ****************************************************************************************************************/
342void MB_InitBEMFPins(void)
343{
344}
345
346/* clang-format off */
347/*
348 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
349MB_InitENCPins:
350- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
351- pin_list:
352 - {pin_num: '42', peripheral: FTM1, signal: 'QD_PH, A', pin_signal: PTA12/FTM1_CH0/FTM1_QD_PHA}
353 - {pin_num: '43', peripheral: FTM1, signal: 'QD_PH, B', pin_signal: PTA13/LLWU_P4/FTM1_CH1/FTM1_QD_PHB}
354 - {pin_num: '99', peripheral: GPIOD, signal: 'GPIO, 6', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, direction: INPUT}
355 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
356 */
357/* clang-format on */
358
359/* FUNCTION ************************************************************************************************************
360 *
361 * Function Name : MB_InitENCPins
362 * Description : Configures pin routing and optionally pin electrical features.
363 *
364 * END ****************************************************************************************************************/
365void MB_InitENCPins(void)
366{
367 /* Port A Clock Gate Control: Clock enabled */
368 CLOCK_EnableClock(kCLOCK_PortA);
369 /* Port D Clock Gate Control: Clock enabled */
370 CLOCK_EnableClock(kCLOCK_PortD);
371
372 gpio_pin_config_t ENC_INDEX_config = {
373 .pinDirection = kGPIO_DigitalInput,
374 .outputLogic = 0U
375 };
376 /* Initialize GPIO functionality on pin PTD6 (pin 99) */
377 GPIO_PinInit(MB_ENC_INDEX_GPIO, MB_ENC_INDEX_PIN, &ENC_INDEX_config);
378
379 /* PORTA12 (pin 42) is configured as FTM1_QD_PHA */
380 PORT_SetPinMux(MB_ENC_PHASE_A_PORT, MB_ENC_PHASE_A_PIN, kPORT_MuxAlt7);
381
382 /* PORTA13 (pin 43) is configured as FTM1_QD_PHB */
383 PORT_SetPinMux(MB_ENC_PHASE_B_PORT, MB_ENC_PHASE_B_PIN, kPORT_MuxAlt7);
384
385 /* PORTD6 (pin 99) is configured as PTD6 */
386 PORT_SetPinMux(MB_ENC_INDEX_PORT, MB_ENC_INDEX_PIN, kPORT_MuxAsGpio);
387}
388
389/* clang-format off */
390/*
391 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
392MB_InitBRAKEPins:
393- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
394- pin_list:
395 - {pin_num: '70', peripheral: GPIOC, signal: 'GPIO, 0', pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/FB_AD14/FTM0_FLT1/SPI0_PCS0, direction: OUTPUT}
396 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
397 */
398/* clang-format on */
399
400/* FUNCTION ************************************************************************************************************
401 *
402 * Function Name : MB_InitBRAKEPins
403 * Description : Configures pin routing and optionally pin electrical features.
404 *
405 * END ****************************************************************************************************************/
406void MB_InitBRAKEPins(void)
407{
408 /* Port C Clock Gate Control: Clock enabled */
409 CLOCK_EnableClock(kCLOCK_PortC);
410
411 gpio_pin_config_t MCU_BRAKE_config = {
412 .pinDirection = kGPIO_DigitalOutput,
413 .outputLogic = 0U
414 };
415 /* Initialize GPIO functionality on pin PTC0 (pin 70) */
416 GPIO_PinInit(MB_MCU_BRAKE_GPIO, MB_MCU_BRAKE_PIN, &MCU_BRAKE_config);
417
418 /* PORTC0 (pin 70) is configured as PTC0 */
419 PORT_SetPinMux(MB_MCU_BRAKE_PORT, MB_MCU_BRAKE_PIN, kPORT_MuxAsGpio);
420}
421
422/* clang-format off */
423/*
424 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
425MB_InitUSB_UARTPins:
426- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
427- pin_list:
428 - {pin_num: '10', peripheral: UART2, signal: TX, pin_signal: ADC0_SE4a/PTE16/SPI0_PCS0/UART2_TX/FTM_CLKIN0/FTM0_FLT3, direction: OUTPUT}
429 - {pin_num: '11', peripheral: UART2, signal: RX, pin_signal: ADC0_SE5a/PTE17/SPI0_SCK/UART2_RX/FTM_CLKIN1/LPTMR0_ALT3}
430 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
431 */
432/* clang-format on */
433
434/* FUNCTION ************************************************************************************************************
435 *
436 * Function Name : MB_InitUSB_UARTPins
437 * Description : Configures pin routing and optionally pin electrical features.
438 *
439 * END ****************************************************************************************************************/
440void MB_InitUSB_UARTPins(void)
441{
442 /* Port E Clock Gate Control: Clock enabled */
443 CLOCK_EnableClock(kCLOCK_PortE);
444
445 /* PORTE16 (pin 10) is configured as UART2_TX */
446 PORT_SetPinMux(MB_TXD_PORT, MB_TXD_PIN, kPORT_MuxAlt3);
447
448 /* PORTE17 (pin 11) is configured as UART2_RX */
449 PORT_SetPinMux(MB_RXD_PORT, MB_RXD_PIN, kPORT_MuxAlt3);
450}
451
452/* clang-format off */
453/*
454 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
455MB_InitEXT_UARTPins:
456- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
457- pin_list:
458 - {pin_num: '2', peripheral: UART1, signal: RX, pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN}
459 - {pin_num: '1', peripheral: UART1, signal: TX, pin_signal: ADC1_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/I2C1_SDA, direction: OUTPUT}
460 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
461 */
462/* clang-format on */
463
464/* FUNCTION ************************************************************************************************************
465 *
466 * Function Name : MB_InitEXT_UARTPins
467 * Description : Configures pin routing and optionally pin electrical features.
468 *
469 * END ****************************************************************************************************************/
470void MB_InitEXT_UARTPins(void)
471{
472 /* Port E Clock Gate Control: Clock enabled */
473 CLOCK_EnableClock(kCLOCK_PortE);
474
475 /* PORTE0 (pin 1) is configured as UART1_TX */
476 PORT_SetPinMux(MB_TXD_1_PORT, MB_TXD_1_PIN, kPORT_MuxAlt3);
477
478 /* PORTE1 (pin 2) is configured as UART1_RX */
479 PORT_SetPinMux(MB_RXD_1_PORT, MB_RXD_1_PIN, kPORT_MuxAlt3);
480
481 SIM->SOPT5 = ((SIM->SOPT5 &
482 /* Mask bits to zero which are setting */
483 (~(SIM_SOPT5_UART1TXSRC_MASK)))
484
485 /* UART 1 transmit data source select: UART1_TX pin. */
486 | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX));
487}
488
489/* clang-format off */
490/*
491 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
492MB_InitMISCPins:
493- options: {prefix: MB_, coreID: core0, enableClock: 'true'}
494- pin_list:
495 - {pin_num: '84', peripheral: GPIOC, signal: 'GPIO, 12', pin_signal: PTC12/FB_AD27/FTM3_FLT0, direction: INPUT}
496 - {peripheral: ADC0, signal: 'TRG, A', pin_signal: PDB0_CH0_TriggerA}
497 - {peripheral: ADC0, signal: 'TRG, B', pin_signal: PDB0_CH0_TriggerB}
498 - {peripheral: ADC1, signal: 'TRG, A', pin_signal: PDB0_CH1_TriggerA}
499 - {peripheral: ADC1, signal: 'TRG, B', pin_signal: PDB0_CH1_TriggerB}
500 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
501 */
502/* clang-format on */
503
504/* FUNCTION ************************************************************************************************************
505 *
506 * Function Name : MB_InitMISCPins
507 * Description : Configures pin routing and optionally pin electrical features.
508 *
509 * END ****************************************************************************************************************/
510void MB_InitMISCPins(void)
511{
512 /* Port C Clock Gate Control: Clock enabled */
513 CLOCK_EnableClock(kCLOCK_PortC);
514
515 gpio_pin_config_t FAULT_2_config = {
516 .pinDirection = kGPIO_DigitalInput,
517 .outputLogic = 0U
518 };
519 /* Initialize GPIO functionality on pin PTC12 (pin 84) */
520 GPIO_PinInit(MB_FAULT_2_GPIO, MB_FAULT_2_PIN, &FAULT_2_config);
521
522 /* PORTC12 (pin 84) is configured as PTC12 */
523 PORT_SetPinMux(MB_FAULT_2_PORT, MB_FAULT_2_PIN, kPORT_MuxAsGpio);
524
525 SIM->SOPT7 = ((SIM->SOPT7 &
526 /* Mask bits to zero which are setting */
527 (~(SIM_SOPT7_ADC0ALTTRGEN_MASK | SIM_SOPT7_ADC1ALTTRGEN_MASK)))
528
529 /* ADC0 alternate trigger enable: PDB trigger selected for ADC0. */
530 | SIM_SOPT7_ADC0ALTTRGEN(SOPT7_ADC0ALTTRGEN_PDB)
531
532 /* ADC1 alternate trigger enable: PDB trigger selected for ADC1. */
533 | SIM_SOPT7_ADC1ALTTRGEN(SOPT7_ADC1ALTTRGEN_PDB));
534}
535
536/* clang-format off */
537/*
538 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
539BOARD_InitPins:
540- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
541- pin_list:
542 - {pin_num: '36', peripheral: TPIU, signal: SWO, pin_signal: PTA2/UART0_TX/FTM0_CH7/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/JTAG_TDO/TRACE_SWO/EZP_DO, pull_select: down,
543 pull_enable: disable}
544 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
545 */
546/* clang-format on */
547
548/* FUNCTION ************************************************************************************************************
549 *
550 * Function Name : BOARD_InitPins
551 * Description : Configures pin routing and optionally pin electrical features.
552 *
553 * END ****************************************************************************************************************/
554void BOARD_InitPins(void)
555{
556 /* Port A Clock Gate Control: Clock enabled */
557 CLOCK_EnableClock(kCLOCK_PortA);
558
559 /* PORTA2 (pin 36) is configured as TRACE_SWO */
560 PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt7);
561
562 PORTA->PCR[2] = ((PORTA->PCR[2] &
563 /* Mask bits to zero which are setting */
564 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
565
566 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
567 * corresponding PE field is set. */
568 | PORT_PCR_PS(kPORT_PullDown)
569
570 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
571 | PORT_PCR_PE(kPORT_PullDisable));
572}
573
574/* clang-format off */
575/*
576 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
577BOARD_InitDEBUG_UARTPins:
578- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
579- pin_list:
580 - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN}
581 - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, direction: OUTPUT}
582 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
583 */
584/* clang-format on */
585
586/* FUNCTION ************************************************************************************************************
587 *
588 * Function Name : BOARD_InitDEBUG_UARTPins
589 * Description : Configures pin routing and optionally pin electrical features.
590 *
591 * END ****************************************************************************************************************/
592void BOARD_InitDEBUG_UARTPins(void)
593{
594 /* Port B Clock Gate Control: Clock enabled */
595 CLOCK_EnableClock(kCLOCK_PortB);
596
597 /* PORTB16 (pin 62) is configured as UART0_RX */
598 PORT_SetPinMux(BOARD_UART_TX_TGTMCU_PORT, BOARD_UART_TX_TGTMCU_PIN, kPORT_MuxAlt3);
599
600 /* PORTB17 (pin 63) is configured as UART0_TX */
601 PORT_SetPinMux(BOARD_UART_RX_TGTMCU_PORT, BOARD_UART_RX_TGTMCU_PIN, kPORT_MuxAlt3);
602
603 SIM->SOPT5 = ((SIM->SOPT5 &
604 /* Mask bits to zero which are setting */
605 (~(SIM_SOPT5_UART0TXSRC_MASK)))
606
607 /* UART 0 transmit data source select: UART0_TX pin. */
608 | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
609}
610
611/* clang-format off */
612/*
613 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
614BOARD_InitLEDSPins:
615- options: {callFromInitBoot: 'false', prefix: BOARD_, coreID: core0, enableClock: 'true'}
616- pin_list:
617 - {pin_num: '65', peripheral: GPIOB, signal: 'GPIO, 19', pin_signal: PTB19/FTM2_CH1/FB_OE_b/FTM2_QD_PHB, direction: OUTPUT}
618 - {pin_num: '39', peripheral: GPIOA, signal: 'GPIO, 5', pin_signal: PTA5/FTM0_CH2/JTAG_TRST_b, direction: OUTPUT}
619 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
620 */
621/* clang-format on */
622
623/* FUNCTION ************************************************************************************************************
624 *
625 * Function Name : BOARD_InitLEDSPins
626 * Description : Configures pin routing and optionally pin electrical features.
627 *
628 * END ****************************************************************************************************************/
629void BOARD_InitLEDSPins(void)
630{
631 /* Port A Clock Gate Control: Clock enabled */
632 CLOCK_EnableClock(kCLOCK_PortA);
633 /* Port B Clock Gate Control: Clock enabled */
634 CLOCK_EnableClock(kCLOCK_PortB);
635
636 gpio_pin_config_t LED_RED_config = {
637 .pinDirection = kGPIO_DigitalOutput,
638 .outputLogic = 0U
639 };
640 /* Initialize GPIO functionality on pin PTA5 (pin 39) */
641 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
642
643 gpio_pin_config_t LED_GREEN_config = {
644 .pinDirection = kGPIO_DigitalOutput,
645 .outputLogic = 0U
646 };
647 /* Initialize GPIO functionality on pin PTB19 (pin 65) */
648 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
649
650 /* PORTA5 (pin 39) is configured as PTA5 */
651 PORT_SetPinMux(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, kPORT_MuxAsGpio);
652
653 /* PORTB19 (pin 65) is configured as PTB19 */
654 PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio);
655}
656/***********************************************************************************************************************
657 * EOF
658 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.h
new file mode 100644
index 000000000..d4ce32ab2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/pin_mux.h
@@ -0,0 +1,358 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _PIN_MUX_H_
9#define _PIN_MUX_H_
10
11/*!
12 * @addtogroup pin_mux
13 * @{
14 */
15
16/***********************************************************************************************************************
17 * API
18 **********************************************************************************************************************/
19
20#if defined(__cplusplus)
21extern "C" {
22#endif
23
24/*!
25 * @brief Calls initialization functions.
26 *
27 */
28void BOARD_InitBootPins(void);
29
30#define SOPT4_FTM0FLT0_FTM 0x00u /*!<@brief FTM0 Fault 0 Select: FTM0_FLT0 pin */
31
32/*! @name PORTC1 (number 71), MB_J11[A14]/MB_U12[18]/MB_PWM_AT/J4[A14]/PWM0
33 @{ */
34#define MB_PWM_AT_PORT PORTC /*!<@brief PORT device name: PORTC */
35#define MB_PWM_AT_PIN 1U /*!<@brief PORTC pin index: 1 */
36 /* @} */
37
38/*! @name PORTC2 (number 72), MB_J11[A15]/MB_U12[12]/MB_PWM_AB/J4[A15]/PWM1
39 @{ */
40#define MB_PWM_AB_PORT PORTC /*!<@brief PORT device name: PORTC */
41#define MB_PWM_AB_PIN 2U /*!<@brief PORTC pin index: 2 */
42 /* @} */
43
44/*! @name PORTC4 (number 76), MB_J11[A17]/MB_U12[13]/MB_PWM_BB/J4[A17]/PWM3
45 @{ */
46#define MB_PWM_BB_PORT PORTC /*!<@brief PORT device name: PORTC */
47#define MB_PWM_BB_PIN 4U /*!<@brief PORTC pin index: 4 */
48 /* @} */
49
50/*! @name PORTC5 (number 77), MB_J11[A16]/MB_U12[19]/MB_PWM_BT/J4[A16]/PWM2
51 @{ */
52#define MB_PWM_BT_PORT PORTC /*!<@brief PORT device name: PORTC */
53#define MB_PWM_BT_PIN 5U /*!<@brief PORTC pin index: 5 */
54 /* @} */
55
56/*! @name PORTD4 (number 97), MB_J11[A18]/MB_U12[20]/MB_PWM_CT/J4[A18]/PWM4
57 @{ */
58#define MB_PWM_CT_PORT PORTD /*!<@brief PORT device name: PORTD */
59#define MB_PWM_CT_PIN 4U /*!<@brief PORTD pin index: 4 */
60 /* @} */
61
62/*! @name PORTD5 (number 98), MB_J11[A19]/MB_U12[14]/MB_PWM_CB/J4[A19]/PWM5
63 @{ */
64#define MB_PWM_CB_PORT PORTD /*!<@brief PORT device name: PORTD */
65#define MB_PWM_CB_PIN 5U /*!<@brief PORTD pin index: 5 */
66 /* @} */
67
68/*! @name PORTA19 (number 51), MB_J11[A25]/MB_U12[11]/MB_TP28/MB_FAULT/MB_FAULT_1/MB_PFC_overcurrent/J4[A25]/FAULT_1
69 @{ */
70#define MB_FAULT_1_PORT PORTA /*!<@brief PORT device name: PORTA */
71#define MB_FAULT_1_PIN 19U /*!<@brief PORTA pin index: 19 */
72 /* @} */
73
74/*!
75 * @brief Configures pin routing and optionally pin electrical features.
76 *
77 */
78void MB_InitMC_PWMPins(void);
79
80/*! @name PORTC6 (number 78), MB_J11[B21]/MB_PFC_zc_2/J4[B21]/MB_TP_27
81 @{ */
82#define MB_PFC_ZC_2_PORT PORTC /*!<@brief PORT device name: PORTC */
83#define MB_PFC_ZC_2_PIN 6U /*!<@brief PORTC pin index: 6 */
84 /* @} */
85
86/*! @name PORTC7 (number 79), MB_J11[B22]/MB_PFC_zc_1/J4[B22]/MB_TP_26
87 @{ */
88#define MB_PFC_ZC_1_PORT PORTC /*!<@brief PORT device name: PORTC */
89#define MB_PFC_ZC_1_PIN 7U /*!<@brief PORTC pin index: 7 */
90 /* @} */
91
92/*! @name PORTC13 (number 85), MB_J11[B28]/MB_Q3[1]/MB_Relay/J4[B28]/Relay
93 @{ */
94#define MB_RELAY_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
95#define MB_RELAY_PORT PORTC /*!<@brief PORT device name: PORTC */
96#define MB_RELAY_PIN 13U /*!<@brief PORTC pin index: 13 */
97 /* @} */
98
99/*! @name PORTE5 (number 6), MB_J11[A22]/MB_U14[4]/MB_TP15/MB_PWM_PFC2/J4[A22]/PWM8
100 @{ */
101#define MB_PWM_PFC2_PORT PORTE /*!<@brief PORT device name: PORTE */
102#define MB_PWM_PFC2_PIN 5U /*!<@brief PORTE pin index: 5 */
103 /* @} */
104
105/*! @name PORTE6 (number 7), MB_J11[A23]/MB_U14[2]/MB_TP12/MB_PWM_PFC1/J4[A23]/PWM9
106 @{ */
107#define MB_PWM_PFC1_PORT PORTE /*!<@brief PORT device name: PORTE */
108#define MB_PWM_PFC1_PIN 6U /*!<@brief PORTE pin index: 6 */
109 /* @} */
110
111/*!
112 * @brief Configures pin routing and optionally pin electrical features.
113 *
114 */
115void MB_InitPFCPins(void);
116
117/*! @name ADC1_SE18 (number 26), MB_J11[B3]/MB_U8B[7]/MB_TP34/MB_I_sense_DCB/J4[B3]/I_dcb
118 @{ */
119/* @} */
120
121/*! @name PORTB2 (number 55), MB_J11[B4]/MB_TP31/MB_V_sense_DCB/MB_DCB_Pos/J4[B4]/U_dcb
122 @{ */
123#define MB_U_DCB_PORT PORTB /*!<@brief PORT device name: PORTB */
124#define MB_U_DCB_PIN 2U /*!<@brief PORTB pin index: 2 */
125 /* @} */
126
127/*! @name PORTC10 (number 82), MB_J11[B5]/MB_TP33/'MB_V_sense_DCB/2'/J4[B5]/'U_dcb/2'
128 @{ */
129#define MB_U_DCB_HALF_PORT PORTC /*!<@brief PORT device name: PORTC */
130#define MB_U_DCB_HALF_PIN 10U /*!<@brief PORTC pin index: 10 */
131 /* @} */
132
133/*! @name PORTC11 (number 83), MB_J11[B9]/MB_U12[2]/MB_TP38/MB_IPM_temp/J4[B9]/Temp_IPM
134 @{ */
135#define MB_TEMP_IPM_PORT PORTC /*!<@brief PORT device name: PORTC */
136#define MB_TEMP_IPM_PIN 11U /*!<@brief PORTC pin index: 11 */
137 /* @} */
138
139/*! @name PORTB0 (number 53), MB_J11[A3]/MB_U11A[1]/MB_TP45/MB_I_sense_A/J4[A3]/I_phA
140 @{ */
141#define MB_I_PH_A_PORT PORTB /*!<@brief PORT device name: PORTB */
142#define MB_I_PH_A_PIN 0U /*!<@brief PORTB pin index: 0 */
143 /* @} */
144
145/*! @name PORTB1 (number 54), MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC
146 @{ */
147#define MB_I_PH_C_PORT PORTB /*!<@brief PORT device name: PORTB */
148#define MB_I_PH_C_PIN 1U /*!<@brief PORTB pin index: 1 */
149 /* @} */
150
151/*! @name ADC1_DP0 (number 20), MB_J11[A4]/MB_U11B[7]/MB_TP40/MB_I_sense_B/J4[A4]/I_phB
152 @{ */
153/* @} */
154
155/*! @name ADC1_DP3 (number 18), MB_J11[A5]/MB_U8A[1]/MB_TP37/MB_I_sense_C/J4[A5]/I_phC
156 @{ */
157/* @} */
158
159/*! @name ADC0_SE23 (number 27), MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in
160 @{ */
161/* @} */
162
163/*! @name ADC1_SE23 (number 28), MB_J11[A7]/MB_TP18/MB_Vin/J4[A7]/V_in
164 @{ */
165/* @} */
166
167/*! @name PORTC8 (number 80), MB_J11[A8]/MB_U2B[7]/MB_TP14/MB_Ipfc1/J4[A8]/I_pfc1
168 @{ */
169#define MB_I_PFC1_PORT PORTC /*!<@brief PORT device name: PORTC */
170#define MB_I_PFC1_PIN 8U /*!<@brief PORTC pin index: 8 */
171 /* @} */
172
173/*! @name PORTC9 (number 81), MB_J11[A9]/MB_U2A[1]/MB_TP5/MB_Ipfc2/J4[A9]/I_pfc2
174 @{ */
175#define MB_I_PFC2_PORT PORTC /*!<@brief PORT device name: PORTC */
176#define MB_I_PFC2_PIN 9U /*!<@brief PORTC pin index: 9 */
177 /* @} */
178
179/*! @name PORTC3 (number 73), MB_J11[A6]/MB_TP16/MB_TACHO/J4[A6]/TACHO
180 @{ */
181#define MB_TACHO_PORT PORTC /*!<@brief PORT device name: PORTC */
182#define MB_TACHO_PIN 3U /*!<@brief PORTC pin index: 3 */
183 /* @} */
184
185/*!
186 * @brief Configures pin routing and optionally pin electrical features.
187 *
188 */
189void MB_InitANA_SENSPins(void);
190
191/*! @name ADC0_DM0 (number 19), MB_J11[B6]/MB_TP44/MB_BEMF_sense_A/MB_Phase_A/J4[B6]/BEMF_A
192 @{ */
193/* @} */
194
195/*! @name ADC1_DM0 (number 21), MB_J11[B7]/MB_TP43/MB_BEMF_sense_B/MB_Phase_B/J4[B7]/BEMF_B
196 @{ */
197/* @} */
198
199/*! @name ADC1_DM1 (number 17), MB_J11[B8]/MB_TP41/MB_BEMF_sense_C/MB_Phase_C/J4[B8]/BEMF_C
200 @{ */
201/* @} */
202
203/*!
204 * @brief Configures pin routing and optionally pin electrical features.
205 *
206 */
207void MB_InitBEMFPins(void);
208
209/*! @name PORTA12 (number 42), MB_J9[3]/MB_J11[B14]/MB_TP13/MB_ENC_PhaseA/J4[B14]/TM0
210 @{ */
211#define MB_ENC_PHASE_A_PORT PORTA /*!<@brief PORT device name: PORTA */
212#define MB_ENC_PHASE_A_PIN 12U /*!<@brief PORTA pin index: 12 */
213 /* @} */
214
215/*! @name PORTA13 (number 43), MB_J9[4]/MB_J11[B15]/MB_TP17/MB_ENC_PhaseB/J4[B15]/TM1
216 @{ */
217#define MB_ENC_PHASE_B_PORT PORTA /*!<@brief PORT device name: PORTA */
218#define MB_ENC_PHASE_B_PIN 13U /*!<@brief PORTA pin index: 13 */
219 /* @} */
220
221/*! @name PORTD6 (number 99), MB_J9[5]/MB_J11[B16]/MB_TP19/MB_ENC_Index/J4[B16]/TM2
222 @{ */
223#define MB_ENC_INDEX_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */
224#define MB_ENC_INDEX_PORT PORTD /*!<@brief PORT device name: PORTD */
225#define MB_ENC_INDEX_PIN 6U /*!<@brief PORTD pin index: 6 */
226 /* @} */
227
228/*!
229 * @brief Configures pin routing and optionally pin electrical features.
230 *
231 */
232void MB_InitENCPins(void);
233
234/*! @name PORTC0 (number 70), MB_J11[B25]/MB_U9[2]/MB_TP_35/MB_MCU_BRAKE/J4[B25]/MCU_BRAKE
235 @{ */
236#define MB_MCU_BRAKE_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
237#define MB_MCU_BRAKE_PORT PORTC /*!<@brief PORT device name: PORTC */
238#define MB_MCU_BRAKE_PIN 0U /*!<@brief PORTC pin index: 0 */
239 /* @} */
240
241/*!
242 * @brief Configures pin routing and optionally pin electrical features.
243 *
244 */
245void MB_InitBRAKEPins(void);
246
247/*! @name PORTE16 (number 10), MB_J1[3]/MB_J11[B26]/MB_U1[13]/MB_U3[25]/MB_TP3/MB_TP7/MB_TxD/J4[B26]/TxD
248 @{ */
249#define MB_TXD_PORT PORTE /*!<@brief PORT device name: PORTE */
250#define MB_TXD_PIN 16U /*!<@brief PORTE pin index: 16 */
251 /* @} */
252
253/*! @name PORTE17 (number 11), MB_J3[2]/MB_J11[B27]/MB_U1[12]/MB_U3[26]/MB_TP2/MB_TP10/MB_RxD/J4[B27]/RxD/MISO/TP19
254 @{ */
255#define MB_RXD_PORT PORTE /*!<@brief PORT device name: PORTE */
256#define MB_RXD_PIN 17U /*!<@brief PORTE pin index: 17 */
257 /* @} */
258
259/*!
260 * @brief Configures pin routing and optionally pin electrical features.
261 *
262 */
263void MB_InitUSB_UARTPins(void);
264
265#define SOPT5_UART1TXSRC_UART_TX 0x00u /*!<@brief UART 1 transmit data source select: UART1_TX pin */
266
267/*! @name PORTE1 (number 2), MB_J2[4]/MB_J3[4]/MB_J11[A32]/MB_RxD_1/MB_RxD_EXT/J4[A32]/RxD1
268 @{ */
269#define MB_RXD_1_PORT PORTE /*!<@brief PORT device name: PORTE */
270#define MB_RXD_1_PIN 1U /*!<@brief PORTE pin index: 1 */
271 /* @} */
272
273/*! @name PORTE0 (number 1), MB_J1[1]/MB_J2[3]/MB_J11[A31]/MB_TxD_1/MB_TxD_EXT/J4[A31]/TxD1
274 @{ */
275#define MB_TXD_1_PORT PORTE /*!<@brief PORT device name: PORTE */
276#define MB_TXD_1_PIN 0U /*!<@brief PORTE pin index: 0 */
277 /* @} */
278
279/*!
280 * @brief Configures pin routing and optionally pin electrical features.
281 *
282 */
283void MB_InitEXT_UARTPins(void);
284
285#define SOPT7_ADC0ALTTRGEN_PDB 0x00u /*!<@brief ADC0 alternate trigger enable: PDB trigger selected for ADC0. */
286#define SOPT7_ADC1ALTTRGEN_PDB 0x00u /*!<@brief ADC1 alternate trigger enable: PDB trigger selected for ADC1 */
287
288/*! @name PORTC12 (number 84), MB_J11[A26]/MB_U9[2]/MB_TP35/MB_FAULT_2/MB_Over-voltage_FAULT/J4[A26]/FAULT_2
289 @{ */
290#define MB_FAULT_2_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
291#define MB_FAULT_2_PORT PORTC /*!<@brief PORT device name: PORTC */
292#define MB_FAULT_2_PIN 12U /*!<@brief PORTC pin index: 12 */
293 /* @} */
294
295/*!
296 * @brief Configures pin routing and optionally pin electrical features.
297 *
298 */
299void MB_InitMISCPins(void);
300
301/*!
302 * @brief Configures pin routing and optionally pin electrical features.
303 *
304 */
305void BOARD_InitPins(void);
306
307#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!<@brief UART 0 transmit data source select: UART0_TX pin */
308
309/*! @name PORTB16 (number 62), U2[24]/U6[13]/TxD_sda/UART_TX_TGTMCU
310 @{ */
311#define BOARD_UART_TX_TGTMCU_PORT PORTB /*!<@brief PORT device name: PORTB */
312#define BOARD_UART_TX_TGTMCU_PIN 16U /*!<@brief PORTB pin index: 16 */
313 /* @} */
314
315/*! @name PORTB17 (number 63), U2[25]/U6[14]/RxD_sda/UART_RX_TGTMCU
316 @{ */
317#define BOARD_UART_RX_TGTMCU_PORT PORTB /*!<@brief PORT device name: PORTB */
318#define BOARD_UART_RX_TGTMCU_PIN 17U /*!<@brief PORTB pin index: 17 */
319 /* @} */
320
321/*!
322 * @brief Configures pin routing and optionally pin electrical features.
323 *
324 */
325void BOARD_InitDEBUG_UARTPins(void);
326
327/*! @name PORTB19 (number 65), MB_J11[B20]/MB_U9[4]/MB_USER_LED/J4[B20]/USER_LED
328 @{ */
329#define BOARD_LED_GREEN_GPIO GPIOB /*!<@brief GPIO device name: GPIOB */
330#define BOARD_LED_GREEN_PORT PORTB /*!<@brief PORT device name: PORTB */
331#define BOARD_LED_GREEN_PIN 19U /*!<@brief PORTB pin index: 19 */
332 /* @} */
333
334/*! @name PORTA5 (number 39), USER_LED_2
335 @{ */
336#define BOARD_LED_RED_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
337#define BOARD_LED_RED_PORT PORTA /*!<@brief PORT device name: PORTA */
338#define BOARD_LED_RED_PIN 5U /*!<@brief PORTA pin index: 5 */
339 /* @} */
340
341/*!
342 * @brief Configures pin routing and optionally pin electrical features.
343 *
344 */
345void BOARD_InitLEDSPins(void);
346
347#if defined(__cplusplus)
348}
349#endif
350
351/*!
352 * @}
353 */
354#endif /* _PIN_MUX_H_ */
355
356/***********************************************************************************************************************
357 * EOF
358 **********************************************************************************************************************/
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