1 files changed, 372 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c
new file mode 100644
index 000000000..7934a5f0d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright 2018 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v4.1
+processor: MKV31F512xxx12
+package_id: MKV31F512VLL12
+mcu_data: ksdk2_0
+processor_version: 4.0.0
+board: HVP-KV31F120M
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+#include "fsl_smc.h"
+#include "clock_config.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE 0U                 /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P 0U                       /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U              /*!< Disable external reference clock */
+#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U     /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U     /*!< PLLFLL select: MCGFLLCLK clock */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description   : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+    uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 31.45728 MHz}
+- {id: Core_clock.outFreq, value: 62.91456 MHz}
+- {id: Flash_clock.outFreq, value: 15.72864 MHz}
+- {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
+- {id: System_clock.outFreq, value: 62.91456 MHz}
+settings:
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '1920', locked: true}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '4'}
+- {id: SIM.OUTDIV4.scale, value: '4'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+    .mcgMode         = kMCG_ModeFEI,      /* FEI - FLL Engaged Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsMidHigh,   /* Mid-High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x1330000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#else
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
+#endif
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 41.94304 MHz}
+- {id: Core_clock.outFreq, value: 83.88608 MHz}
+- {id: Flash_clock.outFreq, value: 20.97152 MHz}
+- {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
+- {id: System_clock.outFreq, value: 83.88608 MHz}
+settings:
+- {id: powerMode, value: HSRUN}
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.FLL_mul.scale, value: '2560'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV3.scale, value: '3'}
+- {id: SIM.OUTDIV4.scale, value: '4'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
+    .mcgMode         = kMCG_ModeFEI,      /* FEI - FLL Engaged Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsHigh,      /* High frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x1230000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
+};
+const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockHSRUN(void)
+{
+    /* Set HSRUN power mode */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
+    {
+    }
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
+                                  mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
+    /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32, mcgConfig_BOARD_BootClockHSRUN.drs,
+                        CLOCK_CONFIG_FllStableDelay);
+#else
+    CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs, CLOCK_CONFIG_FllStableDelay);
+#endif
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 2 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: LPUARTCLK.outFreq, value: 4 MHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: LPUARTClkConfig, value: 'yes'}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+    .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
+    .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
+    .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
+    .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
+    .drs             = kMCG_DrsLow,       /* Low frequency range */
+    .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+    .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
+    .pll0Config =
+        {
+            .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+            .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
+            .vdiv       = 0x0U,            /* VCO divider: multiplied by 24 */
+        },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+    .er32kSrc  = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+    .clkdiv1   = 0x140000U,                   /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+    .freq        = 0U,           /* Oscillator frequency: 0Hz */
+    .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
+    .workMode    = kOSC_ModeExt, /* Use external clock */
+    .oscerConfig = {
+        .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+        .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
+    }};
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+    /* Set LPUART clock source. */
+    CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
+}

diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c new file mode 100644 index 000000000..7934a5f0d --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/boards/hvpkv31f120m/project_template/clock_config.c
@@ -0,0 +1,372 @@
	1	/*
	2	* Copyright 2018 NXP.
	3	* All rights reserved.
	4	*
	5	* SPDX-License-Identifier: BSD-3-Clause
	6	*/
	7
	8	/***********************************************************************************************************************
	9	* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
	10	* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
	11	**********************************************************************************************************************/
	12	/*
	13	* How to setup clock using clock driver functions:
	14	*
	15	* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
	16	* and flash clock are in allowed range during clock mode switch.
	17	*
	18	* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
	19	*
	20	* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
	21	* internal reference clock(MCGIRCLK). Follow the steps to setup:
	22	*
	23	* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
	24	*
	25	* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
	26	* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
	27	* explicitly to setup MCGIRCLK.
	28	*
	29	* 3). Don't need to configure FLL explicitly, because if target mode is FLL
	30	* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
	31	* if the target mode is not FLL mode, the FLL is disabled.
	32	*
	33	* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
	34	* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
	35	* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
	36	*
	37	* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
	38	*/
	39
	40	/* clang-format off */
	41	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	42	!!GlobalInfo
	43	product: Clocks v4.1
	44	processor: MKV31F512xxx12
	45	package_id: MKV31F512VLL12
	46	mcu_data: ksdk2_0
	47	processor_version: 4.0.0
	48	board: HVP-KV31F120M
	49	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	50	/* clang-format on */
	51
	52	#include "fsl_smc.h"
	53	#include "clock_config.h"
	54
	55	/*******************************************************************************
	56	* Definitions
	57	******************************************************************************/
	58	#define MCG_PLL_DISABLE 0U /!< MCGPLLCLK disabled /
	59	#define OSC_CAP0P 0U /!< Oscillator 0pF capacitor load /
	60	#define OSC_ER_CLK_DISABLE 0U /!< Disable external reference clock /
	61	#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /!< LPUART clock select: MCGIRCLK clock /
	62	#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /!< OSC32KSEL select: OSC32KCLK clock /
	63	#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /!< PLLFLL select: MCGFLLCLK clock /
	64
	65	/*******************************************************************************
	66	* Variables
	67	******************************************************************************/
	68	/* System clock frequency. */
	69	extern uint32_t SystemCoreClock;
	70
	71	/*******************************************************************************
	72	* Code
	73	******************************************************************************/
	74	/FUNCTION*********************************************************************
	75	*
	76	* Function Name : CLOCK_CONFIG_FllStableDelay
	77	* Description : This function is used to delay for FLL stable.
	78	*
	79	END*************************************************************************/
	80	static void CLOCK_CONFIG_FllStableDelay(void)
	81	{
	82	uint32_t i = 30000U;
	83	while (i--)
	84	{
	85	__NOP();
	86	}
	87	}
	88
	89	/*******************************************************************************
	90	********************** BOARD_InitBootClocks function **********************
	91	******************************************************************************/
	92	void BOARD_InitBootClocks(void)
	93	{
	94	BOARD_BootClockRUN();
	95	}
	96
	97	/*******************************************************************************
	98	******************** Configuration BOARD_BootClockRUN *********************
	99	******************************************************************************/
	100	/* clang-format off */
	101	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	102	!!Configuration
	103	name: BOARD_BootClockRUN
	104	called_from_default_init: true
	105	outputs:
	106	- {id: Bus_clock.outFreq, value: 31.45728 MHz}
	107	- {id: Core_clock.outFreq, value: 62.91456 MHz}
	108	- {id: Flash_clock.outFreq, value: 15.72864 MHz}
	109	- {id: FlexBus_clock.outFreq, value: 15.72864 MHz}
	110	- {id: LPO_clock.outFreq, value: 1 kHz}
	111	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	112	- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
	113	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	114	- {id: PLLFLLCLK.outFreq, value: 62.91456 MHz}
	115	- {id: System_clock.outFreq, value: 62.91456 MHz}
	116	settings:
	117	- {id: LPUARTClkConfig, value: 'yes'}
	118	- {id: MCG.FCRDIV.scale, value: '1'}
	119	- {id: MCG.FLL_mul.scale, value: '1920', locked: true}
	120	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	121	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	122	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	123	- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
	124	- {id: SIM.OUTDIV2.scale, value: '2'}
	125	- {id: SIM.OUTDIV3.scale, value: '4'}
	126	- {id: SIM.OUTDIV4.scale, value: '4'}
	127	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	128	/* clang-format on */
	129
	130	/*******************************************************************************
	131	* Variables for BOARD_BootClockRUN configuration
	132	******************************************************************************/
	133	const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
	134	.mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
	135	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	136	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	137	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	138	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	139	.drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
	140	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	141	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	142	.pll0Config =
	143	{
	144	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	145	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	146	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	147	},
	148	};
	149	const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
	150	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	151	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	152	.clkdiv1 = 0x1330000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /4 */
	153	};
	154	const osc_config_t oscConfig_BOARD_BootClockRUN = {
	155	.freq = 0U, /* Oscillator frequency: 0Hz */
	156	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	157	.workMode = kOSC_ModeExt, /* Use external clock */
	158	.oscerConfig = {
	159	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	160	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	161	}};
	162
	163	/*******************************************************************************
	164	* Code for BOARD_BootClockRUN configuration
	165	******************************************************************************/
	166	void BOARD_BootClockRUN(void)
	167	{
	168	/* Set the system clock dividers in SIM to safe value. */
	169	CLOCK_SetSimSafeDivs();
	170	/* Configure the Internal Reference clock (MCGIRCLK). */
	171	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
	172	mcgConfig_BOARD_BootClockRUN.fcrdiv);
	173	/* Set MCG to FEI mode. */
	174	#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
	175	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
	176	CLOCK_CONFIG_FllStableDelay);
	177	#else
	178	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs, CLOCK_CONFIG_FllStableDelay);
	179	#endif
	180	/* Set the clock configuration in SIM module. */
	181	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
	182	/* Set SystemCoreClock variable. */
	183	SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
	184	/* Set LPUART clock source. */
	185	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	186	}
	187
	188	/*******************************************************************************
	189	******************* Configuration BOARD_BootClockHSRUN ********************
	190	******************************************************************************/
	191	/* clang-format off */
	192	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	193	!!Configuration
	194	name: BOARD_BootClockHSRUN
	195	outputs:
	196	- {id: Bus_clock.outFreq, value: 41.94304 MHz}
	197	- {id: Core_clock.outFreq, value: 83.88608 MHz}
	198	- {id: Flash_clock.outFreq, value: 20.97152 MHz}
	199	- {id: FlexBus_clock.outFreq, value: 83.88608/3 MHz}
	200	- {id: LPO_clock.outFreq, value: 1 kHz}
	201	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	202	- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
	203	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	204	- {id: PLLFLLCLK.outFreq, value: 83.88608 MHz}
	205	- {id: System_clock.outFreq, value: 83.88608 MHz}
	206	settings:
	207	- {id: powerMode, value: HSRUN}
	208	- {id: LPUARTClkConfig, value: 'yes'}
	209	- {id: MCG.FCRDIV.scale, value: '1'}
	210	- {id: MCG.FLL_mul.scale, value: '2560'}
	211	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	212	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	213	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	214	- {id: SIM.OUTDIV2.scale, value: '2'}
	215	- {id: SIM.OUTDIV3.scale, value: '3'}
	216	- {id: SIM.OUTDIV4.scale, value: '4'}
	217	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	218	/* clang-format on */
	219
	220	/*******************************************************************************
	221	* Variables for BOARD_BootClockHSRUN configuration
	222	******************************************************************************/
	223	const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
	224	.mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
	225	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	226	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	227	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	228	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	229	.drs = kMCG_DrsHigh, /* High frequency range */
	230	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	231	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	232	.pll0Config =
	233	{
	234	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	235	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	236	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	237	},
	238	};
	239	const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
	240	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	241	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	242	.clkdiv1 = 0x1230000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /4 */
	243	};
	244	const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
	245	.freq = 0U, /* Oscillator frequency: 0Hz */
	246	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	247	.workMode = kOSC_ModeExt, /* Use external clock */
	248	.oscerConfig = {
	249	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	250	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	251	}};
	252
	253	/*******************************************************************************
	254	* Code for BOARD_BootClockHSRUN configuration
	255	******************************************************************************/
	256	void BOARD_BootClockHSRUN(void)
	257	{
	258	/* Set HSRUN power mode */
	259	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	260	SMC_SetPowerModeHsrun(SMC);
	261	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
	262	{
	263	}
	264	/* Set the system clock dividers in SIM to safe value. */
	265	CLOCK_SetSimSafeDivs();
	266	/* Configure the Internal Reference clock (MCGIRCLK). */
	267	CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
	268	mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
	269	/* Set MCG to FEI mode. */
	270	#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
	271	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.dmx32, mcgConfig_BOARD_BootClockHSRUN.drs,
	272	CLOCK_CONFIG_FllStableDelay);
	273	#else
	274	CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockHSRUN.drs, CLOCK_CONFIG_FllStableDelay);
	275	#endif
	276	/* Set the clock configuration in SIM module. */
	277	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
	278	/* Set SystemCoreClock variable. */
	279	SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
	280	/* Set LPUART clock source. */
	281	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	282	}
	283
	284	/*******************************************************************************
	285	******************* Configuration BOARD_BootClockVLPR *********************
	286	******************************************************************************/
	287	/* clang-format off */
	288	/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
	289	!!Configuration
	290	name: BOARD_BootClockVLPR
	291	outputs:
	292	- {id: Bus_clock.outFreq, value: 4 MHz}
	293	- {id: Core_clock.outFreq, value: 4 MHz}
	294	- {id: Flash_clock.outFreq, value: 800 kHz}
	295	- {id: FlexBus_clock.outFreq, value: 2 MHz}
	296	- {id: LPO_clock.outFreq, value: 1 kHz}
	297	- {id: LPUARTCLK.outFreq, value: 4 MHz}
	298	- {id: MCGIRCLK.outFreq, value: 4 MHz}
	299	- {id: System_clock.outFreq, value: 4 MHz}
	300	settings:
	301	- {id: MCGMode, value: BLPI}
	302	- {id: powerMode, value: VLPR}
	303	- {id: LPUARTClkConfig, value: 'yes'}
	304	- {id: MCG.CLKS.sel, value: MCG.IRCS}
	305	- {id: MCG.FCRDIV.scale, value: '1'}
	306	- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
	307	- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
	308	- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
	309	- {id: SIM.OUTDIV4.scale, value: '5'}
	310	* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
	311	/* clang-format on */
	312
	313	/*******************************************************************************
	314	* Variables for BOARD_BootClockVLPR configuration
	315	******************************************************************************/
	316	const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
	317	.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
	318	.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
	319	.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
	320	.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
	321	.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
	322	.drs = kMCG_DrsLow, /* Low frequency range */
	323	.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
	324	.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
	325	.pll0Config =
	326	{
	327	.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
	328	.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
	329	.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
	330	},
	331	};
	332	const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
	333	.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
	334	.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
	335	.clkdiv1 = 0x140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /2, OUTDIV4: /5 */
	336	};
	337	const osc_config_t oscConfig_BOARD_BootClockVLPR = {
	338	.freq = 0U, /* Oscillator frequency: 0Hz */
	339	.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
	340	.workMode = kOSC_ModeExt, /* Use external clock */
	341	.oscerConfig = {
	342	.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
	343	.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
	344	}};
	345
	346	/*******************************************************************************
	347	* Code for BOARD_BootClockVLPR configuration
	348	******************************************************************************/
	349	void BOARD_BootClockVLPR(void)
	350	{
	351	/* Set the system clock dividers in SIM to safe value. */
	352	CLOCK_SetSimSafeDivs();
	353	/* Set MCG to BLPI mode. */
	354	CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
	355	mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
	356	/* Set the clock configuration in SIM module. */
	357	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
	358	/* Set VLPR power mode. */
	359	SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
	360	#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
	361	SMC_SetPowerModeVlpr(SMC, false);
	362	#else
	363	SMC_SetPowerModeVlpr(SMC);
	364	#endif
	365	while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
	366	{
	367	}
	368	/* Set SystemCoreClock variable. */
	369	SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
	370	/* Set LPUART clock source. */
	371	CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
	372	}