1 files changed, 901 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c
new file mode 100644
index 000000000..0e179a854
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c
@@ -0,0 +1,901 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v6.0
+processor: K32L2A31xxxxA
+package_id: K32L2A31VLL1A
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+pin_labels:
+- {pin_num: '1', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, label: 'U2[3]/INT1_21002', identifier: GYRO_INT1}
+- {pin_num: '2', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, label: 'U2[2]/INT2_21002', identifier: GYRO_INT2}
+- {pin_num: '3', pin_signal: ADC0_SE18/PTE2/LLWU_P1/LPSPI1_SCK/LPUART1_CTS_b/LPI2C1_SDAS, label: 'J2[5]'}
+- {pin_num: '4', pin_signal: ADC0_SE19/PTE3/LPSPI1_SIN/LPUART1_RTS_b/LPI2C1_SCLS, label: 'J2[7]'}
+- {pin_num: '5', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, label: BUTTON1, identifier: SW3}
+- {pin_num: '6', pin_signal: PTE5/LPSPI1_PCS1, label: 'U10[9]/INT2_8700', identifier: ACCEL_INT2}
+- {pin_num: '7', pin_signal: PTE6/LLWU_P16/LPSPI1_PCS2/USB_SOF_OUT, label: 'J2[9]'}
+- {pin_num: '8', pin_signal: VDD8, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '30', pin_signal: VDD31, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '22', pin_signal: VDDA, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '48', pin_signal: VDD53, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '75', pin_signal: VDD82, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '89', pin_signal: VDD98, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '9', pin_signal: VSS9, label: GND}
+- {pin_num: '25', pin_signal: VSSA, label: GND}
+- {pin_num: '29', pin_signal: VSS30, label: GND}
+- {pin_num: '49', pin_signal: VSS54, label: GND}
+- {pin_num: '74', pin_signal: VSS81, label: GND}
+- {pin_num: '88', pin_signal: VSS97, label: GND}
+- {pin_num: '11', pin_signal: USB0_DM, label: 'J10[2]/K32L2A_USB_DN', identifier: USB_DN}
+- {pin_num: '10', pin_signal: USB0_DP, label: 'J10[3]/K32L2A_USB_DP', identifier: USB_DP}
+- {pin_num: '12', pin_signal: VOUT33, label: TP11/VOUT33}
+- {pin_num: '13', pin_signal: VREGIN, label: P5V_K32L2A, identifier: VREGIN}
+- {pin_num: '14', pin_signal: ADC0_DP1/ADC0_SE1/PTE16/LPSPI0_PCS0/LPUART2_TX/TPM0_CLKIN/LPSPI1_PCS3/FXIO0_D0, label: 'J2[11]/FXIO_D0'}
+- {pin_num: '15', pin_signal: ADC0_DM1/ADC0_SE5a/PTE17/LLWU_P19/LPSPI0_SCK/LPUART2_RX/TPM1_CLKIN/LPTMR0_ALT3/LPTMR1_ALT3/FXIO0_D1, label: 'J2[13]/FXIO_D1'}
+- {pin_num: '16', pin_signal: ADC0_DP2/ADC0_SE2/PTE18/LLWU_P20/LPSPI0_SOUT/LPUART2_CTS_b/LPI2C0_SDA/FXIO0_D2, label: 'J2[15]/FXIO_D2'}
+- {pin_num: '17', pin_signal: ADC0_DM2/ADC0_SE6a/PTE19/LPSPI0_SIN/LPUART2_RTS_b/LPI2C0_SCL/FXIO0_D3, label: 'J2[17]/FXIO_D3'}
+- {pin_num: '18', pin_signal: ADC0_DP0/ADC0_SE0/PTE20/LPSPI2_SCK/TPM1_CH0/LPUART0_TX/FXIO0_D4, label: 'J4[1]/DIFF_ADC0_DP0/FXIO_D4'}
+- {pin_num: '19', pin_signal: ADC0_DM0/ADC0_SE4a/PTE21/LPSPI2_SOUT/TPM1_CH1/LPUART0_RX/FXIO0_D5, label: 'J4[3]/DIFF_ADC0_DM0/FXIO_D5'}
+- {pin_num: '20', pin_signal: ADC0_DP3/ADC0_SE3/PTE22/LPSPI2_SIN/TPM2_CH0/LPUART2_TX/FXIO0_D6, label: 'J4[5]/DIFF_ADC0_DP3/FXIO_D6'}
+- {pin_num: '21', pin_signal: ADC0_DM3/ADC0_SE7a/PTE23/LPSPI2_PCS0/TPM2_CH1/LPUART2_RX/FXIO0_D7, label: 'J4[7]/DIFF_ADC0_DM3/FXIO_D7'}
+- {pin_num: '23', pin_signal: VREFH/VREF_OUT, label: 'J17[2]/P3V3_K32L2A'}
+- {pin_num: '24', pin_signal: VREFL, label: GND}
+- {pin_num: '26', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, label: LEDRGB_RED, identifier: LED_RED}
+- {pin_num: '27', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23/CMP0_IN4/PTE30/EMVSIM0_RST/TPM0_CH3/TPM1_CLKIN, label: 'J4[11]/DAC0_OUT'}
+- {pin_num: '28', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, label: LEDRGB_BLUE, identifier: LED_BLUE}
+- {pin_num: '31', pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, label: 'U2[11]/U10[4]/ACCEL_I2C0_SCL', identifier: ACCEL_SCL;GYRO_SCL}
+- {pin_num: '32', pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, label: 'U2[12]/U10[6]/ACCEL_I2C0_SDA', identifier: ACCEL_SDA;GYRO_SDA}
+- {pin_num: '33', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, label: 'U10[16]/U11[2]/ACCEL_RST', identifier: ACCEL_RST;GYRO_RST}
+- {pin_num: '34', pin_signal: TSI0_CH1/PTA0/LPUART0_CTS_b/TPM0_CH5/LPI2C0_SDAS/SWD_CLK, label: 'J11[4]/U5[11]/K32L2A_SWD_CLK/SWD_CLK_TGTMCU'}
+- {pin_num: '35', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, label: TSI_ELECTRODE1/TSI0_CH2, identifier: TSI_ELECTRODE_1}
+- {pin_num: '36', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, label: TSI_ELECTRODE2/TSI0_CH3, identifier: TSI_ELECTRODE_2}
+- {pin_num: '37', pin_signal: TSI0_CH4/PTA3/LPI2C1_SCL/TPM0_CH0/LPUART0_RTS_b/SWD_DIO, label: 'J11[2]/U5[3]/SWD_DIO_TGTMCU'}
+- {pin_num: '38', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, label: BUTTON2, identifier: SW2}
+- {pin_num: '39', pin_signal: PTA5/USB_CLKIN/TPM0_CH2/LPI2C2_HREQ, label: 'J3[1]'}
+- {pin_num: '40', pin_signal: PTA6/TPM0_CH3, label: 'J3[3]'}
+- {pin_num: '41', pin_signal: PTA7/LPSPI0_PCS3/TPM0_CH4/LPI2C2_SDAS, label: 'J3[5]'}
+- {pin_num: '42', pin_signal: PTA12/TPM1_CH0/LPI2C2_SCL, label: 'J2[20]/D15/I2C2_SCL'}
+- {pin_num: '43', pin_signal: PTA13/LLWU_P4/TPM1_CH1/LPI2C2_SDA, label: 'J2[18]/D14/I2C2_SDA'}
+- {pin_num: '44', pin_signal: PTA14/LPSPI0_PCS0/LPUART0_TX/LPI2C2_SCL, label: 'J3[7]'}
+- {pin_num: '45', pin_signal: PTA15/LPSPI0_SCK/LPUART0_RX, label: 'J3[9]'}
+- {pin_num: '46', pin_signal: PTA16/LPSPI0_SOUT/LPUART0_CTS_b, label: 'J3[11]'}
+- {pin_num: '47', pin_signal: ADC0_SE22/PTA17/LPSPI0_SIN/LPUART0_RTS_b, label: 'J3[13]'}
+- {pin_num: '50', pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, label: 'Y1[1]/EXTAL_32KHZ', identifier: EXTAL0}
+- {pin_num: '51', pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, label: 'Y1[2]/XTAL_32KHZ', identifier: XTAL0}
+- {pin_num: '52', pin_signal: PTA20/LPI2C0_SCLS/TPM2_CLKIN/RESET_b, label: 'J3[6]/J11[10]/U7[21]/RST_K20D50_B'}
+- {pin_num: '53', pin_signal: ADC0_SE8/TSI0_CH0/PTB0/LLWU_P5/LPI2C0_SCL/TPM1_CH0/FXIO0_D8, label: 'J4[2]/A0/ADC0_SE8/FXIO_D8'}
+- {pin_num: '54', pin_signal: ADC0_SE9/TSI0_CH6/PTB1/LPI2C0_SDA/TPM1_CH1/FXIO0_D9, label: 'J4[4]/A1/ADC0_SE9/FXIO_D9'}
+- {pin_num: '55', pin_signal: ADC0_SE12/TSI0_CH7/PTB2/LPI2C0_SCL/TPM2_CH0/LPUART0_RTS_b/FXIO0_D10, label: 'J1[6]/D2/FXIO_D10'}
+- {pin_num: '56', pin_signal: ADC0_SE13/TSI0_CH8/PTB3/LPI2C0_SDA/TPM2_CH1/LPSPI1_PCS3/LPUART0_CTS_b/FXIO0_D11, label: 'J4[8]/A3/ADC0_SE13/FXIO_D11'}
+- {pin_num: '57', pin_signal: PTB7/LPSPI1_PCS1, label: 'U7[31]/OpenSDA GPIO'}
+- {pin_num: '58', pin_signal: PTB8/LPSPI1_PCS0/FXIO0_D12, label: 'J3[15]/FXIO_D12'}
+- {pin_num: '59', pin_signal: PTB9/LPSPI1_SCK/FXIO0_D13, label: 'J1[8]/D3/FXIO_D13'}
+- {pin_num: '60', pin_signal: PTB10/LPSPI1_PCS0/FXIO0_D14, label: 'J1[10]/D4/FXIO_D14'}
+- {pin_num: '61', pin_signal: PTB11/LPSPI1_SCK/TPM2_CLKIN/FXIO0_D15, label: 'J1[12]/D5/FXIO_D15'}
+- {pin_num: '62', pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, label: 'J1[2]/U7[25]/D0/UART0_RX/FXIO_D16/UART1_RX_TGTMCU',
+  identifier: DEBUG_UART_RX}
+- {pin_num: '63', pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, label: 'J1[4]/U7[24]/D1/UART0_TX/FXIO_D17/UART1_TX_TGTMCU',
+  identifier: DEBUG_UART_TX}
+- {pin_num: '64', pin_signal: TSI0_CH11/PTB18/TPM2_CH0/LPI2C1_HREQ/FXIO0_D18, label: 'J1[1]/FXIO_D18'}
+- {pin_num: '65', pin_signal: TSI0_CH12/PTB19/TPM2_CH1/LPSPI2_PCS1/FXIO0_D19, label: 'J1[3]/FXIO_D19'}
+- {pin_num: '66', pin_signal: PTB20/LPSPI2_PCS0/CMP0_OUT, label: 'J20[4]/SPI2_PCS0'}
+- {pin_num: '67', pin_signal: PTB21/LPSPI2_SCK/CMP1_OUT, label: 'J20[5]/SPI2_SCK'}
+- {pin_num: '68', pin_signal: PTB22/LPSPI2_SOUT, label: 'J20[6]/SPI2_SOUT'}
+- {pin_num: '69', pin_signal: PTB23/LPSPI2_SIN, label: 'J20[7]/SPI2_SIN'}
+- {pin_num: '70', pin_signal: ADC0_SE14/TSI0_CH13/PTC0/LPSPI2_PCS1/USB_SOF_OUT/CMP0_OUT, label: 'J1[5]'}
+- {pin_num: '71', pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/LPI2C1_SCL/LPUART1_RTS_b/TPM0_CH0, label: 'J4[12]/A5/ADC0_SE15/I2C1_SCL'}
+- {pin_num: '72', pin_signal: ADC0_SE11/CMP1_IN0/TSI0_CH15/PTC2/LPI2C1_SDA/LPUART1_CTS_b/TPM0_CH1, label: 'J4[10]/A4/ADC0_SE11/I2C1_SDA'}
+- {pin_num: '73', pin_signal: CMP1_IN1/PTC3/LLWU_P7/LPSPI0_PCS1/LPUART1_RX/TPM0_CH2/CLKOUT, label: 'J4[6]/A2/CMP1_IN1/SPI0_PCS1'}
+- {pin_num: '76', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, label: LEDRGB_GREEN, identifier: LED_GREEN}
+- {pin_num: '77', pin_signal: PTC5/LLWU_P9/LPSPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/CMP0_OUT, label: 'J4[9]/CMP0_OUT'}
+- {pin_num: '78', pin_signal: CMP0_IN0/PTC6/LLWU_P10/LPSPI0_SOUT, label: 'J20[3]'}
+- {pin_num: '79', pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, label: 'J1[11]/SOF_OUT/FXIO_D20', identifier: SOF_OUT}
+- {pin_num: '80', pin_signal: CMP0_IN2/PTC8/LPI2C0_SCL/TPM0_CH4/FXIO0_D21, label: 'J1[7]/FXIO_D21'}
+- {pin_num: '81', pin_signal: CMP0_IN3/PTC9/LPI2C0_SDA/TPM0_CH5/FXIO0_D22, label: 'J1[9]/FXIO_D22'}
+- {pin_num: '82', pin_signal: PTC10/LPI2C1_SCL/FXIO0_D23, label: 'J1[13]/FXIO_D23'}
+- {pin_num: '83', pin_signal: PTC11/LLWU_P11/LPI2C1_SDA, label: 'J1[15]'}
+- {pin_num: '84', pin_signal: PTC12/LPI2C1_SCLS/TPM0_CLKIN, label: 'J1[14]/D6'}
+- {pin_num: '85', pin_signal: PTC13/LPI2C1_SDAS/TPM1_CLKIN, label: 'J1[16]/D7'}
+- {pin_num: '86', pin_signal: PTC14/EMVSIM0_CLK, label: 'JP1[3]/EMVSIM_CLK'}
+- {pin_num: '87', pin_signal: PTC15/EMVSIM0_RST, label: 'JP1[4]/EMVSIM_RST'}
+- {pin_num: '90', pin_signal: PTC16/EMVSIM0_VCCEN, label: 'JP1[5]/EMVSIM_VCCEN'}
+- {pin_num: '91', pin_signal: PTC17/EMVSIM0_IO/LPSPI0_PCS3, label: 'JP1[6]/EMVSIM_IO'}
+- {pin_num: '92', pin_signal: PTC18/EMVSIM0_PD/LPSPI0_PCS2, label: 'JP1[7]/EMVSIM_PD'}
+- {pin_num: '93', pin_signal: PTD0/LLWU_P12/LPSPI0_PCS0/LPUART2_RTS_b/TPM0_CH0/FXIO0_D0, label: 'J2[6]/D10/SPI0_PCS0'}
+- {pin_num: '94', pin_signal: ADC0_SE5b/PTD1/LPSPI0_SCK/LPUART2_CTS_b/TPM0_CH1/FXIO0_D1, label: 'J2[12]/D13/SPI0_SCK'}
+- {pin_num: '95', pin_signal: PTD2/LLWU_P13/LPSPI0_SOUT/LPUART2_RX/TPM0_CH2/FXIO0_D2, label: 'J2[8]/D11/SPI0_SOUT'}
+- {pin_num: '96', pin_signal: PTD3/LPSPI0_SIN/LPUART2_TX/TPM0_CH3/FXIO0_D3, label: 'J2[10]/D12/SPI0_SIN'}
+- {pin_num: '97', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, label: 'U10[11]/INT1_8700', identifier: ACCEL_INT1}
+- {pin_num: '98', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, label: 'Q1[1]/LIGHT_SENSOR', identifier: LIGHT_SENSOR}
+- {pin_num: '99', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/LPSPI1_SOUT/LPUART0_RX/FXIO0_D6, label: 'J2[2]/D8'}
+- {pin_num: '100', pin_signal: PTD7/LPSPI1_SIN/LPUART0_TX/FXIO0_D7, label: 'J2[4]/D9'}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+    BOARD_InitDEBUG_UARTPins();
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitBUTTONsPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '5', peripheral: GPIOE, signal: 'GPIO, 4', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, direction: INPUT, slew_rate: slow, open_drain: disable, pull_select: up,
+    pull_enable: enable}
+  - {pin_num: '38', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, direction: INPUT, slew_rate: slow, open_drain: disable,
+    pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBUTTONsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBUTTONsPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+    gpio_pin_config_t SW2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTA4 (pin 38)  */
+    GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
+    gpio_pin_config_t SW3_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE4 (pin 5)  */
+    GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
+    /* PORTA4 (pin 38) is configured as PTA4 */
+    PORT_SetPinMux(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_MuxAsGpio);
+    PORTA->PCR[4] =
+        ((PORTA->PCR[4] &
+          /* Mask bits to zero which are setting */
+          (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
+         /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
+          * field is set. */
+         | PORT_PCR_PS(kPORT_PullDown)
+         /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
+         | PORT_PCR_PE(kPORT_PullDisable)
+         /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
+          * a digital output. */
+         | PORT_PCR_SRE(kPORT_SlowSlewRate)
+         /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
+         | PORT_PCR_ODE(kPORT_OpenDrainDisable));
+    const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
+                                   kPORT_PullUp,
+                                   /* Slow slew rate is configured */
+                                   kPORT_SlowSlewRate,
+                                   /* Passive filter is disabled */
+                                   kPORT_PassiveFilterDisable,
+                                   /* Open drain is disabled */
+                                   kPORT_OpenDrainDisable,
+                                   /* Low drive strength is configured */
+                                   kPORT_LowDriveStrength,
+                                   /* Pin is configured as PTE4 */
+                                   kPORT_MuxAsGpio,
+                                   /* Pin Control Register fields [15:0] are not locked */
+                                   kPORT_UnlockRegister};
+    /* PORTE4 (pin 5) is configured as PTE4 */
+    PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLEDsPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '26', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, direction: OUTPUT, gpio_init_state: 'true',
+    slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
+  - {pin_num: '28', peripheral: GPIOE, signal: 'GPIO, 31', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, direction: OUTPUT, gpio_init_state: 'true',
+    slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
+  - {pin_num: '76', peripheral: GPIOC, signal: 'GPIO, 4', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, direction: OUTPUT, gpio_init_state: 'true',
+    slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLEDsPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLEDsPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortC);
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+    gpio_pin_config_t LED_GREEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTC4 (pin 76)  */
+    GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
+    gpio_pin_config_t LED_RED_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTE29 (pin 26)  */
+    GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
+    gpio_pin_config_t LED_BLUE_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PTE31 (pin 28)  */
+    GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
+    /* PORTC4 (pin 76) is configured as PTC4 */
+    PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio);
+    PORTC->PCR[4] =
+        ((PORTC->PCR[4] &
+          /* Mask bits to zero which are setting */
+          (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
+         /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
+          * field is set. */
+         | PORT_PCR_PS(kPORT_PullDown)
+         /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
+         | PORT_PCR_PE(kPORT_PullDisable)
+         /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
+          * a digital output. */
+         | PORT_PCR_SRE(kPORT_SlowSlewRate)
+         /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
+         | PORT_PCR_ODE(kPORT_OpenDrainDisable));
+    const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Slow slew rate is configured */
+                                       kPORT_SlowSlewRate,
+                                       /* Passive filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Pin is configured as PTE29 */
+                                       kPORT_MuxAsGpio,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORTE29 (pin 26) is configured as PTE29 */
+    PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
+    const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
+                                        kPORT_PullDisable,
+                                        /* Slow slew rate is configured */
+                                        kPORT_SlowSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* Low drive strength is configured */
+                                        kPORT_LowDriveStrength,
+                                        /* Pin is configured as PTE31 */
+                                        kPORT_MuxAsGpio,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE31 (pin 28) is configured as PTE31 */
+    PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitTOUCHPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '35', peripheral: TSI0, signal: 'CH, 2', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
+  - {pin_num: '36', peripheral: TSI0, signal: 'CH, 3', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitTOUCHPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitTOUCHPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+    const port_pin_config_t TSI_ELECTRODE_1 = {/* Internal pull-up/down resistor is disabled */
+                                               kPORT_PullDisable,
+                                               /* Fast slew rate is configured */
+                                               kPORT_FastSlewRate,
+                                               /* Passive filter is disabled */
+                                               kPORT_PassiveFilterDisable,
+                                               /* Open drain is disabled */
+                                               kPORT_OpenDrainDisable,
+                                               /* Low drive strength is configured */
+                                               kPORT_LowDriveStrength,
+                                               /* Pin is configured as TSI0_CH2 */
+                                               kPORT_PinDisabledOrAnalog,
+                                               /* Pin Control Register fields [15:0] are not locked */
+                                               kPORT_UnlockRegister};
+    /* PORTA1 (pin 35) is configured as TSI0_CH2 */
+    PORT_SetPinConfig(BOARD_TSI_ELECTRODE_1_PORT, BOARD_TSI_ELECTRODE_1_PIN, &TSI_ELECTRODE_1);
+    const port_pin_config_t TSI_ELECTRODE_2 = {/* Internal pull-up/down resistor is disabled */
+                                               kPORT_PullDisable,
+                                               /* Fast slew rate is configured */
+                                               kPORT_FastSlewRate,
+                                               /* Passive filter is disabled */
+                                               kPORT_PassiveFilterDisable,
+                                               /* Open drain is disabled */
+                                               kPORT_OpenDrainDisable,
+                                               /* Low drive strength is configured */
+                                               kPORT_LowDriveStrength,
+                                               /* Pin is configured as TSI0_CH3 */
+                                               kPORT_PinDisabledOrAnalog,
+                                               /* Pin Control Register fields [15:0] are not locked */
+                                               kPORT_UnlockRegister};
+    /* PORTA2 (pin 36) is configured as TSI0_CH3 */
+    PORT_SetPinConfig(BOARD_TSI_ELECTRODE_2_PORT, BOARD_TSI_ELECTRODE_2_PIN, &TSI_ELECTRODE_2);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitLIGHT_SENSORPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '98', peripheral: ADC0, signal: 'SE, 6b', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, slew_rate: fast, open_drain: disable,
+    pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitLIGHT_SENSORPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitLIGHT_SENSORPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortD);
+    /* PORTD5 (pin 98) is configured as ADC0_SE6b */
+    PORT_SetPinMux(BOARD_LIGHT_SENSOR_PORT, BOARD_LIGHT_SENSOR_PIN, kPORT_PinDisabledOrAnalog);
+    PORTD->PCR[5] =
+        ((PORTD->PCR[5] &
+          /* Mask bits to zero which are setting */
+          (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
+         /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
+          * field is set. */
+         | PORT_PCR_PS(kPORT_PullDown)
+         /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
+         | PORT_PCR_PE(kPORT_PullDisable)
+         /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
+          * a digital output. */
+         | PORT_PCR_SRE(kPORT_FastSlewRate)
+         /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
+         | PORT_PCR_ODE(kPORT_OpenDrainDisable));
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitUSBPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '11', peripheral: USB0, signal: DM, pin_signal: USB0_DM}
+  - {pin_num: '10', peripheral: USB0, signal: DP, pin_signal: USB0_DP}
+  - {pin_num: '13', peripheral: USB0, signal: VREGIN, pin_signal: VREGIN}
+  - {pin_num: '79', peripheral: USB0, signal: SOF_OUT, pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, slew_rate: fast, open_drain: disable, pull_select: down,
+    pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitUSBPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitUSBPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortC);
+    const port_pin_config_t SOF_OUT = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Fast slew rate is configured */
+                                       kPORT_FastSlewRate,
+                                       /* Passive filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Pin is configured as USB_SOF_OUT */
+                                       kPORT_MuxAlt3,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORTC7 (pin 79) is configured as USB_SOF_OUT */
+    PORT_SetPinConfig(BOARD_SOF_OUT_PORT, BOARD_SOF_OUT_PIN, &SOF_OUT);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitDEBUG_UARTPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '62', peripheral: LPUART0, signal: RX, pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, slew_rate: fast, open_drain: disable,
+    pull_select: down, pull_enable: disable}
+  - {pin_num: '63', peripheral: LPUART0, signal: TX, pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, direction: OUTPUT, slew_rate: fast,
+    open_drain: disable, pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitDEBUG_UARTPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitDEBUG_UARTPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortB);
+    const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
+                                             kPORT_PullDisable,
+                                             /* Fast slew rate is configured */
+                                             kPORT_FastSlewRate,
+                                             /* Passive filter is disabled */
+                                             kPORT_PassiveFilterDisable,
+                                             /* Open drain is disabled */
+                                             kPORT_OpenDrainDisable,
+                                             /* Low drive strength is configured */
+                                             kPORT_LowDriveStrength,
+                                             /* Pin is configured as LPUART0_RX */
+                                             kPORT_MuxAlt3,
+                                             /* Pin Control Register fields [15:0] are not locked */
+                                             kPORT_UnlockRegister};
+    /* PORTB16 (pin 62) is configured as LPUART0_RX */
+    PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
+    const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
+                                             kPORT_PullDisable,
+                                             /* Fast slew rate is configured */
+                                             kPORT_FastSlewRate,
+                                             /* Passive filter is disabled */
+                                             kPORT_PassiveFilterDisable,
+                                             /* Open drain is disabled */
+                                             kPORT_OpenDrainDisable,
+                                             /* Low drive strength is configured */
+                                             kPORT_LowDriveStrength,
+                                             /* Pin is configured as LPUART0_TX */
+                                             kPORT_MuxAlt3,
+                                             /* Pin Control Register fields [15:0] are not locked */
+                                             kPORT_UnlockRegister};
+    /* PORTB17 (pin 63) is configured as LPUART0_TX */
+    PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitACCELPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: ACCEL_SDA, slew_rate: fast,
+    open_drain: enable, pull_select: down, pull_enable: disable}
+  - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: ACCEL_SCL, slew_rate: fast, open_drain: enable,
+    pull_select: down, pull_enable: disable}
+  - {pin_num: '97', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, direction: INPUT, slew_rate: fast,
+    open_drain: disable, pull_select: up, pull_enable: enable}
+  - {pin_num: '6', peripheral: GPIOE, signal: 'GPIO, 5', pin_signal: PTE5/LPSPI1_PCS1, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
+  - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: ACCEL_RST, direction: OUTPUT,
+    slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitACCELPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitACCELPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortD);
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+    gpio_pin_config_t ACCEL_INT1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTD4 (pin 97)  */
+    GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
+    gpio_pin_config_t ACCEL_INT2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE5 (pin 6)  */
+    GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
+    gpio_pin_config_t ACCEL_RST_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE26 (pin 33)  */
+    GPIO_PinInit(BOARD_ACCEL_RST_GPIO, BOARD_ACCEL_RST_PIN, &ACCEL_RST_config);
+    /* PORTD4 (pin 97) is configured as PTD4 */
+    PORT_SetPinMux(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, kPORT_MuxAsGpio);
+    PORTD->PCR[4] =
+        ((PORTD->PCR[4] &
+          /* Mask bits to zero which are setting */
+          (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
+         /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE
+          * field is set. */
+         | (uint32_t)(kPORT_PullUp)
+         /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
+          * a digital output. */
+         | PORT_PCR_SRE(kPORT_FastSlewRate)
+         /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
+         | PORT_PCR_ODE(kPORT_OpenDrainDisable));
+    const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
+                                         kPORT_PullDisable,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is enabled */
+                                         kPORT_OpenDrainEnable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as LPI2C0_SCL */
+                                         kPORT_MuxAlt5,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
+    PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
+    const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
+                                         kPORT_PullDisable,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is enabled */
+                                         kPORT_OpenDrainEnable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as LPI2C0_SDA */
+                                         kPORT_MuxAlt5,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
+    PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
+    const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */
+                                         kPORT_PullDisable,
+                                         /* Slow slew rate is configured */
+                                         kPORT_SlowSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as PTE26 */
+                                         kPORT_MuxAsGpio,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE26 (pin 33) is configured as PTE26 */
+    PORT_SetPinConfig(BOARD_ACCEL_RST_PORT, BOARD_ACCEL_RST_PIN, &ACCEL_RST);
+    const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
+                                          kPORT_PullUp,
+                                          /* Fast slew rate is configured */
+                                          kPORT_FastSlewRate,
+                                          /* Passive filter is disabled */
+                                          kPORT_PassiveFilterDisable,
+                                          /* Open drain is disabled */
+                                          kPORT_OpenDrainDisable,
+                                          /* Low drive strength is configured */
+                                          kPORT_LowDriveStrength,
+                                          /* Pin is configured as PTE5 */
+                                          kPORT_MuxAsGpio,
+                                          /* Pin Control Register fields [15:0] are not locked */
+                                          kPORT_UnlockRegister};
+    /* PORTE5 (pin 6) is configured as PTE5 */
+    PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitGYROPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: GYRO_SCL, slew_rate: fast, open_drain: enable,
+    pull_select: down, pull_enable: disable}
+  - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: GYRO_SDA, slew_rate: fast, open_drain: enable,
+    pull_select: down, pull_enable: disable}
+  - {pin_num: '1', peripheral: GPIOE, signal: 'GPIO, 0', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, direction: INPUT, slew_rate: fast,
+    open_drain: disable, pull_select: up, pull_enable: enable}
+  - {pin_num: '2', peripheral: GPIOE, signal: 'GPIO, 1', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, direction: INPUT, slew_rate: fast,
+    open_drain: disable, pull_select: up, pull_enable: enable}
+  - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: GYRO_RST, direction: OUTPUT, slew_rate: slow,
+    open_drain: disable, pull_select: down, pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitGYROPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitGYROPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortE);
+    gpio_pin_config_t GYRO_INT1_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE0 (pin 1)  */
+    GPIO_PinInit(BOARD_GYRO_INT1_GPIO, BOARD_GYRO_INT1_PIN, &GYRO_INT1_config);
+    gpio_pin_config_t GYRO_INT2_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE1 (pin 2)  */
+    GPIO_PinInit(BOARD_GYRO_INT2_GPIO, BOARD_GYRO_INT2_PIN, &GYRO_INT2_config);
+    gpio_pin_config_t GYRO_RST_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PTE26 (pin 33)  */
+    GPIO_PinInit(BOARD_GYRO_RST_GPIO, BOARD_GYRO_RST_PIN, &GYRO_RST_config);
+    const port_pin_config_t GYRO_INT1 = {/* Internal pull-up resistor is enabled */
+                                         kPORT_PullUp,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as PTE0 */
+                                         kPORT_MuxAsGpio,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE0 (pin 1) is configured as PTE0 */
+    PORT_SetPinConfig(BOARD_GYRO_INT1_PORT, BOARD_GYRO_INT1_PIN, &GYRO_INT1);
+    const port_pin_config_t GYRO_INT2 = {/* Internal pull-up resistor is enabled */
+                                         kPORT_PullUp,
+                                         /* Fast slew rate is configured */
+                                         kPORT_FastSlewRate,
+                                         /* Passive filter is disabled */
+                                         kPORT_PassiveFilterDisable,
+                                         /* Open drain is disabled */
+                                         kPORT_OpenDrainDisable,
+                                         /* Low drive strength is configured */
+                                         kPORT_LowDriveStrength,
+                                         /* Pin is configured as PTE1 */
+                                         kPORT_MuxAsGpio,
+                                         /* Pin Control Register fields [15:0] are not locked */
+                                         kPORT_UnlockRegister};
+    /* PORTE1 (pin 2) is configured as PTE1 */
+    PORT_SetPinConfig(BOARD_GYRO_INT2_PORT, BOARD_GYRO_INT2_PIN, &GYRO_INT2);
+    const port_pin_config_t GYRO_SCL = {/* Internal pull-up/down resistor is disabled */
+                                        kPORT_PullDisable,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is enabled */
+                                        kPORT_OpenDrainEnable,
+                                        /* Low drive strength is configured */
+                                        kPORT_LowDriveStrength,
+                                        /* Pin is configured as LPI2C0_SCL */
+                                        kPORT_MuxAlt5,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
+    PORT_SetPinConfig(BOARD_GYRO_SCL_PORT, BOARD_GYRO_SCL_PIN, &GYRO_SCL);
+    const port_pin_config_t GYRO_SDA = {/* Internal pull-up/down resistor is disabled */
+                                        kPORT_PullDisable,
+                                        /* Fast slew rate is configured */
+                                        kPORT_FastSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is enabled */
+                                        kPORT_OpenDrainEnable,
+                                        /* Low drive strength is configured */
+                                        kPORT_LowDriveStrength,
+                                        /* Pin is configured as LPI2C0_SDA */
+                                        kPORT_MuxAlt5,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
+    PORT_SetPinConfig(BOARD_GYRO_SDA_PORT, BOARD_GYRO_SDA_PIN, &GYRO_SDA);
+    const port_pin_config_t GYRO_RST = {/* Internal pull-up/down resistor is disabled */
+                                        kPORT_PullDisable,
+                                        /* Slow slew rate is configured */
+                                        kPORT_SlowSlewRate,
+                                        /* Passive filter is disabled */
+                                        kPORT_PassiveFilterDisable,
+                                        /* Open drain is disabled */
+                                        kPORT_OpenDrainDisable,
+                                        /* Low drive strength is configured */
+                                        kPORT_LowDriveStrength,
+                                        /* Pin is configured as PTE26 */
+                                        kPORT_MuxAsGpio,
+                                        /* Pin Control Register fields [15:0] are not locked */
+                                        kPORT_UnlockRegister};
+    /* PORTE26 (pin 33) is configured as PTE26 */
+    PORT_SetPinConfig(BOARD_GYRO_RST_PORT, BOARD_GYRO_RST_PIN, &GYRO_RST);
+}
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitOSCPins:
+- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '50', peripheral: SCG, signal: EXTAL0, pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
+  - {pin_num: '51', peripheral: SCG, signal: XTAL0, pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, slew_rate: fast, open_drain: disable, pull_select: down,
+    pull_enable: disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitOSCPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitOSCPins(void)
+{
+    /* Clock Gate Control: Clock enabled */
+    CLOCK_EnableClock(kCLOCK_PortA);
+    const port_pin_config_t EXTAL0 = {/* Internal pull-up/down resistor is disabled */
+                                      kPORT_PullDisable,
+                                      /* Fast slew rate is configured */
+                                      kPORT_FastSlewRate,
+                                      /* Passive filter is disabled */
+                                      kPORT_PassiveFilterDisable,
+                                      /* Open drain is disabled */
+                                      kPORT_OpenDrainDisable,
+                                      /* Low drive strength is configured */
+                                      kPORT_LowDriveStrength,
+                                      /* Pin is configured as EXTAL0 */
+                                      kPORT_PinDisabledOrAnalog,
+                                      /* Pin Control Register fields [15:0] are not locked */
+                                      kPORT_UnlockRegister};
+    /* PORTA18 (pin 50) is configured as EXTAL0 */
+    PORT_SetPinConfig(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, &EXTAL0);
+    const port_pin_config_t XTAL0 = {/* Internal pull-up/down resistor is disabled */
+                                     kPORT_PullDisable,
+                                     /* Fast slew rate is configured */
+                                     kPORT_FastSlewRate,
+                                     /* Passive filter is disabled */
+                                     kPORT_PassiveFilterDisable,
+                                     /* Open drain is disabled */
+                                     kPORT_OpenDrainDisable,
+                                     /* Low drive strength is configured */
+                                     kPORT_LowDriveStrength,
+                                     /* Pin is configured as XTAL0 */
+                                     kPORT_PinDisabledOrAnalog,
+                                     /* Pin Control Register fields [15:0] are not locked */
+                                     kPORT_UnlockRegister};
+    /* PORTA19 (pin 51) is configured as XTAL0 */
+    PORT_SetPinConfig(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, &XTAL0);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/