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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.c108
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.h202
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.c455
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.h164
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.c60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c901
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.h268
8 files changed, 2192 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.c
new file mode 100644
index 000000000..eed1b9214
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.c
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <stdint.h>
9#include "fsl_common.h"
10#include "fsl_debug_console.h"
11#include "board.h"
12#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
13#include "fsl_lpi2c.h"
14#endif /* SDK_I2C_BASED_COMPONENT_USED */
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23/* Initialize debug console. */
24void BOARD_InitDebugConsole(void)
25{
26 CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcSircAsync);
27
28 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
29
30 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
31}
32#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
33void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
34{
35 lpi2c_master_config_t lpi2cConfig = {0};
36
37 /*
38 * lpi2cConfig.debugEnable = false;
39 * lpi2cConfig.ignoreAck = false;
40 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
41 * lpi2cConfig.baudRate_Hz = 100000U;
42 * lpi2cConfig.busIdleTimeout_ns = 0;
43 * lpi2cConfig.pinLowTimeout_ns = 0;
44 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
45 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
46 */
47 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
48 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
49}
50
51status_t BOARD_LPI2C_Send(LPI2C_Type *base,
52 uint8_t deviceAddress,
53 uint32_t subAddress,
54 uint8_t subAddressSize,
55 uint8_t *txBuff,
56 uint8_t txBuffSize)
57{
58 lpi2c_master_transfer_t xfer;
59
60 xfer.flags = kLPI2C_TransferDefaultFlag;
61 xfer.slaveAddress = deviceAddress;
62 xfer.direction = kLPI2C_Write;
63 xfer.subaddress = subAddress;
64 xfer.subaddressSize = subAddressSize;
65 xfer.data = txBuff;
66 xfer.dataSize = txBuffSize;
67
68 return LPI2C_MasterTransferBlocking(base, &xfer);
69}
70
71status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
72 uint8_t deviceAddress,
73 uint32_t subAddress,
74 uint8_t subAddressSize,
75 uint8_t *rxBuff,
76 uint8_t rxBuffSize)
77{
78 lpi2c_master_transfer_t xfer;
79
80 xfer.flags = kLPI2C_TransferDefaultFlag;
81 xfer.slaveAddress = deviceAddress;
82 xfer.direction = kLPI2C_Read;
83 xfer.subaddress = subAddress;
84 xfer.subaddressSize = subAddressSize;
85 xfer.data = rxBuff;
86 xfer.dataSize = rxBuffSize;
87
88 return LPI2C_MasterTransferBlocking(base, &xfer);
89}
90
91void BOARD_Accel_I2C_Init(void)
92{
93 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
94}
95
96status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
97{
98 uint8_t data = (uint8_t)txBuff;
99
100 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
101}
102
103status_t BOARD_Accel_I2C_Receive(
104 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
105{
106 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
107}
108#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.h
new file mode 100644
index 000000000..1acfe5bb1
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/board.h
@@ -0,0 +1,202 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_gpio.h"
13
14/*******************************************************************************
15 * Definitions
16 ******************************************************************************/
17
18/*! @brief The board name */
19#define BOARD_NAME "FRDM-K32L2A4S"
20
21/*! @brief The UART to use for debug messages. */
22#define BOARD_USE_UART
23#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
24#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
25#define BOARD_DEBUG_UART_INSTANCE 0U
26#define BOARD_DEBUG_UART_CLKSRC kCLOCK_ScgSircAsyncDiv3Clk
27#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(kCLOCK_Lpuart0)
28#define BOARD_UART_IRQ LPUART0_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
30#define BOARD_DEBUG_UART_PCC_ADDRESS kCLOCK_Lpuart0
31
32#define BOARD_ACCEL_I2C_BASEADDR LPI2C0
33#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetIpFreq(kCLOCK_Lpi2c0))
34
35#ifndef BOARD_DEBUG_UART_BAUDRATE
36#define BOARD_DEBUG_UART_BAUDRATE 115200
37#endif /* BOARD_DEBUG_UART_BAUDRATE */
38
39/*! @brief The CMP instance/channel used for board. */
40#define BOARD_CMP_BASEADDR CMP0
41#define BOARD_CMP_CHANNEL 0U
42
43/*! @brief The rtc instance used for board. */
44#define BOARD_RTC_FUNC_BASEADDR RTC
45
46/*! @brief The tsi instance used for board. */
47#define BOARD_TSI_ELECTRODE_CNT 2
48#ifndef BOARD_TSI_ELECTRODE_1
49#define BOARD_TSI_ELECTRODE_1 2
50#endif
51#ifndef BOARD_TSI_ELECTRODE_2
52#define BOARD_TSI_ELECTRODE_2 3
53#endif
54
55/* @brief The EMVSIM SMARTCARD interface. */
56#define BOARD_SMARTCARD_MODULE (EMVSIM0) /*!< SMARTCARD communicational module instance */
57#define BOARD_SMARTCARD_MODULE_IRQ (EMVSIM0_IRQn) /*!< SMARTCARD communicational module IRQ handler */
58#define BOARD_SMARTCARD_CLOCK_MODULE (0U) /*!< SMARTCARD clock generation module instance (EMVSIM0) */
59#define BOARD_SMARTCARD_CLOCK_MODULE_CHANNEL (0U) /*!< SMARTCARD clock generation module channel */
60#define BOARD_SMARTCARD_CLOCK_MODULE_SOURCE_CLK \
61 (kCLOCK_ScgFircAsyncDiv3Clk) /*!< SMARTCARD clock module peripheral source clock */
62#define BOARD_SMARTCARD_CLOCK_MODULE_CLK_FREQ CLOCK_GetFreq(kCLOCK_ScgFircAsyncDiv3Clk)
63#define BOARD_SMARTCARD_CLOCK_VALUE (4000000U) /*!< SMARTCARD clock frequency */
64#define BOARD_SMARTCARD_CONTROL_PORT (2U) /*!< SMARTCARD control pin port instance number (PORTC) */
65#define BOARD_SMARTCARD_CONTROL_PIN (16U) /*!< SMARTCARD control pin number */
66#ifndef BOARD_SMARTCARD_RST_PORT
67#define BOARD_SMARTCARD_RST_PORT (2U) /*!< SMARTCARD reset pin port instance number (PORTC) */
68#endif
69#ifndef BOARD_SMARTCARD_RST_PIN
70#define BOARD_SMARTCARD_RST_PIN (15U) /*!< SMARTCARD reset pin number */
71#endif
72#define BOARD_SMARTCARD_IRQ_PORT (4U) /*!< SMARTCARD irq port pin instance number (PORTE) */
73#define BOARD_SMARTCARD_IRQ_PIN (2U) /*!< SMARTCARD irq pin number */
74#define BOARD_SMARTCARD_IRQ_PIN_IRQ (PORTE_IRQn) /*!< SMARTCARD irq port handler */
75#define BOARD_SMARTCARD_VSEL0_PORT (4U) /*!< SMARTCARD Voltage selection pin0 port instance (PORTE) */
76#define BOARD_SMARTCARD_VSEL0_PIN (3U) /*!< SMARTCARD Voltage selection pin0 pin number */
77#define BOARD_SMARTCARD_VSEL1_PORT (4U) /*!< SMARTCARD Voltage selection pin1 port instance (PORTE) */
78#define BOARD_SMARTCARD_VSEL1_PIN (6U) /*!< SMARTCARD Voltage selection pin1 pin number */
79
80/*! @brief Define the port interrupt number for the board switches */
81#ifndef BOARD_SW2_GPIO
82#define BOARD_SW2_GPIO GPIOA
83#endif
84#ifndef BOARD_SW2_PORT
85#define BOARD_SW2_PORT PORTA
86#endif
87#ifndef BOARD_SW2_GPIO_PIN
88#define BOARD_SW2_GPIO_PIN 4U
89#endif
90#define BOARD_SW2_IRQ PORTA_IRQn
91#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
92#define BOARD_SW2_NAME "SW2"
93
94#ifndef BOARD_SW3_GPIO
95#define BOARD_SW3_GPIO GPIOE
96#endif
97#ifndef BOARD_SW3_PORT
98#define BOARD_SW3_PORT PORTE
99#endif
100#ifndef BOARD_SW3_GPIO_PIN
101#define BOARD_SW3_GPIO_PIN 4U
102#endif
103#define BOARD_SW3_IRQ PORTE_IRQn
104#define BOARD_SW3_IRQ_HANDLER PORTE_IRQHandler
105#define BOARD_SW3_NAME "SW3"
106
107#define LLWU_SW_GPIO BOARD_SW3_GPIO
108#define LLWU_SW_PORT BOARD_SW3_PORT
109#define LLWU_SW_GPIO_PIN BOARD_SW3_GPIO_PIN
110#define LLWU_SW_IRQ BOARD_SW3_IRQ
111#define LLWU_SW_IRQ_HANDLER BOARD_SW3_IRQ_HANDLER
112#define LLWU_SW_NAME BOARD_SW3_NAME
113
114/* Board led color mapping */
115#define LOGIC_LED_ON 0U
116#define LOGIC_LED_OFF 1U
117#ifndef BOARD_LED_RED_GPIO
118#define BOARD_LED_RED_GPIO GPIOE
119#endif
120#define BOARD_LED_RED_GPIO_PORT PORTE
121#ifndef BOARD_LED_RED_GPIO_PIN
122#define BOARD_LED_RED_GPIO_PIN 29U
123#endif
124#ifndef BOARD_LED_GREEN_GPIO
125#define BOARD_LED_GREEN_GPIO GPIOC
126#endif
127#define BOARD_LED_GREEN_GPIO_PORT PORTC
128#ifndef BOARD_LED_GREEN_GPIO_PIN
129#define BOARD_LED_GREEN_GPIO_PIN 4U
130#endif
131#ifndef BOARD_LED_BLUE_GPIO
132#define BOARD_LED_BLUE_GPIO GPIOE
133#endif
134#define BOARD_LED_BLUE_GPIO_PORT PORTE
135#ifndef BOARD_LED_BLUE_GPIO_PIN
136#define BOARD_LED_BLUE_GPIO_PIN 31U
137#endif
138
139#define LED_RED_INIT(output) \
140 GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \
141 BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */
142#define LED_RED_ON() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */
143#define LED_RED_OFF() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */
144#define LED_RED_TOGGLE() \
145 GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */
146
147#define LED_GREEN_INIT(output) \
148 GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \
149 BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */
150#define LED_GREEN_ON() \
151 GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */
152#define LED_GREEN_OFF() \
153 GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */
154#define LED_GREEN_TOGGLE() \
155 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */
156
157#define LED_BLUE_INIT(output) \
158 GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \
159 BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */
160#define LED_BLUE_ON() \
161 GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE \
162 */
163#define LED_BLUE_OFF() \
164 GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE \
165 */
166#define LED_BLUE_TOGGLE() \
167 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */
168
169#if defined(__cplusplus)
170extern "C" {
171#endif /* __cplusplus */
172
173/*******************************************************************************
174 * API
175 ******************************************************************************/
176
177void BOARD_InitDebugConsole(void);
178#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
179void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
180status_t BOARD_LPI2C_Send(LPI2C_Type *base,
181 uint8_t deviceAddress,
182 uint32_t subAddress,
183 uint8_t subaddressSize,
184 uint8_t *txBuff,
185 uint8_t txBuffSize);
186status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
187 uint8_t deviceAddress,
188 uint32_t subAddress,
189 uint8_t subaddressSize,
190 uint8_t *rxBuff,
191 uint8_t rxBuffSize);
192void BOARD_Accel_I2C_Init(void);
193status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
194status_t BOARD_Accel_I2C_Receive(
195 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
196#endif /* SDK_I2C_BASED_COMPONENT_USED */
197
198#if defined(__cplusplus)
199}
200#endif /* __cplusplus */
201
202#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.c
new file mode 100644
index 000000000..34cdf1881
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.c
@@ -0,0 +1,455 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30/* clang-format off */
31/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32!!GlobalInfo
33product: Clocks v6.0
34processor: K32L2A31xxxxA
35package_id: K32L2A31VLL1A
36mcu_data: ksdk2_0
37processor_version: 0.0.0
38 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
39/* clang-format on */
40
41#include "fsl_smc.h"
42#include "clock_config.h"
43
44/*******************************************************************************
45 * Definitions
46 ******************************************************************************/
47#define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
48#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
49#define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
50#define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
51
52/*******************************************************************************
53 * Variables
54 ******************************************************************************/
55/* System clock frequency. */
56extern uint32_t SystemCoreClock;
57
58/*******************************************************************************
59 * Code
60 ******************************************************************************/
61/*FUNCTION**********************************************************************
62 *
63 * Function Name : CLOCK_CONFIG_SetScgOutSel
64 * Description : Set the SCG clock out select (CLKOUTSEL).
65 * Param setting : The selected clock source.
66 *
67 *END**************************************************************************/
68static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
69{
70 SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
71}
72
73/*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_FircSafeConfig
76 * Description : This function is used to safely configure FIRC clock.
77 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
78 * Before setting FIRC, change to use SIRC as system clock,
79 * then configure FIRC. After FIRC is set, change back to use FIRC
80 * in case SIRC need to be configured.
81 * Param fircConfig : FIRC configuration.
82 *
83 *END**************************************************************************/
84static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
85{
86 scg_sys_clk_config_t curConfig;
87 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
88 .div1 = kSCG_AsyncClkDisable,
89 .div3 = kSCG_AsyncClkDivBy2,
90 .range = kSCG_SircRangeHigh};
91 scg_sys_clk_config_t sysClkSafeConfigSource = {
92 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
93#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
94 .reserved1 = 0,
95 .reserved2 = 0,
96 .reserved3 = 0,
97#endif
98 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
99#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
100 .reserved4 = 0,
101#endif
102 .src = kSCG_SysClkSrcSirc, /* System clock source */
103#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
104 .reserved5 = 0,
105#endif
106 };
107 /* Init Sirc. */
108 CLOCK_InitSirc(&scgSircConfig);
109 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
110 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
111 /* Wait for clock source switch finished. */
112 do
113 {
114 CLOCK_GetCurSysClkConfig(&curConfig);
115 } while (curConfig.src != sysClkSafeConfigSource.src);
116
117 /* Init Firc. */
118 CLOCK_InitFirc(fircConfig);
119 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
120 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
121 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
122 /* Wait for clock source switch finished. */
123 do
124 {
125 CLOCK_GetCurSysClkConfig(&curConfig);
126 } while (curConfig.src != sysClkSafeConfigSource.src);
127}
128
129/*******************************************************************************
130 ************************ BOARD_InitBootClocks function ************************
131 ******************************************************************************/
132void BOARD_InitBootClocks(void)
133{
134 BOARD_BootClockRUN();
135}
136
137/*******************************************************************************
138 ********************** Configuration BOARD_BootClockRUN ***********************
139 ******************************************************************************/
140/* clang-format off */
141/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
142!!Configuration
143name: BOARD_BootClockRUN
144called_from_default_init: true
145outputs:
146- {id: Core_clock.outFreq, value: 48 MHz}
147- {id: LPO_clock.outFreq, value: 1 kHz}
148- {id: SIRC_CLK.outFreq, value: 8 MHz}
149- {id: Slow_clock.outFreq, value: 24 MHz}
150- {id: System_clock.outFreq, value: 48 MHz}
151 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
152/* clang-format on */
153
154/*******************************************************************************
155 * Variables for BOARD_BootClockRUN configuration
156 ******************************************************************************/
157const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
158 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
159#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
160 .reserved1 = 0,
161 .reserved2 = 0,
162 .reserved3 = 0,
163#endif
164 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
165#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
166 .reserved4 = 0,
167#endif
168 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
169#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
170 .reserved5 = 0,
171#endif
172};
173const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
174 .freq = 0U, /* System Oscillator frequency: 0Hz */
175 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
176 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
177 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
178 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
179 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
180 .workMode = kSCG_SysOscModeExt, /* Use external clock */
181};
182const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
183 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
184 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
185 .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
186 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
187};
188const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
189 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
190 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
191 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
192 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
193 .trimConfig = NULL, /* Fast IRC Trim disabled */
194};
195const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN = {
196 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
197 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
198 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
199 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
200 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
201 .prediv = 0, /* Divided by 1 */
202 .mult = 0, /* Multiply Factor is 16 */
203};
204/*******************************************************************************
205 * Code for BOARD_BootClockRUN configuration
206 ******************************************************************************/
207void BOARD_BootClockRUN(void)
208{
209 scg_sys_clk_config_t curConfig;
210
211 /* Init FIRC. */
212 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
213 /* Init SIRC. */
214 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
215 /* Set SCG to FIRC mode. */
216 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
217 /* Wait for clock source switch finished. */
218 do
219 {
220 CLOCK_GetCurSysClkConfig(&curConfig);
221 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
222 /* Set SystemCoreClock variable. */
223 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
224}
225
226/*******************************************************************************
227 ********************* Configuration BOARD_BootClockHSRUN **********************
228 ******************************************************************************/
229/* clang-format off */
230/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
231!!Configuration
232name: BOARD_BootClockHSRUN
233outputs:
234- {id: CLKOUT.outFreq, value: 8 MHz}
235- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
236- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
237- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
238- {id: LPO_clock.outFreq, value: 1 kHz}
239- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
240- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
241- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
242- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
243- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
244- {id: SIRC_CLK.outFreq, value: 8 MHz}
245- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
246- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
247- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
248- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
249- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
250- {id: System_clock.outFreq, value: 96 MHz}
251settings:
252- {id: SCGMode, value: SPLL}
253- {id: powerMode, value: HSRUN}
254- {id: CLKOUTConfig, value: 'yes'}
255- {id: SCG.DIVSLOW.scale, value: '4'}
256- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
257- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
258- {id: SCG.PREDIV.scale, value: '4'}
259- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
260- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
261- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
262- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
263- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
264- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
265- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
266- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
267- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
268- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
269- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
270- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
271sources:
272- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
273 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
274/* clang-format on */
275
276/*******************************************************************************
277 * Variables for BOARD_BootClockHSRUN configuration
278 ******************************************************************************/
279const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = {
280 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
281#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
282 .reserved1 = 0,
283 .reserved2 = 0,
284 .reserved3 = 0,
285#endif
286 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
287#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
288 .reserved4 = 0,
289#endif
290 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
291#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
292 .reserved5 = 0,
293#endif
294};
295const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN = {
296 .freq = 32768U, /* System Oscillator frequency: 32768Hz */
297 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk, /* Enable System OSC clock, Enable OSCERCLK */
298 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
299 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
300 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
301 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
302 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
303};
304const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
305 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
306 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
307 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
308 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
309};
310const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = {
311 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
312 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
313 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
314 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
315 .trimConfig = NULL, /* Fast IRC Trim disabled */
316};
317const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN = {
318 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
319 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
320 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
321 .div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
322 .src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
323 .prediv = 3, /* Divided by 4 */
324 .mult = 0, /* Multiply Factor is 16 */
325};
326/*******************************************************************************
327 * Code for BOARD_BootClockHSRUN configuration
328 ******************************************************************************/
329void BOARD_BootClockHSRUN(void)
330{
331 scg_sys_clk_config_t curConfig;
332
333 /* Init SOSC according to board configuration. */
334 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
335 /* Set the XTAL0 frequency based on board settings. */
336 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
337 /* Init FIRC. */
338 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
339 /* Init SIRC. */
340 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
341 /* Init SysPll. */
342 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
343 /* Set HSRUN power mode. */
344 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
345 SMC_SetPowerModeHsrun(SMC);
346 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
347 {
348 }
349
350 /* Set SCG to SPLL mode. */
351 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
352 /* Wait for clock source switch finished. */
353 do
354 {
355 CLOCK_GetCurSysClkConfig(&curConfig);
356 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
357 /* Set SystemCoreClock variable. */
358 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
359 /* Set SCG CLKOUT selection. */
360 CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
361}
362
363/*******************************************************************************
364 ********************* Configuration BOARD_BootClockVLPR ***********************
365 ******************************************************************************/
366/* clang-format off */
367/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
368!!Configuration
369name: BOARD_BootClockVLPR
370outputs:
371- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
372- {id: LPO_clock.outFreq, value: 1 kHz}
373- {id: SIRC_CLK.outFreq, value: 8 MHz}
374- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
375- {id: System_clock.outFreq, value: 8 MHz}
376settings:
377- {id: SCGMode, value: SIRC}
378- {id: powerMode, value: VLPR}
379- {id: SCG.DIVSLOW.scale, value: '8'}
380- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
381- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
382sources:
383- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
384 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
385/* clang-format on */
386
387/*******************************************************************************
388 * Variables for BOARD_BootClockVLPR configuration
389 ******************************************************************************/
390const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
391 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
392#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
393 .reserved1 = 0,
394 .reserved2 = 0,
395 .reserved3 = 0,
396#endif
397 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
398#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
399 .reserved4 = 0,
400#endif
401 .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
402#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
403 .reserved5 = 0,
404#endif
405};
406const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
407 .freq = 0U, /* System Oscillator frequency: 0Hz */
408 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
409 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
410 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
411 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
412 .capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
413 .workMode = kSCG_SysOscModeExt, /* Use external clock */
414};
415const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
416 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
417 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
418 .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
419 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
420};
421const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
422 .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower, /* Enable FIRC clock, Enable FIRC in low power mode */
423 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
424 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
425 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
426 .trimConfig = NULL, /* Fast IRC Trim disabled */
427};
428const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR = {
429 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
430 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
431 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
432 .div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
433 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
434 .prediv = 0, /* Divided by 1 */
435 .mult = 0, /* Multiply Factor is 16 */
436};
437/*******************************************************************************
438 * Code for BOARD_BootClockVLPR configuration
439 ******************************************************************************/
440void BOARD_BootClockVLPR(void)
441{
442 /* Init FIRC. */
443 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
444 /* Init SIRC. */
445 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
446 /* Allow SMC all power modes. */
447 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
448 /* Set VLPR power mode. */
449 SMC_SetPowerModeVlpr(SMC);
450 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
451 {
452 }
453 /* Set SystemCoreClock variable. */
454 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
455}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.h
new file mode 100644
index 000000000..463e1a776
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/clock_config.h
@@ -0,0 +1,164 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 32768U /*!< Board xtal0 frequency in Hz */
22
23/*******************************************************************************
24 ************************ BOARD_InitBootClocks function ************************
25 ******************************************************************************/
26
27#if defined(__cplusplus)
28extern "C" {
29#endif /* __cplusplus*/
30
31/*!
32 * @brief This function executes default configuration of clocks.
33 *
34 */
35void BOARD_InitBootClocks(void);
36
37#if defined(__cplusplus)
38}
39#endif /* __cplusplus*/
40
41/*******************************************************************************
42 ********************** Configuration BOARD_BootClockRUN ***********************
43 ******************************************************************************/
44/*******************************************************************************
45 * Definitions for BOARD_BootClockRUN configuration
46 ******************************************************************************/
47#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
48
49/*! @brief SCG set for BOARD_BootClockRUN configuration.
50 */
51extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
52/*! @brief System OSC set for BOARD_BootClockRUN configuration.
53 */
54extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
55/*! @brief SIRC set for BOARD_BootClockRUN configuration.
56 */
57extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
58/*! @brief FIRC set for BOARD_BootClockRUN configuration.
59 */
60extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
61extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
62/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
63 */
64
65/*******************************************************************************
66 * API for BOARD_BootClockRUN configuration
67 ******************************************************************************/
68#if defined(__cplusplus)
69extern "C" {
70#endif /* __cplusplus*/
71
72/*!
73 * @brief This function executes configuration of clocks.
74 *
75 */
76void BOARD_BootClockRUN(void);
77
78#if defined(__cplusplus)
79}
80#endif /* __cplusplus*/
81
82/*******************************************************************************
83 ********************* Configuration BOARD_BootClockHSRUN **********************
84 ******************************************************************************/
85/*******************************************************************************
86 * Definitions for BOARD_BootClockHSRUN configuration
87 ******************************************************************************/
88#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
89
90/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
91 */
92extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
93/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
94 */
95extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
96/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
97 */
98extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
99/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
100 */
101extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
102extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
103/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
104 */
105
106/*******************************************************************************
107 * API for BOARD_BootClockHSRUN configuration
108 ******************************************************************************/
109#if defined(__cplusplus)
110extern "C" {
111#endif /* __cplusplus*/
112
113/*!
114 * @brief This function executes configuration of clocks.
115 *
116 */
117void BOARD_BootClockHSRUN(void);
118
119#if defined(__cplusplus)
120}
121#endif /* __cplusplus*/
122
123/*******************************************************************************
124 ********************* Configuration BOARD_BootClockVLPR ***********************
125 ******************************************************************************/
126/*******************************************************************************
127 * Definitions for BOARD_BootClockVLPR configuration
128 ******************************************************************************/
129#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 8000000U /*!< Core clock frequency: 8000000Hz */
130
131/*! @brief SCG set for BOARD_BootClockVLPR configuration.
132 */
133extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
134/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
135 */
136extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
137/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
138 */
139extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
140/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
141 */
142extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
143extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
144/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
145 */
146
147/*******************************************************************************
148 * API for BOARD_BootClockVLPR configuration
149 ******************************************************************************/
150#if defined(__cplusplus)
151extern "C" {
152#endif /* __cplusplus*/
153
154/*!
155 * @brief This function executes configuration of clocks.
156 *
157 */
158void BOARD_BootClockVLPR(void);
159
160#if defined(__cplusplus)
161}
162#endif /* __cplusplus*/
163
164#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.c
new file mode 100644
index 000000000..892f163b1
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v6.0
17processor: K32L2A31xxxxA
18package_id: K32L2A31VLL1A
19mcu_data: ksdk2_0
20processor_version: 0.0.0
21functionalGroups:
22- name: BOARD_InitPeripherals
23 called_from_default_init: true
24 selectedCore: core0
25 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
26
27/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
28component:
29- type: 'system'
30- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
31- global_system_definitions: []
32 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
33
34/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
35component:
36- type: 'msg'
37- type_id: 'msg_6e2baaf3b97dbeef01c0043275f9a0e7'
38- global_messages: []
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40/* clang-format on */
41
42/***********************************************************************************************************************
43 * Included files
44 **********************************************************************************************************************/
45#include "peripherals.h"
46
47/***********************************************************************************************************************
48 * Initialization functions
49 **********************************************************************************************************************/
50void BOARD_InitPeripherals(void)
51{
52}
53
54/***********************************************************************************************************************
55 * BOARD_InitBootPeripherals function
56 **********************************************************************************************************************/
57void BOARD_InitBootPeripherals(void)
58{
59 BOARD_InitPeripherals();
60}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.h
new file mode 100644
index 000000000..96cfdfdd2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c
new file mode 100644
index 000000000..0e179a854
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.c
@@ -0,0 +1,901 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16!!GlobalInfo
17product: Pins v6.0
18processor: K32L2A31xxxxA
19package_id: K32L2A31VLL1A
20mcu_data: ksdk2_0
21processor_version: 0.0.0
22pin_labels:
23- {pin_num: '1', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, label: 'U2[3]/INT1_21002', identifier: GYRO_INT1}
24- {pin_num: '2', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, label: 'U2[2]/INT2_21002', identifier: GYRO_INT2}
25- {pin_num: '3', pin_signal: ADC0_SE18/PTE2/LLWU_P1/LPSPI1_SCK/LPUART1_CTS_b/LPI2C1_SDAS, label: 'J2[5]'}
26- {pin_num: '4', pin_signal: ADC0_SE19/PTE3/LPSPI1_SIN/LPUART1_RTS_b/LPI2C1_SCLS, label: 'J2[7]'}
27- {pin_num: '5', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, label: BUTTON1, identifier: SW3}
28- {pin_num: '6', pin_signal: PTE5/LPSPI1_PCS1, label: 'U10[9]/INT2_8700', identifier: ACCEL_INT2}
29- {pin_num: '7', pin_signal: PTE6/LLWU_P16/LPSPI1_PCS2/USB_SOF_OUT, label: 'J2[9]'}
30- {pin_num: '8', pin_signal: VDD8, label: 'J17[2]/P3V3_K32L2A'}
31- {pin_num: '30', pin_signal: VDD31, label: 'J17[2]/P3V3_K32L2A'}
32- {pin_num: '22', pin_signal: VDDA, label: 'J17[2]/P3V3_K32L2A'}
33- {pin_num: '48', pin_signal: VDD53, label: 'J17[2]/P3V3_K32L2A'}
34- {pin_num: '75', pin_signal: VDD82, label: 'J17[2]/P3V3_K32L2A'}
35- {pin_num: '89', pin_signal: VDD98, label: 'J17[2]/P3V3_K32L2A'}
36- {pin_num: '9', pin_signal: VSS9, label: GND}
37- {pin_num: '25', pin_signal: VSSA, label: GND}
38- {pin_num: '29', pin_signal: VSS30, label: GND}
39- {pin_num: '49', pin_signal: VSS54, label: GND}
40- {pin_num: '74', pin_signal: VSS81, label: GND}
41- {pin_num: '88', pin_signal: VSS97, label: GND}
42- {pin_num: '11', pin_signal: USB0_DM, label: 'J10[2]/K32L2A_USB_DN', identifier: USB_DN}
43- {pin_num: '10', pin_signal: USB0_DP, label: 'J10[3]/K32L2A_USB_DP', identifier: USB_DP}
44- {pin_num: '12', pin_signal: VOUT33, label: TP11/VOUT33}
45- {pin_num: '13', pin_signal: VREGIN, label: P5V_K32L2A, identifier: VREGIN}
46- {pin_num: '14', pin_signal: ADC0_DP1/ADC0_SE1/PTE16/LPSPI0_PCS0/LPUART2_TX/TPM0_CLKIN/LPSPI1_PCS3/FXIO0_D0, label: 'J2[11]/FXIO_D0'}
47- {pin_num: '15', pin_signal: ADC0_DM1/ADC0_SE5a/PTE17/LLWU_P19/LPSPI0_SCK/LPUART2_RX/TPM1_CLKIN/LPTMR0_ALT3/LPTMR1_ALT3/FXIO0_D1, label: 'J2[13]/FXIO_D1'}
48- {pin_num: '16', pin_signal: ADC0_DP2/ADC0_SE2/PTE18/LLWU_P20/LPSPI0_SOUT/LPUART2_CTS_b/LPI2C0_SDA/FXIO0_D2, label: 'J2[15]/FXIO_D2'}
49- {pin_num: '17', pin_signal: ADC0_DM2/ADC0_SE6a/PTE19/LPSPI0_SIN/LPUART2_RTS_b/LPI2C0_SCL/FXIO0_D3, label: 'J2[17]/FXIO_D3'}
50- {pin_num: '18', pin_signal: ADC0_DP0/ADC0_SE0/PTE20/LPSPI2_SCK/TPM1_CH0/LPUART0_TX/FXIO0_D4, label: 'J4[1]/DIFF_ADC0_DP0/FXIO_D4'}
51- {pin_num: '19', pin_signal: ADC0_DM0/ADC0_SE4a/PTE21/LPSPI2_SOUT/TPM1_CH1/LPUART0_RX/FXIO0_D5, label: 'J4[3]/DIFF_ADC0_DM0/FXIO_D5'}
52- {pin_num: '20', pin_signal: ADC0_DP3/ADC0_SE3/PTE22/LPSPI2_SIN/TPM2_CH0/LPUART2_TX/FXIO0_D6, label: 'J4[5]/DIFF_ADC0_DP3/FXIO_D6'}
53- {pin_num: '21', pin_signal: ADC0_DM3/ADC0_SE7a/PTE23/LPSPI2_PCS0/TPM2_CH1/LPUART2_RX/FXIO0_D7, label: 'J4[7]/DIFF_ADC0_DM3/FXIO_D7'}
54- {pin_num: '23', pin_signal: VREFH/VREF_OUT, label: 'J17[2]/P3V3_K32L2A'}
55- {pin_num: '24', pin_signal: VREFL, label: GND}
56- {pin_num: '26', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, label: LEDRGB_RED, identifier: LED_RED}
57- {pin_num: '27', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23/CMP0_IN4/PTE30/EMVSIM0_RST/TPM0_CH3/TPM1_CLKIN, label: 'J4[11]/DAC0_OUT'}
58- {pin_num: '28', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, label: LEDRGB_BLUE, identifier: LED_BLUE}
59- {pin_num: '31', pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, label: 'U2[11]/U10[4]/ACCEL_I2C0_SCL', identifier: ACCEL_SCL;GYRO_SCL}
60- {pin_num: '32', pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, label: 'U2[12]/U10[6]/ACCEL_I2C0_SDA', identifier: ACCEL_SDA;GYRO_SDA}
61- {pin_num: '33', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, label: 'U10[16]/U11[2]/ACCEL_RST', identifier: ACCEL_RST;GYRO_RST}
62- {pin_num: '34', pin_signal: TSI0_CH1/PTA0/LPUART0_CTS_b/TPM0_CH5/LPI2C0_SDAS/SWD_CLK, label: 'J11[4]/U5[11]/K32L2A_SWD_CLK/SWD_CLK_TGTMCU'}
63- {pin_num: '35', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, label: TSI_ELECTRODE1/TSI0_CH2, identifier: TSI_ELECTRODE_1}
64- {pin_num: '36', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, label: TSI_ELECTRODE2/TSI0_CH3, identifier: TSI_ELECTRODE_2}
65- {pin_num: '37', pin_signal: TSI0_CH4/PTA3/LPI2C1_SCL/TPM0_CH0/LPUART0_RTS_b/SWD_DIO, label: 'J11[2]/U5[3]/SWD_DIO_TGTMCU'}
66- {pin_num: '38', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, label: BUTTON2, identifier: SW2}
67- {pin_num: '39', pin_signal: PTA5/USB_CLKIN/TPM0_CH2/LPI2C2_HREQ, label: 'J3[1]'}
68- {pin_num: '40', pin_signal: PTA6/TPM0_CH3, label: 'J3[3]'}
69- {pin_num: '41', pin_signal: PTA7/LPSPI0_PCS3/TPM0_CH4/LPI2C2_SDAS, label: 'J3[5]'}
70- {pin_num: '42', pin_signal: PTA12/TPM1_CH0/LPI2C2_SCL, label: 'J2[20]/D15/I2C2_SCL'}
71- {pin_num: '43', pin_signal: PTA13/LLWU_P4/TPM1_CH1/LPI2C2_SDA, label: 'J2[18]/D14/I2C2_SDA'}
72- {pin_num: '44', pin_signal: PTA14/LPSPI0_PCS0/LPUART0_TX/LPI2C2_SCL, label: 'J3[7]'}
73- {pin_num: '45', pin_signal: PTA15/LPSPI0_SCK/LPUART0_RX, label: 'J3[9]'}
74- {pin_num: '46', pin_signal: PTA16/LPSPI0_SOUT/LPUART0_CTS_b, label: 'J3[11]'}
75- {pin_num: '47', pin_signal: ADC0_SE22/PTA17/LPSPI0_SIN/LPUART0_RTS_b, label: 'J3[13]'}
76- {pin_num: '50', pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, label: 'Y1[1]/EXTAL_32KHZ', identifier: EXTAL0}
77- {pin_num: '51', pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, label: 'Y1[2]/XTAL_32KHZ', identifier: XTAL0}
78- {pin_num: '52', pin_signal: PTA20/LPI2C0_SCLS/TPM2_CLKIN/RESET_b, label: 'J3[6]/J11[10]/U7[21]/RST_K20D50_B'}
79- {pin_num: '53', pin_signal: ADC0_SE8/TSI0_CH0/PTB0/LLWU_P5/LPI2C0_SCL/TPM1_CH0/FXIO0_D8, label: 'J4[2]/A0/ADC0_SE8/FXIO_D8'}
80- {pin_num: '54', pin_signal: ADC0_SE9/TSI0_CH6/PTB1/LPI2C0_SDA/TPM1_CH1/FXIO0_D9, label: 'J4[4]/A1/ADC0_SE9/FXIO_D9'}
81- {pin_num: '55', pin_signal: ADC0_SE12/TSI0_CH7/PTB2/LPI2C0_SCL/TPM2_CH0/LPUART0_RTS_b/FXIO0_D10, label: 'J1[6]/D2/FXIO_D10'}
82- {pin_num: '56', pin_signal: ADC0_SE13/TSI0_CH8/PTB3/LPI2C0_SDA/TPM2_CH1/LPSPI1_PCS3/LPUART0_CTS_b/FXIO0_D11, label: 'J4[8]/A3/ADC0_SE13/FXIO_D11'}
83- {pin_num: '57', pin_signal: PTB7/LPSPI1_PCS1, label: 'U7[31]/OpenSDA GPIO'}
84- {pin_num: '58', pin_signal: PTB8/LPSPI1_PCS0/FXIO0_D12, label: 'J3[15]/FXIO_D12'}
85- {pin_num: '59', pin_signal: PTB9/LPSPI1_SCK/FXIO0_D13, label: 'J1[8]/D3/FXIO_D13'}
86- {pin_num: '60', pin_signal: PTB10/LPSPI1_PCS0/FXIO0_D14, label: 'J1[10]/D4/FXIO_D14'}
87- {pin_num: '61', pin_signal: PTB11/LPSPI1_SCK/TPM2_CLKIN/FXIO0_D15, label: 'J1[12]/D5/FXIO_D15'}
88- {pin_num: '62', pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, label: 'J1[2]/U7[25]/D0/UART0_RX/FXIO_D16/UART1_RX_TGTMCU',
89 identifier: DEBUG_UART_RX}
90- {pin_num: '63', pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, label: 'J1[4]/U7[24]/D1/UART0_TX/FXIO_D17/UART1_TX_TGTMCU',
91 identifier: DEBUG_UART_TX}
92- {pin_num: '64', pin_signal: TSI0_CH11/PTB18/TPM2_CH0/LPI2C1_HREQ/FXIO0_D18, label: 'J1[1]/FXIO_D18'}
93- {pin_num: '65', pin_signal: TSI0_CH12/PTB19/TPM2_CH1/LPSPI2_PCS1/FXIO0_D19, label: 'J1[3]/FXIO_D19'}
94- {pin_num: '66', pin_signal: PTB20/LPSPI2_PCS0/CMP0_OUT, label: 'J20[4]/SPI2_PCS0'}
95- {pin_num: '67', pin_signal: PTB21/LPSPI2_SCK/CMP1_OUT, label: 'J20[5]/SPI2_SCK'}
96- {pin_num: '68', pin_signal: PTB22/LPSPI2_SOUT, label: 'J20[6]/SPI2_SOUT'}
97- {pin_num: '69', pin_signal: PTB23/LPSPI2_SIN, label: 'J20[7]/SPI2_SIN'}
98- {pin_num: '70', pin_signal: ADC0_SE14/TSI0_CH13/PTC0/LPSPI2_PCS1/USB_SOF_OUT/CMP0_OUT, label: 'J1[5]'}
99- {pin_num: '71', pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/LPI2C1_SCL/LPUART1_RTS_b/TPM0_CH0, label: 'J4[12]/A5/ADC0_SE15/I2C1_SCL'}
100- {pin_num: '72', pin_signal: ADC0_SE11/CMP1_IN0/TSI0_CH15/PTC2/LPI2C1_SDA/LPUART1_CTS_b/TPM0_CH1, label: 'J4[10]/A4/ADC0_SE11/I2C1_SDA'}
101- {pin_num: '73', pin_signal: CMP1_IN1/PTC3/LLWU_P7/LPSPI0_PCS1/LPUART1_RX/TPM0_CH2/CLKOUT, label: 'J4[6]/A2/CMP1_IN1/SPI0_PCS1'}
102- {pin_num: '76', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, label: LEDRGB_GREEN, identifier: LED_GREEN}
103- {pin_num: '77', pin_signal: PTC5/LLWU_P9/LPSPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/CMP0_OUT, label: 'J4[9]/CMP0_OUT'}
104- {pin_num: '78', pin_signal: CMP0_IN0/PTC6/LLWU_P10/LPSPI0_SOUT, label: 'J20[3]'}
105- {pin_num: '79', pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, label: 'J1[11]/SOF_OUT/FXIO_D20', identifier: SOF_OUT}
106- {pin_num: '80', pin_signal: CMP0_IN2/PTC8/LPI2C0_SCL/TPM0_CH4/FXIO0_D21, label: 'J1[7]/FXIO_D21'}
107- {pin_num: '81', pin_signal: CMP0_IN3/PTC9/LPI2C0_SDA/TPM0_CH5/FXIO0_D22, label: 'J1[9]/FXIO_D22'}
108- {pin_num: '82', pin_signal: PTC10/LPI2C1_SCL/FXIO0_D23, label: 'J1[13]/FXIO_D23'}
109- {pin_num: '83', pin_signal: PTC11/LLWU_P11/LPI2C1_SDA, label: 'J1[15]'}
110- {pin_num: '84', pin_signal: PTC12/LPI2C1_SCLS/TPM0_CLKIN, label: 'J1[14]/D6'}
111- {pin_num: '85', pin_signal: PTC13/LPI2C1_SDAS/TPM1_CLKIN, label: 'J1[16]/D7'}
112- {pin_num: '86', pin_signal: PTC14/EMVSIM0_CLK, label: 'JP1[3]/EMVSIM_CLK'}
113- {pin_num: '87', pin_signal: PTC15/EMVSIM0_RST, label: 'JP1[4]/EMVSIM_RST'}
114- {pin_num: '90', pin_signal: PTC16/EMVSIM0_VCCEN, label: 'JP1[5]/EMVSIM_VCCEN'}
115- {pin_num: '91', pin_signal: PTC17/EMVSIM0_IO/LPSPI0_PCS3, label: 'JP1[6]/EMVSIM_IO'}
116- {pin_num: '92', pin_signal: PTC18/EMVSIM0_PD/LPSPI0_PCS2, label: 'JP1[7]/EMVSIM_PD'}
117- {pin_num: '93', pin_signal: PTD0/LLWU_P12/LPSPI0_PCS0/LPUART2_RTS_b/TPM0_CH0/FXIO0_D0, label: 'J2[6]/D10/SPI0_PCS0'}
118- {pin_num: '94', pin_signal: ADC0_SE5b/PTD1/LPSPI0_SCK/LPUART2_CTS_b/TPM0_CH1/FXIO0_D1, label: 'J2[12]/D13/SPI0_SCK'}
119- {pin_num: '95', pin_signal: PTD2/LLWU_P13/LPSPI0_SOUT/LPUART2_RX/TPM0_CH2/FXIO0_D2, label: 'J2[8]/D11/SPI0_SOUT'}
120- {pin_num: '96', pin_signal: PTD3/LPSPI0_SIN/LPUART2_TX/TPM0_CH3/FXIO0_D3, label: 'J2[10]/D12/SPI0_SIN'}
121- {pin_num: '97', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, label: 'U10[11]/INT1_8700', identifier: ACCEL_INT1}
122- {pin_num: '98', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, label: 'Q1[1]/LIGHT_SENSOR', identifier: LIGHT_SENSOR}
123- {pin_num: '99', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/LPSPI1_SOUT/LPUART0_RX/FXIO0_D6, label: 'J2[2]/D8'}
124- {pin_num: '100', pin_signal: PTD7/LPSPI1_SIN/LPUART0_TX/FXIO0_D7, label: 'J2[4]/D9'}
125 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
126 */
127/* clang-format on */
128
129#include "fsl_common.h"
130#include "fsl_port.h"
131#include "fsl_gpio.h"
132#include "pin_mux.h"
133
134/* FUNCTION ************************************************************************************************************
135 *
136 * Function Name : BOARD_InitBootPins
137 * Description : Calls initialization functions.
138 *
139 * END ****************************************************************************************************************/
140void BOARD_InitBootPins(void)
141{
142 BOARD_InitPins();
143 BOARD_InitDEBUG_UARTPins();
144}
145
146/* clang-format off */
147/*
148 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
149BOARD_InitPins:
150- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
151- pin_list: []
152 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
153 */
154/* clang-format on */
155
156/* FUNCTION ************************************************************************************************************
157 *
158 * Function Name : BOARD_InitPins
159 * Description : Configures pin routing and optionally pin electrical features.
160 *
161 * END ****************************************************************************************************************/
162void BOARD_InitPins(void)
163{
164}
165
166/* clang-format off */
167/*
168 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
169BOARD_InitBUTTONsPins:
170- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
171- pin_list:
172 - {pin_num: '5', peripheral: GPIOE, signal: 'GPIO, 4', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, direction: INPUT, slew_rate: slow, open_drain: disable, pull_select: up,
173 pull_enable: enable}
174 - {pin_num: '38', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, direction: INPUT, slew_rate: slow, open_drain: disable,
175 pull_select: down, pull_enable: disable}
176 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
177 */
178/* clang-format on */
179
180/* FUNCTION ************************************************************************************************************
181 *
182 * Function Name : BOARD_InitBUTTONsPins
183 * Description : Configures pin routing and optionally pin electrical features.
184 *
185 * END ****************************************************************************************************************/
186void BOARD_InitBUTTONsPins(void)
187{
188 /* Clock Gate Control: Clock enabled */
189 CLOCK_EnableClock(kCLOCK_PortA);
190 /* Clock Gate Control: Clock enabled */
191 CLOCK_EnableClock(kCLOCK_PortE);
192
193 gpio_pin_config_t SW2_config = {
194 .pinDirection = kGPIO_DigitalInput,
195 .outputLogic = 0U
196 };
197 /* Initialize GPIO functionality on pin PTA4 (pin 38) */
198 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
199
200 gpio_pin_config_t SW3_config = {
201 .pinDirection = kGPIO_DigitalInput,
202 .outputLogic = 0U
203 };
204 /* Initialize GPIO functionality on pin PTE4 (pin 5) */
205 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
206
207 /* PORTA4 (pin 38) is configured as PTA4 */
208 PORT_SetPinMux(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_MuxAsGpio);
209
210 PORTA->PCR[4] =
211 ((PORTA->PCR[4] &
212 /* Mask bits to zero which are setting */
213 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
214
215 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
216 * field is set. */
217 | PORT_PCR_PS(kPORT_PullDown)
218
219 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
220 | PORT_PCR_PE(kPORT_PullDisable)
221
222 /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
223 * a digital output. */
224 | PORT_PCR_SRE(kPORT_SlowSlewRate)
225
226 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
227 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
228
229 const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
230 kPORT_PullUp,
231 /* Slow slew rate is configured */
232 kPORT_SlowSlewRate,
233 /* Passive filter is disabled */
234 kPORT_PassiveFilterDisable,
235 /* Open drain is disabled */
236 kPORT_OpenDrainDisable,
237 /* Low drive strength is configured */
238 kPORT_LowDriveStrength,
239 /* Pin is configured as PTE4 */
240 kPORT_MuxAsGpio,
241 /* Pin Control Register fields [15:0] are not locked */
242 kPORT_UnlockRegister};
243 /* PORTE4 (pin 5) is configured as PTE4 */
244 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
245}
246
247/* clang-format off */
248/*
249 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
250BOARD_InitLEDsPins:
251- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
252- pin_list:
253 - {pin_num: '26', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, direction: OUTPUT, gpio_init_state: 'true',
254 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
255 - {pin_num: '28', peripheral: GPIOE, signal: 'GPIO, 31', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, direction: OUTPUT, gpio_init_state: 'true',
256 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
257 - {pin_num: '76', peripheral: GPIOC, signal: 'GPIO, 4', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, direction: OUTPUT, gpio_init_state: 'true',
258 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
259 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
260 */
261/* clang-format on */
262
263/* FUNCTION ************************************************************************************************************
264 *
265 * Function Name : BOARD_InitLEDsPins
266 * Description : Configures pin routing and optionally pin electrical features.
267 *
268 * END ****************************************************************************************************************/
269void BOARD_InitLEDsPins(void)
270{
271 /* Clock Gate Control: Clock enabled */
272 CLOCK_EnableClock(kCLOCK_PortC);
273 /* Clock Gate Control: Clock enabled */
274 CLOCK_EnableClock(kCLOCK_PortE);
275
276 gpio_pin_config_t LED_GREEN_config = {
277 .pinDirection = kGPIO_DigitalOutput,
278 .outputLogic = 1U
279 };
280 /* Initialize GPIO functionality on pin PTC4 (pin 76) */
281 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
282
283 gpio_pin_config_t LED_RED_config = {
284 .pinDirection = kGPIO_DigitalOutput,
285 .outputLogic = 1U
286 };
287 /* Initialize GPIO functionality on pin PTE29 (pin 26) */
288 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
289
290 gpio_pin_config_t LED_BLUE_config = {
291 .pinDirection = kGPIO_DigitalOutput,
292 .outputLogic = 1U
293 };
294 /* Initialize GPIO functionality on pin PTE31 (pin 28) */
295 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
296
297 /* PORTC4 (pin 76) is configured as PTC4 */
298 PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio);
299
300 PORTC->PCR[4] =
301 ((PORTC->PCR[4] &
302 /* Mask bits to zero which are setting */
303 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
304
305 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
306 * field is set. */
307 | PORT_PCR_PS(kPORT_PullDown)
308
309 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
310 | PORT_PCR_PE(kPORT_PullDisable)
311
312 /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
313 * a digital output. */
314 | PORT_PCR_SRE(kPORT_SlowSlewRate)
315
316 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
317 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
318
319 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
320 kPORT_PullDisable,
321 /* Slow slew rate is configured */
322 kPORT_SlowSlewRate,
323 /* Passive filter is disabled */
324 kPORT_PassiveFilterDisable,
325 /* Open drain is disabled */
326 kPORT_OpenDrainDisable,
327 /* Low drive strength is configured */
328 kPORT_LowDriveStrength,
329 /* Pin is configured as PTE29 */
330 kPORT_MuxAsGpio,
331 /* Pin Control Register fields [15:0] are not locked */
332 kPORT_UnlockRegister};
333 /* PORTE29 (pin 26) is configured as PTE29 */
334 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
335
336 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
337 kPORT_PullDisable,
338 /* Slow slew rate is configured */
339 kPORT_SlowSlewRate,
340 /* Passive filter is disabled */
341 kPORT_PassiveFilterDisable,
342 /* Open drain is disabled */
343 kPORT_OpenDrainDisable,
344 /* Low drive strength is configured */
345 kPORT_LowDriveStrength,
346 /* Pin is configured as PTE31 */
347 kPORT_MuxAsGpio,
348 /* Pin Control Register fields [15:0] are not locked */
349 kPORT_UnlockRegister};
350 /* PORTE31 (pin 28) is configured as PTE31 */
351 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
352}
353
354/* clang-format off */
355/*
356 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
357BOARD_InitTOUCHPins:
358- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
359- pin_list:
360 - {pin_num: '35', peripheral: TSI0, signal: 'CH, 2', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
361 - {pin_num: '36', peripheral: TSI0, signal: 'CH, 3', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
362 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
363 */
364/* clang-format on */
365
366/* FUNCTION ************************************************************************************************************
367 *
368 * Function Name : BOARD_InitTOUCHPins
369 * Description : Configures pin routing and optionally pin electrical features.
370 *
371 * END ****************************************************************************************************************/
372void BOARD_InitTOUCHPins(void)
373{
374 /* Clock Gate Control: Clock enabled */
375 CLOCK_EnableClock(kCLOCK_PortA);
376
377 const port_pin_config_t TSI_ELECTRODE_1 = {/* Internal pull-up/down resistor is disabled */
378 kPORT_PullDisable,
379 /* Fast slew rate is configured */
380 kPORT_FastSlewRate,
381 /* Passive filter is disabled */
382 kPORT_PassiveFilterDisable,
383 /* Open drain is disabled */
384 kPORT_OpenDrainDisable,
385 /* Low drive strength is configured */
386 kPORT_LowDriveStrength,
387 /* Pin is configured as TSI0_CH2 */
388 kPORT_PinDisabledOrAnalog,
389 /* Pin Control Register fields [15:0] are not locked */
390 kPORT_UnlockRegister};
391 /* PORTA1 (pin 35) is configured as TSI0_CH2 */
392 PORT_SetPinConfig(BOARD_TSI_ELECTRODE_1_PORT, BOARD_TSI_ELECTRODE_1_PIN, &TSI_ELECTRODE_1);
393
394 const port_pin_config_t TSI_ELECTRODE_2 = {/* Internal pull-up/down resistor is disabled */
395 kPORT_PullDisable,
396 /* Fast slew rate is configured */
397 kPORT_FastSlewRate,
398 /* Passive filter is disabled */
399 kPORT_PassiveFilterDisable,
400 /* Open drain is disabled */
401 kPORT_OpenDrainDisable,
402 /* Low drive strength is configured */
403 kPORT_LowDriveStrength,
404 /* Pin is configured as TSI0_CH3 */
405 kPORT_PinDisabledOrAnalog,
406 /* Pin Control Register fields [15:0] are not locked */
407 kPORT_UnlockRegister};
408 /* PORTA2 (pin 36) is configured as TSI0_CH3 */
409 PORT_SetPinConfig(BOARD_TSI_ELECTRODE_2_PORT, BOARD_TSI_ELECTRODE_2_PIN, &TSI_ELECTRODE_2);
410}
411
412/* clang-format off */
413/*
414 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
415BOARD_InitLIGHT_SENSORPins:
416- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
417- pin_list:
418 - {pin_num: '98', peripheral: ADC0, signal: 'SE, 6b', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, slew_rate: fast, open_drain: disable,
419 pull_select: down, pull_enable: disable}
420 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
421 */
422/* clang-format on */
423
424/* FUNCTION ************************************************************************************************************
425 *
426 * Function Name : BOARD_InitLIGHT_SENSORPins
427 * Description : Configures pin routing and optionally pin electrical features.
428 *
429 * END ****************************************************************************************************************/
430void BOARD_InitLIGHT_SENSORPins(void)
431{
432 /* Clock Gate Control: Clock enabled */
433 CLOCK_EnableClock(kCLOCK_PortD);
434
435 /* PORTD5 (pin 98) is configured as ADC0_SE6b */
436 PORT_SetPinMux(BOARD_LIGHT_SENSOR_PORT, BOARD_LIGHT_SENSOR_PIN, kPORT_PinDisabledOrAnalog);
437
438 PORTD->PCR[5] =
439 ((PORTD->PCR[5] &
440 /* Mask bits to zero which are setting */
441 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
442
443 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
444 * field is set. */
445 | PORT_PCR_PS(kPORT_PullDown)
446
447 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
448 | PORT_PCR_PE(kPORT_PullDisable)
449
450 /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
451 * a digital output. */
452 | PORT_PCR_SRE(kPORT_FastSlewRate)
453
454 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
455 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
456}
457
458/* clang-format off */
459/*
460 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
461BOARD_InitUSBPins:
462- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
463- pin_list:
464 - {pin_num: '11', peripheral: USB0, signal: DM, pin_signal: USB0_DM}
465 - {pin_num: '10', peripheral: USB0, signal: DP, pin_signal: USB0_DP}
466 - {pin_num: '13', peripheral: USB0, signal: VREGIN, pin_signal: VREGIN}
467 - {pin_num: '79', peripheral: USB0, signal: SOF_OUT, pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, slew_rate: fast, open_drain: disable, pull_select: down,
468 pull_enable: disable}
469 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
470 */
471/* clang-format on */
472
473/* FUNCTION ************************************************************************************************************
474 *
475 * Function Name : BOARD_InitUSBPins
476 * Description : Configures pin routing and optionally pin electrical features.
477 *
478 * END ****************************************************************************************************************/
479void BOARD_InitUSBPins(void)
480{
481 /* Clock Gate Control: Clock enabled */
482 CLOCK_EnableClock(kCLOCK_PortC);
483
484 const port_pin_config_t SOF_OUT = {/* Internal pull-up/down resistor is disabled */
485 kPORT_PullDisable,
486 /* Fast slew rate is configured */
487 kPORT_FastSlewRate,
488 /* Passive filter is disabled */
489 kPORT_PassiveFilterDisable,
490 /* Open drain is disabled */
491 kPORT_OpenDrainDisable,
492 /* Low drive strength is configured */
493 kPORT_LowDriveStrength,
494 /* Pin is configured as USB_SOF_OUT */
495 kPORT_MuxAlt3,
496 /* Pin Control Register fields [15:0] are not locked */
497 kPORT_UnlockRegister};
498 /* PORTC7 (pin 79) is configured as USB_SOF_OUT */
499 PORT_SetPinConfig(BOARD_SOF_OUT_PORT, BOARD_SOF_OUT_PIN, &SOF_OUT);
500}
501
502/* clang-format off */
503/*
504 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
505BOARD_InitDEBUG_UARTPins:
506- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
507- pin_list:
508 - {pin_num: '62', peripheral: LPUART0, signal: RX, pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, slew_rate: fast, open_drain: disable,
509 pull_select: down, pull_enable: disable}
510 - {pin_num: '63', peripheral: LPUART0, signal: TX, pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, direction: OUTPUT, slew_rate: fast,
511 open_drain: disable, pull_select: down, pull_enable: disable}
512 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
513 */
514/* clang-format on */
515
516/* FUNCTION ************************************************************************************************************
517 *
518 * Function Name : BOARD_InitDEBUG_UARTPins
519 * Description : Configures pin routing and optionally pin electrical features.
520 *
521 * END ****************************************************************************************************************/
522void BOARD_InitDEBUG_UARTPins(void)
523{
524 /* Clock Gate Control: Clock enabled */
525 CLOCK_EnableClock(kCLOCK_PortB);
526
527 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
528 kPORT_PullDisable,
529 /* Fast slew rate is configured */
530 kPORT_FastSlewRate,
531 /* Passive filter is disabled */
532 kPORT_PassiveFilterDisable,
533 /* Open drain is disabled */
534 kPORT_OpenDrainDisable,
535 /* Low drive strength is configured */
536 kPORT_LowDriveStrength,
537 /* Pin is configured as LPUART0_RX */
538 kPORT_MuxAlt3,
539 /* Pin Control Register fields [15:0] are not locked */
540 kPORT_UnlockRegister};
541 /* PORTB16 (pin 62) is configured as LPUART0_RX */
542 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
543
544 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
545 kPORT_PullDisable,
546 /* Fast slew rate is configured */
547 kPORT_FastSlewRate,
548 /* Passive filter is disabled */
549 kPORT_PassiveFilterDisable,
550 /* Open drain is disabled */
551 kPORT_OpenDrainDisable,
552 /* Low drive strength is configured */
553 kPORT_LowDriveStrength,
554 /* Pin is configured as LPUART0_TX */
555 kPORT_MuxAlt3,
556 /* Pin Control Register fields [15:0] are not locked */
557 kPORT_UnlockRegister};
558 /* PORTB17 (pin 63) is configured as LPUART0_TX */
559 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
560}
561
562/* clang-format off */
563/*
564 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
565BOARD_InitACCELPins:
566- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
567- pin_list:
568 - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: ACCEL_SDA, slew_rate: fast,
569 open_drain: enable, pull_select: down, pull_enable: disable}
570 - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: ACCEL_SCL, slew_rate: fast, open_drain: enable,
571 pull_select: down, pull_enable: disable}
572 - {pin_num: '97', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, direction: INPUT, slew_rate: fast,
573 open_drain: disable, pull_select: up, pull_enable: enable}
574 - {pin_num: '6', peripheral: GPIOE, signal: 'GPIO, 5', pin_signal: PTE5/LPSPI1_PCS1, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
575 - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: ACCEL_RST, direction: OUTPUT,
576 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
577 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
578 */
579/* clang-format on */
580
581/* FUNCTION ************************************************************************************************************
582 *
583 * Function Name : BOARD_InitACCELPins
584 * Description : Configures pin routing and optionally pin electrical features.
585 *
586 * END ****************************************************************************************************************/
587void BOARD_InitACCELPins(void)
588{
589 /* Clock Gate Control: Clock enabled */
590 CLOCK_EnableClock(kCLOCK_PortD);
591 /* Clock Gate Control: Clock enabled */
592 CLOCK_EnableClock(kCLOCK_PortE);
593
594 gpio_pin_config_t ACCEL_INT1_config = {
595 .pinDirection = kGPIO_DigitalInput,
596 .outputLogic = 0U
597 };
598 /* Initialize GPIO functionality on pin PTD4 (pin 97) */
599 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
600
601 gpio_pin_config_t ACCEL_INT2_config = {
602 .pinDirection = kGPIO_DigitalInput,
603 .outputLogic = 0U
604 };
605 /* Initialize GPIO functionality on pin PTE5 (pin 6) */
606 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
607
608 gpio_pin_config_t ACCEL_RST_config = {
609 .pinDirection = kGPIO_DigitalOutput,
610 .outputLogic = 0U
611 };
612 /* Initialize GPIO functionality on pin PTE26 (pin 33) */
613 GPIO_PinInit(BOARD_ACCEL_RST_GPIO, BOARD_ACCEL_RST_PIN, &ACCEL_RST_config);
614
615 /* PORTD4 (pin 97) is configured as PTD4 */
616 PORT_SetPinMux(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, kPORT_MuxAsGpio);
617
618 PORTD->PCR[4] =
619 ((PORTD->PCR[4] &
620 /* Mask bits to zero which are setting */
621 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
622
623 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE
624 * field is set. */
625 | (uint32_t)(kPORT_PullUp)
626
627 /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
628 * a digital output. */
629 | PORT_PCR_SRE(kPORT_FastSlewRate)
630
631 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
632 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
633
634 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
635 kPORT_PullDisable,
636 /* Fast slew rate is configured */
637 kPORT_FastSlewRate,
638 /* Passive filter is disabled */
639 kPORT_PassiveFilterDisable,
640 /* Open drain is enabled */
641 kPORT_OpenDrainEnable,
642 /* Low drive strength is configured */
643 kPORT_LowDriveStrength,
644 /* Pin is configured as LPI2C0_SCL */
645 kPORT_MuxAlt5,
646 /* Pin Control Register fields [15:0] are not locked */
647 kPORT_UnlockRegister};
648 /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
649 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
650
651 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
652 kPORT_PullDisable,
653 /* Fast slew rate is configured */
654 kPORT_FastSlewRate,
655 /* Passive filter is disabled */
656 kPORT_PassiveFilterDisable,
657 /* Open drain is enabled */
658 kPORT_OpenDrainEnable,
659 /* Low drive strength is configured */
660 kPORT_LowDriveStrength,
661 /* Pin is configured as LPI2C0_SDA */
662 kPORT_MuxAlt5,
663 /* Pin Control Register fields [15:0] are not locked */
664 kPORT_UnlockRegister};
665 /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
666 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
667
668 const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */
669 kPORT_PullDisable,
670 /* Slow slew rate is configured */
671 kPORT_SlowSlewRate,
672 /* Passive filter is disabled */
673 kPORT_PassiveFilterDisable,
674 /* Open drain is disabled */
675 kPORT_OpenDrainDisable,
676 /* Low drive strength is configured */
677 kPORT_LowDriveStrength,
678 /* Pin is configured as PTE26 */
679 kPORT_MuxAsGpio,
680 /* Pin Control Register fields [15:0] are not locked */
681 kPORT_UnlockRegister};
682 /* PORTE26 (pin 33) is configured as PTE26 */
683 PORT_SetPinConfig(BOARD_ACCEL_RST_PORT, BOARD_ACCEL_RST_PIN, &ACCEL_RST);
684
685 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
686 kPORT_PullUp,
687 /* Fast slew rate is configured */
688 kPORT_FastSlewRate,
689 /* Passive filter is disabled */
690 kPORT_PassiveFilterDisable,
691 /* Open drain is disabled */
692 kPORT_OpenDrainDisable,
693 /* Low drive strength is configured */
694 kPORT_LowDriveStrength,
695 /* Pin is configured as PTE5 */
696 kPORT_MuxAsGpio,
697 /* Pin Control Register fields [15:0] are not locked */
698 kPORT_UnlockRegister};
699 /* PORTE5 (pin 6) is configured as PTE5 */
700 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
701}
702
703/* clang-format off */
704/*
705 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
706BOARD_InitGYROPins:
707- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
708- pin_list:
709 - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: GYRO_SCL, slew_rate: fast, open_drain: enable,
710 pull_select: down, pull_enable: disable}
711 - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: GYRO_SDA, slew_rate: fast, open_drain: enable,
712 pull_select: down, pull_enable: disable}
713 - {pin_num: '1', peripheral: GPIOE, signal: 'GPIO, 0', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, direction: INPUT, slew_rate: fast,
714 open_drain: disable, pull_select: up, pull_enable: enable}
715 - {pin_num: '2', peripheral: GPIOE, signal: 'GPIO, 1', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, direction: INPUT, slew_rate: fast,
716 open_drain: disable, pull_select: up, pull_enable: enable}
717 - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: GYRO_RST, direction: OUTPUT, slew_rate: slow,
718 open_drain: disable, pull_select: down, pull_enable: disable}
719 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
720 */
721/* clang-format on */
722
723/* FUNCTION ************************************************************************************************************
724 *
725 * Function Name : BOARD_InitGYROPins
726 * Description : Configures pin routing and optionally pin electrical features.
727 *
728 * END ****************************************************************************************************************/
729void BOARD_InitGYROPins(void)
730{
731 /* Clock Gate Control: Clock enabled */
732 CLOCK_EnableClock(kCLOCK_PortE);
733
734 gpio_pin_config_t GYRO_INT1_config = {
735 .pinDirection = kGPIO_DigitalInput,
736 .outputLogic = 0U
737 };
738 /* Initialize GPIO functionality on pin PTE0 (pin 1) */
739 GPIO_PinInit(BOARD_GYRO_INT1_GPIO, BOARD_GYRO_INT1_PIN, &GYRO_INT1_config);
740
741 gpio_pin_config_t GYRO_INT2_config = {
742 .pinDirection = kGPIO_DigitalInput,
743 .outputLogic = 0U
744 };
745 /* Initialize GPIO functionality on pin PTE1 (pin 2) */
746 GPIO_PinInit(BOARD_GYRO_INT2_GPIO, BOARD_GYRO_INT2_PIN, &GYRO_INT2_config);
747
748 gpio_pin_config_t GYRO_RST_config = {
749 .pinDirection = kGPIO_DigitalOutput,
750 .outputLogic = 0U
751 };
752 /* Initialize GPIO functionality on pin PTE26 (pin 33) */
753 GPIO_PinInit(BOARD_GYRO_RST_GPIO, BOARD_GYRO_RST_PIN, &GYRO_RST_config);
754
755 const port_pin_config_t GYRO_INT1 = {/* Internal pull-up resistor is enabled */
756 kPORT_PullUp,
757 /* Fast slew rate is configured */
758 kPORT_FastSlewRate,
759 /* Passive filter is disabled */
760 kPORT_PassiveFilterDisable,
761 /* Open drain is disabled */
762 kPORT_OpenDrainDisable,
763 /* Low drive strength is configured */
764 kPORT_LowDriveStrength,
765 /* Pin is configured as PTE0 */
766 kPORT_MuxAsGpio,
767 /* Pin Control Register fields [15:0] are not locked */
768 kPORT_UnlockRegister};
769 /* PORTE0 (pin 1) is configured as PTE0 */
770 PORT_SetPinConfig(BOARD_GYRO_INT1_PORT, BOARD_GYRO_INT1_PIN, &GYRO_INT1);
771
772 const port_pin_config_t GYRO_INT2 = {/* Internal pull-up resistor is enabled */
773 kPORT_PullUp,
774 /* Fast slew rate is configured */
775 kPORT_FastSlewRate,
776 /* Passive filter is disabled */
777 kPORT_PassiveFilterDisable,
778 /* Open drain is disabled */
779 kPORT_OpenDrainDisable,
780 /* Low drive strength is configured */
781 kPORT_LowDriveStrength,
782 /* Pin is configured as PTE1 */
783 kPORT_MuxAsGpio,
784 /* Pin Control Register fields [15:0] are not locked */
785 kPORT_UnlockRegister};
786 /* PORTE1 (pin 2) is configured as PTE1 */
787 PORT_SetPinConfig(BOARD_GYRO_INT2_PORT, BOARD_GYRO_INT2_PIN, &GYRO_INT2);
788
789 const port_pin_config_t GYRO_SCL = {/* Internal pull-up/down resistor is disabled */
790 kPORT_PullDisable,
791 /* Fast slew rate is configured */
792 kPORT_FastSlewRate,
793 /* Passive filter is disabled */
794 kPORT_PassiveFilterDisable,
795 /* Open drain is enabled */
796 kPORT_OpenDrainEnable,
797 /* Low drive strength is configured */
798 kPORT_LowDriveStrength,
799 /* Pin is configured as LPI2C0_SCL */
800 kPORT_MuxAlt5,
801 /* Pin Control Register fields [15:0] are not locked */
802 kPORT_UnlockRegister};
803 /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
804 PORT_SetPinConfig(BOARD_GYRO_SCL_PORT, BOARD_GYRO_SCL_PIN, &GYRO_SCL);
805
806 const port_pin_config_t GYRO_SDA = {/* Internal pull-up/down resistor is disabled */
807 kPORT_PullDisable,
808 /* Fast slew rate is configured */
809 kPORT_FastSlewRate,
810 /* Passive filter is disabled */
811 kPORT_PassiveFilterDisable,
812 /* Open drain is enabled */
813 kPORT_OpenDrainEnable,
814 /* Low drive strength is configured */
815 kPORT_LowDriveStrength,
816 /* Pin is configured as LPI2C0_SDA */
817 kPORT_MuxAlt5,
818 /* Pin Control Register fields [15:0] are not locked */
819 kPORT_UnlockRegister};
820 /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
821 PORT_SetPinConfig(BOARD_GYRO_SDA_PORT, BOARD_GYRO_SDA_PIN, &GYRO_SDA);
822
823 const port_pin_config_t GYRO_RST = {/* Internal pull-up/down resistor is disabled */
824 kPORT_PullDisable,
825 /* Slow slew rate is configured */
826 kPORT_SlowSlewRate,
827 /* Passive filter is disabled */
828 kPORT_PassiveFilterDisable,
829 /* Open drain is disabled */
830 kPORT_OpenDrainDisable,
831 /* Low drive strength is configured */
832 kPORT_LowDriveStrength,
833 /* Pin is configured as PTE26 */
834 kPORT_MuxAsGpio,
835 /* Pin Control Register fields [15:0] are not locked */
836 kPORT_UnlockRegister};
837 /* PORTE26 (pin 33) is configured as PTE26 */
838 PORT_SetPinConfig(BOARD_GYRO_RST_PORT, BOARD_GYRO_RST_PIN, &GYRO_RST);
839}
840
841/* clang-format off */
842/*
843 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
844BOARD_InitOSCPins:
845- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
846- pin_list:
847 - {pin_num: '50', peripheral: SCG, signal: EXTAL0, pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
848 - {pin_num: '51', peripheral: SCG, signal: XTAL0, pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, slew_rate: fast, open_drain: disable, pull_select: down,
849 pull_enable: disable}
850 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
851 */
852/* clang-format on */
853
854/* FUNCTION ************************************************************************************************************
855 *
856 * Function Name : BOARD_InitOSCPins
857 * Description : Configures pin routing and optionally pin electrical features.
858 *
859 * END ****************************************************************************************************************/
860void BOARD_InitOSCPins(void)
861{
862 /* Clock Gate Control: Clock enabled */
863 CLOCK_EnableClock(kCLOCK_PortA);
864
865 const port_pin_config_t EXTAL0 = {/* Internal pull-up/down resistor is disabled */
866 kPORT_PullDisable,
867 /* Fast slew rate is configured */
868 kPORT_FastSlewRate,
869 /* Passive filter is disabled */
870 kPORT_PassiveFilterDisable,
871 /* Open drain is disabled */
872 kPORT_OpenDrainDisable,
873 /* Low drive strength is configured */
874 kPORT_LowDriveStrength,
875 /* Pin is configured as EXTAL0 */
876 kPORT_PinDisabledOrAnalog,
877 /* Pin Control Register fields [15:0] are not locked */
878 kPORT_UnlockRegister};
879 /* PORTA18 (pin 50) is configured as EXTAL0 */
880 PORT_SetPinConfig(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, &EXTAL0);
881
882 const port_pin_config_t XTAL0 = {/* Internal pull-up/down resistor is disabled */
883 kPORT_PullDisable,
884 /* Fast slew rate is configured */
885 kPORT_FastSlewRate,
886 /* Passive filter is disabled */
887 kPORT_PassiveFilterDisable,
888 /* Open drain is disabled */
889 kPORT_OpenDrainDisable,
890 /* Low drive strength is configured */
891 kPORT_LowDriveStrength,
892 /* Pin is configured as XTAL0 */
893 kPORT_PinDisabledOrAnalog,
894 /* Pin Control Register fields [15:0] are not locked */
895 kPORT_UnlockRegister};
896 /* PORTA19 (pin 51) is configured as XTAL0 */
897 PORT_SetPinConfig(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, &XTAL0);
898}
899/***********************************************************************************************************************
900 * EOF
901 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.h
new file mode 100644
index 000000000..6af625fcb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A31A/project_template/pin_mux.h
@@ -0,0 +1,268 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/*!
17 * @addtogroup pin_mux
18 * @{
19 */
20
21/***********************************************************************************************************************
22 * API
23 **********************************************************************************************************************/
24
25#if defined(__cplusplus)
26extern "C" {
27#endif
28
29/*!
30 * @brief Calls initialization functions.
31 *
32 */
33void BOARD_InitBootPins(void);
34
35/*!
36 * @brief Configures pin routing and optionally pin electrical features.
37 *
38 */
39void BOARD_InitPins(void);
40
41/*! @name PORTE4 (number 5), BUTTON1
42 @{ */
43#define BOARD_SW3_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
44#define BOARD_SW3_PORT PORTE /*!<@brief PORT device name: PORTE */
45#define BOARD_SW3_PIN 4U /*!<@brief PORTE pin index: 4 */
46 /* @} */
47
48/*! @name PORTA4 (number 38), BUTTON2
49 @{ */
50#define BOARD_SW2_FGPIO FGPIOA /*!<@brief FGPIO device name: FGPIOA */
51#define BOARD_SW2_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
52#define BOARD_SW2_PORT PORTA /*!<@brief PORT device name: PORTA */
53#define BOARD_SW2_PIN 4U /*!<@brief PORTA pin index: 4 */
54 /* @} */
55
56/*!
57 * @brief Configures pin routing and optionally pin electrical features.
58 *
59 */
60void BOARD_InitBUTTONsPins(void);
61
62/*! @name PORTE29 (number 26), LEDRGB_RED
63 @{ */
64#define BOARD_LED_RED_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
65#define BOARD_LED_RED_PORT PORTE /*!<@brief PORT device name: PORTE */
66#define BOARD_LED_RED_PIN 29U /*!<@brief PORTE pin index: 29 */
67 /* @} */
68
69/*! @name PORTE31 (number 28), LEDRGB_BLUE
70 @{ */
71#define BOARD_LED_BLUE_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
72#define BOARD_LED_BLUE_PORT PORTE /*!<@brief PORT device name: PORTE */
73#define BOARD_LED_BLUE_PIN 31U /*!<@brief PORTE pin index: 31 */
74 /* @} */
75
76/*! @name PORTC4 (number 76), LEDRGB_GREEN
77 @{ */
78#define BOARD_LED_GREEN_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
79#define BOARD_LED_GREEN_PORT PORTC /*!<@brief PORT device name: PORTC */
80#define BOARD_LED_GREEN_PIN 4U /*!<@brief PORTC pin index: 4 */
81 /* @} */
82
83/*!
84 * @brief Configures pin routing and optionally pin electrical features.
85 *
86 */
87void BOARD_InitLEDsPins(void);
88
89/*! @name PORTA1 (number 35), TSI_ELECTRODE1/TSI0_CH2
90 @{ */
91#define BOARD_TSI_ELECTRODE_1_PORT PORTA /*!<@brief PORT device name: PORTA */
92#define BOARD_TSI_ELECTRODE_1_PIN 1U /*!<@brief PORTA pin index: 1 */
93 /* @} */
94
95/*! @name PORTA2 (number 36), TSI_ELECTRODE2/TSI0_CH3
96 @{ */
97#define BOARD_TSI_ELECTRODE_2_PORT PORTA /*!<@brief PORT device name: PORTA */
98#define BOARD_TSI_ELECTRODE_2_PIN 2U /*!<@brief PORTA pin index: 2 */
99 /* @} */
100
101/*!
102 * @brief Configures pin routing and optionally pin electrical features.
103 *
104 */
105void BOARD_InitTOUCHPins(void);
106
107/*! @name PORTD5 (number 98), Q1[1]/LIGHT_SENSOR
108 @{ */
109#define BOARD_LIGHT_SENSOR_PORT PORTD /*!<@brief PORT device name: PORTD */
110#define BOARD_LIGHT_SENSOR_PIN 5U /*!<@brief PORTD pin index: 5 */
111 /* @} */
112
113/*!
114 * @brief Configures pin routing and optionally pin electrical features.
115 *
116 */
117void BOARD_InitLIGHT_SENSORPins(void);
118
119/*! @name USB0_DM (number 11), J10[2]/K32L2A_USB_DN
120 @{ */
121/* @} */
122
123/*! @name USB0_DP (number 10), J10[3]/K32L2A_USB_DP
124 @{ */
125/* @} */
126
127/*! @name VREGIN (number 13), P5V_K32L2A
128 @{ */
129/* @} */
130
131/*! @name PORTC7 (number 79), J1[11]/SOF_OUT/FXIO_D20
132 @{ */
133#define BOARD_SOF_OUT_PORT PORTC /*!<@brief PORT device name: PORTC */
134#define BOARD_SOF_OUT_PIN 7U /*!<@brief PORTC pin index: 7 */
135 /* @} */
136
137/*!
138 * @brief Configures pin routing and optionally pin electrical features.
139 *
140 */
141void BOARD_InitUSBPins(void);
142
143/*! @name PORTB16 (number 62), J1[2]/U7[25]/D0/UART0_RX/FXIO_D16/UART1_RX_TGTMCU
144 @{ */
145#define BOARD_DEBUG_UART_RX_PORT PORTB /*!<@brief PORT device name: PORTB */
146#define BOARD_DEBUG_UART_RX_PIN 16U /*!<@brief PORTB pin index: 16 */
147 /* @} */
148
149/*! @name PORTB17 (number 63), J1[4]/U7[24]/D1/UART0_TX/FXIO_D17/UART1_TX_TGTMCU
150 @{ */
151#define BOARD_DEBUG_UART_TX_PORT PORTB /*!<@brief PORT device name: PORTB */
152#define BOARD_DEBUG_UART_TX_PIN 17U /*!<@brief PORTB pin index: 17 */
153 /* @} */
154
155/*!
156 * @brief Configures pin routing and optionally pin electrical features.
157 *
158 */
159void BOARD_InitDEBUG_UARTPins(void);
160
161/*! @name PORTE25 (number 32), U2[12]/U10[6]/ACCEL_I2C0_SDA
162 @{ */
163#define BOARD_ACCEL_SDA_PORT PORTE /*!<@brief PORT device name: PORTE */
164#define BOARD_ACCEL_SDA_PIN 25U /*!<@brief PORTE pin index: 25 */
165 /* @} */
166
167/*! @name PORTE24 (number 31), U2[11]/U10[4]/ACCEL_I2C0_SCL
168 @{ */
169#define BOARD_ACCEL_SCL_PORT PORTE /*!<@brief PORT device name: PORTE */
170#define BOARD_ACCEL_SCL_PIN 24U /*!<@brief PORTE pin index: 24 */
171 /* @} */
172
173/*! @name PORTD4 (number 97), U10[11]/INT1_8700
174 @{ */
175#define BOARD_ACCEL_INT1_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */
176#define BOARD_ACCEL_INT1_PORT PORTD /*!<@brief PORT device name: PORTD */
177#define BOARD_ACCEL_INT1_PIN 4U /*!<@brief PORTD pin index: 4 */
178 /* @} */
179
180/*! @name PORTE5 (number 6), U10[9]/INT2_8700
181 @{ */
182#define BOARD_ACCEL_INT2_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
183#define BOARD_ACCEL_INT2_PORT PORTE /*!<@brief PORT device name: PORTE */
184#define BOARD_ACCEL_INT2_PIN 5U /*!<@brief PORTE pin index: 5 */
185 /* @} */
186
187/*! @name PORTE26 (number 33), U10[16]/U11[2]/ACCEL_RST
188 @{ */
189#define BOARD_ACCEL_RST_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
190#define BOARD_ACCEL_RST_PORT PORTE /*!<@brief PORT device name: PORTE */
191#define BOARD_ACCEL_RST_PIN 26U /*!<@brief PORTE pin index: 26 */
192 /* @} */
193
194/*!
195 * @brief Configures pin routing and optionally pin electrical features.
196 *
197 */
198void BOARD_InitACCELPins(void);
199
200/*! @name PORTE24 (number 31), U2[11]/U10[4]/ACCEL_I2C0_SCL
201 @{ */
202#define BOARD_GYRO_SCL_PORT PORTE /*!<@brief PORT device name: PORTE */
203#define BOARD_GYRO_SCL_PIN 24U /*!<@brief PORTE pin index: 24 */
204 /* @} */
205
206/*! @name PORTE25 (number 32), U2[12]/U10[6]/ACCEL_I2C0_SDA
207 @{ */
208#define BOARD_GYRO_SDA_PORT PORTE /*!<@brief PORT device name: PORTE */
209#define BOARD_GYRO_SDA_PIN 25U /*!<@brief PORTE pin index: 25 */
210 /* @} */
211
212/*! @name PORTE0 (number 1), U2[3]/INT1_21002
213 @{ */
214#define BOARD_GYRO_INT1_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
215#define BOARD_GYRO_INT1_PORT PORTE /*!<@brief PORT device name: PORTE */
216#define BOARD_GYRO_INT1_PIN 0U /*!<@brief PORTE pin index: 0 */
217 /* @} */
218
219/*! @name PORTE1 (number 2), U2[2]/INT2_21002
220 @{ */
221#define BOARD_GYRO_INT2_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
222#define BOARD_GYRO_INT2_PORT PORTE /*!<@brief PORT device name: PORTE */
223#define BOARD_GYRO_INT2_PIN 1U /*!<@brief PORTE pin index: 1 */
224 /* @} */
225
226/*! @name PORTE26 (number 33), U10[16]/U11[2]/ACCEL_RST
227 @{ */
228#define BOARD_GYRO_RST_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
229#define BOARD_GYRO_RST_PORT PORTE /*!<@brief PORT device name: PORTE */
230#define BOARD_GYRO_RST_PIN 26U /*!<@brief PORTE pin index: 26 */
231 /* @} */
232
233/*!
234 * @brief Configures pin routing and optionally pin electrical features.
235 *
236 */
237void BOARD_InitGYROPins(void);
238
239/*! @name PORTA18 (number 50), Y1[1]/EXTAL_32KHZ
240 @{ */
241#define BOARD_EXTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */
242#define BOARD_EXTAL0_PIN 18U /*!<@brief PORTA pin index: 18 */
243 /* @} */
244
245/*! @name PORTA19 (number 51), Y1[2]/XTAL_32KHZ
246 @{ */
247#define BOARD_XTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */
248#define BOARD_XTAL0_PIN 19U /*!<@brief PORTA pin index: 19 */
249 /* @} */
250
251/*!
252 * @brief Configures pin routing and optionally pin electrical features.
253 *
254 */
255void BOARD_InitOSCPins(void);
256
257#if defined(__cplusplus)
258}
259#endif
260
261/*!
262 * @}
263 */
264#endif /* _PIN_MUX_H_ */
265
266/***********************************************************************************************************************
267 * EOF
268 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 17:19:08 +0100