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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/K32L2A41A.h18673
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/K32L2A41A_features.h1640
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/all_lib_device_K32L2A41A.cmake114
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/arm/MK_P512_K32L2A.FLMbin0 -> 31484 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/device_CMSIS.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/device_startup.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/device_system.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/drivers/driver_clock.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/drivers/fsl_clock.c1214
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/drivers/fsl_clock.h1430
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/gcc/K32L2A41xxxxA_flash.ld227
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/gcc/K32L2A41xxxxA_ram.ld219
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/gcc/startup_K32L2A41A.S498
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/mcuxpresso/startup_k32l2a41a.c669
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/mcuxpresso/startup_k32l2a41a.cpp669
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/board.c108
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/board.h202
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/clock_config.c368
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/clock_config.h123
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/peripherals.c61
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/pin_mux.c902
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/pin_mux.h268
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/system_K32L2A41A.c134
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/system_K32L2A41A.h116
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/template/RTE_Device.h166
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/fsl_shell.h292
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/utility_notifier.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/utilities/utility_shell.cmake18
34 files changed, 29803 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/K32L2A41A.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/K32L2A41A.h
new file mode 100644
index 000000000..b852c1f30
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/K32L2A41A.h
@@ -0,0 +1,18673 @@
1/*
2** ###################################################################
3** Processors: K32L2A41VLH1A
4** K32L2A41VLL1A
5**
6** Compilers: Freescale C/C++ for Embedded ARM
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: K32L2AxRM, Rev. 1, 12/2019
13** Version: rev. 1.0, 2019-10-30
14** Build: b191218
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for K32L2A41A
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2019 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2019-10-30)
30** Initial version.
31**
32** ###################################################################
33*/
34
35/*!
36 * @file K32L2A41A.h
37 * @version 1.0
38 * @date 2019-10-30
39 * @brief CMSIS Peripheral Access Layer for K32L2A41A
40 *
41 * CMSIS Peripheral Access Layer for K32L2A41A
42 */
43
44#ifndef _K32L2A41A_H_
45#define _K32L2A41A_H_ /**< Symbol preventing repeated inclusion */
46
47/** Memory map major version (memory maps with equal major version number are
48 * compatible) */
49#define MCU_MEM_MAP_VERSION 0x0100U
50/** Memory map minor version */
51#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
52
53/* ----------------------------------------------------------------------------
54 -- Interrupt vector numbers
55 ---------------------------------------------------------------------------- */
56
57/*!
58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59 * @{
60 */
61
62/** Interrupt Number Definitions */
63#define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */
64
65typedef enum IRQn
66{
67 /* Auxiliary constants */
68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
69
70 /* Core interrupts */
71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
76
77 /* Device specific interrupts */
78 DMA0_04_IRQn = 0, /**< DMA0 channel 0/4 transfer complete */
79 DMA0_15_IRQn = 1, /**< DMA0 channel 1/5 transfer complete */
80 DMA0_26_IRQn = 2, /**< DMA0 channel 2/6 transfer complete */
81 DMA0_37_IRQn = 3, /**< DMA0 channel 3/7 transfer complete */
82 CTI0_DMA0_Error_IRQn = 4, /**< CTI0 or DMA0 error */
83 FLEXIO0_IRQn = 5, /**< FLEXIO0 */
84 TPM0_IRQn = 6, /**< TPM0 single interrupt vector for all sources */
85 TPM1_IRQn = 7, /**< TPM1 single interrupt vector for all sources */
86 TPM2_IRQn = 8, /**< TPM2 single interrupt vector for all sources */
87 LPIT0_IRQn = 9, /**< LPIT0 interrupt */
88 LPSPI0_IRQn = 10, /**< LPSPI0 single interrupt vector for all sources */
89 LPSPI1_IRQn = 11, /**< LPSPI1 single interrupt vector for all sources */
90 LPUART0_IRQn = 12, /**< LPUART0 status and error */
91 LPUART1_IRQn = 13, /**< LPUART1 status and error */
92 LPI2C0_IRQn = 14, /**< LPI2C0 interrupt */
93 LPI2C1_IRQn = 15, /**< LPI2C1 interrupt */
94 Reserved32_IRQn = 16, /**< Reserved interrupt */
95 PORTA_IRQn = 17, /**< PORTA Pin detect */
96 PORTB_IRQn = 18, /**< PORTB Pin detect */
97 PORTC_IRQn = 19, /**< PORTC Pin detect */
98 PORTD_IRQn = 20, /**< PORTD Pin detect */
99 PORTE_IRQn = 21, /**< PORTE Pin detect */
100 LLWU_IRQn = 22, /**< Low leakage wakeup */
101 Reserved39_IRQn = 23, /**< Reserved interrupt */
102 USB0_IRQn = 24, /**< USB0 interrupt */
103 ADC0_IRQn = 25, /**< ADC0 interrupt */
104 LPTMR0_IRQn = 26, /**< LPTMR0 interrupt */
105 RTC_Seconds_IRQn = 27, /**< RTC seconds */
106 INTMUX0_0_IRQn = 28, /**< INTMUX0 channel 0 interrupt */
107 INTMUX0_1_IRQn = 29, /**< INTMUX0 channel 1 interrupt */
108 INTMUX0_2_IRQn = 30, /**< INTMUX0 channel 2 interrupt */
109 INTMUX0_3_IRQn = 31, /**< INTMUX0 channel 3 interrupt */
110 LPTMR1_IRQn = 32, /**< LPTMR1 interrupt (INTMUX source IRQ0) */
111 Reserved49_IRQn = 33, /**< Reserved interrupt */
112 Reserved50_IRQn = 34, /**< Reserved interrupt */
113 Reserved51_IRQn = 35, /**< Reserved interrupt */
114 LPSPI2_IRQn = 36, /**< LPSPI2 single interrupt vector for all sources (INTMUX source IRQ4) */
115 LPUART2_IRQn = 37, /**< LPUART2 status and error (INTMUX source IRQ5) */
116 EMVSIM0_IRQn = 38, /**< EMVSIM0 interrupt (INTMUX source IRQ6) */
117 LPI2C2_IRQn = 39, /**< LPI2C2 interrupt (INTMUX source IRQ7) */
118 TSI0_IRQn = 40, /**< TSI0 interrupt (INTMUX source IRQ8) */
119 PMC_IRQn = 41, /**< PMC interrupt (INTMUX source IRQ9) */
120 FTFA_IRQn = 42, /**< FTFA interrupt (INTMUX source IRQ10) */
121 SCG_IRQn = 43, /**< SCG interrupt (INTMUX source IRQ11) */
122 WDOG0_IRQn = 44, /**< WDOG0 interrupt (INTMUX source IRQ12) */
123 DAC0_IRQn = 45, /**< DAC0 interrupt (INTMUX source IRQ13) */
124 TRNG_IRQn = 46, /**< TRNG interrupt (INTMUX source IRQ14) */
125 RCM_IRQn = 47, /**< RCM interrupt (INTMUX source IRQ15) */
126 CMP0_IRQn = 48, /**< CMP0 interrupt (INTMUX source IRQ16) */
127 CMP1_IRQn = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */
128 RTC_IRQn = 50, /**< RTC Alarm interrupt (INTMUX source IRQ18) */
129 Reserved67_IRQn = 51, /**< Reserved interrupt */
130 Reserved68_IRQn = 52, /**< Reserved interrupt */
131 Reserved69_IRQn = 53, /**< Reserved interrupt */
132 Reserved70_IRQn = 54, /**< Reserved interrupt */
133 Reserved71_IRQn = 55, /**< Reserved interrupt */
134 Reserved72_IRQn = 56, /**< Reserved interrupt */
135 Reserved73_IRQn = 57, /**< Reserved interrupt */
136 Reserved74_IRQn = 58, /**< Reserved interrupt */
137 Reserved75_IRQn = 59, /**< Reserved interrupt */
138 Reserved76_IRQn = 60, /**< Reserved interrupt */
139 Reserved77_IRQn = 61, /**< Reserved interrupt */
140 Reserved78_IRQn = 62, /**< Reserved interrupt */
141 Reserved79_IRQn = 63 /**< Reserved interrupt */
142} IRQn_Type;
143
144/*!
145 * @}
146 */ /* end of group Interrupt_vector_numbers */
147
148/* ----------------------------------------------------------------------------
149 -- Cortex M0 Core Configuration
150 ---------------------------------------------------------------------------- */
151
152/*!
153 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
154 * @{
155 */
156
157#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
158#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
159#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
160#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
161#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
162
163#include "core_cm0plus.h" /* Core Peripheral Access Layer */
164#include "system_K32L2A41A.h" /* Device specific configuration file */
165
166/*!
167 * @}
168 */ /* end of group Cortex_Core_Configuration */
169
170/* ----------------------------------------------------------------------------
171 -- Mapping Information
172 ---------------------------------------------------------------------------- */
173
174/*!
175 * @addtogroup Mapping_Information Mapping Information
176 * @{
177 */
178
179/** Mapping Information */
180/*!
181 * @addtogroup edma_request
182 * @{
183 */
184
185/*******************************************************************************
186 * Definitions
187 ******************************************************************************/
188
189/*!
190 * @brief Structure for the DMA hardware request
191 *
192 * Defines the structure for the DMA hardware request collections. The user can configure the
193 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
194 * of the hardware request varies according to the to SoC.
195 */
196typedef enum _dma_request_source
197{
198 kDmaRequestMux0Disable = 0 | 0x100U, /**< DMAMUX TriggerDisabled */
199 kDmaRequestMux0FlexIO0Channel0 = 1 | 0x100U, /**< FLEXIO0 Channel 0 */
200 kDmaRequestMux0FlexIO0Channel1 = 2 | 0x100U, /**< FLEXIO0 Channel 1 */
201 kDmaRequestMux0FlexIO0Channel2 = 3 | 0x100U, /**< FLEXIO0 Channel 2 */
202 kDmaRequestMux0FlexIO0Channel3 = 4 | 0x100U, /**< FLEXIO0 Channel 3 */
203 kDmaRequestMux0FlexIO0Channel4 = 5 | 0x100U, /**< FLEXIO0 Channel 4 */
204 kDmaRequestMux0FlexIO0Channel5 = 6 | 0x100U, /**< FLEXIO0 Channel 5 */
205 kDmaRequestMux0FlexIO0Channel6 = 7 | 0x100U, /**< FLEXIO0 Channel 6 */
206 kDmaRequestMux0FlexIO0Channel7 = 8 | 0x100U, /**< FLEXIO0 Channel 7 */
207 kDmaRequestMux0LPI2C0Rx = 9 | 0x100U, /**< LPI2C0 Receive */
208 kDmaRequestMux0LPI2C0Tx = 10 | 0x100U, /**< LPI2C0 Transmit */
209 kDmaRequestMux0LPI2C1Rx = 11 | 0x100U, /**< LPI2C1 Receive */
210 kDmaRequestMux0LPI2C1Tx = 12 | 0x100U, /**< LPI2C1 Transmit */
211 kDmaRequestMux0LPI2C2Rx = 13 | 0x100U, /**< LPI2C2 Receive */
212 kDmaRequestMux0LPI2C2Tx = 14 | 0x100U, /**< LPI2C2 Transmit */
213 kDmaRequestMux0LPUART0Rx = 15 | 0x100U, /**< LPUART0 Receive */
214 kDmaRequestMux0LPUART0Tx = 16 | 0x100U, /**< LPUART0 Transmit */
215 kDmaRequestMux0LPUART1Rx = 17 | 0x100U, /**< LPUART1 Receive */
216 kDmaRequestMux0LPUART1Tx = 18 | 0x100U, /**< LPUART1 Transmit */
217 kDmaRequestMux0LPUART2Rx = 19 | 0x100U, /**< LPUART2 Receive */
218 kDmaRequestMux0LPUART2Tx = 20 | 0x100U, /**< LPUART2 Transmit */
219 kDmaRequestMux0LPSPI0Rx = 21 | 0x100U, /**< LPSPI0 Receive */
220 kDmaRequestMux0LPSPI0Tx = 22 | 0x100U, /**< LPSPI0 Transmit */
221 kDmaRequestMux0LPSPI1Rx = 23 | 0x100U, /**< LPSPI1 Receive */
222 kDmaRequestMux0LPSPI1Tx = 24 | 0x100U, /**< LPSPI1 Transmit */
223 kDmaRequestMux0LPSPI2Rx = 25 | 0x100U, /**< LPSPI2 Receive */
224 kDmaRequestMux0LPSPI2Tx = 26 | 0x100U, /**< LPSPI2 Transmit */
225 kDmaRequestMux0TPM0Channel0 = 27 | 0x100U, /**< TPM0 C0V Transmit */
226 kDmaRequestMux0TPM0Channel1 = 28 | 0x100U, /**< TPM0 C1V Transmit */
227 kDmaRequestMux0TPM0Channel2 = 29 | 0x100U, /**< TPM0 C2V Transmit */
228 kDmaRequestMux0TPM0Channel3 = 30 | 0x100U, /**< TPM0 C3V Transmit */
229 kDmaRequestMux0TPM0Channel4 = 31 | 0x100U, /**< TPM0 C4V Transmit */
230 kDmaRequestMux0TPM0Channel5 = 32 | 0x100U, /**< TPM0 C5V Transmit */
231 kDmaRequestMux0Reserved33 = 33 | 0x100U, /**< Reserved33 */
232 kDmaRequestMux0Reserved34 = 34 | 0x100U, /**< Reserved34 */
233 kDmaRequestMux0TPM0Overflow = 35 | 0x100U, /**< TPM0 */
234 kDmaRequestMux0TPM1Channel0 = 36 | 0x100U, /**< TPM1 C0V Transmit */
235 kDmaRequestMux0TPM1Channel1 = 37 | 0x100U, /**< TPM1 C1V Transmit */
236 kDmaRequestMux0TPM1Overflow = 38 | 0x100U, /**< TPM1 */
237 kDmaRequestMux0TPM2Channel0 = 39 | 0x100U, /**< TPM2 C0V Transmit */
238 kDmaRequestMux0TPM2Channel1 = 40 | 0x100U, /**< TPM2 C1V Transmit */
239 kDmaRequestMux0TPM2Overflow = 41 | 0x100U, /**< TPM2 */
240 kDmaRequestMux0Reserved42 = 42 | 0x100U, /**< Reserved42 */
241 kDmaRequestMux0EMVSIM0Rx = 43 | 0x100U, /**< EMVSIM0 Receive */
242 kDmaRequestMux0EMVSIM0Tx = 44 | 0x100U, /**< EMVSIM0 Transmit */
243 kDmaRequestMux0Reserved45 = 45 | 0x100U, /**< Reserved45 */
244 kDmaRequestMux0Reserved46 = 46 | 0x100U, /**< Reserved46 */
245 kDmaRequestMux0PortA = 47 | 0x100U, /**< PTA */
246 kDmaRequestMux0PortB = 48 | 0x100U, /**< PTB */
247 kDmaRequestMux0PortC = 49 | 0x100U, /**< PTC */
248 kDmaRequestMux0PortD = 50 | 0x100U, /**< PTD */
249 kDmaRequestMux0PortE = 51 | 0x100U, /**< PTE */
250 kDmaRequestMux0ADC0 = 52 | 0x100U, /**< ADC0 */
251 kDmaRequestMux0Reserved53 = 53 | 0x100U, /**< Reserved53 */
252 kDmaRequestMux0DAC0 = 54 | 0x100U, /**< DAC0 */
253 kDmaRequestMux0Reserved55 = 55 | 0x100U, /**< Reserved55 */
254 kDmaRequestMux0CMP0 = 56 | 0x100U, /**< CMP0 */
255 kDmaRequestMux0CMP1 = 57 | 0x100U, /**< CMP1 */
256 kDmaRequestMux0Reserved58 = 58 | 0x100U, /**< Reserved58 */
257 kDmaRequestMux0Reserved59 = 59 | 0x100U, /**< Reserved59 */
258 kDmaRequestMux0TSI0 = 60 | 0x100U, /**< TSI0 */
259 kDmaRequestMux0LPTMR0 = 61 | 0x100U, /**< LPTMR0 */
260 kDmaRequestMux0LPTMR1 = 62 | 0x100U, /**< LPTMR1 */
261 kDmaRequestMux0AlwaysOn63 = 63 | 0x100U, /**< DMAMUX Always Enabled slot */
262} dma_request_source_t;
263
264/* @} */
265
266/*!
267 * @addtogroup trgmux_source
268 * @{ */
269
270/*******************************************************************************
271 * Definitions
272 *******************************************************************************/
273
274/*!
275 * @brief Structure for the TRGMUX source
276 *
277 * Defines the structure for the TRGMUX source collections.
278 */
279typedef enum _trgmux_source
280{
281 kTRGMUX_SourceDisabled = 0U, /**< Trigger function is disabled */
282 kTRGMUX_SourcePortPin = 1U, /**< Port pin trigger intput is selected */
283 kTRGMUX_SourceFlexIOTimer0 = 2U, /**< FlexIO Timer 0 input is selected */
284 kTRGMUX_SourceFlexIOTimer1 = 3U, /**< FlexIO Timer 1 input is selected */
285 kTRGMUX_SourceFlexIOTimer2 = 4U, /**< FlexIO Timer 2 input is selected */
286 kTRGMUX_SourceFlexIOTimer3 = 5U, /**< FlexIO Timer 3 input is selected */
287 kTRGMUX_SourceFlexIOTimer4 = 6U, /**< FlexIO Timer 4 input is selected */
288 kTRGMUX_SourceFlexIOTimer5 = 7U, /**< FlexIO Timer 5 input is selected */
289 kTRGMUX_SourceFlexIOTimer6 = 8U, /**< FlexIO Timer 6 input is selected */
290 kTRGMUX_SourceFlexIOTimer7 = 9U, /**< FlexIO Timer 7 input is selected */
291 kTRGMUX_SourceTpm0Overflow = 10U, /**< TPM0 Overflow is selected */
292 kTRGMUX_SourceTpm0Ch0 = 11U, /**< TPM0 Channel 0 is selected */
293 kTRGMUX_SourceTpm0Ch1 = 12U, /**< TPM0 Channel 1 is selected */
294 kTRGMUX_SourceTpm1Overflow = 13U, /**< TPM1 Overflow is selected */
295 kTRGMUX_SourceTpm1Ch0 = 14U, /**< TPM1 Channel 0 is selected */
296 kTRGMUX_SourceTpm1Ch1 = 15U, /**< TPM1 Channel 1 is selected */
297 kTRGMUX_SourceLpit1Ch0 = 16U, /**< LPIT1 Channel 0 is selected */
298 kTRGMUX_SourceLpit1Ch1 = 17U, /**< LPIT1 Channel 1 is selected */
299 kTRGMUX_SourceLpit1Ch2 = 18U, /**< LPIT1 Channel 2 is selected */
300 kTRGMUX_SourceLpit1Ch3 = 19U, /**< LPIT1 Channel 3 is selected */
301 kTRGMUX_SourceLpuart0RxData = 20U, /**< LPUART0 RX Data is selected */
302 kTRGMUX_SourceLpuart0TxData = 21U, /**< LPUART0 TX Data is selected */
303 kTRGMUX_SourceLpuart0RxIdle = 22U, /**< LPUART0 RX Idle is selected */
304 kTRGMUX_SourceLpuart1RxData = 23U, /**< LPUART1 RX Data is selected */
305 kTRGMUX_SourceLpuart1TxData = 24U, /**< LPUART1 TX Data is selected */
306 kTRGMUX_SourceLpuart1RxIdle = 25U, /**< LPUART1 RX Idle is selected */
307 kTRGMUX_SourceLpi2c0MasterStop = 26U, /**< LPI2C0 Master STOP is selected */
308 kTRGMUX_SourceLpi2c0SlaveStop = 27U, /**< LPI2C0 Slave STOP is selected */
309 kTRGMUX_SourceLpi2c1MasterStop = 28U, /**< LPI2C1 Master STOP is selected */
310 kTRGMUX_SourceLpi2c1SlaveStop = 29U, /**< LPI2C1 Slave STOP is selected */
311 kTRGMUX_SourceLpspi0Frame = 30U, /**< LPSPI0 Frame is selected */
312 kTRGMUX_SourceLpspi0RxData = 31U, /**< LPSPI0 RX Data is selected */
313 kTRGMUX_SourceLpspi1Frame = 32U, /**< LPSPI1 Frame is selected */
314 kTRGMUX_SourceLpspi1RxData = 33U, /**< LPSPI1 RX Data is selected */
315 kTRGMUX_SourceRtcSecCount = 34U, /**< RTC Seconds Counter is selected */
316 kTRGMUX_SourceRtcAlarm = 35U, /**< RTC Alarm is selected */
317 kTRGMUX_SourceLptmr0Trg = 36U, /**< LPTMR0 Trigger is selected */
318 kTRGMUX_SourceLptmr1Trg = 37U, /**< LPTMR1 Trigger is selected */
319 kTRGMUX_SourceCmp0Output = 38U, /**< CMP0 Output is selected */
320 kTRGMUX_SourceCmp1Output = 39U, /**< CMP1 Output is selected */
321 kTRGMUX_SourceAdc0ConvAComplete = 40U, /**< ADC0 Conversion A Complete is selected */
322 kTRGMUX_SourceAdc0ConvBComplete = 41U, /**< ADC0 Conversion B Complete is selected */
323 kTRGMUX_SourcePortAPinTrg = 42U, /**< Port A Pin Trigger is selected */
324 kTRGMUX_SourcePortBPinTrg = 43U, /**< Port B Pin Trigger is selected */
325 kTRGMUX_SourcePortCPinTrg = 44U, /**< Port C Pin Trigger is selected */
326 kTRGMUX_SourcePortDPinTrg = 45U, /**< Port D Pin Trigger is selected */
327 kTRGMUX_SourcePortEPinTrg = 46U, /**< Port E Pin Trigger is selected */
328 kTRGMUX_SourceTpm2Overflow = 47U, /**< TPM2 Overflow is selected */
329 kTRGMUX_SourceTpm2Ch0 = 48U, /**< TPM2 Channel 0 is selected */
330 kTRGMUX_SourceTpm2Ch1 = 49U, /**< TPM2 Channel 1 is selected */
331 kTRGMUX_SourceLpit0Ch0 = 50U, /**< LPIT0 Channel 0 is selected */
332 kTRGMUX_SourceLpit0Ch1 = 51U, /**< LPIT0 Channel 1 is selected */
333 kTRGMUX_SourceLpit0Ch2 = 52U, /**< LPIT0 Channel 2 is selected */
334 kTRGMUX_SourceLpit0Ch3 = 53U, /**< LPIT0 Channel 3 is selected */
335 kTRGMUX_SourceUsbSof = 54U, /**< USB Start-of-Frame is selected */
336 kTRGMUX_SourceLpuart2RxData = 55U, /**< LPUART2 RX Data is selected */
337 kTRGMUX_SourceLpuart2TxData = 56U, /**< LPUART2 TX Data is selected */
338 kTRGMUX_SourceLpuart2RxIdle = 57U, /**< LPUART2 RX Idle is selected */
339 kTRGMUX_SourceLpi2c2MasterStop = 58U, /**< LPI2C2 Master STOP is selected */
340 kTRGMUX_SourceLpi2c2SlaveStop = 59U, /**< LPI2C2 Slave STOP is selected */
341 kTRGMUX_SourceLpspi2Frame = 60U, /**< LPSPI2 Frame is selected */
342 kTRGMUX_SourceLpspi2RxData = 61U, /**< LPSPI2 RX Data is selected */
343 kTRGMUX_SourceI2c0TxFrameSync = 62U, /**< I2C0 TX Frame Sync is selected */
344 kTRGMUX_SourceI2c0RxFrameSync = 63U, /**< I2C0 RX Frame Sync is selected */
345} trgmux_source_t;
346
347/*!
348 * @brief Structure for the TRGMUX device
349 *
350 * Defines the structure for the TRGMUX device collections.
351 */
352typedef enum _trgmux_device
353{
354 kTRGMUX_Trgmux0Dmamux0 = 0U, /**< DMAMUX0 device trigger input */
355 kTRGMUX_Trgmux0Lpit0 = 1U, /**< LPIT0 device trigger input */
356 kTRGMUX_Trgmux0Tpm2 = 2U, /**< TPM2 device trigger input */
357 kTRGMUX_Trgmux1Tpm0 = 2U, /**< TPM0 device trigger input */
358 kTRGMUX_Trgmux0Adc0 = 4U, /**< ADC0 device trigger input */
359 kTRGMUX_Trgmux1Flexio = 4U, /**< FLEXIO device trigger input */
360 kTRGMUX_Trgmux0Lpuart2 = 5U, /**< LPUART2 device trigger input */
361 kTRGMUX_Trgmux1Lpuart0 = 5U, /**< LPUART0 device trigger input */
362 kTRGMUX_Trgmux0Lpi2c2 = 7U, /**< LPI2C2 device trigger input */
363 kTRGMUX_Trgmux1Lpi2c0 = 7U, /**< LPI2C0 device trigger input */
364 kTRGMUX_Trgmux0Lpspi2 = 9U, /**< LPSPI2 device trigger input */
365 kTRGMUX_Trgmux1Lpspi0 = 9U, /**< LPSPI0 device trigger input */
366 kTRGMUX_Trgmux0Cmp0 = 11U, /**< CMP0 device trigger input */
367 kTRGMUX_Trgmux0Cmp1 = 12U, /**< CMP1 device trigger input */
368 kTRGMUX_Trgmux0Dac0 = 13U, /**< DAC0 device trigger input */
369 kTRGMUX_Trgmux1Tpm1 = 3U, /**< TPM1 device trigger input */
370 kTRGMUX_Trgmux1Lpuart1 = 6U, /**< LPUART1 device trigger input */
371 kTRGMUX_Trgmux1Lpi2c1 = 8U, /**< LPI2C1 device trigger input */
372 kTRGMUX_Trgmux1Lpspi1 = 10U, /**< LPSPI1 device trigger input */
373} trgmux_device_t;
374
375/* @} */
376
377/*!
378 * @}
379 */ /* end of group Mapping_Information */
380
381/* ----------------------------------------------------------------------------
382 -- Device Peripheral Access Layer
383 ---------------------------------------------------------------------------- */
384
385/*!
386 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
387 * @{
388 */
389
390/*
391** Start of section using anonymous unions
392*/
393
394#if defined(__ARMCC_VERSION)
395#if (__ARMCC_VERSION >= 6010050)
396#pragma clang diagnostic push
397#else
398#pragma push
399#pragma anon_unions
400#endif
401#elif defined(__CWCC__)
402#pragma push
403#pragma cpp_extensions on
404#elif defined(__GNUC__)
405/* anonymous unions are enabled by default */
406#elif defined(__IAR_SYSTEMS_ICC__)
407#pragma language = extended
408#else
409#error Not supported compiler type
410#endif
411
412/* ----------------------------------------------------------------------------
413 -- ADC Peripheral Access Layer
414 ---------------------------------------------------------------------------- */
415
416/*!
417 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
418 * @{
419 */
420
421/** ADC - Register Layout Typedef */
422typedef struct
423{
424 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
425 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
426 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
427 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
428 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
429 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
430 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
431 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
432 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
433 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
434 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
435 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
436 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
437 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
438 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
439 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
440 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
441 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
442 uint8_t RESERVED_0[4];
443 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
444 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
445 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
446 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
447 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
448 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
449 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
450} ADC_Type;
451
452/* ----------------------------------------------------------------------------
453 -- ADC Register Masks
454 ---------------------------------------------------------------------------- */
455
456/*!
457 * @addtogroup ADC_Register_Masks ADC Register Masks
458 * @{
459 */
460
461/*! @name SC1 - ADC Status and Control Registers 1 */
462/*! @{ */
463#define ADC_SC1_ADCH_MASK (0x1FU)
464#define ADC_SC1_ADCH_SHIFT (0U)
465/*! ADCH - Input channel select
466 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
467 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
468 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
469 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
470 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
471 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
472 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
473 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
474 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
475 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
476 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
477 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
478 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
479 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
480 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
481 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
482 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
483 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
484 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
485 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
486 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
487 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
488 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
489 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
490 * 0b11000..Reserved.
491 * 0b11001..Reserved.
492 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is
493 * selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap
494 * (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when
495 * DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
496 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is
497 * determined by SC2[REFSEL]. 0b11111..Module is disabled.
498 */
499#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
500#define ADC_SC1_DIFF_MASK (0x20U)
501#define ADC_SC1_DIFF_SHIFT (5U)
502/*! DIFF - Differential Mode Enable
503 * 0b0..Single-ended conversions and input channels are selected.
504 * 0b1..Differential conversions and input channels are selected.
505 */
506#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
507#define ADC_SC1_AIEN_MASK (0x40U)
508#define ADC_SC1_AIEN_SHIFT (6U)
509/*! AIEN - Interrupt Enable
510 * 0b0..Conversion complete interrupt is disabled.
511 * 0b1..Conversion complete interrupt is enabled.
512 */
513#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
514#define ADC_SC1_COCO_MASK (0x80U)
515#define ADC_SC1_COCO_SHIFT (7U)
516/*! COCO - Conversion Complete Flag
517 * 0b0..Conversion is not completed.
518 * 0b1..Conversion is completed.
519 */
520#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
521/*! @} */
522
523/* The count of ADC_SC1 */
524#define ADC_SC1_COUNT (2U)
525
526/*! @name CFG1 - ADC Configuration Register 1 */
527/*! @{ */
528#define ADC_CFG1_ADICLK_MASK (0x3U)
529#define ADC_CFG1_ADICLK_SHIFT (0U)
530/*! ADICLK - Input Clock Select
531 * 0b00..Bus clock
532 * 0b01..Bus clock divided by 2(BUSCLK/2)
533 * 0b10..Alternate clock (ALTCLK)
534 * 0b11..Asynchronous clock (ADACK)
535 */
536#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
537#define ADC_CFG1_MODE_MASK (0xCU)
538#define ADC_CFG1_MODE_SHIFT (2U)
539/*! MODE - Conversion mode selection
540 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's
541 * complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit
542 * conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
543 * differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..;
544 * when DIFF=1, it is differential 16-bit conversion with 2's complement output
545 */
546#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
547#define ADC_CFG1_ADLSMP_MASK (0x10U)
548#define ADC_CFG1_ADLSMP_SHIFT (4U)
549/*! ADLSMP - Sample Time Configuration
550 * 0b0..Short sample time.
551 * 0b1..Long sample time.
552 */
553#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
554#define ADC_CFG1_ADIV_MASK (0x60U)
555#define ADC_CFG1_ADIV_SHIFT (5U)
556/*! ADIV - Clock Divide Select
557 * 0b00..The divide ratio is 1 and the clock rate is input clock.
558 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
559 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
560 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
561 */
562#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
563#define ADC_CFG1_ADLPC_MASK (0x80U)
564#define ADC_CFG1_ADLPC_SHIFT (7U)
565/*! ADLPC - Low-Power Configuration
566 * 0b0..Normal power configuration.
567 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
568 */
569#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
570/*! @} */
571
572/*! @name CFG2 - ADC Configuration Register 2 */
573/*! @{ */
574#define ADC_CFG2_ADLSTS_MASK (0x3U)
575#define ADC_CFG2_ADLSTS_SHIFT (0U)
576/*! ADLSTS - Long Sample Time Select
577 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
578 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
579 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
580 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
581 */
582#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
583#define ADC_CFG2_ADHSC_MASK (0x4U)
584#define ADC_CFG2_ADHSC_SHIFT (2U)
585/*! ADHSC - High-Speed Configuration
586 * 0b0..Normal conversion sequence selected.
587 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
588 */
589#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
590#define ADC_CFG2_ADACKEN_MASK (0x8U)
591#define ADC_CFG2_ADACKEN_SHIFT (3U)
592/*! ADACKEN - Asynchronous Clock Output Enable
593 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion
594 * is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
595 */
596#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
597#define ADC_CFG2_MUXSEL_MASK (0x10U)
598#define ADC_CFG2_MUXSEL_SHIFT (4U)
599/*! MUXSEL - ADC Mux Select
600 * 0b0..ADxxa channels are selected.
601 * 0b1..ADxxb channels are selected.
602 */
603#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
604/*! @} */
605
606/*! @name R - ADC Data Result Register */
607/*! @{ */
608#define ADC_R_D_MASK (0xFFFFU)
609#define ADC_R_D_SHIFT (0U)
610/*! D - Data result
611 */
612#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
613/*! @} */
614
615/* The count of ADC_R */
616#define ADC_R_COUNT (2U)
617
618/*! @name CV1 - Compare Value Registers */
619/*! @{ */
620#define ADC_CV1_CV_MASK (0xFFFFU)
621#define ADC_CV1_CV_SHIFT (0U)
622/*! CV - Compare Value.
623 */
624#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
625/*! @} */
626
627/*! @name CV2 - Compare Value Registers */
628/*! @{ */
629#define ADC_CV2_CV_MASK (0xFFFFU)
630#define ADC_CV2_CV_SHIFT (0U)
631/*! CV - Compare Value.
632 */
633#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
634/*! @} */
635
636/*! @name SC2 - Status and Control Register 2 */
637/*! @{ */
638#define ADC_SC2_REFSEL_MASK (0x3U)
639#define ADC_SC2_REFSEL_SHIFT (0U)
640/*! REFSEL - Voltage Reference Selection
641 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
642 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or
643 * internal sources depending on the MCU configuration. See the chip configuration information for details
644 * specific to this MCU
645 * 0b10..Reserved
646 * 0b11..Reserved
647 */
648#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
649#define ADC_SC2_DMAEN_MASK (0x4U)
650#define ADC_SC2_DMAEN_SHIFT (2U)
651/*! DMAEN - DMA Enable
652 * 0b0..DMA is disabled.
653 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any
654 * of the SC1n[COCO] flags is asserted.
655 */
656#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
657#define ADC_SC2_ACREN_MASK (0x8U)
658#define ADC_SC2_ACREN_SHIFT (3U)
659/*! ACREN - Compare Function Range Enable
660 * 0b0..Range function disabled. Only CV1 is compared.
661 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
662 */
663#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
664#define ADC_SC2_ACFGT_MASK (0x10U)
665#define ADC_SC2_ACFGT_SHIFT (4U)
666/*! ACFGT - Compare Function Greater Than Enable
667 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality
668 * based on the values placed in CV1 and CV2.
669 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the
670 * values placed in CV1 and CV2.
671 */
672#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
673#define ADC_SC2_ACFE_MASK (0x20U)
674#define ADC_SC2_ACFE_SHIFT (5U)
675/*! ACFE - Compare Function Enable
676 * 0b0..Compare function disabled.
677 * 0b1..Compare function enabled.
678 */
679#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
680#define ADC_SC2_ADTRG_MASK (0x40U)
681#define ADC_SC2_ADTRG_SHIFT (6U)
682/*! ADTRG - Conversion Trigger Select
683 * 0b0..Software trigger selected.
684 * 0b1..Hardware trigger selected.
685 */
686#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
687#define ADC_SC2_ADACT_MASK (0x80U)
688#define ADC_SC2_ADACT_SHIFT (7U)
689/*! ADACT - Conversion Active
690 * 0b0..Conversion not in progress.
691 * 0b1..Conversion in progress.
692 */
693#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
694/*! @} */
695
696/*! @name SC3 - Status and Control Register 3 */
697/*! @{ */
698#define ADC_SC3_AVGS_MASK (0x3U)
699#define ADC_SC3_AVGS_SHIFT (0U)
700/*! AVGS - Hardware Average Select
701 * 0b00..4 samples averaged.
702 * 0b01..8 samples averaged.
703 * 0b10..16 samples averaged.
704 * 0b11..32 samples averaged.
705 */
706#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
707#define ADC_SC3_AVGE_MASK (0x4U)
708#define ADC_SC3_AVGE_SHIFT (2U)
709/*! AVGE - Hardware Average Enable
710 * 0b0..Hardware average function disabled.
711 * 0b1..Hardware average function enabled.
712 */
713#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
714#define ADC_SC3_ADCO_MASK (0x8U)
715#define ADC_SC3_ADCO_SHIFT (3U)
716/*! ADCO - Continuous Conversion Enable
717 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after
718 * initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is
719 * enabled, that is, AVGE=1, after initiating a conversion.
720 */
721#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
722#define ADC_SC3_CALF_MASK (0x40U)
723#define ADC_SC3_CALF_SHIFT (6U)
724/*! CALF - Calibration Failed Flag
725 * 0b0..Calibration completed normally.
726 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
727 */
728#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
729#define ADC_SC3_CAL_MASK (0x80U)
730#define ADC_SC3_CAL_SHIFT (7U)
731/*! CAL - Calibration
732 */
733#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
734/*! @} */
735
736/*! @name OFS - ADC Offset Correction Register */
737/*! @{ */
738#define ADC_OFS_OFS_MASK (0xFFFFU)
739#define ADC_OFS_OFS_SHIFT (0U)
740/*! OFS - Offset Error Correction Value
741 */
742#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
743/*! @} */
744
745/*! @name PG - ADC Plus-Side Gain Register */
746/*! @{ */
747#define ADC_PG_PG_MASK (0xFFFFU)
748#define ADC_PG_PG_SHIFT (0U)
749/*! PG - Plus-Side Gain
750 */
751#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
752/*! @} */
753
754/*! @name MG - ADC Minus-Side Gain Register */
755/*! @{ */
756#define ADC_MG_MG_MASK (0xFFFFU)
757#define ADC_MG_MG_SHIFT (0U)
758/*! MG - Minus-Side Gain
759 */
760#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
761/*! @} */
762
763/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
764/*! @{ */
765#define ADC_CLPD_CLPD_MASK (0x3FU)
766#define ADC_CLPD_CLPD_SHIFT (0U)
767/*! CLPD - Calibration Value
768 */
769#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
770/*! @} */
771
772/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
773/*! @{ */
774#define ADC_CLPS_CLPS_MASK (0x3FU)
775#define ADC_CLPS_CLPS_SHIFT (0U)
776/*! CLPS - Calibration Value
777 */
778#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
779/*! @} */
780
781/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
782/*! @{ */
783#define ADC_CLP4_CLP4_MASK (0x3FFU)
784#define ADC_CLP4_CLP4_SHIFT (0U)
785/*! CLP4 - Calibration Value
786 */
787#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
788/*! @} */
789
790/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
791/*! @{ */
792#define ADC_CLP3_CLP3_MASK (0x1FFU)
793#define ADC_CLP3_CLP3_SHIFT (0U)
794/*! CLP3 - Calibration Value
795 */
796#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
797/*! @} */
798
799/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
800/*! @{ */
801#define ADC_CLP2_CLP2_MASK (0xFFU)
802#define ADC_CLP2_CLP2_SHIFT (0U)
803/*! CLP2 - Calibration Value
804 */
805#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
806/*! @} */
807
808/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
809/*! @{ */
810#define ADC_CLP1_CLP1_MASK (0x7FU)
811#define ADC_CLP1_CLP1_SHIFT (0U)
812/*! CLP1 - Calibration Value
813 */
814#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
815/*! @} */
816
817/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
818/*! @{ */
819#define ADC_CLP0_CLP0_MASK (0x3FU)
820#define ADC_CLP0_CLP0_SHIFT (0U)
821/*! CLP0 - Calibration Value
822 */
823#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
824/*! @} */
825
826/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
827/*! @{ */
828#define ADC_CLMD_CLMD_MASK (0x3FU)
829#define ADC_CLMD_CLMD_SHIFT (0U)
830/*! CLMD - Calibration Value
831 */
832#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
833/*! @} */
834
835/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
836/*! @{ */
837#define ADC_CLMS_CLMS_MASK (0x3FU)
838#define ADC_CLMS_CLMS_SHIFT (0U)
839/*! CLMS - Calibration Value
840 */
841#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
842/*! @} */
843
844/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
845/*! @{ */
846#define ADC_CLM4_CLM4_MASK (0x3FFU)
847#define ADC_CLM4_CLM4_SHIFT (0U)
848/*! CLM4 - Calibration Value
849 */
850#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
851/*! @} */
852
853/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
854/*! @{ */
855#define ADC_CLM3_CLM3_MASK (0x1FFU)
856#define ADC_CLM3_CLM3_SHIFT (0U)
857/*! CLM3 - Calibration Value
858 */
859#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
860/*! @} */
861
862/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
863/*! @{ */
864#define ADC_CLM2_CLM2_MASK (0xFFU)
865#define ADC_CLM2_CLM2_SHIFT (0U)
866/*! CLM2 - Calibration Value
867 */
868#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
869/*! @} */
870
871/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
872/*! @{ */
873#define ADC_CLM1_CLM1_MASK (0x7FU)
874#define ADC_CLM1_CLM1_SHIFT (0U)
875/*! CLM1 - Calibration Value
876 */
877#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
878/*! @} */
879
880/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
881/*! @{ */
882#define ADC_CLM0_CLM0_MASK (0x3FU)
883#define ADC_CLM0_CLM0_SHIFT (0U)
884/*! CLM0 - Calibration Value
885 */
886#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
887/*! @} */
888
889/*!
890 * @}
891 */ /* end of group ADC_Register_Masks */
892
893/* ADC - Peripheral instance base addresses */
894/** Peripheral ADC0 base address */
895#define ADC0_BASE (0x40066000u)
896/** Peripheral ADC0 base pointer */
897#define ADC0 ((ADC_Type *)ADC0_BASE)
898/** Array initializer of ADC peripheral base addresses */
899#define ADC_BASE_ADDRS \
900 { \
901 ADC0_BASE \
902 }
903/** Array initializer of ADC peripheral base pointers */
904#define ADC_BASE_PTRS \
905 { \
906 ADC0 \
907 }
908/** Interrupt vectors for the ADC peripheral type */
909#define ADC_IRQS \
910 { \
911 ADC0_IRQn \
912 }
913
914/*!
915 * @}
916 */ /* end of group ADC_Peripheral_Access_Layer */
917
918/* ----------------------------------------------------------------------------
919 -- CAU Peripheral Access Layer
920 ---------------------------------------------------------------------------- */
921
922/*!
923 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
924 * @{
925 */
926
927/** CAU - Register Layout Typedef */
928typedef struct
929{
930 __O uint32_t
931 DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
932 uint8_t RESERVED_0[2048];
933 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
934 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
935 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load
936 Register command, array offset: 0x848, array step: 0x4 */
937 uint8_t RESERVED_1[20];
938 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
939 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
940 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store
941 Register command, array offset: 0x888, array step: 0x4 */
942 uint8_t RESERVED_2[20];
943 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
944 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
945 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add
946 to register command, array offset: 0x8C8, array step: 0x4 */
947 uint8_t RESERVED_3[20];
948 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
949 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
950 __O uint32_t
951 RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 -
952 Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
953 uint8_t RESERVED_4[84];
954 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
955 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
956 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 -
957 Exclusive Or command, array offset: 0x988, array step: 0x4 */
958 uint8_t RESERVED_5[20];
959 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
960 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
961 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate
962 Left command, array offset: 0x9C8, array step: 0x4 */
963 uint8_t RESERVED_6[276];
964 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
965 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
966 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8
967 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
968 uint8_t RESERVED_7[20];
969 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
970 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
971 __O uint32_t
972 AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8
973 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
974} CAU_Type;
975
976/* ----------------------------------------------------------------------------
977 -- CAU Register Masks
978 ---------------------------------------------------------------------------- */
979
980/*!
981 * @addtogroup CAU_Register_Masks CAU Register Masks
982 * @{
983 */
984
985/*! @name DIRECT - Direct access register 0..Direct access register 15 */
986/*! @{ */
987#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
988#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
989/*! CAU_DIRECT0 - Direct register 0
990 */
991#define CAU_DIRECT_CAU_DIRECT0(x) \
992 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
993#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
994#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
995/*! CAU_DIRECT1 - Direct register 1
996 */
997#define CAU_DIRECT_CAU_DIRECT1(x) \
998 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
999#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
1000#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
1001/*! CAU_DIRECT2 - Direct register 2
1002 */
1003#define CAU_DIRECT_CAU_DIRECT2(x) \
1004 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
1005#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
1006#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
1007/*! CAU_DIRECT3 - Direct register 3
1008 */
1009#define CAU_DIRECT_CAU_DIRECT3(x) \
1010 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
1011#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
1012#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
1013/*! CAU_DIRECT4 - Direct register 4
1014 */
1015#define CAU_DIRECT_CAU_DIRECT4(x) \
1016 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
1017#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
1018#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
1019/*! CAU_DIRECT5 - Direct register 5
1020 */
1021#define CAU_DIRECT_CAU_DIRECT5(x) \
1022 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
1023#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
1024#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
1025/*! CAU_DIRECT6 - Direct register 6
1026 */
1027#define CAU_DIRECT_CAU_DIRECT6(x) \
1028 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
1029#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
1030#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
1031/*! CAU_DIRECT7 - Direct register 7
1032 */
1033#define CAU_DIRECT_CAU_DIRECT7(x) \
1034 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
1035#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
1036#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
1037/*! CAU_DIRECT8 - Direct register 8
1038 */
1039#define CAU_DIRECT_CAU_DIRECT8(x) \
1040 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
1041#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
1042#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
1043/*! CAU_DIRECT9 - Direct register 9
1044 */
1045#define CAU_DIRECT_CAU_DIRECT9(x) \
1046 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
1047#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
1048#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
1049/*! CAU_DIRECT10 - Direct register 10
1050 */
1051#define CAU_DIRECT_CAU_DIRECT10(x) \
1052 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
1053#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
1054#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
1055/*! CAU_DIRECT11 - Direct register 11
1056 */
1057#define CAU_DIRECT_CAU_DIRECT11(x) \
1058 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
1059#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
1060#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
1061/*! CAU_DIRECT12 - Direct register 12
1062 */
1063#define CAU_DIRECT_CAU_DIRECT12(x) \
1064 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
1065#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
1066#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
1067/*! CAU_DIRECT13 - Direct register 13
1068 */
1069#define CAU_DIRECT_CAU_DIRECT13(x) \
1070 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
1071#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
1072#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
1073/*! CAU_DIRECT14 - Direct register 14
1074 */
1075#define CAU_DIRECT_CAU_DIRECT14(x) \
1076 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
1077#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
1078#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
1079/*! CAU_DIRECT15 - Direct register 15
1080 */
1081#define CAU_DIRECT_CAU_DIRECT15(x) \
1082 (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
1083/*! @} */
1084
1085/* The count of CAU_DIRECT */
1086#define CAU_DIRECT_COUNT (16U)
1087
1088/*! @name LDR_CASR - Status register - Load Register command */
1089/*! @{ */
1090#define CAU_LDR_CASR_IC_MASK (0x1U)
1091#define CAU_LDR_CASR_IC_SHIFT (0U)
1092/*! IC
1093 * 0b0..No illegal commands issued
1094 * 0b1..Illegal command issued
1095 */
1096#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
1097#define CAU_LDR_CASR_DPE_MASK (0x2U)
1098#define CAU_LDR_CASR_DPE_SHIFT (1U)
1099/*! DPE
1100 * 0b0..No error detected
1101 * 0b1..DES key parity error detected
1102 */
1103#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
1104#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
1105#define CAU_LDR_CASR_VER_SHIFT (28U)
1106/*! VER - CAU version
1107 * 0b0001..Initial CAU version
1108 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1109 */
1110#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
1111/*! @} */
1112
1113/*! @name LDR_CAA - Accumulator register - Load Register command */
1114/*! @{ */
1115#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
1116#define CAU_LDR_CAA_ACC_SHIFT (0U)
1117/*! ACC - ACC
1118 */
1119#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
1120/*! @} */
1121
1122/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register
1123 * command */
1124/*! @{ */
1125#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
1126#define CAU_LDR_CA_CA0_SHIFT (0U)
1127/*! CA0 - CA0
1128 */
1129#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
1130#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
1131#define CAU_LDR_CA_CA1_SHIFT (0U)
1132/*! CA1 - CA1
1133 */
1134#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
1135#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
1136#define CAU_LDR_CA_CA2_SHIFT (0U)
1137/*! CA2 - CA2
1138 */
1139#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
1140#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
1141#define CAU_LDR_CA_CA3_SHIFT (0U)
1142/*! CA3 - CA3
1143 */
1144#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
1145#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
1146#define CAU_LDR_CA_CA4_SHIFT (0U)
1147/*! CA4 - CA4
1148 */
1149#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
1150#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
1151#define CAU_LDR_CA_CA5_SHIFT (0U)
1152/*! CA5 - CA5
1153 */
1154#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
1155#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
1156#define CAU_LDR_CA_CA6_SHIFT (0U)
1157/*! CA6 - CA6
1158 */
1159#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
1160#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
1161#define CAU_LDR_CA_CA7_SHIFT (0U)
1162/*! CA7 - CA7
1163 */
1164#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
1165#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
1166#define CAU_LDR_CA_CA8_SHIFT (0U)
1167/*! CA8 - CA8
1168 */
1169#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
1170/*! @} */
1171
1172/* The count of CAU_LDR_CA */
1173#define CAU_LDR_CA_COUNT (9U)
1174
1175/*! @name STR_CASR - Status register - Store Register command */
1176/*! @{ */
1177#define CAU_STR_CASR_IC_MASK (0x1U)
1178#define CAU_STR_CASR_IC_SHIFT (0U)
1179/*! IC
1180 * 0b0..No illegal commands issued
1181 * 0b1..Illegal command issued
1182 */
1183#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
1184#define CAU_STR_CASR_DPE_MASK (0x2U)
1185#define CAU_STR_CASR_DPE_SHIFT (1U)
1186/*! DPE
1187 * 0b0..No error detected
1188 * 0b1..DES key parity error detected
1189 */
1190#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
1191#define CAU_STR_CASR_VER_MASK (0xF0000000U)
1192#define CAU_STR_CASR_VER_SHIFT (28U)
1193/*! VER - CAU version
1194 * 0b0001..Initial CAU version
1195 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1196 */
1197#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
1198/*! @} */
1199
1200/*! @name STR_CAA - Accumulator register - Store Register command */
1201/*! @{ */
1202#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
1203#define CAU_STR_CAA_ACC_SHIFT (0U)
1204/*! ACC - ACC
1205 */
1206#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
1207/*! @} */
1208
1209/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register
1210 * command */
1211/*! @{ */
1212#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
1213#define CAU_STR_CA_CA0_SHIFT (0U)
1214/*! CA0 - CA0
1215 */
1216#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
1217#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
1218#define CAU_STR_CA_CA1_SHIFT (0U)
1219/*! CA1 - CA1
1220 */
1221#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
1222#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
1223#define CAU_STR_CA_CA2_SHIFT (0U)
1224/*! CA2 - CA2
1225 */
1226#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
1227#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
1228#define CAU_STR_CA_CA3_SHIFT (0U)
1229/*! CA3 - CA3
1230 */
1231#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
1232#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
1233#define CAU_STR_CA_CA4_SHIFT (0U)
1234/*! CA4 - CA4
1235 */
1236#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
1237#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
1238#define CAU_STR_CA_CA5_SHIFT (0U)
1239/*! CA5 - CA5
1240 */
1241#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
1242#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
1243#define CAU_STR_CA_CA6_SHIFT (0U)
1244/*! CA6 - CA6
1245 */
1246#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
1247#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
1248#define CAU_STR_CA_CA7_SHIFT (0U)
1249/*! CA7 - CA7
1250 */
1251#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
1252#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
1253#define CAU_STR_CA_CA8_SHIFT (0U)
1254/*! CA8 - CA8
1255 */
1256#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
1257/*! @} */
1258
1259/* The count of CAU_STR_CA */
1260#define CAU_STR_CA_COUNT (9U)
1261
1262/*! @name ADR_CASR - Status register - Add Register command */
1263/*! @{ */
1264#define CAU_ADR_CASR_IC_MASK (0x1U)
1265#define CAU_ADR_CASR_IC_SHIFT (0U)
1266/*! IC
1267 * 0b0..No illegal commands issued
1268 * 0b1..Illegal command issued
1269 */
1270#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
1271#define CAU_ADR_CASR_DPE_MASK (0x2U)
1272#define CAU_ADR_CASR_DPE_SHIFT (1U)
1273/*! DPE
1274 * 0b0..No error detected
1275 * 0b1..DES key parity error detected
1276 */
1277#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
1278#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
1279#define CAU_ADR_CASR_VER_SHIFT (28U)
1280/*! VER - CAU version
1281 * 0b0001..Initial CAU version
1282 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1283 */
1284#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
1285/*! @} */
1286
1287/*! @name ADR_CAA - Accumulator register - Add to register command */
1288/*! @{ */
1289#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
1290#define CAU_ADR_CAA_ACC_SHIFT (0U)
1291/*! ACC - ACC
1292 */
1293#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
1294/*! @} */
1295
1296/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register
1297 * command */
1298/*! @{ */
1299#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
1300#define CAU_ADR_CA_CA0_SHIFT (0U)
1301/*! CA0 - CA0
1302 */
1303#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
1304#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
1305#define CAU_ADR_CA_CA1_SHIFT (0U)
1306/*! CA1 - CA1
1307 */
1308#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
1309#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
1310#define CAU_ADR_CA_CA2_SHIFT (0U)
1311/*! CA2 - CA2
1312 */
1313#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
1314#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
1315#define CAU_ADR_CA_CA3_SHIFT (0U)
1316/*! CA3 - CA3
1317 */
1318#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
1319#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
1320#define CAU_ADR_CA_CA4_SHIFT (0U)
1321/*! CA4 - CA4
1322 */
1323#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
1324#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
1325#define CAU_ADR_CA_CA5_SHIFT (0U)
1326/*! CA5 - CA5
1327 */
1328#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
1329#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
1330#define CAU_ADR_CA_CA6_SHIFT (0U)
1331/*! CA6 - CA6
1332 */
1333#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
1334#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
1335#define CAU_ADR_CA_CA7_SHIFT (0U)
1336/*! CA7 - CA7
1337 */
1338#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
1339#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
1340#define CAU_ADR_CA_CA8_SHIFT (0U)
1341/*! CA8 - CA8
1342 */
1343#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
1344/*! @} */
1345
1346/* The count of CAU_ADR_CA */
1347#define CAU_ADR_CA_COUNT (9U)
1348
1349/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
1350/*! @{ */
1351#define CAU_RADR_CASR_IC_MASK (0x1U)
1352#define CAU_RADR_CASR_IC_SHIFT (0U)
1353/*! IC
1354 * 0b0..No illegal commands issued
1355 * 0b1..Illegal command issued
1356 */
1357#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
1358#define CAU_RADR_CASR_DPE_MASK (0x2U)
1359#define CAU_RADR_CASR_DPE_SHIFT (1U)
1360/*! DPE
1361 * 0b0..No error detected
1362 * 0b1..DES key parity error detected
1363 */
1364#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
1365#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
1366#define CAU_RADR_CASR_VER_SHIFT (28U)
1367/*! VER - CAU version
1368 * 0b0001..Initial CAU version
1369 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1370 */
1371#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
1372/*! @} */
1373
1374/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
1375/*! @{ */
1376#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
1377#define CAU_RADR_CAA_ACC_SHIFT (0U)
1378/*! ACC - ACC
1379 */
1380#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
1381/*! @} */
1382
1383/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 -
1384 * Reverse and Add to Register command */
1385/*! @{ */
1386#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
1387#define CAU_RADR_CA_CA0_SHIFT (0U)
1388/*! CA0 - CA0
1389 */
1390#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
1391#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
1392#define CAU_RADR_CA_CA1_SHIFT (0U)
1393/*! CA1 - CA1
1394 */
1395#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
1396#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
1397#define CAU_RADR_CA_CA2_SHIFT (0U)
1398/*! CA2 - CA2
1399 */
1400#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
1401#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
1402#define CAU_RADR_CA_CA3_SHIFT (0U)
1403/*! CA3 - CA3
1404 */
1405#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
1406#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
1407#define CAU_RADR_CA_CA4_SHIFT (0U)
1408/*! CA4 - CA4
1409 */
1410#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
1411#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
1412#define CAU_RADR_CA_CA5_SHIFT (0U)
1413/*! CA5 - CA5
1414 */
1415#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
1416#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
1417#define CAU_RADR_CA_CA6_SHIFT (0U)
1418/*! CA6 - CA6
1419 */
1420#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
1421#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
1422#define CAU_RADR_CA_CA7_SHIFT (0U)
1423/*! CA7 - CA7
1424 */
1425#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
1426#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
1427#define CAU_RADR_CA_CA8_SHIFT (0U)
1428/*! CA8 - CA8
1429 */
1430#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
1431/*! @} */
1432
1433/* The count of CAU_RADR_CA */
1434#define CAU_RADR_CA_COUNT (9U)
1435
1436/*! @name XOR_CASR - Status register - Exclusive Or command */
1437/*! @{ */
1438#define CAU_XOR_CASR_IC_MASK (0x1U)
1439#define CAU_XOR_CASR_IC_SHIFT (0U)
1440/*! IC
1441 * 0b0..No illegal commands issued
1442 * 0b1..Illegal command issued
1443 */
1444#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
1445#define CAU_XOR_CASR_DPE_MASK (0x2U)
1446#define CAU_XOR_CASR_DPE_SHIFT (1U)
1447/*! DPE
1448 * 0b0..No error detected
1449 * 0b1..DES key parity error detected
1450 */
1451#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
1452#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
1453#define CAU_XOR_CASR_VER_SHIFT (28U)
1454/*! VER - CAU version
1455 * 0b0001..Initial CAU version
1456 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1457 */
1458#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
1459/*! @} */
1460
1461/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
1462/*! @{ */
1463#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
1464#define CAU_XOR_CAA_ACC_SHIFT (0U)
1465/*! ACC - ACC
1466 */
1467#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
1468/*! @} */
1469
1470/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command
1471 */
1472/*! @{ */
1473#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
1474#define CAU_XOR_CA_CA0_SHIFT (0U)
1475/*! CA0 - CA0
1476 */
1477#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
1478#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
1479#define CAU_XOR_CA_CA1_SHIFT (0U)
1480/*! CA1 - CA1
1481 */
1482#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
1483#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
1484#define CAU_XOR_CA_CA2_SHIFT (0U)
1485/*! CA2 - CA2
1486 */
1487#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
1488#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
1489#define CAU_XOR_CA_CA3_SHIFT (0U)
1490/*! CA3 - CA3
1491 */
1492#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
1493#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
1494#define CAU_XOR_CA_CA4_SHIFT (0U)
1495/*! CA4 - CA4
1496 */
1497#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
1498#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
1499#define CAU_XOR_CA_CA5_SHIFT (0U)
1500/*! CA5 - CA5
1501 */
1502#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
1503#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
1504#define CAU_XOR_CA_CA6_SHIFT (0U)
1505/*! CA6 - CA6
1506 */
1507#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
1508#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
1509#define CAU_XOR_CA_CA7_SHIFT (0U)
1510/*! CA7 - CA7
1511 */
1512#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
1513#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
1514#define CAU_XOR_CA_CA8_SHIFT (0U)
1515/*! CA8 - CA8
1516 */
1517#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
1518/*! @} */
1519
1520/* The count of CAU_XOR_CA */
1521#define CAU_XOR_CA_COUNT (9U)
1522
1523/*! @name ROTL_CASR - Status register - Rotate Left command */
1524/*! @{ */
1525#define CAU_ROTL_CASR_IC_MASK (0x1U)
1526#define CAU_ROTL_CASR_IC_SHIFT (0U)
1527/*! IC
1528 * 0b0..No illegal commands issued
1529 * 0b1..Illegal command issued
1530 */
1531#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
1532#define CAU_ROTL_CASR_DPE_MASK (0x2U)
1533#define CAU_ROTL_CASR_DPE_SHIFT (1U)
1534/*! DPE
1535 * 0b0..No error detected
1536 * 0b1..DES key parity error detected
1537 */
1538#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
1539#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
1540#define CAU_ROTL_CASR_VER_SHIFT (28U)
1541/*! VER - CAU version
1542 * 0b0001..Initial CAU version
1543 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1544 */
1545#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
1546/*! @} */
1547
1548/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
1549/*! @{ */
1550#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
1551#define CAU_ROTL_CAA_ACC_SHIFT (0U)
1552/*! ACC - ACC
1553 */
1554#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
1555/*! @} */
1556
1557/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command
1558 */
1559/*! @{ */
1560#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
1561#define CAU_ROTL_CA_CA0_SHIFT (0U)
1562/*! CA0 - CA0
1563 */
1564#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
1565#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
1566#define CAU_ROTL_CA_CA1_SHIFT (0U)
1567/*! CA1 - CA1
1568 */
1569#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
1570#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
1571#define CAU_ROTL_CA_CA2_SHIFT (0U)
1572/*! CA2 - CA2
1573 */
1574#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
1575#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
1576#define CAU_ROTL_CA_CA3_SHIFT (0U)
1577/*! CA3 - CA3
1578 */
1579#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
1580#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
1581#define CAU_ROTL_CA_CA4_SHIFT (0U)
1582/*! CA4 - CA4
1583 */
1584#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
1585#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
1586#define CAU_ROTL_CA_CA5_SHIFT (0U)
1587/*! CA5 - CA5
1588 */
1589#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
1590#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
1591#define CAU_ROTL_CA_CA6_SHIFT (0U)
1592/*! CA6 - CA6
1593 */
1594#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
1595#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
1596#define CAU_ROTL_CA_CA7_SHIFT (0U)
1597/*! CA7 - CA7
1598 */
1599#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
1600#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
1601#define CAU_ROTL_CA_CA8_SHIFT (0U)
1602/*! CA8 - CA8
1603 */
1604#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
1605/*! @} */
1606
1607/* The count of CAU_ROTL_CA */
1608#define CAU_ROTL_CA_COUNT (9U)
1609
1610/*! @name AESC_CASR - Status register - AES Column Operation command */
1611/*! @{ */
1612#define CAU_AESC_CASR_IC_MASK (0x1U)
1613#define CAU_AESC_CASR_IC_SHIFT (0U)
1614/*! IC
1615 * 0b0..No illegal commands issued
1616 * 0b1..Illegal command issued
1617 */
1618#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
1619#define CAU_AESC_CASR_DPE_MASK (0x2U)
1620#define CAU_AESC_CASR_DPE_SHIFT (1U)
1621/*! DPE
1622 * 0b0..No error detected
1623 * 0b1..DES key parity error detected
1624 */
1625#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
1626#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
1627#define CAU_AESC_CASR_VER_SHIFT (28U)
1628/*! VER - CAU version
1629 * 0b0001..Initial CAU version
1630 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1631 */
1632#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
1633/*! @} */
1634
1635/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
1636/*! @{ */
1637#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
1638#define CAU_AESC_CAA_ACC_SHIFT (0U)
1639/*! ACC - ACC
1640 */
1641#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
1642/*! @} */
1643
1644/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column
1645 * Operation command */
1646/*! @{ */
1647#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
1648#define CAU_AESC_CA_CA0_SHIFT (0U)
1649/*! CA0 - CA0
1650 */
1651#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
1652#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
1653#define CAU_AESC_CA_CA1_SHIFT (0U)
1654/*! CA1 - CA1
1655 */
1656#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
1657#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
1658#define CAU_AESC_CA_CA2_SHIFT (0U)
1659/*! CA2 - CA2
1660 */
1661#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
1662#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
1663#define CAU_AESC_CA_CA3_SHIFT (0U)
1664/*! CA3 - CA3
1665 */
1666#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
1667#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
1668#define CAU_AESC_CA_CA4_SHIFT (0U)
1669/*! CA4 - CA4
1670 */
1671#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
1672#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
1673#define CAU_AESC_CA_CA5_SHIFT (0U)
1674/*! CA5 - CA5
1675 */
1676#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
1677#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
1678#define CAU_AESC_CA_CA6_SHIFT (0U)
1679/*! CA6 - CA6
1680 */
1681#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
1682#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
1683#define CAU_AESC_CA_CA7_SHIFT (0U)
1684/*! CA7 - CA7
1685 */
1686#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
1687#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
1688#define CAU_AESC_CA_CA8_SHIFT (0U)
1689/*! CA8 - CA8
1690 */
1691#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
1692/*! @} */
1693
1694/* The count of CAU_AESC_CA */
1695#define CAU_AESC_CA_COUNT (9U)
1696
1697/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
1698/*! @{ */
1699#define CAU_AESIC_CASR_IC_MASK (0x1U)
1700#define CAU_AESIC_CASR_IC_SHIFT (0U)
1701/*! IC
1702 * 0b0..No illegal commands issued
1703 * 0b1..Illegal command issued
1704 */
1705#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
1706#define CAU_AESIC_CASR_DPE_MASK (0x2U)
1707#define CAU_AESIC_CASR_DPE_SHIFT (1U)
1708/*! DPE
1709 * 0b0..No error detected
1710 * 0b1..DES key parity error detected
1711 */
1712#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
1713#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
1714#define CAU_AESIC_CASR_VER_SHIFT (28U)
1715/*! VER - CAU version
1716 * 0b0001..Initial CAU version
1717 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
1718 */
1719#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
1720/*! @} */
1721
1722/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
1723/*! @{ */
1724#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
1725#define CAU_AESIC_CAA_ACC_SHIFT (0U)
1726/*! ACC - ACC
1727 */
1728#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
1729/*! @} */
1730
1731/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES
1732 * Inverse Column Operation command */
1733/*! @{ */
1734#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
1735#define CAU_AESIC_CA_CA0_SHIFT (0U)
1736/*! CA0 - CA0
1737 */
1738#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
1739#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
1740#define CAU_AESIC_CA_CA1_SHIFT (0U)
1741/*! CA1 - CA1
1742 */
1743#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
1744#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
1745#define CAU_AESIC_CA_CA2_SHIFT (0U)
1746/*! CA2 - CA2
1747 */
1748#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
1749#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
1750#define CAU_AESIC_CA_CA3_SHIFT (0U)
1751/*! CA3 - CA3
1752 */
1753#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
1754#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
1755#define CAU_AESIC_CA_CA4_SHIFT (0U)
1756/*! CA4 - CA4
1757 */
1758#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
1759#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
1760#define CAU_AESIC_CA_CA5_SHIFT (0U)
1761/*! CA5 - CA5
1762 */
1763#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
1764#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
1765#define CAU_AESIC_CA_CA6_SHIFT (0U)
1766/*! CA6 - CA6
1767 */
1768#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
1769#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
1770#define CAU_AESIC_CA_CA7_SHIFT (0U)
1771/*! CA7 - CA7
1772 */
1773#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
1774#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
1775#define CAU_AESIC_CA_CA8_SHIFT (0U)
1776/*! CA8 - CA8
1777 */
1778#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
1779/*! @} */
1780
1781/* The count of CAU_AESIC_CA */
1782#define CAU_AESIC_CA_COUNT (9U)
1783
1784/*!
1785 * @}
1786 */ /* end of group CAU_Register_Masks */
1787
1788/* CAU - Peripheral instance base addresses */
1789/** Peripheral CAU0 base address */
1790#define CAU0_BASE (0xF0005000u)
1791/** Peripheral CAU0 base pointer */
1792#define CAU0 ((CAU_Type *)CAU0_BASE)
1793/** Array initializer of CAU peripheral base addresses */
1794#define CAU_BASE_ADDRS \
1795 { \
1796 CAU0_BASE \
1797 }
1798/** Array initializer of CAU peripheral base pointers */
1799#define CAU_BASE_PTRS \
1800 { \
1801 CAU0 \
1802 }
1803
1804/*!
1805 * @}
1806 */ /* end of group CAU_Peripheral_Access_Layer */
1807
1808/* ----------------------------------------------------------------------------
1809 -- CMP Peripheral Access Layer
1810 ---------------------------------------------------------------------------- */
1811
1812/*!
1813 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
1814 * @{
1815 */
1816
1817/** CMP - Register Layout Typedef */
1818typedef struct
1819{
1820 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
1821 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
1822 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
1823 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
1824 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
1825 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
1826} CMP_Type;
1827
1828/* ----------------------------------------------------------------------------
1829 -- CMP Register Masks
1830 ---------------------------------------------------------------------------- */
1831
1832/*!
1833 * @addtogroup CMP_Register_Masks CMP Register Masks
1834 * @{
1835 */
1836
1837/*! @name CR0 - CMP Control Register 0 */
1838/*! @{ */
1839#define CMP_CR0_HYSTCTR_MASK (0x3U)
1840#define CMP_CR0_HYSTCTR_SHIFT (0U)
1841/*! HYSTCTR - Comparator hard block hysteresis control
1842 * 0b00..Level 0
1843 * 0b01..Level 1
1844 * 0b10..Level 2
1845 * 0b11..Level 3
1846 */
1847#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
1848#define CMP_CR0_FILTER_CNT_MASK (0x70U)
1849#define CMP_CR0_FILTER_CNT_SHIFT (4U)
1850/*! FILTER_CNT - Filter Sample Count
1851 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If
1852 * SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive
1853 * samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5
1854 * consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.
1855 */
1856#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
1857/*! @} */
1858
1859/*! @name CR1 - CMP Control Register 1 */
1860/*! @{ */
1861#define CMP_CR1_EN_MASK (0x1U)
1862#define CMP_CR1_EN_SHIFT (0U)
1863/*! EN - Comparator Module Enable
1864 * 0b0..Analog Comparator is disabled.
1865 * 0b1..Analog Comparator is enabled.
1866 */
1867#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
1868#define CMP_CR1_OPE_MASK (0x2U)
1869#define CMP_CR1_OPE_SHIFT (1U)
1870/*! OPE - Comparator Output Pin Enable
1871 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has
1872 * no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on
1873 * the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has
1874 * no effect.
1875 */
1876#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
1877#define CMP_CR1_COS_MASK (0x4U)
1878#define CMP_CR1_COS_SHIFT (2U)
1879/*! COS - Comparator Output Select
1880 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
1881 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
1882 */
1883#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
1884#define CMP_CR1_INV_MASK (0x8U)
1885#define CMP_CR1_INV_SHIFT (3U)
1886/*! INV - Comparator INVERT
1887 * 0b0..Does not invert the comparator output.
1888 * 0b1..Inverts the comparator output.
1889 */
1890#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
1891#define CMP_CR1_PMODE_MASK (0x10U)
1892#define CMP_CR1_PMODE_SHIFT (4U)
1893/*! PMODE - Power Mode Select
1894 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower
1895 * current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation
1896 * delay and higher current consumption.
1897 */
1898#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
1899#define CMP_CR1_TRIGM_MASK (0x20U)
1900#define CMP_CR1_TRIGM_SHIFT (5U)
1901/*! TRIGM - Trigger Mode Enable
1902 * 0b0..Trigger mode is disabled.
1903 * 0b1..Trigger mode is enabled.
1904 */
1905#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
1906#define CMP_CR1_WE_MASK (0x40U)
1907#define CMP_CR1_WE_SHIFT (6U)
1908/*! WE - Windowing Enable
1909 * 0b0..Windowing mode is not selected.
1910 * 0b1..Windowing mode is selected.
1911 */
1912#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
1913#define CMP_CR1_SE_MASK (0x80U)
1914#define CMP_CR1_SE_SHIFT (7U)
1915/*! SE - Sample Enable
1916 * 0b0..Sampling mode is not selected.
1917 * 0b1..Sampling mode is selected.
1918 */
1919#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
1920/*! @} */
1921
1922/*! @name FPR - CMP Filter Period Register */
1923/*! @{ */
1924#define CMP_FPR_FILT_PER_MASK (0xFFU)
1925#define CMP_FPR_FILT_PER_SHIFT (0U)
1926/*! FILT_PER - Filter Sample Period
1927 */
1928#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
1929/*! @} */
1930
1931/*! @name SCR - CMP Status and Control Register */
1932/*! @{ */
1933#define CMP_SCR_COUT_MASK (0x1U)
1934#define CMP_SCR_COUT_SHIFT (0U)
1935/*! COUT - Analog Comparator Output
1936 */
1937#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
1938#define CMP_SCR_CFF_MASK (0x2U)
1939#define CMP_SCR_CFF_SHIFT (1U)
1940/*! CFF - Analog Comparator Flag Falling
1941 * 0b0..Falling-edge on COUT has not been detected.
1942 * 0b1..Falling-edge on COUT has occurred.
1943 */
1944#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
1945#define CMP_SCR_CFR_MASK (0x4U)
1946#define CMP_SCR_CFR_SHIFT (2U)
1947/*! CFR - Analog Comparator Flag Rising
1948 * 0b0..Rising-edge on COUT has not been detected.
1949 * 0b1..Rising-edge on COUT has occurred.
1950 */
1951#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
1952#define CMP_SCR_IEF_MASK (0x8U)
1953#define CMP_SCR_IEF_SHIFT (3U)
1954/*! IEF - Comparator Interrupt Enable Falling
1955 * 0b0..Interrupt is disabled.
1956 * 0b1..Interrupt is enabled.
1957 */
1958#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
1959#define CMP_SCR_IER_MASK (0x10U)
1960#define CMP_SCR_IER_SHIFT (4U)
1961/*! IER - Comparator Interrupt Enable Rising
1962 * 0b0..Interrupt is disabled.
1963 * 0b1..Interrupt is enabled.
1964 */
1965#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
1966#define CMP_SCR_DMAEN_MASK (0x40U)
1967#define CMP_SCR_DMAEN_SHIFT (6U)
1968/*! DMAEN - DMA Enable Control
1969 * 0b0..DMA is disabled.
1970 * 0b1..DMA is enabled.
1971 */
1972#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
1973/*! @} */
1974
1975/*! @name DACCR - DAC Control Register */
1976/*! @{ */
1977#define CMP_DACCR_VOSEL_MASK (0x3FU)
1978#define CMP_DACCR_VOSEL_SHIFT (0U)
1979/*! VOSEL - DAC Output Voltage Select
1980 */
1981#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1982#define CMP_DACCR_VRSEL_MASK (0x40U)
1983#define CMP_DACCR_VRSEL_SHIFT (6U)
1984/*! VRSEL - Supply Voltage Reference Source Select
1985 * 0b0..Vin1 is selected as resistor ladder network supply reference.
1986 * 0b1..Vin2 is selected as resistor ladder network supply reference.
1987 */
1988#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
1989#define CMP_DACCR_DACEN_MASK (0x80U)
1990#define CMP_DACCR_DACEN_SHIFT (7U)
1991/*! DACEN - DAC Enable
1992 * 0b0..DAC is disabled.
1993 * 0b1..DAC is enabled.
1994 */
1995#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1996/*! @} */
1997
1998/*! @name MUXCR - MUX Control Register */
1999/*! @{ */
2000#define CMP_MUXCR_MSEL_MASK (0x7U)
2001#define CMP_MUXCR_MSEL_SHIFT (0U)
2002/*! MSEL - Minus Input Mux Control
2003 * 0b000..IN0
2004 * 0b001..IN1
2005 * 0b010..IN2
2006 * 0b011..IN3
2007 * 0b100..IN4
2008 * 0b101..IN5
2009 * 0b110..IN6
2010 * 0b111..IN7
2011 */
2012#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
2013#define CMP_MUXCR_PSEL_MASK (0x38U)
2014#define CMP_MUXCR_PSEL_SHIFT (3U)
2015/*! PSEL - Plus Input Mux Control
2016 * 0b000..IN0
2017 * 0b001..IN1
2018 * 0b010..IN2
2019 * 0b011..IN3
2020 * 0b100..IN4
2021 * 0b101..IN5
2022 * 0b110..IN6
2023 * 0b111..IN7
2024 */
2025#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
2026#define CMP_MUXCR_PSTM_MASK (0x80U)
2027#define CMP_MUXCR_PSTM_SHIFT (7U)
2028/*! PSTM - Pass Through Mode Enable
2029 * 0b0..Pass Through Mode is disabled.
2030 * 0b1..Pass Through Mode is enabled.
2031 */
2032#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
2033/*! @} */
2034
2035/*!
2036 * @}
2037 */ /* end of group CMP_Register_Masks */
2038
2039/* CMP - Peripheral instance base addresses */
2040/** Peripheral CMP0 base address */
2041#define CMP0_BASE (0x4006E000u)
2042/** Peripheral CMP0 base pointer */
2043#define CMP0 ((CMP_Type *)CMP0_BASE)
2044/** Peripheral CMP1 base address */
2045#define CMP1_BASE (0x400EF000u)
2046/** Peripheral CMP1 base pointer */
2047#define CMP1 ((CMP_Type *)CMP1_BASE)
2048/** Array initializer of CMP peripheral base addresses */
2049#define CMP_BASE_ADDRS \
2050 { \
2051 CMP0_BASE, CMP1_BASE \
2052 }
2053/** Array initializer of CMP peripheral base pointers */
2054#define CMP_BASE_PTRS \
2055 { \
2056 CMP0, CMP1 \
2057 }
2058/** Interrupt vectors for the CMP peripheral type */
2059#define CMP_IRQS \
2060 { \
2061 CMP0_IRQn, CMP1_IRQn \
2062 }
2063
2064/*!
2065 * @}
2066 */ /* end of group CMP_Peripheral_Access_Layer */
2067
2068/* ----------------------------------------------------------------------------
2069 -- CRC Peripheral Access Layer
2070 ---------------------------------------------------------------------------- */
2071
2072/*!
2073 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2074 * @{
2075 */
2076
2077/** CRC - Register Layout Typedef */
2078typedef struct
2079{
2080 union
2081 { /* offset: 0x0 */
2082 struct
2083 { /* offset: 0x0 */
2084 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
2085 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
2086 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
2087 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
2088 } ACCESS8BIT;
2089 struct
2090 { /* offset: 0x0 */
2091 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
2092 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
2093 } ACCESS16BIT;
2094 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
2095 };
2096 union
2097 { /* offset: 0x4 */
2098 struct
2099 { /* offset: 0x4 */
2100 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
2101 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
2102 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
2103 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
2104 } GPOLY_ACCESS8BIT;
2105 struct
2106 { /* offset: 0x4 */
2107 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
2108 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
2109 } GPOLY_ACCESS16BIT;
2110 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
2111 };
2112 union
2113 { /* offset: 0x8 */
2114 struct
2115 { /* offset: 0x8 */
2116 uint8_t RESERVED_0[3];
2117 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
2118 } CTRL_ACCESS8BIT;
2119 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
2120 };
2121} CRC_Type;
2122
2123/* ----------------------------------------------------------------------------
2124 -- CRC Register Masks
2125 ---------------------------------------------------------------------------- */
2126
2127/*!
2128 * @addtogroup CRC_Register_Masks CRC Register Masks
2129 * @{
2130 */
2131
2132/*! @name DATALL - CRC_DATALL register. */
2133/*! @{ */
2134#define CRC_DATALL_DATALL_MASK (0xFFU)
2135#define CRC_DATALL_DATALL_SHIFT (0U)
2136/*! DATALL - CRCLL stores the first 8 bits of the 32 bit DATA
2137 */
2138#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
2139/*! @} */
2140
2141/*! @name DATALU - CRC_DATALU register. */
2142/*! @{ */
2143#define CRC_DATALU_DATALU_MASK (0xFFU)
2144#define CRC_DATALU_DATALU_SHIFT (0U)
2145/*! DATALU - DATALL stores the second 8 bits of the 32 bit CRC
2146 */
2147#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
2148/*! @} */
2149
2150/*! @name DATAHL - CRC_DATAHL register. */
2151/*! @{ */
2152#define CRC_DATAHL_DATAHL_MASK (0xFFU)
2153#define CRC_DATAHL_DATAHL_SHIFT (0U)
2154/*! DATAHL - DATAHL stores the third 8 bits of the 32 bit CRC
2155 */
2156#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
2157/*! @} */
2158
2159/*! @name DATAHU - CRC_DATAHU register. */
2160/*! @{ */
2161#define CRC_DATAHU_DATAHU_MASK (0xFFU)
2162#define CRC_DATAHU_DATAHU_SHIFT (0U)
2163/*! DATAHU - DATAHU stores the fourth 8 bits of the 32 bit CRC
2164 */
2165#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
2166/*! @} */
2167
2168/*! @name DATAL - CRC_DATAL register. */
2169/*! @{ */
2170#define CRC_DATAL_DATAL_MASK (0xFFFFU)
2171#define CRC_DATAL_DATAL_SHIFT (0U)
2172/*! DATAL - DATAL stores the lower 16 bits of the 16/32 bit CRC
2173 */
2174#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
2175/*! @} */
2176
2177/*! @name DATAH - CRC_DATAH register. */
2178/*! @{ */
2179#define CRC_DATAH_DATAH_MASK (0xFFFFU)
2180#define CRC_DATAH_DATAH_SHIFT (0U)
2181/*! DATAH - DATAH stores the high 16 bits of the 16/32 bit CRC
2182 */
2183#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
2184/*! @} */
2185
2186/*! @name DATA - CRC Data register */
2187/*! @{ */
2188#define CRC_DATA_LL_MASK (0xFFU)
2189#define CRC_DATA_LL_SHIFT (0U)
2190/*! LL - CRC Low Lower Byte
2191 */
2192#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
2193#define CRC_DATA_LU_MASK (0xFF00U)
2194#define CRC_DATA_LU_SHIFT (8U)
2195/*! LU - CRC Low Upper Byte
2196 */
2197#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
2198#define CRC_DATA_HL_MASK (0xFF0000U)
2199#define CRC_DATA_HL_SHIFT (16U)
2200/*! HL - CRC High Lower Byte
2201 */
2202#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
2203#define CRC_DATA_HU_MASK (0xFF000000U)
2204#define CRC_DATA_HU_SHIFT (24U)
2205/*! HU - CRC High Upper Byte
2206 */
2207#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
2208/*! @} */
2209
2210/*! @name GPOLYLL - CRC_GPOLYLL register. */
2211/*! @{ */
2212#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
2213#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
2214/*! GPOLYLL - POLYLL stores the first 8 bits of the 32 bit CRC
2215 */
2216#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
2217/*! @} */
2218
2219/*! @name GPOLYLU - CRC_GPOLYLU register. */
2220/*! @{ */
2221#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
2222#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
2223/*! GPOLYLU - POLYLL stores the second 8 bits of the 32 bit CRC
2224 */
2225#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
2226/*! @} */
2227
2228/*! @name GPOLYHL - CRC_GPOLYHL register. */
2229/*! @{ */
2230#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
2231#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
2232/*! GPOLYHL - POLYHL stores the third 8 bits of the 32 bit CRC
2233 */
2234#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
2235/*! @} */
2236
2237/*! @name GPOLYHU - CRC_GPOLYHU register. */
2238/*! @{ */
2239#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
2240#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
2241/*! GPOLYHU - POLYHU stores the fourth 8 bits of the 32 bit CRC
2242 */
2243#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
2244/*! @} */
2245
2246/*! @name GPOLYL - CRC_GPOLYL register. */
2247/*! @{ */
2248#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
2249#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
2250/*! GPOLYL - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
2251 */
2252#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
2253/*! @} */
2254
2255/*! @name GPOLYH - CRC_GPOLYH register. */
2256/*! @{ */
2257#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
2258#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
2259/*! GPOLYH - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
2260 */
2261#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
2262/*! @} */
2263
2264/*! @name GPOLY - CRC Polynomial register */
2265/*! @{ */
2266#define CRC_GPOLY_LOW_MASK (0xFFFFU)
2267#define CRC_GPOLY_LOW_SHIFT (0U)
2268/*! LOW - Low Polynominal Half-word
2269 */
2270#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
2271#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
2272#define CRC_GPOLY_HIGH_SHIFT (16U)
2273/*! HIGH - High Polynominal Half-word
2274 */
2275#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
2276/*! @} */
2277
2278/*! @name CTRLHU - CRC_CTRLHU register. */
2279/*! @{ */
2280#define CRC_CTRLHU_TCRC_MASK (0x1U)
2281#define CRC_CTRLHU_TCRC_SHIFT (0U)
2282/*! TCRC
2283 * 0b0..16-bit CRC protocol.
2284 * 0b1..32-bit CRC protocol.
2285 */
2286#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
2287#define CRC_CTRLHU_WAS_MASK (0x2U)
2288#define CRC_CTRLHU_WAS_SHIFT (1U)
2289/*! WAS
2290 * 0b0..Writes to CRC data register are data values.
2291 * 0b1..Writes to CRC data reguster are seed values.
2292 */
2293#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
2294#define CRC_CTRLHU_FXOR_MASK (0x4U)
2295#define CRC_CTRLHU_FXOR_SHIFT (2U)
2296/*! FXOR
2297 * 0b0..No XOR on reading.
2298 * 0b1..Invert or complement the read value of CRC data register.
2299 */
2300#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
2301#define CRC_CTRLHU_TOTR_MASK (0x30U)
2302#define CRC_CTRLHU_TOTR_SHIFT (4U)
2303/*! TOTR
2304 * 0b00..No Transposition.
2305 * 0b01..Bits in bytes are transposed, bytes are not transposed.
2306 * 0b10..Both bits in bytes and bytes are transposed.
2307 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2308 */
2309#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
2310#define CRC_CTRLHU_TOT_MASK (0xC0U)
2311#define CRC_CTRLHU_TOT_SHIFT (6U)
2312/*! TOT
2313 * 0b00..No Transposition.
2314 * 0b01..Bits in bytes are transposed, bytes are not transposed.
2315 * 0b10..Both bits in bytes and bytes are transposed.
2316 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2317 */
2318#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
2319/*! @} */
2320
2321/*! @name CTRL - CRC Control register */
2322/*! @{ */
2323#define CRC_CTRL_TCRC_MASK (0x1000000U)
2324#define CRC_CTRL_TCRC_SHIFT (24U)
2325/*! TCRC
2326 * 0b0..16-bit CRC protocol.
2327 * 0b1..32-bit CRC protocol.
2328 */
2329#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
2330#define CRC_CTRL_WAS_MASK (0x2000000U)
2331#define CRC_CTRL_WAS_SHIFT (25U)
2332/*! WAS - Write CRC Data Register As Seed
2333 * 0b0..Writes to the CRC data register are data values.
2334 * 0b1..Writes to the CRC data register are seed values.
2335 */
2336#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
2337#define CRC_CTRL_FXOR_MASK (0x4000000U)
2338#define CRC_CTRL_FXOR_SHIFT (26U)
2339/*! FXOR - Complement Read Of CRC Data Register
2340 * 0b0..No XOR on reading.
2341 * 0b1..Invert or complement the read value of the CRC Data register.
2342 */
2343#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
2344#define CRC_CTRL_TOTR_MASK (0x30000000U)
2345#define CRC_CTRL_TOTR_SHIFT (28U)
2346/*! TOTR - Type Of Transpose For Read
2347 * 0b00..No transposition.
2348 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2349 * 0b10..Both bits in bytes and bytes are transposed.
2350 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2351 */
2352#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
2353#define CRC_CTRL_TOT_MASK (0xC0000000U)
2354#define CRC_CTRL_TOT_SHIFT (30U)
2355/*! TOT - Type Of Transpose For Writes
2356 * 0b00..No transposition.
2357 * 0b01..Bits in bytes are transposed; bytes are not transposed.
2358 * 0b10..Both bits in bytes and bytes are transposed.
2359 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
2360 */
2361#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
2362/*! @} */
2363
2364/*!
2365 * @}
2366 */ /* end of group CRC_Register_Masks */
2367
2368/* CRC - Peripheral instance base addresses */
2369/** Peripheral CRC base address */
2370#define CRC_BASE (0x40078000u)
2371/** Peripheral CRC base pointer */
2372#define CRC0 ((CRC_Type *)CRC_BASE)
2373/** Array initializer of CRC peripheral base addresses */
2374#define CRC_BASE_ADDRS \
2375 { \
2376 CRC_BASE \
2377 }
2378/** Array initializer of CRC peripheral base pointers */
2379#define CRC_BASE_PTRS \
2380 { \
2381 CRC0 \
2382 }
2383
2384/*!
2385 * @}
2386 */ /* end of group CRC_Peripheral_Access_Layer */
2387
2388/* ----------------------------------------------------------------------------
2389 -- DAC Peripheral Access Layer
2390 ---------------------------------------------------------------------------- */
2391
2392/*!
2393 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
2394 * @{
2395 */
2396
2397/** DAC - Register Layout Typedef */
2398typedef struct
2399{
2400 struct
2401 { /* offset: 0x0, array step: 0x2 */
2402 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
2403 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
2404 } DAT[16];
2405 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
2406 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
2407 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
2408 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
2409} DAC_Type;
2410
2411/* ----------------------------------------------------------------------------
2412 -- DAC Register Masks
2413 ---------------------------------------------------------------------------- */
2414
2415/*!
2416 * @addtogroup DAC_Register_Masks DAC Register Masks
2417 * @{
2418 */
2419
2420/*! @name DATL - DAC Data Low Register */
2421/*! @{ */
2422#define DAC_DATL_DATA0_MASK (0xFFU)
2423#define DAC_DATL_DATA0_SHIFT (0U)
2424/*! DATA0 - DATA0
2425 */
2426#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
2427/*! @} */
2428
2429/* The count of DAC_DATL */
2430#define DAC_DATL_COUNT (16U)
2431
2432/*! @name DATH - DAC Data High Register */
2433/*! @{ */
2434#define DAC_DATH_DATA1_MASK (0xFU)
2435#define DAC_DATH_DATA1_SHIFT (0U)
2436/*! DATA1 - DATA1
2437 */
2438#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
2439/*! @} */
2440
2441/* The count of DAC_DATH */
2442#define DAC_DATH_COUNT (16U)
2443
2444/*! @name SR - DAC Status Register */
2445/*! @{ */
2446#define DAC_SR_DACBFRPBF_MASK (0x1U)
2447#define DAC_SR_DACBFRPBF_SHIFT (0U)
2448/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
2449 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
2450 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
2451 */
2452#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
2453#define DAC_SR_DACBFRPTF_MASK (0x2U)
2454#define DAC_SR_DACBFRPTF_SHIFT (1U)
2455/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
2456 * 0b0..The DAC buffer read pointer is not zero.
2457 * 0b1..The DAC buffer read pointer is zero.
2458 */
2459#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
2460#define DAC_SR_DACBFWMF_MASK (0x4U)
2461#define DAC_SR_DACBFWMF_SHIFT (2U)
2462/*! DACBFWMF - DAC Buffer Watermark Flag
2463 * 0b0..The DAC buffer read pointer has not reached the watermark level.
2464 * 0b1..The DAC buffer read pointer has reached the watermark level.
2465 */
2466#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
2467/*! @} */
2468
2469/*! @name C0 - DAC Control Register */
2470/*! @{ */
2471#define DAC_C0_DACBBIEN_MASK (0x1U)
2472#define DAC_C0_DACBBIEN_SHIFT (0U)
2473/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
2474 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
2475 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
2476 */
2477#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
2478#define DAC_C0_DACBTIEN_MASK (0x2U)
2479#define DAC_C0_DACBTIEN_SHIFT (1U)
2480/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
2481 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
2482 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
2483 */
2484#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
2485#define DAC_C0_DACBWIEN_MASK (0x4U)
2486#define DAC_C0_DACBWIEN_SHIFT (2U)
2487/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
2488 * 0b0..The DAC buffer watermark interrupt is disabled.
2489 * 0b1..The DAC buffer watermark interrupt is enabled.
2490 */
2491#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
2492#define DAC_C0_LPEN_MASK (0x8U)
2493#define DAC_C0_LPEN_SHIFT (3U)
2494/*! LPEN - DAC Low Power Control
2495 * 0b0..High-Power mode
2496 * 0b1..Low-Power mode
2497 */
2498#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
2499#define DAC_C0_DACSWTRG_MASK (0x10U)
2500#define DAC_C0_DACSWTRG_SHIFT (4U)
2501/*! DACSWTRG - DAC Software Trigger
2502 * 0b0..The DAC soft trigger is not valid.
2503 * 0b1..The DAC soft trigger is valid.
2504 */
2505#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
2506#define DAC_C0_DACTRGSEL_MASK (0x20U)
2507#define DAC_C0_DACTRGSEL_SHIFT (5U)
2508/*! DACTRGSEL - DAC Trigger Select
2509 * 0b0..The DAC hardware trigger is selected.
2510 * 0b1..The DAC software trigger is selected.
2511 */
2512#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
2513#define DAC_C0_DACRFS_MASK (0x40U)
2514#define DAC_C0_DACRFS_SHIFT (6U)
2515/*! DACRFS - DAC Reference Select
2516 * 0b0..The DAC selects DACREF_1 as the reference voltage.
2517 * 0b1..The DAC selects DACREF_2 as the reference voltage.
2518 */
2519#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
2520#define DAC_C0_DACEN_MASK (0x80U)
2521#define DAC_C0_DACEN_SHIFT (7U)
2522/*! DACEN - DAC Enable
2523 * 0b0..The DAC system is disabled.
2524 * 0b1..The DAC system is enabled.
2525 */
2526#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
2527/*! @} */
2528
2529/*! @name C1 - DAC Control Register 1 */
2530/*! @{ */
2531#define DAC_C1_DACBFEN_MASK (0x1U)
2532#define DAC_C1_DACBFEN_SHIFT (0U)
2533/*! DACBFEN - DAC Buffer Enable
2534 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
2535 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means
2536 * converted data can be from any word of the buffer.
2537 */
2538#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
2539#define DAC_C1_DACBFMD_MASK (0x6U)
2540#define DAC_C1_DACBFMD_SHIFT (1U)
2541/*! DACBFMD - DAC Buffer Work Mode Select
2542 * 0b00..Normal mode
2543 * 0b01..Swing mode
2544 * 0b10..One-Time Scan mode
2545 * 0b11..Reserved
2546 */
2547#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
2548#define DAC_C1_DACBFWM_MASK (0x18U)
2549#define DAC_C1_DACBFWM_SHIFT (3U)
2550/*! DACBFWM - DAC Buffer Watermark Select
2551 * 0b00..1 word
2552 * 0b01..2 words
2553 * 0b10..3 words
2554 * 0b11..4 words
2555 */
2556#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
2557#define DAC_C1_DMAEN_MASK (0x80U)
2558#define DAC_C1_DMAEN_SHIFT (7U)
2559/*! DMAEN - DMA Enable Select
2560 * 0b0..DMA is disabled.
2561 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
2562 * interrupts will not be presented on this module at the same time.
2563 */
2564#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
2565/*! @} */
2566
2567/*! @name C2 - DAC Control Register 2 */
2568/*! @{ */
2569#define DAC_C2_DACBFUP_MASK (0xFU)
2570#define DAC_C2_DACBFUP_SHIFT (0U)
2571/*! DACBFUP - DAC Buffer Upper Limit
2572 */
2573#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
2574#define DAC_C2_DACBFRP_MASK (0xF0U)
2575#define DAC_C2_DACBFRP_SHIFT (4U)
2576/*! DACBFRP - DAC Buffer Read Pointer
2577 */
2578#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
2579/*! @} */
2580
2581/*!
2582 * @}
2583 */ /* end of group DAC_Register_Masks */
2584
2585/* DAC - Peripheral instance base addresses */
2586/** Peripheral DAC0 base address */
2587#define DAC0_BASE (0x4006A000u)
2588/** Peripheral DAC0 base pointer */
2589#define DAC0 ((DAC_Type *)DAC0_BASE)
2590/** Array initializer of DAC peripheral base addresses */
2591#define DAC_BASE_ADDRS \
2592 { \
2593 DAC0_BASE \
2594 }
2595/** Array initializer of DAC peripheral base pointers */
2596#define DAC_BASE_PTRS \
2597 { \
2598 DAC0 \
2599 }
2600/** Interrupt vectors for the DAC peripheral type */
2601#define DAC_IRQS \
2602 { \
2603 DAC0_IRQn \
2604 }
2605
2606/*!
2607 * @}
2608 */ /* end of group DAC_Peripheral_Access_Layer */
2609
2610/* ----------------------------------------------------------------------------
2611 -- DMA Peripheral Access Layer
2612 ---------------------------------------------------------------------------- */
2613
2614/*!
2615 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
2616 * @{
2617 */
2618
2619/** DMA - Register Layout Typedef */
2620typedef struct
2621{
2622 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
2623 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
2624 uint8_t RESERVED_0[4];
2625 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
2626 uint8_t RESERVED_1[4];
2627 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
2628 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
2629 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
2630 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
2631 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2632 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
2633 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
2634 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
2635 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
2636 uint8_t RESERVED_2[4];
2637 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
2638 uint8_t RESERVED_3[4];
2639 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
2640 uint8_t RESERVED_4[4];
2641 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
2642 uint8_t RESERVED_5[12];
2643 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
2644 uint8_t RESERVED_6[184];
2645 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
2646 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
2647 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
2648 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
2649 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
2650 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
2651 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
2652 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
2653 uint8_t RESERVED_7[3832];
2654 struct
2655 { /* offset: 0x1000, array step: 0x20 */
2656 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
2657 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
2658 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
2659 union
2660 { /* offset: 0x1008, array step: 0x20 */
2661 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008,
2662 array step: 0x20 */
2663 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset
2664 Disabled), array offset: 0x1008, array step: 0x20 */
2665 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled),
2666 array offset: 0x1008, array step: 0x20 */
2667 };
2668 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
2669 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
2670 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
2671 union
2672 { /* offset: 0x1016, array step: 0x20 */
2673 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled),
2674 array offset: 0x1016, array step: 0x20 */
2675 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled),
2676 array offset: 0x1016, array step: 0x20 */
2677 };
2678 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset:
2679 0x1018, array step: 0x20 */
2680 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
2681 union
2682 { /* offset: 0x101E, array step: 0x20 */
2683 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
2684 Disabled), array offset: 0x101E, array step: 0x20 */
2685 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking
2686 Enabled), array offset: 0x101E, array step: 0x20 */
2687 };
2688 } TCD[8];
2689} DMA_Type;
2690
2691/* ----------------------------------------------------------------------------
2692 -- DMA Register Masks
2693 ---------------------------------------------------------------------------- */
2694
2695/*!
2696 * @addtogroup DMA_Register_Masks DMA Register Masks
2697 * @{
2698 */
2699
2700/*! @name CR - Control Register */
2701/*! @{ */
2702#define DMA_CR_EDBG_MASK (0x2U)
2703#define DMA_CR_EDBG_SHIFT (1U)
2704/*! EDBG - Enable Debug
2705 * 0b0..When in debug mode, the DMA continues to operate.
2706 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
2707 * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
2708 */
2709#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
2710#define DMA_CR_ERCA_MASK (0x4U)
2711#define DMA_CR_ERCA_SHIFT (2U)
2712/*! ERCA - Enable Round Robin Channel Arbitration
2713 * 0b0..Fixed priority arbitration is used for channel selection .
2714 * 0b1..Round robin arbitration is used for channel selection .
2715 */
2716#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
2717#define DMA_CR_HOE_MASK (0x10U)
2718#define DMA_CR_HOE_SHIFT (4U)
2719/*! HOE - Halt On Error
2720 * 0b0..Normal operation
2721 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is
2722 * cleared.
2723 */
2724#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
2725#define DMA_CR_HALT_MASK (0x20U)
2726#define DMA_CR_HALT_SHIFT (5U)
2727/*! HALT - Halt DMA Operations
2728 * 0b0..Normal operation
2729 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when
2730 * this bit is cleared.
2731 */
2732#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
2733#define DMA_CR_CLM_MASK (0x40U)
2734#define DMA_CR_CLM_SHIFT (6U)
2735/*! CLM - Continuous Link Mode
2736 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
2737 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
2738 * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
2739 * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
2740 * next minor loop.
2741 */
2742#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
2743#define DMA_CR_EMLM_MASK (0x80U)
2744#define DMA_CR_EMLM_SHIFT (7U)
2745/*! EMLM - Enable Minor Loop Mapping
2746 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
2747 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
2748 * field. The individual enable fields allow the minor loop offset to be applied to the source address, the
2749 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
2750 */
2751#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
2752#define DMA_CR_ECX_MASK (0x10000U)
2753#define DMA_CR_ECX_SHIFT (16U)
2754/*! ECX - Error Cancel Transfer
2755 * 0b0..Normal operation
2756 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
2757 * force the minor loop to finish. The cancel takes effect after the last write of the current read/write
2758 * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
2759 * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
2760 * optional error interrupt.
2761 */
2762#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
2763#define DMA_CR_CX_MASK (0x20000U)
2764#define DMA_CR_CX_SHIFT (17U)
2765/*! CX - Cancel Transfer
2766 * 0b0..Normal operation
2767 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
2768 * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
2769 * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
2770 */
2771#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
2772#define DMA_CR_ACTIVE_MASK (0x80000000U)
2773#define DMA_CR_ACTIVE_SHIFT (31U)
2774/*! ACTIVE - DMA Active Status
2775 * 0b0..eDMA is idle.
2776 * 0b1..eDMA is executing a channel.
2777 */
2778#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
2779/*! @} */
2780
2781/*! @name ES - Error Status Register */
2782/*! @{ */
2783#define DMA_ES_DBE_MASK (0x1U)
2784#define DMA_ES_DBE_SHIFT (0U)
2785/*! DBE - Destination Bus Error
2786 * 0b0..No destination bus error
2787 * 0b1..The last recorded error was a bus error on a destination write
2788 */
2789#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
2790#define DMA_ES_SBE_MASK (0x2U)
2791#define DMA_ES_SBE_SHIFT (1U)
2792/*! SBE - Source Bus Error
2793 * 0b0..No source bus error
2794 * 0b1..The last recorded error was a bus error on a source read
2795 */
2796#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
2797#define DMA_ES_SGE_MASK (0x4U)
2798#define DMA_ES_SGE_SHIFT (2U)
2799/*! SGE - Scatter/Gather Configuration Error
2800 * 0b0..No scatter/gather configuration error
2801 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
2802 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
2803 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
2804 */
2805#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
2806#define DMA_ES_NCE_MASK (0x8U)
2807#define DMA_ES_NCE_SHIFT (3U)
2808/*! NCE - NBYTES/CITER Configuration Error
2809 * 0b0..No NBYTES/CITER configuration error
2810 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
2811 * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
2812 * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
2813 */
2814#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
2815#define DMA_ES_DOE_MASK (0x10U)
2816#define DMA_ES_DOE_SHIFT (4U)
2817/*! DOE - Destination Offset Error
2818 * 0b0..No destination offset configuration error
2819 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent
2820 * with TCDn_ATTR[DSIZE].
2821 */
2822#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
2823#define DMA_ES_DAE_MASK (0x20U)
2824#define DMA_ES_DAE_SHIFT (5U)
2825/*! DAE - Destination Address Error
2826 * 0b0..No destination address configuration error
2827 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent
2828 * with TCDn_ATTR[DSIZE].
2829 */
2830#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
2831#define DMA_ES_SOE_MASK (0x40U)
2832#define DMA_ES_SOE_SHIFT (6U)
2833/*! SOE - Source Offset Error
2834 * 0b0..No source offset configuration error
2835 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent
2836 * with TCDn_ATTR[SSIZE].
2837 */
2838#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
2839#define DMA_ES_SAE_MASK (0x80U)
2840#define DMA_ES_SAE_SHIFT (7U)
2841/*! SAE - Source Address Error
2842 * 0b0..No source address configuration error.
2843 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent
2844 * with TCDn_ATTR[SSIZE].
2845 */
2846#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
2847#define DMA_ES_ERRCHN_MASK (0x700U)
2848#define DMA_ES_ERRCHN_SHIFT (8U)
2849/*! ERRCHN - Error Channel Number or Canceled Channel Number
2850 */
2851#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
2852#define DMA_ES_CPE_MASK (0x4000U)
2853#define DMA_ES_CPE_SHIFT (14U)
2854/*! CPE - Channel Priority Error
2855 * 0b0..No channel priority error
2856 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not
2857 * unique.
2858 */
2859#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
2860#define DMA_ES_ECX_MASK (0x10000U)
2861#define DMA_ES_ECX_SHIFT (16U)
2862/*! ECX - Transfer Canceled
2863 * 0b0..No canceled transfers
2864 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
2865 */
2866#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
2867#define DMA_ES_VLD_MASK (0x80000000U)
2868#define DMA_ES_VLD_SHIFT (31U)
2869/*! VLD
2870 * 0b0..No ERR bits are set.
2871 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
2872 */
2873#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
2874/*! @} */
2875
2876/*! @name ERQ - Enable Request Register */
2877/*! @{ */
2878#define DMA_ERQ_ERQ0_MASK (0x1U)
2879#define DMA_ERQ_ERQ0_SHIFT (0U)
2880/*! ERQ0 - Enable DMA Request 0
2881 * 0b0..The DMA request signal for the corresponding channel is disabled
2882 * 0b1..The DMA request signal for the corresponding channel is enabled
2883 */
2884#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
2885#define DMA_ERQ_ERQ1_MASK (0x2U)
2886#define DMA_ERQ_ERQ1_SHIFT (1U)
2887/*! ERQ1 - Enable DMA Request 1
2888 * 0b0..The DMA request signal for the corresponding channel is disabled
2889 * 0b1..The DMA request signal for the corresponding channel is enabled
2890 */
2891#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
2892#define DMA_ERQ_ERQ2_MASK (0x4U)
2893#define DMA_ERQ_ERQ2_SHIFT (2U)
2894/*! ERQ2 - Enable DMA Request 2
2895 * 0b0..The DMA request signal for the corresponding channel is disabled
2896 * 0b1..The DMA request signal for the corresponding channel is enabled
2897 */
2898#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
2899#define DMA_ERQ_ERQ3_MASK (0x8U)
2900#define DMA_ERQ_ERQ3_SHIFT (3U)
2901/*! ERQ3 - Enable DMA Request 3
2902 * 0b0..The DMA request signal for the corresponding channel is disabled
2903 * 0b1..The DMA request signal for the corresponding channel is enabled
2904 */
2905#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
2906#define DMA_ERQ_ERQ4_MASK (0x10U)
2907#define DMA_ERQ_ERQ4_SHIFT (4U)
2908/*! ERQ4 - Enable DMA Request 4
2909 * 0b0..The DMA request signal for the corresponding channel is disabled
2910 * 0b1..The DMA request signal for the corresponding channel is enabled
2911 */
2912#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
2913#define DMA_ERQ_ERQ5_MASK (0x20U)
2914#define DMA_ERQ_ERQ5_SHIFT (5U)
2915/*! ERQ5 - Enable DMA Request 5
2916 * 0b0..The DMA request signal for the corresponding channel is disabled
2917 * 0b1..The DMA request signal for the corresponding channel is enabled
2918 */
2919#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
2920#define DMA_ERQ_ERQ6_MASK (0x40U)
2921#define DMA_ERQ_ERQ6_SHIFT (6U)
2922/*! ERQ6 - Enable DMA Request 6
2923 * 0b0..The DMA request signal for the corresponding channel is disabled
2924 * 0b1..The DMA request signal for the corresponding channel is enabled
2925 */
2926#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
2927#define DMA_ERQ_ERQ7_MASK (0x80U)
2928#define DMA_ERQ_ERQ7_SHIFT (7U)
2929/*! ERQ7 - Enable DMA Request 7
2930 * 0b0..The DMA request signal for the corresponding channel is disabled
2931 * 0b1..The DMA request signal for the corresponding channel is enabled
2932 */
2933#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
2934/*! @} */
2935
2936/*! @name EEI - Enable Error Interrupt Register */
2937/*! @{ */
2938#define DMA_EEI_EEI0_MASK (0x1U)
2939#define DMA_EEI_EEI0_SHIFT (0U)
2940/*! EEI0 - Enable Error Interrupt 0
2941 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2942 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2943 */
2944#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
2945#define DMA_EEI_EEI1_MASK (0x2U)
2946#define DMA_EEI_EEI1_SHIFT (1U)
2947/*! EEI1 - Enable Error Interrupt 1
2948 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2949 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2950 */
2951#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
2952#define DMA_EEI_EEI2_MASK (0x4U)
2953#define DMA_EEI_EEI2_SHIFT (2U)
2954/*! EEI2 - Enable Error Interrupt 2
2955 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2956 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2957 */
2958#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
2959#define DMA_EEI_EEI3_MASK (0x8U)
2960#define DMA_EEI_EEI3_SHIFT (3U)
2961/*! EEI3 - Enable Error Interrupt 3
2962 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2963 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2964 */
2965#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
2966#define DMA_EEI_EEI4_MASK (0x10U)
2967#define DMA_EEI_EEI4_SHIFT (4U)
2968/*! EEI4 - Enable Error Interrupt 4
2969 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2970 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2971 */
2972#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
2973#define DMA_EEI_EEI5_MASK (0x20U)
2974#define DMA_EEI_EEI5_SHIFT (5U)
2975/*! EEI5 - Enable Error Interrupt 5
2976 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2977 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2978 */
2979#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
2980#define DMA_EEI_EEI6_MASK (0x40U)
2981#define DMA_EEI_EEI6_SHIFT (6U)
2982/*! EEI6 - Enable Error Interrupt 6
2983 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2984 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2985 */
2986#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
2987#define DMA_EEI_EEI7_MASK (0x80U)
2988#define DMA_EEI_EEI7_SHIFT (7U)
2989/*! EEI7 - Enable Error Interrupt 7
2990 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2991 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2992 */
2993#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
2994/*! @} */
2995
2996/*! @name CEEI - Clear Enable Error Interrupt Register */
2997/*! @{ */
2998#define DMA_CEEI_CEEI_MASK (0x7U)
2999#define DMA_CEEI_CEEI_SHIFT (0U)
3000/*! CEEI - Clear Enable Error Interrupt
3001 */
3002#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
3003#define DMA_CEEI_CAEE_MASK (0x40U)
3004#define DMA_CEEI_CAEE_SHIFT (6U)
3005/*! CAEE - Clear All Enable Error Interrupts
3006 * 0b0..Clear only the EEI bit specified in the CEEI field
3007 * 0b1..Clear all bits in EEI
3008 */
3009#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
3010#define DMA_CEEI_NOP_MASK (0x80U)
3011#define DMA_CEEI_NOP_SHIFT (7U)
3012/*! NOP - No Op enable
3013 * 0b0..Normal operation
3014 * 0b1..No operation, ignore the other bits in this register
3015 */
3016#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
3017/*! @} */
3018
3019/*! @name SEEI - Set Enable Error Interrupt Register */
3020/*! @{ */
3021#define DMA_SEEI_SEEI_MASK (0x7U)
3022#define DMA_SEEI_SEEI_SHIFT (0U)
3023/*! SEEI - Set Enable Error Interrupt
3024 */
3025#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
3026#define DMA_SEEI_SAEE_MASK (0x40U)
3027#define DMA_SEEI_SAEE_SHIFT (6U)
3028/*! SAEE - Sets All Enable Error Interrupts
3029 * 0b0..Set only the EEI bit specified in the SEEI field.
3030 * 0b1..Sets all bits in EEI
3031 */
3032#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
3033#define DMA_SEEI_NOP_MASK (0x80U)
3034#define DMA_SEEI_NOP_SHIFT (7U)
3035/*! NOP - No Op enable
3036 * 0b0..Normal operation
3037 * 0b1..No operation, ignore the other bits in this register
3038 */
3039#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
3040/*! @} */
3041
3042/*! @name CERQ - Clear Enable Request Register */
3043/*! @{ */
3044#define DMA_CERQ_CERQ_MASK (0x7U)
3045#define DMA_CERQ_CERQ_SHIFT (0U)
3046/*! CERQ - Clear Enable Request
3047 */
3048#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
3049#define DMA_CERQ_CAER_MASK (0x40U)
3050#define DMA_CERQ_CAER_SHIFT (6U)
3051/*! CAER - Clear All Enable Requests
3052 * 0b0..Clear only the ERQ bit specified in the CERQ field
3053 * 0b1..Clear all bits in ERQ
3054 */
3055#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
3056#define DMA_CERQ_NOP_MASK (0x80U)
3057#define DMA_CERQ_NOP_SHIFT (7U)
3058/*! NOP - No Op enable
3059 * 0b0..Normal operation
3060 * 0b1..No operation, ignore the other bits in this register
3061 */
3062#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
3063/*! @} */
3064
3065/*! @name SERQ - Set Enable Request Register */
3066/*! @{ */
3067#define DMA_SERQ_SERQ_MASK (0x7U)
3068#define DMA_SERQ_SERQ_SHIFT (0U)
3069/*! SERQ - Set Enable Request
3070 */
3071#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
3072#define DMA_SERQ_SAER_MASK (0x40U)
3073#define DMA_SERQ_SAER_SHIFT (6U)
3074/*! SAER - Set All Enable Requests
3075 * 0b0..Set only the ERQ bit specified in the SERQ field
3076 * 0b1..Set all bits in ERQ
3077 */
3078#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
3079#define DMA_SERQ_NOP_MASK (0x80U)
3080#define DMA_SERQ_NOP_SHIFT (7U)
3081/*! NOP - No Op enable
3082 * 0b0..Normal operation
3083 * 0b1..No operation, ignore the other bits in this register
3084 */
3085#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
3086/*! @} */
3087
3088/*! @name CDNE - Clear DONE Status Bit Register */
3089/*! @{ */
3090#define DMA_CDNE_CDNE_MASK (0x7U)
3091#define DMA_CDNE_CDNE_SHIFT (0U)
3092/*! CDNE - Clear DONE Bit
3093 */
3094#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
3095#define DMA_CDNE_CADN_MASK (0x40U)
3096#define DMA_CDNE_CADN_SHIFT (6U)
3097/*! CADN - Clears All DONE Bits
3098 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
3099 * 0b1..Clears all bits in TCDn_CSR[DONE]
3100 */
3101#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
3102#define DMA_CDNE_NOP_MASK (0x80U)
3103#define DMA_CDNE_NOP_SHIFT (7U)
3104/*! NOP - No Op enable
3105 * 0b0..Normal operation
3106 * 0b1..No operation, ignore the other bits in this register
3107 */
3108#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
3109/*! @} */
3110
3111/*! @name SSRT - Set START Bit Register */
3112/*! @{ */
3113#define DMA_SSRT_SSRT_MASK (0x7U)
3114#define DMA_SSRT_SSRT_SHIFT (0U)
3115/*! SSRT - Set START Bit
3116 */
3117#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
3118#define DMA_SSRT_SAST_MASK (0x40U)
3119#define DMA_SSRT_SAST_SHIFT (6U)
3120/*! SAST - Set All START Bits (activates all channels)
3121 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
3122 * 0b1..Set all bits in TCDn_CSR[START]
3123 */
3124#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
3125#define DMA_SSRT_NOP_MASK (0x80U)
3126#define DMA_SSRT_NOP_SHIFT (7U)
3127/*! NOP - No Op enable
3128 * 0b0..Normal operation
3129 * 0b1..No operation, ignore the other bits in this register
3130 */
3131#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
3132/*! @} */
3133
3134/*! @name CERR - Clear Error Register */
3135/*! @{ */
3136#define DMA_CERR_CERR_MASK (0x7U)
3137#define DMA_CERR_CERR_SHIFT (0U)
3138/*! CERR - Clear Error Indicator
3139 */
3140#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
3141#define DMA_CERR_CAEI_MASK (0x40U)
3142#define DMA_CERR_CAEI_SHIFT (6U)
3143/*! CAEI - Clear All Error Indicators
3144 * 0b0..Clear only the ERR bit specified in the CERR field
3145 * 0b1..Clear all bits in ERR
3146 */
3147#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
3148#define DMA_CERR_NOP_MASK (0x80U)
3149#define DMA_CERR_NOP_SHIFT (7U)
3150/*! NOP - No Op enable
3151 * 0b0..Normal operation
3152 * 0b1..No operation, ignore the other bits in this register
3153 */
3154#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
3155/*! @} */
3156
3157/*! @name CINT - Clear Interrupt Request Register */
3158/*! @{ */
3159#define DMA_CINT_CINT_MASK (0x7U)
3160#define DMA_CINT_CINT_SHIFT (0U)
3161/*! CINT - Clear Interrupt Request
3162 */
3163#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
3164#define DMA_CINT_CAIR_MASK (0x40U)
3165#define DMA_CINT_CAIR_SHIFT (6U)
3166/*! CAIR - Clear All Interrupt Requests
3167 * 0b0..Clear only the INT bit specified in the CINT field
3168 * 0b1..Clear all bits in INT
3169 */
3170#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
3171#define DMA_CINT_NOP_MASK (0x80U)
3172#define DMA_CINT_NOP_SHIFT (7U)
3173/*! NOP - No Op enable
3174 * 0b0..Normal operation
3175 * 0b1..No operation, ignore the other bits in this register
3176 */
3177#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
3178/*! @} */
3179
3180/*! @name INT - Interrupt Request Register */
3181/*! @{ */
3182#define DMA_INT_INT0_MASK (0x1U)
3183#define DMA_INT_INT0_SHIFT (0U)
3184/*! INT0 - Interrupt Request 0
3185 * 0b0..The interrupt request for corresponding channel is cleared
3186 * 0b1..The interrupt request for corresponding channel is active
3187 */
3188#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
3189#define DMA_INT_INT1_MASK (0x2U)
3190#define DMA_INT_INT1_SHIFT (1U)
3191/*! INT1 - Interrupt Request 1
3192 * 0b0..The interrupt request for corresponding channel is cleared
3193 * 0b1..The interrupt request for corresponding channel is active
3194 */
3195#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
3196#define DMA_INT_INT2_MASK (0x4U)
3197#define DMA_INT_INT2_SHIFT (2U)
3198/*! INT2 - Interrupt Request 2
3199 * 0b0..The interrupt request for corresponding channel is cleared
3200 * 0b1..The interrupt request for corresponding channel is active
3201 */
3202#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
3203#define DMA_INT_INT3_MASK (0x8U)
3204#define DMA_INT_INT3_SHIFT (3U)
3205/*! INT3 - Interrupt Request 3
3206 * 0b0..The interrupt request for corresponding channel is cleared
3207 * 0b1..The interrupt request for corresponding channel is active
3208 */
3209#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
3210#define DMA_INT_INT4_MASK (0x10U)
3211#define DMA_INT_INT4_SHIFT (4U)
3212/*! INT4 - Interrupt Request 4
3213 * 0b0..The interrupt request for corresponding channel is cleared
3214 * 0b1..The interrupt request for corresponding channel is active
3215 */
3216#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
3217#define DMA_INT_INT5_MASK (0x20U)
3218#define DMA_INT_INT5_SHIFT (5U)
3219/*! INT5 - Interrupt Request 5
3220 * 0b0..The interrupt request for corresponding channel is cleared
3221 * 0b1..The interrupt request for corresponding channel is active
3222 */
3223#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
3224#define DMA_INT_INT6_MASK (0x40U)
3225#define DMA_INT_INT6_SHIFT (6U)
3226/*! INT6 - Interrupt Request 6
3227 * 0b0..The interrupt request for corresponding channel is cleared
3228 * 0b1..The interrupt request for corresponding channel is active
3229 */
3230#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
3231#define DMA_INT_INT7_MASK (0x80U)
3232#define DMA_INT_INT7_SHIFT (7U)
3233/*! INT7 - Interrupt Request 7
3234 * 0b0..The interrupt request for corresponding channel is cleared
3235 * 0b1..The interrupt request for corresponding channel is active
3236 */
3237#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
3238/*! @} */
3239
3240/*! @name ERR - Error Register */
3241/*! @{ */
3242#define DMA_ERR_ERR0_MASK (0x1U)
3243#define DMA_ERR_ERR0_SHIFT (0U)
3244/*! ERR0 - Error In Channel 0
3245 * 0b0..An error in this channel has not occurred
3246 * 0b1..An error in this channel has occurred
3247 */
3248#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
3249#define DMA_ERR_ERR1_MASK (0x2U)
3250#define DMA_ERR_ERR1_SHIFT (1U)
3251/*! ERR1 - Error In Channel 1
3252 * 0b0..An error in this channel has not occurred
3253 * 0b1..An error in this channel has occurred
3254 */
3255#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
3256#define DMA_ERR_ERR2_MASK (0x4U)
3257#define DMA_ERR_ERR2_SHIFT (2U)
3258/*! ERR2 - Error In Channel 2
3259 * 0b0..An error in this channel has not occurred
3260 * 0b1..An error in this channel has occurred
3261 */
3262#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
3263#define DMA_ERR_ERR3_MASK (0x8U)
3264#define DMA_ERR_ERR3_SHIFT (3U)
3265/*! ERR3 - Error In Channel 3
3266 * 0b0..An error in this channel has not occurred
3267 * 0b1..An error in this channel has occurred
3268 */
3269#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
3270#define DMA_ERR_ERR4_MASK (0x10U)
3271#define DMA_ERR_ERR4_SHIFT (4U)
3272/*! ERR4 - Error In Channel 4
3273 * 0b0..An error in this channel has not occurred
3274 * 0b1..An error in this channel has occurred
3275 */
3276#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
3277#define DMA_ERR_ERR5_MASK (0x20U)
3278#define DMA_ERR_ERR5_SHIFT (5U)
3279/*! ERR5 - Error In Channel 5
3280 * 0b0..An error in this channel has not occurred
3281 * 0b1..An error in this channel has occurred
3282 */
3283#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
3284#define DMA_ERR_ERR6_MASK (0x40U)
3285#define DMA_ERR_ERR6_SHIFT (6U)
3286/*! ERR6 - Error In Channel 6
3287 * 0b0..An error in this channel has not occurred
3288 * 0b1..An error in this channel has occurred
3289 */
3290#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
3291#define DMA_ERR_ERR7_MASK (0x80U)
3292#define DMA_ERR_ERR7_SHIFT (7U)
3293/*! ERR7 - Error In Channel 7
3294 * 0b0..An error in this channel has not occurred
3295 * 0b1..An error in this channel has occurred
3296 */
3297#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
3298/*! @} */
3299
3300/*! @name HRS - Hardware Request Status Register */
3301/*! @{ */
3302#define DMA_HRS_HRS0_MASK (0x1U)
3303#define DMA_HRS_HRS0_SHIFT (0U)
3304/*! HRS0 - Hardware Request Status Channel 0
3305 * 0b0..A hardware service request for channel 0 is not present
3306 * 0b1..A hardware service request for channel 0 is present
3307 */
3308#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
3309#define DMA_HRS_HRS1_MASK (0x2U)
3310#define DMA_HRS_HRS1_SHIFT (1U)
3311/*! HRS1 - Hardware Request Status Channel 1
3312 * 0b0..A hardware service request for channel 1 is not present
3313 * 0b1..A hardware service request for channel 1 is present
3314 */
3315#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
3316#define DMA_HRS_HRS2_MASK (0x4U)
3317#define DMA_HRS_HRS2_SHIFT (2U)
3318/*! HRS2 - Hardware Request Status Channel 2
3319 * 0b0..A hardware service request for channel 2 is not present
3320 * 0b1..A hardware service request for channel 2 is present
3321 */
3322#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
3323#define DMA_HRS_HRS3_MASK (0x8U)
3324#define DMA_HRS_HRS3_SHIFT (3U)
3325/*! HRS3 - Hardware Request Status Channel 3
3326 * 0b0..A hardware service request for channel 3 is not present
3327 * 0b1..A hardware service request for channel 3 is present
3328 */
3329#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
3330#define DMA_HRS_HRS4_MASK (0x10U)
3331#define DMA_HRS_HRS4_SHIFT (4U)
3332/*! HRS4 - Hardware Request Status Channel 4
3333 * 0b0..A hardware service request for channel 4 is not present
3334 * 0b1..A hardware service request for channel 4 is present
3335 */
3336#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
3337#define DMA_HRS_HRS5_MASK (0x20U)
3338#define DMA_HRS_HRS5_SHIFT (5U)
3339/*! HRS5 - Hardware Request Status Channel 5
3340 * 0b0..A hardware service request for channel 5 is not present
3341 * 0b1..A hardware service request for channel 5 is present
3342 */
3343#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
3344#define DMA_HRS_HRS6_MASK (0x40U)
3345#define DMA_HRS_HRS6_SHIFT (6U)
3346/*! HRS6 - Hardware Request Status Channel 6
3347 * 0b0..A hardware service request for channel 6 is not present
3348 * 0b1..A hardware service request for channel 6 is present
3349 */
3350#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
3351#define DMA_HRS_HRS7_MASK (0x80U)
3352#define DMA_HRS_HRS7_SHIFT (7U)
3353/*! HRS7 - Hardware Request Status Channel 7
3354 * 0b0..A hardware service request for channel 7 is not present
3355 * 0b1..A hardware service request for channel 7 is present
3356 */
3357#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
3358/*! @} */
3359
3360/*! @name EARS - Enable Asynchronous Request in Stop Register */
3361/*! @{ */
3362#define DMA_EARS_EDREQ_0_MASK (0x1U)
3363#define DMA_EARS_EDREQ_0_SHIFT (0U)
3364/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
3365 * 0b0..Disable asynchronous DMA request for channel 0.
3366 * 0b1..Enable asynchronous DMA request for channel 0.
3367 */
3368#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
3369#define DMA_EARS_EDREQ_1_MASK (0x2U)
3370#define DMA_EARS_EDREQ_1_SHIFT (1U)
3371/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
3372 * 0b0..Disable asynchronous DMA request for channel 1
3373 * 0b1..Enable asynchronous DMA request for channel 1.
3374 */
3375#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
3376#define DMA_EARS_EDREQ_2_MASK (0x4U)
3377#define DMA_EARS_EDREQ_2_SHIFT (2U)
3378/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
3379 * 0b0..Disable asynchronous DMA request for channel 2.
3380 * 0b1..Enable asynchronous DMA request for channel 2.
3381 */
3382#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
3383#define DMA_EARS_EDREQ_3_MASK (0x8U)
3384#define DMA_EARS_EDREQ_3_SHIFT (3U)
3385/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
3386 * 0b0..Disable asynchronous DMA request for channel 3.
3387 * 0b1..Enable asynchronous DMA request for channel 3.
3388 */
3389#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
3390#define DMA_EARS_EDREQ_4_MASK (0x10U)
3391#define DMA_EARS_EDREQ_4_SHIFT (4U)
3392/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
3393 * 0b0..Disable asynchronous DMA request for channel 4.
3394 * 0b1..Enable asynchronous DMA request for channel 4.
3395 */
3396#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
3397#define DMA_EARS_EDREQ_5_MASK (0x20U)
3398#define DMA_EARS_EDREQ_5_SHIFT (5U)
3399/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
3400 * 0b0..Disable asynchronous DMA request for channel 5.
3401 * 0b1..Enable asynchronous DMA request for channel 5.
3402 */
3403#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
3404#define DMA_EARS_EDREQ_6_MASK (0x40U)
3405#define DMA_EARS_EDREQ_6_SHIFT (6U)
3406/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
3407 * 0b0..Disable asynchronous DMA request for channel 6.
3408 * 0b1..Enable asynchronous DMA request for channel 6.
3409 */
3410#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
3411#define DMA_EARS_EDREQ_7_MASK (0x80U)
3412#define DMA_EARS_EDREQ_7_SHIFT (7U)
3413/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
3414 * 0b0..Disable asynchronous DMA request for channel 7.
3415 * 0b1..Enable asynchronous DMA request for channel 7.
3416 */
3417#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
3418/*! @} */
3419
3420/*! @name DCHPRI3 - Channel n Priority Register */
3421/*! @{ */
3422#define DMA_DCHPRI3_CHPRI_MASK (0x7U)
3423#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
3424/*! CHPRI - Channel n Arbitration Priority
3425 */
3426#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
3427#define DMA_DCHPRI3_DPA_MASK (0x40U)
3428#define DMA_DCHPRI3_DPA_SHIFT (6U)
3429/*! DPA - Disable Preempt Ability.
3430 * 0b0..Channel n can suspend a lower priority channel.
3431 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3432 */
3433#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
3434#define DMA_DCHPRI3_ECP_MASK (0x80U)
3435#define DMA_DCHPRI3_ECP_SHIFT (7U)
3436/*! ECP - Enable Channel Preemption.
3437 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3438 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3439 */
3440#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
3441/*! @} */
3442
3443/*! @name DCHPRI2 - Channel n Priority Register */
3444/*! @{ */
3445#define DMA_DCHPRI2_CHPRI_MASK (0x7U)
3446#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
3447/*! CHPRI - Channel n Arbitration Priority
3448 */
3449#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
3450#define DMA_DCHPRI2_DPA_MASK (0x40U)
3451#define DMA_DCHPRI2_DPA_SHIFT (6U)
3452/*! DPA - Disable Preempt Ability.
3453 * 0b0..Channel n can suspend a lower priority channel.
3454 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3455 */
3456#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
3457#define DMA_DCHPRI2_ECP_MASK (0x80U)
3458#define DMA_DCHPRI2_ECP_SHIFT (7U)
3459/*! ECP - Enable Channel Preemption.
3460 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3461 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3462 */
3463#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
3464/*! @} */
3465
3466/*! @name DCHPRI1 - Channel n Priority Register */
3467/*! @{ */
3468#define DMA_DCHPRI1_CHPRI_MASK (0x7U)
3469#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
3470/*! CHPRI - Channel n Arbitration Priority
3471 */
3472#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
3473#define DMA_DCHPRI1_DPA_MASK (0x40U)
3474#define DMA_DCHPRI1_DPA_SHIFT (6U)
3475/*! DPA - Disable Preempt Ability.
3476 * 0b0..Channel n can suspend a lower priority channel.
3477 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3478 */
3479#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
3480#define DMA_DCHPRI1_ECP_MASK (0x80U)
3481#define DMA_DCHPRI1_ECP_SHIFT (7U)
3482/*! ECP - Enable Channel Preemption.
3483 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3484 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3485 */
3486#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
3487/*! @} */
3488
3489/*! @name DCHPRI0 - Channel n Priority Register */
3490/*! @{ */
3491#define DMA_DCHPRI0_CHPRI_MASK (0x7U)
3492#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
3493/*! CHPRI - Channel n Arbitration Priority
3494 */
3495#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
3496#define DMA_DCHPRI0_DPA_MASK (0x40U)
3497#define DMA_DCHPRI0_DPA_SHIFT (6U)
3498/*! DPA - Disable Preempt Ability.
3499 * 0b0..Channel n can suspend a lower priority channel.
3500 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3501 */
3502#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
3503#define DMA_DCHPRI0_ECP_MASK (0x80U)
3504#define DMA_DCHPRI0_ECP_SHIFT (7U)
3505/*! ECP - Enable Channel Preemption.
3506 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3507 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3508 */
3509#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
3510/*! @} */
3511
3512/*! @name DCHPRI7 - Channel n Priority Register */
3513/*! @{ */
3514#define DMA_DCHPRI7_CHPRI_MASK (0x7U)
3515#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
3516/*! CHPRI - Channel n Arbitration Priority
3517 */
3518#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
3519#define DMA_DCHPRI7_DPA_MASK (0x40U)
3520#define DMA_DCHPRI7_DPA_SHIFT (6U)
3521/*! DPA - Disable Preempt Ability.
3522 * 0b0..Channel n can suspend a lower priority channel.
3523 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3524 */
3525#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
3526#define DMA_DCHPRI7_ECP_MASK (0x80U)
3527#define DMA_DCHPRI7_ECP_SHIFT (7U)
3528/*! ECP - Enable Channel Preemption.
3529 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3530 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3531 */
3532#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
3533/*! @} */
3534
3535/*! @name DCHPRI6 - Channel n Priority Register */
3536/*! @{ */
3537#define DMA_DCHPRI6_CHPRI_MASK (0x7U)
3538#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
3539/*! CHPRI - Channel n Arbitration Priority
3540 */
3541#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
3542#define DMA_DCHPRI6_DPA_MASK (0x40U)
3543#define DMA_DCHPRI6_DPA_SHIFT (6U)
3544/*! DPA - Disable Preempt Ability.
3545 * 0b0..Channel n can suspend a lower priority channel.
3546 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3547 */
3548#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
3549#define DMA_DCHPRI6_ECP_MASK (0x80U)
3550#define DMA_DCHPRI6_ECP_SHIFT (7U)
3551/*! ECP - Enable Channel Preemption.
3552 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3553 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3554 */
3555#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
3556/*! @} */
3557
3558/*! @name DCHPRI5 - Channel n Priority Register */
3559/*! @{ */
3560#define DMA_DCHPRI5_CHPRI_MASK (0x7U)
3561#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
3562/*! CHPRI - Channel n Arbitration Priority
3563 */
3564#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
3565#define DMA_DCHPRI5_DPA_MASK (0x40U)
3566#define DMA_DCHPRI5_DPA_SHIFT (6U)
3567/*! DPA - Disable Preempt Ability.
3568 * 0b0..Channel n can suspend a lower priority channel.
3569 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3570 */
3571#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
3572#define DMA_DCHPRI5_ECP_MASK (0x80U)
3573#define DMA_DCHPRI5_ECP_SHIFT (7U)
3574/*! ECP - Enable Channel Preemption.
3575 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3576 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3577 */
3578#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
3579/*! @} */
3580
3581/*! @name DCHPRI4 - Channel n Priority Register */
3582/*! @{ */
3583#define DMA_DCHPRI4_CHPRI_MASK (0x7U)
3584#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
3585/*! CHPRI - Channel n Arbitration Priority
3586 */
3587#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
3588#define DMA_DCHPRI4_DPA_MASK (0x40U)
3589#define DMA_DCHPRI4_DPA_SHIFT (6U)
3590/*! DPA - Disable Preempt Ability.
3591 * 0b0..Channel n can suspend a lower priority channel.
3592 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
3593 */
3594#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
3595#define DMA_DCHPRI4_ECP_MASK (0x80U)
3596#define DMA_DCHPRI4_ECP_SHIFT (7U)
3597/*! ECP - Enable Channel Preemption.
3598 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
3599 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
3600 */
3601#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
3602/*! @} */
3603
3604/*! @name SADDR - TCD Source Address */
3605/*! @{ */
3606#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
3607#define DMA_SADDR_SADDR_SHIFT (0U)
3608/*! SADDR - Source Address
3609 */
3610#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
3611/*! @} */
3612
3613/* The count of DMA_SADDR */
3614#define DMA_SADDR_COUNT (8U)
3615
3616/*! @name SOFF - TCD Signed Source Address Offset */
3617/*! @{ */
3618#define DMA_SOFF_SOFF_MASK (0xFFFFU)
3619#define DMA_SOFF_SOFF_SHIFT (0U)
3620/*! SOFF - Source address signed offset
3621 */
3622#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
3623/*! @} */
3624
3625/* The count of DMA_SOFF */
3626#define DMA_SOFF_COUNT (8U)
3627
3628/*! @name ATTR - TCD Transfer Attributes */
3629/*! @{ */
3630#define DMA_ATTR_DSIZE_MASK (0x7U)
3631#define DMA_ATTR_DSIZE_SHIFT (0U)
3632/*! DSIZE - Destination data transfer size
3633 */
3634#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
3635#define DMA_ATTR_DMOD_MASK (0xF8U)
3636#define DMA_ATTR_DMOD_SHIFT (3U)
3637/*! DMOD - Destination Address Modulo
3638 */
3639#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
3640#define DMA_ATTR_SSIZE_MASK (0x700U)
3641#define DMA_ATTR_SSIZE_SHIFT (8U)
3642/*! SSIZE - Source data transfer size
3643 * 0b000..8-bit
3644 * 0b001..16-bit
3645 * 0b010..32-bit
3646 * 0b011..Reserved
3647 * 0b100..16-byte
3648 * 0b101..32-byte
3649 * 0b110..Reserved
3650 * 0b111..Reserved
3651 */
3652#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
3653#define DMA_ATTR_SMOD_MASK (0xF800U)
3654#define DMA_ATTR_SMOD_SHIFT (11U)
3655/*! SMOD - Source Address Modulo
3656 * 0b00000..Source address modulo feature is disabled
3657 */
3658#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
3659/*! @} */
3660
3661/* The count of DMA_ATTR */
3662#define DMA_ATTR_COUNT (8U)
3663
3664/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
3665/*! @{ */
3666#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
3667#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
3668/*! NBYTES - Minor Byte Transfer Count
3669 */
3670#define DMA_NBYTES_MLNO_NBYTES(x) \
3671 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
3672/*! @} */
3673
3674/* The count of DMA_NBYTES_MLNO */
3675#define DMA_NBYTES_MLNO_COUNT (8U)
3676
3677/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
3678/*! @{ */
3679#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
3680#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
3681/*! NBYTES - Minor Byte Transfer Count
3682 */
3683#define DMA_NBYTES_MLOFFNO_NBYTES(x) \
3684 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
3685#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
3686#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
3687/*! DMLOE - Destination Minor Loop Offset enable
3688 * 0b0..The minor loop offset is not applied to the DADDR
3689 * 0b1..The minor loop offset is applied to the DADDR
3690 */
3691#define DMA_NBYTES_MLOFFNO_DMLOE(x) \
3692 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
3693#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
3694#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
3695/*! SMLOE - Source Minor Loop Offset Enable
3696 * 0b0..The minor loop offset is not applied to the SADDR
3697 * 0b1..The minor loop offset is applied to the SADDR
3698 */
3699#define DMA_NBYTES_MLOFFNO_SMLOE(x) \
3700 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
3701/*! @} */
3702
3703/* The count of DMA_NBYTES_MLOFFNO */
3704#define DMA_NBYTES_MLOFFNO_COUNT (8U)
3705
3706/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
3707/*! @{ */
3708#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
3709#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
3710/*! NBYTES - Minor Byte Transfer Count
3711 */
3712#define DMA_NBYTES_MLOFFYES_NBYTES(x) \
3713 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
3714#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
3715#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
3716/*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the
3717 * source or destination address to form the next-state value after the minor loop completes.
3718 */
3719#define DMA_NBYTES_MLOFFYES_MLOFF(x) \
3720 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
3721#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
3722#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
3723/*! DMLOE - Destination Minor Loop Offset enable
3724 * 0b0..The minor loop offset is not applied to the DADDR
3725 * 0b1..The minor loop offset is applied to the DADDR
3726 */
3727#define DMA_NBYTES_MLOFFYES_DMLOE(x) \
3728 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
3729#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
3730#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
3731/*! SMLOE - Source Minor Loop Offset Enable
3732 * 0b0..The minor loop offset is not applied to the SADDR
3733 * 0b1..The minor loop offset is applied to the SADDR
3734 */
3735#define DMA_NBYTES_MLOFFYES_SMLOE(x) \
3736 (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
3737/*! @} */
3738
3739/* The count of DMA_NBYTES_MLOFFYES */
3740#define DMA_NBYTES_MLOFFYES_COUNT (8U)
3741
3742/*! @name SLAST - TCD Last Source Address Adjustment */
3743/*! @{ */
3744#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
3745#define DMA_SLAST_SLAST_SHIFT (0U)
3746/*! SLAST - Last Source Address Adjustment
3747 */
3748#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
3749/*! @} */
3750
3751/* The count of DMA_SLAST */
3752#define DMA_SLAST_COUNT (8U)
3753
3754/*! @name DADDR - TCD Destination Address */
3755/*! @{ */
3756#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
3757#define DMA_DADDR_DADDR_SHIFT (0U)
3758/*! DADDR - Destination Address
3759 */
3760#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
3761/*! @} */
3762
3763/* The count of DMA_DADDR */
3764#define DMA_DADDR_COUNT (8U)
3765
3766/*! @name DOFF - TCD Signed Destination Address Offset */
3767/*! @{ */
3768#define DMA_DOFF_DOFF_MASK (0xFFFFU)
3769#define DMA_DOFF_DOFF_SHIFT (0U)
3770/*! DOFF - Destination Address Signed Offset
3771 */
3772#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
3773/*! @} */
3774
3775/* The count of DMA_DOFF */
3776#define DMA_DOFF_COUNT (8U)
3777
3778/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3779/*! @{ */
3780#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
3781#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
3782/*! CITER - Current Major Iteration Count
3783 */
3784#define DMA_CITER_ELINKNO_CITER(x) \
3785 (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
3786#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
3787#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
3788/*! ELINK - Enable channel-to-channel linking on minor-loop complete
3789 * 0b0..The channel-to-channel linking is disabled
3790 * 0b1..The channel-to-channel linking is enabled
3791 */
3792#define DMA_CITER_ELINKNO_ELINK(x) \
3793 (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
3794/*! @} */
3795
3796/* The count of DMA_CITER_ELINKNO */
3797#define DMA_CITER_ELINKNO_COUNT (8U)
3798
3799/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3800/*! @{ */
3801#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
3802#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
3803/*! CITER - Current Major Iteration Count
3804 */
3805#define DMA_CITER_ELINKYES_CITER(x) \
3806 (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
3807#define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U)
3808#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
3809/*! LINKCH - Minor Loop Link Channel Number
3810 */
3811#define DMA_CITER_ELINKYES_LINKCH(x) \
3812 (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
3813#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
3814#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
3815/*! ELINK - Enable channel-to-channel linking on minor-loop complete
3816 * 0b0..The channel-to-channel linking is disabled
3817 * 0b1..The channel-to-channel linking is enabled
3818 */
3819#define DMA_CITER_ELINKYES_ELINK(x) \
3820 (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
3821/*! @} */
3822
3823/* The count of DMA_CITER_ELINKYES */
3824#define DMA_CITER_ELINKYES_COUNT (8U)
3825
3826/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
3827/*! @{ */
3828#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
3829#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
3830#define DMA_DLAST_SGA_DLASTSGA(x) \
3831 (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
3832/*! @} */
3833
3834/* The count of DMA_DLAST_SGA */
3835#define DMA_DLAST_SGA_COUNT (8U)
3836
3837/*! @name CSR - TCD Control and Status */
3838/*! @{ */
3839#define DMA_CSR_START_MASK (0x1U)
3840#define DMA_CSR_START_SHIFT (0U)
3841/*! START - Channel Start
3842 * 0b0..The channel is not explicitly started.
3843 * 0b1..The channel is explicitly started via a software initiated service request.
3844 */
3845#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
3846#define DMA_CSR_INTMAJOR_MASK (0x2U)
3847#define DMA_CSR_INTMAJOR_SHIFT (1U)
3848/*! INTMAJOR - Enable an interrupt when major iteration count completes.
3849 * 0b0..The end-of-major loop interrupt is disabled.
3850 * 0b1..The end-of-major loop interrupt is enabled.
3851 */
3852#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
3853#define DMA_CSR_INTHALF_MASK (0x4U)
3854#define DMA_CSR_INTHALF_SHIFT (2U)
3855/*! INTHALF - Enable an interrupt when major counter is half complete.
3856 * 0b0..The half-point interrupt is disabled.
3857 * 0b1..The half-point interrupt is enabled.
3858 */
3859#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
3860#define DMA_CSR_DREQ_MASK (0x8U)
3861#define DMA_CSR_DREQ_SHIFT (3U)
3862/*! DREQ - Disable Request
3863 * 0b0..The channel's ERQ bit is not affected.
3864 * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
3865 */
3866#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
3867#define DMA_CSR_ESG_MASK (0x10U)
3868#define DMA_CSR_ESG_SHIFT (4U)
3869/*! ESG - Enable Scatter/Gather Processing
3870 * 0b0..The current channel's TCD is normal format.
3871 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
3872 * to the next TCD to be loaded into this channel after the major loop completes its execution.
3873 */
3874#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
3875#define DMA_CSR_MAJORELINK_MASK (0x20U)
3876#define DMA_CSR_MAJORELINK_SHIFT (5U)
3877/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
3878 * 0b0..The channel-to-channel linking is disabled.
3879 * 0b1..The channel-to-channel linking is enabled.
3880 */
3881#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
3882#define DMA_CSR_ACTIVE_MASK (0x40U)
3883#define DMA_CSR_ACTIVE_SHIFT (6U)
3884/*! ACTIVE - Channel Active
3885 */
3886#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
3887#define DMA_CSR_DONE_MASK (0x80U)
3888#define DMA_CSR_DONE_SHIFT (7U)
3889/*! DONE - Channel Done
3890 */
3891#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
3892#define DMA_CSR_MAJORLINKCH_MASK (0x700U)
3893#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
3894/*! MAJORLINKCH - Major Loop Link Channel Number
3895 */
3896#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
3897#define DMA_CSR_BWC_MASK (0xC000U)
3898#define DMA_CSR_BWC_SHIFT (14U)
3899/*! BWC - Bandwidth Control
3900 * 0b00..No eDMA engine stalls.
3901 * 0b01..Reserved
3902 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
3903 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
3904 */
3905#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
3906/*! @} */
3907
3908/* The count of DMA_CSR */
3909#define DMA_CSR_COUNT (8U)
3910
3911/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3912/*! @{ */
3913#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
3914#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
3915/*! BITER - Starting Major Iteration Count
3916 */
3917#define DMA_BITER_ELINKNO_BITER(x) \
3918 (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
3919#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
3920#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
3921/*! ELINK - Enables channel-to-channel linking on minor loop complete
3922 * 0b0..The channel-to-channel linking is disabled
3923 * 0b1..The channel-to-channel linking is enabled
3924 */
3925#define DMA_BITER_ELINKNO_ELINK(x) \
3926 (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
3927/*! @} */
3928
3929/* The count of DMA_BITER_ELINKNO */
3930#define DMA_BITER_ELINKNO_COUNT (8U)
3931
3932/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3933/*! @{ */
3934#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
3935#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
3936/*! BITER - Starting major iteration count
3937 */
3938#define DMA_BITER_ELINKYES_BITER(x) \
3939 (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
3940#define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U)
3941#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
3942/*! LINKCH - Link Channel Number
3943 */
3944#define DMA_BITER_ELINKYES_LINKCH(x) \
3945 (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
3946#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
3947#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
3948/*! ELINK - Enables channel-to-channel linking on minor loop complete
3949 * 0b0..The channel-to-channel linking is disabled
3950 * 0b1..The channel-to-channel linking is enabled
3951 */
3952#define DMA_BITER_ELINKYES_ELINK(x) \
3953 (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
3954/*! @} */
3955
3956/* The count of DMA_BITER_ELINKYES */
3957#define DMA_BITER_ELINKYES_COUNT (8U)
3958
3959/*!
3960 * @}
3961 */ /* end of group DMA_Register_Masks */
3962
3963/* DMA - Peripheral instance base addresses */
3964/** Peripheral DMA0 base address */
3965#define DMA0_BASE (0x40008000u)
3966/** Peripheral DMA0 base pointer */
3967#define DMA0 ((DMA_Type *)DMA0_BASE)
3968/** Array initializer of DMA peripheral base addresses */
3969#define DMA_BASE_ADDRS \
3970 { \
3971 DMA0_BASE \
3972 }
3973/** Array initializer of DMA peripheral base pointers */
3974#define DMA_BASE_PTRS \
3975 { \
3976 DMA0 \
3977 }
3978/** Interrupt vectors for the DMA peripheral type */
3979#define DMA_CHN_IRQS \
3980 { \
3981 { \
3982 DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn, DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, \
3983 DMA0_37_IRQn \
3984 } \
3985 }
3986#define DMA_ERROR_IRQS \
3987 { \
3988 CTI0_DMA0_Error_IRQn \
3989 }
3990
3991/*!
3992 * @}
3993 */ /* end of group DMA_Peripheral_Access_Layer */
3994
3995/* ----------------------------------------------------------------------------
3996 -- DMAMUX Peripheral Access Layer
3997 ---------------------------------------------------------------------------- */
3998
3999/*!
4000 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
4001 * @{
4002 */
4003
4004/** DMAMUX - Register Layout Typedef */
4005typedef struct
4006{
4007 __IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
4008} DMAMUX_Type;
4009
4010/* ----------------------------------------------------------------------------
4011 -- DMAMUX Register Masks
4012 ---------------------------------------------------------------------------- */
4013
4014/*!
4015 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
4016 * @{
4017 */
4018
4019/*! @name CHCFG - Channel Configuration register */
4020/*! @{ */
4021#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
4022#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
4023/*! SOURCE - DMA Channel Source (Slot)
4024 */
4025#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
4026#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
4027#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
4028/*! TRIG - DMA Channel Trigger Enable
4029 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
4030 * specified source to the DMA channel. (Normal mode)
4031 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
4032 */
4033#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
4034#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
4035#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
4036/*! ENBL - DMA Channel Enable
4037 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has
4038 * separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
4039 * 0b1..DMA channel is enabled
4040 */
4041#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
4042/*! @} */
4043
4044/* The count of DMAMUX_CHCFG */
4045#define DMAMUX_CHCFG_COUNT (8U)
4046
4047/*!
4048 * @}
4049 */ /* end of group DMAMUX_Register_Masks */
4050
4051/* DMAMUX - Peripheral instance base addresses */
4052/** Peripheral DMAMUX0 base address */
4053#define DMAMUX0_BASE (0x40021000u)
4054/** Peripheral DMAMUX0 base pointer */
4055#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
4056/** Array initializer of DMAMUX peripheral base addresses */
4057#define DMAMUX_BASE_ADDRS \
4058 { \
4059 DMAMUX0_BASE \
4060 }
4061/** Array initializer of DMAMUX peripheral base pointers */
4062#define DMAMUX_BASE_PTRS \
4063 { \
4064 DMAMUX0 \
4065 }
4066
4067/*!
4068 * @}
4069 */ /* end of group DMAMUX_Peripheral_Access_Layer */
4070
4071/* ----------------------------------------------------------------------------
4072 -- EMVSIM Peripheral Access Layer
4073 ---------------------------------------------------------------------------- */
4074
4075/*!
4076 * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
4077 * @{
4078 */
4079
4080/** EMVSIM - Register Layout Typedef */
4081typedef struct
4082{
4083 __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
4084 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
4085 __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
4086 __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
4087 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
4088 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
4089 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
4090 __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
4091 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
4092 __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
4093 __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
4094 __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
4095 __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
4096 __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
4097 __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
4098 __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
4099 __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
4100 __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
4101 __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
4102} EMVSIM_Type;
4103
4104/* ----------------------------------------------------------------------------
4105 -- EMVSIM Register Masks
4106 ---------------------------------------------------------------------------- */
4107
4108/*!
4109 * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
4110 * @{
4111 */
4112
4113/*! @name VER_ID - Version ID Register */
4114/*! @{ */
4115#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
4116#define EMVSIM_VER_ID_VER_SHIFT (0U)
4117/*! VER - Version ID of the module
4118 */
4119#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
4120/*! @} */
4121
4122/*! @name PARAM - Parameter Register */
4123/*! @{ */
4124#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
4125#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
4126/*! RX_FIFO_DEPTH - Receive FIFO Depth
4127 */
4128#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) \
4129 (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
4130#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
4131#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
4132/*! TX_FIFO_DEPTH - Transmit FIFO Depth
4133 */
4134#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) \
4135 (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
4136/*! @} */
4137
4138/*! @name CLKCFG - Clock Configuration Register */
4139/*! @{ */
4140#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
4141#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
4142/*! CLK_PRSC - Clock Prescaler Value
4143 * 0b00000010..Divide by 2
4144 */
4145#define EMVSIM_CLKCFG_CLK_PRSC(x) \
4146 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
4147#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
4148#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
4149/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
4150 * 0b00..Disabled / Reset (default)
4151 * 0b01..Card Clock
4152 * 0b10..Receive Clock
4153 * 0b11..ETU Clock (transmit clock)
4154 */
4155#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) \
4156 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
4157#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
4158#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
4159/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
4160 * 0b00..Disabled / Reset (default)
4161 * 0b01..Card Clock
4162 * 0b10..Receive Clock
4163 * 0b11..ETU Clock (transmit clock)
4164 */
4165#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) \
4166 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
4167/*! @} */
4168
4169/*! @name DIVISOR - Baud Rate Divisor Register */
4170/*! @{ */
4171#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
4172#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
4173/*! DIVISOR_VALUE - Divisor (F/D) Value
4174 * 0b101110100..Divisor value for F = 372 and D = 1 (default)
4175 */
4176#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) \
4177 (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
4178/*! @} */
4179
4180/*! @name CTRL - Control Register */
4181/*! @{ */
4182#define EMVSIM_CTRL_IC_MASK (0x1U)
4183#define EMVSIM_CTRL_IC_SHIFT (0U)
4184/*! IC - Inverse Convention
4185 * 0b0..Direction convention transfers enabled (default)
4186 * 0b1..Inverse convention transfers enabled
4187 */
4188#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
4189#define EMVSIM_CTRL_ICM_MASK (0x2U)
4190#define EMVSIM_CTRL_ICM_SHIFT (1U)
4191/*! ICM - Initial Character Mode
4192 * 0b0..Initial Character Mode disabled
4193 * 0b1..Initial Character Mode enabled (default)
4194 */
4195#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
4196#define EMVSIM_CTRL_ANACK_MASK (0x4U)
4197#define EMVSIM_CTRL_ANACK_SHIFT (2U)
4198/*! ANACK - Auto NACK Enable
4199 * 0b0..NACK generation on errors disabled
4200 * 0b1..NACK generation on errors enabled (default)
4201 */
4202#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
4203#define EMVSIM_CTRL_ONACK_MASK (0x8U)
4204#define EMVSIM_CTRL_ONACK_SHIFT (3U)
4205/*! ONACK - Overrun NACK Enable
4206 * 0b0..NACK generation on overrun is disabled (default)
4207 * 0b1..NACK generation on overrun is enabled
4208 */
4209#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
4210#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
4211#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
4212/*! FLSH_RX - Flush Receiver Bit
4213 * 0b0..EMV SIM Receiver normal operation (default)
4214 * 0b1..EMV SIM Receiver held in Reset
4215 */
4216#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
4217#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
4218#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
4219/*! FLSH_TX - Flush Transmitter Bit
4220 * 0b0..EMV SIM Transmitter normal operation (default)
4221 * 0b1..EMV SIM Transmitter held in Reset
4222 */
4223#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
4224#define EMVSIM_CTRL_SW_RST_MASK (0x400U)
4225#define EMVSIM_CTRL_SW_RST_SHIFT (10U)
4226/*! SW_RST - Software Reset Bit
4227 * 0b0..EMV SIM Normal operation (default)
4228 * 0b1..EMV SIM held in Reset
4229 */
4230#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
4231#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
4232#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
4233/*! KILL_CLOCKS - Kill all internal clocks
4234 * 0b0..EMV SIM input clock enabled (default)
4235 * 0b1..EMV SIM input clock is disabled
4236 */
4237#define EMVSIM_CTRL_KILL_CLOCKS(x) \
4238 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
4239#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
4240#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
4241/*! DOZE_EN - Doze Enable
4242 * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO
4243 * is empty (default) 0b1..DOZE instruction has no effect on EMV SIM module
4244 */
4245#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
4246#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
4247#define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
4248/*! STOP_EN - STOP Enable
4249 * 0b0..STOP instruction shuts down all EMV SIM clocks (default)
4250 * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
4251 */
4252#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
4253#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
4254#define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
4255/*! RCV_EN - Receiver Enable
4256 * 0b0..EMV SIM Receiver disabled (default)
4257 * 0b1..EMV SIM Receiver enabled
4258 */
4259#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
4260#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
4261#define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
4262/*! XMT_EN - Transmitter Enable
4263 * 0b0..EMV SIM Transmitter disabled (default)
4264 * 0b1..EMV SIM Transmitter enabled
4265 */
4266#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
4267#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
4268#define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
4269/*! RCVR_11 - Receiver 11 ETU Mode Enable
4270 * 0b0..Receiver configured for 12 ETU operation mode (default)
4271 * 0b1..Receiver configured for 11 ETU operation mode
4272 */
4273#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
4274#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
4275#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
4276/*! RX_DMA_EN - Receive DMA Enable
4277 * 0b0..No DMA Read Request asserted for Receiver (default)
4278 * 0b1..DMA Read Request asserted for Receiver
4279 */
4280#define EMVSIM_CTRL_RX_DMA_EN(x) \
4281 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
4282#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
4283#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
4284/*! TX_DMA_EN - Transmit DMA Enable
4285 * 0b0..No DMA Write Request asserted for Transmitter (default)
4286 * 0b1..DMA Write Request asserted for Transmitter
4287 */
4288#define EMVSIM_CTRL_TX_DMA_EN(x) \
4289 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
4290#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
4291#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
4292/*! INV_CRC_VAL - Invert bits in the CRC Output Value
4293 * 0b0..Bits in CRC Output value will not be inverted.
4294 * 0b1..Bits in CRC Output value will be inverted. (default)
4295 */
4296#define EMVSIM_CTRL_INV_CRC_VAL(x) \
4297 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
4298#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
4299#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
4300/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
4301 * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
4302 * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
4303 */
4304#define EMVSIM_CTRL_CRC_OUT_FLIP(x) \
4305 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
4306#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
4307#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
4308/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
4309 * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
4310 * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
4311 */
4312#define EMVSIM_CTRL_CRC_IN_FLIP(x) \
4313 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
4314#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
4315#define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
4316/*! CWT_EN - Character Wait Time Counter Enable
4317 * 0b0..Character Wait time Counter is disabled (default)
4318 * 0b1..Character Wait time counter is enabled
4319 */
4320#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
4321#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
4322#define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
4323/*! LRC_EN - LRC Enable
4324 * 0b0..8-bit Linear Redundancy Checking disabled (default)
4325 * 0b1..8-bit Linear Redundancy Checking enabled
4326 */
4327#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
4328#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
4329#define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
4330/*! CRC_EN - CRC Enable
4331 * 0b0..16-bit Cyclic Redundancy Checking disabled (default)
4332 * 0b1..16-bit Cyclic Redundancy Checking enabled
4333 */
4334#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
4335#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
4336#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
4337/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
4338 * 0b0..No CRC or LRC value is transmitted (default)