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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2A41A/project_template/pin_mux.c
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@@ -0,0 +1,902 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16!!GlobalInfo
17product: Pins v6.0
18processor: K32L2A41xxxxA
19package_id: K32L2A41VLL1A
20mcu_data: ksdk2_0
21processor_version: 0.0.0
22board: FRDM-K32L2A4S
23pin_labels:
24- {pin_num: '1', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, label: 'U2[3]/INT1_21002', identifier: GYRO_INT1}
25- {pin_num: '2', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, label: 'U2[2]/INT2_21002', identifier: GYRO_INT2}
26- {pin_num: '3', pin_signal: ADC0_SE18/PTE2/LLWU_P1/LPSPI1_SCK/LPUART1_CTS_b/LPI2C1_SDAS, label: 'J2[5]'}
27- {pin_num: '4', pin_signal: ADC0_SE19/PTE3/LPSPI1_SIN/LPUART1_RTS_b/LPI2C1_SCLS, label: 'J2[7]'}
28- {pin_num: '5', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, label: BUTTON1, identifier: SW3}
29- {pin_num: '6', pin_signal: PTE5/LPSPI1_PCS1, label: 'U10[9]/INT2_8700', identifier: ACCEL_INT2}
30- {pin_num: '7', pin_signal: PTE6/LLWU_P16/LPSPI1_PCS2/USB_SOF_OUT, label: 'J2[9]'}
31- {pin_num: '8', pin_signal: VDD8, label: 'J17[2]/P3V3_K32L2A'}
32- {pin_num: '30', pin_signal: VDD31, label: 'J17[2]/P3V3_K32L2A'}
33- {pin_num: '22', pin_signal: VDDA, label: 'J17[2]/P3V3_K32L2A'}
34- {pin_num: '48', pin_signal: VDD53, label: 'J17[2]/P3V3_K32L2A'}
35- {pin_num: '75', pin_signal: VDD82, label: 'J17[2]/P3V3_K32L2A'}
36- {pin_num: '89', pin_signal: VDD98, label: 'J17[2]/P3V3_K32L2A'}
37- {pin_num: '9', pin_signal: VSS9, label: GND}
38- {pin_num: '25', pin_signal: VSSA, label: GND}
39- {pin_num: '29', pin_signal: VSS30, label: GND}
40- {pin_num: '49', pin_signal: VSS54, label: GND}
41- {pin_num: '74', pin_signal: VSS81, label: GND}
42- {pin_num: '88', pin_signal: VSS97, label: GND}
43- {pin_num: '11', pin_signal: USB0_DM, label: 'J10[2]/K32L2A_USB_DN', identifier: USB_DN}
44- {pin_num: '10', pin_signal: USB0_DP, label: 'J10[3]/K32L2A_USB_DP', identifier: USB_DP}
45- {pin_num: '12', pin_signal: VOUT33, label: TP11/VOUT33}
46- {pin_num: '13', pin_signal: VREGIN, label: P5V_K32L2A, identifier: VREGIN}
47- {pin_num: '14', pin_signal: ADC0_DP1/ADC0_SE1/PTE16/LPSPI0_PCS0/LPUART2_TX/TPM0_CLKIN/LPSPI1_PCS3/FXIO0_D0, label: 'J2[11]/FXIO_D0'}
48- {pin_num: '15', pin_signal: ADC0_DM1/ADC0_SE5a/PTE17/LLWU_P19/LPSPI0_SCK/LPUART2_RX/TPM1_CLKIN/LPTMR0_ALT3/LPTMR1_ALT3/FXIO0_D1, label: 'J2[13]/FXIO_D1'}
49- {pin_num: '16', pin_signal: ADC0_DP2/ADC0_SE2/PTE18/LLWU_P20/LPSPI0_SOUT/LPUART2_CTS_b/LPI2C0_SDA/FXIO0_D2, label: 'J2[15]/FXIO_D2'}
50- {pin_num: '17', pin_signal: ADC0_DM2/ADC0_SE6a/PTE19/LPSPI0_SIN/LPUART2_RTS_b/LPI2C0_SCL/FXIO0_D3, label: 'J2[17]/FXIO_D3'}
51- {pin_num: '18', pin_signal: ADC0_DP0/ADC0_SE0/PTE20/LPSPI2_SCK/TPM1_CH0/LPUART0_TX/FXIO0_D4, label: 'J4[1]/DIFF_ADC0_DP0/FXIO_D4'}
52- {pin_num: '19', pin_signal: ADC0_DM0/ADC0_SE4a/PTE21/LPSPI2_SOUT/TPM1_CH1/LPUART0_RX/FXIO0_D5, label: 'J4[3]/DIFF_ADC0_DM0/FXIO_D5'}
53- {pin_num: '20', pin_signal: ADC0_DP3/ADC0_SE3/PTE22/LPSPI2_SIN/TPM2_CH0/LPUART2_TX/FXIO0_D6, label: 'J4[5]/DIFF_ADC0_DP3/FXIO_D6'}
54- {pin_num: '21', pin_signal: ADC0_DM3/ADC0_SE7a/PTE23/LPSPI2_PCS0/TPM2_CH1/LPUART2_RX/FXIO0_D7, label: 'J4[7]/DIFF_ADC0_DM3/FXIO_D7'}
55- {pin_num: '23', pin_signal: VREFH/VREF_OUT, label: 'J17[2]/P3V3_K32L2A'}
56- {pin_num: '24', pin_signal: VREFL, label: GND}
57- {pin_num: '26', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, label: LEDRGB_RED, identifier: LED_RED}
58- {pin_num: '27', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23/CMP0_IN4/PTE30/EMVSIM0_RST/TPM0_CH3/TPM1_CLKIN, label: 'J4[11]/DAC0_OUT'}
59- {pin_num: '28', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, label: LEDRGB_BLUE, identifier: LED_BLUE}
60- {pin_num: '31', pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, label: 'U2[11]/U10[4]/ACCEL_I2C0_SCL', identifier: ACCEL_SCL;GYRO_SCL}
61- {pin_num: '32', pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, label: 'U2[12]/U10[6]/ACCEL_I2C0_SDA', identifier: ACCEL_SDA;GYRO_SDA}
62- {pin_num: '33', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, label: 'U10[16]/U11[2]/ACCEL_RST', identifier: ACCEL_RST;GYRO_RST}
63- {pin_num: '34', pin_signal: TSI0_CH1/PTA0/LPUART0_CTS_b/TPM0_CH5/LPI2C0_SDAS/SWD_CLK, label: 'J11[4]/U5[11]/K32L2A_SWD_CLK/SWD_CLK_TGTMCU'}
64- {pin_num: '35', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, label: TSI_ELECTRODE1/TSI0_CH2, identifier: TSI_ELECTRODE_1}
65- {pin_num: '36', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, label: TSI_ELECTRODE2/TSI0_CH3, identifier: TSI_ELECTRODE_2}
66- {pin_num: '37', pin_signal: TSI0_CH4/PTA3/LPI2C1_SCL/TPM0_CH0/LPUART0_RTS_b/SWD_DIO, label: 'J11[2]/U5[3]/SWD_DIO_TGTMCU'}
67- {pin_num: '38', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, label: BUTTON2, identifier: SW2}
68- {pin_num: '39', pin_signal: PTA5/USB_CLKIN/TPM0_CH2/LPI2C2_HREQ, label: 'J3[1]'}
69- {pin_num: '40', pin_signal: PTA6/TPM0_CH3, label: 'J3[3]'}
70- {pin_num: '41', pin_signal: PTA7/LPSPI0_PCS3/TPM0_CH4/LPI2C2_SDAS, label: 'J3[5]'}
71- {pin_num: '42', pin_signal: PTA12/TPM1_CH0/LPI2C2_SCL, label: 'J2[20]/D15/I2C2_SCL'}
72- {pin_num: '43', pin_signal: PTA13/LLWU_P4/TPM1_CH1/LPI2C2_SDA, label: 'J2[18]/D14/I2C2_SDA'}
73- {pin_num: '44', pin_signal: PTA14/LPSPI0_PCS0/LPUART0_TX/LPI2C2_SCL, label: 'J3[7]'}
74- {pin_num: '45', pin_signal: PTA15/LPSPI0_SCK/LPUART0_RX, label: 'J3[9]'}
75- {pin_num: '46', pin_signal: PTA16/LPSPI0_SOUT/LPUART0_CTS_b, label: 'J3[11]'}
76- {pin_num: '47', pin_signal: ADC0_SE22/PTA17/LPSPI0_SIN/LPUART0_RTS_b, label: 'J3[13]'}
77- {pin_num: '50', pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, label: 'Y1[1]/EXTAL_32KHZ', identifier: EXTAL0}
78- {pin_num: '51', pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, label: 'Y1[2]/XTAL_32KHZ', identifier: XTAL0}
79- {pin_num: '52', pin_signal: PTA20/LPI2C0_SCLS/TPM2_CLKIN/RESET_b, label: 'J3[6]/J11[10]/U7[21]/RST_K20D50_B'}
80- {pin_num: '53', pin_signal: ADC0_SE8/TSI0_CH0/PTB0/LLWU_P5/LPI2C0_SCL/TPM1_CH0/FXIO0_D8, label: 'J4[2]/A0/ADC0_SE8/FXIO_D8'}
81- {pin_num: '54', pin_signal: ADC0_SE9/TSI0_CH6/PTB1/LPI2C0_SDA/TPM1_CH1/FXIO0_D9, label: 'J4[4]/A1/ADC0_SE9/FXIO_D9'}
82- {pin_num: '55', pin_signal: ADC0_SE12/TSI0_CH7/PTB2/LPI2C0_SCL/TPM2_CH0/LPUART0_RTS_b/FXIO0_D10, label: 'J1[6]/D2/FXIO_D10'}
83- {pin_num: '56', pin_signal: ADC0_SE13/TSI0_CH8/PTB3/LPI2C0_SDA/TPM2_CH1/LPSPI1_PCS3/LPUART0_CTS_b/FXIO0_D11, label: 'J4[8]/A3/ADC0_SE13/FXIO_D11'}
84- {pin_num: '57', pin_signal: PTB7/LPSPI1_PCS1, label: 'U7[31]/OpenSDA GPIO'}
85- {pin_num: '58', pin_signal: PTB8/LPSPI1_PCS0/FXIO0_D12, label: 'J3[15]/FXIO_D12'}
86- {pin_num: '59', pin_signal: PTB9/LPSPI1_SCK/FXIO0_D13, label: 'J1[8]/D3/FXIO_D13'}
87- {pin_num: '60', pin_signal: PTB10/LPSPI1_PCS0/FXIO0_D14, label: 'J1[10]/D4/FXIO_D14'}
88- {pin_num: '61', pin_signal: PTB11/LPSPI1_SCK/TPM2_CLKIN/FXIO0_D15, label: 'J1[12]/D5/FXIO_D15'}
89- {pin_num: '62', pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, label: 'J1[2]/U7[25]/D0/UART0_RX/FXIO_D16/UART1_RX_TGTMCU',
90 identifier: DEBUG_UART_RX}
91- {pin_num: '63', pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, label: 'J1[4]/U7[24]/D1/UART0_TX/FXIO_D17/UART1_TX_TGTMCU',
92 identifier: DEBUG_UART_TX}
93- {pin_num: '64', pin_signal: TSI0_CH11/PTB18/TPM2_CH0/LPI2C1_HREQ/FXIO0_D18, label: 'J1[1]/FXIO_D18'}
94- {pin_num: '65', pin_signal: TSI0_CH12/PTB19/TPM2_CH1/LPSPI2_PCS1/FXIO0_D19, label: 'J1[3]/FXIO_D19'}
95- {pin_num: '66', pin_signal: PTB20/LPSPI2_PCS0/CMP0_OUT, label: 'J20[4]/SPI2_PCS0'}
96- {pin_num: '67', pin_signal: PTB21/LPSPI2_SCK/CMP1_OUT, label: 'J20[5]/SPI2_SCK'}
97- {pin_num: '68', pin_signal: PTB22/LPSPI2_SOUT, label: 'J20[6]/SPI2_SOUT'}
98- {pin_num: '69', pin_signal: PTB23/LPSPI2_SIN, label: 'J20[7]/SPI2_SIN'}
99- {pin_num: '70', pin_signal: ADC0_SE14/TSI0_CH13/PTC0/LPSPI2_PCS1/USB_SOF_OUT/CMP0_OUT, label: 'J1[5]'}
100- {pin_num: '71', pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/LPI2C1_SCL/LPUART1_RTS_b/TPM0_CH0, label: 'J4[12]/A5/ADC0_SE15/I2C1_SCL'}
101- {pin_num: '72', pin_signal: ADC0_SE11/CMP1_IN0/TSI0_CH15/PTC2/LPI2C1_SDA/LPUART1_CTS_b/TPM0_CH1, label: 'J4[10]/A4/ADC0_SE11/I2C1_SDA'}
102- {pin_num: '73', pin_signal: CMP1_IN1/PTC3/LLWU_P7/LPSPI0_PCS1/LPUART1_RX/TPM0_CH2/CLKOUT, label: 'J4[6]/A2/CMP1_IN1/SPI0_PCS1'}
103- {pin_num: '76', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, label: LEDRGB_GREEN, identifier: LED_GREEN}
104- {pin_num: '77', pin_signal: PTC5/LLWU_P9/LPSPI0_SCK/LPTMR0_ALT2/LPTMR1_ALT2/CMP0_OUT, label: 'J4[9]/CMP0_OUT'}
105- {pin_num: '78', pin_signal: CMP0_IN0/PTC6/LLWU_P10/LPSPI0_SOUT, label: 'J20[3]'}
106- {pin_num: '79', pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, label: 'J1[11]/SOF_OUT/FXIO_D20', identifier: SOF_OUT}
107- {pin_num: '80', pin_signal: CMP0_IN2/PTC8/LPI2C0_SCL/TPM0_CH4/FXIO0_D21, label: 'J1[7]/FXIO_D21'}
108- {pin_num: '81', pin_signal: CMP0_IN3/PTC9/LPI2C0_SDA/TPM0_CH5/FXIO0_D22, label: 'J1[9]/FXIO_D22'}
109- {pin_num: '82', pin_signal: PTC10/LPI2C1_SCL/FXIO0_D23, label: 'J1[13]/FXIO_D23'}
110- {pin_num: '83', pin_signal: PTC11/LLWU_P11/LPI2C1_SDA, label: 'J1[15]'}
111- {pin_num: '84', pin_signal: PTC12/LPI2C1_SCLS/TPM0_CLKIN, label: 'J1[14]/D6'}
112- {pin_num: '85', pin_signal: PTC13/LPI2C1_SDAS/TPM1_CLKIN, label: 'J1[16]/D7'}
113- {pin_num: '86', pin_signal: PTC14/EMVSIM0_CLK, label: 'JP1[3]/EMVSIM_CLK'}
114- {pin_num: '87', pin_signal: PTC15/EMVSIM0_RST, label: 'JP1[4]/EMVSIM_RST'}
115- {pin_num: '90', pin_signal: PTC16/EMVSIM0_VCCEN, label: 'JP1[5]/EMVSIM_VCCEN'}
116- {pin_num: '91', pin_signal: PTC17/EMVSIM0_IO/LPSPI0_PCS3, label: 'JP1[6]/EMVSIM_IO'}
117- {pin_num: '92', pin_signal: PTC18/EMVSIM0_PD/LPSPI0_PCS2, label: 'JP1[7]/EMVSIM_PD'}
118- {pin_num: '93', pin_signal: PTD0/LLWU_P12/LPSPI0_PCS0/LPUART2_RTS_b/TPM0_CH0/FXIO0_D0, label: 'J2[6]/D10/SPI0_PCS0'}
119- {pin_num: '94', pin_signal: ADC0_SE5b/PTD1/LPSPI0_SCK/LPUART2_CTS_b/TPM0_CH1/FXIO0_D1, label: 'J2[12]/D13/SPI0_SCK'}
120- {pin_num: '95', pin_signal: PTD2/LLWU_P13/LPSPI0_SOUT/LPUART2_RX/TPM0_CH2/FXIO0_D2, label: 'J2[8]/D11/SPI0_SOUT'}
121- {pin_num: '96', pin_signal: PTD3/LPSPI0_SIN/LPUART2_TX/TPM0_CH3/FXIO0_D3, label: 'J2[10]/D12/SPI0_SIN'}
122- {pin_num: '97', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, label: 'U10[11]/INT1_8700', identifier: ACCEL_INT1}
123- {pin_num: '98', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, label: 'Q1[1]/LIGHT_SENSOR', identifier: LIGHT_SENSOR}
124- {pin_num: '99', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/LPSPI1_SOUT/LPUART0_RX/FXIO0_D6, label: 'J2[2]/D8'}
125- {pin_num: '100', pin_signal: PTD7/LPSPI1_SIN/LPUART0_TX/FXIO0_D7, label: 'J2[4]/D9'}
126 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
127 */
128/* clang-format on */
129
130#include "fsl_common.h"
131#include "fsl_port.h"
132#include "fsl_gpio.h"
133#include "pin_mux.h"
134
135/* FUNCTION ************************************************************************************************************
136 *
137 * Function Name : BOARD_InitBootPins
138 * Description : Calls initialization functions.
139 *
140 * END ****************************************************************************************************************/
141void BOARD_InitBootPins(void)
142{
143 BOARD_InitPins();
144 BOARD_InitDEBUG_UARTPins();
145}
146
147/* clang-format off */
148/*
149 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
150BOARD_InitPins:
151- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
152- pin_list: []
153 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
154 */
155/* clang-format on */
156
157/* FUNCTION ************************************************************************************************************
158 *
159 * Function Name : BOARD_InitPins
160 * Description : Configures pin routing and optionally pin electrical features.
161 *
162 * END ****************************************************************************************************************/
163void BOARD_InitPins(void)
164{
165}
166
167/* clang-format off */
168/*
169 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
170BOARD_InitBUTTONsPins:
171- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
172- pin_list:
173 - {pin_num: '5', peripheral: GPIOE, signal: 'GPIO, 4', pin_signal: PTE4/LLWU_P2/LPSPI1_PCS0, direction: INPUT, slew_rate: slow, open_drain: disable, pull_select: up,
174 pull_enable: enable}
175 - {pin_num: '38', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: TSI0_CH5/PTA4/LLWU_P3/LPI2C1_SDA/TPM0_CH1/NMI0_b, direction: INPUT, slew_rate: slow, open_drain: disable,
176 pull_select: down, pull_enable: disable}
177 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
178 */
179/* clang-format on */
180
181/* FUNCTION ************************************************************************************************************
182 *
183 * Function Name : BOARD_InitBUTTONsPins
184 * Description : Configures pin routing and optionally pin electrical features.
185 *
186 * END ****************************************************************************************************************/
187void BOARD_InitBUTTONsPins(void)
188{
189 /* Clock Gate Control: Clock enabled */
190 CLOCK_EnableClock(kCLOCK_PortA);
191 /* Clock Gate Control: Clock enabled */
192 CLOCK_EnableClock(kCLOCK_PortE);
193
194 gpio_pin_config_t SW2_config = {
195 .pinDirection = kGPIO_DigitalInput,
196 .outputLogic = 0U
197 };
198 /* Initialize GPIO functionality on pin PTA4 (pin 38) */
199 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
200
201 gpio_pin_config_t SW3_config = {
202 .pinDirection = kGPIO_DigitalInput,
203 .outputLogic = 0U
204 };
205 /* Initialize GPIO functionality on pin PTE4 (pin 5) */
206 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
207
208 /* PORTA4 (pin 38) is configured as PTA4 */
209 PORT_SetPinMux(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_MuxAsGpio);
210
211 PORTA->PCR[4] =
212 ((PORTA->PCR[4] &
213 /* Mask bits to zero which are setting */
214 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
215
216 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
217 * field is set. */
218 | PORT_PCR_PS(kPORT_PullDown)
219
220 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
221 | PORT_PCR_PE(kPORT_PullDisable)
222
223 /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
224 * a digital output. */
225 | PORT_PCR_SRE(kPORT_SlowSlewRate)
226
227 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
228 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
229
230 const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
231 kPORT_PullUp,
232 /* Slow slew rate is configured */
233 kPORT_SlowSlewRate,
234 /* Passive filter is disabled */
235 kPORT_PassiveFilterDisable,
236 /* Open drain is disabled */
237 kPORT_OpenDrainDisable,
238 /* Low drive strength is configured */
239 kPORT_LowDriveStrength,
240 /* Pin is configured as PTE4 */
241 kPORT_MuxAsGpio,
242 /* Pin Control Register fields [15:0] are not locked */
243 kPORT_UnlockRegister};
244 /* PORTE4 (pin 5) is configured as PTE4 */
245 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
246}
247
248/* clang-format off */
249/*
250 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
251BOARD_InitLEDsPins:
252- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
253- pin_list:
254 - {pin_num: '26', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/ADC0_SE4b/PTE29/EMVSIM0_CLK/TPM0_CH2/TPM0_CLKIN, direction: OUTPUT, gpio_init_state: 'true',
255 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
256 - {pin_num: '28', peripheral: GPIOE, signal: 'GPIO, 31', pin_signal: PTE31/EMVSIM0_VCCEN/TPM0_CH4/TPM2_CLKIN/LPI2C0_HREQ, direction: OUTPUT, gpio_init_state: 'true',
257 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
258 - {pin_num: '76', peripheral: GPIOC, signal: 'GPIO, 4', pin_signal: PTC4/LLWU_P8/LPSPI0_PCS0/LPUART1_TX/TPM0_CH3/CMP1_OUT, direction: OUTPUT, gpio_init_state: 'true',
259 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
260 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
261 */
262/* clang-format on */
263
264/* FUNCTION ************************************************************************************************************
265 *
266 * Function Name : BOARD_InitLEDsPins
267 * Description : Configures pin routing and optionally pin electrical features.
268 *
269 * END ****************************************************************************************************************/
270void BOARD_InitLEDsPins(void)
271{
272 /* Clock Gate Control: Clock enabled */
273 CLOCK_EnableClock(kCLOCK_PortC);
274 /* Clock Gate Control: Clock enabled */
275 CLOCK_EnableClock(kCLOCK_PortE);
276
277 gpio_pin_config_t LED_GREEN_config = {
278 .pinDirection = kGPIO_DigitalOutput,
279 .outputLogic = 1U
280 };
281 /* Initialize GPIO functionality on pin PTC4 (pin 76) */
282 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
283
284 gpio_pin_config_t LED_RED_config = {
285 .pinDirection = kGPIO_DigitalOutput,
286 .outputLogic = 1U
287 };
288 /* Initialize GPIO functionality on pin PTE29 (pin 26) */
289 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
290
291 gpio_pin_config_t LED_BLUE_config = {
292 .pinDirection = kGPIO_DigitalOutput,
293 .outputLogic = 1U
294 };
295 /* Initialize GPIO functionality on pin PTE31 (pin 28) */
296 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
297
298 /* PORTC4 (pin 76) is configured as PTC4 */
299 PORT_SetPinMux(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, kPORT_MuxAsGpio);
300
301 PORTC->PCR[4] =
302 ((PORTC->PCR[4] &
303 /* Mask bits to zero which are setting */
304 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
305
306 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
307 * field is set. */
308 | PORT_PCR_PS(kPORT_PullDown)
309
310 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
311 | PORT_PCR_PE(kPORT_PullDisable)
312
313 /* Slew Rate Enable: Slow slew rate is configured on the corresponding pin, if the pin is configured as
314 * a digital output. */
315 | PORT_PCR_SRE(kPORT_SlowSlewRate)
316
317 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
318 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
319
320 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
321 kPORT_PullDisable,
322 /* Slow slew rate is configured */
323 kPORT_SlowSlewRate,
324 /* Passive filter is disabled */
325 kPORT_PassiveFilterDisable,
326 /* Open drain is disabled */
327 kPORT_OpenDrainDisable,
328 /* Low drive strength is configured */
329 kPORT_LowDriveStrength,
330 /* Pin is configured as PTE29 */
331 kPORT_MuxAsGpio,
332 /* Pin Control Register fields [15:0] are not locked */
333 kPORT_UnlockRegister};
334 /* PORTE29 (pin 26) is configured as PTE29 */
335 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
336
337 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
338 kPORT_PullDisable,
339 /* Slow slew rate is configured */
340 kPORT_SlowSlewRate,
341 /* Passive filter is disabled */
342 kPORT_PassiveFilterDisable,
343 /* Open drain is disabled */
344 kPORT_OpenDrainDisable,
345 /* Low drive strength is configured */
346 kPORT_LowDriveStrength,
347 /* Pin is configured as PTE31 */
348 kPORT_MuxAsGpio,
349 /* Pin Control Register fields [15:0] are not locked */
350 kPORT_UnlockRegister};
351 /* PORTE31 (pin 28) is configured as PTE31 */
352 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
353}
354
355/* clang-format off */
356/*
357 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
358BOARD_InitTOUCHPins:
359- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
360- pin_list:
361 - {pin_num: '35', peripheral: TSI0, signal: 'CH, 2', pin_signal: TSI0_CH2/PTA1/LPUART0_RX/TPM2_CH0, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
362 - {pin_num: '36', peripheral: TSI0, signal: 'CH, 3', pin_signal: TSI0_CH3/PTA2/LPUART0_TX/TPM2_CH1, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
363 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
364 */
365/* clang-format on */
366
367/* FUNCTION ************************************************************************************************************
368 *
369 * Function Name : BOARD_InitTOUCHPins
370 * Description : Configures pin routing and optionally pin electrical features.
371 *
372 * END ****************************************************************************************************************/
373void BOARD_InitTOUCHPins(void)
374{
375 /* Clock Gate Control: Clock enabled */
376 CLOCK_EnableClock(kCLOCK_PortA);
377
378 const port_pin_config_t TSI_ELECTRODE_1 = {/* Internal pull-up/down resistor is disabled */
379 kPORT_PullDisable,
380 /* Fast slew rate is configured */
381 kPORT_FastSlewRate,
382 /* Passive filter is disabled */
383 kPORT_PassiveFilterDisable,
384 /* Open drain is disabled */
385 kPORT_OpenDrainDisable,
386 /* Low drive strength is configured */
387 kPORT_LowDriveStrength,
388 /* Pin is configured as TSI0_CH2 */
389 kPORT_PinDisabledOrAnalog,
390 /* Pin Control Register fields [15:0] are not locked */
391 kPORT_UnlockRegister};
392 /* PORTA1 (pin 35) is configured as TSI0_CH2 */
393 PORT_SetPinConfig(BOARD_TSI_ELECTRODE_1_PORT, BOARD_TSI_ELECTRODE_1_PIN, &TSI_ELECTRODE_1);
394
395 const port_pin_config_t TSI_ELECTRODE_2 = {/* Internal pull-up/down resistor is disabled */
396 kPORT_PullDisable,
397 /* Fast slew rate is configured */
398 kPORT_FastSlewRate,
399 /* Passive filter is disabled */
400 kPORT_PassiveFilterDisable,
401 /* Open drain is disabled */
402 kPORT_OpenDrainDisable,
403 /* Low drive strength is configured */
404 kPORT_LowDriveStrength,
405 /* Pin is configured as TSI0_CH3 */
406 kPORT_PinDisabledOrAnalog,
407 /* Pin Control Register fields [15:0] are not locked */
408 kPORT_UnlockRegister};
409 /* PORTA2 (pin 36) is configured as TSI0_CH3 */
410 PORT_SetPinConfig(BOARD_TSI_ELECTRODE_2_PORT, BOARD_TSI_ELECTRODE_2_PIN, &TSI_ELECTRODE_2);
411}
412
413/* clang-format off */
414/*
415 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
416BOARD_InitLIGHT_SENSORPins:
417- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
418- pin_list:
419 - {pin_num: '98', peripheral: ADC0, signal: 'SE, 6b', pin_signal: ADC0_SE6b/PTD5/LPSPI1_SCK/LPUART2_TX/TPM0_CH5/LPUART0_CTS_b/FXIO0_D5, slew_rate: fast, open_drain: disable,
420 pull_select: down, pull_enable: disable}
421 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
422 */
423/* clang-format on */
424
425/* FUNCTION ************************************************************************************************************
426 *
427 * Function Name : BOARD_InitLIGHT_SENSORPins
428 * Description : Configures pin routing and optionally pin electrical features.
429 *
430 * END ****************************************************************************************************************/
431void BOARD_InitLIGHT_SENSORPins(void)
432{
433 /* Clock Gate Control: Clock enabled */
434 CLOCK_EnableClock(kCLOCK_PortD);
435
436 /* PORTD5 (pin 98) is configured as ADC0_SE6b */
437 PORT_SetPinMux(BOARD_LIGHT_SENSOR_PORT, BOARD_LIGHT_SENSOR_PIN, kPORT_PinDisabledOrAnalog);
438
439 PORTD->PCR[5] =
440 ((PORTD->PCR[5] &
441 /* Mask bits to zero which are setting */
442 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
443
444 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE
445 * field is set. */
446 | PORT_PCR_PS(kPORT_PullDown)
447
448 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
449 | PORT_PCR_PE(kPORT_PullDisable)
450
451 /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
452 * a digital output. */
453 | PORT_PCR_SRE(kPORT_FastSlewRate)
454
455 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
456 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
457}
458
459/* clang-format off */
460/*
461 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
462BOARD_InitUSBPins:
463- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
464- pin_list:
465 - {pin_num: '11', peripheral: USB0, signal: DM, pin_signal: USB0_DM}
466 - {pin_num: '10', peripheral: USB0, signal: DP, pin_signal: USB0_DP}
467 - {pin_num: '13', peripheral: USB0, signal: VREGIN, pin_signal: VREGIN}
468 - {pin_num: '79', peripheral: USB0, signal: SOF_OUT, pin_signal: CMP0_IN1/PTC7/LPSPI0_SIN/USB_SOF_OUT/FXIO0_D20, slew_rate: fast, open_drain: disable, pull_select: down,
469 pull_enable: disable}
470 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
471 */
472/* clang-format on */
473
474/* FUNCTION ************************************************************************************************************
475 *
476 * Function Name : BOARD_InitUSBPins
477 * Description : Configures pin routing and optionally pin electrical features.
478 *
479 * END ****************************************************************************************************************/
480void BOARD_InitUSBPins(void)
481{
482 /* Clock Gate Control: Clock enabled */
483 CLOCK_EnableClock(kCLOCK_PortC);
484
485 const port_pin_config_t SOF_OUT = {/* Internal pull-up/down resistor is disabled */
486 kPORT_PullDisable,
487 /* Fast slew rate is configured */
488 kPORT_FastSlewRate,
489 /* Passive filter is disabled */
490 kPORT_PassiveFilterDisable,
491 /* Open drain is disabled */
492 kPORT_OpenDrainDisable,
493 /* Low drive strength is configured */
494 kPORT_LowDriveStrength,
495 /* Pin is configured as USB_SOF_OUT */
496 kPORT_MuxAlt3,
497 /* Pin Control Register fields [15:0] are not locked */
498 kPORT_UnlockRegister};
499 /* PORTC7 (pin 79) is configured as USB_SOF_OUT */
500 PORT_SetPinConfig(BOARD_SOF_OUT_PORT, BOARD_SOF_OUT_PIN, &SOF_OUT);
501}
502
503/* clang-format off */
504/*
505 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
506BOARD_InitDEBUG_UARTPins:
507- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
508- pin_list:
509 - {pin_num: '62', peripheral: LPUART0, signal: RX, pin_signal: TSI0_CH9/PTB16/LPSPI1_SOUT/LPUART0_RX/TPM0_CLKIN/LPSPI2_PCS3/FXIO0_D16, slew_rate: fast, open_drain: disable,
510 pull_select: down, pull_enable: disable}
511 - {pin_num: '63', peripheral: LPUART0, signal: TX, pin_signal: TSI0_CH10/PTB17/LPSPI1_SIN/LPUART0_TX/TPM1_CLKIN/LPSPI2_PCS2/FXIO0_D17, direction: OUTPUT, slew_rate: fast,
512 open_drain: disable, pull_select: down, pull_enable: disable}
513 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
514 */
515/* clang-format on */
516
517/* FUNCTION ************************************************************************************************************
518 *
519 * Function Name : BOARD_InitDEBUG_UARTPins
520 * Description : Configures pin routing and optionally pin electrical features.
521 *
522 * END ****************************************************************************************************************/
523void BOARD_InitDEBUG_UARTPins(void)
524{
525 /* Clock Gate Control: Clock enabled */
526 CLOCK_EnableClock(kCLOCK_PortB);
527
528 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
529 kPORT_PullDisable,
530 /* Fast slew rate is configured */
531 kPORT_FastSlewRate,
532 /* Passive filter is disabled */
533 kPORT_PassiveFilterDisable,
534 /* Open drain is disabled */
535 kPORT_OpenDrainDisable,
536 /* Low drive strength is configured */
537 kPORT_LowDriveStrength,
538 /* Pin is configured as LPUART0_RX */
539 kPORT_MuxAlt3,
540 /* Pin Control Register fields [15:0] are not locked */
541 kPORT_UnlockRegister};
542 /* PORTB16 (pin 62) is configured as LPUART0_RX */
543 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
544
545 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
546 kPORT_PullDisable,
547 /* Fast slew rate is configured */
548 kPORT_FastSlewRate,
549 /* Passive filter is disabled */
550 kPORT_PassiveFilterDisable,
551 /* Open drain is disabled */
552 kPORT_OpenDrainDisable,
553 /* Low drive strength is configured */
554 kPORT_LowDriveStrength,
555 /* Pin is configured as LPUART0_TX */
556 kPORT_MuxAlt3,
557 /* Pin Control Register fields [15:0] are not locked */
558 kPORT_UnlockRegister};
559 /* PORTB17 (pin 63) is configured as LPUART0_TX */
560 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
561}
562
563/* clang-format off */
564/*
565 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
566BOARD_InitACCELPins:
567- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
568- pin_list:
569 - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: ACCEL_SDA, slew_rate: fast,
570 open_drain: enable, pull_select: down, pull_enable: disable}
571 - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: ACCEL_SCL, slew_rate: fast, open_drain: enable,
572 pull_select: down, pull_enable: disable}
573 - {pin_num: '97', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/LLWU_P14/LPSPI1_PCS0/LPUART2_RX/TPM0_CH4/LPUART0_RTS_b/FXIO0_D4, direction: INPUT, slew_rate: fast,
574 open_drain: disable, pull_select: up, pull_enable: enable}
575 - {pin_num: '6', peripheral: GPIOE, signal: 'GPIO, 5', pin_signal: PTE5/LPSPI1_PCS1, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
576 - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: ACCEL_RST, direction: OUTPUT,
577 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
578 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
579 */
580/* clang-format on */
581
582/* FUNCTION ************************************************************************************************************
583 *
584 * Function Name : BOARD_InitACCELPins
585 * Description : Configures pin routing and optionally pin electrical features.
586 *
587 * END ****************************************************************************************************************/
588void BOARD_InitACCELPins(void)
589{
590 /* Clock Gate Control: Clock enabled */
591 CLOCK_EnableClock(kCLOCK_PortD);
592 /* Clock Gate Control: Clock enabled */
593 CLOCK_EnableClock(kCLOCK_PortE);
594
595 gpio_pin_config_t ACCEL_INT1_config = {
596 .pinDirection = kGPIO_DigitalInput,
597 .outputLogic = 0U
598 };
599 /* Initialize GPIO functionality on pin PTD4 (pin 97) */
600 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
601
602 gpio_pin_config_t ACCEL_INT2_config = {
603 .pinDirection = kGPIO_DigitalInput,
604 .outputLogic = 0U
605 };
606 /* Initialize GPIO functionality on pin PTE5 (pin 6) */
607 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
608
609 gpio_pin_config_t ACCEL_RST_config = {
610 .pinDirection = kGPIO_DigitalOutput,
611 .outputLogic = 0U
612 };
613 /* Initialize GPIO functionality on pin PTE26 (pin 33) */
614 GPIO_PinInit(BOARD_ACCEL_RST_GPIO, BOARD_ACCEL_RST_PIN, &ACCEL_RST_config);
615
616 /* PORTD4 (pin 97) is configured as PTD4 */
617 PORT_SetPinMux(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, kPORT_MuxAsGpio);
618
619 PORTD->PCR[4] =
620 ((PORTD->PCR[4] &
621 /* Mask bits to zero which are setting */
622 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
623
624 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE
625 * field is set. */
626 | (uint32_t)(kPORT_PullUp)
627
628 /* Slew Rate Enable: Fast slew rate is configured on the corresponding pin, if the pin is configured as
629 * a digital output. */
630 | PORT_PCR_SRE(kPORT_FastSlewRate)
631
632 /* Open Drain Enable: Open drain output is disabled on the corresponding pin. */
633 | PORT_PCR_ODE(kPORT_OpenDrainDisable));
634
635 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
636 kPORT_PullDisable,
637 /* Fast slew rate is configured */
638 kPORT_FastSlewRate,
639 /* Passive filter is disabled */
640 kPORT_PassiveFilterDisable,
641 /* Open drain is enabled */
642 kPORT_OpenDrainEnable,
643 /* Low drive strength is configured */
644 kPORT_LowDriveStrength,
645 /* Pin is configured as LPI2C0_SCL */
646 kPORT_MuxAlt5,
647 /* Pin Control Register fields [15:0] are not locked */
648 kPORT_UnlockRegister};
649 /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
650 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
651
652 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
653 kPORT_PullDisable,
654 /* Fast slew rate is configured */
655 kPORT_FastSlewRate,
656 /* Passive filter is disabled */
657 kPORT_PassiveFilterDisable,
658 /* Open drain is enabled */
659 kPORT_OpenDrainEnable,
660 /* Low drive strength is configured */
661 kPORT_LowDriveStrength,
662 /* Pin is configured as LPI2C0_SDA */
663 kPORT_MuxAlt5,
664 /* Pin Control Register fields [15:0] are not locked */
665 kPORT_UnlockRegister};
666 /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
667 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
668
669 const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */
670 kPORT_PullDisable,
671 /* Slow slew rate is configured */
672 kPORT_SlowSlewRate,
673 /* Passive filter is disabled */
674 kPORT_PassiveFilterDisable,
675 /* Open drain is disabled */
676 kPORT_OpenDrainDisable,
677 /* Low drive strength is configured */
678 kPORT_LowDriveStrength,
679 /* Pin is configured as PTE26 */
680 kPORT_MuxAsGpio,
681 /* Pin Control Register fields [15:0] are not locked */
682 kPORT_UnlockRegister};
683 /* PORTE26 (pin 33) is configured as PTE26 */
684 PORT_SetPinConfig(BOARD_ACCEL_RST_PORT, BOARD_ACCEL_RST_PIN, &ACCEL_RST);
685
686 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
687 kPORT_PullUp,
688 /* Fast slew rate is configured */
689 kPORT_FastSlewRate,
690 /* Passive filter is disabled */
691 kPORT_PassiveFilterDisable,
692 /* Open drain is disabled */
693 kPORT_OpenDrainDisable,
694 /* Low drive strength is configured */
695 kPORT_LowDriveStrength,
696 /* Pin is configured as PTE5 */
697 kPORT_MuxAsGpio,
698 /* Pin Control Register fields [15:0] are not locked */
699 kPORT_UnlockRegister};
700 /* PORTE5 (pin 6) is configured as PTE5 */
701 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
702}
703
704/* clang-format off */
705/*
706 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
707BOARD_InitGYROPins:
708- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
709- pin_list:
710 - {pin_num: '31', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE20/PTE24/EMVSIM0_IO/TPM0_CH0/LPI2C0_SCL, identifier: GYRO_SCL, slew_rate: fast, open_drain: enable,
711 pull_select: down, pull_enable: disable}
712 - {pin_num: '32', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE21/PTE25/LLWU_P21/EMVSIM0_PD/TPM0_CH1/LPI2C0_SDA, identifier: GYRO_SDA, slew_rate: fast, open_drain: enable,
713 pull_select: down, pull_enable: disable}
714 - {pin_num: '1', peripheral: GPIOE, signal: 'GPIO, 0', pin_signal: ADC0_SE16/PTE0/RTC_CLKOUT/LPSPI1_SIN/LPUART1_TX/CMP0_OUT/LPI2C1_SDA, direction: INPUT, slew_rate: fast,
715 open_drain: disable, pull_select: up, pull_enable: enable}
716 - {pin_num: '2', peripheral: GPIOE, signal: 'GPIO, 1', pin_signal: ADC0_SE17/PTE1/LLWU_P0/LPSPI1_SOUT/LPUART1_RX/LPI2C1_SCL, direction: INPUT, slew_rate: fast,
717 open_drain: disable, pull_select: up, pull_enable: enable}
718 - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/RTC_CLKOUT/TPM0_CH5/LPI2C0_SCLS/USB_CLKIN, identifier: GYRO_RST, direction: OUTPUT, slew_rate: slow,
719 open_drain: disable, pull_select: down, pull_enable: disable}
720 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
721 */
722/* clang-format on */
723
724/* FUNCTION ************************************************************************************************************
725 *
726 * Function Name : BOARD_InitGYROPins
727 * Description : Configures pin routing and optionally pin electrical features.
728 *
729 * END ****************************************************************************************************************/
730void BOARD_InitGYROPins(void)
731{
732 /* Clock Gate Control: Clock enabled */
733 CLOCK_EnableClock(kCLOCK_PortE);
734
735 gpio_pin_config_t GYRO_INT1_config = {
736 .pinDirection = kGPIO_DigitalInput,
737 .outputLogic = 0U
738 };
739 /* Initialize GPIO functionality on pin PTE0 (pin 1) */
740 GPIO_PinInit(BOARD_GYRO_INT1_GPIO, BOARD_GYRO_INT1_PIN, &GYRO_INT1_config);
741
742 gpio_pin_config_t GYRO_INT2_config = {
743 .pinDirection = kGPIO_DigitalInput,
744 .outputLogic = 0U
745 };
746 /* Initialize GPIO functionality on pin PTE1 (pin 2) */
747 GPIO_PinInit(BOARD_GYRO_INT2_GPIO, BOARD_GYRO_INT2_PIN, &GYRO_INT2_config);
748
749 gpio_pin_config_t GYRO_RST_config = {
750 .pinDirection = kGPIO_DigitalOutput,
751 .outputLogic = 0U
752 };
753 /* Initialize GPIO functionality on pin PTE26 (pin 33) */
754 GPIO_PinInit(BOARD_GYRO_RST_GPIO, BOARD_GYRO_RST_PIN, &GYRO_RST_config);
755
756 const port_pin_config_t GYRO_INT1 = {/* Internal pull-up resistor is enabled */
757 kPORT_PullUp,
758 /* Fast slew rate is configured */
759 kPORT_FastSlewRate,
760 /* Passive filter is disabled */
761 kPORT_PassiveFilterDisable,
762 /* Open drain is disabled */
763 kPORT_OpenDrainDisable,
764 /* Low drive strength is configured */
765 kPORT_LowDriveStrength,
766 /* Pin is configured as PTE0 */
767 kPORT_MuxAsGpio,
768 /* Pin Control Register fields [15:0] are not locked */
769 kPORT_UnlockRegister};
770 /* PORTE0 (pin 1) is configured as PTE0 */
771 PORT_SetPinConfig(BOARD_GYRO_INT1_PORT, BOARD_GYRO_INT1_PIN, &GYRO_INT1);
772
773 const port_pin_config_t GYRO_INT2 = {/* Internal pull-up resistor is enabled */
774 kPORT_PullUp,
775 /* Fast slew rate is configured */
776 kPORT_FastSlewRate,
777 /* Passive filter is disabled */
778 kPORT_PassiveFilterDisable,
779 /* Open drain is disabled */
780 kPORT_OpenDrainDisable,
781 /* Low drive strength is configured */
782 kPORT_LowDriveStrength,
783 /* Pin is configured as PTE1 */
784 kPORT_MuxAsGpio,
785 /* Pin Control Register fields [15:0] are not locked */
786 kPORT_UnlockRegister};
787 /* PORTE1 (pin 2) is configured as PTE1 */
788 PORT_SetPinConfig(BOARD_GYRO_INT2_PORT, BOARD_GYRO_INT2_PIN, &GYRO_INT2);
789
790 const port_pin_config_t GYRO_SCL = {/* Internal pull-up/down resistor is disabled */
791 kPORT_PullDisable,
792 /* Fast slew rate is configured */
793 kPORT_FastSlewRate,
794 /* Passive filter is disabled */
795 kPORT_PassiveFilterDisable,
796 /* Open drain is enabled */
797 kPORT_OpenDrainEnable,
798 /* Low drive strength is configured */
799 kPORT_LowDriveStrength,
800 /* Pin is configured as LPI2C0_SCL */
801 kPORT_MuxAlt5,
802 /* Pin Control Register fields [15:0] are not locked */
803 kPORT_UnlockRegister};
804 /* PORTE24 (pin 31) is configured as LPI2C0_SCL */
805 PORT_SetPinConfig(BOARD_GYRO_SCL_PORT, BOARD_GYRO_SCL_PIN, &GYRO_SCL);
806
807 const port_pin_config_t GYRO_SDA = {/* Internal pull-up/down resistor is disabled */
808 kPORT_PullDisable,
809 /* Fast slew rate is configured */
810 kPORT_FastSlewRate,
811 /* Passive filter is disabled */
812 kPORT_PassiveFilterDisable,
813 /* Open drain is enabled */
814 kPORT_OpenDrainEnable,
815 /* Low drive strength is configured */
816 kPORT_LowDriveStrength,
817 /* Pin is configured as LPI2C0_SDA */
818 kPORT_MuxAlt5,
819 /* Pin Control Register fields [15:0] are not locked */
820 kPORT_UnlockRegister};
821 /* PORTE25 (pin 32) is configured as LPI2C0_SDA */
822 PORT_SetPinConfig(BOARD_GYRO_SDA_PORT, BOARD_GYRO_SDA_PIN, &GYRO_SDA);
823
824 const port_pin_config_t GYRO_RST = {/* Internal pull-up/down resistor is disabled */
825 kPORT_PullDisable,
826 /* Slow slew rate is configured */
827 kPORT_SlowSlewRate,
828 /* Passive filter is disabled */
829 kPORT_PassiveFilterDisable,
830 /* Open drain is disabled */
831 kPORT_OpenDrainDisable,
832 /* Low drive strength is configured */
833 kPORT_LowDriveStrength,
834 /* Pin is configured as PTE26 */
835 kPORT_MuxAsGpio,
836 /* Pin Control Register fields [15:0] are not locked */
837 kPORT_UnlockRegister};
838 /* PORTE26 (pin 33) is configured as PTE26 */
839 PORT_SetPinConfig(BOARD_GYRO_RST_PORT, BOARD_GYRO_RST_PIN, &GYRO_RST);
840}
841
842/* clang-format off */
843/*
844 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
845BOARD_InitOSCPins:
846- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
847- pin_list:
848 - {pin_num: '50', peripheral: SCG, signal: EXTAL0, pin_signal: EXTAL0/PTA18/LPUART1_RX/TPM0_CLKIN, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
849 - {pin_num: '51', peripheral: SCG, signal: XTAL0, pin_signal: XTAL0/PTA19/LPUART1_TX/TPM1_CLKIN/LPTMR0_ALT1/LPTMR1_ALT1, slew_rate: fast, open_drain: disable, pull_select: down,
850 pull_enable: disable}
851 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
852 */
853/* clang-format on */
854
855/* FUNCTION ************************************************************************************************************
856 *
857 * Function Name : BOARD_InitOSCPins
858 * Description : Configures pin routing and optionally pin electrical features.
859 *
860 * END ****************************************************************************************************************/
861void BOARD_InitOSCPins(void)
862{
863 /* Clock Gate Control: Clock enabled */
864 CLOCK_EnableClock(kCLOCK_PortA);
865
866 const port_pin_config_t EXTAL0 = {/* Internal pull-up/down resistor is disabled */
867 kPORT_PullDisable,
868 /* Fast slew rate is configured */
869 kPORT_FastSlewRate,
870 /* Passive filter is disabled */
871 kPORT_PassiveFilterDisable,
872 /* Open drain is disabled */
873 kPORT_OpenDrainDisable,
874 /* Low drive strength is configured */
875 kPORT_LowDriveStrength,
876 /* Pin is configured as EXTAL0 */
877 kPORT_PinDisabledOrAnalog,
878 /* Pin Control Register fields [15:0] are not locked */
879 kPORT_UnlockRegister};
880 /* PORTA18 (pin 50) is configured as EXTAL0 */
881 PORT_SetPinConfig(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, &EXTAL0);
882
883 const port_pin_config_t XTAL0 = {/* Internal pull-up/down resistor is disabled */
884 kPORT_PullDisable,
885 /* Fast slew rate is configured */
886 kPORT_FastSlewRate,
887 /* Passive filter is disabled */
888 kPORT_PassiveFilterDisable,
889 /* Open drain is disabled */
890 kPORT_OpenDrainDisable,
891 /* Low drive strength is configured */
892 kPORT_LowDriveStrength,
893 /* Pin is configured as XTAL0 */
894 kPORT_PinDisabledOrAnalog,
895 /* Pin Control Register fields [15:0] are not locked */
896 kPORT_UnlockRegister};
897 /* PORTA19 (pin 51) is configured as XTAL0 */
898 PORT_SetPinConfig(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, &XTAL0);
899}
900/***********************************************************************************************************************
901 * EOF
902 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:28:24 +0100