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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/K32L2B21A.h14744
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/K32L2B21A_features.h1407
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/arm/MK_P128_48MHZ_K32L2B.FLMbin0 -> 33536 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/drivers/fsl_clock.c506
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/drivers/fsl_clock.h809
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/fsl_device_registers.h36
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/gcc/K32L2B21xxxxA_flash.ld217
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/gcc/K32L2B21xxxxA_ram.ld209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/gcc/startup_K32L2B21A.S362
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/mcuxpresso/startup_k32l2b21a.c531
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/mcuxpresso/startup_k32l2b21a.cpp531
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/board.c107
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/board.h182
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/clock_config.c210
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/clock_config.h110
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/peripherals.c60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/pin_mux.c791
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/project_template/pin_mux.h271
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/system_K32L2B21A.c121
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/system_K32L2B21A.h123
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/template/RTE_Device.h115
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/utilities/fsl_shell.h292
27 files changed, 23313 insertions, 0 deletions
<
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/K32L2B21A.h b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/K32L2B21A.h
new file mode 100644
index 000000000..a52a39aa4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/K32L2B21A/K32L2B21A.h
@@ -0,0 +1,14744 @@
1/*
2** ###################################################################
3** Processors: K32L2B21VFM0A
4** K32L2B21VFT0A
5** K32L2B21VLH0A
6** K32L2B21VMP0A
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: K32L2B3xRM, Rev.0, July 2019
15** Version: rev. 1.0, 2019-07-30
16** Build: b191223
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for K32L2B21A
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2019 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 1.0 (2019-07-30)
32** Initial version.
33**
34** ###################################################################
35*/
36
37/*!
38 * @file K32L2B21A.h
39 * @version 1.0
40 * @date 2019-07-30
41 * @brief CMSIS Peripheral Access Layer for K32L2B21A
42 *
43 * CMSIS Peripheral Access Layer for K32L2B21A
44 */
45
46#ifndef _K32L2B21A_H_
47#define _K32L2B21A_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0100U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
54
55/* ----------------------------------------------------------------------------
56 -- Interrupt vector numbers
57 ---------------------------------------------------------------------------- */
58
59/*!
60 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
61 * @{
62 */
63
64/** Interrupt Number Definitions */
65#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
66
67typedef enum IRQn
68{
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
78
79 /* Device specific interrupts */
80 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
82 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
83 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
84 Reserved20_IRQn = 4, /**< Reserved interrupt */
85 FTFA_IRQn = 5, /**< Command complete and read collision */
86 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
87 LLWU_IRQn = 7, /**< Low leakage wakeup */
88 I2C0_IRQn = 8, /**< I2C0 interrupt */
89 I2C1_IRQn = 9, /**< I2C1 interrupt */
90 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
91 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
92 LPUART0_IRQn = 12, /**< LPUART0 status and error */
93 LPUART1_IRQn = 13, /**< LPUART1 status and error */
94 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
95 ADC0_IRQn = 15, /**< ADC0 interrupt */
96 CMP0_IRQn = 16, /**< CMP0 interrupt */
97 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
98 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
99 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
100 RTC_IRQn = 20, /**< RTC alarm */
101 RTC_Seconds_IRQn = 21, /**< RTC seconds */
102 PIT_IRQn = 22, /**< PIT interrupt */
103 Reserved39_IRQn = 23, /**< Reserved interrupt */
104 USB0_IRQn = 24, /**< USB0 interrupt */
105 DAC0_IRQn = 25, /**< DAC0 interrupt */
106 Reserved42_IRQn = 26, /**< Reserved interrupt */
107 Reserved43_IRQn = 27, /**< Reserved interrupt */
108 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
109 LCD_IRQn = 29, /**< LCD interrupt */
110 PORTA_IRQn = 30, /**< PORTA Pin detect */
111 PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
112} IRQn_Type;
113
114/*!
115 * @}
116 */ /* end of group Interrupt_vector_numbers */
117
118/* ----------------------------------------------------------------------------
119 -- Cortex M0 Core Configuration
120 ---------------------------------------------------------------------------- */
121
122/*!
123 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
124 * @{
125 */
126
127#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
128#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
129#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
130#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
131#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
132
133#include "core_cm0plus.h" /* Core Peripheral Access Layer */
134#include "system_K32L2B21A.h" /* Device specific configuration file */
135
136/*!
137 * @}
138 */ /* end of group Cortex_Core_Configuration */
139
140/* ----------------------------------------------------------------------------
141 -- Mapping Information
142 ---------------------------------------------------------------------------- */
143
144/*!
145 * @addtogroup Mapping_Information Mapping Information
146 * @{
147 */
148
149/** Mapping Information */
150/*!
151 * @addtogroup edma_request
152 * @{
153 */
154
155/*******************************************************************************
156 * Definitions
157 ******************************************************************************/
158
159/*!
160 * @brief Structure for the DMA hardware request
161 *
162 * Defines the structure for the DMA hardware request collections. The user can configure the
163 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
164 * of the hardware request varies according to the to SoC.
165 */
166typedef enum _dma_request_source
167{
168 kDmaRequestMux0Disable = 0 | 0x100U, /**< DMAMUX TriggerDisabled */
169 kDmaRequestMux0Reserved1 = 1 | 0x100U, /**< Reserved1 */
170 kDmaRequestMux0LPUART0Rx = 2 | 0x100U, /**< LPUART0 Receive */
171 kDmaRequestMux0LPUART0Tx = 3 | 0x100U, /**< LPUART0 Transmit */
172 kDmaRequestMux0LPUART1Rx = 4 | 0x100U, /**< LPUART1 Receive */
173 kDmaRequestMux0LPUART1Tx = 5 | 0x100U, /**< LPUART1 Transmit */
174 kDmaRequestMux0UART2Rx = 6 | 0x100U, /**< UART2 Receive */
175 kDmaRequestMux0UART2Tx = 7 | 0x100U, /**< UART2 Transmit */
176 kDmaRequestMux0Reserved8 = 8 | 0x100U, /**< Reserved8 */
177 kDmaRequestMux0Reserved9 = 9 | 0x100U, /**< Reserved9 */
178 kDmaRequestMux0FlexIOChannel0 = 10 | 0x100U, /**< FlexIO Channel 0 */
179 kDmaRequestMux0FlexIOChannel1 = 11 | 0x100U, /**< FlexIO Channel 1 */
180 kDmaRequestMux0FlexIOChannel2 = 12 | 0x100U, /**< FlexIO Channel 2 */
181 kDmaRequestMux0FlexIOChannel3 = 13 | 0x100U, /**< FlexIO Channel 3 */
182 kDmaRequestMux0SPI0Rx = 16 | 0x100U, /**< SPI0 Receive */
183 kDmaRequestMux0SPI0Tx = 17 | 0x100U, /**< SPI0 Transmit */
184 kDmaRequestMux0SPI1Rx = 18 | 0x100U, /**< SPI1 Receive */
185 kDmaRequestMux0SPI1Tx = 19 | 0x100U, /**< SPI1 Transmit */
186 kDmaRequestMux0Reserved20 = 20 | 0x100U, /**< Reserved20 */
187 kDmaRequestMux0Reserved21 = 21 | 0x100U, /**< Reserved21 */
188 kDmaRequestMux0I2C0 = 22 | 0x100U, /**< I2C0 */
189 kDmaRequestMux0I2C1 = 23 | 0x100U, /**< I2C1 */
190 kDmaRequestMux0TPM0Channel0 = 24 | 0x100U, /**< TPM0 channel 0 */
191 kDmaRequestMux0TPM0Channel1 = 25 | 0x100U, /**< TPM0 channel 1 */
192 kDmaRequestMux0TPM0Channel2 = 26 | 0x100U, /**< TPM0 channel 2 */
193 kDmaRequestMux0TPM0Channel3 = 27 | 0x100U, /**< TPM0 channel 3 */
194 kDmaRequestMux0TPM0Channel4 = 28 | 0x100U, /**< TPM0 channel 4 */
195 kDmaRequestMux0TPM0Channel5 = 29 | 0x100U, /**< TPM0 channel 5 */
196 kDmaRequestMux0Reserved30 = 30 | 0x100U, /**< Reserved30 */
197 kDmaRequestMux0Reserved31 = 31 | 0x100U, /**< Reserved31 */
198 kDmaRequestMux0TPM1Channel0 = 32 | 0x100U, /**< TPM1 channel 0 */
199 kDmaRequestMux0TPM1Channel1 = 33 | 0x100U, /**< TPM1 channel 1 */
200 kDmaRequestMux0TPM2Channel0 = 34 | 0x100U, /**< TPM2 channel 0 */
201 kDmaRequestMux0TPM2Channel1 = 35 | 0x100U, /**< TPM2 channel 1 */
202 kDmaRequestMux0Reserved36 = 36 | 0x100U, /**< Reserved36 */
203 kDmaRequestMux0Reserved37 = 37 | 0x100U, /**< Reserved37 */
204 kDmaRequestMux0Reserved38 = 38 | 0x100U, /**< Reserved38 */
205 kDmaRequestMux0Reserved39 = 39 | 0x100U, /**< Reserved39 */
206 kDmaRequestMux0ADC0 = 40 | 0x100U, /**< ADC0 */
207 kDmaRequestMux0Reserved41 = 41 | 0x100U, /**< Reserved41 */
208 kDmaRequestMux0CMP0 = 42 | 0x100U, /**< CMP0 */
209 kDmaRequestMux0Reserved43 = 43 | 0x100U, /**< Reserved43 */
210 kDmaRequestMux0Reserved44 = 44 | 0x100U, /**< Reserved44 */
211 kDmaRequestMux0DAC0 = 45 | 0x100U, /**< DAC0 */
212 kDmaRequestMux0Reserved46 = 46 | 0x100U, /**< Reserved46 */
213 kDmaRequestMux0Reserved47 = 47 | 0x100U, /**< Reserved47 */
214 kDmaRequestMux0Reserved48 = 48 | 0x100U, /**< Reserved48 */
215 kDmaRequestMux0PortA = 49 | 0x100U, /**< GPIO Port A */
216 kDmaRequestMux0Reserved50 = 50 | 0x100U, /**< Reserved50 */
217 kDmaRequestMux0PortC = 51 | 0x100U, /**< GPIO Port C */
218 kDmaRequestMux0PortD = 52 | 0x100U, /**< GPIO Port D */
219 kDmaRequestMux0Reserved53 = 53 | 0x100U, /**< Reserved53 */
220 kDmaRequestMux0TPM0Overflow = 54 | 0x100U, /**< TPM0 overflow */
221 kDmaRequestMux0TPM1Overflow = 55 | 0x100U, /**< TPM1 overflow */
222 kDmaRequestMux0TPM2Overflow = 56 | 0x100U, /**< TPM2 overflow */
223 kDmaRequestMux0Reserved57 = 57 | 0x100U, /**< Reserved57 */
224 kDmaRequestMux0Reserved58 = 58 | 0x100U, /**< Reserved58 */
225 kDmaRequestMux0Reserved59 = 59 | 0x100U, /**< Reserved59 */
226 kDmaRequestMux0AlwaysOn60 = 60 | 0x100U, /**< DMAMUX Always Enabled slot */
227 kDmaRequestMux0AlwaysOn61 = 61 | 0x100U, /**< DMAMUX Always Enabled slot */
228 kDmaRequestMux0AlwaysOn62 = 62 | 0x100U, /**< DMAMUX Always Enabled slot */
229 kDmaRequestMux0AlwaysOn63 = 63 | 0x100U, /**< DMAMUX Always Enabled slot */
230} dma_request_source_t;
231
232/* @} */
233
234/*!
235 * @}
236 */ /* end of group Mapping_Information */
237
238/* ----------------------------------------------------------------------------
239 -- Device Peripheral Access Layer
240 ---------------------------------------------------------------------------- */
241
242/*!
243 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
244 * @{
245 */
246
247/*
248** Start of section using anonymous unions
249*/
250
251#if defined(__ARMCC_VERSION)
252#if (__ARMCC_VERSION >= 6010050)
253#pragma clang diagnostic push
254#else
255#pragma push
256#pragma anon_unions
257#endif
258#elif defined(__CWCC__)
259#pragma push
260#pragma cpp_extensions on
261#elif defined(__GNUC__)
262/* anonymous unions are enabled by default */
263#elif defined(__IAR_SYSTEMS_ICC__)
264#pragma language = extended
265#else
266#error Not supported compiler type
267#endif
268
269/* ----------------------------------------------------------------------------
270 -- ADC Peripheral Access Layer
271 ---------------------------------------------------------------------------- */
272
273/*!
274 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
275 * @{
276 */
277
278/** ADC - Register Layout Typedef */
279typedef struct
280{
281 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
282 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
283 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
284 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
285 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
286 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
287 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
288 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
289 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
290 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
291 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
292 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
293 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
294 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
295 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
296 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
297 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
298 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
299 uint8_t RESERVED_0[4];
300 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
301 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
302 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
303 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
304 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
305 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
306 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
307} ADC_Type;
308
309/* ----------------------------------------------------------------------------
310 -- ADC Register Masks
311 ---------------------------------------------------------------------------- */
312
313/*!
314 * @addtogroup ADC_Register_Masks ADC Register Masks
315 * @{
316 */
317
318/*! @name SC1 - ADC Status and Control Registers 1 */
319/*! @{ */
320#define ADC_SC1_ADCH_MASK (0x1FU)
321#define ADC_SC1_ADCH_SHIFT (0U)
322/*! ADCH - Input channel select
323 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
324 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
325 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
326 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
327 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
328 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
329 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
330 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
331 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
332 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
333 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
334 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
335 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
336 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
337 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
338 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
339 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
340 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
341 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
342 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
343 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
344 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
345 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
346 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
347 * 0b11000..Reserved.
348 * 0b11001..Reserved.
349 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is
350 * selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap
351 * (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when
352 * DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
353 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is
354 * determined by SC2[REFSEL]. 0b11111..Module is disabled.
355 */
356#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
357#define ADC_SC1_DIFF_MASK (0x20U)
358#define ADC_SC1_DIFF_SHIFT (5U)
359/*! DIFF - Differential Mode Enable
360 * 0b0..Single-ended conversions and input channels are selected.
361 * 0b1..Differential conversions and input channels are selected.
362 */
363#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
364#define ADC_SC1_AIEN_MASK (0x40U)
365#define ADC_SC1_AIEN_SHIFT (6U)
366/*! AIEN - Interrupt Enable
367 * 0b0..Conversion complete interrupt is disabled.
368 * 0b1..Conversion complete interrupt is enabled.
369 */
370#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
371#define ADC_SC1_COCO_MASK (0x80U)
372#define ADC_SC1_COCO_SHIFT (7U)
373/*! COCO - Conversion Complete Flag
374 * 0b0..Conversion is not completed.
375 * 0b1..Conversion is completed.
376 */
377#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
378/*! @} */
379
380/* The count of ADC_SC1 */
381#define ADC_SC1_COUNT (2U)
382
383/*! @name CFG1 - ADC Configuration Register 1 */
384/*! @{ */
385#define ADC_CFG1_ADICLK_MASK (0x3U)
386#define ADC_CFG1_ADICLK_SHIFT (0U)
387/*! ADICLK - Input Clock Select
388 * 0b00..Bus clock
389 * 0b01..Bus clock divided by 2(BUSCLK/2)
390 * 0b10..Alternate clock (ALTCLK)
391 * 0b11..Asynchronous clock (ADACK)
392 */
393#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
394#define ADC_CFG1_MODE_MASK (0xCU)
395#define ADC_CFG1_MODE_SHIFT (2U)
396/*! MODE - Conversion mode selection
397 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's
398 * complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit
399 * conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
400 * differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..;
401 * when DIFF=1, it is differential 16-bit conversion with 2's complement output
402 */
403#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
404#define ADC_CFG1_ADLSMP_MASK (0x10U)
405#define ADC_CFG1_ADLSMP_SHIFT (4U)
406/*! ADLSMP - Sample Time Configuration
407 * 0b0..Short sample time.
408 * 0b1..Long sample time.
409 */
410#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
411#define ADC_CFG1_ADIV_MASK (0x60U)
412#define ADC_CFG1_ADIV_SHIFT (5U)
413/*! ADIV - Clock Divide Select
414 * 0b00..The divide ratio is 1 and the clock rate is input clock.
415 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
416 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
417 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
418 */
419#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
420#define ADC_CFG1_ADLPC_MASK (0x80U)
421#define ADC_CFG1_ADLPC_SHIFT (7U)
422/*! ADLPC - Low-Power Configuration
423 * 0b0..Normal power configuration.
424 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
425 */
426#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
427/*! @} */
428
429/*! @name CFG2 - ADC Configuration Register 2 */
430/*! @{ */
431#define ADC_CFG2_ADLSTS_MASK (0x3U)
432#define ADC_CFG2_ADLSTS_SHIFT (0U)
433/*! ADLSTS - Long Sample Time Select
434 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
435 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
436 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
437 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
438 */
439#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
440#define ADC_CFG2_ADHSC_MASK (0x4U)
441#define ADC_CFG2_ADHSC_SHIFT (2U)
442/*! ADHSC - High-Speed Configuration
443 * 0b0..Normal conversion sequence selected.
444 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
445 */
446#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
447#define ADC_CFG2_ADACKEN_MASK (0x8U)
448#define ADC_CFG2_ADACKEN_SHIFT (3U)
449/*! ADACKEN - Asynchronous Clock Output Enable
450 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion
451 * is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
452 */
453#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
454#define ADC_CFG2_MUXSEL_MASK (0x10U)
455#define ADC_CFG2_MUXSEL_SHIFT (4U)
456/*! MUXSEL - ADC Mux Select
457 * 0b0..ADxxa channels are selected.
458 * 0b1..ADxxb channels are selected.
459 */
460#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
461/*! @} */
462
463/*! @name R - ADC Data Result Register */
464/*! @{ */
465#define ADC_R_D_MASK (0xFFFFU)
466#define ADC_R_D_SHIFT (0U)
467/*! D - Data result
468 */
469#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
470/*! @} */
471
472/* The count of ADC_R */
473#define ADC_R_COUNT (2U)
474
475/*! @name CV1 - Compare Value Registers */
476/*! @{ */
477#define ADC_CV1_CV_MASK (0xFFFFU)
478#define ADC_CV1_CV_SHIFT (0U)
479/*! CV - Compare Value.
480 */
481#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
482/*! @} */
483
484/*! @name CV2 - Compare Value Registers */
485/*! @{ */
486#define ADC_CV2_CV_MASK (0xFFFFU)
487#define ADC_CV2_CV_SHIFT (0U)
488/*! CV - Compare Value.
489 */
490#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
491/*! @} */
492
493/*! @name SC2 - Status and Control Register 2 */
494/*! @{ */
495#define ADC_SC2_REFSEL_MASK (0x3U)
496#define ADC_SC2_REFSEL_SHIFT (0U)
497/*! REFSEL - Voltage Reference Selection
498 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
499 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or
500 * internal sources depending on the MCU configuration. See the chip configuration information for details
501 * specific to this MCU
502 * 0b10..Reserved
503 * 0b11..Reserved
504 */
505#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
506#define ADC_SC2_DMAEN_MASK (0x4U)
507#define ADC_SC2_DMAEN_SHIFT (2U)
508/*! DMAEN - DMA Enable
509 * 0b0..DMA is disabled.
510 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any
511 * of the SC1n[COCO] flags is asserted.
512 */
513#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
514#define ADC_SC2_ACREN_MASK (0x8U)
515#define ADC_SC2_ACREN_SHIFT (3U)
516/*! ACREN - Compare Function Range Enable
517 * 0b0..Range function disabled. Only CV1 is compared.
518 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
519 */
520#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
521#define ADC_SC2_ACFGT_MASK (0x10U)
522#define ADC_SC2_ACFGT_SHIFT (4U)
523/*! ACFGT - Compare Function Greater Than Enable
524 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality
525 * based on the values placed in CV1 and CV2.
526 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the
527 * values placed in CV1 and CV2.
528 */
529#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
530#define ADC_SC2_ACFE_MASK (0x20U)
531#define ADC_SC2_ACFE_SHIFT (5U)
532/*! ACFE - Compare Function Enable
533 * 0b0..Compare function disabled.
534 * 0b1..Compare function enabled.
535 */
536#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
537#define ADC_SC2_ADTRG_MASK (0x40U)
538#define ADC_SC2_ADTRG_SHIFT (6U)
539/*! ADTRG - Conversion Trigger Select
540 * 0b0..Software trigger selected.
541 * 0b1..Hardware trigger selected.
542 */
543#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
544#define ADC_SC2_ADACT_MASK (0x80U)
545#define ADC_SC2_ADACT_SHIFT (7U)
546/*! ADACT - Conversion Active
547 * 0b0..Conversion not in progress.
548 * 0b1..Conversion in progress.
549 */
550#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
551/*! @} */
552
553/*! @name SC3 - Status and Control Register 3 */
554/*! @{ */
555#define ADC_SC3_AVGS_MASK (0x3U)
556#define ADC_SC3_AVGS_SHIFT (0U)
557/*! AVGS - Hardware Average Select
558 * 0b00..4 samples averaged.
559 * 0b01..8 samples averaged.
560 * 0b10..16 samples averaged.
561 * 0b11..32 samples averaged.
562 */
563#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
564#define ADC_SC3_AVGE_MASK (0x4U)
565#define ADC_SC3_AVGE_SHIFT (2U)
566/*! AVGE - Hardware Average Enable
567 * 0b0..Hardware average function disabled.
568 * 0b1..Hardware average function enabled.
569 */
570#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
571#define ADC_SC3_ADCO_MASK (0x8U)
572#define ADC_SC3_ADCO_SHIFT (3U)
573/*! ADCO - Continuous Conversion Enable
574 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after
575 * initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is
576 * enabled, that is, AVGE=1, after initiating a conversion.
577 */
578#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
579#define ADC_SC3_CALF_MASK (0x40U)
580#define ADC_SC3_CALF_SHIFT (6U)
581/*! CALF - Calibration Failed Flag
582 * 0b0..Calibration completed normally.
583 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
584 */
585#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
586#define ADC_SC3_CAL_MASK (0x80U)
587#define ADC_SC3_CAL_SHIFT (7U)
588/*! CAL - Calibration
589 */
590#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
591/*! @} */
592
593/*! @name OFS - ADC Offset Correction Register */
594/*! @{ */
595#define ADC_OFS_OFS_MASK (0xFFFFU)
596#define ADC_OFS_OFS_SHIFT (0U)
597/*! OFS - Offset Error Correction Value
598 */
599#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
600/*! @} */
601
602/*! @name PG - ADC Plus-Side Gain Register */
603/*! @{ */
604#define ADC_PG_PG_MASK (0xFFFFU)
605#define ADC_PG_PG_SHIFT (0U)
606/*! PG - Plus-Side Gain
607 */
608#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
609/*! @} */
610
611/*! @name MG - ADC Minus-Side Gain Register */
612/*! @{ */
613#define ADC_MG_MG_MASK (0xFFFFU)
614#define ADC_MG_MG_SHIFT (0U)
615/*! MG - Minus-Side Gain
616 */
617#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
618/*! @} */
619
620/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
621/*! @{ */
622#define ADC_CLPD_CLPD_MASK (0x3FU)
623#define ADC_CLPD_CLPD_SHIFT (0U)
624/*! CLPD - Calibration Value
625 */
626#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
627/*! @} */
628
629/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
630/*! @{ */
631#define ADC_CLPS_CLPS_MASK (0x3FU)
632#define ADC_CLPS_CLPS_SHIFT (0U)
633/*! CLPS - Calibration Value
634 */
635#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
636/*! @} */
637
638/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
639/*! @{ */
640#define ADC_CLP4_CLP4_MASK (0x3FFU)
641#define ADC_CLP4_CLP4_SHIFT (0U)
642/*! CLP4 - Calibration Value
643 */
644#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
645/*! @} */
646
647/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
648/*! @{ */
649#define ADC_CLP3_CLP3_MASK (0x1FFU)
650#define ADC_CLP3_CLP3_SHIFT (0U)
651/*! CLP3 - Calibration Value
652 */
653#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
654/*! @} */
655
656/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
657/*! @{ */
658#define ADC_CLP2_CLP2_MASK (0xFFU)
659#define ADC_CLP2_CLP2_SHIFT (0U)
660/*! CLP2 - Calibration Value
661 */
662#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
663/*! @} */
664
665/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
666/*! @{ */
667#define ADC_CLP1_CLP1_MASK (0x7FU)
668#define ADC_CLP1_CLP1_SHIFT (0U)
669/*! CLP1 - Calibration Value
670 */
671#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
672/*! @} */
673
674/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
675/*! @{ */
676#define ADC_CLP0_CLP0_MASK (0x3FU)
677#define ADC_CLP0_CLP0_SHIFT (0U)
678/*! CLP0 - Calibration Value
679 */
680#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
681/*! @} */
682
683/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
684/*! @{ */
685#define ADC_CLMD_CLMD_MASK (0x3FU)
686#define ADC_CLMD_CLMD_SHIFT (0U)
687/*! CLMD - Calibration Value
688 */
689#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
690/*! @} */
691
692/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
693/*! @{ */
694#define ADC_CLMS_CLMS_MASK (0x3FU)
695#define ADC_CLMS_CLMS_SHIFT (0U)
696/*! CLMS - Calibration Value
697 */
698#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
699/*! @} */
700
701/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
702/*! @{ */
703#define ADC_CLM4_CLM4_MASK (0x3FFU)
704#define ADC_CLM4_CLM4_SHIFT (0U)
705/*! CLM4 - Calibration Value
706 */
707#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
708/*! @} */
709
710/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
711/*! @{ */
712#define ADC_CLM3_CLM3_MASK (0x1FFU)
713#define ADC_CLM3_CLM3_SHIFT (0U)
714/*! CLM3 - Calibration Value
715 */
716#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
717/*! @} */
718
719/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
720/*! @{ */
721#define ADC_CLM2_CLM2_MASK (0xFFU)
722#define ADC_CLM2_CLM2_SHIFT (0U)
723/*! CLM2 - Calibration Value
724 */
725#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
726/*! @} */
727
728/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
729/*! @{ */
730#define ADC_CLM1_CLM1_MASK (0x7FU)
731#define ADC_CLM1_CLM1_SHIFT (0U)
732/*! CLM1 - Calibration Value
733 */
734#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
735/*! @} */
736
737/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
738/*! @{ */
739#define ADC_CLM0_CLM0_MASK (0x3FU)
740#define ADC_CLM0_CLM0_SHIFT (0U)
741/*! CLM0 - Calibration Value
742 */
743#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
744/*! @} */
745
746/*!
747 * @}
748 */ /* end of group ADC_Register_Masks */
749
750/* ADC - Peripheral instance base addresses */
751/** Peripheral ADC0 base address */
752#define ADC0_BASE (0x4003B000u)
753/** Peripheral ADC0 base pointer */
754#define ADC0 ((ADC_Type *)ADC0_BASE)
755/** Array initializer of ADC peripheral base addresses */
756#define ADC_BASE_ADDRS \
757 { \
758 ADC0_BASE \
759 }
760/** Array initializer of ADC peripheral base pointers */
761#define ADC_BASE_PTRS \
762 { \
763 ADC0 \
764 }
765/** Interrupt vectors for the ADC peripheral type */
766#define ADC_IRQS \
767 { \
768 ADC0_IRQn \
769 }
770
771/*!
772 * @}
773 */ /* end of group ADC_Peripheral_Access_Layer */
774
775/* ----------------------------------------------------------------------------
776 -- CMP Peripheral Access Layer
777 ---------------------------------------------------------------------------- */
778
779/*!
780 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
781 * @{
782 */
783
784/** CMP - Register Layout Typedef */
785typedef struct
786{
787 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
788 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
789 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
790 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
791 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
792 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
793} CMP_Type;
794
795/* ----------------------------------------------------------------------------
796 -- CMP Register Masks
797 ---------------------------------------------------------------------------- */
798
799/*!
800 * @addtogroup CMP_Register_Masks CMP Register Masks
801 * @{
802 */
803
804/*! @name CR0 - CMP Control Register 0 */
805/*! @{ */
806#define CMP_CR0_HYSTCTR_MASK (0x3U)
807#define CMP_CR0_HYSTCTR_SHIFT (0U)
808/*! HYSTCTR - Comparator hard block hysteresis control
809 * 0b00..Level 0
810 * 0b01..Level 1
811 * 0b10..Level 2
812 * 0b11..Level 3
813 */
814#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
815#define CMP_CR0_FILTER_CNT_MASK (0x70U)
816#define CMP_CR0_FILTER_CNT_SHIFT (4U)
817/*! FILTER_CNT - Filter Sample Count
818 * 0b000..Filter is disabled. SE = 0, COUT = COUTA.
819 * 0b001..One sample must agree. The comparator output is simply sampled.
820 * 0b010..2 consecutive samples must agree.
821 * 0b011..3 consecutive samples must agree.
822 * 0b100..4 consecutive samples must agree.
823 * 0b101..5 consecutive samples must agree.
824 * 0b110..6 consecutive samples must agree.
825 * 0b111..7 consecutive samples must agree.
826 */
827#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
828/*! @} */
829
830/*! @name CR1 - CMP Control Register 1 */
831/*! @{ */
832#define CMP_CR1_EN_MASK (0x1U)
833#define CMP_CR1_EN_SHIFT (0U)
834/*! EN - Comparator Module Enable
835 * 0b0..Analog Comparator is disabled.
836 * 0b1..Analog Comparator is enabled.
837 */
838#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
839#define CMP_CR1_OPE_MASK (0x2U)
840#define CMP_CR1_OPE_SHIFT (1U)
841/*! OPE - Comparator Output Pin Enable
842 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has
843 * no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on
844 * the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has
845 * no effect.
846 */
847#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
848#define CMP_CR1_COS_MASK (0x4U)
849#define CMP_CR1_COS_SHIFT (2U)
850/*! COS - Comparator Output Select
851 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
852 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
853 */
854#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
855#define CMP_CR1_INV_MASK (0x8U)
856#define CMP_CR1_INV_SHIFT (3U)
857/*! INV - Comparator INVERT
858 * 0b0..Does not invert the comparator output.
859 * 0b1..Inverts the comparator output.
860 */
861#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
862#define CMP_CR1_PMODE_MASK (0x10U)
863#define CMP_CR1_PMODE_SHIFT (4U)
864/*! PMODE - Power Mode Select
865 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower
866 * current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation
867 * delay and higher current consumption.
868 */
869#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
870#define CMP_CR1_TRIGM_MASK (0x20U)
871#define CMP_CR1_TRIGM_SHIFT (5U)
872/*! TRIGM - Trigger Mode Enable
873 * 0b0..Trigger mode is disabled.
874 * 0b1..Trigger mode is enabled.
875 */
876#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
877#define CMP_CR1_WE_MASK (0x40U)
878#define CMP_CR1_WE_SHIFT (6U)
879/*! WE - Windowing Enable
880 * 0b0..Windowing mode is not selected.
881 * 0b1..Windowing mode is selected.
882 */
883#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
884#define CMP_CR1_SE_MASK (0x80U)
885#define CMP_CR1_SE_SHIFT (7U)
886/*! SE - Sample Enable
887 * 0b0..Sampling mode is not selected.
888 * 0b1..Sampling mode is selected.
889 */
890#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
891/*! @} */
892
893/*! @name FPR - CMP Filter Period Register */
894/*! @{ */
895#define CMP_FPR_FILT_PER_MASK (0xFFU)
896#define CMP_FPR_FILT_PER_SHIFT (0U)
897/*! FILT_PER - Filter Sample Period
898 */
899#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
900/*! @} */
901
902/*! @name SCR - CMP Status and Control Register */
903/*! @{ */
904#define CMP_SCR_COUT_MASK (0x1U)
905#define CMP_SCR_COUT_SHIFT (0U)
906/*! COUT - Analog Comparator Output
907 */
908#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
909#define CMP_SCR_CFF_MASK (0x2U)
910#define CMP_SCR_CFF_SHIFT (1U)
911/*! CFF - Analog Comparator Flag Falling
912 * 0b0..Falling-edge on COUT has not been detected.
913 * 0b1..Falling-edge on COUT has occurred.
914 */
915#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
916#define CMP_SCR_CFR_MASK (0x4U)
917#define CMP_SCR_CFR_SHIFT (2U)
918/*! CFR - Analog Comparator Flag Rising
919 * 0b0..Rising-edge on COUT has not been detected.
920 * 0b1..Rising-edge on COUT has occurred.
921 */
922#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
923#define CMP_SCR_IEF_MASK (0x8U)
924#define CMP_SCR_IEF_SHIFT (3U)
925/*! IEF - Comparator Interrupt Enable Falling
926 * 0b0..Interrupt is disabled.
927 * 0b1..Interrupt is enabled.
928 */
929#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
930#define CMP_SCR_IER_MASK (0x10U)
931#define CMP_SCR_IER_SHIFT (4U)
932/*! IER - Comparator Interrupt Enable Rising
933 * 0b0..Interrupt is disabled.
934 * 0b1..Interrupt is enabled.
935 */
936#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
937#define CMP_SCR_DMAEN_MASK (0x40U)
938#define CMP_SCR_DMAEN_SHIFT (6U)
939/*! DMAEN - DMA Enable Control
940 * 0b0..DMA is disabled.
941 * 0b1..DMA is enabled.
942 */
943#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
944/*! @} */
945
946/*! @name DACCR - DAC Control Register */
947/*! @{ */
948#define CMP_DACCR_VOSEL_MASK (0x3FU)
949#define CMP_DACCR_VOSEL_SHIFT (0U)
950/*! VOSEL - DAC Output Voltage Select
951 */
952#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
953#define CMP_DACCR_VRSEL_MASK (0x40U)
954#define CMP_DACCR_VRSEL_SHIFT (6U)
955/*! VRSEL - Supply Voltage Reference Source Select
956 * 0b0..Vin1 is selected as resistor ladder network supply reference.
957 * 0b1..Vin2 is selected as resistor ladder network supply reference.
958 */
959#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
960#define CMP_DACCR_DACEN_MASK (0x80U)
961#define CMP_DACCR_DACEN_SHIFT (7U)
962/*! DACEN - DAC Enable
963 * 0b0..DAC is disabled.
964 * 0b1..DAC is enabled.
965 */
966#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
967/*! @} */
968
969/*! @name MUXCR - MUX Control Register */
970/*! @{ */
971#define CMP_MUXCR_MSEL_MASK (0x7U)
972#define CMP_MUXCR_MSEL_SHIFT (0U)
973/*! MSEL - Minus Input Mux Control
974 * 0b000..IN0
975 * 0b001..IN1
976 * 0b010..IN2
977 * 0b011..IN3
978 * 0b100..IN4
979 * 0b101..IN5
980 * 0b110..IN6
981 * 0b111..IN7
982 */
983#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
984#define CMP_MUXCR_PSEL_MASK (0x38U)
985#define CMP_MUXCR_PSEL_SHIFT (3U)
986/*! PSEL - Plus Input Mux Control
987 * 0b000..IN0
988 * 0b001..IN1
989 * 0b010..IN2
990 * 0b011..IN3
991 * 0b100..IN4
992 * 0b101..IN5
993 * 0b110..IN6
994 * 0b111..IN7
995 */
996#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
997#define CMP_MUXCR_PSTM_MASK (0x80U)
998#define CMP_MUXCR_PSTM_SHIFT (7U)
999/*! PSTM - Pass Through Mode Enable
1000 * 0b0..Pass Through Mode is disabled.
1001 * 0b1..Pass Through Mode is enabled.
1002 */
1003#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
1004/*! @} */
1005
1006/*!
1007 * @}
1008 */ /* end of group CMP_Register_Masks */
1009
1010/* CMP - Peripheral instance base addresses */
1011/** Peripheral CMP0 base address */
1012#define CMP0_BASE (0x40073000u)
1013/** Peripheral CMP0 base pointer */
1014#define CMP0 ((CMP_Type *)CMP0_BASE)
1015/** Array initializer of CMP peripheral base addresses */
1016#define CMP_BASE_ADDRS \
1017 { \
1018 CMP0_BASE \
1019 }
1020/** Array initializer of CMP peripheral base pointers */
1021#define CMP_BASE_PTRS \
1022 { \
1023 CMP0 \
1024 }
1025/** Interrupt vectors for the CMP peripheral type */
1026#define CMP_IRQS \
1027 { \
1028 CMP0_IRQn \
1029 }
1030
1031/*!
1032 * @}
1033 */ /* end of group CMP_Peripheral_Access_Layer */
1034
1035/* ----------------------------------------------------------------------------
1036 -- DAC Peripheral Access Layer
1037 ---------------------------------------------------------------------------- */
1038
1039/*!
1040 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1041 * @{
1042 */
1043
1044/** DAC - Register Layout Typedef */
1045typedef struct
1046{
1047 struct
1048 { /* offset: 0x0, array step: 0x2 */
1049 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1050 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1051 } DAT[2];
1052 uint8_t RESERVED_0[28];
1053 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
1054 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
1055 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
1056 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
1057} DAC_Type;
1058
1059/* ----------------------------------------------------------------------------
1060 -- DAC Register Masks
1061 ---------------------------------------------------------------------------- */
1062
1063/*!
1064 * @addtogroup DAC_Register_Masks DAC Register Masks
1065 * @{
1066 */
1067
1068/*! @name DATL - DAC Data Low Register */
1069/*! @{ */
1070#define DAC_DATL_DATA0_MASK (0xFFU)
1071#define DAC_DATL_DATA0_SHIFT (0U)
1072/*! DATA0 - DATA0
1073 */
1074#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
1075/*! @} */
1076
1077/* The count of DAC_DATL */
1078#define DAC_DATL_COUNT (2U)
1079
1080/*! @name DATH - DAC Data High Register */
1081/*! @{ */
1082#define DAC_DATH_DATA1_MASK (0xFU)
1083#define DAC_DATH_DATA1_SHIFT (0U)
1084/*! DATA1 - DATA1
1085 */
1086#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
1087/*! @} */
1088
1089/* The count of DAC_DATH */
1090#define DAC_DATH_COUNT (2U)
1091
1092/*! @name SR - DAC Status Register */
1093/*! @{ */
1094#define DAC_SR_DACBFRPBF_MASK (0x1U)
1095#define DAC_SR_DACBFRPBF_SHIFT (0U)
1096/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
1097 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
1098 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
1099 */
1100#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
1101#define DAC_SR_DACBFRPTF_MASK (0x2U)
1102#define DAC_SR_DACBFRPTF_SHIFT (1U)
1103/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
1104 * 0b0..The DAC buffer read pointer is not zero.
1105 * 0b1..The DAC buffer read pointer is zero.
1106 */
1107#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
1108/*! @} */
1109
1110/*! @name C0 - DAC Control Register */
1111/*! @{ */
1112#define DAC_C0_DACBBIEN_MASK (0x1U)
1113#define DAC_C0_DACBBIEN_SHIFT (0U)
1114/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
1115 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
1116 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
1117 */
1118#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
1119#define DAC_C0_DACBTIEN_MASK (0x2U)
1120#define DAC_C0_DACBTIEN_SHIFT (1U)
1121/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
1122 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
1123 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
1124 */
1125#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
1126#define DAC_C0_LPEN_MASK (0x8U)
1127#define DAC_C0_LPEN_SHIFT (3U)
1128/*! LPEN - DAC Low Power Control
1129 * 0b0..High-Power mode
1130 * 0b1..Low-Power mode
1131 */
1132#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
1133#define DAC_C0_DACSWTRG_MASK (0x10U)
1134#define DAC_C0_DACSWTRG_SHIFT (4U)
1135/*! DACSWTRG - DAC Software Trigger
1136 * 0b0..The DAC soft trigger is not valid.
1137 * 0b1..The DAC soft trigger is valid.
1138 */
1139#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
1140#define DAC_C0_DACTRGSEL_MASK (0x20U)
1141#define DAC_C0_DACTRGSEL_SHIFT (5U)
1142/*! DACTRGSEL - DAC Trigger Select
1143 * 0b0..The DAC hardware trigger is selected.
1144 * 0b1..The DAC software trigger is selected.
1145 */
1146#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
1147#define DAC_C0_DACRFS_MASK (0x40U)
1148#define DAC_C0_DACRFS_SHIFT (6U)
1149/*! DACRFS - DAC Reference Select
1150 * 0b0..The DAC selects DACREF_1 as the reference voltage.
1151 * 0b1..The DAC selects DACREF_2 as the reference voltage.
1152 */
1153#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
1154#define DAC_C0_DACEN_MASK (0x80U)
1155#define DAC_C0_DACEN_SHIFT (7U)
1156/*! DACEN - DAC Enable
1157 * 0b0..The DAC system is disabled.
1158 * 0b1..The DAC system is enabled.
1159 */
1160#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
1161/*! @} */
1162
1163/*! @name C1 - DAC Control Register 1 */
1164/*! @{ */
1165#define DAC_C1_DACBFEN_MASK (0x1U)
1166#define DAC_C1_DACBFEN_SHIFT (0U)
1167/*! DACBFEN - DAC Buffer Enable
1168 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1169 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means
1170 * converted data can be from any word of the buffer.
1171 */
1172#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
1173#define DAC_C1_DACBFMD_MASK (0x6U)
1174#define DAC_C1_DACBFMD_SHIFT (1U)
1175/*! DACBFMD - DAC Buffer Work Mode Select
1176 * 0b00..Normal mode
1177 * 0b01..Reserved
1178 * 0b10..One-Time Scan mode
1179 * 0b11..FIFO mode
1180 */
1181#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
1182#define DAC_C1_DMAEN_MASK (0x80U)
1183#define DAC_C1_DMAEN_SHIFT (7U)
1184/*! DMAEN - DMA Enable Select
1185 * 0b0..DMA is disabled.
1186 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
1187 * interrupts will not be presented on this module at the same time.
1188 */
1189#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
1190/*! @} */
1191
1192/*! @name C2 - DAC Control Register 2 */
1193/*! @{ */
1194#define DAC_C2_DACBFUP_MASK (0x1U)
1195#define DAC_C2_DACBFUP_SHIFT (0U)
1196/*! DACBFUP - DAC Buffer Upper Limit
1197 */
1198#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
1199#define DAC_C2_DACBFRP_MASK (0x10U)
1200#define DAC_C2_DACBFRP_SHIFT (4U)
1201/*! DACBFRP - DAC Buffer Read Pointer
1202 */
1203#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
1204/*! @} */
1205
1206/*!
1207 * @}
1208 */ /* end of group DAC_Register_Masks */
1209
1210/* DAC - Peripheral instance base addresses */
1211/** Peripheral DAC0 base address */
1212#define DAC0_BASE (0x4003F000u)
1213/** Peripheral DAC0 base pointer */
1214#define DAC0 ((DAC_Type *)DAC0_BASE)
1215/** Array initializer of DAC peripheral base addresses */
1216#define DAC_BASE_ADDRS \
1217 { \
1218 DAC0_BASE \
1219 }
1220/** Array initializer of DAC peripheral base pointers */
1221#define DAC_BASE_PTRS \
1222 { \
1223 DAC0 \
1224 }
1225/** Interrupt vectors for the DAC peripheral type */
1226#define DAC_IRQS \
1227 { \
1228 DAC0_IRQn \
1229 }
1230
1231/*!
1232 * @}
1233 */ /* end of group DAC_Peripheral_Access_Layer */
1234
1235/* ----------------------------------------------------------------------------
1236 -- DMA Peripheral Access Layer
1237 ---------------------------------------------------------------------------- */
1238
1239/*!
1240 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1241 * @{
1242 */
1243
1244/** DMA - Register Layout Typedef */
1245typedef struct
1246{
1247 uint8_t RESERVED_0[256];
1248 struct
1249 { /* offset: 0x100, array step: 0x10 */
1250 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
1251 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
1252 union
1253 { /* offset: 0x108, array step: 0x10 */
1254 struct
1255 { /* offset: 0x108, array step: 0x10 */
1256 uint8_t RESERVED_0[3];
1257 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
1258 } DMA_DSR_ACCESS8BIT;
1259 __IO uint32_t
1260 DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
1261 };
1262 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
1263 } DMA[4];
1264} DMA_Type;
1265
1266/* ----------------------------------------------------------------------------
1267 -- DMA Register Masks
1268 ---------------------------------------------------------------------------- */
1269
1270/*!
1271 * @addtogroup DMA_Register_Masks DMA Register Masks
1272 * @{
1273 */
1274
1275/*! @name SAR - Source Address Register */
1276/*! @{ */
1277#define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
1278#define DMA_SAR_SAR_SHIFT (0U)
1279/*! SAR - SAR
1280 */
1281#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
1282/*! @} */
1283
1284/* The count of DMA_SAR */
1285#define DMA_SAR_COUNT (4U)
1286
1287/*! @name DAR - Destination Address Register */
1288/*! @{ */
1289#define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
1290#define DMA_DAR_DAR_SHIFT (0U)
1291/*! DAR - DAR
1292 */
1293#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
1294/*! @} */
1295
1296/* The count of DMA_DAR */
1297#define DMA_DAR_COUNT (4U)
1298
1299/* The count of DMA_DSR */
1300#define DMA_DSR_COUNT (4U)
1301
1302/*! @name DSR_BCR - DMA Status Register / Byte Count Register */
1303/*! @{ */
1304#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
1305#define DMA_DSR_BCR_BCR_SHIFT (0U)
1306/*! BCR - BCR
1307 */
1308#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
1309#define DMA_DSR_BCR_DONE_MASK (0x1000000U)
1310#define DMA_DSR_BCR_DONE_SHIFT (24U)
1311/*! DONE - Transactions Done
1312 * 0b0..DMA transfer is not yet complete. Writing a 0 has no effect.
1313 * 0b1..DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an
1314 * interrupt service routine to clear the DMA interrupt and error bits.
1315 */
1316#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
1317#define DMA_DSR_BCR_BSY_MASK (0x2000000U)
1318#define DMA_DSR_BCR_BSY_SHIFT (25U)
1319/*! BSY - Busy
1320 * 0b0..DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1321 * 0b1..BSY is set the first time the channel is enabled after a transfer is initiated.
1322 */
1323#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
1324#define DMA_DSR_BCR_REQ_MASK (0x4000000U)
1325#define DMA_DSR_BCR_REQ_SHIFT (26U)
1326/*! REQ - Request
1327 * 0b0..No request is pending or the channel is currently active. Cleared when the channel is selected.
1328 * 0b1..The DMA channel has a transfer remaining and the channel is not selected.
1329 */
1330#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
1331#define DMA_DSR_BCR_BED_MASK (0x10000000U)
1332#define DMA_DSR_BCR_BED_SHIFT (28U)
1333/*! BED - Bus Error on Destination
1334 * 0b0..No bus error occurred.
1335 * 0b1..The DMA channel terminated with a bus error during the write portion of a transfer.
1336 */
1337#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
1338#define DMA_DSR_BCR_BES_MASK (0x20000000U)
1339#define DMA_DSR_BCR_BES_SHIFT (29U)
1340/*! BES - Bus Error on Source
1341 * 0b0..No bus error occurred.
1342 * 0b1..The DMA channel terminated with a bus error during the read portion of a transfer.
1343 */
1344#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
1345#define DMA_DSR_BCR_CE_MASK (0x40000000U)
1346#define DMA_DSR_BCR_CE_SHIFT (30U)
1347/*! CE - Configuration Error
1348 * 0b0..No configuration error exists.
1349 * 0b1..A configuration error has occurred.
1350 */
1351#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
1352/*! @} */
1353
1354/* The count of DMA_DSR_BCR */
1355#define DMA_DSR_BCR_COUNT (4U)
1356
1357/*! @name DCR - DMA Control Register */
1358/*! @{ */
1359#define DMA_DCR_LCH2_MASK (0x3U)
1360#define DMA_DCR_LCH2_SHIFT (0U)
1361/*! LCH2 - Link Channel 2
1362 * 0b00..DMA Channel 0
1363 * 0b01..DMA Channel 1
1364 * 0b10..DMA Channel 2
1365 * 0b11..DMA Channel 3
1366 */
1367#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
1368#define DMA_DCR_LCH1_MASK (0xCU)
1369#define DMA_DCR_LCH1_SHIFT (2U)
1370/*! LCH1 - Link Channel 1
1371 * 0b00..DMA Channel 0
1372 * 0b01..DMA Channel 1
1373 * 0b10..DMA Channel 2
1374 * 0b11..DMA Channel 3
1375 */
1376#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
1377#define DMA_DCR_LINKCC_MASK (0x30U)
1378#define DMA_DCR_LINKCC_SHIFT (4U)
1379/*! LINKCC - Link Channel Control
1380 * 0b00..No channel-to-channel linking
1381 * 0b01..Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR
1382 * decrements to 0. 0b10..Perform a link to channel LCH1 after each cycle-steal transfer 0b11..Perform a link to channel
1383 * LCH1 after the BCR decrements to 0.
1384 */
1385#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
1386#define DMA_DCR_D_REQ_MASK (0x80U)
1387#define DMA_DCR_D_REQ_SHIFT (7U)
1388/*! D_REQ - Disable Request
1389 * 0b0..ERQ bit is not affected.
1390 * 0b1..ERQ bit is cleared when the BCR is exhausted.
1391 */
1392#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
1393#define DMA_DCR_DMOD_MASK (0xF00U)
1394#define DMA_DCR_DMOD_SHIFT (8U)
1395/*! DMOD - Destination Address Modulo
1396 * 0b0000..Buffer disabled
1397 * 0b0001..Circular buffer size is 16 bytes
1398 * 0b0010..Circular buffer size is 32 bytes
1399 * 0b0011..Circular buffer size is 64 bytes
1400 * 0b0100..Circular buffer size is 128 bytes
1401 * 0b0101..Circular buffer size is 256 bytes
1402 * 0b0110..Circular buffer size is 512 bytes
1403 * 0b0111..Circular buffer size is 1 KB
1404 * 0b1000..Circular buffer size is 2 KB
1405 * 0b1001..Circular buffer size is 4 KB
1406 * 0b1010..Circular buffer size is 8 KB
1407 * 0b1011..Circular buffer size is 16 KB
1408 * 0b1100..Circular buffer size is 32 KB
1409 * 0b1101..Circular buffer size is 64 KB
1410 * 0b1110..Circular buffer size is 128 KB
1411 * 0b1111..Circular buffer size is 256 KB
1412 */
1413#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
1414#define DMA_DCR_SMOD_MASK (0xF000U)
1415#define DMA_DCR_SMOD_SHIFT (12U)
1416/*! SMOD - Source Address Modulo
1417 * 0b0000..Buffer disabled
1418 * 0b0001..Circular buffer size is 16 bytes.
1419 * 0b0010..Circular buffer size is 32 bytes.
1420 * 0b0011..Circular buffer size is 64 bytes.
1421 * 0b0100..Circular buffer size is 128 bytes.
1422 * 0b0101..Circular buffer size is 256 bytes.
1423 * 0b0110..Circular buffer size is 512 bytes.
1424 * 0b0111..Circular buffer size is 1 KB.
1425 * 0b1000..Circular buffer size is 2 KB.
1426 * 0b1001..Circular buffer size is 4 KB.
1427 * 0b1010..Circular buffer size is 8 KB.
1428 * 0b1011..Circular buffer size is 16 KB.
1429 * 0b1100..Circular buffer size is 32 KB.
1430 * 0b1101..Circular buffer size is 64 KB.
1431 * 0b1110..Circular buffer size is 128 KB.
1432 * 0b1111..Circular buffer size is 256 KB.
1433 */
1434#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
1435#define DMA_DCR_START_MASK (0x10000U)
1436#define DMA_DCR_START_SHIFT (16U)
1437/*! START - Start Transfer
1438 * 0b0..DMA inactive
1439 * 0b1..The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after
1440 * one module clock and always reads as logic 0.
1441 */
1442#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
1443#define DMA_DCR_DSIZE_MASK (0x60000U)
1444#define DMA_DCR_DSIZE_SHIFT (17U)
1445/*! DSIZE - Destination Size
1446 * 0b00..32-bit
1447 * 0b01..8-bit
1448 * 0b10..16-bit
1449 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
1450 */
1451#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
1452#define DMA_DCR_DINC_MASK (0x80000U)
1453#define DMA_DCR_DINC_SHIFT (19U)
1454/*! DINC - Destination Increment
1455 * 0b0..No change to the DAR after a successful transfer.
1456 * 0b1..The DAR increments by 1, 2, 4 depending upon the size of the transfer.
1457 */
1458#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
1459#define DMA_DCR_SSIZE_MASK (0x300000U)
1460#define DMA_DCR_SSIZE_SHIFT (20U)
1461/*! SSIZE - Source Size
1462 * 0b00..32-bit
1463 * 0b01..8-bit
1464 * 0b10..16-bit
1465 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
1466 */
1467#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
1468#define DMA_DCR_SINC_MASK (0x400000U)
1469#define DMA_DCR_SINC_SHIFT (22U)
1470/*! SINC - Source Increment
1471 * 0b0..No change to SAR after a successful transfer.
1472 * 0b1..The SAR increments by 1, 2, 4 as determined by the transfer size.
1473 */
1474#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
1475#define DMA_DCR_EADREQ_MASK (0x800000U)
1476#define DMA_DCR_EADREQ_SHIFT (23U)
1477/*! EADREQ - Enable asynchronous DMA requests
1478 * 0b0..Disabled
1479 * 0b1..Enabled
1480 */
1481#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
1482#define DMA_DCR_AA_MASK (0x10000000U)
1483#define DMA_DCR_AA_SHIFT (28U)
1484/*! AA - Auto-align
1485 * 0b0..Auto-align disabled
1486 * 0b1..If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise,
1487 * destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If
1488 * auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
1489 */
1490#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
1491#define DMA_DCR_CS_MASK (0x20000000U)
1492#define DMA_DCR_CS_SHIFT (29U)
1493/*! CS - Cycle Steal
1494 * 0b0..DMA continuously makes read/write transfers until the BCR decrements to 0.
1495 * 0b1..Forces a single read/write transfer per request.
1496 */
1497#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
1498#define DMA_DCR_ERQ_MASK (0x40000000U)
1499#define DMA_DCR_ERQ_SHIFT (30U)
1500/*! ERQ - Enable Peripheral Request
1501 * 0b0..Peripheral request is ignored.
1502 * 0b1..Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always
1503 * enabled.
1504 */
1505#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
1506#define DMA_DCR_EINT_MASK (0x80000000U)
1507#define DMA_DCR_EINT_SHIFT (31U)
1508/*! EINT - Enable Interrupt on Completion of Transfer
1509 * 0b0..No interrupt is generated.
1510 * 0b1..Interrupt signal is enabled.
1511 */
1512#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
1513/*! @} */
1514
1515/* The count of DMA_DCR */
1516#define DMA_DCR_COUNT (4U)
1517
1518/*!
1519 * @}
1520 */ /* end of group DMA_Register_Masks */
1521
1522/* DMA - Peripheral instance base addresses */
1523/** Peripheral DMA base address */
1524#define DMA_BASE (0x40008000u)
1525/** Peripheral DMA base pointer */
1526#define DMA0 ((DMA_Type *)DMA_BASE)
1527/** Array initializer of DMA peripheral base addresses */
1528#define DMA_BASE_ADDRS \
1529 { \
1530 DMA_BASE \
1531 }
1532/** Array initializer of DMA peripheral base pointers */
1533#define DMA_BASE_PTRS \
1534 { \
1535 DMA0 \
1536 }
1537/** Interrupt vectors for the DMA peripheral type */
1538#define DMA_CHN_IRQS \
1539 { \
1540 { \
1541 DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn \
1542 } \
1543 }
1544
1545/*!
1546 * @}
1547 */ /* end of group DMA_Peripheral_Access_Layer */
1548
1549/* ----------------------------------------------------------------------------
1550 -- DMAMUX Peripheral Access Layer
1551 ---------------------------------------------------------------------------- */
1552
1553/*!
1554 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1555 * @{
1556 */
1557
1558/** DMAMUX - Register Layout Typedef */
1559typedef struct
1560{
1561 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
1562} DMAMUX_Type;
1563
1564/* ----------------------------------------------------------------------------
1565 -- DMAMUX Register Masks
1566 ---------------------------------------------------------------------------- */
1567
1568/*!
1569 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1570 * @{
1571 */
1572
1573/*! @name CHCFG - Channel Configuration register */
1574/*! @{ */
1575#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
1576#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
1577/*! SOURCE - DMA Channel Source (Slot)
1578 * 0b000000..Disable_Signal
1579 * 0b000010..LPUART0_Rx_Signal
1580 * 0b000011..LPUART0_Tx_Signal
1581 * 0b000100..LPUART1_Rx_Signal
1582 * 0b000101..LPUART1_Tx_Signal
1583 * 0b000110..UART2_Rx_Signal
1584 * 0b000111..UART2_Tx_Signal
1585 * 0b001010..FlexIO_Channel0_Signal
1586 * 0b001011..FlexIO_Channel1_Signal
1587 * 0b001100..FlexIO_Channel2_Signal
1588 * 0b001101..FlexIO_Channel3_Signal
1589 * 0b010000..SPI0_Rx_Signal
1590 * 0b010001..SPI0_Tx_Signal
1591 * 0b010010..SPI1_Rx_Signal
1592 * 0b010011..SPI1_Tx_Signal
1593 * 0b010110..I2C0_Signal
1594 * 0b010111..I2C1_Signal
1595 * 0b011000..TPM0_Channel0_Signal
1596 * 0b011001..TPM0_Channel1_Signal
1597 * 0b011010..TPM0_Channel2_Signal
1598 * 0b011011..TPM0_Channel3_Signal
1599 * 0b011100..TPM0_Channel4_Signal
1600 * 0b011101..TPM0_Channel5_Signal
1601 * 0b100000..TPM1_Channel0_Signal
1602 * 0b100001..TPM1_Channel1_Signal
1603 * 0b100010..TPM2_Channel0_Signal
1604 * 0b100011..TPM2_Channel1_Signal
1605 * 0b101000..ADC0_Signal
1606 * 0b101010..CMP0_Signal
1607 * 0b101101..DAC0_Signal
1608 * 0b110001..Port_A_Signal
1609 * 0b110011..Port_C_Signal
1610 * 0b110100..Port_D_Signal
1611 * 0b110110..TPM0_Overflow_Signal
1612 * 0b110111..TPM1_Overflow_Signal
1613 * 0b111000..TPM2_Overflow_Signal
1614 * 0b111100..AlwaysOn60_Signal
1615 * 0b111101..AlwaysOn61_Signal
1616 * 0b111110..AlwaysOn62_Signal
1617 * 0b111111..AlwaysOn63_Signal
1618 */
1619#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
1620#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
1621#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
1622/*! TRIG - DMA Channel Trigger Enable
1623 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
1624 * specified source to the DMA channel. (Normal mode)
1625 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
1626 */
1627#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
1628#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
1629#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
1630/*! ENBL - DMA Channel Enable
1631 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has
1632 * separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
1633 * 0b1..DMA channel is enabled
1634 */
1635#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
1636/*! @} */
1637
1638/* The count of DMAMUX_CHCFG */
1639#define DMAMUX_CHCFG_COUNT (4U)
1640
1641/*!
1642 * @}
1643 */ /* end of group DMAMUX_Register_Masks */
1644
1645/* DMAMUX - Peripheral instance base addresses */
1646/** Peripheral DMAMUX0 base address */
1647#define DMAMUX0_BASE (0x40021000u)
1648/** Peripheral DMAMUX0 base pointer */
1649#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
1650/** Array initializer of DMAMUX peripheral base addresses */
1651#define DMAMUX_BASE_ADDRS \
1652 { \
1653 DMAMUX0_BASE \
1654 }
1655/** Array initializer of DMAMUX peripheral base pointers */
1656#define DMAMUX_BASE_PTRS \
1657 { \
1658 DMAMUX0 \
1659 }
1660
1661/*!
1662 * @}
1663 */ /* end of group DMAMUX_Peripheral_Access_Layer */
1664
1665/* ----------------------------------------------------------------------------
1666 -- FGPIO Peripheral Access Layer
1667 ---------------------------------------------------------------------------- */
1668
1669/*!
1670 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
1671 * @{
1672 */
1673
1674/** FGPIO - Register Layout Typedef */
1675typedef struct
1676{
1677 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1678 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1679 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1680 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1681 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1682 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1683} FGPIO_Type;
1684
1685/* ----------------------------------------------------------------------------
1686 -- FGPIO Register Masks
1687 ---------------------------------------------------------------------------- */
1688
1689/*!
1690 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
1691 * @{
1692 */
1693
1694/*! @name PDOR - Port Data Output Register */
1695/*! @{ */
1696#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
1697#define FGPIO_PDOR_PDO_SHIFT (0U)
1698/*! PDO - Port Data Output
1699 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose
1700 * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for
1701 * general-purpose output.
1702 */
1703#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
1704/*! @} */
1705
1706/*! @name PSOR - Port Set Output Register */
1707/*! @{ */
1708#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
1709#define FGPIO_PSOR_PTSO_SHIFT (0U)
1710/*! PTSO - Port Set Output
1711 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
1712 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
1713 */
1714#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
1715/*! @} */
1716
1717/*! @name PCOR - Port Clear Output Register */
1718/*! @{ */
1719#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
1720#define FGPIO_PCOR_PTCO_SHIFT (0U)
1721/*! PTCO - Port Clear Output
1722 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
1723 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
1724 */
1725#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
1726/*! @} */
1727
1728/*! @name PTOR - Port Toggle Output Register */
1729/*! @{ */
1730#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
1731#define FGPIO_PTOR_PTTO_SHIFT (0U)
1732/*! PTTO - Port Toggle Output
1733 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
1734 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
1735 */
1736#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
1737/*! @} */
1738
1739/*! @name PDIR - Port Data Input Register */
1740/*! @{ */
1741#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
1742#define FGPIO_PDIR_PDI_SHIFT (0U)
1743/*! PDI - Port Data Input
1744 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
1745 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
1746 */
1747#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
1748/*! @} */
1749
1750/*! @name PDDR - Port Data Direction Register */
1751/*! @{ */
1752#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
1753#define FGPIO_PDDR_PDD_SHIFT (0U)
1754/*! PDD - Port Data Direction
1755 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
1756 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
1757 */
1758#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
1759/*! @} */
1760
1761/*!
1762 * @}
1763 */ /* end of group FGPIO_Register_Masks */
1764
1765/* FGPIO - Peripheral instance base addresses */
1766/** Peripheral FGPIOA base address */
1767#define FGPIOA_BASE (0xF8000000u)
1768/** Peripheral FGPIOA base pointer */
1769#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
1770/** Peripheral FGPIOB base address */
1771#define FGPIOB_BASE (0xF8000040u)
1772/** Peripheral FGPIOB base pointer */
1773#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
1774/** Peripheral FGPIOC base address */
1775#define FGPIOC_BASE (0xF8000080u)
1776/** Peripheral FGPIOC base pointer */
1777#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
1778/** Peripheral FGPIOD base address */
1779#define FGPIOD_BASE (0xF80000C0u)
1780/** Peripheral FGPIOD base pointer */
1781#define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
1782/** Peripheral FGPIOE base address */
1783#define FGPIOE_BASE (0xF8000100u)
1784/** Peripheral FGPIOE base pointer */
1785#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
1786/** Array initializer of FGPIO peripheral base addresses */
1787#define FGPIO_BASE_ADDRS \
1788 { \
1789 FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE \
1790 }
1791/** Array initializer of FGPIO peripheral base pointers */
1792#define FGPIO_BASE_PTRS \
1793 { \
1794 FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE \
1795 }
1796
1797/*!
1798 * @}
1799 */ /* end of group FGPIO_Peripheral_Access_Layer */
1800
1801/* ----------------------------------------------------------------------------
1802 -- FLEXIO Peripheral Access Layer
1803 ---------------------------------------------------------------------------- */
1804
1805/*!
1806 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
1807 * @{
1808 */
1809
1810/** FLEXIO - Register Layout Typedef */
1811typedef struct
1812{
1813 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
1814 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
1815 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
1816 uint8_t RESERVED_0[4];
1817 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
1818 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
1819 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
1820 uint8_t RESERVED_1[4];
1821 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
1822 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
1823 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
1824 uint8_t RESERVED_2[4];
1825 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
1826 uint8_t RESERVED_3[76];
1827 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
1828 uint8_t RESERVED_4[112];
1829 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
1830 uint8_t RESERVED_5[240];
1831 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
1832 uint8_t RESERVED_6[112];
1833 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
1834 uint8_t RESERVED_7[112];
1835 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
1836 uint8_t RESERVED_8[112];
1837 __IO uint32_t
1838 SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
1839 uint8_t RESERVED_9[112];
1840 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
1841 uint8_t RESERVED_10[112];
1842 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
1843 uint8_t RESERVED_11[112];
1844 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
1845} FLEXIO_Type;
1846
1847/* ----------------------------------------------------------------------------
1848 -- FLEXIO Register Masks
1849 ---------------------------------------------------------------------------- */
1850
1851/*!
1852 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
1853 * @{
1854 */
1855
1856/*! @name VERID - Version ID Register */
1857/*! @{ */
1858#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
1859#define FLEXIO_VERID_FEATURE_SHIFT (0U)
1860/*! FEATURE - Feature Specification Number
1861 * 0b0000000000000000..Standard features implemented.
1862 * 0b0000000000000001..Supports state, logic and parallel modes.
1863 */
1864#define FLEXIO_VERID_FEATURE(x) \
1865 (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
1866#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
1867#define FLEXIO_VERID_MINOR_SHIFT (16U)
1868/*! MINOR - Minor Version Number
1869 */
1870#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
1871#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
1872#define FLEXIO_VERID_MAJOR_SHIFT (24U)
1873/*! MAJOR - Major Version Number
1874 */
1875#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
1876/*! @} */
1877
1878/*! @name PARAM - Parameter Register */
1879/*! @{ */
1880#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
1881#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
1882/*! SHIFTER - Shifter Number
1883 */
1884#define FLEXIO_PARAM_SHIFTER(x) \
1885 (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
1886#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
1887#define FLEXIO_PARAM_TIMER_SHIFT (8U)
1888/*! TIMER - Timer Number
1889 */
1890#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
1891#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
1892#define FLEXIO_PARAM_PIN_SHIFT (16U)
1893/*! PIN - Pin Number
1894 */
1895#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
1896#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
1897#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
1898/*! TRIGGER - Trigger Number
1899 */
1900#define FLEXIO_PARAM_TRIGGER(x) \
1901 (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
1902/*! @} */
1903
1904/*! @name CTRL - FlexIO Control Register */
1905/*! @{ */
1906#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
1907#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
1908/*! FLEXEN - FlexIO Enable
1909 * 0b0..FlexIO module is disabled.
1910 * 0b1..FlexIO module is enabled.
1911 */
1912#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
1913#define FLEXIO_CTRL_SWRST_MASK (0x2U)
1914#define FLEXIO_CTRL_SWRST_SHIFT (1U)
1915/*! SWRST - Software Reset
1916 * 0b0..Software reset is disabled
1917 * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
1918 */
1919#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
1920#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
1921#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
1922/*! FASTACC - Fast Access
1923 * 0b0..Configures for normal register accesses to FlexIO
1924 * 0b1..Configures for fast register accesses to FlexIO
1925 */
1926#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
1927#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
1928#define FLEXIO_CTRL_DBGE_SHIFT (30U)
1929/*! DBGE - Debug Enable
1930 * 0b0..FlexIO is disabled in debug modes.
1931 * 0b1..FlexIO is enabled in debug modes
1932 */
1933#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
1934#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
1935#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
1936/*! DOZEN - Doze Enable
1937 * 0b0..FlexIO enabled in Doze modes.
1938 * 0b1..FlexIO disabled in Doze modes.
1939 */
1940#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
1941/*! @} */
1942
1943/*! @name SHIFTSTAT - Shifter Status Register */
1944/*! @{ */
1945#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
1946#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
1947/*! SSF - Shifter Status Flag
1948 * 0b0000..Status flag is clear
1949 * 0b0001..Status flag is set
1950 */
1951#define FLEXIO_SHIFTSTAT_SSF(x) \
1952 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
1953/*! @} */
1954
1955/*! @name SHIFTERR - Shifter Error Register */
1956/*! @{ */
1957#define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
1958#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
1959/*! SEF - Shifter Error Flags
1960 * 0b0000..Shifter Error Flag is clear
1961 * 0b0001..Shifter Error Flag is set
1962 */
1963#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
1964/*! @} */
1965
1966/*! @name TIMSTAT - Timer Status Register */
1967/*! @{ */
1968#define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
1969#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
1970/*! TSF - Timer Status Flags
1971 * 0b0000..Timer Status Flag is clear
1972 * 0b0001..Timer Status Flag is set
1973 */
1974#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
1975/*! @} */
1976
1977/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
1978/*! @{ */
1979#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
1980#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
1981/*! SSIE - Shifter Status Interrupt Enable
1982 * 0b0000..Shifter Status Flag interrupt disabled
1983 * 0b0001..Shifter Status Flag interrupt enabled
1984 */
1985#define FLEXIO_SHIFTSIEN_SSIE(x) \
1986 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
1987/*! @} */
1988
1989/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
1990/*! @{ */
1991#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
1992#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
1993/*! SEIE - Shifter Error Interrupt Enable
1994 * 0b0000..Shifter Error Flag interrupt disabled
1995 * 0b0001..Shifter Error Flag interrupt enabled
1996 */
1997#define FLEXIO_SHIFTEIEN_SEIE(x) \
1998 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
1999/*! @} */
2000
2001/*! @name TIMIEN - Timer Interrupt Enable Register */
2002/*! @{ */
2003#define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
2004#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
2005/*! TEIE - Timer Status Interrupt Enable
2006 * 0b0000..Timer Status Flag interrupt is disabled
2007 * 0b0001..Timer Status Flag interrupt is enabled
2008 */
2009#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
2010/*! @} */
2011
2012/*! @name SHIFTSDEN - Shifter Status DMA Enable */
2013/*! @{ */
2014#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
2015#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
2016/*! SSDE - Shifter Status DMA Enable
2017 * 0b0000..Shifter Status Flag DMA request is disabled
2018 * 0b0001..Shifter Status Flag DMA request is enabled
2019 */
2020#define FLEXIO_SHIFTSDEN_SSDE(x) \
2021 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
2022/*! @} */
2023
2024/*! @name SHIFTCTL - Shifter Control N Register */
2025/*! @{ */
2026#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
2027#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
2028/*! SMOD - Shifter Mode
2029 * 0b000..Disabled.
2030 * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
2031 * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
2032 * 0b011..Reserved.
2033 * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
2034 * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
2035 * 0b110..Reserved.
2036 * 0b111..Reserved.
2037 */
2038#define FLEXIO_SHIFTCTL_SMOD(x) \
2039 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
2040#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
2041#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
2042/*! PINPOL - Shifter Pin Polarity
2043 * 0b0..Pin is active high
2044 * 0b1..Pin is active low
2045 */
2046#define FLEXIO_SHIFTCTL_PINPOL(x) \
2047 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
2048#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U)
2049#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
2050/*! PINSEL - Shifter Pin Select
2051 */
2052#define FLEXIO_SHIFTCTL_PINSEL(x) \
2053 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
2054#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
2055#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
2056/*! PINCFG - Shifter Pin Configuration
2057 * 0b00..Shifter pin output disabled
2058 * 0b01..Shifter pin open drain or bidirectional output enable
2059 * 0b10..Shifter pin bidirectional output data
2060 * 0b11..Shifter pin output
2061 */
2062#define FLEXIO_SHIFTCTL_PINCFG(x) \
2063 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
2064#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
2065#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
2066/*! TIMPOL - Timer Polarity
2067 * 0b0..Shift on posedge of Shift clock
2068 * 0b1..Shift on negedge of Shift clock
2069 */
2070#define FLEXIO_SHIFTCTL_TIMPOL(x) \
2071 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
2072#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
2073#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
2074/*! TIMSEL - Timer Select
2075 */
2076#define FLEXIO_SHIFTCTL_TIMSEL(x) \
2077 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
2078/*! @} */
2079
2080/* The count of FLEXIO_SHIFTCTL */
2081#define FLEXIO_SHIFTCTL_COUNT (4U)
2082
2083/*! @name SHIFTCFG - Shifter Configuration N Register */
2084/*! @{ */
2085#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
2086#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
2087/*! SSTART - Shifter Start bit
2088 * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
2089 * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
2090 * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag
2091 * if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match
2092 * store sets error flag if start bit is not 1
2093 */
2094#define FLEXIO_SHIFTCFG_SSTART(x) \
2095 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
2096#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
2097#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
2098/*! SSTOP - Shifter Stop bit
2099 * 0b00..Stop bit disabled for transmitter/receiver/match store
2100 * 0b01..Reserved for transmitter/receiver/match store
2101 * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
2102 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
2103 */
2104#define FLEXIO_SHIFTCFG_SSTOP(x) \
2105 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
2106#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
2107#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
2108/*! INSRC - Input Source
2109 * 0b0..Pin
2110 * 0b1..Shifter N+1 Output
2111 */
2112#define FLEXIO_SHIFTCFG_INSRC(x) \
2113 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
2114/*! @} */
2115
2116/* The count of FLEXIO_SHIFTCFG */
2117#define FLEXIO_SHIFTCFG_COUNT (4U)
2118
2119/*! @name SHIFTBUF - Shifter Buffer N Register */
2120/*! @{ */
2121#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
2122#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
2123/*! SHIFTBUF - Shift Buffer
2124 */
2125#define FLEXIO_SHIFTBUF_SHIFTBUF(x) \
2126 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
2127/*! @} */
2128
2129/* The count of FLEXIO_SHIFTBUF */
2130#define FLEXIO_SHIFTBUF_COUNT (4U)
2131
2132/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
2133/*! @{ */
2134#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
2135#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
2136/*! SHIFTBUFBIS - Shift Buffer
2137 */
2138#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) \
2139 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
2140/*! @} */
2141
2142/* The count of FLEXIO_SHIFTBUFBIS */
2143#define FLEXIO_SHIFTBUFBIS_COUNT (4U)
2144
2145/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
2146/*! @{ */
2147#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
2148#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
2149/*! SHIFTBUFBYS - Shift Buffer
2150 */
2151#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) \
2152 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
2153/*! @} */
2154
2155/* The count of FLEXIO_SHIFTBUFBYS */
2156#define FLEXIO_SHIFTBUFBYS_COUNT (4U)
2157
2158/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
2159/*! @{ */
2160#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
2161#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
2162/*! SHIFTBUFBBS - Shift Buffer
2163 */
2164#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) \
2165 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
2166/*! @} */
2167
2168/* The count of FLEXIO_SHIFTBUFBBS */
2169#define FLEXIO_SHIFTBUFBBS_COUNT (4U)
2170
2171/*! @name TIMCTL - Timer Control N Register */
2172/*! @{ */
2173#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
2174#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
2175/*! TIMOD - Timer Mode
2176 * 0b00..Timer Disabled.
2177 * 0b01..Dual 8-bit counters baud/bit mode.
2178 * 0b10..Dual 8-bit counters PWM mode.
2179 * 0b11..Single 16-bit counter mode.
2180 */
2181#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
2182#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
2183#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
2184/*! PINPOL - Timer Pin Polarity
2185 * 0b0..Pin is active high
2186 * 0b1..Pin is active low
2187 */
2188#define FLEXIO_TIMCTL_PINPOL(x) \
2189 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
2190#define FLEXIO_TIMCTL_PINSEL_MASK (0x700U)
2191#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
2192/*! PINSEL - Timer Pin Select
2193 */
2194#define FLEXIO_TIMCTL_PINSEL(x) \
2195 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
2196#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
2197#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
2198/*! PINCFG - Timer Pin Configuration
2199 * 0b00..Timer pin output disabled
2200 * 0b01..Timer pin open drain or bidirectional output enable
2201 * 0b10..Timer pin bidirectional output data
2202 * 0b11..Timer pin output
2203 */
2204#define FLEXIO_TIMCTL_PINCFG(x) \
2205 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
2206#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
2207#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
2208/*! TRGSRC - Trigger Source
2209 * 0b0..External trigger selected
2210 * 0b1..Internal trigger selected
2211 */
2212#define FLEXIO_TIMCTL_TRGSRC(x) \
2213 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
2214#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
2215#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
2216/*! TRGPOL - Trigger Polarity
2217 * 0b0..Trigger active high
2218 * 0b1..Trigger active low
2219 */
2220#define FLEXIO_TIMCTL_TRGPOL(x) \
2221 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
2222#define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U)
2223#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
2224/*! TRGSEL - Trigger Select
2225 */
2226#define FLEXIO_TIMCTL_TRGSEL(x) \
2227 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
2228/*! @} */
2229
2230/* The count of FLEXIO_TIMCTL */
2231#define FLEXIO_TIMCTL_COUNT (4U)
2232
2233/*! @name TIMCFG - Timer Configuration N Register */
2234/*! @{ */
2235#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
2236#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
2237/*! TSTART - Timer Start Bit
2238 * 0b0..Start bit disabled
2239 * 0b1..Start bit enabled
2240 */
2241#define FLEXIO_TIMCFG_TSTART(x) \
2242 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
2243#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
2244#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
2245/*! TSTOP - Timer Stop Bit
2246 * 0b00..Stop bit disabled
2247 * 0b01..Stop bit is enabled on timer compare
2248 * 0b10..Stop bit is enabled on timer disable
2249 * 0b11..Stop bit is enabled on timer compare and timer disable
2250 */
2251#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
2252#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
2253#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
2254/*! TIMENA - Timer Enable
2255 * 0b000..Timer always enabled
2256 * 0b001..Timer enabled on Timer N-1 enable
2257 * 0b010..Timer enabled on Trigger high
2258 * 0b011..Timer enabled on Trigger high and Pin high
2259 * 0b100..Timer enabled on Pin rising edge
2260 * 0b101..Timer enabled on Pin rising edge and Trigger high
2261 * 0b110..Timer enabled on Trigger rising edge
2262 * 0b111..Timer enabled on Trigger rising or falling edge
2263 */
2264#define FLEXIO_TIMCFG_TIMENA(x) \
2265 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
2266#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
2267#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
2268/*! TIMDIS - Timer Disable
2269 * 0b000..Timer never disabled
2270 * 0b001..Timer disabled on Timer N-1 disable
2271 * 0b010..Timer disabled on Timer compare
2272 * 0b011..Timer disabled on Timer compare and Trigger Low
2273 * 0b100..Timer disabled on Pin rising or falling edge
2274 * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
2275 * 0b110..Timer disabled on Trigger falling edge
2276 * 0b111..Reserved
2277 */
2278#define FLEXIO_TIMCFG_TIMDIS(x) \
2279 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
2280#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
2281#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
2282/*! TIMRST - Timer Reset
2283 * 0b000..Timer never reset
2284 * 0b001..Reserved
2285 * 0b010..Timer reset on Timer Pin equal to Timer Output
2286 * 0b011..Timer reset on Timer Trigger equal to Timer Output
2287 * 0b100..Timer reset on Timer Pin rising edge
2288 * 0b101..Reserved
2289 * 0b110..Timer reset on Trigger rising edge
2290 * 0b111..Timer reset on Trigger rising or falling edge
2291 */
2292#define FLEXIO_TIMCFG_TIMRST(x) \
2293 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
2294#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
2295#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
2296/*! TIMDEC - Timer Decrement
2297 * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
2298 * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
2299 * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
2300 * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
2301 */
2302#define FLEXIO_TIMCFG_TIMDEC(x) \
2303 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
2304#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
2305#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
2306/*! TIMOUT - Timer Output
2307 * 0b00..Timer output is logic one when enabled and is not affected by timer reset
2308 * 0b01..Timer output is logic zero when enabled and is not affected by timer reset
2309 * 0b10..Timer output is logic one when enabled and on timer reset
2310 * 0b11..Timer output is logic zero when enabled and on timer reset
2311 */
2312#define FLEXIO_TIMCFG_TIMOUT(x) \
2313 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
2314/*! @} */
2315
2316/* The count of FLEXIO_TIMCFG */
2317#define FLEXIO_TIMCFG_COUNT (4U)
2318
2319/*! @name TIMCMP - Timer Compare N Register */
2320/*! @{ */
2321#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
2322#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
2323/*! CMP - Timer Compare Value
2324 */
2325#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
2326/*! @} */
2327
2328/* The count of FLEXIO_TIMCMP */
2329#define FLEXIO_TIMCMP_COUNT (4U)
2330
2331/*!
2332 * @}
2333 */ /* end of group FLEXIO_Register_Masks */
2334
2335/* FLEXIO - Peripheral instance base addresses */
2336/** Peripheral FLEXIO base address */
2337#define FLEXIO_BASE (0x4005F000u)
2338/** Peripheral FLEXIO base pointer */
2339#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
2340/** Array initializer of FLEXIO peripheral base addresses */
2341#define FLEXIO_BASE_ADDRS \
2342 { \
2343 FLEXIO_BASE \
2344 }
2345/** Array initializer of FLEXIO peripheral base pointers */
2346#define FLEXIO_BASE_PTRS \
2347 { \
2348 FLEXIO \
2349 }
2350/** Interrupt vectors for the FLEXIO peripheral type */
2351#define FLEXIO_IRQS \
2352 { \
2353 UART2_FLEXIO_IRQn \
2354 }
2355
2356/*!
2357 * @}
2358 */ /* end of group FLEXIO_Peripheral_Access_Layer */
2359
2360/* ----------------------------------------------------------------------------
2361 -- FTFA Peripheral Access Layer
2362 ---------------------------------------------------------------------------- */
2363
2364/*!
2365 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
2366 * @{
2367 */
2368
2369/** FTFA - Register Layout Typedef */
2370typedef struct
2371{
2372 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
2373 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
2374 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
2375 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
2376 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
2377 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
2378 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
2379 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
2380 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
2381 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
2382 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
2383 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
2384 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
2385 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
2386 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
2387 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
2388 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
2389 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
2390 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
2391 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
2392} FTFA_Type;
2393
2394/* ----------------------------------------------------------------------------
2395 -- FTFA Register Masks
2396 ---------------------------------------------------------------------------- */
2397
2398/*!
2399 * @addtogroup FTFA_Register_Masks FTFA Register Masks
2400 * @{
2401 */
2402
2403/*! @name FSTAT - Flash Status Register */
2404/*! @{ */
2405#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
2406#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
2407/*! MGSTAT0 - Memory Controller Command Completion Status Flag
2408 */
2409#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
2410#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
2411#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
2412/*! FPVIOL - Flash Protection Violation Flag
2413 * 0b0..No protection violation detected
2414 * 0b1..Protection violation detected
2415 */
2416#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
2417#define FTFA_FSTAT_ACCERR_MASK (0x20U)
2418#define FTFA_FSTAT_ACCERR_SHIFT (5U)
2419/*! ACCERR - Flash Access Error Flag
2420 * 0b0..No access error detected
2421 * 0b1..Access error detected
2422 */
2423#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
2424#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
2425#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
2426/*! RDCOLERR - Flash Read Collision Error Flag
2427 * 0b0..No collision error detected
2428 * 0b1..Collision error detected
2429 */
2430#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
2431#define FTFA_FSTAT_CCIF_MASK (0x80U)
2432#define FTFA_FSTAT_CCIF_SHIFT (7U)
2433/*! CCIF - Command Complete Interrupt Flag
2434 * 0b0..Flash command in progress
2435 * 0b1..Flash command has completed
2436 */
2437#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
2438/*! @} */
2439
2440/*! @name FCNFG - Flash Configuration Register */
2441/*! @{ */
2442#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
2443#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
2444/*! ERSSUSP - Erase Suspend
2445 * 0b0..No suspend requested
2446 * 0b1..Suspend the current Erase Flash Sector command execution.
2447 */
2448#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
2449#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
2450#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
2451/*! ERSAREQ - Erase All Request
2452 * 0b0..No request or request complete
2453 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the
2454 * Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to
2455 * the unsecure state.
2456 */
2457#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
2458#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
2459#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
2460/*! RDCOLLIE - Read Collision Error Interrupt Enable
2461 * 0b0..Read collision error interrupt disabled
2462 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read
2463 * collision error is detected (see the description of FSTAT[RDCOLERR]).
2464 */
2465#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
2466#define FTFA_FCNFG_CCIE_MASK (0x80U)
2467#define FTFA_FCNFG_CCIE_SHIFT (7U)
2468/*! CCIE - Command Complete Interrupt Enable
2469 * 0b0..Command complete interrupt disabled
2470 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
2471 */
2472#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
2473/*! @} */
2474
2475/*! @name FSEC - Flash Security Register */
2476/*! @{ */
2477#define FTFA_FSEC_SEC_MASK (0x3U)
2478#define FTFA_FSEC_SEC_SHIFT (0U)
2479/*! SEC - Flash Security
2480 * 0b00..MCU security status is secure.
2481 * 0b01..MCU security status is secure.
2482 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
2483 * 0b11..MCU security status is secure.
2484 */
2485#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
2486#define FTFA_FSEC_FSLACC_MASK (0xCU)
2487#define FTFA_FSEC_FSLACC_SHIFT (2U)
2488/*! FSLACC - Factory Security Level Access Code
2489 * 0b00..NXP factory access granted
2490 * 0b01..NXP factory access denied
2491 * 0b10..NXP factory access denied
2492 * 0b11..NXP factory access granted
2493 */
2494#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
2495#define FTFA_FSEC_MEEN_MASK (0x30U)
2496#define FTFA_FSEC_MEEN_SHIFT (4U)
2497/*! MEEN - Mass Erase Enable
2498 * 0b00..Mass erase is enabled
2499 * 0b01..Mass erase is enabled
2500 * 0b10..Mass erase is disabled
2501 * 0b11..Mass erase is enabled
2502 */
2503#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
2504#define FTFA_FSEC_KEYEN_MASK (0xC0U)
2505#define FTFA_FSEC_KEYEN_SHIFT (6U)
2506/*! KEYEN - Backdoor Key Security Enable
2507 * 0b00..Backdoor key access disabled
2508 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
2509 * 0b10..Backdoor key access enabled
2510 * 0b11..Backdoor key access disabled
2511 */
2512#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
2513/*! @} */
2514
2515/*! @name FOPT - Flash Option Register */
2516/*! @{ */
2517#define FTFA_FOPT_OPT_MASK (0xFFU)
2518#define FTFA_FOPT_OPT_SHIFT (0U)
2519/*! OPT - Nonvolatile Option
2520 */
2521#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
2522/*! @} */
2523
2524/*! @name FCCOB3 - Flash Common Command Object Registers */
2525/*! @{ */
2526#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
2527#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
2528#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
2529/*! @} */
2530
2531/*! @name FCCOB2 - Flash Common Command Object Registers */
2532/*! @{ */
2533#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
2534#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
2535#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
2536/*! @} */
2537
2538/*! @name FCCOB1 - Flash Common Command Object Registers */
2539/*! @{ */
2540#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
2541#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
2542#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
2543/*! @} */
2544
2545/*! @name FCCOB0 - Flash Common Command Object Registers */
2546/*! @{ */
2547#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
2548#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
2549#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
2550/*! @} */
2551
2552/*! @name FCCOB7 - Flash Common Command Object Registers */
2553/*! @{ */
2554#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
2555#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
2556#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
2557/*! @} */
2558
2559/*! @name FCCOB6 - Flash Common Command Object Registers */
2560/*! @{ */
2561#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
2562#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
2563#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
2564/*! @} */
2565
2566/*! @name FCCOB5 - Flash Common Command Object Registers */
2567/*! @{ */
2568#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
2569#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
2570#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
2571/*! @} */
2572
2573/*! @name FCCOB4 - Flash Common Command Object Registers */
2574/*! @{ */
2575#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
2576#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
2577#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
2578/*! @} */
2579
2580/*! @name FCCOBB - Flash Common Command Object Registers */
2581/*! @{ */
2582#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
2583#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
2584#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
2585/*! @} */
2586
2587/*! @name FCCOBA - Flash Common Command Object Registers */
2588/*! @{ */
2589#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
2590#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
2591#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
2592/*! @} */
2593
2594/*! @name FCCOB9 - Flash Common Command Object Registers */
2595/*! @{ */
2596#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
2597#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
2598#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
2599/*! @} */
2600
2601/*! @name FCCOB8 - Flash Common Command Object Registers */
2602/*! @{ */
2603#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
2604#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
2605#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
2606/*! @} */
2607
2608/*! @name FPROT3 - Program Flash Protection Registers */
2609/*! @{ */
2610#define FTFA_FPROT3_PROT_MASK (0xFFU)
2611#define FTFA_FPROT3_PROT_SHIFT (0U)
2612/*! PROT - Program Flash Region Protect
2613 * 0b00000000..Program flash region is protected.
2614 * 0b00000001..Program flash region is not protected
2615 */
2616#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
2617/*! @} */
2618
2619/*! @name FPROT2 - Program Flash Protection Registers */
2620/*! @{ */
2621#define FTFA_FPROT2_PROT_MASK (0xFFU)
2622#define FTFA_FPROT2_PROT_SHIFT (0U)
2623/*! PROT - Program Flash Region Protect
2624 * 0b00000000..Program flash region is protected.
2625 * 0b00000001..Program flash region is not protected
2626 */
2627#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
2628/*! @} */
2629
2630/*! @name FPROT1 - Program Flash Protection Registers */
2631/*! @{ */
2632#define FTFA_FPROT1_PROT_MASK (0xFFU)
2633#define FTFA_FPROT1_PROT_SHIFT (0U)
2634/*! PROT - Program Flash Region Protect
2635 * 0b00000000..Program flash region is protected.
2636 * 0b00000001..Program flash region is not protected
2637 */
2638#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
2639/*! @} */
2640
2641/*! @name FPROT0 - Program Flash Protection Registers */
2642/*! @{ */
2643#define FTFA_FPROT0_PROT_MASK (0xFFU)
2644#define FTFA_FPROT0_PROT_SHIFT (0U)
2645/*! PROT - Program Flash Region Protect
2646 * 0b00000000..Program flash region is protected.
2647 * 0b00000001..Program flash region is not protected
2648 */
2649#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
2650/*! @} */
2651
2652/*!
2653 * @}
2654 */ /* end of group FTFA_Register_Masks */
2655
2656/* FTFA - Peripheral instance base addresses */
2657/** Peripheral FTFA base address */
2658#define FTFA_BASE (0x40020000u)
2659/** Peripheral FTFA base pointer */
2660#define FTFA ((FTFA_Type *)FTFA_BASE)
2661/** Array initializer of FTFA peripheral base addresses */
2662#define FTFA_BASE_ADDRS \
2663 { \
2664 FTFA_BASE \
2665 }
2666/** Array initializer of FTFA peripheral base pointers */
2667#define FTFA_BASE_PTRS \
2668 { \
2669 FTFA \
2670 }
2671/** Interrupt vectors for the FTFA peripheral type */
2672#define FTFA_COMMAND_COMPLETE_IRQS \
2673 { \
2674 FTFA_IRQn \
2675 }
2676
2677/*!
2678 * @}
2679 */ /* end of group FTFA_Peripheral_Access_Layer */
2680
2681/* ----------------------------------------------------------------------------
2682 -- GPIO Peripheral Access Layer
2683 ---------------------------------------------------------------------------- */
2684
2685/*!
2686 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
2687 * @{
2688 */
2689
2690/** GPIO - Register Layout Typedef */
2691typedef struct
2692{
2693 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
2694 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
2695 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
2696 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
2697 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
2698 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
2699} GPIO_Type;
2700
2701/* ----------------------------------------------------------------------------
2702 -- GPIO Register Masks
2703 ---------------------------------------------------------------------------- */
2704
2705/*!
2706 * @addtogroup GPIO_Register_Masks GPIO Register Masks
2707 * @{
2708 */
2709
2710/*! @name PDOR - Port Data Output Register */
2711/*! @{ */
2712#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
2713#define GPIO_PDOR_PDO_SHIFT (0U)
2714/*! PDO - Port Data Output
2715 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose
2716 * output. 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for
2717 * general-purpose output.
2718 */
2719#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
2720/*! @} */
2721
2722/*! @name PSOR - Port Set Output Register */
2723/*! @{ */
2724#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
2725#define GPIO_PSOR_PTSO_SHIFT (0U)
2726/*! PTSO - Port Set Output
2727 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
2728 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
2729 */
2730#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
2731/*! @} */
2732
2733/*! @name PCOR - Port Clear Output Register */
2734/*! @{ */
2735#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
2736#define GPIO_PCOR_PTCO_SHIFT (0U)
2737/*! PTCO - Port Clear Output
2738 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
2739 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
2740 */
2741#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
2742/*! @} */
2743
2744/*! @name PTOR - Port Toggle Output Register */
2745/*! @{ */
2746#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
2747#define GPIO_PTOR_PTTO_SHIFT (0U)
2748/*! PTTO - Port Toggle Output
2749 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
2750 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
2751 */
2752#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
2753/*! @} */
2754
2755/*! @name PDIR - Port Data Input Register */
2756/*! @{ */
2757#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
2758#define GPIO_PDIR_PDI_SHIFT (0U)
2759/*! PDI - Port Data Input
2760 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
2761 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
2762 */
2763#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
2764/*! @} */
2765
2766/*! @name PDDR - Port Data Direction Register */
2767/*! @{ */
2768#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
2769#define GPIO_PDDR_PDD_SHIFT (0U)
2770/*! PDD - Port Data Direction
2771 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
2772 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
2773 */
2774#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
2775/*! @} */
2776
2777/*!
2778 * @}
2779 */ /* end of group GPIO_Register_Masks */
2780
2781/* GPIO - Peripheral instance base addresses */
2782/** Peripheral GPIOA base address */
2783#define GPIOA_BASE (0x400FF000u)
2784/** Peripheral GPIOA base pointer */
2785#define GPIOA ((GPIO_Type *)GPIOA_BASE)
2786/** Peripheral GPIOB base address */
2787#define GPIOB_BASE (0x400FF040u)
2788/** Peripheral GPIOB base pointer */
2789#define GPIOB ((GPIO_Type *)GPIOB_BASE)
2790/** Peripheral GPIOC base address */
2791#define GPIOC_BASE (0x400FF080u)
2792/** Peripheral GPIOC base pointer */
2793#define GPIOC ((GPIO_Type *)GPIOC_BASE)
2794/** Peripheral GPIOD base address */
2795#define GPIOD_BASE (0x400FF0C0u)
2796/** Peripheral GPIOD base pointer */
2797#define GPIOD ((GPIO_Type *)GPIOD_BASE)
2798/** Peripheral GPIOE base address */
2799#define GPIOE_BASE (0x400FF100u)
2800/** Peripheral GPIOE base pointer */
2801#define GPIOE ((GPIO_Type *)GPIOE_BASE)
2802/** Array initializer of GPIO peripheral base addresses */
2803#define GPIO_BASE_ADDRS \
2804 { \
2805 GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE \
2806 }
2807/** Array initializer of GPIO peripheral base pointers */
2808#define GPIO_BASE_PTRS \
2809 { \
2810 GPIOA, GPIOB, GPIOC, GPIOD, GPIOE \
2811 }
2812
2813/*!
2814 * @}
2815 */ /* end of group GPIO_Peripheral_Access_Layer */
2816
2817/* ----------------------------------------------------------------------------
2818 -- I2C Peripheral Access Layer
2819 ---------------------------------------------------------------------------- */
2820
2821/*!
2822 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
2823 * @{
2824 */
2825
2826/** I2C - Register Layout Typedef */
2827typedef struct
2828{
2829 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
2830 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
2831 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
2832 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
2833 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
2834 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
2835 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
2836 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
2837 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
2838 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
2839 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
2840 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
2841 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
2842} I2C_Type;
2843
2844/* ----------------------------------------------------------------------------
2845 -- I2C Register Masks
2846 ---------------------------------------------------------------------------- */
2847
2848/*!
2849 * @addtogroup I2C_Register_Masks I2C Register Masks
2850 * @{
2851 */
2852
2853/*! @name A1 - I2C Address Register 1 */
2854/*! @{ */
2855#define I2C_A1_AD_MASK (0xFEU)
2856#define I2C_A1_AD_SHIFT (1U)
2857/*! AD - Address
2858 */
2859#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
2860/*! @} */
2861
2862/*! @name F - I2C Frequency Divider register */
2863/*! @{ */
2864#define I2C_F_ICR_MASK (0x3FU)
2865#define I2C_F_ICR_SHIFT (0U)
2866/*! ICR - ClockRate
2867 */
2868#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
2869#define I2C_F_MULT_MASK (0xC0U)
2870#define I2C_F_MULT_SHIFT (6U)
2871/*! MULT - Multiplier Factor
2872 * 0b00..mul = 1
2873 * 0b01..mul = 2
2874 * 0b10..mul = 4
2875 * 0b11..Reserved
2876 */
2877#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
2878/*! @} */
2879
2880/*! @name C1 - I2C Control Register 1 */
2881/*! @{ */
2882#define I2C_C1_DMAEN_MASK (0x1U)
2883#define I2C_C1_DMAEN_SHIFT (0U)
2884/*! DMAEN - DMA Enable
2885 * 0b0..All DMA signalling disabled.
2886 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data
2887 * byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received
2888 * matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF]
2889 * are set. If the direction of transfer is known from master to slave, then it is not required to check
2890 * S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from
2891 * the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be
2892 * used. When FACK = 1, an address or a data byte is transmitted.
2893 */
2894#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
2895#define I2C_C1_WUEN_MASK (0x2U)
2896#define I2C_C1_WUEN_SHIFT (1U)
2897/*! WUEN - Wakeup Enable
2898 * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
2899 * 0b1..Enables the wakeup function in low power mode.
2900 */
2901#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
2902#define I2C_C1_RSTA_MASK (0x4U)
2903#define I2C_C1_RSTA_SHIFT (2U)
2904/*! RSTA - Repeat START
2905 */
2906#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
2907#define I2C_C1_TXAK_MASK (0x8U)
2908#define I2C_C1_TXAK_SHIFT (3U)
2909/*! TXAK - Transmit Acknowledge Enable
2910 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the
2911 * current receiving byte (if FACK is set).
2912 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the
2913 * current receiving data byte (if FACK is set).
2914 */
2915#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
2916#define I2C_C1_TX_MASK (0x10U)
2917#define I2C_C1_TX_SHIFT (4U)
2918/*! TX - Transmit Mode Select
2919 * 0b0..Receive
2920 * 0b1..Transmit
2921 */
2922#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
2923#define I2C_C1_MST_MASK (0x20U)
2924#define I2C_C1_MST_SHIFT (5U)
2925/*! MST - Master Mode Select
2926 * 0b0..Slave mode
2927 * 0b1..Master mode
2928 */
2929#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
2930#define I2C_C1_IICIE_MASK (0x40U)
2931#define I2C_C1_IICIE_SHIFT (6U)
2932/*! IICIE - I2C Interrupt Enable
2933 * 0b0..Disabled
2934 * 0b1..Enabled
2935 */
2936#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
2937#define I2C_C1_IICEN_MASK (0x80U)
2938#define I2C_C1_IICEN_SHIFT (7U)
2939/*! IICEN - I2C Enable
2940 * 0b0..Disabled
2941 * 0b1..Enabled
2942 */
2943#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
2944/*! @} */
2945
2946/*! @name S - I2C Status register */
2947/*! @{ */
2948#define I2C_S_RXAK_MASK (0x1U)
2949#define I2C_S_RXAK_SHIFT (0U)
2950/*! RXAK - Receive Acknowledge
2951 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
2952 * 0b1..No acknowledge signal detected
2953 */
2954#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
2955#define I2C_S_IICIF_MASK (0x2U)
2956#define I2C_S_IICIF_SHIFT (1U)
2957/*! IICIF - Interrupt Flag
2958 * 0b0..No interrupt pending
2959 * 0b1..Interrupt pending
2960 */
2961#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
2962#define I2C_S_SRW_MASK (0x4U)
2963#define I2C_S_SRW_SHIFT (2U)
2964/*! SRW - Slave Read/Write
2965 * 0b0..Slave receive, master writing to slave
2966 * 0b1..Slave transmit, master reading from slave
2967 */
2968#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
2969#define I2C_S_RAM_MASK (0x8U)
2970#define I2C_S_RAM_SHIFT (3U)
2971/*! RAM - Range Address Match
2972 * 0b0..Not addressed
2973 * 0b1..Addressed as a slave
2974 */
2975#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
2976#define I2C_S_ARBL_MASK (0x10U)
2977#define I2C_S_ARBL_SHIFT (4U)
2978/*! ARBL - Arbitration Lost
2979 * 0b0..Standard bus operation.
2980 * 0b1..Loss of arbitration.
2981 */
2982#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
2983#define I2C_S_BUSY_MASK (0x20U)
2984#define I2C_S_BUSY_SHIFT (5U)
2985/*! BUSY - Bus Busy
2986 * 0b0..Bus is idle
2987 * 0b1..Bus is busy
2988 */
2989#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
2990#define I2C_S_IAAS_MASK (0x40U)
2991#define I2C_S_IAAS_SHIFT (6U)
2992/*! IAAS - Addressed As A Slave
2993 * 0b0..Not addressed
2994 * 0b1..Addressed as a slave
2995 */
2996#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
2997#define I2C_S_TCF_MASK (0x80U)
2998#define I2C_S_TCF_SHIFT (7U)
2999/*! TCF - Transfer Complete Flag
3000 * 0b0..Transfer in progress
3001 * 0b1..Transfer complete
3002 */
3003#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
3004/*! @} */
3005
3006/*! @name D - I2C Data I/O register */
3007/*! @{ */
3008#define I2C_D_DATA_MASK (0xFFU)
3009#define I2C_D_DATA_SHIFT (0U)
3010/*! DATA - Data
3011 */
3012#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
3013/*! @} */
3014
3015/*! @name C2 - I2C Control Register 2 */
3016/*! @{ */
3017#define I2C_C2_AD_MASK (0x7U)
3018#define I2C_C2_AD_SHIFT (0U)
3019/*! AD - Slave Address
3020 */
3021#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
3022#define I2C_C2_RMEN_MASK (0x8U)
3023#define I2C_C2_RMEN_SHIFT (3U)
3024/*! RMEN - Range Address Matching Enable
3025 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA
3026 * registers. 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of
3027 * values of the A1 and RA registers.
3028 */
3029#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
3030#define I2C_C2_SBRC_MASK (0x10U)
3031#define I2C_C2_SBRC_SHIFT (4U)
3032/*! SBRC - Slave Baud Rate Control
3033 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
3034 * 0b1..Slave baud rate is independent of the master baud rate
3035 */
3036#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
3037#define I2C_C2_HDRS_MASK (0x20U)
3038#define I2C_C2_HDRS_SHIFT (5U)
3039/*! HDRS - High Drive Select
3040 * 0b0..Normal drive mode
3041 * 0b1..High drive mode
3042 */
3043#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
3044#define I2C_C2_ADEXT_MASK (0x40U)
3045#define I2C_C2_ADEXT_SHIFT (6U)
3046/*! ADEXT - Address Extension
3047 * 0b0..7-bit address scheme
3048 * 0b1..10-bit address scheme
3049 */
3050#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
3051#define I2C_C2_GCAEN_MASK (0x80U)
3052#define I2C_C2_GCAEN_SHIFT (7U)
3053/*! GCAEN - General Call Address Enable
3054 * 0b0..Disabled
3055 * 0b1..Enabled
3056 */
3057#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
3058/*! @} */
3059
3060/*! @name FLT - I2C Programmable Input Glitch Filter Register */
3061/*! @{ */
3062#define I2C_FLT_FLT_MASK (0xFU)
3063#define I2C_FLT_FLT_SHIFT (0U)
3064/*! FLT - I2C Programmable Filter Factor
3065 * 0b0000..No filter/bypass
3066 */
3067#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
3068#define I2C_FLT_STARTF_MASK (0x10U)
3069#define I2C_FLT_STARTF_SHIFT (4U)
3070/*! STARTF - I2C Bus Start Detect Flag
3071 * 0b0..No start happens on I2C bus
3072 * 0b1..Start detected on I2C bus
3073 */
3074#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
3075#define I2C_FLT_SSIE_MASK (0x20U)
3076#define I2C_FLT_SSIE_SHIFT (5U)
3077/*! SSIE - I2C Bus Stop or Start Interrupt Enable
3078 * 0b0..Stop or start detection interrupt is disabled
3079 * 0b1..Stop or start detection interrupt is enabled
3080 */
3081#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
3082#define I2C_FLT_STOPF_MASK (0x40U)
3083#define I2C_FLT_STOPF_SHIFT (6U)
3084/*! STOPF - I2C Bus Stop Detect Flag
3085 * 0b0..No stop happens on I2C bus
3086 * 0b1..Stop detected on I2C bus
3087 */
3088#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
3089#define I2C_FLT_SHEN_MASK (0x80U)
3090#define I2C_FLT_SHEN_SHIFT (7U)
3091/*! SHEN - Stop Hold Enable
3092 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
3093 * 0b1..Stop holdoff is enabled.
3094 */
3095#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
3096/*! @} */
3097
3098/*! @name RA - I2C Range Address register */
3099/*! @{ */
3100#define I2C_RA_RAD_MASK (0xFEU)
3101#define I2C_RA_RAD_SHIFT (1U)
3102/*! RAD - Range Slave Address
3103 */
3104#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
3105/*! @} */
3106
3107/*! @name SMB - I2C SMBus Control and Status register */
3108/*! @{ */
3109#define I2C_SMB_SHTF2IE_MASK (0x1U)
3110#define I2C_SMB_SHTF2IE_SHIFT (0U)
3111/*! SHTF2IE - SHTF2 Interrupt Enable
3112 * 0b0..SHTF2 interrupt is disabled
3113 * 0b1..SHTF2 interrupt is enabled
3114 */
3115#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
3116#define I2C_SMB_SHTF2_MASK (0x2U)
3117#define I2C_SMB_SHTF2_SHIFT (1U)
3118/*! SHTF2 - SCL High Timeout Flag 2
3119 * 0b0..No SCL high and SDA low timeout occurs
3120 * 0b1..SCL high and SDA low timeout occurs
3121 */
3122#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
3123#define I2C_SMB_SHTF1_MASK (0x4U)
3124#define I2C_SMB_SHTF1_SHIFT (2U)
3125/*! SHTF1 - SCL High Timeout Flag 1
3126 * 0b0..No SCL high and SDA high timeout occurs
3127 * 0b1..SCL high and SDA high timeout occurs
3128 */
3129#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
3130#define I2C_SMB_SLTF_MASK (0x8U)
3131#define I2C_SMB_SLTF_SHIFT (3U)
3132/*! SLTF - SCL Low Timeout Flag
3133 * 0b0..No low timeout occurs
3134 * 0b1..Low timeout occurs
3135 */
3136#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
3137#define I2C_SMB_TCKSEL_MASK (0x10U)
3138#define I2C_SMB_TCKSEL_SHIFT (4U)
3139/*! TCKSEL - Timeout Counter Clock Select
3140 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
3141 * 0b1..Timeout counter counts at the frequency of the I2C module clock
3142 */
3143#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
3144#define I2C_SMB_SIICAEN_MASK (0x20U)
3145#define I2C_SMB_SIICAEN_SHIFT (5U)
3146/*! SIICAEN - Second I2C Address Enable
3147 * 0b0..I2C address register 2 matching is disabled
3148 * 0b1..I2C address register 2 matching is enabled
3149 */
3150#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
3151#define I2C_SMB_ALERTEN_MASK (0x40U)
3152#define I2C_SMB_ALERTEN_SHIFT (6U)
3153/*! ALERTEN - SMBus Alert Response Address Enable
3154 * 0b0..SMBus alert response address matching is disabled
3155 * 0b1..SMBus alert response address matching is enabled
3156 */
3157#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
3158#define I2C_SMB_FACK_MASK (0x80U)
3159#define I2C_SMB_FACK_SHIFT (7U)
3160/*! FACK - Fast NACK/ACK Enable
3161 * 0b0..An ACK or NACK is sent on the following receiving data byte
3162 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte
3163 * generates a NACK.
3164 */
3165#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
3166/*! @} */
3167
3168/*! @name A2 - I2C Address Register 2 */
3169/*! @{ */
3170#define I2C_A2_SAD_MASK (0xFEU)
3171#define I2C_A2_SAD_SHIFT (1U)
3172/*! SAD - SMBus Address
3173 */
3174#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
3175/*! @} */
3176
3177/*! @name SLTH - I2C SCL Low Timeout Register High */
3178/*! @{ */
3179#define I2C_SLTH_SSLT_MASK (0xFFU)
3180#define I2C_SLTH_SSLT_SHIFT (0U)
3181/*! SSLT - SSLT[15:8]
3182 */
3183#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
3184/*! @} */
3185
3186/*! @name SLTL - I2C SCL Low Timeout Register Low */
3187/*! @{ */
3188#define I2C_SLTL_SSLT_MASK (0xFFU)
3189#define I2C_SLTL_SSLT_SHIFT (0U)
3190/*! SSLT - SSLT[7:0]
3191 */
3192#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
3193/*! @} */
3194
3195/*! @name S2 - I2C Status register 2 */
3196/*! @{ */
3197#define I2C_S2_EMPTY_MASK (0x1U)
3198#define I2C_S2_EMPTY_SHIFT (0U)
3199/*! EMPTY - Empty flag
3200 * 0b0..Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
3201 * 0b1..Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.
3202 */
3203#define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
3204#define I2C_S2_ERROR_MASK (0x2U)
3205#define I2C_S2_ERROR_SHIFT (1U)
3206/*! ERROR - Error flag
3207 * 0b0..The buffer is not full and all write/read operations have no errors.
3208 * 0b1..There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the
3209 * buffer is busy).
3210 */
3211#define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
3212/*! @} */
3213
3214/*!
3215 * @}
3216 */ /* end of group I2C_Register_Masks */
3217
3218/* I2C - Peripheral instance base addresses */
3219/** Peripheral I2C0 base address */
3220#define I2C0_BASE (0x40066000u)
3221/** Peripheral I2C0 base pointer */
3222#define I2C0 ((I2C_Type *)I2C0_BASE)
3223/** Peripheral I2C1 base address */
3224#define I2C1_BASE (0x40067000u)
3225/** Peripheral I2C1 base pointer */
3226#define I2C1 ((I2C_Type *)I2C1_BASE)
3227/** Array initializer of I2C peripheral base addresses */
3228#define I2C_BASE_ADDRS \
3229 { \
3230 I2C0_BASE, I2C1_BASE \
3231 }
3232/** Array initializer of I2C peripheral base pointers */
3233#define I2C_BASE_PTRS \
3234 { \
3235 I2C0, I2C1 \
3236 }
3237/** Interrupt vectors for the I2C peripheral type */
3238#define I2C_IRQS \
3239 { \
3240 I2C0_IRQn, I2C1_IRQn \
3241 }
3242
3243/*!
3244 * @}
3245 */ /* end of group I2C_Peripheral_Access_Layer */
3246
3247/* ----------------------------------------------------------------------------
3248 -- LCD Peripheral Access Layer
3249 ---------------------------------------------------------------------------- */
3250
3251/*!
3252 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
3253 * @{
3254 */
3255
3256/** LCD - Register Layout Typedef */
3257typedef struct
3258{
3259 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
3260 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
3261 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
3262 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
3263 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
3264 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
3265 union
3266 { /* offset: 0x20 */
3267 __IO uint8_t
3268 WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
3269 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
3270 };
3271} LCD_Type;
3272
3273/* ----------------------------------------------------------------------------
3274 -- LCD Register Masks
3275 ---------------------------------------------------------------------------- */
3276
3277/*!
3278 * @addtogroup LCD_Register_Masks LCD Register Masks
3279 * @{
3280 */
3281
3282/*! @name GCR - LCD General Control Register */
3283/*! @{ */
3284#define LCD_GCR_DUTY_MASK (0x7U)
3285#define LCD_GCR_DUTY_SHIFT (0U)
3286/*! DUTY - LCD duty select
3287 * 0b000..Use 1 BP (1/1 duty cycle).
3288 * 0b001..Use 2 BP (1/2 duty cycle).
3289 * 0b010..Use 3 BP (1/3 duty cycle).
3290 * 0b011..Use 4 BP (1/4 duty cycle). (Default)
3291 * 0b100..
3292 * 0b101..
3293 * 0b110..
3294 * 0b111..Use 8 BP (1/8 duty cycle).
3295 */
3296#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_DUTY_SHIFT)) & LCD_GCR_DUTY_MASK)
3297#define LCD_GCR_LCLK_MASK (0x38U)
3298#define LCD_GCR_LCLK_SHIFT (3U)
3299/*! LCLK - LCD Clock Prescaler
3300 */
3301#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCLK_SHIFT)) & LCD_GCR_LCLK_MASK)
3302#define LCD_GCR_SOURCE_MASK (0x40U)
3303#define LCD_GCR_SOURCE_SHIFT (6U)
3304/*! SOURCE - LCD Clock Source Select
3305 * 0b0..Selects the default clock as the LCD clock source.
3306 * 0b1..Selects output of the alternate clock source selection (see ALTSOURCE) as the LCD clock source.
3307 */
3308#define LCD_GCR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_SOURCE_SHIFT)) & LCD_GCR_SOURCE_MASK)
3309#define LCD_GCR_LCDEN_MASK (0x80U)
3310#define LCD_GCR_LCDEN_SHIFT (7U)
3311/*! LCDEN - LCD Driver Enable
3312 * 0b0..All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD
3313 * waveform generation clocks are stopped. V LL3 is connected to V DD internally. All LCD pins, LCD_Pn,
3314 * enabled using the LCD Pin Enable register, output a low value.
3315 * 0b1..LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD
3316 * pins, LCD_Pn, enabled if PAD_SAFE is clearusing the LCD Pin Enable register, output an LCD driver
3317 * waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0].
3318 * Charge pump or resistor bias is enabled.
3319 */
3320#define LCD_GCR_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDEN_SHIFT)) & LCD_GCR_LCDEN_MASK)
3321#define LCD_GCR_LCDSTP_MASK (0x100U)
3322#define LCD_GCR_LCDSTP_SHIFT (8U)
3323/*! LCDSTP - LCD Stop
3324 * 0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during
3325 * Stop mode. 0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters
3326 * Stop mode.
3327 */
3328#define LCD_GCR_LCDSTP(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDSTP_SHIFT)) & LCD_GCR_LCDSTP_MASK)
3329#define LCD_GCR_LCDDOZE_MASK (0x200U)
3330#define LCD_GCR_LCDDOZE_SHIFT (9U)
3331/*! LCDDOZE - LCD Doze enable
3332 * 0b0..Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during
3333 * Doze mode. 0b1..Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters
3334 * Doze mode.
3335 */
3336#define LCD_GCR_LCDDOZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LCDDOZE_SHIFT)) & LCD_GCR_LCDDOZE_MASK)
3337#define LCD_GCR_FFR_MASK (0x400U)
3338#define LCD_GCR_FFR_SHIFT (10U)
3339/*! FFR - Fast Frame Rate Select
3340 * 0b0..Standard Frame Rate LCD Frame Freq: 23.3 (min) 73.1 (max)
3341 * 0b1..Fast Frame Rate (Standard Frame Rate *2) LCD Frame Freq: 46.6 (min) 146.2 (max)
3342 */
3343#define LCD_GCR_FFR(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FFR_SHIFT)) & LCD_GCR_FFR_MASK)
3344#define LCD_GCR_ALTSOURCE_MASK (0x800U)
3345#define LCD_GCR_ALTSOURCE_SHIFT (11U)
3346/*! ALTSOURCE - Selects the alternate clock source
3347 * 0b0..Select Alternate Clock Source 1 (default)
3348 * 0b1..Select Alternate Clock Source 2
3349 */
3350#define LCD_GCR_ALTSOURCE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTSOURCE_SHIFT)) & LCD_GCR_ALTSOURCE_MASK)
3351#define LCD_GCR_ALTDIV_MASK (0x3000U)
3352#define LCD_GCR_ALTDIV_SHIFT (12U)
3353/*! ALTDIV - LCD Alternate Clock Divider
3354 * 0b00..Divide factor = 1 (No divide)
3355 * 0b01..Divide factor = 64
3356 * 0b10..Divide factor = 256
3357 * 0b11..Divide factor = 512
3358 */
3359#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_ALTDIV_SHIFT)) & LCD_GCR_ALTDIV_MASK)
3360#define LCD_GCR_FDCIEN_MASK (0x4000U)
3361#define LCD_GCR_FDCIEN_SHIFT (14U)
3362/*! FDCIEN - LCD Fault Detection Complete Interrupt Enable
3363 * 0b0..No interrupt request is generated by this event.
3364 * 0b1..When a fault is detected and FDCF bit is set, this event causes an interrupt request.
3365 */
3366#define LCD_GCR_FDCIEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_FDCIEN_SHIFT)) & LCD_GCR_FDCIEN_MASK)
3367#define LCD_GCR_PADSAFE_MASK (0x8000U)
3368#define LCD_GCR_PADSAFE_SHIFT (15U)
3369/*! PADSAFE - Pad Safe State Enable
3370 * 0b0..LCD frontplane and backplane functions enabled according to other LCD control bits
3371 * 0b1..LCD frontplane and backplane functions disabled
3372 */
3373#define LCD_GCR_PADSAFE(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_PADSAFE_SHIFT)) & LCD_GCR_PADSAFE_MASK)
3374#define LCD_GCR_VSUPPLY_MASK (0x20000U)
3375#define LCD_GCR_VSUPPLY_SHIFT (17U)
3376/*! VSUPPLY - Voltage Supply Control
3377 * 0b0..Drive VLL3 internally from VDD
3378 * 0b1..Drive VLL3 externally from VDD or drive VLL1 internally from vIREG
3379 */
3380#define LCD_GCR_VSUPPLY(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_VSUPPLY_SHIFT)) & LCD_GCR_VSUPPLY_MASK)
3381#define LCD_GCR_LADJ_MASK (0x300000U)
3382#define LCD_GCR_LADJ_SHIFT (20U)
3383/*! LADJ - Load Adjust
3384 */
3385#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_LADJ_SHIFT)) & LCD_GCR_LADJ_MASK)
3386#define LCD_GCR_CPSEL_MASK (0x800000U)
3387#define LCD_GCR_CPSEL_SHIFT (23U)
3388/*! CPSEL - Charge Pump or Resistor Bias Select
3389 * 0b0..LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)
3390 * 0b1..LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)
3391 */
3392#define LCD_GCR_CPSEL(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_CPSEL_SHIFT)) & LCD_GCR_CPSEL_MASK)
3393#define LCD_GCR_RVTRIM_MASK (0xF000000U)
3394#define LCD_GCR_RVTRIM_SHIFT (24U)
3395/*! RVTRIM - Regulated Voltage Trim
3396 */
3397#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVTRIM_SHIFT)) & LCD_GCR_RVTRIM_MASK)
3398#define LCD_GCR_RVEN_MASK (0x80000000U)
3399#define LCD_GCR_RVEN_SHIFT (31U)
3400/*! RVEN - Regulated Voltage Enable
3401 * 0b0..Regulated voltage disabled.
3402 * 0b1..Regulated voltage enabled.
3403 */
3404#define LCD_GCR_RVEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_GCR_RVEN_SHIFT)) & LCD_GCR_RVEN_MASK)
3405/*! @} */
3406
3407/*! @name AR - LCD Auxiliary Register */
3408/*! @{ */
3409#define LCD_AR_BRATE_MASK (0x7U)
3410#define LCD_AR_BRATE_SHIFT (0U)
3411/*! BRATE - Blink-rate configuration
3412 */
3413#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BRATE_SHIFT)) & LCD_AR_BRATE_MASK)
3414#define LCD_AR_BMODE_MASK (0x8U)
3415#define LCD_AR_BMODE_SHIFT (3U)
3416/*! BMODE - Blink mode
3417 * 0b0..Display blank during the blink period.
3418 * 0b1..Display alternate display during blink period (Ignored if duty is 5 or greater).
3419 */
3420#define LCD_AR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BMODE_SHIFT)) & LCD_AR_BMODE_MASK)
3421#define LCD_AR_BLANK_MASK (0x20U)
3422#define LCD_AR_BLANK_SHIFT (5U)
3423/*! BLANK - Blank display mode
3424 * 0b0..Normal or alternate display mode.
3425 * 0b1..Blank display mode.
3426 */
3427#define LCD_AR_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLANK_SHIFT)) & LCD_AR_BLANK_MASK)
3428#define LCD_AR_ALT_MASK (0x40U)
3429#define LCD_AR_ALT_SHIFT (6U)
3430/*! ALT - Alternate display mode
3431 * 0b0..Normal display mode.
3432 * 0b1..Alternate display mode.
3433 */
3434#define LCD_AR_ALT(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_ALT_SHIFT)) & LCD_AR_ALT_MASK)
3435#define LCD_AR_BLINK_MASK (0x80U)
3436#define LCD_AR_BLINK_SHIFT (7U)
3437/*! BLINK - Blink command
3438 * 0b0..Disables blinking.
3439 * 0b1..Starts blinking at blinking frequency specified by LCD blink rate calculation.
3440 */
3441#define LCD_AR_BLINK(x) (((uint32_t)(((uint32_t)(x)) << LCD_AR_BLINK_SHIFT)) & LCD_AR_BLINK_MASK)
3442/*! @} */
3443
3444/*! @name FDCR - LCD Fault Detect Control Register */
3445/*! @{ */
3446#define LCD_FDCR_FDPINID_MASK (0x3FU)
3447#define LCD_FDCR_FDPINID_SHIFT (0U)
3448/*! FDPINID - Fault Detect Pin ID
3449 * 0b000000..Fault detection for LCD_P0 pin.
3450 * 0b000001..Fault detection for LCD_P1 pin.
3451 * 0b111111..Fault detection for LCD_P63 pin.
3452 */
3453#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPINID_SHIFT)) & LCD_FDCR_FDPINID_MASK)
3454#define LCD_FDCR_FDBPEN_MASK (0x40U)
3455#define LCD_FDCR_FDBPEN_SHIFT (6U)
3456/*! FDBPEN - Fault Detect Back Plane Enable
3457 * 0b0..Type of the selected pin under fault detect test is front plane.
3458 * 0b1..Type of the selected pin under fault detect test is back plane.
3459 */
3460#define LCD_FDCR_FDBPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDBPEN_SHIFT)) & LCD_FDCR_FDBPEN_MASK)
3461#define LCD_FDCR_FDEN_MASK (0x80U)
3462#define LCD_FDCR_FDEN_SHIFT (7U)
3463/*! FDEN - Fault Detect Enable
3464 * 0b0..Disable fault detection.
3465 * 0b1..Enable fault detection.
3466 */
3467#define LCD_FDCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDEN_SHIFT)) & LCD_FDCR_FDEN_MASK)
3468#define LCD_FDCR_FDSWW_MASK (0xE00U)
3469#define LCD_FDCR_FDSWW_SHIFT (9U)
3470/*! FDSWW - Fault Detect Sample Window Width
3471 * 0b000..Sample window width is 4 sample clock cycles.
3472 * 0b001..Sample window width is 8 sample clock cycles.
3473 * 0b010..Sample window width is 16 sample clock cycles.
3474 * 0b011..Sample window width is 32 sample clock cycles.
3475 * 0b100..Sample window width is 64 sample clock cycles.
3476 * 0b101..Sample window width is 128 sample clock cycles.
3477 * 0b110..Sample window width is 256 sample clock cycles.
3478 * 0b111..Sample window width is 512 sample clock cycles.
3479 */
3480#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDSWW_SHIFT)) & LCD_FDCR_FDSWW_MASK)
3481#define LCD_FDCR_FDPRS_MASK (0x7000U)
3482#define LCD_FDCR_FDPRS_SHIFT (12U)
3483/*! FDPRS - Fault Detect Clock Prescaler
3484 * 0b000..1/1 bus clock.
3485 * 0b001..1/2 bus clock.
3486 * 0b010..1/4 bus clock.
3487 * 0b011..1/8 bus clock.
3488 * 0b100..1/16 bus clock.
3489 * 0b101..1/32 bus clock.
3490 * 0b110..1/64 bus clock.
3491 * 0b111..1/128 bus clock.
3492 */
3493#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDCR_FDPRS_SHIFT)) & LCD_FDCR_FDPRS_MASK)
3494/*! @} */
3495
3496/*! @name FDSR - LCD Fault Detect Status Register */
3497/*! @{ */
3498#define LCD_FDSR_FDCNT_MASK (0xFFU)
3499#define LCD_FDSR_FDCNT_SHIFT (0U)
3500/*! FDCNT - Fault Detect Counter
3501 * 0b00000000..No "one" samples.
3502 * 0b00000001..1 "one" samples.
3503 * 0b00000010..2 "one" samples.
3504 * 0b11111110..254 "one" samples.
3505 * 0b11111111..255 or more "one" samples. The FDCNT can overflow. Therefore, FDSWW and FDPRS must be reconfigured for
3506 * proper sampling.
3507 */
3508#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCNT_SHIFT)) & LCD_FDSR_FDCNT_MASK)
3509#define LCD_FDSR_FDCF_MASK (0x8000U)
3510#define LCD_FDSR_FDCF_SHIFT (15U)
3511/*! FDCF - Fault Detection Complete Flag
3512 * 0b0..Fault detection is not completed.
3513 * 0b1..Fault detection is completed.
3514 */
3515#define LCD_FDSR_FDCF(x) (((uint32_t)(((uint32_t)(x)) << LCD_FDSR_FDCF_SHIFT)) & LCD_FDSR_FDCF_MASK)
3516/*! @} */
3517
3518/*! @name PEN - LCD Pin Enable register */
3519/*! @{ */
3520#define LCD_PEN_PEN_MASK (0xFFFFFFFFU)
3521#define LCD_PEN_PEN_SHIFT (0U)
3522/*! PEN - LCD Pin Enable
3523 * 0b00000000000000000000000000000000..LCD operation disabled on LCD_Pn.
3524 * 0b00000000000000000000000000000001..LCD operation enabled on LCD_Pn.
3525 */
3526#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_PEN_PEN_SHIFT)) & LCD_PEN_PEN_MASK)
3527/*! @} */
3528
3529/* The count of LCD_PEN */
3530#define LCD_PEN_COUNT (2U)
3531
3532/*! @name BPEN - LCD Back Plane Enable register */
3533/*! @{ */
3534#define LCD_BPEN_BPEN_MASK (0xFFFFFFFFU)
3535#define LCD_BPEN_BPEN_SHIFT (0U)
3536/*! BPEN - Back Plane Enable
3537 * 0b00000000000000000000000000000000..Front plane operation enabled on LCD_Pn.
3538 * 0b00000000000000000000000000000001..Back plane operation enabled on LCD_Pn.
3539 */
3540#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_BPEN_BPEN_SHIFT)) & LCD_BPEN_BPEN_MASK)
3541/*! @} */
3542
3543/* The count of LCD_BPEN */
3544#define LCD_BPEN_COUNT (2U)
3545
3546/*! @name WF8B - LCD Waveform Register 0...LCD Waveform Register 63. */
3547/*! @{ */
3548#define LCD_WF8B_BPALCD0_MASK (0x1U)
3549#define LCD_WF8B_BPALCD0_SHIFT (0U)
3550/*! BPALCD0
3551 * 0b0..LCD segment off or LCD backplane inactive for phase A
3552 * 0b1..LCD segment on or LCD backplane active for phase A
3553 */
3554#define LCD_WF8B_BPALCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD0_SHIFT)) & LCD_WF8B_BPALCD0_MASK)
3555#define LCD_WF8B_BPALCD1_MASK (0x1U)
3556#define LCD_WF8B_BPALCD1_SHIFT (0U)
3557/*! BPALCD1
3558 * 0b0..LCD segment off or LCD backplane inactive for phase A
3559 * 0b1..LCD segment on or LCD backplane active for phase A
3560 */
3561#define LCD_WF8B_BPALCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD1_SHIFT)) & LCD_WF8B_BPALCD1_MASK)
3562#define LCD_WF8B_BPALCD2_MASK (0x1U)
3563#define LCD_WF8B_BPALCD2_SHIFT (0U)
3564/*! BPALCD2
3565 * 0b0..LCD segment off or LCD backplane inactive for phase A
3566 * 0b1..LCD segment on or LCD backplane active for phase A
3567 */
3568#define LCD_WF8B_BPALCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD2_SHIFT)) & LCD_WF8B_BPALCD2_MASK)
3569#define LCD_WF8B_BPALCD3_MASK (0x1U)
3570#define LCD_WF8B_BPALCD3_SHIFT (0U)
3571/*! BPALCD3
3572 * 0b0..LCD segment off or LCD backplane inactive for phase A
3573 * 0b1..LCD segment on or LCD backplane active for phase A
3574 */
3575#define LCD_WF8B_BPALCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD3_SHIFT)) & LCD_WF8B_BPALCD3_MASK)
3576#define LCD_WF8B_BPALCD4_MASK (0x1U)
3577#define LCD_WF8B_BPALCD4_SHIFT (0U)
3578/*! BPALCD4
3579 * 0b0..LCD segment off or LCD backplane inactive for phase A
3580 * 0b1..LCD segment on or LCD backplane active for phase A
3581 */
3582#define LCD_WF8B_BPALCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD4_SHIFT)) & LCD_WF8B_BPALCD4_MASK)
3583#define LCD_WF8B_BPALCD5_MASK (0x1U)
3584#define LCD_WF8B_BPALCD5_SHIFT (0U)
3585/*! BPALCD5
3586 * 0b0..LCD segment off or LCD backplane inactive for phase A
3587 * 0b1..LCD segment on or LCD backplane active for phase A
3588 */
3589#define LCD_WF8B_BPALCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD5_SHIFT)) & LCD_WF8B_BPALCD5_MASK)
3590#define LCD_WF8B_BPALCD6_MASK (0x1U)
3591#define LCD_WF8B_BPALCD6_SHIFT (0U)
3592/*! BPALCD6
3593 * 0b0..LCD segment off or LCD backplane inactive for phase A
3594 * 0b1..LCD segment on or LCD backplane active for phase A
3595 */
3596#define LCD_WF8B_BPALCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD6_SHIFT)) & LCD_WF8B_BPALCD6_MASK)
3597#define LCD_WF8B_BPALCD7_MASK (0x1U)
3598#define LCD_WF8B_BPALCD7_SHIFT (0U)
3599/*! BPALCD7
3600 * 0b0..LCD segment off or LCD backplane inactive for phase A
3601 * 0b1..LCD segment on or LCD backplane active for phase A
3602 */
3603#define LCD_WF8B_BPALCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD7_SHIFT)) & LCD_WF8B_BPALCD7_MASK)
3604#define LCD_WF8B_BPALCD8_MASK (0x1U)
3605#define LCD_WF8B_BPALCD8_SHIFT (0U)
3606/*! BPALCD8
3607 * 0b0..LCD segment off or LCD backplane inactive for phase A
3608 * 0b1..LCD segment on or LCD backplane active for phase A
3609 */
3610#define LCD_WF8B_BPALCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD8_SHIFT)) & LCD_WF8B_BPALCD8_MASK)
3611#define LCD_WF8B_BPALCD9_MASK (0x1U)
3612#define LCD_WF8B_BPALCD9_SHIFT (0U)
3613/*! BPALCD9
3614 * 0b0..LCD segment off or LCD backplane inactive for phase A
3615 * 0b1..LCD segment on or LCD backplane active for phase A
3616 */
3617#define LCD_WF8B_BPALCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD9_SHIFT)) & LCD_WF8B_BPALCD9_MASK)
3618#define LCD_WF8B_BPALCD10_MASK (0x1U)
3619#define LCD_WF8B_BPALCD10_SHIFT (0U)
3620/*! BPALCD10
3621 * 0b0..LCD segment off or LCD backplane inactive for phase A
3622 * 0b1..LCD segment on or LCD backplane active for phase A
3623 */
3624#define LCD_WF8B_BPALCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD10_SHIFT)) & LCD_WF8B_BPALCD10_MASK)
3625#define LCD_WF8B_BPALCD11_MASK (0x1U)
3626#define LCD_WF8B_BPALCD11_SHIFT (0U)
3627/*! BPALCD11
3628 * 0b0..LCD segment off or LCD backplane inactive for phase A
3629 * 0b1..LCD segment on or LCD backplane active for phase A
3630 */
3631#define LCD_WF8B_BPALCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD11_SHIFT)) & LCD_WF8B_BPALCD11_MASK)
3632#define LCD_WF8B_BPALCD12_MASK (0x1U)
3633#define LCD_WF8B_BPALCD12_SHIFT (0U)
3634/*! BPALCD12
3635 * 0b0..LCD segment off or LCD backplane inactive for phase A
3636 * 0b1..LCD segment on or LCD backplane active for phase A
3637 */
3638#define LCD_WF8B_BPALCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD12_SHIFT)) & LCD_WF8B_BPALCD12_MASK)
3639#define LCD_WF8B_BPALCD13_MASK (0x1U)
3640#define LCD_WF8B_BPALCD13_SHIFT (0U)
3641/*! BPALCD13
3642 * 0b0..LCD segment off or LCD backplane inactive for phase A
3643 * 0b1..LCD segment on or LCD backplane active for phase A
3644 */
3645#define LCD_WF8B_BPALCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD13_SHIFT)) & LCD_WF8B_BPALCD13_MASK)
3646#define LCD_WF8B_BPALCD14_MASK (0x1U)
3647#define LCD_WF8B_BPALCD14_SHIFT (0U)
3648/*! BPALCD14
3649 * 0b0..LCD segment off or LCD backplane inactive for phase A
3650 * 0b1..LCD segment on or LCD backplane active for phase A
3651 */
3652#define LCD_WF8B_BPALCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD14_SHIFT)) & LCD_WF8B_BPALCD14_MASK)
3653#define LCD_WF8B_BPALCD15_MASK (0x1U)
3654#define LCD_WF8B_BPALCD15_SHIFT (0U)
3655/*! BPALCD15
3656 * 0b0..LCD segment off or LCD backplane inactive for phase A
3657 * 0b1..LCD segment on or LCD backplane active for phase A
3658 */
3659#define LCD_WF8B_BPALCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD15_SHIFT)) & LCD_WF8B_BPALCD15_MASK)
3660#define LCD_WF8B_BPALCD16_MASK (0x1U)
3661#define LCD_WF8B_BPALCD16_SHIFT (0U)
3662/*! BPALCD16
3663 * 0b0..LCD segment off or LCD backplane inactive for phase A
3664 * 0b1..LCD segment on or LCD backplane active for phase A
3665 */
3666#define LCD_WF8B_BPALCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD16_SHIFT)) & LCD_WF8B_BPALCD16_MASK)
3667#define LCD_WF8B_BPALCD17_MASK (0x1U)
3668#define LCD_WF8B_BPALCD17_SHIFT (0U)
3669/*! BPALCD17
3670 * 0b0..LCD segment off or LCD backplane inactive for phase A
3671 * 0b1..LCD segment on or LCD backplane active for phase A
3672 */
3673#define LCD_WF8B_BPALCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD17_SHIFT)) & LCD_WF8B_BPALCD17_MASK)
3674#define LCD_WF8B_BPALCD18_MASK (0x1U)
3675#define LCD_WF8B_BPALCD18_SHIFT (0U)
3676/*! BPALCD18
3677 * 0b0..LCD segment off or LCD backplane inactive for phase A
3678 * 0b1..LCD segment on or LCD backplane active for phase A
3679 */
3680#define LCD_WF8B_BPALCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD18_SHIFT)) & LCD_WF8B_BPALCD18_MASK)
3681#define LCD_WF8B_BPALCD19_MASK (0x1U)
3682#define LCD_WF8B_BPALCD19_SHIFT (0U)
3683/*! BPALCD19
3684 * 0b0..LCD segment off or LCD backplane inactive for phase A
3685 * 0b1..LCD segment on or LCD backplane active for phase A
3686 */
3687#define LCD_WF8B_BPALCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD19_SHIFT)) & LCD_WF8B_BPALCD19_MASK)
3688#define LCD_WF8B_BPALCD20_MASK (0x1U)
3689#define LCD_WF8B_BPALCD20_SHIFT (0U)
3690/*! BPALCD20
3691 * 0b0..LCD segment off or LCD backplane inactive for phase A
3692 * 0b1..LCD segment on or LCD backplane active for phase A
3693 */
3694#define LCD_WF8B_BPALCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD20_SHIFT)) & LCD_WF8B_BPALCD20_MASK)
3695#define LCD_WF8B_BPALCD21_MASK (0x1U)
3696#define LCD_WF8B_BPALCD21_SHIFT (0U)
3697/*! BPALCD21
3698 * 0b0..LCD segment off or LCD backplane inactive for phase A
3699 * 0b1..LCD segment on or LCD backplane active for phase A
3700 */
3701#define LCD_WF8B_BPALCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD21_SHIFT)) & LCD_WF8B_BPALCD21_MASK)
3702#define LCD_WF8B_BPALCD22_MASK (0x1U)
3703#define LCD_WF8B_BPALCD22_SHIFT (0U)
3704/*! BPALCD22
3705 * 0b0..LCD segment off or LCD backplane inactive for phase A
3706 * 0b1..LCD segment on or LCD backplane active for phase A
3707 */
3708#define LCD_WF8B_BPALCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD22_SHIFT)) & LCD_WF8B_BPALCD22_MASK)
3709#define LCD_WF8B_BPALCD23_MASK (0x1U)
3710#define LCD_WF8B_BPALCD23_SHIFT (0U)
3711/*! BPALCD23
3712 * 0b0..LCD segment off or LCD backplane inactive for phase A
3713 * 0b1..LCD segment on or LCD backplane active for phase A
3714 */
3715#define LCD_WF8B_BPALCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD23_SHIFT)) & LCD_WF8B_BPALCD23_MASK)
3716#define LCD_WF8B_BPALCD24_MASK (0x1U)
3717#define LCD_WF8B_BPALCD24_SHIFT (0U)
3718/*! BPALCD24
3719 * 0b0..LCD segment off or LCD backplane inactive for phase A
3720 * 0b1..LCD segment on or LCD backplane active for phase A
3721 */
3722#define LCD_WF8B_BPALCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD24_SHIFT)) & LCD_WF8B_BPALCD24_MASK)
3723#define LCD_WF8B_BPALCD25_MASK (0x1U)
3724#define LCD_WF8B_BPALCD25_SHIFT (0U)
3725/*! BPALCD25
3726 * 0b0..LCD segment off or LCD backplane inactive for phase A
3727 * 0b1..LCD segment on or LCD backplane active for phase A
3728 */
3729#define LCD_WF8B_BPALCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD25_SHIFT)) & LCD_WF8B_BPALCD25_MASK)
3730#define LCD_WF8B_BPALCD26_MASK (0x1U)
3731#define LCD_WF8B_BPALCD26_SHIFT (0U)
3732/*! BPALCD26
3733 * 0b0..LCD segment off or LCD backplane inactive for phase A
3734 * 0b1..LCD segment on or LCD backplane active for phase A
3735 */
3736#define LCD_WF8B_BPALCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD26_SHIFT)) & LCD_WF8B_BPALCD26_MASK)
3737#define LCD_WF8B_BPALCD27_MASK (0x1U)
3738#define LCD_WF8B_BPALCD27_SHIFT (0U)
3739/*! BPALCD27
3740 * 0b0..LCD segment off or LCD backplane inactive for phase A
3741 * 0b1..LCD segment on or LCD backplane active for phase A
3742 */
3743#define LCD_WF8B_BPALCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD27_SHIFT)) & LCD_WF8B_BPALCD27_MASK)
3744#define LCD_WF8B_BPALCD28_MASK (0x1U)
3745#define LCD_WF8B_BPALCD28_SHIFT (0U)
3746/*! BPALCD28
3747 * 0b0..LCD segment off or LCD backplane inactive for phase A
3748 * 0b1..LCD segment on or LCD backplane active for phase A
3749 */
3750#define LCD_WF8B_BPALCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD28_SHIFT)) & LCD_WF8B_BPALCD28_MASK)
3751#define LCD_WF8B_BPALCD29_MASK (0x1U)
3752#define LCD_WF8B_BPALCD29_SHIFT (0U)
3753/*! BPALCD29
3754 * 0b0..LCD segment off or LCD backplane inactive for phase A
3755 * 0b1..LCD segment on or LCD backplane active for phase A
3756 */
3757#define LCD_WF8B_BPALCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD29_SHIFT)) & LCD_WF8B_BPALCD29_MASK)
3758#define LCD_WF8B_BPALCD30_MASK (0x1U)
3759#define LCD_WF8B_BPALCD30_SHIFT (0U)
3760/*! BPALCD30
3761 * 0b0..LCD segment off or LCD backplane inactive for phase A
3762 * 0b1..LCD segment on or LCD backplane active for phase A
3763 */
3764#define LCD_WF8B_BPALCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD30_SHIFT)) & LCD_WF8B_BPALCD30_MASK)
3765#define LCD_WF8B_BPALCD31_MASK (0x1U)
3766#define LCD_WF8B_BPALCD31_SHIFT (0U)
3767/*! BPALCD31
3768 * 0b0..LCD segment off or LCD backplane inactive for phase A
3769 * 0b1..LCD segment on or LCD backplane active for phase A
3770 */
3771#define LCD_WF8B_BPALCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD31_SHIFT)) & LCD_WF8B_BPALCD31_MASK)
3772#define LCD_WF8B_BPALCD32_MASK (0x1U)
3773#define LCD_WF8B_BPALCD32_SHIFT (0U)
3774/*! BPALCD32
3775 * 0b0..LCD segment off or LCD backplane inactive for phase A
3776 * 0b1..LCD segment on or LCD backplane active for phase A
3777 */
3778#define LCD_WF8B_BPALCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD32_SHIFT)) & LCD_WF8B_BPALCD32_MASK)
3779#define LCD_WF8B_BPALCD33_MASK (0x1U)
3780#define LCD_WF8B_BPALCD33_SHIFT (0U)
3781/*! BPALCD33
3782 * 0b0..LCD segment off or LCD backplane inactive for phase A
3783 * 0b1..LCD segment on or LCD backplane active for phase A
3784 */
3785#define LCD_WF8B_BPALCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD33_SHIFT)) & LCD_WF8B_BPALCD33_MASK)
3786#define LCD_WF8B_BPALCD34_MASK (0x1U)
3787#define LCD_WF8B_BPALCD34_SHIFT (0U)
3788/*! BPALCD34
3789 * 0b0..LCD segment off or LCD backplane inactive for phase A
3790 * 0b1..LCD segment on or LCD backplane active for phase A
3791 */
3792#define LCD_WF8B_BPALCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD34_SHIFT)) & LCD_WF8B_BPALCD34_MASK)
3793#define LCD_WF8B_BPALCD35_MASK (0x1U)
3794#define LCD_WF8B_BPALCD35_SHIFT (0U)
3795/*! BPALCD35
3796 * 0b0..LCD segment off or LCD backplane inactive for phase A
3797 * 0b1..LCD segment on or LCD backplane active for phase A
3798 */
3799#define LCD_WF8B_BPALCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD35_SHIFT)) & LCD_WF8B_BPALCD35_MASK)
3800#define LCD_WF8B_BPALCD36_MASK (0x1U)
3801#define LCD_WF8B_BPALCD36_SHIFT (0U)
3802/*! BPALCD36
3803 * 0b0..LCD segment off or LCD backplane inactive for phase A
3804 * 0b1..LCD segment on or LCD backplane active for phase A
3805 */
3806#define LCD_WF8B_BPALCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD36_SHIFT)) & LCD_WF8B_BPALCD36_MASK)
3807#define LCD_WF8B_BPALCD37_MASK (0x1U)
3808#define LCD_WF8B_BPALCD37_SHIFT (0U)
3809/*! BPALCD37
3810 * 0b0..LCD segment off or LCD backplane inactive for phase A
3811 * 0b1..LCD segment on or LCD backplane active for phase A
3812 */
3813#define LCD_WF8B_BPALCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD37_SHIFT)) & LCD_WF8B_BPALCD37_MASK)
3814#define LCD_WF8B_BPALCD38_MASK (0x1U)
3815#define LCD_WF8B_BPALCD38_SHIFT (0U)
3816/*! BPALCD38
3817 * 0b0..LCD segment off or LCD backplane inactive for phase A
3818 * 0b1..LCD segment on or LCD backplane active for phase A
3819 */
3820#define LCD_WF8B_BPALCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD38_SHIFT)) & LCD_WF8B_BPALCD38_MASK)
3821#define LCD_WF8B_BPALCD39_MASK (0x1U)
3822#define LCD_WF8B_BPALCD39_SHIFT (0U)
3823/*! BPALCD39
3824 * 0b0..LCD segment off or LCD backplane inactive for phase A
3825 * 0b1..LCD segment on or LCD backplane active for phase A
3826 */
3827#define LCD_WF8B_BPALCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD39_SHIFT)) & LCD_WF8B_BPALCD39_MASK)
3828#define LCD_WF8B_BPALCD40_MASK (0x1U)
3829#define LCD_WF8B_BPALCD40_SHIFT (0U)
3830/*! BPALCD40
3831 * 0b0..LCD segment off or LCD backplane inactive for phase A
3832 * 0b1..LCD segment on or LCD backplane active for phase A
3833 */
3834#define LCD_WF8B_BPALCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD40_SHIFT)) & LCD_WF8B_BPALCD40_MASK)
3835#define LCD_WF8B_BPALCD41_MASK (0x1U)
3836#define LCD_WF8B_BPALCD41_SHIFT (0U)
3837/*! BPALCD41
3838 * 0b0..LCD segment off or LCD backplane inactive for phase A
3839 * 0b1..LCD segment on or LCD backplane active for phase A
3840 */
3841#define LCD_WF8B_BPALCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD41_SHIFT)) & LCD_WF8B_BPALCD41_MASK)
3842#define LCD_WF8B_BPALCD42_MASK (0x1U)
3843#define LCD_WF8B_BPALCD42_SHIFT (0U)
3844/*! BPALCD42
3845 * 0b0..LCD segment off or LCD backplane inactive for phase A
3846 * 0b1..LCD segment on or LCD backplane active for phase A
3847 */
3848#define LCD_WF8B_BPALCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD42_SHIFT)) & LCD_WF8B_BPALCD42_MASK)
3849#define LCD_WF8B_BPALCD43_MASK (0x1U)
3850#define LCD_WF8B_BPALCD43_SHIFT (0U)
3851/*! BPALCD43
3852 * 0b0..LCD segment off or LCD backplane inactive for phase A
3853 * 0b1..LCD segment on or LCD backplane active for phase A
3854 */
3855#define LCD_WF8B_BPALCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD43_SHIFT)) & LCD_WF8B_BPALCD43_MASK)
3856#define LCD_WF8B_BPALCD44_MASK (0x1U)
3857#define LCD_WF8B_BPALCD44_SHIFT (0U)
3858/*! BPALCD44
3859 * 0b0..LCD segment off or LCD backplane inactive for phase A
3860 * 0b1..LCD segment on or LCD backplane active for phase A
3861 */
3862#define LCD_WF8B_BPALCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD44_SHIFT)) & LCD_WF8B_BPALCD44_MASK)
3863#define LCD_WF8B_BPALCD45_MASK (0x1U)
3864#define LCD_WF8B_BPALCD45_SHIFT (0U)
3865/*! BPALCD45
3866 * 0b0..LCD segment off or LCD backplane inactive for phase A
3867 * 0b1..LCD segment on or LCD backplane active for phase A
3868 */
3869#define LCD_WF8B_BPALCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD45_SHIFT)) & LCD_WF8B_BPALCD45_MASK)
3870#define LCD_WF8B_BPALCD46_MASK (0x1U)
3871#define LCD_WF8B_BPALCD46_SHIFT (0U)
3872/*! BPALCD46
3873 * 0b0..LCD segment off or LCD backplane inactive for phase A
3874 * 0b1..LCD segment on or LCD backplane active for phase A
3875 */
3876#define LCD_WF8B_BPALCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD46_SHIFT)) & LCD_WF8B_BPALCD46_MASK)
3877#define LCD_WF8B_BPALCD47_MASK (0x1U)
3878#define LCD_WF8B_BPALCD47_SHIFT (0U)
3879/*! BPALCD47
3880 * 0b0..LCD segment off or LCD backplane inactive for phase A
3881 * 0b1..LCD segment on or LCD backplane active for phase A
3882 */
3883#define LCD_WF8B_BPALCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD47_SHIFT)) & LCD_WF8B_BPALCD47_MASK)
3884#define LCD_WF8B_BPALCD48_MASK (0x1U)
3885#define LCD_WF8B_BPALCD48_SHIFT (0U)
3886/*! BPALCD48
3887 * 0b0..LCD segment off or LCD backplane inactive for phase A
3888 * 0b1..LCD segment on or LCD backplane active for phase A
3889 */
3890#define LCD_WF8B_BPALCD48(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD48_SHIFT)) & LCD_WF8B_BPALCD48_MASK)
3891#define LCD_WF8B_BPALCD49_MASK (0x1U)
3892#define LCD_WF8B_BPALCD49_SHIFT (0U)
3893/*! BPALCD49
3894 * 0b0..LCD segment off or LCD backplane inactive for phase A
3895 * 0b1..LCD segment on or LCD backplane active for phase A
3896 */
3897#define LCD_WF8B_BPALCD49(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD49_SHIFT)) & LCD_WF8B_BPALCD49_MASK)
3898#define LCD_WF8B_BPALCD50_MASK (0x1U)
3899#define LCD_WF8B_BPALCD50_SHIFT (0U)
3900/*! BPALCD50
3901 * 0b0..LCD segment off or LCD backplane inactive for phase A
3902 * 0b1..LCD segment on or LCD backplane active for phase A
3903 */
3904#define LCD_WF8B_BPALCD50(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD50_SHIFT)) & LCD_WF8B_BPALCD50_MASK)
3905#define LCD_WF8B_BPALCD51_MASK (0x1U)
3906#define LCD_WF8B_BPALCD51_SHIFT (0U)
3907/*! BPALCD51
3908 * 0b0..LCD segment off or LCD backplane inactive for phase A
3909 * 0b1..LCD segment on or LCD backplane active for phase A
3910 */
3911#define LCD_WF8B_BPALCD51(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD51_SHIFT)) & LCD_WF8B_BPALCD51_MASK)
3912#define LCD_WF8B_BPALCD52_MASK (0x1U)
3913#define LCD_WF8B_BPALCD52_SHIFT (0U)
3914/*! BPALCD52
3915 * 0b0..LCD segment off or LCD backplane inactive for phase A
3916 * 0b1..LCD segment on or LCD backplane active for phase A
3917 */
3918#define LCD_WF8B_BPALCD52(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD52_SHIFT)) & LCD_WF8B_BPALCD52_MASK)
3919#define LCD_WF8B_BPALCD53_MASK (0x1U)
3920#define LCD_WF8B_BPALCD53_SHIFT (0U)
3921/*! BPALCD53
3922 * 0b0..LCD segment off or LCD backplane inactive for phase A
3923 * 0b1..LCD segment on or LCD backplane active for phase A
3924 */
3925#define LCD_WF8B_BPALCD53(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD53_SHIFT)) & LCD_WF8B_BPALCD53_MASK)
3926#define LCD_WF8B_BPALCD54_MASK (0x1U)
3927#define LCD_WF8B_BPALCD54_SHIFT (0U)
3928/*! BPALCD54
3929 * 0b0..LCD segment off or LCD backplane inactive for phase A
3930 * 0b1..LCD segment on or LCD backplane active for phase A
3931 */
3932#define LCD_WF8B_BPALCD54(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD54_SHIFT)) & LCD_WF8B_BPALCD54_MASK)
3933#define LCD_WF8B_BPALCD55_MASK (0x1U)
3934#define LCD_WF8B_BPALCD55_SHIFT (0U)
3935/*! BPALCD55
3936 * 0b0..LCD segment off or LCD backplane inactive for phase A
3937 * 0b1..LCD segment on or LCD backplane active for phase A
3938 */
3939#define LCD_WF8B_BPALCD55(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD55_SHIFT)) & LCD_WF8B_BPALCD55_MASK)
3940#define LCD_WF8B_BPALCD56_MASK (0x1U)
3941#define LCD_WF8B_BPALCD56_SHIFT (0U)
3942/*! BPALCD56
3943 * 0b0..LCD segment off or LCD backplane inactive for phase A
3944 * 0b1..LCD segment on or LCD backplane active for phase A
3945 */
3946#define LCD_WF8B_BPALCD56(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD56_SHIFT)) & LCD_WF8B_BPALCD56_MASK)
3947#define LCD_WF8B_BPALCD57_MASK (0x1U)
3948#define LCD_WF8B_BPALCD57_SHIFT (0U)
3949/*! BPALCD57
3950 * 0b0..LCD segment off or LCD backplane inactive for phase A
3951 * 0b1..LCD segment on or LCD backplane active for phase A
3952 */
3953#define LCD_WF8B_BPALCD57(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD57_SHIFT)) & LCD_WF8B_BPALCD57_MASK)
3954#define LCD_WF8B_BPALCD58_MASK (0x1U)
3955#define LCD_WF8B_BPALCD58_SHIFT (0U)
3956/*! BPALCD58
3957 * 0b0..LCD segment off or LCD backplane inactive for phase A
3958 * 0b1..LCD segment on or LCD backplane active for phase A
3959 */
3960#define LCD_WF8B_BPALCD58(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD58_SHIFT)) & LCD_WF8B_BPALCD58_MASK)
3961#define LCD_WF8B_BPALCD59_MASK (0x1U)
3962#define LCD_WF8B_BPALCD59_SHIFT (0U)
3963/*! BPALCD59
3964 * 0b0..LCD segment off or LCD backplane inactive for phase A
3965 * 0b1..LCD segment on or LCD backplane active for phase A
3966 */
3967#define LCD_WF8B_BPALCD59(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD59_SHIFT)) & LCD_WF8B_BPALCD59_MASK)
3968#define LCD_WF8B_BPALCD60_MASK (0x1U)
3969#define LCD_WF8B_BPALCD60_SHIFT (0U)
3970/*! BPALCD60
3971 * 0b0..LCD segment off or LCD backplane inactive for phase A
3972 * 0b1..LCD segment on or LCD backplane active for phase A
3973 */
3974#define LCD_WF8B_BPALCD60(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD60_SHIFT)) & LCD_WF8B_BPALCD60_MASK)
3975#define LCD_WF8B_BPALCD61_MASK (0x1U)
3976#define LCD_WF8B_BPALCD61_SHIFT (0U)
3977/*! BPALCD61
3978 * 0b0..LCD segment off or LCD backplane inactive for phase A
3979 * 0b1..LCD segment on or LCD backplane active for phase A
3980 */
3981#define LCD_WF8B_BPALCD61(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD61_SHIFT)) & LCD_WF8B_BPALCD61_MASK)
3982#define LCD_WF8B_BPALCD62_MASK (0x1U)
3983#define LCD_WF8B_BPALCD62_SHIFT (0U)
3984/*! BPALCD62
3985 * 0b0..LCD segment off or LCD backplane inactive for phase A
3986 * 0b1..LCD segment on or LCD backplane active for phase A
3987 */
3988#define LCD_WF8B_BPALCD62(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD62_SHIFT)) & LCD_WF8B_BPALCD62_MASK)
3989#define LCD_WF8B_BPALCD63_MASK (0x1U)
3990#define LCD_WF8B_BPALCD63_SHIFT (0U)
3991/*! BPALCD63
3992 * 0b0..LCD segment off or LCD backplane inactive for phase A
3993 * 0b1..LCD segment on or LCD backplane active for phase A
3994 */
3995#define LCD_WF8B_BPALCD63(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPALCD63_SHIFT)) & LCD_WF8B_BPALCD63_MASK)
3996#define LCD_WF8B_BPBLCD0_MASK (0x2U)
3997#define LCD_WF8B_BPBLCD0_SHIFT (1U)
3998/*! BPBLCD0
3999 * 0b0..LCD segment off or LCD backplane inactive for phase B
4000 * 0b1..LCD segment on or LCD backplane active for phase B
4001 */
4002#define LCD_WF8B_BPBLCD0(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD0_SHIFT)) & LCD_WF8B_BPBLCD0_MASK)
4003#define LCD_WF8B_BPBLCD1_MASK (0x2U)
4004#define LCD_WF8B_BPBLCD1_SHIFT (1U)
4005/*! BPBLCD1
4006 * 0b0..LCD segment off or LCD backplane inactive for phase B
4007 * 0b1..LCD segment on or LCD backplane active for phase B
4008 */
4009#define LCD_WF8B_BPBLCD1(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD1_SHIFT)) & LCD_WF8B_BPBLCD1_MASK)
4010#define LCD_WF8B_BPBLCD2_MASK (0x2U)
4011#define LCD_WF8B_BPBLCD2_SHIFT (1U)
4012/*! BPBLCD2
4013 * 0b0..LCD segment off or LCD backplane inactive for phase B
4014 * 0b1..LCD segment on or LCD backplane active for phase B
4015 */
4016#define LCD_WF8B_BPBLCD2(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD2_SHIFT)) & LCD_WF8B_BPBLCD2_MASK)
4017#define LCD_WF8B_BPBLCD3_MASK (0x2U)
4018#define LCD_WF8B_BPBLCD3_SHIFT (1U)
4019/*! BPBLCD3
4020 * 0b0..LCD segment off or LCD backplane inactive for phase B
4021 * 0b1..LCD segment on or LCD backplane active for phase B
4022 */
4023#define LCD_WF8B_BPBLCD3(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD3_SHIFT)) & LCD_WF8B_BPBLCD3_MASK)
4024#define LCD_WF8B_BPBLCD4_MASK (0x2U)
4025#define LCD_WF8B_BPBLCD4_SHIFT (1U)
4026/*! BPBLCD4
4027 * 0b0..LCD segment off or LCD backplane inactive for phase B
4028 * 0b1..LCD segment on or LCD backplane active for phase B
4029 */
4030#define LCD_WF8B_BPBLCD4(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD4_SHIFT)) & LCD_WF8B_BPBLCD4_MASK)
4031#define LCD_WF8B_BPBLCD5_MASK (0x2U)
4032#define LCD_WF8B_BPBLCD5_SHIFT (1U)
4033/*! BPBLCD5
4034 * 0b0..LCD segment off or LCD backplane inactive for phase B
4035 * 0b1..LCD segment on or LCD backplane active for phase B
4036 */
4037#define LCD_WF8B_BPBLCD5(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD5_SHIFT)) & LCD_WF8B_BPBLCD5_MASK)
4038#define LCD_WF8B_BPBLCD6_MASK (0x2U)
4039#define LCD_WF8B_BPBLCD6_SHIFT (1U)
4040/*! BPBLCD6
4041 * 0b0..LCD segment off or LCD backplane inactive for phase B
4042 * 0b1..LCD segment on or LCD backplane active for phase B
4043 */
4044#define LCD_WF8B_BPBLCD6(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD6_SHIFT)) & LCD_WF8B_BPBLCD6_MASK)
4045#define LCD_WF8B_BPBLCD7_MASK (0x2U)
4046#define LCD_WF8B_BPBLCD7_SHIFT (1U)
4047/*! BPBLCD7
4048 * 0b0..LCD segment off or LCD backplane inactive for phase B
4049 * 0b1..LCD segment on or LCD backplane active for phase B
4050 */
4051#define LCD_WF8B_BPBLCD7(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD7_SHIFT)) & LCD_WF8B_BPBLCD7_MASK)
4052#define LCD_WF8B_BPBLCD8_MASK (0x2U)
4053#define LCD_WF8B_BPBLCD8_SHIFT (1U)
4054/*! BPBLCD8
4055 * 0b0..LCD segment off or LCD backplane inactive for phase B
4056 * 0b1..LCD segment on or LCD backplane active for phase B
4057 */
4058#define LCD_WF8B_BPBLCD8(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD8_SHIFT)) & LCD_WF8B_BPBLCD8_MASK)
4059#define LCD_WF8B_BPBLCD9_MASK (0x2U)
4060#define LCD_WF8B_BPBLCD9_SHIFT (1U)
4061/*! BPBLCD9
4062 * 0b0..LCD segment off or LCD backplane inactive for phase B
4063 * 0b1..LCD segment on or LCD backplane active for phase B
4064 */
4065#define LCD_WF8B_BPBLCD9(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD9_SHIFT)) & LCD_WF8B_BPBLCD9_MASK)
4066#define LCD_WF8B_BPBLCD10_MASK (0x2U)
4067#define LCD_WF8B_BPBLCD10_SHIFT (1U)
4068/*! BPBLCD10
4069 * 0b0..LCD segment off or LCD backplane inactive for phase B
4070 * 0b1..LCD segment on or LCD backplane active for phase B
4071 */
4072#define LCD_WF8B_BPBLCD10(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD10_SHIFT)) & LCD_WF8B_BPBLCD10_MASK)
4073#define LCD_WF8B_BPBLCD11_MASK (0x2U)
4074#define LCD_WF8B_BPBLCD11_SHIFT (1U)
4075/*! BPBLCD11
4076 * 0b0..LCD segment off or LCD backplane inactive for phase B
4077 * 0b1..LCD segment on or LCD backplane active for phase B
4078 */
4079#define LCD_WF8B_BPBLCD11(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD11_SHIFT)) & LCD_WF8B_BPBLCD11_MASK)
4080#define LCD_WF8B_BPBLCD12_MASK (0x2U)
4081#define LCD_WF8B_BPBLCD12_SHIFT (1U)
4082/*! BPBLCD12
4083 * 0b0..LCD segment off or LCD backplane inactive for phase B
4084 * 0b1..LCD segment on or LCD backplane active for phase B
4085 */
4086#define LCD_WF8B_BPBLCD12(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD12_SHIFT)) & LCD_WF8B_BPBLCD12_MASK)
4087#define LCD_WF8B_BPBLCD13_MASK (0x2U)
4088#define LCD_WF8B_BPBLCD13_SHIFT (1U)
4089/*! BPBLCD13
4090 * 0b0..LCD segment off or LCD backplane inactive for phase B
4091 * 0b1..LCD segment on or LCD backplane active for phase B
4092 */
4093#define LCD_WF8B_BPBLCD13(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD13_SHIFT)) & LCD_WF8B_BPBLCD13_MASK)
4094#define LCD_WF8B_BPBLCD14_MASK (0x2U)
4095#define LCD_WF8B_BPBLCD14_SHIFT (1U)
4096/*! BPBLCD14
4097 * 0b0..LCD segment off or LCD backplane inactive for phase B
4098 * 0b1..LCD segment on or LCD backplane active for phase B
4099 */
4100#define LCD_WF8B_BPBLCD14(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD14_SHIFT)) & LCD_WF8B_BPBLCD14_MASK)
4101#define LCD_WF8B_BPBLCD15_MASK (0x2U)
4102#define LCD_WF8B_BPBLCD15_SHIFT (1U)
4103/*! BPBLCD15
4104 * 0b0..LCD segment off or LCD backplane inactive for phase B
4105 * 0b1..LCD segment on or LCD backplane active for phase B
4106 */
4107#define LCD_WF8B_BPBLCD15(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD15_SHIFT)) & LCD_WF8B_BPBLCD15_MASK)
4108#define LCD_WF8B_BPBLCD16_MASK (0x2U)
4109#define LCD_WF8B_BPBLCD16_SHIFT (1U)
4110/*! BPBLCD16
4111 * 0b0..LCD segment off or LCD backplane inactive for phase B
4112 * 0b1..LCD segment on or LCD backplane active for phase B
4113 */
4114#define LCD_WF8B_BPBLCD16(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD16_SHIFT)) & LCD_WF8B_BPBLCD16_MASK)
4115#define LCD_WF8B_BPBLCD17_MASK (0x2U)
4116#define LCD_WF8B_BPBLCD17_SHIFT (1U)
4117/*! BPBLCD17
4118 * 0b0..LCD segment off or LCD backplane inactive for phase B
4119 * 0b1..LCD segment on or LCD backplane active for phase B
4120 */
4121#define LCD_WF8B_BPBLCD17(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD17_SHIFT)) & LCD_WF8B_BPBLCD17_MASK)
4122#define LCD_WF8B_BPBLCD18_MASK (0x2U)
4123#define LCD_WF8B_BPBLCD18_SHIFT (1U)
4124/*! BPBLCD18
4125 * 0b0..LCD segment off or LCD backplane inactive for phase B
4126 * 0b1..LCD segment on or LCD backplane active for phase B
4127 */
4128#define LCD_WF8B_BPBLCD18(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD18_SHIFT)) & LCD_WF8B_BPBLCD18_MASK)
4129#define LCD_WF8B_BPBLCD19_MASK (0x2U)
4130#define LCD_WF8B_BPBLCD19_SHIFT (1U)
4131/*! BPBLCD19
4132 * 0b0..LCD segment off or LCD backplane inactive for phase B
4133 * 0b1..LCD segment on or LCD backplane active for phase B
4134 */
4135#define LCD_WF8B_BPBLCD19(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD19_SHIFT)) & LCD_WF8B_BPBLCD19_MASK)
4136#define LCD_WF8B_BPBLCD20_MASK (0x2U)
4137#define LCD_WF8B_BPBLCD20_SHIFT (1U)
4138/*! BPBLCD20
4139 * 0b0..LCD segment off or LCD backplane inactive for phase B
4140 * 0b1..LCD segment on or LCD backplane active for phase B
4141 */
4142#define LCD_WF8B_BPBLCD20(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD20_SHIFT)) & LCD_WF8B_BPBLCD20_MASK)
4143#define LCD_WF8B_BPBLCD21_MASK (0x2U)
4144#define LCD_WF8B_BPBLCD21_SHIFT (1U)
4145/*! BPBLCD21
4146 * 0b0..LCD segment off or LCD backplane inactive for phase B
4147 * 0b1..LCD segment on or LCD backplane active for phase B
4148 */
4149#define LCD_WF8B_BPBLCD21(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD21_SHIFT)) & LCD_WF8B_BPBLCD21_MASK)
4150#define LCD_WF8B_BPBLCD22_MASK (0x2U)
4151#define LCD_WF8B_BPBLCD22_SHIFT (1U)
4152/*! BPBLCD22
4153 * 0b0..LCD segment off or LCD backplane inactive for phase B
4154 * 0b1..LCD segment on or LCD backplane active for phase B
4155 */
4156#define LCD_WF8B_BPBLCD22(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD22_SHIFT)) & LCD_WF8B_BPBLCD22_MASK)
4157#define LCD_WF8B_BPBLCD23_MASK (0x2U)
4158#define LCD_WF8B_BPBLCD23_SHIFT (1U)
4159/*! BPBLCD23
4160 * 0b0..LCD segment off or LCD backplane inactive for phase B
4161 * 0b1..LCD segment on or LCD backplane active for phase B
4162 */
4163#define LCD_WF8B_BPBLCD23(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD23_SHIFT)) & LCD_WF8B_BPBLCD23_MASK)
4164#define LCD_WF8B_BPBLCD24_MASK (0x2U)
4165#define LCD_WF8B_BPBLCD24_SHIFT (1U)
4166/*! BPBLCD24
4167 * 0b0..LCD segment off or LCD backplane inactive for phase B
4168 * 0b1..LCD segment on or LCD backplane active for phase B
4169 */
4170#define LCD_WF8B_BPBLCD24(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD24_SHIFT)) & LCD_WF8B_BPBLCD24_MASK)
4171#define LCD_WF8B_BPBLCD25_MASK (0x2U)
4172#define LCD_WF8B_BPBLCD25_SHIFT (1U)
4173/*! BPBLCD25
4174 * 0b0..LCD segment off or LCD backplane inactive for phase B
4175 * 0b1..LCD segment on or LCD backplane active for phase B
4176 */
4177#define LCD_WF8B_BPBLCD25(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD25_SHIFT)) & LCD_WF8B_BPBLCD25_MASK)
4178#define LCD_WF8B_BPBLCD26_MASK (0x2U)
4179#define LCD_WF8B_BPBLCD26_SHIFT (1U)
4180/*! BPBLCD26
4181 * 0b0..LCD segment off or LCD backplane inactive for phase B
4182 * 0b1..LCD segment on or LCD backplane active for phase B
4183 */
4184#define LCD_WF8B_BPBLCD26(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD26_SHIFT)) & LCD_WF8B_BPBLCD26_MASK)
4185#define LCD_WF8B_BPBLCD27_MASK (0x2U)
4186#define LCD_WF8B_BPBLCD27_SHIFT (1U)
4187/*! BPBLCD27
4188 * 0b0..LCD segment off or LCD backplane inactive for phase B
4189 * 0b1..LCD segment on or LCD backplane active for phase B
4190 */
4191#define LCD_WF8B_BPBLCD27(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD27_SHIFT)) & LCD_WF8B_BPBLCD27_MASK)
4192#define LCD_WF8B_BPBLCD28_MASK (0x2U)
4193#define LCD_WF8B_BPBLCD28_SHIFT (1U)
4194/*! BPBLCD28
4195 * 0b0..LCD segment off or LCD backplane inactive for phase B
4196 * 0b1..LCD segment on or LCD backplane active for phase B
4197 */
4198#define LCD_WF8B_BPBLCD28(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD28_SHIFT)) & LCD_WF8B_BPBLCD28_MASK)
4199#define LCD_WF8B_BPBLCD29_MASK (0x2U)
4200#define LCD_WF8B_BPBLCD29_SHIFT (1U)
4201/*! BPBLCD29
4202 * 0b0..LCD segment off or LCD backplane inactive for phase B
4203 * 0b1..LCD segment on or LCD backplane active for phase B
4204 */
4205#define LCD_WF8B_BPBLCD29(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD29_SHIFT)) & LCD_WF8B_BPBLCD29_MASK)
4206#define LCD_WF8B_BPBLCD30_MASK (0x2U)
4207#define LCD_WF8B_BPBLCD30_SHIFT (1U)
4208/*! BPBLCD30
4209 * 0b0..LCD segment off or LCD backplane inactive for phase B
4210 * 0b1..LCD segment on or LCD backplane active for phase B
4211 */
4212#define LCD_WF8B_BPBLCD30(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD30_SHIFT)) & LCD_WF8B_BPBLCD30_MASK)
4213#define LCD_WF8B_BPBLCD31_MASK (0x2U)
4214#define LCD_WF8B_BPBLCD31_SHIFT (1U)
4215/*! BPBLCD31
4216 * 0b0..LCD segment off or LCD backplane inactive for phase B
4217 * 0b1..LCD segment on or LCD backplane active for phase B
4218 */
4219#define LCD_WF8B_BPBLCD31(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD31_SHIFT)) & LCD_WF8B_BPBLCD31_MASK)
4220#define LCD_WF8B_BPBLCD32_MASK (0x2U)
4221#define LCD_WF8B_BPBLCD32_SHIFT (1U)
4222/*! BPBLCD32
4223 * 0b0..LCD segment off or LCD backplane inactive for phase B
4224 * 0b1..LCD segment on or LCD backplane active for phase B
4225 */
4226#define LCD_WF8B_BPBLCD32(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD32_SHIFT)) & LCD_WF8B_BPBLCD32_MASK)
4227#define LCD_WF8B_BPBLCD33_MASK (0x2U)
4228#define LCD_WF8B_BPBLCD33_SHIFT (1U)
4229/*! BPBLCD33
4230 * 0b0..LCD segment off or LCD backplane inactive for phase B
4231 * 0b1..LCD segment on or LCD backplane active for phase B
4232 */
4233#define LCD_WF8B_BPBLCD33(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD33_SHIFT)) & LCD_WF8B_BPBLCD33_MASK)
4234#define LCD_WF8B_BPBLCD34_MASK (0x2U)
4235#define LCD_WF8B_BPBLCD34_SHIFT (1U)
4236/*! BPBLCD34
4237 * 0b0..LCD segment off or LCD backplane inactive for phase B
4238 * 0b1..LCD segment on or LCD backplane active for phase B
4239 */
4240#define LCD_WF8B_BPBLCD34(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD34_SHIFT)) & LCD_WF8B_BPBLCD34_MASK)
4241#define LCD_WF8B_BPBLCD35_MASK (0x2U)
4242#define LCD_WF8B_BPBLCD35_SHIFT (1U)
4243/*! BPBLCD35
4244 * 0b0..LCD segment off or LCD backplane inactive for phase B
4245 * 0b1..LCD segment on or LCD backplane active for phase B
4246 */
4247#define LCD_WF8B_BPBLCD35(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD35_SHIFT)) & LCD_WF8B_BPBLCD35_MASK)
4248#define LCD_WF8B_BPBLCD36_MASK (0x2U)
4249#define LCD_WF8B_BPBLCD36_SHIFT (1U)
4250/*! BPBLCD36
4251 * 0b0..LCD segment off or LCD backplane inactive for phase B
4252 * 0b1..LCD segment on or LCD backplane active for phase B
4253 */
4254#define LCD_WF8B_BPBLCD36(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD36_SHIFT)) & LCD_WF8B_BPBLCD36_MASK)
4255#define LCD_WF8B_BPBLCD37_MASK (0x2U)
4256#define LCD_WF8B_BPBLCD37_SHIFT (1U)
4257/*! BPBLCD37
4258 * 0b0..LCD segment off or LCD backplane inactive for phase B
4259 * 0b1..LCD segment on or LCD backplane active for phase B
4260 */
4261#define LCD_WF8B_BPBLCD37(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD37_SHIFT)) & LCD_WF8B_BPBLCD37_MASK)
4262#define LCD_WF8B_BPBLCD38_MASK (0x2U)
4263#define LCD_WF8B_BPBLCD38_SHIFT (1U)
4264/*! BPBLCD38
4265 * 0b0..LCD segment off or LCD backplane inactive for phase B
4266 * 0b1..LCD segment on or LCD backplane active for phase B
4267 */
4268#define LCD_WF8B_BPBLCD38(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD38_SHIFT)) & LCD_WF8B_BPBLCD38_MASK)
4269#define LCD_WF8B_BPBLCD39_MASK (0x2U)
4270#define LCD_WF8B_BPBLCD39_SHIFT (1U)
4271/*! BPBLCD39
4272 * 0b0..LCD segment off or LCD backplane inactive for phase B
4273 * 0b1..LCD segment on or LCD backplane active for phase B
4274 */
4275#define LCD_WF8B_BPBLCD39(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD39_SHIFT)) & LCD_WF8B_BPBLCD39_MASK)
4276#define LCD_WF8B_BPBLCD40_MASK (0x2U)
4277#define LCD_WF8B_BPBLCD40_SHIFT (1U)
4278/*! BPBLCD40
4279 * 0b0..LCD segment off or LCD backplane inactive for phase B
4280 * 0b1..LCD segment on or LCD backplane active for phase B
4281 */
4282#define LCD_WF8B_BPBLCD40(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD40_SHIFT)) & LCD_WF8B_BPBLCD40_MASK)
4283#define LCD_WF8B_BPBLCD41_MASK (0x2U)
4284#define LCD_WF8B_BPBLCD41_SHIFT (1U)
4285/*! BPBLCD41
4286 * 0b0..LCD segment off or LCD backplane inactive for phase B
4287 * 0b1..LCD segment on or LCD backplane active for phase B
4288 */
4289#define LCD_WF8B_BPBLCD41(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD41_SHIFT)) & LCD_WF8B_BPBLCD41_MASK)
4290#define LCD_WF8B_BPBLCD42_MASK (0x2U)
4291#define LCD_WF8B_BPBLCD42_SHIFT (1U)
4292/*! BPBLCD42
4293 * 0b0..LCD segment off or LCD backplane inactive for phase B
4294 * 0b1..LCD segment on or LCD backplane active for phase B
4295 */
4296#define LCD_WF8B_BPBLCD42(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD42_SHIFT)) & LCD_WF8B_BPBLCD42_MASK)
4297#define LCD_WF8B_BPBLCD43_MASK (0x2U)
4298#define LCD_WF8B_BPBLCD43_SHIFT (1U)
4299/*! BPBLCD43
4300 * 0b0..LCD segment off or LCD backplane inactive for phase B
4301 * 0b1..LCD segment on or LCD backplane active for phase B
4302 */
4303#define LCD_WF8B_BPBLCD43(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD43_SHIFT)) & LCD_WF8B_BPBLCD43_MASK)
4304#define LCD_WF8B_BPBLCD44_MASK (0x2U)
4305#define LCD_WF8B_BPBLCD44_SHIFT (1U)
4306/*! BPBLCD44
4307 * 0b0..LCD segment off or LCD backplane inactive for phase B
4308 * 0b1..LCD segment on or LCD backplane active for phase B
4309 */
4310#define LCD_WF8B_BPBLCD44(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD44_SHIFT)) & LCD_WF8B_BPBLCD44_MASK)
4311#define LCD_WF8B_BPBLCD45_MASK (0x2U)
4312#define LCD_WF8B_BPBLCD45_SHIFT (1U)
4313/*! BPBLCD45
4314 * 0b0..LCD segment off or LCD backplane inactive for phase B
4315 * 0b1..LCD segment on or LCD backplane active for phase B
4316 */
4317#define LCD_WF8B_BPBLCD45(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD45_SHIFT)) & LCD_WF8B_BPBLCD45_MASK)
4318#define LCD_WF8B_BPBLCD46_MASK (0x2U)
4319#define LCD_WF8B_BPBLCD46_SHIFT (1U)
4320/*! BPBLCD46
4321 * 0b0..LCD segment off or LCD backplane inactive for phase B
4322 * 0b1..LCD segment on or LCD backplane active for phase B
4323 */
4324#define LCD_WF8B_BPBLCD46(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD46_SHIFT)) & LCD_WF8B_BPBLCD46_MASK)
4325#define LCD_WF8B_BPBLCD47_MASK (0x2U)
4326#define LCD_WF8B_BPBLCD47_SHIFT (1U)
4327/*! BPBLCD47
4328 * 0b0..LCD segment off or LCD backplane inactive for phase B
4329 * 0b1..LCD segment on or LCD backplane active for phase B
4330 */
4331#define LCD_WF8B_BPBLCD47(x) (((uint8_t)(((uint8_t)(x)) << LCD_WF8B_BPBLCD47_SHIFT)) & LCD_WF8B_BPBLCD47_MASK)
4332#define LCD_WF8B_BPBLCD48_MASK (0x2U)
4333#define LCD_WF8B_BPBLCD48_SHIFT (1U)