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1/*
2** ###################################################################
3** Processors: LPC54018J2MET180
4** LPC54018J4MET180
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC54018JxM/LPC54S018JxM User manual Rev.1.0 20 September 2018
12** Version: rev. 1.2, 2017-06-08
13** Build: b200304
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for LPC54018M
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-08-12)
29** Initial version.
30** - rev. 1.1 (2016-11-25)
31** Update CANFD and Classic CAN register.
32** Add MAC TIMERSTAMP registers.
33** - rev. 1.2 (2017-06-08)
34** Remove RTC_CTRL_RTC_OSC_BYPASS.
35** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
36** Remove RESET and HALT from SYSCON_AHBCLKDIV.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file LPC54018M.h
43 * @version 1.2
44 * @date 2017-06-08
45 * @brief CMSIS Peripheral Access Layer for LPC54018M
46 *
47 * CMSIS Peripheral Access Layer for LPC54018M
48 */
49
50#ifndef _LPC54018M_H_
51#define _LPC54018M_H_ /**< Symbol preventing repeated inclusion */
52
53/** Memory map major version (memory maps with equal major version number are
54 * compatible) */
55#define MCU_MEM_MAP_VERSION 0x0100U
56/** Memory map minor version */
57#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
58
59
60/* ----------------------------------------------------------------------------
61 -- Interrupt vector numbers
62 ---------------------------------------------------------------------------- */
63
64/*!
65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
66 * @{
67 */
68
69/** Interrupt Number Definitions */
70#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
71
72typedef enum IRQn {
73 /* Auxiliary constants */
74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
75
76 /* Core interrupts */
77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
78 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
79 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
80 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
81 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
82 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
83 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
84 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
85 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
86
87 /* Device specific interrupts */
88 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
89 DMA0_IRQn = 1, /**< DMA controller */
90 GINT0_IRQn = 2, /**< GPIO group 0 */
91 GINT1_IRQn = 3, /**< GPIO group 1 */
92 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
93 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
94 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
95 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
96 UTICK0_IRQn = 8, /**< Micro-tick Timer */
97 MRT0_IRQn = 9, /**< Multi-rate timer */
98 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
99 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
100 SCT0_IRQn = 12, /**< SCTimer/PWM */
101 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
102 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
103 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
104 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
105 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
106 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
107 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
108 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
109 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
110 ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
111 ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
112 ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
113 DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
114 HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
115 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
116 USB0_IRQn = 28, /**< USB device */
117 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
118 FLEXCOMM10_IRQn = 30, /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
119 Reserved47_IRQn = 31, /**< Reserved interrupt */
120 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
121 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
122 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
123 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
124 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
125 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
126 RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
127 SPIFI0_IRQn = 39, /**< SPI flash interface */
128 FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
129 FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
130 SDIO_IRQn = 42, /**< SD/MMC */
131 CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
132 CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
133 CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
134 CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
135 USB1_IRQn = 47, /**< USB1 interrupt */
136 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
137 ETHERNET_IRQn = 49, /**< Ethernet */
138 ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
139 ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
140 Reserved68_IRQn = 52, /**< Reserved interrupt */
141 LCD_IRQn = 53, /**< LCD interrupt */
142 SHA_IRQn = 54, /**< SHA interrupt */
143 SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
144 SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M4 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165
166#include "core_cm4.h" /* Core Peripheral Access Layer */
167#include "system_LPC54018M.h" /* Device specific configuration file */
168
169/*!
170 * @}
171 */ /* end of group Cortex_Core_Configuration */
172
173
174/* ----------------------------------------------------------------------------
175 -- Mapping Information
176 ---------------------------------------------------------------------------- */
177
178/*!
179 * @addtogroup Mapping_Information Mapping Information
180 * @{
181 */
182
183/** Mapping Information */
184/*!
185 * @addtogroup dma_request
186 * @{
187 */
188
189/*******************************************************************************
190 * Definitions
191 ******************************************************************************/
192
193/*!
194 * @brief Structure for the DMA hardware request
195 *
196 * Defines the structure for the DMA hardware request collections. The user can configure the
197 * hardware request to trigger the DMA transfer accordingly. The index
198 * of the hardware request varies according to the to SoC.
199 */
200typedef enum _dma_request_source
201{
202 kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */
203 kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */
204 kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */
205 kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */
206 kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */
207 kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */
208 kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */
209 kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */
210 kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */
211 kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */
212 kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */
213 kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */
214 kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */
215 kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */
216 kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */
217 kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */
218 kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */
219 kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */
220 kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */
221 kDmaRequestSHA = 19U, /**< Secure Hash Algorithm */
222 kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */
223 kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */
224 kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */
225 kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */
226 kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */
227 kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */
228 kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */
229 kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */
230 kDmaRequestFlexcomm10Rx = 28U, /**< Flexcomm Interface 10 RX */
231 kDmaRequestFlexcomm10Tx = 29U, /**< Flexcomm Interface 10 TX */
232} dma_request_source_t;
233
234/* @} */
235
236
237/*!
238 * @}
239 */ /* end of group Mapping_Information */
240
241
242/* ----------------------------------------------------------------------------
243 -- Device Peripheral Access Layer
244 ---------------------------------------------------------------------------- */
245
246/*!
247 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
248 * @{
249 */
250
251
252/*
253** Start of section using anonymous unions
254*/
255
256#if defined(__ARMCC_VERSION)
257 #if (__ARMCC_VERSION >= 6010050)
258 #pragma clang diagnostic push
259 #else
260 #pragma push
261 #pragma anon_unions
262 #endif
263#elif defined(__GNUC__)
264 /* anonymous unions are enabled by default */
265#elif defined(__IAR_SYSTEMS_ICC__)
266 #pragma language=extended
267#else
268 #error Not supported compiler type
269#endif
270
271/* ----------------------------------------------------------------------------
272 -- ADC Peripheral Access Layer
273 ---------------------------------------------------------------------------- */
274
275/*!
276 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
277 * @{
278 */
279
280/** ADC - Register Layout Typedef */
281typedef struct {
282 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
283 __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
284 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
285 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
286 uint8_t RESERVED_0[8];
287 __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
288 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
289 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
290 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
291 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
292 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
293 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
294 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
295 __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
296 __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
297} ADC_Type;
298
299/* ----------------------------------------------------------------------------
300 -- ADC Register Masks
301 ---------------------------------------------------------------------------- */
302
303/*!
304 * @addtogroup ADC_Register_Masks ADC Register Masks
305 * @{
306 */
307
308/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
309/*! @{ */
310#define ADC_CTRL_CLKDIV_MASK (0xFFU)
311#define ADC_CTRL_CLKDIV_SHIFT (0U)
312/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
313 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
314 * software should program the smallest value in this field that yields this maximum clock rate or
315 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
316 * be desirable. This field is ignored in the asynchronous operating mode.
317 */
318#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
319#define ADC_CTRL_ASYNMODE_MASK (0x100U)
320#define ADC_CTRL_ASYNMODE_SHIFT (8U)
321/*! ASYNMODE - Select clock mode.
322 * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
323 * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
324 * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
325 * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
326 * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
327 * pulse.
328 * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
329 */
330#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
331#define ADC_CTRL_RESOL_MASK (0x600U)
332#define ADC_CTRL_RESOL_SHIFT (9U)
333/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
334 * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
335 * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
336 * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
337 * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
338 * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
339 * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
340 * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
341 * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
342 * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
343 * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
344 */
345#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
346#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
347#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
348/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
349 * error is not a concern in the application.
350 * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
351 * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
352 * be warranted periodically - especially if operating conditions have changed.
353 * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
354 * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
355 */
356#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
357#define ADC_CTRL_TSAMP_MASK (0x7000U)
358#define ADC_CTRL_TSAMP_SHIFT (12U)
359/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
360 * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
361 * and the output impedance of the analog source, longer sampling times may be required. See
362 * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
363 * seven, by which the sample period will be extended. The total conversion time will increase by
364 * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
365 * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
366 * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
367 * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
368 * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
369 * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
370 * 22 ADC clocks.
371 */
372#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
373/*! @} */
374
375/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
376/*! @{ */
377#define ADC_INSEL_SEL_MASK (0x3U)
378#define ADC_INSEL_SEL_SHIFT (0U)
379/*! SEL - Selects the input source for channel 0. All other values are reserved.
380 * 0b00..ADC0_IN0 function.
381 * 0b11..Internal temperature sensor.
382 */
383#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
384/*! @} */
385
386/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
387/*! @{ */
388#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
389#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
390/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
391 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
392 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
393 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
394 * software command, ADC conversions will be performed on each enabled channel, in sequence,
395 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
396 * is LOW. It is allowed to change this field and set bit 31 in the same write.
397 */
398#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
399#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
400#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
401/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
402 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
403 * to avoid generating a spurious trigger, it is recommended writing to this field only when
404 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
405 */
406#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
407#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
408#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
409/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
410 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
411 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
412 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
413 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
414 */
415#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
416#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
417#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
418/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
419 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
420 * conversion. There are slightly different criteria for whether or not this bit can be set
421 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
422 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
423 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
424 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
425 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
426 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
427 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
428 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
429 * maintained for one system clock period.
430 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
431 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
432 */
433#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
434#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
435#define ADC_SEQ_CTRL_START_SHIFT (26U)
436/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
437 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
438 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
439 * conversion sequence. It will consequently always read back as a zero.
440 */
441#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
442#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
443#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
444/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
445 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
446 * can be halted by clearing this bit. The sequence currently in progress will be completed before
447 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
448 */
449#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
450#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
451#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
452/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
453 * single conversion on the next channel in the sequence instead of the default response of
454 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
455 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
456 * channel. Interrupt generation will still occur either after each individual conversion or at
457 * the end of the entire sequence, depending on the state of the MODE bit.
458 */
459#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
460#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
461#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
462/*! LOWPRIO - Set priority for sequence A.
463 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
464 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
465 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
466 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
467 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
468 * conversion sequence will resume from that point.
469 */
470#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
471#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
472#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
473/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
474 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
475 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
476 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
477 * overrun conditions contribute to an overrun interrupt as described below.
478 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
479 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
480 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
481 * if enabled.
482 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
483 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
484 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
485 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
486 */
487#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
488#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
489#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
490/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
491 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
492 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
493 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
494 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
495 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
496 * triggered immediately upon being enabled.
497 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
498 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
499 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
500 * 0b1..Enabled. Sequence n is enabled.
501 */
502#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
503/*! @} */
504
505/* The count of ADC_SEQ_CTRL */
506#define ADC_SEQ_CTRL_COUNT (2U)
507
508/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
509/*! @{ */
510#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
511#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
512/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
513 * performed under conversion sequence associated with this register. The result is a binary
514 * fraction representing the voltage on the currently-selected input channel as it falls within the
515 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
516 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
517 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
518 * result has not yet been read.
519 */
520#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
521#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
522#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
523/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
524 * within the range established by the designated threshold comparison registers (THRn_LOW and
525 * THRn_HIGH).
526 */
527#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
528#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
529#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
530/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
531 * crossing of the threshold level established by the designated LOW threshold comparison register
532 * (THRn_LOW) and, if so, in what direction the crossing occurred.
533 */
534#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
535#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
536#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
537/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
538 * identifies channel 0, 0001 channel 1, etc.).
539 */
540#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
541#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
542#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
543/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
544 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
545 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
546 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
547 * to '0' (and if the overrun interrupt is enabled).
548 */
549#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
550#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
551#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
552/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
553 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
554 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
555 * sequence is set to 0 (and if the interrupt is enabled).
556 */
557#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
558/*! @} */
559
560/* The count of ADC_SEQ_GDAT */
561#define ADC_SEQ_GDAT_COUNT (2U)
562
563/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
564/*! @{ */
565#define ADC_DAT_RESULT_MASK (0xFFF0U)
566#define ADC_DAT_RESULT_SHIFT (4U)
567/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
568 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
569 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
570 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
571 * the voltage on the input was close to, equal to, or greater than that on VREFP.
572 */
573#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
574#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
575#define ADC_DAT_THCMPRANGE_SHIFT (16U)
576/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
577 * was greater than or equal to the value programmed into the designated LOW threshold register
578 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
579 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
580 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
581 * completed conversion was greater than the value programmed into the designated HIGH threshold
582 * register (THRn_HIGH). 0x3 = Reserved.
583 */
584#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
585#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
586#define ADC_DAT_THCMPCROSS_SHIFT (18U)
587/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
588 * most recent completed conversion on this channel had the same relationship (above or below) to
589 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
590 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
591 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
592 * previous sample on this channel was above the threshold value established by the designated LOW
593 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
594 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
595 * - i.e. the previous sample on this channel was below the threshold value established by the
596 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
597 */
598#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
599#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
600#define ADC_DAT_CHANNEL_SHIFT (26U)
601/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
602 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
603 * register, etc)
604 */
605#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
606#define ADC_DAT_OVERRUN_MASK (0x40000000U)
607#define ADC_DAT_OVERRUN_SHIFT (30U)
608/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
609 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
610 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
611 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
612 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
613 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
614 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
615 * data registers associated with any of the channels that are shared between the two sequences. Any
616 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
617 */
618#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
619#define ADC_DAT_DATAVALID_MASK (0x80000000U)
620#define ADC_DAT_DATAVALID_SHIFT (31U)
621/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
622 * cleared whenever this register is read or when the data related to this channel is read from
623 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
624 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
625 * the data registers associated with any of the channels that are shared between the two
626 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
627 */
628#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
629/*! @} */
630
631/* The count of ADC_DAT */
632#define ADC_DAT_COUNT (12U)
633
634/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
635/*! @{ */
636#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
637#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
638/*! THRLOW - Low threshold value against which ADC results will be compared
639 */
640#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
641/*! @} */
642
643/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
644/*! @{ */
645#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
646#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
647/*! THRLOW - Low threshold value against which ADC results will be compared
648 */
649#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
650/*! @} */
651
652/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
653/*! @{ */
654#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
655#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
656/*! THRHIGH - High threshold value against which ADC results will be compared
657 */
658#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
659/*! @} */
660
661/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
662/*! @{ */
663#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
664#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
665/*! THRHIGH - High threshold value against which ADC results will be compared
666 */
667#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
668/*! @} */
669
670/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
671/*! @{ */
672#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
673#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
674/*! CH0_THRSEL - Threshold select for channel 0.
675 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
676 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
677 */
678#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
679#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
680#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
681/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
682 */
683#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
684#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
685#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
686/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
687 */
688#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
689#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
690#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
691/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
692 */
693#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
694#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
695#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
696/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
697 */
698#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
699#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
700#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
701/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
702 */
703#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
704#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
705#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
706/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
707 */
708#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
709#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
710#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
711/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
712 */
713#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
714#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
715#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
716/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
717 */
718#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
719#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
720#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
721/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
722 */
723#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
724#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
725#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
726/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
727 */
728#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
729#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
730#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
731/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
732 */
733#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
734/*! @} */
735
736/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
737/*! @{ */
738#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
739#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
740/*! SEQA_INTEN - Sequence A interrupt enable.
741 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
742 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
743 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
744 * conversions, depending on the MODE bit in the SEQA_CTRL register.
745 */
746#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
747#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
748#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
749/*! SEQB_INTEN - Sequence B interrupt enable.
750 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
751 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
752 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
753 * conversions, depending on the MODE bit in the SEQB_CTRL register.
754 */
755#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
756#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
757#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
758/*! OVR_INTEN - Overrun interrupt enable.
759 * 0b0..Disabled. The overrun interrupt is disabled.
760 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
761 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
762 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
763 * interrupt/DMA trigger to be asserted.
764 */
765#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
766#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
767#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
768/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
769 * 0b00..Disabled.
770 * 0b01..Outside threshold.
771 * 0b10..Crossing threshold.
772 * 0b11..Reserved
773 */
774#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
775#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
776#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
777/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
778 */
779#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
780#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
781#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
782/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
783 */
784#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
785#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
786#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
787/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
788 */
789#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
790#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
791#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
792/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
793 */
794#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
795#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
796#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
797/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
798 */
799#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
800#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
801#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
802/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
803 */
804#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
805#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
806#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
807/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
808 */
809#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
810#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
811#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
812/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
813 */
814#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
815#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
816#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
817/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
818 */
819#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
820#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
821#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
822/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
823 */
824#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
825#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
826#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
827/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
828 */
829#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
830/*! @} */
831
832/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
833/*! @{ */
834#define ADC_FLAGS_THCMP0_MASK (0x1U)
835#define ADC_FLAGS_THCMP0_SHIFT (0U)
836/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
837 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
838 * writing a 1.
839 */
840#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
841#define ADC_FLAGS_THCMP1_MASK (0x2U)
842#define ADC_FLAGS_THCMP1_SHIFT (1U)
843/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
844 */
845#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
846#define ADC_FLAGS_THCMP2_MASK (0x4U)
847#define ADC_FLAGS_THCMP2_SHIFT (2U)
848/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
849 */
850#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
851#define ADC_FLAGS_THCMP3_MASK (0x8U)
852#define ADC_FLAGS_THCMP3_SHIFT (3U)
853/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
854 */
855#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
856#define ADC_FLAGS_THCMP4_MASK (0x10U)
857#define ADC_FLAGS_THCMP4_SHIFT (4U)
858/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
859 */
860#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
861#define ADC_FLAGS_THCMP5_MASK (0x20U)
862#define ADC_FLAGS_THCMP5_SHIFT (5U)
863/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
864 */
865#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
866#define ADC_FLAGS_THCMP6_MASK (0x40U)
867#define ADC_FLAGS_THCMP6_SHIFT (6U)
868/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
869 */
870#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
871#define ADC_FLAGS_THCMP7_MASK (0x80U)
872#define ADC_FLAGS_THCMP7_SHIFT (7U)
873/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
874 */
875#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
876#define ADC_FLAGS_THCMP8_MASK (0x100U)
877#define ADC_FLAGS_THCMP8_SHIFT (8U)
878/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
879 */
880#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
881#define ADC_FLAGS_THCMP9_MASK (0x200U)
882#define ADC_FLAGS_THCMP9_SHIFT (9U)
883/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
884 */
885#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
886#define ADC_FLAGS_THCMP10_MASK (0x400U)
887#define ADC_FLAGS_THCMP10_SHIFT (10U)
888/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
889 */
890#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
891#define ADC_FLAGS_THCMP11_MASK (0x800U)
892#define ADC_FLAGS_THCMP11_SHIFT (11U)
893/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
894 */
895#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
896#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
897#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
898/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
899 */
900#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
901#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
902#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
903/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
904 */
905#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
906#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
907#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
908/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
909 */
910#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
911#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
912#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
913/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
914 */
915#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
916#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
917#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
918/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
919 */
920#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
921#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
922#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
923/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
924 */
925#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
926#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
927#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
928/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
929 */
930#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
931#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
932#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
933/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
934 */
935#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
936#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
937#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
938/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
939 */
940#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
941#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
942#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
943/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
944 */
945#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
946#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
947#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
948/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
949 */
950#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
951#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
952#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
953/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
954 */
955#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
956#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
957#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
958/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
959 */
960#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
961#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
962#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
963/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
964 */
965#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
966#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
967#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
968/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
969 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
970 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
971 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
972 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
973 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
974 * register.
975 */
976#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
977#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
978#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
979/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
980 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
981 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
982 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
983 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
984 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
985 * register.
986 */
987#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
988#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
989#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
990/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
991 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
992 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
993 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
994 * when all of the individual threshold flags are cleared via writing 1s to those bits.
995 */
996#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
997#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
998#define ADC_FLAGS_OVR_INT_SHIFT (31U)
999/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
1000 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
1001 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
1002 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
1003 * of the individual overrun bits have been cleared via reading the corresponding data registers.
1004 */
1005#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
1006/*! @} */
1007
1008/*! @name STARTUP - ADC Startup register. */
1009/*! @{ */
1010#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
1011#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
1012/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
1013 * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
1014 * after the ADC is powered up (typically by altering a system-level ADC power control bit).
1015 */
1016#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
1017#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
1018#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
1019/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
1020 * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
1021 * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
1022 * required if a calibration is not performed. It will also reload the stored calibration value from
1023 * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
1024 * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
1025 * an ADC dummy conversion cycle is required. It should not be set during the same write that
1026 * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
1027 * when the 'dummy' conversion cycle completes.
1028 */
1029#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
1030/*! @} */
1031
1032/*! @name CALIB - ADC Calibration register. */
1033/*! @{ */
1034#define ADC_CALIB_CALIB_MASK (0x1U)
1035#define ADC_CALIB_CALIB_SHIFT (0U)
1036/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
1037 * only be set to a '1' by software. It is cleared automatically when the calibration cycle
1038 * completes.
1039 */
1040#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
1041#define ADC_CALIB_CALREQD_MASK (0x2U)
1042#define ADC_CALIB_CALREQD_SHIFT (1U)
1043/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
1044 * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
1045 * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
1046 * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
1047 * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
1048 * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
1049 * required for calibration.
1050 */
1051#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
1052#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
1053#define ADC_CALIB_CALVALUE_SHIFT (2U)
1054/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
1055 * during last calibration cycle. This value is not typically of any use to the user.
1056 */
1057#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
1058/*! @} */
1059
1060
1061/*!
1062 * @}
1063 */ /* end of group ADC_Register_Masks */
1064
1065
1066/* ADC - Peripheral instance base addresses */
1067/** Peripheral ADC0 base address */
1068#define ADC0_BASE (0x400A0000u)
1069/** Peripheral ADC0 base pointer */
1070#define ADC0 ((ADC_Type *)ADC0_BASE)
1071/** Array initializer of ADC peripheral base addresses */
1072#define ADC_BASE_ADDRS { ADC0_BASE }
1073/** Array initializer of ADC peripheral base pointers */
1074#define ADC_BASE_PTRS { ADC0 }
1075/** Interrupt vectors for the ADC peripheral type */
1076#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1077#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1078
1079/*!
1080 * @}
1081 */ /* end of group ADC_Peripheral_Access_Layer */
1082
1083
1084/* ----------------------------------------------------------------------------
1085 -- ASYNC_SYSCON Peripheral Access Layer
1086 ---------------------------------------------------------------------------- */
1087
1088/*!
1089 * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
1090 * @{
1091 */
1092
1093/** ASYNC_SYSCON - Register Layout Typedef */
1094typedef struct {
1095 __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
1096 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1097 __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1098 uint8_t RESERVED_0[4];
1099 __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
1100 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1101 __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
1102 uint8_t RESERVED_1[4];
1103 __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
1104} ASYNC_SYSCON_Type;
1105
1106/* ----------------------------------------------------------------------------
1107 -- ASYNC_SYSCON Register Masks
1108 ---------------------------------------------------------------------------- */
1109
1110/*!
1111 * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
1112 * @{
1113 */
1114
1115/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
1116/*! @{ */
1117#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
1118#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
1119/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1120 */
1121#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
1122#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
1123#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
1124/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1125 */
1126#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
1127/*! @} */
1128
1129/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
1130/*! @{ */
1131#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
1132#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
1133/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
1134 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1135 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1136 */
1137#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
1138/*! @} */
1139
1140/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
1141/*! @{ */
1142#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
1143#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
1144/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
1145 * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1146 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1147 */
1148#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
1149/*! @} */
1150
1151/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
1152/*! @{ */
1153#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
1154#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
1155/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
1156 */
1157#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
1158#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
1159#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
1160/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
1161 */
1162#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
1163/*! @} */
1164
1165/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
1166/*! @{ */
1167#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
1168#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
1169/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
1170 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1171 * ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
1172 */
1173#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
1174/*! @} */
1175
1176/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
1177/*! @{ */
1178#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
1179#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
1180/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
1181 * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
1182 * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
1183 */
1184#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
1185/*! @} */
1186
1187/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
1188/*! @{ */
1189#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
1190#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
1191/*! SEL - Clock source for asynchronous clock source selector A
1192 * 0b00..Main clock (main_clk)
1193 * 0b01..FRO 12 MHz (fro_12m)
1194 * 0b10..Audio PLL clock.(AUDPLL_BYPASS)
1195 * 0b11..fc6 fclk (fc6_fclk)
1196 */
1197#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
1198/*! @} */
1199
1200
1201/*!
1202 * @}
1203 */ /* end of group ASYNC_SYSCON_Register_Masks */
1204
1205
1206/* ASYNC_SYSCON - Peripheral instance base addresses */
1207/** Peripheral ASYNC_SYSCON base address */
1208#define ASYNC_SYSCON_BASE (0x40040000u)
1209/** Peripheral ASYNC_SYSCON base pointer */
1210#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
1211/** Array initializer of ASYNC_SYSCON peripheral base addresses */
1212#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
1213/** Array initializer of ASYNC_SYSCON peripheral base pointers */
1214#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
1215
1216/*!
1217 * @}
1218 */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
1219
1220
1221/* ----------------------------------------------------------------------------
1222 -- CAN Peripheral Access Layer
1223 ---------------------------------------------------------------------------- */
1224
1225/*!
1226 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1227 * @{
1228 */
1229
1230/** CAN - Register Layout Typedef */
1231typedef struct {
1232 uint8_t RESERVED_0[12];
1233 __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
1234 __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
1235 uint8_t RESERVED_1[4];
1236 __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
1237 __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
1238 __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
1239 __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
1240 __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
1241 __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
1242 uint8_t RESERVED_2[16];
1243 __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
1244 __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
1245 __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
1246 uint8_t RESERVED_3[4];
1247 __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
1248 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
1249 __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
1250 __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
1251 uint8_t RESERVED_4[32];
1252 __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
1253 __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
1254 __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
1255 uint8_t RESERVED_5[4];
1256 __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
1257 __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
1258 __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
1259 __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
1260 __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
1261 __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
1262 __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
1263 __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
1264 __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
1265 __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
1266 __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
1267 __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
1268 __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
1269 __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
1270 __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
1271 __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
1272 __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
1273 __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
1274 __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
1275 __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
1276 __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
1277 __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
1278 uint8_t RESERVED_6[8];
1279 __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
1280 __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
1281 __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
1282 uint8_t RESERVED_7[260];
1283 __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
1284 uint8_t RESERVED_8[508];
1285 __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
1286 uint8_t RESERVED_9[508];
1287 __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
1288} CAN_Type;
1289
1290/* ----------------------------------------------------------------------------
1291 -- CAN Register Masks
1292 ---------------------------------------------------------------------------- */
1293
1294/*!
1295 * @addtogroup CAN_Register_Masks CAN Register Masks
1296 * @{
1297 */
1298
1299/*! @name DBTP - Data Bit Timing Prescaler Register */
1300/*! @{ */
1301#define CAN_DBTP_DSJW_MASK (0xFU)
1302#define CAN_DBTP_DSJW_SHIFT (0U)
1303/*! DSJW - Data (re)synchronization jump width.
1304 */
1305#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
1306#define CAN_DBTP_DTSEG2_MASK (0xF0U)
1307#define CAN_DBTP_DTSEG2_SHIFT (4U)
1308/*! DTSEG2 - Data time segment after sample point.
1309 */
1310#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
1311#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
1312#define CAN_DBTP_DTSEG1_SHIFT (8U)
1313/*! DTSEG1 - Data time segment before sample point.
1314 */
1315#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
1316#define CAN_DBTP_DBRP_MASK (0x1F0000U)
1317#define CAN_DBTP_DBRP_SHIFT (16U)
1318/*! DBRP - Data bit rate prescaler.
1319 */
1320#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
1321#define CAN_DBTP_TDC_MASK (0x800000U)
1322#define CAN_DBTP_TDC_SHIFT (23U)
1323/*! TDC - Transmitter delay compensation.
1324 */
1325#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
1326/*! @} */
1327
1328/*! @name TEST - Test Register */
1329/*! @{ */
1330#define CAN_TEST_LBCK_MASK (0x10U)
1331#define CAN_TEST_LBCK_SHIFT (4U)
1332/*! LBCK - Loop back mode.
1333 */
1334#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
1335#define CAN_TEST_TX_MASK (0x60U)
1336#define CAN_TEST_TX_SHIFT (5U)
1337/*! TX - Control of transmit pin.
1338 */
1339#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
1340#define CAN_TEST_RX_MASK (0x80U)
1341#define CAN_TEST_RX_SHIFT (7U)
1342/*! RX - Monitors the actual value of the CAN_RXD.
1343 */
1344#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
1345/*! @} */
1346
1347/*! @name CCCR - CC Control Register */
1348/*! @{ */
1349#define CAN_CCCR_INIT_MASK (0x1U)
1350#define CAN_CCCR_INIT_SHIFT (0U)
1351/*! INIT - Initialization.
1352 */
1353#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
1354#define CAN_CCCR_CCE_MASK (0x2U)
1355#define CAN_CCCR_CCE_SHIFT (1U)
1356/*! CCE - Configuration change enable.
1357 */
1358#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
1359#define CAN_CCCR_ASM_MASK (0x4U)
1360#define CAN_CCCR_ASM_SHIFT (2U)
1361/*! ASM - Restricted operational mode.
1362 */
1363#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
1364#define CAN_CCCR_CSA_MASK (0x8U)
1365#define CAN_CCCR_CSA_SHIFT (3U)
1366/*! CSA - Clock Stop Acknowledge.
1367 */
1368#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
1369#define CAN_CCCR_CSR_MASK (0x10U)
1370#define CAN_CCCR_CSR_SHIFT (4U)
1371/*! CSR - Clock Stop Request.
1372 */
1373#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
1374#define CAN_CCCR_MON_MASK (0x20U)
1375#define CAN_CCCR_MON_SHIFT (5U)
1376/*! MON - Bus monitoring mode.
1377 */
1378#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
1379#define CAN_CCCR_DAR_MASK (0x40U)
1380#define CAN_CCCR_DAR_SHIFT (6U)
1381/*! DAR - Disable automatic retransmission.
1382 */
1383#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
1384#define CAN_CCCR_TEST_MASK (0x80U)
1385#define CAN_CCCR_TEST_SHIFT (7U)
1386/*! TEST - Test mode enable.
1387 */
1388#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
1389#define CAN_CCCR_FDOE_MASK (0x100U)
1390#define CAN_CCCR_FDOE_SHIFT (8U)
1391/*! FDOE - CAN FD operation enable.
1392 */
1393#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
1394#define CAN_CCCR_BRSE_MASK (0x200U)
1395#define CAN_CCCR_BRSE_SHIFT (9U)
1396/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
1397 */
1398#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
1399#define CAN_CCCR_PXHD_MASK (0x1000U)
1400#define CAN_CCCR_PXHD_SHIFT (12U)
1401/*! PXHD - Protocol exception handling disable.
1402 */
1403#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
1404#define CAN_CCCR_EFBI_MASK (0x2000U)
1405#define CAN_CCCR_EFBI_SHIFT (13U)
1406/*! EFBI - Edge filtering during bus integration.
1407 */
1408#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
1409#define CAN_CCCR_TXP_MASK (0x4000U)
1410#define CAN_CCCR_TXP_SHIFT (14U)
1411/*! TXP - Transmit pause.
1412 */
1413#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
1414#define CAN_CCCR_NISO_MASK (0x8000U)
1415#define CAN_CCCR_NISO_SHIFT (15U)
1416/*! NISO - Non ISO operation.
1417 */
1418#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
1419/*! @} */
1420
1421/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
1422/*! @{ */
1423#define CAN_NBTP_NTSEG2_MASK (0x7FU)
1424#define CAN_NBTP_NTSEG2_SHIFT (0U)
1425/*! NTSEG2 - Nominal time segment after sample point.
1426 */
1427#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
1428#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
1429#define CAN_NBTP_NTSEG1_SHIFT (8U)
1430/*! NTSEG1 - Nominal time segment before sample point.
1431 */
1432#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
1433#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
1434#define CAN_NBTP_NBRP_SHIFT (16U)
1435/*! NBRP - Nominal bit rate prescaler.
1436 */
1437#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
1438#define CAN_NBTP_NSJW_MASK (0xFE000000U)
1439#define CAN_NBTP_NSJW_SHIFT (25U)
1440/*! NSJW - Nominal (re)synchronization jump width.
1441 */
1442#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
1443/*! @} */
1444
1445/*! @name TSCC - Timestamp Counter Configuration */
1446/*! @{ */
1447#define CAN_TSCC_TSS_MASK (0x3U)
1448#define CAN_TSCC_TSS_SHIFT (0U)
1449/*! TSS - Timestamp select.
1450 */
1451#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
1452#define CAN_TSCC_TCP_MASK (0xF0000U)
1453#define CAN_TSCC_TCP_SHIFT (16U)
1454/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
1455 */
1456#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
1457/*! @} */
1458
1459/*! @name TSCV - Timestamp Counter Value */
1460/*! @{ */
1461#define CAN_TSCV_TSC_MASK (0xFFFFU)
1462#define CAN_TSCV_TSC_SHIFT (0U)
1463/*! TSC - Timestamp counter.
1464 */
1465#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
1466/*! @} */
1467
1468/*! @name TOCC - Timeout Counter Configuration */
1469/*! @{ */
1470#define CAN_TOCC_ETOC_MASK (0x1U)
1471#define CAN_TOCC_ETOC_SHIFT (0U)
1472/*! ETOC - Enable timeout counter.
1473 */
1474#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
1475#define CAN_TOCC_TOS_MASK (0x6U)
1476#define CAN_TOCC_TOS_SHIFT (1U)
1477/*! TOS - Timeout select.
1478 */
1479#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
1480#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
1481#define CAN_TOCC_TOP_SHIFT (16U)
1482/*! TOP - Timeout period.
1483 */
1484#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
1485/*! @} */
1486
1487/*! @name TOCV - Timeout Counter Value */
1488/*! @{ */
1489#define CAN_TOCV_TOC_MASK (0xFFFFU)
1490#define CAN_TOCV_TOC_SHIFT (0U)
1491/*! TOC - Timeout counter.
1492 */
1493#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
1494/*! @} */
1495
1496/*! @name ECR - Error Counter Register */
1497/*! @{ */
1498#define CAN_ECR_TEC_MASK (0xFFU)
1499#define CAN_ECR_TEC_SHIFT (0U)
1500/*! TEC - Transmit error counter.
1501 */
1502#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
1503#define CAN_ECR_REC_MASK (0x7F00U)
1504#define CAN_ECR_REC_SHIFT (8U)
1505/*! REC - Receive error counter.
1506 */
1507#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
1508#define CAN_ECR_RP_MASK (0x8000U)
1509#define CAN_ECR_RP_SHIFT (15U)
1510/*! RP - Receive error passive.
1511 */
1512#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
1513#define CAN_ECR_CEL_MASK (0xFF0000U)
1514#define CAN_ECR_CEL_SHIFT (16U)
1515/*! CEL - CAN error logging.
1516 */
1517#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
1518/*! @} */
1519
1520/*! @name PSR - Protocol Status Register */
1521/*! @{ */
1522#define CAN_PSR_LEC_MASK (0x7U)
1523#define CAN_PSR_LEC_SHIFT (0U)
1524/*! LEC - Last error code.
1525 */
1526#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
1527#define CAN_PSR_ACT_MASK (0x18U)
1528#define CAN_PSR_ACT_SHIFT (3U)
1529/*! ACT - Activity.
1530 */
1531#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
1532#define CAN_PSR_EP_MASK (0x20U)
1533#define CAN_PSR_EP_SHIFT (5U)
1534/*! EP - Error Passive.
1535 */
1536#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
1537#define CAN_PSR_EW_MASK (0x40U)
1538#define CAN_PSR_EW_SHIFT (6U)
1539/*! EW - Warning status.
1540 */
1541#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
1542#define CAN_PSR_BO_MASK (0x80U)
1543#define CAN_PSR_BO_SHIFT (7U)
1544/*! BO - Bus Off Status.
1545 */
1546#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
1547#define CAN_PSR_DLEC_MASK (0x700U)
1548#define CAN_PSR_DLEC_SHIFT (8U)
1549/*! DLEC - Data phase last error code.
1550 */
1551#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
1552#define CAN_PSR_RESI_MASK (0x800U)
1553#define CAN_PSR_RESI_SHIFT (11U)
1554/*! RESI - ESI flag of the last received CAN FD message.
1555 */
1556#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
1557#define CAN_PSR_RBRS_MASK (0x1000U)
1558#define CAN_PSR_RBRS_SHIFT (12U)
1559/*! RBRS - BRS flag of last received CAN FD message.
1560 */
1561#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
1562#define CAN_PSR_RFDF_MASK (0x2000U)
1563#define CAN_PSR_RFDF_SHIFT (13U)
1564/*! RFDF - Received a CAN FD message.
1565 */
1566#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
1567#define CAN_PSR_PXE_MASK (0x4000U)
1568#define CAN_PSR_PXE_SHIFT (14U)
1569/*! PXE - Protocol exception event.
1570 */
1571#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
1572#define CAN_PSR_TDCV_MASK (0x7F0000U)
1573#define CAN_PSR_TDCV_SHIFT (16U)
1574/*! TDCV - Transmitter delay compensation value.
1575 */
1576#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
1577/*! @} */
1578
1579/*! @name TDCR - Transmitter Delay Compensator Register */
1580/*! @{ */
1581#define CAN_TDCR_TDCF_MASK (0x7FU)
1582#define CAN_TDCR_TDCF_SHIFT (0U)
1583/*! TDCF - Transmitter delay compensation filter window length.
1584 */
1585#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
1586#define CAN_TDCR_TDCO_MASK (0x7F00U)
1587#define CAN_TDCR_TDCO_SHIFT (8U)
1588/*! TDCO - Transmitter delay compensation offset.
1589 */
1590#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
1591/*! @} */
1592
1593/*! @name IR - Interrupt Register */
1594/*! @{ */
1595#define CAN_IR_RF0N_MASK (0x1U)
1596#define CAN_IR_RF0N_SHIFT (0U)
1597/*! RF0N - Rx FIFO 0 new message.
1598 */
1599#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
1600#define CAN_IR_RF0W_MASK (0x2U)
1601#define CAN_IR_RF0W_SHIFT (1U)
1602/*! RF0W - Rx FIFO 0 watermark reached.
1603 */
1604#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
1605#define CAN_IR_RF0F_MASK (0x4U)
1606#define CAN_IR_RF0F_SHIFT (2U)
1607/*! RF0F - Rx FIFO 0 full.
1608 */
1609#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
1610#define CAN_IR_RF0L_MASK (0x8U)
1611#define CAN_IR_RF0L_SHIFT (3U)
1612/*! RF0L - Rx FIFO 0 message lost.
1613 */
1614#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
1615#define CAN_IR_RF1N_MASK (0x10U)
1616#define CAN_IR_RF1N_SHIFT (4U)
1617/*! RF1N - Rx FIFO 1 new message.
1618 */
1619#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
1620#define CAN_IR_RF1W_MASK (0x20U)
1621#define CAN_IR_RF1W_SHIFT (5U)
1622/*! RF1W - Rx FIFO 1 watermark reached.
1623 */
1624#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
1625#define CAN_IR_RF1F_MASK (0x40U)
1626#define CAN_IR_RF1F_SHIFT (6U)
1627/*! RF1F - Rx FIFO 1 full.
1628 */
1629#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
1630#define CAN_IR_RF1L_MASK (0x80U)
1631#define CAN_IR_RF1L_SHIFT (7U)
1632/*! RF1L - Rx FIFO 1 message lost.
1633 */
1634#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
1635#define CAN_IR_HPM_MASK (0x100U)
1636#define CAN_IR_HPM_SHIFT (8U)
1637/*! HPM - High priority message.
1638 */
1639#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
1640#define CAN_IR_TC_MASK (0x200U)
1641#define CAN_IR_TC_SHIFT (9U)
1642/*! TC - Transmission completed.
1643 */
1644#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
1645#define CAN_IR_TCF_MASK (0x400U)
1646#define CAN_IR_TCF_SHIFT (10U)
1647/*! TCF - Transmission cancellation finished.
1648 */
1649#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
1650#define CAN_IR_TFE_MASK (0x800U)
1651#define CAN_IR_TFE_SHIFT (11U)
1652/*! TFE - Tx FIFO empty.
1653 */
1654#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
1655#define CAN_IR_TEFN_MASK (0x1000U)
1656#define CAN_IR_TEFN_SHIFT (12U)
1657/*! TEFN - Tx event FIFO new entry.
1658 */
1659#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
1660#define CAN_IR_TEFW_MASK (0x2000U)
1661#define CAN_IR_TEFW_SHIFT (13U)
1662/*! TEFW - Tx event FIFO watermark reached.
1663 */
1664#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
1665#define CAN_IR_TEFF_MASK (0x4000U)
1666#define CAN_IR_TEFF_SHIFT (14U)
1667/*! TEFF - Tx event FIFO full.
1668 */
1669#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
1670#define CAN_IR_TEFL_MASK (0x8000U)
1671#define CAN_IR_TEFL_SHIFT (15U)
1672/*! TEFL - Tx event FIFO element lost.
1673 */
1674#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
1675#define CAN_IR_TSW_MASK (0x10000U)
1676#define CAN_IR_TSW_SHIFT (16U)
1677/*! TSW - Timestamp wraparound.
1678 */
1679#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
1680#define CAN_IR_MRAF_MASK (0x20000U)
1681#define CAN_IR_MRAF_SHIFT (17U)
1682/*! MRAF - Message RAM access failure.
1683 */
1684#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
1685#define CAN_IR_TOO_MASK (0x40000U)
1686#define CAN_IR_TOO_SHIFT (18U)
1687/*! TOO - Timeout occurred.
1688 */
1689#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
1690#define CAN_IR_DRX_MASK (0x80000U)
1691#define CAN_IR_DRX_SHIFT (19U)
1692/*! DRX - Message stored in dedicated Rx buffer.
1693 */
1694#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
1695#define CAN_IR_BEC_MASK (0x100000U)
1696#define CAN_IR_BEC_SHIFT (20U)
1697/*! BEC - Bit error corrected.
1698 */
1699#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
1700#define CAN_IR_BEU_MASK (0x200000U)
1701#define CAN_IR_BEU_SHIFT (21U)
1702/*! BEU - Bit error uncorrected.
1703 */
1704#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
1705#define CAN_IR_ELO_MASK (0x400000U)
1706#define CAN_IR_ELO_SHIFT (22U)
1707/*! ELO - Error logging overflow.
1708 */
1709#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
1710#define CAN_IR_EP_MASK (0x800000U)
1711#define CAN_IR_EP_SHIFT (23U)
1712/*! EP - Error passive.
1713 */
1714#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
1715#define CAN_IR_EW_MASK (0x1000000U)
1716#define CAN_IR_EW_SHIFT (24U)
1717/*! EW - Warning status.
1718 */
1719#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
1720#define CAN_IR_BO_MASK (0x2000000U)
1721#define CAN_IR_BO_SHIFT (25U)
1722/*! BO - Bus_Off Status.
1723 */
1724#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
1725#define CAN_IR_WDI_MASK (0x4000000U)
1726#define CAN_IR_WDI_SHIFT (26U)
1727/*! WDI - Watchdog interrupt.
1728 */
1729#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
1730#define CAN_IR_PEA_MASK (0x8000000U)
1731#define CAN_IR_PEA_SHIFT (27U)
1732/*! PEA - Protocol error in arbitration phase.
1733 */
1734#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
1735#define CAN_IR_PED_MASK (0x10000000U)
1736#define CAN_IR_PED_SHIFT (28U)
1737/*! PED - Protocol error in data phase.
1738 */
1739#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
1740#define CAN_IR_ARA_MASK (0x20000000U)
1741#define CAN_IR_ARA_SHIFT (29U)
1742/*! ARA - Access to reserved address.
1743 */
1744#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
1745/*! @} */
1746
1747/*! @name IE - Interrupt Enable */
1748/*! @{ */
1749#define CAN_IE_RF0NE_MASK (0x1U)
1750#define CAN_IE_RF0NE_SHIFT (0U)
1751/*! RF0NE - Rx FIFO 0 new message interrupt enable.
1752 */
1753#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
1754#define CAN_IE_RF0WE_MASK (0x2U)
1755#define CAN_IE_RF0WE_SHIFT (1U)
1756/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
1757 */
1758#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
1759#define CAN_IE_RF0FE_MASK (0x4U)
1760#define CAN_IE_RF0FE_SHIFT (2U)
1761/*! RF0FE - Rx FIFO 0 full interrupt enable.
1762 */
1763#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
1764#define CAN_IE_RF0LE_MASK (0x8U)
1765#define CAN_IE_RF0LE_SHIFT (3U)
1766/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
1767 */
1768#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
1769#define CAN_IE_RF1NE_MASK (0x10U)
1770#define CAN_IE_RF1NE_SHIFT (4U)
1771/*! RF1NE - Rx FIFO 1 new message interrupt enable.
1772 */
1773#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
1774#define CAN_IE_RF1WE_MASK (0x20U)
1775#define CAN_IE_RF1WE_SHIFT (5U)
1776/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
1777 */
1778#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
1779#define CAN_IE_RF1FE_MASK (0x40U)
1780#define CAN_IE_RF1FE_SHIFT (6U)
1781/*! RF1FE - Rx FIFO 1 full interrupt enable.
1782 */
1783#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
1784#define CAN_IE_RF1LE_MASK (0x80U)
1785#define CAN_IE_RF1LE_SHIFT (7U)
1786/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
1787 */
1788#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
1789#define CAN_IE_HPME_MASK (0x100U)
1790#define CAN_IE_HPME_SHIFT (8U)
1791/*! HPME - High priority message interrupt enable.
1792 */
1793#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
1794#define CAN_IE_TCE_MASK (0x200U)
1795#define CAN_IE_TCE_SHIFT (9U)
1796/*! TCE - Transmission completed interrupt enable.
1797 */
1798#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
1799#define CAN_IE_TCFE_MASK (0x400U)
1800#define CAN_IE_TCFE_SHIFT (10U)
1801/*! TCFE - Transmission cancellation finished interrupt enable.
1802 */
1803#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
1804#define CAN_IE_TFEE_MASK (0x800U)
1805#define CAN_IE_TFEE_SHIFT (11U)
1806/*! TFEE - Tx FIFO empty interrupt enable.
1807 */
1808#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
1809#define CAN_IE_TEFNE_MASK (0x1000U)
1810#define CAN_IE_TEFNE_SHIFT (12U)
1811/*! TEFNE - Tx event FIFO new entry interrupt enable.
1812 */
1813#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
1814#define CAN_IE_TEFWE_MASK (0x2000U)
1815#define CAN_IE_TEFWE_SHIFT (13U)
1816/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
1817 */
1818#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
1819#define CAN_IE_TEFFE_MASK (0x4000U)
1820#define CAN_IE_TEFFE_SHIFT (14U)
1821/*! TEFFE - Tx event FIFO full interrupt enable.
1822 */
1823#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
1824#define CAN_IE_TEFLE_MASK (0x8000U)
1825#define CAN_IE_TEFLE_SHIFT (15U)
1826/*! TEFLE - Tx event FIFO element lost interrupt enable.
1827 */
1828#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
1829#define CAN_IE_TSWE_MASK (0x10000U)
1830#define CAN_IE_TSWE_SHIFT (16U)
1831/*! TSWE - Timestamp wraparound interrupt enable.
1832 */
1833#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
1834#define CAN_IE_MRAFE_MASK (0x20000U)
1835#define CAN_IE_MRAFE_SHIFT (17U)
1836/*! MRAFE - Message RAM access failure interrupt enable.
1837 */
1838#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
1839#define CAN_IE_TOOE_MASK (0x40000U)
1840#define CAN_IE_TOOE_SHIFT (18U)
1841/*! TOOE - Timeout occurred interrupt enable.
1842 */
1843#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
1844#define CAN_IE_DRXE_MASK (0x80000U)
1845#define CAN_IE_DRXE_SHIFT (19U)
1846/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
1847 */
1848#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
1849#define CAN_IE_BECE_MASK (0x100000U)
1850#define CAN_IE_BECE_SHIFT (20U)
1851/*! BECE - Bit error corrected interrupt enable.
1852 */
1853#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
1854#define CAN_IE_BEUE_MASK (0x200000U)
1855#define CAN_IE_BEUE_SHIFT (21U)
1856/*! BEUE - Bit error uncorrected interrupt enable.
1857 */
1858#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
1859#define CAN_IE_ELOE_MASK (0x400000U)
1860#define CAN_IE_ELOE_SHIFT (22U)
1861/*! ELOE - Error logging overflow interrupt enable.
1862 */
1863#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
1864#define CAN_IE_EPE_MASK (0x800000U)
1865#define CAN_IE_EPE_SHIFT (23U)
1866/*! EPE - Error passive interrupt enable.
1867 */
1868#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
1869#define CAN_IE_EWE_MASK (0x1000000U)
1870#define CAN_IE_EWE_SHIFT (24U)
1871/*! EWE - Warning status interrupt enable.
1872 */
1873#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
1874#define CAN_IE_BOE_MASK (0x2000000U)
1875#define CAN_IE_BOE_SHIFT (25U)
1876/*! BOE - Bus_Off Status interrupt enable.
1877 */
1878#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
1879#define CAN_IE_WDIE_MASK (0x4000000U)
1880#define CAN_IE_WDIE_SHIFT (26U)
1881/*! WDIE - Watchdog interrupt enable.
1882 */
1883#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
1884#define CAN_IE_PEAE_MASK (0x8000000U)
1885#define CAN_IE_PEAE_SHIFT (27U)
1886/*! PEAE - Protocol error in arbitration phase interrupt enable.
1887 */
1888#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
1889#define CAN_IE_PEDE_MASK (0x10000000U)
1890#define CAN_IE_PEDE_SHIFT (28U)
1891/*! PEDE - Protocol error in data phase interrupt enable.
1892 */
1893#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
1894#define CAN_IE_ARAE_MASK (0x20000000U)
1895#define CAN_IE_ARAE_SHIFT (29U)
1896/*! ARAE - Access to reserved address interrupt enable.
1897 */
1898#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
1899/*! @} */
1900
1901/*! @name ILS - Interrupt Line Select */
1902/*! @{ */
1903#define CAN_ILS_RF0NL_MASK (0x1U)
1904#define CAN_ILS_RF0NL_SHIFT (0U)
1905/*! RF0NL - Rx FIFO 0 new message interrupt line.
1906 */
1907#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
1908#define CAN_ILS_RF0WL_MASK (0x2U)
1909#define CAN_ILS_RF0WL_SHIFT (1U)
1910/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
1911 */
1912#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
1913#define CAN_ILS_RF0FL_MASK (0x4U)
1914#define CAN_ILS_RF0FL_SHIFT (2U)
1915/*! RF0FL - Rx FIFO 0 full interrupt line.
1916 */
1917#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
1918#define CAN_ILS_RF0LL_MASK (0x8U)
1919#define CAN_ILS_RF0LL_SHIFT (3U)
1920/*! RF0LL - Rx FIFO 0 message lost interrupt line.
1921 */
1922#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
1923#define CAN_ILS_RF1NL_MASK (0x10U)
1924#define CAN_ILS_RF1NL_SHIFT (4U)
1925/*! RF1NL - Rx FIFO 1 new message interrupt line.
1926 */
1927#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
1928#define CAN_ILS_RF1WL_MASK (0x20U)
1929#define CAN_ILS_RF1WL_SHIFT (5U)
1930/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
1931 */
1932#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
1933#define CAN_ILS_RF1FL_MASK (0x40U)
1934#define CAN_ILS_RF1FL_SHIFT (6U)
1935/*! RF1FL - Rx FIFO 1 full interrupt line.
1936 */
1937#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
1938#define CAN_ILS_RF1LL_MASK (0x80U)
1939#define CAN_ILS_RF1LL_SHIFT (7U)
1940/*! RF1LL - Rx FIFO 1 message lost interrupt line.
1941 */
1942#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
1943#define CAN_ILS_HPML_MASK (0x100U)
1944#define CAN_ILS_HPML_SHIFT (8U)
1945/*! HPML - High priority message interrupt line.
1946 */
1947#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
1948#define CAN_ILS_TCL_MASK (0x200U)
1949#define CAN_ILS_TCL_SHIFT (9U)
1950/*! TCL - Transmission completed interrupt line.
1951 */
1952#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
1953#define CAN_ILS_TCFL_MASK (0x400U)
1954#define CAN_ILS_TCFL_SHIFT (10U)
1955/*! TCFL - Transmission cancellation finished interrupt line.
1956 */
1957#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
1958#define CAN_ILS_TFEL_MASK (0x800U)
1959#define CAN_ILS_TFEL_SHIFT (11U)
1960/*! TFEL - Tx FIFO empty interrupt line.
1961 */
1962#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
1963#define CAN_ILS_TEFNL_MASK (0x1000U)
1964#define CAN_ILS_TEFNL_SHIFT (12U)
1965/*! TEFNL - Tx event FIFO new entry interrupt line.
1966 */
1967#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
1968#define CAN_ILS_TEFWL_MASK (0x2000U)
1969#define CAN_ILS_TEFWL_SHIFT (13U)
1970/*! TEFWL - Tx event FIFO watermark reached interrupt line.
1971 */
1972#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
1973#define CAN_ILS_TEFFL_MASK (0x4000U)
1974#define CAN_ILS_TEFFL_SHIFT (14U)
1975/*! TEFFL - Tx event FIFO full interrupt line.
1976 */
1977#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
1978#define CAN_ILS_TEFLL_MASK (0x8000U)
1979#define CAN_ILS_TEFLL_SHIFT (15U)
1980/*! TEFLL - Tx event FIFO element lost interrupt line.
1981 */
1982#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
1983#define CAN_ILS_TSWL_MASK (0x10000U)
1984#define CAN_ILS_TSWL_SHIFT (16U)
1985/*! TSWL - Timestamp wraparound interrupt line.
1986 */
1987#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
1988#define CAN_ILS_MRAFL_MASK (0x20000U)
1989#define CAN_ILS_MRAFL_SHIFT (17U)
1990/*! MRAFL - Message RAM access failure interrupt line.
1991 */
1992#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
1993#define CAN_ILS_TOOL_MASK (0x40000U)
1994#define CAN_ILS_TOOL_SHIFT (18U)
1995/*! TOOL - Timeout occurred interrupt line.
1996 */
1997#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
1998#define CAN_ILS_DRXL_MASK (0x80000U)
1999#define CAN_ILS_DRXL_SHIFT (19U)
2000/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
2001 */
2002#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
2003#define CAN_ILS_BECL_MASK (0x100000U)
2004#define CAN_ILS_BECL_SHIFT (20U)
2005/*! BECL - Bit error corrected interrupt line.
2006 */
2007#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
2008#define CAN_ILS_BEUL_MASK (0x200000U)
2009#define CAN_ILS_BEUL_SHIFT (21U)
2010/*! BEUL - Bit error uncorrected interrupt line.
2011 */
2012#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
2013#define CAN_ILS_ELOL_MASK (0x400000U)
2014#define CAN_ILS_ELOL_SHIFT (22U)
2015/*! ELOL - Error logging overflow interrupt line.
2016 */
2017#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
2018#define CAN_ILS_EPL_MASK (0x800000U)
2019#define CAN_ILS_EPL_SHIFT (23U)
2020/*! EPL - Error passive interrupt line.
2021 */
2022#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
2023#define CAN_ILS_EWL_MASK (0x1000000U)
2024#define CAN_ILS_EWL_SHIFT (24U)
2025/*! EWL - Warning status interrupt line.
2026 */
2027#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
2028#define CAN_ILS_BOL_MASK (0x2000000U)
2029#define CAN_ILS_BOL_SHIFT (25U)
2030/*! BOL - Bus_Off Status interrupt line.
2031 */
2032#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
2033#define CAN_ILS_WDIL_MASK (0x4000000U)
2034#define CAN_ILS_WDIL_SHIFT (26U)
2035/*! WDIL - Watchdog interrupt line.
2036 */
2037#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
2038#define CAN_ILS_PEAL_MASK (0x8000000U)
2039#define CAN_ILS_PEAL_SHIFT (27U)
2040/*! PEAL - Protocol error in arbitration phase interrupt line.
2041 */
2042#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
2043#define CAN_ILS_PEDL_MASK (0x10000000U)
2044#define CAN_ILS_PEDL_SHIFT (28U)
2045/*! PEDL - Protocol error in data phase interrupt line.
2046 */
2047#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
2048#define CAN_ILS_ARAL_MASK (0x20000000U)
2049#define CAN_ILS_ARAL_SHIFT (29U)
2050/*! ARAL - Access to reserved address interrupt line.
2051 */
2052#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
2053/*! @} */
2054
2055/*! @name ILE - Interrupt Line Enable */
2056/*! @{ */
2057#define CAN_ILE_EINT0_MASK (0x1U)
2058#define CAN_ILE_EINT0_SHIFT (0U)
2059/*! EINT0 - Enable interrupt line 0.
2060 */
2061#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
2062#define CAN_ILE_EINT1_MASK (0x2U)
2063#define CAN_ILE_EINT1_SHIFT (1U)
2064/*! EINT1 - Enable interrupt line 1.
2065 */
2066#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
2067/*! @} */
2068
2069/*! @name GFC - Global Filter Configuration */
2070/*! @{ */
2071#define CAN_GFC_RRFE_MASK (0x1U)
2072#define CAN_GFC_RRFE_SHIFT (0U)
2073/*! RRFE - Reject remote frames extended.
2074 */
2075#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
2076#define CAN_GFC_RRFS_MASK (0x2U)
2077#define CAN_GFC_RRFS_SHIFT (1U)
2078/*! RRFS - Reject remote frames standard.
2079 */
2080#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
2081#define CAN_GFC_ANFE_MASK (0xCU)
2082#define CAN_GFC_ANFE_SHIFT (2U)
2083/*! ANFE - Accept non-matching frames extended.
2084 */
2085#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
2086#define CAN_GFC_ANFS_MASK (0x30U)
2087#define CAN_GFC_ANFS_SHIFT (4U)
2088/*! ANFS - Accept non-matching frames standard.
2089 */
2090#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
2091/*! @} */
2092
2093/*! @name SIDFC - Standard ID Filter Configuration */
2094/*! @{ */
2095#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
2096#define CAN_SIDFC_FLSSA_SHIFT (2U)
2097/*! FLSSA - Filter list standard start address.
2098 */
2099#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
2100#define CAN_SIDFC_LSS_MASK (0xFF0000U)
2101#define CAN_SIDFC_LSS_SHIFT (16U)
2102/*! LSS - List size standard 0 = No standard message ID filter.
2103 */
2104#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
2105/*! @} */
2106
2107/*! @name XIDFC - Extended ID Filter Configuration */
2108/*! @{ */
2109#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
2110#define CAN_XIDFC_FLESA_SHIFT (2U)
2111/*! FLESA - Filter list extended start address.
2112 */
2113#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
2114#define CAN_XIDFC_LSE_MASK (0xFF0000U)
2115#define CAN_XIDFC_LSE_SHIFT (16U)
2116/*! LSE - List size extended 0 = No extended message ID filter.
2117 */
2118#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
2119/*! @} */
2120
2121/*! @name XIDAM - Extended ID AND Mask */
2122/*! @{ */
2123#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
2124#define CAN_XIDAM_EIDM_SHIFT (0U)
2125/*! EIDM - Extended ID mask.
2126 */
2127#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
2128/*! @} */
2129
2130/*! @name HPMS - High Priority Message Status */
2131/*! @{ */
2132#define CAN_HPMS_BIDX_MASK (0x3FU)
2133#define CAN_HPMS_BIDX_SHIFT (0U)
2134/*! BIDX - Buffer index.
2135 */
2136#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
2137#define CAN_HPMS_MSI_MASK (0xC0U)
2138#define CAN_HPMS_MSI_SHIFT (6U)
2139/*! MSI - Message storage indicator.
2140 */
2141#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
2142#define CAN_HPMS_FIDX_MASK (0x7F00U)
2143#define CAN_HPMS_FIDX_SHIFT (8U)
2144/*! FIDX - Filter index.
2145 */
2146#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
2147#define CAN_HPMS_FLST_MASK (0x8000U)
2148#define CAN_HPMS_FLST_SHIFT (15U)
2149/*! FLST - Filter list.
2150 */
2151#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
2152/*! @} */
2153
2154/*! @name NDAT1 - New Data 1 */
2155/*! @{ */
2156#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
2157#define CAN_NDAT1_ND_SHIFT (0U)
2158/*! ND - New Data.
2159 */
2160#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
2161/*! @} */
2162
2163/*! @name NDAT2 - New Data 2 */
2164/*! @{ */
2165#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
2166#define CAN_NDAT2_ND_SHIFT (0U)
2167/*! ND - New Data.
2168 */
2169#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
2170/*! @} */
2171
2172/*! @name RXF0C - Rx FIFO 0 Configuration */
2173/*! @{ */
2174#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
2175#define CAN_RXF0C_F0SA_SHIFT (2U)
2176/*! F0SA - Rx FIFO 0 start address.
2177 */
2178#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
2179#define CAN_RXF0C_F0S_MASK (0x7F0000U)
2180#define CAN_RXF0C_F0S_SHIFT (16U)
2181/*! F0S - Rx FIFO 0 size.
2182 */
2183#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
2184#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
2185#define CAN_RXF0C_F0WM_SHIFT (24U)
2186/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
2187 */
2188#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
2189#define CAN_RXF0C_F0OM_MASK (0x80000000U)
2190#define CAN_RXF0C_F0OM_SHIFT (31U)
2191/*! F0OM - FIFO 0 operation mode.
2192 */
2193#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
2194/*! @} */
2195
2196/*! @name RXF0S - Rx FIFO 0 Status */
2197/*! @{ */
2198#define CAN_RXF0S_F0FL_MASK (0x7FU)
2199#define CAN_RXF0S_F0FL_SHIFT (0U)
2200/*! F0FL - Rx FIFO 0 fill level.
2201 */
2202#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
2203#define CAN_RXF0S_F0GI_MASK (0x3F00U)
2204#define CAN_RXF0S_F0GI_SHIFT (8U)
2205/*! F0GI - Rx FIFO 0 get index.
2206 */
2207#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
2208#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
2209#define CAN_RXF0S_F0PI_SHIFT (16U)
2210/*! F0PI - Rx FIFO 0 put index.
2211 */
2212#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
2213#define CAN_RXF0S_F0F_MASK (0x1000000U)
2214#define CAN_RXF0S_F0F_SHIFT (24U)
2215/*! F0F - Rx FIFO 0 full.
2216 */
2217#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
2218#define CAN_RXF0S_RF0L_MASK (0x2000000U)
2219#define CAN_RXF0S_RF0L_SHIFT (25U)
2220/*! RF0L - Rx FIFO 0 message lost.
2221 */
2222#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
2223/*! @} */
2224
2225/*! @name RXF0A - Rx FIFO 0 Acknowledge */
2226/*! @{ */
2227#define CAN_RXF0A_F0AI_MASK (0x3FU)
2228#define CAN_RXF0A_F0AI_SHIFT (0U)
2229/*! F0AI - Rx FIFO 0 acknowledge index.
2230 */
2231#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
2232/*! @} */
2233
2234/*! @name RXBC - Rx Buffer Configuration */
2235/*! @{ */
2236#define CAN_RXBC_RBSA_MASK (0xFFFCU)
2237#define CAN_RXBC_RBSA_SHIFT (2U)
2238/*! RBSA - Rx buffer start address.
2239 */
2240#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
2241/*! @} */
2242
2243/*! @name RXF1C - Rx FIFO 1 Configuration */
2244/*! @{ */
2245#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
2246#define CAN_RXF1C_F1SA_SHIFT (2U)
2247/*! F1SA - Rx FIFO 1 start address.
2248 */
2249#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
2250#define CAN_RXF1C_F1S_MASK (0x7F0000U)
2251#define CAN_RXF1C_F1S_SHIFT (16U)
2252/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
2253 */
2254#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
2255#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
2256#define CAN_RXF1C_F1WM_SHIFT (24U)
2257/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
2258 */
2259#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
2260#define CAN_RXF1C_F1OM_MASK (0x80000000U)
2261#define CAN_RXF1C_F1OM_SHIFT (31U)
2262/*! F1OM - FIFO 1 operation mode.
2263 */
2264#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
2265/*! @} */
2266
2267/*! @name RXF1S - Rx FIFO 1 Status */
2268/*! @{ */
2269#define CAN_RXF1S_F1FL_MASK (0x7FU)
2270#define CAN_RXF1S_F1FL_SHIFT (0U)
2271/*! F1FL - Rx FIFO 1 fill level.
2272 */
2273#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
2274#define CAN_RXF1S_F1GI_MASK (0x3F00U)
2275#define CAN_RXF1S_F1GI_SHIFT (8U)
2276/*! F1GI - Rx FIFO 1 get index.
2277 */
2278#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
2279#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
2280#define CAN_RXF1S_F1PI_SHIFT (16U)
2281/*! F1PI - Rx FIFO 1 put index.
2282 */
2283#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
2284#define CAN_RXF1S_F1F_MASK (0x1000000U)
2285#define CAN_RXF1S_F1F_SHIFT (24U)
2286/*! F1F - Rx FIFO 1 full.
2287 */
2288#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
2289#define CAN_RXF1S_RF1L_MASK (0x2000000U)
2290#define CAN_RXF1S_RF1L_SHIFT (25U)
2291/*! RF1L - Rx FIFO 1 message lost.
2292 */
2293#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
2294/*! @} */
2295
2296/*! @name RXF1A - Rx FIFO 1 Acknowledge */
2297/*! @{ */
2298#define CAN_RXF1A_F1AI_MASK (0x3FU)
2299#define CAN_RXF1A_F1AI_SHIFT (0U)
2300/*! F1AI - Rx FIFO 1 acknowledge index.
2301 */
2302#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
2303/*! @} */
2304
2305/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
2306/*! @{ */
2307#define CAN_RXESC_F0DS_MASK (0x7U)
2308#define CAN_RXESC_F0DS_SHIFT (0U)
2309/*! F0DS - Rx FIFO 0 data field size.
2310 */
2311#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
2312#define CAN_RXESC_F1DS_MASK (0x70U)
2313#define CAN_RXESC_F1DS_SHIFT (4U)
2314/*! F1DS - Rx FIFO 1 data field size.
2315 */
2316#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
2317#define CAN_RXESC_RBDS_MASK (0x700U)
2318#define CAN_RXESC_RBDS_SHIFT (8U)
2319/*! RBDS - .
2320 */
2321#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
2322/*! @} */
2323
2324/*! @name TXBC - Tx Buffer Configuration */
2325/*! @{ */
2326#define CAN_TXBC_TBSA_MASK (0xFFFCU)
2327#define CAN_TXBC_TBSA_SHIFT (2U)
2328/*! TBSA - Tx buffers start address.
2329 */
2330#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
2331#define CAN_TXBC_NDTB_MASK (0x3F0000U)
2332#define CAN_TXBC_NDTB_SHIFT (16U)
2333/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
2334 */
2335#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
2336#define CAN_TXBC_TFQS_MASK (0x3F000000U)
2337#define CAN_TXBC_TFQS_SHIFT (24U)
2338/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
2339 */
2340#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
2341#define CAN_TXBC_TFQM_MASK (0x40000000U)
2342#define CAN_TXBC_TFQM_SHIFT (30U)
2343/*! TFQM - Tx FIFO/queue mode.
2344 */
2345#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
2346/*! @} */
2347
2348/*! @name TXFQS - Tx FIFO/Queue Status */
2349/*! @{ */
2350#define CAN_TXFQS_TFGI_MASK (0x1F00U)
2351#define CAN_TXFQS_TFGI_SHIFT (8U)
2352/*! TFGI - Tx FIFO get index.
2353 */
2354#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
2355#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
2356#define CAN_TXFQS_TFQPI_SHIFT (16U)
2357/*! TFQPI - Tx FIFO/queue put index.
2358 */
2359#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
2360#define CAN_TXFQS_TFQF_MASK (0x200000U)
2361#define CAN_TXFQS_TFQF_SHIFT (21U)
2362/*! TFQF - Tx FIFO/queue full.
2363 */
2364#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
2365/*! @} */
2366
2367/*! @name TXESC - Tx Buffer Element Size Configuration */
2368/*! @{ */
2369#define CAN_TXESC_TBDS_MASK (0x7U)
2370#define CAN_TXESC_TBDS_SHIFT (0U)
2371/*! TBDS - Tx buffer data field size.
2372 */
2373#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
2374/*! @} */
2375
2376/*! @name TXBRP - Tx Buffer Request Pending */
2377/*! @{ */
2378#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
2379#define CAN_TXBRP_TRP_SHIFT (0U)
2380/*! TRP - Transmission request pending.
2381 */
2382#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
2383/*! @} */
2384
2385/*! @name TXBAR - Tx Buffer Add Request */
2386/*! @{ */
2387#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
2388#define CAN_TXBAR_AR_SHIFT (0U)
2389/*! AR - Add request.
2390 */
2391#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
2392/*! @} */
2393
2394/*! @name TXBCR - Tx Buffer Cancellation Request */
2395/*! @{ */
2396#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
2397#define CAN_TXBCR_CR_SHIFT (0U)
2398/*! CR - Cancellation request.
2399 */
2400#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
2401/*! @} */
2402
2403/*! @name TXBTO - Tx Buffer Transmission Occurred */
2404/*! @{ */
2405#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
2406#define CAN_TXBTO_TO_SHIFT (0U)
2407/*! TO - Transmission occurred.
2408 */
2409#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
2410/*! @} */
2411
2412/*! @name TXBCF - Tx Buffer Cancellation Finished */
2413/*! @{ */
2414#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
2415#define CAN_TXBCF_TO_SHIFT (0U)
2416/*! TO - Cancellation finished.
2417 */
2418#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
2419/*! @} */
2420
2421/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
2422/*! @{ */
2423#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
2424#define CAN_TXBTIE_TIE_SHIFT (0U)
2425/*! TIE - Transmission interrupt enable.
2426 */
2427#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
2428/*! @} */
2429
2430/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
2431/*! @{ */
2432#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
2433#define CAN_TXBCIE_CFIE_SHIFT (0U)
2434/*! CFIE - Cancellation finished interrupt enable.
2435 */
2436#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
2437/*! @} */
2438
2439/*! @name TXEFC - Tx Event FIFO Configuration */
2440/*! @{ */
2441#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
2442#define CAN_TXEFC_EFSA_SHIFT (2U)
2443/*! EFSA - Event FIFO start address.
2444 */
2445#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
2446#define CAN_TXEFC_EFS_MASK (0x3F0000U)
2447#define CAN_TXEFC_EFS_SHIFT (16U)
2448/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
2449 */
2450#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
2451#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
2452#define CAN_TXEFC_EFWM_SHIFT (24U)
2453/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
2454 */
2455#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
2456/*! @} */
2457
2458/*! @name TXEFS - Tx Event FIFO Status */
2459/*! @{ */
2460#define CAN_TXEFS_EFFL_MASK (0x3FU)
2461#define CAN_TXEFS_EFFL_SHIFT (0U)
2462/*! EFFL - Event FIFO fill level.
2463 */
2464#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
2465#define CAN_TXEFS_EFGI_MASK (0x1F00U)
2466#define CAN_TXEFS_EFGI_SHIFT (8U)
2467/*! EFGI - Event FIFO get index.
2468 */
2469#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
2470#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
2471#define CAN_TXEFS_EFPI_SHIFT (16U)
2472/*! EFPI - Event FIFO put index.
2473 */
2474#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
2475#define CAN_TXEFS_EFF_MASK (0x1000000U)
2476#define CAN_TXEFS_EFF_SHIFT (24U)
2477/*! EFF - Event FIFO full.
2478 */
2479#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
2480#define CAN_TXEFS_TEFL_MASK (0x2000000U)
2481#define CAN_TXEFS_TEFL_SHIFT (25U)
2482/*! TEFL - Tx event FIFO element lost.
2483 */
2484#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
2485/*! @} */
2486
2487/*! @name TXEFA - Tx Event FIFO Acknowledge */
2488/*! @{ */
2489#define CAN_TXEFA_EFAI_MASK (0x1FU)
2490#define CAN_TXEFA_EFAI_SHIFT (0U)
2491/*! EFAI - Event FIFO acknowledge index.
2492 */
2493#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
2494/*! @} */
2495
2496/*! @name MRBA - CAN Message RAM Base Address */
2497/*! @{ */
2498#define CAN_MRBA_BA_MASK (0xFFFF0000U)
2499#define CAN_MRBA_BA_SHIFT (16U)
2500/*! BA - Base address for the message RAM in the chip memory map.
2501 */
2502#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
2503/*! @} */
2504
2505/*! @name ETSCC - External Timestamp Counter Configuration */
2506/*! @{ */
2507#define CAN_ETSCC_ETCP_MASK (0x7FFU)
2508#define CAN_ETSCC_ETCP_SHIFT (0U)
2509/*! ETCP - External timestamp prescaler value.
2510 */
2511#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
2512#define CAN_ETSCC_ETCE_MASK (0x80000000U)
2513#define CAN_ETSCC_ETCE_SHIFT (31U)
2514/*! ETCE - External timestamp counter enable.
2515 */
2516#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
2517/*! @} */
2518
2519/*! @name ETSCV - External Timestamp Counter Value */
2520/*! @{ */
2521#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
2522#define CAN_ETSCV_ETSC_SHIFT (0U)
2523/*! ETSC - External timestamp counter.
2524 */
2525#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
2526/*! @} */
2527
2528
2529/*!
2530 * @}
2531 */ /* end of group CAN_Register_Masks */
2532
2533
2534/* CAN - Peripheral instance base addresses */
2535/** Peripheral CAN0 base address */
2536#define CAN0_BASE (0x4009D000u)
2537/** Peripheral CAN0 base pointer */
2538#define CAN0 ((CAN_Type *)CAN0_BASE)
2539/** Peripheral CAN1 base address */
2540#define CAN1_BASE (0x4009E000u)
2541/** Peripheral CAN1 base pointer */
2542#define CAN1 ((CAN_Type *)CAN1_BASE)
2543/** Array initializer of CAN peripheral base addresses */
2544#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
2545/** Array initializer of CAN peripheral base pointers */
2546#define CAN_BASE_PTRS { CAN0, CAN1 }
2547/** Interrupt vectors for the CAN peripheral type */
2548#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
2549
2550/*!
2551 * @}
2552 */ /* end of group CAN_Peripheral_Access_Layer */
2553
2554
2555/* ----------------------------------------------------------------------------
2556 -- CRC Peripheral Access Layer
2557 ---------------------------------------------------------------------------- */
2558
2559/*!
2560 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
2561 * @{
2562 */
2563
2564/** CRC - Register Layout Typedef */
2565typedef struct {
2566 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
2567 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
2568 union { /* offset: 0x8 */
2569 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
2570 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
2571 };
2572} CRC_Type;
2573
2574/* ----------------------------------------------------------------------------
2575 -- CRC Register Masks
2576 ---------------------------------------------------------------------------- */
2577
2578/*!
2579 * @addtogroup CRC_Register_Masks CRC Register Masks
2580 * @{
2581 */
2582
2583/*! @name MODE - CRC mode register */
2584/*! @{ */
2585#define CRC_MODE_CRC_POLY_MASK (0x3U)
2586#define CRC_MODE_CRC_POLY_SHIFT (0U)
2587/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
2588 */
2589#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
2590#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
2591#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
2592/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2593 */
2594#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
2595#define CRC_MODE_CMPL_WR_MASK (0x8U)
2596#define CRC_MODE_CMPL_WR_SHIFT (3U)
2597/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
2598 */
2599#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
2600#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
2601#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
2602/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
2603 */
2604#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
2605#define CRC_MODE_CMPL_SUM_MASK (0x20U)
2606#define CRC_MODE_CMPL_SUM_SHIFT (5U)
2607/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
2608 */
2609#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
2610/*! @} */
2611
2612/*! @name SEED - CRC seed register */
2613/*! @{ */
2614#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
2615#define CRC_SEED_CRC_SEED_SHIFT (0U)
2616/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
2617 * selected bit order and 1's complement pre-processes. A write access to this register will
2618 * overrule the CRC calculation in progresses.
2619 */
2620#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
2621/*! @} */
2622
2623/*! @name SUM - CRC checksum register */
2624/*! @{ */
2625#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
2626#define CRC_SUM_CRC_SUM_SHIFT (0U)
2627/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
2628 */
2629#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
2630/*! @} */
2631
2632/*! @name WR_DATA - CRC data register */
2633/*! @{ */
2634#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
2635#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
2636/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
2637 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
2638 * accept back-to-back transactions.
2639 */
2640#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
2641/*! @} */
2642
2643
2644/*!
2645 * @}
2646 */ /* end of group CRC_Register_Masks */
2647
2648
2649/* CRC - Peripheral instance base addresses */
2650/** Peripheral CRC_ENGINE base address */
2651#define CRC_ENGINE_BASE (0x40095000u)
2652/** Peripheral CRC_ENGINE base pointer */
2653#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
2654/** Array initializer of CRC peripheral base addresses */
2655#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
2656/** Array initializer of CRC peripheral base pointers */
2657#define CRC_BASE_PTRS { CRC_ENGINE }
2658
2659/*!
2660 * @}
2661 */ /* end of group CRC_Peripheral_Access_Layer */
2662
2663
2664/* ----------------------------------------------------------------------------
2665 -- CTIMER Peripheral Access Layer
2666 ---------------------------------------------------------------------------- */
2667
2668/*!
2669 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
2670 * @{
2671 */
2672
2673/** CTIMER - Register Layout Typedef */
2674typedef struct {
2675 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
2676 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
2677 __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
2678 __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
2679 __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
2680 __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
2681 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
2682 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
2683 __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
2684 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
2685 uint8_t RESERVED_0[48];
2686 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
2687 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
2688 __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
2689} CTIMER_Type;
2690
2691/* ----------------------------------------------------------------------------
2692 -- CTIMER Register Masks
2693 ---------------------------------------------------------------------------- */
2694
2695/*!
2696 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
2697 * @{
2698 */
2699
2700/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
2701/*! @{ */
2702#define CTIMER_IR_MR0INT_MASK (0x1U)
2703#define CTIMER_IR_MR0INT_SHIFT (0U)
2704/*! MR0INT - Interrupt flag for match channel 0.
2705 */
2706#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
2707#define CTIMER_IR_MR1INT_MASK (0x2U)
2708#define CTIMER_IR_MR1INT_SHIFT (1U)
2709/*! MR1INT - Interrupt flag for match channel 1.
2710 */
2711#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
2712#define CTIMER_IR_MR2INT_MASK (0x4U)
2713#define CTIMER_IR_MR2INT_SHIFT (2U)
2714/*! MR2INT - Interrupt flag for match channel 2.
2715 */
2716#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
2717#define CTIMER_IR_MR3INT_MASK (0x8U)
2718#define CTIMER_IR_MR3INT_SHIFT (3U)
2719/*! MR3INT - Interrupt flag for match channel 3.
2720 */
2721#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
2722#define CTIMER_IR_CR0INT_MASK (0x10U)
2723#define CTIMER_IR_CR0INT_SHIFT (4U)
2724/*! CR0INT - Interrupt flag for capture channel 0 event.
2725 */
2726#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
2727#define CTIMER_IR_CR1INT_MASK (0x20U)
2728#define CTIMER_IR_CR1INT_SHIFT (5U)
2729/*! CR1INT - Interrupt flag for capture channel 1 event.
2730 */
2731#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
2732#define CTIMER_IR_CR2INT_MASK (0x40U)
2733#define CTIMER_IR_CR2INT_SHIFT (6U)
2734/*! CR2INT - Interrupt flag for capture channel 2 event.
2735 */
2736#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
2737#define CTIMER_IR_CR3INT_MASK (0x80U)
2738#define CTIMER_IR_CR3INT_SHIFT (7U)
2739/*! CR3INT - Interrupt flag for capture channel 3 event.
2740 */
2741#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
2742/*! @} */
2743
2744/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
2745/*! @{ */
2746#define CTIMER_TCR_CEN_MASK (0x1U)
2747#define CTIMER_TCR_CEN_SHIFT (0U)
2748/*! CEN - Counter enable.
2749 * 0b0..Disabled.The counters are disabled.
2750 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
2751 */
2752#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
2753#define CTIMER_TCR_CRST_MASK (0x2U)
2754#define CTIMER_TCR_CRST_SHIFT (1U)
2755/*! CRST - Counter reset.
2756 * 0b0..Disabled. Do nothing.
2757 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
2758 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
2759 */
2760#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
2761/*! @} */
2762
2763/*! @name TC - Timer Counter */
2764/*! @{ */
2765#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
2766#define CTIMER_TC_TCVAL_SHIFT (0U)
2767/*! TCVAL - Timer counter value.
2768 */
2769#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
2770/*! @} */
2771
2772/*! @name PR - Prescale Register */
2773/*! @{ */
2774#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
2775#define CTIMER_PR_PRVAL_SHIFT (0U)
2776/*! PRVAL - Prescale counter value.
2777 */
2778#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
2779/*! @} */
2780
2781/*! @name PC - Prescale Counter */
2782/*! @{ */
2783#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
2784#define CTIMER_PC_PCVAL_SHIFT (0U)
2785/*! PCVAL - Prescale counter value.
2786 */
2787#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
2788/*! @} */
2789
2790/*! @name MCR - Match Control Register */
2791/*! @{ */
2792#define CTIMER_MCR_MR0I_MASK (0x1U)
2793#define CTIMER_MCR_MR0I_SHIFT (0U)
2794/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
2795 */
2796#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
2797#define CTIMER_MCR_MR0R_MASK (0x2U)
2798#define CTIMER_MCR_MR0R_SHIFT (1U)
2799/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
2800 */
2801#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
2802#define CTIMER_MCR_MR0S_MASK (0x4U)
2803#define CTIMER_MCR_MR0S_SHIFT (2U)
2804/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
2805 */
2806#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
2807#define CTIMER_MCR_MR1I_MASK (0x8U)
2808#define CTIMER_MCR_MR1I_SHIFT (3U)
2809/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
2810 */
2811#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
2812#define CTIMER_MCR_MR1R_MASK (0x10U)
2813#define CTIMER_MCR_MR1R_SHIFT (4U)
2814/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
2815 */
2816#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
2817#define CTIMER_MCR_MR1S_MASK (0x20U)
2818#define CTIMER_MCR_MR1S_SHIFT (5U)
2819/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
2820 */
2821#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
2822#define CTIMER_MCR_MR2I_MASK (0x40U)
2823#define CTIMER_MCR_MR2I_SHIFT (6U)
2824/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
2825 */
2826#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
2827#define CTIMER_MCR_MR2R_MASK (0x80U)
2828#define CTIMER_MCR_MR2R_SHIFT (7U)
2829/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
2830 */
2831#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
2832#define CTIMER_MCR_MR2S_MASK (0x100U)
2833#define CTIMER_MCR_MR2S_SHIFT (8U)
2834/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
2835 */
2836#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
2837#define CTIMER_MCR_MR3I_MASK (0x200U)
2838#define CTIMER_MCR_MR3I_SHIFT (9U)
2839/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
2840 */
2841#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
2842#define CTIMER_MCR_MR3R_MASK (0x400U)
2843#define CTIMER_MCR_MR3R_SHIFT (10U)
2844/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
2845 */
2846#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
2847#define CTIMER_MCR_MR3S_MASK (0x800U)
2848#define CTIMER_MCR_MR3S_SHIFT (11U)
2849/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
2850 */
2851#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
2852#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
2853#define CTIMER_MCR_MR0RL_SHIFT (24U)
2854/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
2855 * (either via a match event or a write to bit 1 of the TCR).
2856 */
2857#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
2858#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
2859#define CTIMER_MCR_MR1RL_SHIFT (25U)
2860/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
2861 * (either via a match event or a write to bit 1 of the TCR).
2862 */
2863#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
2864#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
2865#define CTIMER_MCR_MR2RL_SHIFT (26U)
2866/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
2867 * (either via a match event or a write to bit 1 of the TCR).
2868 */
2869#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
2870#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
2871#define CTIMER_MCR_MR3RL_SHIFT (27U)
2872/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
2873 * (either via a match event or a write to bit 1 of the TCR).
2874 */
2875#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
2876/*! @} */
2877
2878/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
2879/*! @{ */
2880#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
2881#define CTIMER_MR_MATCH_SHIFT (0U)
2882/*! MATCH - Timer counter match value.
2883 */
2884#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
2885/*! @} */
2886
2887/* The count of CTIMER_MR */
2888#define CTIMER_MR_COUNT (4U)
2889
2890/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
2891/*! @{ */
2892#define CTIMER_CCR_CAP0RE_MASK (0x1U)
2893#define CTIMER_CCR_CAP0RE_SHIFT (0U)
2894/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
2895 * the contents of TC. 0 = disabled. 1 = enabled.
2896 */
2897#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
2898#define CTIMER_CCR_CAP0FE_MASK (0x2U)
2899#define CTIMER_CCR_CAP0FE_SHIFT (1U)
2900/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
2901 * the contents of TC. 0 = disabled. 1 = enabled.
2902 */
2903#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
2904#define CTIMER_CCR_CAP0I_MASK (0x4U)
2905#define CTIMER_CCR_CAP0I_SHIFT (2U)
2906/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2907 */
2908#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
2909#define CTIMER_CCR_CAP1RE_MASK (0x8U)
2910#define CTIMER_CCR_CAP1RE_SHIFT (3U)
2911/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
2912 * the contents of TC. 0 = disabled. 1 = enabled.
2913 */
2914#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
2915#define CTIMER_CCR_CAP1FE_MASK (0x10U)
2916#define CTIMER_CCR_CAP1FE_SHIFT (4U)
2917/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
2918 * the contents of TC. 0 = disabled. 1 = enabled.
2919 */
2920#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
2921#define CTIMER_CCR_CAP1I_MASK (0x20U)
2922#define CTIMER_CCR_CAP1I_SHIFT (5U)
2923/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
2924 */
2925#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
2926#define CTIMER_CCR_CAP2RE_MASK (0x40U)
2927#define CTIMER_CCR_CAP2RE_SHIFT (6U)
2928/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
2929 * the contents of TC. 0 = disabled. 1 = enabled.
2930 */
2931#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
2932#define CTIMER_CCR_CAP2FE_MASK (0x80U)
2933#define CTIMER_CCR_CAP2FE_SHIFT (7U)
2934/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
2935 * the contents of TC. 0 = disabled. 1 = enabled.
2936 */
2937#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
2938#define CTIMER_CCR_CAP2I_MASK (0x100U)
2939#define CTIMER_CCR_CAP2I_SHIFT (8U)
2940/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
2941 */
2942#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
2943#define CTIMER_CCR_CAP3RE_MASK (0x200U)
2944#define CTIMER_CCR_CAP3RE_SHIFT (9U)
2945/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
2946 * the contents of TC. 0 = disabled. 1 = enabled.
2947 */
2948#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
2949#define CTIMER_CCR_CAP3FE_MASK (0x400U)
2950#define CTIMER_CCR_CAP3FE_SHIFT (10U)
2951/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
2952 * the contents of TC. 0 = disabled. 1 = enabled.
2953 */
2954#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
2955#define CTIMER_CCR_CAP3I_MASK (0x800U)
2956#define CTIMER_CCR_CAP3I_SHIFT (11U)
2957/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
2958 */
2959#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
2960/*! @} */
2961
2962/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
2963/*! @{ */
2964#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
2965#define CTIMER_CR_CAP_SHIFT (0U)
2966/*! CAP - Timer counter capture value.
2967 */
2968#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
2969/*! @} */
2970
2971/* The count of CTIMER_CR */
2972#define CTIMER_CR_COUNT (4U)
2973
2974/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
2975/*! @{ */
2976#define CTIMER_EMR_EM0_MASK (0x1U)
2977#define CTIMER_EMR_EM0_SHIFT (0U)
2978/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
2979 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
2980 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
2981 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2982 */
2983#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
2984#define CTIMER_EMR_EM1_MASK (0x2U)
2985#define CTIMER_EMR_EM1_SHIFT (1U)
2986/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
2987 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
2988 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
2989 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2990 */
2991#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
2992#define CTIMER_EMR_EM2_MASK (0x4U)
2993#define CTIMER_EMR_EM2_SHIFT (2U)
2994/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
2995 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
2996 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
2997 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2998 */
2999#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
3000#define CTIMER_EMR_EM3_MASK (0x8U)
3001#define CTIMER_EMR_EM3_SHIFT (3U)
3002/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
3003 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
3004 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
3005 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3006 */
3007#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
3008#define CTIMER_EMR_EMC0_MASK (0x30U)
3009#define CTIMER_EMR_EMC0_SHIFT (4U)
3010/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
3011 * 0b00..Do Nothing.
3012 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
3013 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
3014 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3015 */
3016#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
3017#define CTIMER_EMR_EMC1_MASK (0xC0U)
3018#define CTIMER_EMR_EMC1_SHIFT (6U)
3019/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
3020 * 0b00..Do Nothing.
3021 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
3022 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
3023 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3024 */
3025#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
3026#define CTIMER_EMR_EMC2_MASK (0x300U)
3027#define CTIMER_EMR_EMC2_SHIFT (8U)
3028/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
3029 * 0b00..Do Nothing.
3030 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
3031 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
3032 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3033 */
3034#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
3035#define CTIMER_EMR_EMC3_MASK (0xC00U)
3036#define CTIMER_EMR_EMC3_SHIFT (10U)
3037/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
3038 * 0b00..Do Nothing.
3039 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
3040 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
3041 * 0b11..Toggle. Toggle the corresponding External Match bit/output.
3042 */
3043#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
3044/*! @} */
3045
3046/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
3047/*! @{ */
3048#define CTIMER_CTCR_CTMODE_MASK (0x3U)
3049#define CTIMER_CTCR_CTMODE_SHIFT (0U)
3050/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
3051 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
3052 * is incremented when the Prescale Counter matches the Prescale Register.
3053 * 0b00..Timer Mode. Incremented every rising APB bus clock edge.
3054 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
3055 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3056 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
3057 */
3058#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
3059#define CTIMER_CTCR_CINSEL_MASK (0xCU)
3060#define CTIMER_CTCR_CINSEL_SHIFT (2U)
3061/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
3062 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
3063 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
3064 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
3065 * same timer.
3066 * 0b00..Channel 0. CAPn.0 for CTIMERn
3067 * 0b01..Channel 1. CAPn.1 for CTIMERn
3068 * 0b10..Channel 2. CAPn.2 for CTIMERn
3069 * 0b11..Channel 3. CAPn.3 for CTIMERn
3070 */
3071#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
3072#define CTIMER_CTCR_ENCC_MASK (0x10U)
3073#define CTIMER_CTCR_ENCC_SHIFT (4U)
3074/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
3075 * capture-edge event specified in bits 7:5 occurs.
3076 */
3077#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
3078#define CTIMER_CTCR_SELCC_MASK (0xE0U)
3079#define CTIMER_CTCR_SELCC_SHIFT (5U)
3080/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
3081 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
3082 * 0x3 and 0x6 to 0x7 are reserved.
3083 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3084 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
3085 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3086 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
3087 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3088 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
3089 */
3090#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
3091/*! @} */
3092
3093/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
3094/*! @{ */
3095#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
3096#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
3097/*! PWMEN0 - PWM mode enable for channel0.
3098 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
3099 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
3100 */
3101#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
3102#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
3103#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
3104/*! PWMEN1 - PWM mode enable for channel1.
3105 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
3106 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
3107 */
3108#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
3109#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
3110#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
3111/*! PWMEN2 - PWM mode enable for channel2.
3112 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
3113 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
3114 */
3115#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
3116#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
3117#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
3118/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3119 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
3120 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
3121 */
3122#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
3123/*! @} */
3124
3125/*! @name MSR - Match Shadow Register */
3126/*! @{ */
3127#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
3128#define CTIMER_MSR_SHADOWW_SHIFT (0U)
3129/*! SHADOWW - Timer counter match shadow value.
3130 */
3131#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
3132/*! @} */
3133
3134/* The count of CTIMER_MSR */
3135#define CTIMER_MSR_COUNT (4U)
3136
3137
3138/*!
3139 * @}
3140 */ /* end of group CTIMER_Register_Masks */
3141
3142
3143/* CTIMER - Peripheral instance base addresses */
3144/** Peripheral CTIMER0 base address */
3145#define CTIMER0_BASE (0x40008000u)
3146/** Peripheral CTIMER0 base pointer */
3147#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
3148/** Peripheral CTIMER1 base address */
3149#define CTIMER1_BASE (0x40009000u)
3150/** Peripheral CTIMER1 base pointer */
3151#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
3152/** Peripheral CTIMER2 base address */
3153#define CTIMER2_BASE (0x40028000u)
3154/** Peripheral CTIMER2 base pointer */
3155#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
3156/** Peripheral CTIMER3 base address */
3157#define CTIMER3_BASE (0x40048000u)
3158/** Peripheral CTIMER3 base pointer */
3159#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
3160/** Peripheral CTIMER4 base address */
3161#define CTIMER4_BASE (0x40049000u)
3162/** Peripheral CTIMER4 base pointer */
3163#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
3164/** Array initializer of CTIMER peripheral base addresses */
3165#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
3166/** Array initializer of CTIMER peripheral base pointers */
3167#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
3168/** Interrupt vectors for the CTIMER peripheral type */
3169#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
3170
3171/*!
3172 * @}
3173 */ /* end of group CTIMER_Peripheral_Access_Layer */
3174
3175
3176/* ----------------------------------------------------------------------------
3177 -- DMA Peripheral Access Layer
3178 ---------------------------------------------------------------------------- */
3179
3180/*!
3181 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3182 * @{
3183 */
3184
3185/** DMA - Register Layout Typedef */
3186typedef struct {
3187 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
3188 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
3189 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
3190 uint8_t RESERVED_0[20];
3191 struct { /* offset: 0x20, array step: 0x5C */
3192 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
3193 uint8_t RESERVED_0[4];
3194 __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
3195 uint8_t RESERVED_1[4];
3196 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
3197 uint8_t RESERVED_2[4];
3198 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
3199 uint8_t RESERVED_3[4];
3200 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
3201 uint8_t RESERVED_4[4];
3202 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
3203 uint8_t RESERVED_5[4];
3204 __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
3205 uint8_t RESERVED_6[4];
3206 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
3207 uint8_t RESERVED_7[4];
3208 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
3209 uint8_t RESERVED_8[4];
3210 __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
3211 uint8_t RESERVED_9[4];
3212 __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
3213 uint8_t RESERVED_10[4];
3214 __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
3215 } COMMON[1];
3216 uint8_t RESERVED_1[900];
3217 struct { /* offset: 0x400, array step: 0x10 */
3218 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
3219 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
3220 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
3221 uint8_t RESERVED_0[4];
3222 } CHANNEL[32];
3223} DMA_Type;
3224
3225/* ----------------------------------------------------------------------------
3226 -- DMA Register Masks
3227 ---------------------------------------------------------------------------- */
3228
3229/*!
3230 * @addtogroup DMA_Register_Masks DMA Register Masks
3231 * @{
3232 */
3233
3234/*! @name CTRL - DMA control. */
3235/*! @{ */
3236#define DMA_CTRL_ENABLE_MASK (0x1U)
3237#define DMA_CTRL_ENABLE_SHIFT (0U)
3238/*! ENABLE - DMA controller master enable.
3239 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
3240 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
3241 * 0b1..Enabled. The DMA controller is enabled.
3242 */
3243#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
3244/*! @} */
3245
3246/*! @name INTSTAT - Interrupt status. */
3247/*! @{ */
3248#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
3249#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
3250/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
3251 * 0b0..Not pending. No enabled interrupts are pending.
3252 * 0b1..Pending. At least one enabled interrupt is pending.
3253 */
3254#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
3255#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
3256#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
3257/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
3258 * 0b0..Not pending. No error interrupts are pending.
3259 * 0b1..Pending. At least one error interrupt is pending.
3260 */
3261#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
3262/*! @} */
3263
3264/*! @name SRAMBASE - SRAM address of the channel configuration table. */
3265/*! @{ */
3266#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
3267#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
3268/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
3269 * table must begin on a 512 byte boundary.
3270 */
3271#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
3272/*! @} */
3273
3274/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
3275/*! @{ */
3276#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
3277#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
3278/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
3279 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
3280 */
3281#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
3282/*! @} */
3283
3284/* The count of DMA_COMMON_ENABLESET */
3285#define DMA_COMMON_ENABLESET_COUNT (1U)
3286
3287/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
3288/*! @{ */
3289#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
3290#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
3291/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
3292 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
3293 * are reserved.
3294 */
3295#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
3296/*! @} */
3297
3298/* The count of DMA_COMMON_ENABLECLR */
3299#define DMA_COMMON_ENABLECLR_COUNT (1U)
3300
3301/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
3302/*! @{ */
3303#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
3304#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
3305/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3306 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
3307 */
3308#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
3309/*! @} */
3310
3311/* The count of DMA_COMMON_ACTIVE */
3312#define DMA_COMMON_ACTIVE_COUNT (1U)
3313
3314/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
3315/*! @{ */
3316#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
3317#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
3318/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
3319 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
3320 */
3321#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
3322/*! @} */
3323
3324/* The count of DMA_COMMON_BUSY */
3325#define DMA_COMMON_BUSY_COUNT (1U)
3326
3327/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
3328/*! @{ */
3329#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
3330#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
3331/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
3332 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
3333 * not active. 1 = error interrupt is active.
3334 */
3335#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
3336/*! @} */
3337
3338/* The count of DMA_COMMON_ERRINT */
3339#define DMA_COMMON_ERRINT_COUNT (1U)
3340
3341/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
3342/*! @{ */
3343#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
3344#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
3345/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
3346 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
3347 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
3348 */
3349#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
3350/*! @} */
3351
3352/* The count of DMA_COMMON_INTENSET */
3353#define DMA_COMMON_INTENSET_COUNT (1U)
3354
3355/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
3356/*! @{ */
3357#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
3358#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
3359/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
3360 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
3361 * reserved.
3362 */
3363#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
3364/*! @} */
3365
3366/* The count of DMA_COMMON_INTENCLR */
3367#define DMA_COMMON_INTENCLR_COUNT (1U)
3368
3369/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
3370/*! @{ */
3371#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
3372#define DMA_COMMON_INTA_IA_SHIFT (0U)
3373/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3374 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3375 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
3376 */
3377#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
3378/*! @} */
3379
3380/* The count of DMA_COMMON_INTA */
3381#define DMA_COMMON_INTA_COUNT (1U)
3382
3383/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
3384/*! @{ */
3385#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
3386#define DMA_COMMON_INTB_IB_SHIFT (0U)
3387/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
3388 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
3389 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
3390 */
3391#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
3392/*! @} */
3393
3394/* The count of DMA_COMMON_INTB */
3395#define DMA_COMMON_INTB_COUNT (1U)
3396
3397/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
3398/*! @{ */
3399#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
3400#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
3401/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
3402 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
3403 * VALIDPENDING control bit for DMA channel n
3404 */
3405#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
3406/*! @} */
3407
3408/* The count of DMA_COMMON_SETVALID */
3409#define DMA_COMMON_SETVALID_COUNT (1U)
3410
3411/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
3412/*! @{ */
3413#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
3414#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
3415/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
3416 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
3417 * sets the TRIG bit for DMA channel n.
3418 */
3419#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
3420/*! @} */
3421
3422/* The count of DMA_COMMON_SETTRIG */
3423#define DMA_COMMON_SETTRIG_COUNT (1U)
3424
3425/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
3426/*! @{ */
3427#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
3428#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
3429/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
3430 * 1 = aborts DMA operations on channel n.
3431 */
3432#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
3433/*! @} */
3434
3435/* The count of DMA_COMMON_ABORT */
3436#define DMA_COMMON_ABORT_COUNT (1U)
3437
3438/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
3439/*! @{ */
3440#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
3441#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
3442/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
3443 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
3444 * interaction between the peripheral and the DMA controller.
3445 * 0b0..Disabled. Peripheral DMA requests are disabled.
3446 * 0b1..Enabled. Peripheral DMA requests are enabled.
3447 */
3448#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
3449#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
3450#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
3451/*! HWTRIGEN - Hardware Triggering Enable for this channel.
3452 * 0b0..Disabled. Hardware triggering is not used.
3453 * 0b1..Enabled. Use hardware triggering.
3454 */
3455#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
3456#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
3457#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
3458/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
3459 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
3460 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
3461 */
3462#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
3463#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
3464#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
3465/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
3466 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
3467 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
3468 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
3469 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
3470 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
3471 * current BURSTPOWER length are completed.
3472 */
3473#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
3474#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
3475#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
3476/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
3477 * 0b0..Single transfer. Hardware trigger causes a single transfer.
3478 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
3479 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
3480 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
3481 * complete.
3482 */
3483#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
3484#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
3485#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
3486/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
3487 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
3488 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
3489 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
3490 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
3491 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
3492 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
3493 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
3494 * multiple of the burst size.
3495 */
3496#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
3497#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
3498#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
3499/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
3500 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
3501 * could be used to read several sequential registers from a peripheral for each DMA burst,
3502 * reading the same registers again for each burst.
3503 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
3504 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
3505 */
3506#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
3507#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
3508#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
3509/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
3510 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
3511 * example, this could be used to write several sequential registers to a peripheral for each DMA
3512 * burst, writing the same registers again for each burst.
3513 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
3514 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
3515 */
3516#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
3517#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
3518#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
3519/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
3520 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
3521 */
3522#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
3523/*! @} */
3524
3525/* The count of DMA_CHANNEL_CFG */
3526#define DMA_CHANNEL_CFG_COUNT (32U)
3527
3528/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
3529/*! @{ */
3530#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
3531#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
3532/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
3533 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
3534 * 0b0..No effect. No effect on DMA operation.
3535 * 0b1..Valid pending.
3536 */
3537#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
3538#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
3539#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
3540/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
3541 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
3542 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
3543 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
3544 */
3545#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
3546/*! @} */
3547
3548/* The count of DMA_CHANNEL_CTLSTAT */
3549#define DMA_CHANNEL_CTLSTAT_COUNT (32U)
3550
3551/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
3552/*! @{ */
3553#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
3554#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
3555/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
3556 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
3557 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
3558 * 0b1..Valid. The current channel descriptor is considered valid.
3559 */
3560#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
3561#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
3562#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
3563/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current