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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/LPC54018M.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/LPC54018M.h
new file mode 100644
index 000000000..f24f110ae
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/LPC54018M.h
@@ -0,0 +1,21391 @@
+/*
+** ###################################################################
+**     Processors:          LPC54018J2MET180
+**                          LPC54018J4MET180
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54018JxM/LPC54S018JxM User manual Rev.1.0 20 September 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b200304
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54018M
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018M.h
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief CMSIS Peripheral Access Layer for LPC54018M
+ *
+ * CMSIS Peripheral Access Layer for LPC54018M
+ */
+
+#ifndef _LPC54018M_H_
+#define _LPC54018M_H_                            /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  FLEXCOMM10_IRQn              = 30,               /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56                /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54018M.h"          /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestFlexcomm0Rx          = 0U,          /**< Flexcomm Interface 0 RX/I2C Slave */
+    kDmaRequestFlexcomm0Tx          = 1U,          /**< Flexcomm Interface 0 TX/I2C Master */
+    kDmaRequestFlexcomm1Rx          = 2U,          /**< Flexcomm Interface 1 RX/I2C Slave */
+    kDmaRequestFlexcomm1Tx          = 3U,          /**< Flexcomm Interface 1 TX/I2C Master */
+    kDmaRequestFlexcomm2Rx          = 4U,          /**< Flexcomm Interface 2 RX/I2C Slave */
+    kDmaRequestFlexcomm2Tx          = 5U,          /**< Flexcomm Interface 2 TX/I2C Master */
+    kDmaRequestFlexcomm3Rx          = 6U,          /**< Flexcomm Interface 3 RX/I2C Slave */
+    kDmaRequestFlexcomm3Tx          = 7U,          /**< Flexcomm Interface 3 TX/I2C Master */
+    kDmaRequestFlexcomm4Rx          = 8U,          /**< Flexcomm Interface 4 RX/I2C Slave */
+    kDmaRequestFlexcomm4Tx          = 9U,          /**< Flexcomm Interface 4 TX/I2C Master */
+    kDmaRequestFlexcomm5Rx          = 10U,         /**< Flexcomm Interface 5 RX/I2C Slave */
+    kDmaRequestFlexcomm5Tx          = 11U,         /**< Flexcomm Interface 5 TX/I2C Master */
+    kDmaRequestFlexcomm6Rx          = 12U,         /**< Flexcomm Interface 6 RX/I2C Slave */
+    kDmaRequestFlexcomm6Tx          = 13U,         /**< Flexcomm Interface 6 TX/I2C Master */
+    kDmaRequestFlexcomm7Rx          = 14U,         /**< Flexcomm Interface 7 RX/I2C Slave */
+    kDmaRequestFlexcomm7Tx          = 15U,         /**< Flexcomm Interface 7 TX/I2C Master */
+    kDmaRequestDMIC0                = 16U,         /**< Digital microphone interface 0 channel 0 */
+    kDmaRequestDMIC1                = 17U,         /**< Digital microphone interface 0 channel 1 */
+    kDmaRequestSPIFI                = 18U,         /**< SPI Flash Interface */
+    kDmaRequestSHA                  = 19U,         /**< Secure Hash Algorithm */
+    kDmaRequestFlexcomm8Rx          = 20U,         /**< Flexcomm Interface 8 RX/I2C Slave */
+    kDmaRequestFlexcomm8Tx          = 21U,         /**< Flexcomm Interface 8 TX/I2C Slave */
+    kDmaRequestFlexcomm9Rx          = 22U,         /**< Flexcomm Interface 9 RX/I2C Slave */
+    kDmaRequestFlexcomm9Tx          = 23U,         /**< Flexcomm Interface 9 TX/I2C Slave */
+    kDmaRequestSMARTCARD0_RX        = 24U,         /**< SMARTCARD0 RX */
+    kDmaRequestSMARTCARD0_TX        = 25U,         /**< SMARTCARD0 TX */
+    kDmaRequestSMARTCARD1_RX        = 26U,         /**< SMARTCARD1 RX */
+    kDmaRequestSMARTCARD1_TX        = 27U,         /**< SMARTCARD1 TX */
+    kDmaRequestFlexcomm10Rx         = 28U,         /**< Flexcomm Interface 10 RX */
+    kDmaRequestFlexcomm10Tx         = 29U,         /**< Flexcomm Interface 10 TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+/*! @{ */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
+ *    the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
+ *    software should program the smallest value in this field that yields this maximum clock rate or
+ *    slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
+ *    be desirable. This field is ignored in the asynchronous operating mode.
+ */
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+/*! ASYNMODE - Select clock mode.
+ *  0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
+ *       the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
+ *       eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
+ *       In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
+ *       input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
+ *       pulse.
+ *  0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
+ */
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
+ *    conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
+ *    selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
+ *    the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
+ *    results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
+ *    for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
+ *    clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
+ *  0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
+ */
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
+ *    error is not a concern in the application.
+ *  0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
+ *       offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
+ *       be warranted periodically - especially if operating conditions have changed.
+ *  0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
+ *       particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
+ */
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
+ *    is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
+ *    and the output impedance of the analog source, longer sampling times may be required. See
+ *    Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
+ *    seven, by which the sample period will be extended. The total conversion time will increase by
+ *    the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
+ *    complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
+ *    be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
+ *    require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
+ *    cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
+ *    extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
+ *    22 ADC clocks.
+ */
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+/*! @} */
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+/*! @{ */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+/*! SEL - Selects the input source for channel 0. All other values are reserved.
+ *  0b00..ADC0_IN0 function.
+ *  0b11..Internal temperature sensor.
+ */
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+/*! @{ */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
+ *    sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
+ *    included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
+ *    and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
+ *    software command, ADC conversions will be performed on each enabled channel, in sequence,
+ *    beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
+ *    is LOW. It is allowed to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
+ *    sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
+ *    to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
+ *    order to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ *  0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
+ *  0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
+ */
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
+ *    flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
+ *    conversion. There are slightly different criteria for whether or not this bit can be set
+ *    depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
+ *    Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
+ *    synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
+ *    Whether this bit is set or not, a trigger pulse must be maintained for at least one system
+ *    clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
+ *    bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
+ *    will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
+ *    on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
+ *    maintained for one system clock period.
+ *  0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
+ *  0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
+ */
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
+ *    behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
+ *    bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
+ *    conversion sequence. It will consequently always read back as a zero.
+ */
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
+ *    through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
+ *    can be halted by clearing this bit. The sequence currently in progress will be completed before
+ *    conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
+ */
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
+ *    single conversion on the next channel in the sequence instead of the default response of
+ *    launching an entire sequence of conversions. Once all of the channels comprising a sequence have
+ *    been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
+ *    channel. Interrupt generation will still occur either after each individual conversion or at
+ *    the end of the entire sequence, depending on the state of the MODE bit.
+ */
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+/*! LOWPRIO - Set priority for sequence A.
+ *  0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
+ *  0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
+ *       software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
+ *       currently in progress will be terminated. The A sequence that was interrupted will automatically resume
+ *       after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
+ *       conversion sequence will resume from that point.
+ */
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
+ *    will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
+ *    conversion, or the individual channel result registers at the end of the entire sequence. Impacts
+ *    when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
+ *    overrun conditions contribute to an overrun interrupt as described below.
+ *  0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
+ *       conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
+ *       OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
+ *       if enabled.
+ *  0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
+ *       conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
+ *       this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
+ *       interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
+ */
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
+ *    taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
+ *    (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
+ *    immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
+ *    should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
+ *    state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
+ *    triggered immediately upon being enabled.
+ *  0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
+ *       n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
+ *       re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
+ *  0b1..Enabled. Sequence n is enabled.
+ */
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+/*! @{ */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
+ *    performed under conversion sequence associated with this register. The result is a binary
+ *    fraction representing the voltage on the currently-selected input channel as it falls within the
+ *    range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
+ *    than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
+ *    was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
+ *    result has not yet been read.
+ */
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
+ *    within the range established by the designated threshold comparison registers (THRn_LOW and
+ *    THRn_HIGH).
+ */
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
+ *    crossing of the threshold level established by the designated LOW threshold comparison register
+ *    (THRn_LOW) and, if so, in what direction the crossing occurred.
+ */
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
+ *    identifies channel 0, 0001 channel 1, etc.).
+ */
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
+ *    previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
+ *    with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
+ *    interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
+ *    to '0' (and if the overrun interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
+ *    into the RESULT field. It is cleared whenever this register is read. This bit will cause a
+ *    conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
+ *    sequence is set to 0 (and if the interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+/*! @{ */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
+ *    on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
+ *    as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
+ *    the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
+ *    the voltage on the input was close to, equal to, or greater than that on VREFP.
+ */
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
+ *    was greater than or equal to the value programmed into the designated LOW threshold register
+ *    (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
+ *    programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
+ *    completed conversion was greater than the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x3 = Reserved.
+ */
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
+ *    most recent completed conversion on this channel had the same relationship (above or below) to
+ *    the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
+ *    previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
+ *    Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
+ *    previous sample on this channel was above the threshold value established by the designated LOW
+ *    threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
+ *    Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
+ *    - i.e. the previous sample on this channel was below the threshold value established by the
+ *    designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
+ */
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
+ *    relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
+ *    register, etc)
+ */
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
+ *    overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
+ *    is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
+ *    the data related to this channel is read from either of the global SEQn_GDAT registers. This
+ *    bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
+ *    the overrun interrupt is enabled. While it is allowed to include the same channels in both
+ *    conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
+ *    data registers associated with any of the channels that are shared between the two sequences. Any
+ *    erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
+ *    cleared whenever this register is read or when the data related to this channel is read from
+ *    either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
+ *    both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
+ *    the data registers associated with any of the channels that are shared between the two
+ *    sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+/*! @{ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+/*! CH0_THRSEL - Threshold select for channel 0.
+ *  0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
+ *  0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
+ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+/*! @} */
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+/*! @{ */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+/*! SEQA_INTEN - Sequence A interrupt enable.
+ *  0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
+ *       conversions, depending on the MODE bit in the SEQA_CTRL register.
+ */
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+/*! SEQB_INTEN - Sequence B interrupt enable.
+ *  0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
+ *       conversions, depending on the MODE bit in the SEQB_CTRL register.
+ */
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+/*! OVR_INTEN - Overrun interrupt enable.
+ *  0b0..Disabled. The overrun interrupt is disabled.
+ *  0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
+ *       data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
+ *       sequence is 0, then an overrun in the global data register for that sequence will also cause this
+ *       interrupt/DMA trigger to be asserted.
+ */
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
+ *  0b00..Disabled.
+ *  0b01..Outside threshold.
+ *  0b10..Crossing threshold.
+ *  0b11..Reserved
+ */
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+/*! @} */
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+/*! @{ */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
+ *    a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
+ *    writing a 1.
+ */
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
+ */
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
+ */
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
+ */
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
+ */
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
+ */
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
+ */
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
+ */
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
+ */
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
+ */
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
+ */
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
+ */
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
+ */
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
+ */
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
+ */
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
+ *    automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
+ *    is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
+ *    automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
+ *    is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
+ *    the lower bits of this register are set to 1 (due to an enabled out-of-range or
+ *    threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
+ *    individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
+ *    when all of the individual threshold flags are cleared via writing 1s to those bits.
+ */
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
+ *    registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
+ *    is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
+ *    interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
+ *    of the individual overrun bits have been cleared via reading the corresponding data registers.
+ */
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+/*! @} */
+
+/*! @name STARTUP - ADC Startup register. */
+/*! @{ */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
+ *    automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
+ *    after the ADC is powered up (typically by altering a system-level ADC power control bit).
+ */
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
+ *    will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
+ *    calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
+ *    required if a calibration is not performed. It will also reload the stored calibration value from
+ *    a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
+ *    ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
+ *    an ADC dummy conversion cycle is required. It should not be set during the same write that
+ *    sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
+ *    when the 'dummy' conversion cycle completes.
+ */
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+/*! @} */
+
+/*! @name CALIB - ADC Calibration register. */
+/*! @{ */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
+ *    only be set to a '1' by software. It is cleared automatically when the calibration cycle
+ *    completes.
+ */
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
+ *    enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
+ *    powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
+ *    determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
+ *    register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
+ *    Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
+ *    required for calibration.
+ */
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
+ *    during last calibration cycle. This value is not typically of any use to the user.
+ */
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+/*! SEL - Clock source for asynchronous clock source selector A
+ *  0b00..Main clock (main_clk)
+ *  0b01..FRO 12 MHz (fro_12m)
+ *  0b10..Audio PLL clock.(AUDPLL_BYPASS)
+ *  0b11..fc6 fclk (fc6_fclk)
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DBTP;                              /**< Data Bit Timing Prescaler Register, offset: 0xC */
+  __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
+  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
+  __I  uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
+  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
+  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
+       uint8_t RESERVED_2[16];
+  __I  uint32_t ECR;                               /**< Error Counter Register, offset: 0x40 */
+  __I  uint32_t PSR;                               /**< Protocol Status Register, offset: 0x44 */
+  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator Register, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x50 */
+  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
+  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
+  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
+       uint8_t RESERVED_4[32];
+  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
+  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
+  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
+  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
+  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
+  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
+  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+  __I  uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
+  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
+  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
+  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
+  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
+  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+  __I  uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
+  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
+  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+  __I  uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+  __I  uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+       uint8_t RESERVED_6[8];
+  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
+  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
+  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+       uint8_t RESERVED_7[260];
+  __IO uint32_t MRBA;                              /**< CAN Message RAM Base Address, offset: 0x200 */
+       uint8_t RESERVED_8[508];
+  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
+       uint8_t RESERVED_9[508];
+  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+/*! @{ */
+#define CAN_DBTP_DSJW_MASK                       (0xFU)
+#define CAN_DBTP_DSJW_SHIFT                      (0U)
+/*! DSJW - Data (re)synchronization jump width.
+ */
+#define CAN_DBTP_DSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK                     (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT                    (4U)
+/*! DTSEG2 - Data time segment after sample point.
+ */
+#define CAN_DBTP_DTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK                     (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT                    (8U)
+/*! DTSEG1 - Data time segment before sample point.
+ */
+#define CAN_DBTP_DTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK                       (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT                      (16U)
+/*! DBRP - Data bit rate prescaler.
+ */
+#define CAN_DBTP_DBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK                        (0x800000U)
+#define CAN_DBTP_TDC_SHIFT                       (23U)
+/*! TDC - Transmitter delay compensation.
+ */
+#define CAN_DBTP_TDC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+/*! @} */
+
+/*! @name TEST - Test Register */
+/*! @{ */
+#define CAN_TEST_LBCK_MASK                       (0x10U)
+#define CAN_TEST_LBCK_SHIFT                      (4U)
+/*! LBCK - Loop back mode.
+ */
+#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK                         (0x60U)
+#define CAN_TEST_TX_SHIFT                        (5U)
+/*! TX - Control of transmit pin.
+ */
+#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK                         (0x80U)
+#define CAN_TEST_RX_SHIFT                        (7U)
+/*! RX - Monitors the actual value of the CAN_RXD.
+ */
+#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+/*! @} */
+
+/*! @name CCCR - CC Control Register */
+/*! @{ */
+#define CAN_CCCR_INIT_MASK                       (0x1U)
+#define CAN_CCCR_INIT_SHIFT                      (0U)
+/*! INIT - Initialization.
+ */
+#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK                        (0x2U)
+#define CAN_CCCR_CCE_SHIFT                       (1U)
+/*! CCE - Configuration change enable.
+ */
+#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK                        (0x4U)
+#define CAN_CCCR_ASM_SHIFT                       (2U)
+/*! ASM - Restricted operational mode.
+ */
+#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK                        (0x8U)
+#define CAN_CCCR_CSA_SHIFT                       (3U)
+/*! CSA - Clock Stop Acknowledge.
+ */
+#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK                        (0x10U)
+#define CAN_CCCR_CSR_SHIFT                       (4U)
+/*! CSR - Clock Stop Request.
+ */
+#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK                        (0x20U)
+#define CAN_CCCR_MON_SHIFT                       (5U)
+/*! MON - Bus monitoring mode.
+ */
+#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK                        (0x40U)
+#define CAN_CCCR_DAR_SHIFT                       (6U)
+/*! DAR - Disable automatic retransmission.
+ */
+#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK                       (0x80U)
+#define CAN_CCCR_TEST_SHIFT                      (7U)
+/*! TEST - Test mode enable.
+ */
+#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK                       (0x100U)
+#define CAN_CCCR_FDOE_SHIFT                      (8U)
+/*! FDOE - CAN FD operation enable.
+ */
+#define CAN_CCCR_FDOE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK                       (0x200U)
+#define CAN_CCCR_BRSE_SHIFT                      (9U)
+/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
+ */
+#define CAN_CCCR_BRSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
+#define CAN_CCCR_PXHD_MASK                       (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT                      (12U)
+/*! PXHD - Protocol exception handling disable.
+ */
+#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK                       (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT                      (13U)
+/*! EFBI - Edge filtering during bus integration.
+ */
+#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK                        (0x4000U)
+#define CAN_CCCR_TXP_SHIFT                       (14U)
+/*! TXP - Transmit pause.
+ */
+#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK                       (0x8000U)
+#define CAN_CCCR_NISO_SHIFT                      (15U)
+/*! NISO - Non ISO operation.
+ */
+#define CAN_CCCR_NISO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
+/*! @} */
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+/*! @{ */
+#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
+/*! NTSEG2 - Nominal time segment after sample point.
+ */
+#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
+/*! NTSEG1 - Nominal time segment before sample point.
+ */
+#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT                      (16U)
+/*! NBRP - Nominal bit rate prescaler.
+ */
+#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT                      (25U)
+/*! NSJW - Nominal (re)synchronization jump width.
+ */
+#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+/*! @} */
+
+/*! @name TSCC - Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_TSCC_TSS_MASK                        (0x3U)
+#define CAN_TSCC_TSS_SHIFT                       (0U)
+/*! TSS - Timestamp select.
+ */
+#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK                        (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT                       (16U)
+/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
+ */
+#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+/*! @} */
+
+/*! @name TSCV - Timestamp Counter Value */
+/*! @{ */
+#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT                       (0U)
+/*! TSC - Timestamp counter.
+ */
+#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+/*! @} */
+
+/*! @name TOCC - Timeout Counter Configuration */
+/*! @{ */
+#define CAN_TOCC_ETOC_MASK                       (0x1U)
+#define CAN_TOCC_ETOC_SHIFT                      (0U)
+/*! ETOC - Enable timeout counter.
+ */
+#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK                        (0x6U)
+#define CAN_TOCC_TOS_SHIFT                       (1U)
+/*! TOS - Timeout select.
+ */
+#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT                       (16U)
+/*! TOP - Timeout period.
+ */
+#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+/*! @} */
+
+/*! @name TOCV - Timeout Counter Value */
+/*! @{ */
+#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT                       (0U)
+/*! TOC - Timeout counter.
+ */
+#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter Register */
+/*! @{ */
+#define CAN_ECR_TEC_MASK                         (0xFFU)
+#define CAN_ECR_TEC_SHIFT                        (0U)
+/*! TEC - Transmit error counter.
+ */
+#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK                         (0x7F00U)
+#define CAN_ECR_REC_SHIFT                        (8U)
+/*! REC - Receive error counter.
+ */
+#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK                          (0x8000U)
+#define CAN_ECR_RP_SHIFT                         (15U)
+/*! RP - Receive error passive.
+ */
+#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK                         (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT                        (16U)
+/*! CEL - CAN error logging.
+ */
+#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+/*! @} */
+
+/*! @name PSR - Protocol Status Register */
+/*! @{ */
+#define CAN_PSR_LEC_MASK                         (0x7U)
+#define CAN_PSR_LEC_SHIFT                        (0U)
+/*! LEC - Last error code.
+ */
+#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK                         (0x18U)
+#define CAN_PSR_ACT_SHIFT                        (3U)
+/*! ACT - Activity.
+ */
+#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK                          (0x20U)
+#define CAN_PSR_EP_SHIFT                         (5U)
+/*! EP - Error Passive.
+ */
+#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK                          (0x40U)
+#define CAN_PSR_EW_SHIFT                         (6U)
+/*! EW - Warning status.
+ */
+#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK                          (0x80U)
+#define CAN_PSR_BO_SHIFT                         (7U)
+/*! BO - Bus Off Status.
+ */
+#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK                        (0x700U)
+#define CAN_PSR_DLEC_SHIFT                       (8U)
+/*! DLEC - Data phase last error code.
+ */
+#define CAN_PSR_DLEC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK                        (0x800U)
+#define CAN_PSR_RESI_SHIFT                       (11U)
+/*! RESI - ESI flag of the last received CAN FD message.
+ */
+#define CAN_PSR_RESI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK                        (0x1000U)
+#define CAN_PSR_RBRS_SHIFT                       (12U)
+/*! RBRS - BRS flag of last received CAN FD message.
+ */
+#define CAN_PSR_RBRS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK                        (0x2000U)
+#define CAN_PSR_RFDF_SHIFT                       (13U)
+/*! RFDF - Received a CAN FD message.
+ */
+#define CAN_PSR_RFDF(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
+#define CAN_PSR_PXE_MASK                         (0x4000U)
+#define CAN_PSR_PXE_SHIFT                        (14U)
+/*! PXE - Protocol exception event.
+ */
+#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT                       (16U)
+/*! TDCV - Transmitter delay compensation value.
+ */
+#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+/*! @} */
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+/*! @{ */
+#define CAN_TDCR_TDCF_MASK                       (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT                      (0U)
+/*! TDCF - Transmitter delay compensation filter window length.
+ */
+#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT                      (8U)
+/*! TDCO - Transmitter delay compensation offset.
+ */
+#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+/*! @} */
+
+/*! @name IR - Interrupt Register */
+/*! @{ */
+#define CAN_IR_RF0N_MASK                         (0x1U)
+#define CAN_IR_RF0N_SHIFT                        (0U)
+/*! RF0N - Rx FIFO 0 new message.
+ */
+#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK                         (0x2U)
+#define CAN_IR_RF0W_SHIFT                        (1U)
+/*! RF0W - Rx FIFO 0 watermark reached.
+ */
+#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK                         (0x4U)
+#define CAN_IR_RF0F_SHIFT                        (2U)
+/*! RF0F - Rx FIFO 0 full.
+ */
+#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK                         (0x8U)
+#define CAN_IR_RF0L_SHIFT                        (3U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK                         (0x10U)
+#define CAN_IR_RF1N_SHIFT                        (4U)
+/*! RF1N - Rx FIFO 1 new message.
+ */
+#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK                         (0x20U)
+#define CAN_IR_RF1W_SHIFT                        (5U)
+/*! RF1W - Rx FIFO 1 watermark reached.
+ */
+#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK                         (0x40U)
+#define CAN_IR_RF1F_SHIFT                        (6U)
+/*! RF1F - Rx FIFO 1 full.
+ */
+#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK                         (0x80U)
+#define CAN_IR_RF1L_SHIFT                        (7U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK                          (0x100U)
+#define CAN_IR_HPM_SHIFT                         (8U)
+/*! HPM - High priority message.
+ */
+#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK                           (0x200U)
+#define CAN_IR_TC_SHIFT                          (9U)
+/*! TC - Transmission completed.
+ */
+#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK                          (0x400U)
+#define CAN_IR_TCF_SHIFT                         (10U)
+/*! TCF - Transmission cancellation finished.
+ */
+#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK                          (0x800U)
+#define CAN_IR_TFE_SHIFT                         (11U)
+/*! TFE - Tx FIFO empty.
+ */
+#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK                         (0x1000U)
+#define CAN_IR_TEFN_SHIFT                        (12U)
+/*! TEFN - Tx event FIFO new entry.
+ */
+#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK                         (0x2000U)
+#define CAN_IR_TEFW_SHIFT                        (13U)
+/*! TEFW - Tx event FIFO watermark reached.
+ */
+#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK                         (0x4000U)
+#define CAN_IR_TEFF_SHIFT                        (14U)
+/*! TEFF - Tx event FIFO full.
+ */
+#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK                         (0x8000U)
+#define CAN_IR_TEFL_SHIFT                        (15U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK                          (0x10000U)
+#define CAN_IR_TSW_SHIFT                         (16U)
+/*! TSW - Timestamp wraparound.
+ */
+#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK                         (0x20000U)
+#define CAN_IR_MRAF_SHIFT                        (17U)
+/*! MRAF - Message RAM access failure.
+ */
+#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK                          (0x40000U)
+#define CAN_IR_TOO_SHIFT                         (18U)
+/*! TOO - Timeout occurred.
+ */
+#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK                          (0x80000U)
+#define CAN_IR_DRX_SHIFT                         (19U)
+/*! DRX - Message stored in dedicated Rx buffer.
+ */
+#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK                          (0x100000U)
+#define CAN_IR_BEC_SHIFT                         (20U)
+/*! BEC - Bit error corrected.
+ */
+#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK                          (0x200000U)
+#define CAN_IR_BEU_SHIFT                         (21U)
+/*! BEU - Bit error uncorrected.
+ */
+#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK                          (0x400000U)
+#define CAN_IR_ELO_SHIFT                         (22U)
+/*! ELO - Error logging overflow.
+ */
+#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK                           (0x800000U)
+#define CAN_IR_EP_SHIFT                          (23U)
+/*! EP - Error passive.
+ */
+#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK                           (0x1000000U)
+#define CAN_IR_EW_SHIFT                          (24U)
+/*! EW - Warning status.
+ */
+#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK                           (0x2000000U)
+#define CAN_IR_BO_SHIFT                          (25U)
+/*! BO - Bus_Off Status.
+ */
+#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK                          (0x4000000U)
+#define CAN_IR_WDI_SHIFT                         (26U)
+/*! WDI - Watchdog interrupt.
+ */
+#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK                          (0x8000000U)
+#define CAN_IR_PEA_SHIFT                         (27U)
+/*! PEA - Protocol error in arbitration phase.
+ */
+#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK                          (0x10000000U)
+#define CAN_IR_PED_SHIFT                         (28U)
+/*! PED - Protocol error in data phase.
+ */
+#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK                          (0x20000000U)
+#define CAN_IR_ARA_SHIFT                         (29U)
+/*! ARA - Access to reserved address.
+ */
+#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable */
+/*! @{ */
+#define CAN_IE_RF0NE_MASK                        (0x1U)
+#define CAN_IE_RF0NE_SHIFT                       (0U)
+/*! RF0NE - Rx FIFO 0 new message interrupt enable.
+ */
+#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK                        (0x2U)
+#define CAN_IE_RF0WE_SHIFT                       (1U)
+/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK                        (0x4U)
+#define CAN_IE_RF0FE_SHIFT                       (2U)
+/*! RF0FE - Rx FIFO 0 full interrupt enable.
+ */
+#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK                        (0x8U)
+#define CAN_IE_RF0LE_SHIFT                       (3U)
+/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
+ */
+#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK                        (0x10U)
+#define CAN_IE_RF1NE_SHIFT                       (4U)
+/*! RF1NE - Rx FIFO 1 new message interrupt enable.
+ */
+#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK                        (0x20U)
+#define CAN_IE_RF1WE_SHIFT                       (5U)
+/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK                        (0x40U)
+#define CAN_IE_RF1FE_SHIFT                       (6U)
+/*! RF1FE - Rx FIFO 1 full interrupt enable.
+ */
+#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK                        (0x80U)
+#define CAN_IE_RF1LE_SHIFT                       (7U)
+/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
+ */
+#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK                         (0x100U)
+#define CAN_IE_HPME_SHIFT                        (8U)
+/*! HPME - High priority message interrupt enable.
+ */
+#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK                          (0x200U)
+#define CAN_IE_TCE_SHIFT                         (9U)
+/*! TCE - Transmission completed interrupt enable.
+ */
+#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK                         (0x400U)
+#define CAN_IE_TCFE_SHIFT                        (10U)
+/*! TCFE - Transmission cancellation finished interrupt enable.
+ */
+#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK                         (0x800U)
+#define CAN_IE_TFEE_SHIFT                        (11U)
+/*! TFEE - Tx FIFO empty interrupt enable.
+ */
+#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK                        (0x1000U)
+#define CAN_IE_TEFNE_SHIFT                       (12U)
+/*! TEFNE - Tx event FIFO new entry interrupt enable.
+ */
+#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK                        (0x2000U)
+#define CAN_IE_TEFWE_SHIFT                       (13U)
+/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
+ */
+#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK                        (0x4000U)
+#define CAN_IE_TEFFE_SHIFT                       (14U)
+/*! TEFFE - Tx event FIFO full interrupt enable.
+ */
+#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK                        (0x8000U)
+#define CAN_IE_TEFLE_SHIFT                       (15U)
+/*! TEFLE - Tx event FIFO element lost interrupt enable.
+ */
+#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK                         (0x10000U)
+#define CAN_IE_TSWE_SHIFT                        (16U)
+/*! TSWE - Timestamp wraparound interrupt enable.
+ */
+#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK                        (0x20000U)
+#define CAN_IE_MRAFE_SHIFT                       (17U)
+/*! MRAFE - Message RAM access failure interrupt enable.
+ */
+#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK                         (0x40000U)
+#define CAN_IE_TOOE_SHIFT                        (18U)
+/*! TOOE - Timeout occurred interrupt enable.
+ */
+#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK                         (0x80000U)
+#define CAN_IE_DRXE_SHIFT                        (19U)
+/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
+ */
+#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK                         (0x100000U)
+#define CAN_IE_BECE_SHIFT                        (20U)
+/*! BECE - Bit error corrected interrupt enable.
+ */
+#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK                         (0x200000U)
+#define CAN_IE_BEUE_SHIFT                        (21U)
+/*! BEUE - Bit error uncorrected interrupt enable.
+ */
+#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK                         (0x400000U)
+#define CAN_IE_ELOE_SHIFT                        (22U)
+/*! ELOE - Error logging overflow interrupt enable.
+ */
+#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK                          (0x800000U)
+#define CAN_IE_EPE_SHIFT                         (23U)
+/*! EPE - Error passive interrupt enable.
+ */
+#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK                          (0x1000000U)
+#define CAN_IE_EWE_SHIFT                         (24U)
+/*! EWE - Warning status interrupt enable.
+ */
+#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK                          (0x2000000U)
+#define CAN_IE_BOE_SHIFT                         (25U)
+/*! BOE - Bus_Off Status interrupt enable.
+ */
+#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK                         (0x4000000U)
+#define CAN_IE_WDIE_SHIFT                        (26U)
+/*! WDIE - Watchdog interrupt enable.
+ */
+#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK                         (0x8000000U)
+#define CAN_IE_PEAE_SHIFT                        (27U)
+/*! PEAE - Protocol error in arbitration phase interrupt enable.
+ */
+#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK                         (0x10000000U)
+#define CAN_IE_PEDE_SHIFT                        (28U)
+/*! PEDE - Protocol error in data phase interrupt enable.
+ */
+#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK                         (0x20000000U)
+#define CAN_IE_ARAE_SHIFT                        (29U)
+/*! ARAE - Access to reserved address interrupt enable.
+ */
+#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+/*! @} */
+
+/*! @name ILS - Interrupt Line Select */
+/*! @{ */
+#define CAN_ILS_RF0NL_MASK                       (0x1U)
+#define CAN_ILS_RF0NL_SHIFT                      (0U)
+/*! RF0NL - Rx FIFO 0 new message interrupt line.
+ */
+#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK                       (0x2U)
+#define CAN_ILS_RF0WL_SHIFT                      (1U)
+/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK                       (0x4U)
+#define CAN_ILS_RF0FL_SHIFT                      (2U)
+/*! RF0FL - Rx FIFO 0 full interrupt line.
+ */
+#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK                       (0x8U)
+#define CAN_ILS_RF0LL_SHIFT                      (3U)
+/*! RF0LL - Rx FIFO 0 message lost interrupt line.
+ */
+#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK                       (0x10U)
+#define CAN_ILS_RF1NL_SHIFT                      (4U)
+/*! RF1NL - Rx FIFO 1 new message interrupt line.
+ */
+#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK                       (0x20U)
+#define CAN_ILS_RF1WL_SHIFT                      (5U)
+/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK                       (0x40U)
+#define CAN_ILS_RF1FL_SHIFT                      (6U)
+/*! RF1FL - Rx FIFO 1 full interrupt line.
+ */
+#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK                       (0x80U)
+#define CAN_ILS_RF1LL_SHIFT                      (7U)
+/*! RF1LL - Rx FIFO 1 message lost interrupt line.
+ */
+#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK                        (0x100U)
+#define CAN_ILS_HPML_SHIFT                       (8U)
+/*! HPML - High priority message interrupt line.
+ */
+#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK                         (0x200U)
+#define CAN_ILS_TCL_SHIFT                        (9U)
+/*! TCL - Transmission completed interrupt line.
+ */
+#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK                        (0x400U)
+#define CAN_ILS_TCFL_SHIFT                       (10U)
+/*! TCFL - Transmission cancellation finished interrupt line.
+ */
+#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK                        (0x800U)
+#define CAN_ILS_TFEL_SHIFT                       (11U)
+/*! TFEL - Tx FIFO empty interrupt line.
+ */
+#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK                       (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT                      (12U)
+/*! TEFNL - Tx event FIFO new entry interrupt line.
+ */
+#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK                       (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT                      (13U)
+/*! TEFWL - Tx event FIFO watermark reached interrupt line.
+ */
+#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK                       (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT                      (14U)
+/*! TEFFL - Tx event FIFO full interrupt line.
+ */
+#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK                       (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT                      (15U)
+/*! TEFLL - Tx event FIFO element lost interrupt line.
+ */
+#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK                        (0x10000U)
+#define CAN_ILS_TSWL_SHIFT                       (16U)
+/*! TSWL - Timestamp wraparound interrupt line.
+ */
+#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK                       (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT                      (17U)
+/*! MRAFL - Message RAM access failure interrupt line.
+ */
+#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK                        (0x40000U)
+#define CAN_ILS_TOOL_SHIFT                       (18U)
+/*! TOOL - Timeout occurred interrupt line.
+ */
+#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK                        (0x80000U)
+#define CAN_ILS_DRXL_SHIFT                       (19U)
+/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
+ */
+#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK                        (0x100000U)
+#define CAN_ILS_BECL_SHIFT                       (20U)
+/*! BECL - Bit error corrected interrupt line.
+ */
+#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK                        (0x200000U)
+#define CAN_ILS_BEUL_SHIFT                       (21U)
+/*! BEUL - Bit error uncorrected interrupt line.
+ */
+#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK                        (0x400000U)
+#define CAN_ILS_ELOL_SHIFT                       (22U)
+/*! ELOL - Error logging overflow interrupt line.
+ */
+#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK                         (0x800000U)
+#define CAN_ILS_EPL_SHIFT                        (23U)
+/*! EPL - Error passive interrupt line.
+ */
+#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK                         (0x1000000U)
+#define CAN_ILS_EWL_SHIFT                        (24U)
+/*! EWL - Warning status interrupt line.
+ */
+#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK                         (0x2000000U)
+#define CAN_ILS_BOL_SHIFT                        (25U)
+/*! BOL - Bus_Off Status interrupt line.
+ */
+#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK                        (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT                       (26U)
+/*! WDIL - Watchdog interrupt line.
+ */
+#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK                        (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT                       (27U)
+/*! PEAL - Protocol error in arbitration phase interrupt line.
+ */
+#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK                        (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT                       (28U)
+/*! PEDL - Protocol error in data phase interrupt line.
+ */
+#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK                        (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT                       (29U)
+/*! ARAL - Access to reserved address interrupt line.
+ */
+#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+/*! @} */
+
+/*! @name ILE - Interrupt Line Enable */
+/*! @{ */
+#define CAN_ILE_EINT0_MASK                       (0x1U)
+#define CAN_ILE_EINT0_SHIFT                      (0U)
+/*! EINT0 - Enable interrupt line 0.
+ */
+#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK                       (0x2U)
+#define CAN_ILE_EINT1_SHIFT                      (1U)
+/*! EINT1 - Enable interrupt line 1.
+ */
+#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+/*! @} */
+
+/*! @name GFC - Global Filter Configuration */
+/*! @{ */
+#define CAN_GFC_RRFE_MASK                        (0x1U)
+#define CAN_GFC_RRFE_SHIFT                       (0U)
+/*! RRFE - Reject remote frames extended.
+ */
+#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK                        (0x2U)
+#define CAN_GFC_RRFS_SHIFT                       (1U)
+/*! RRFS - Reject remote frames standard.
+ */
+#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK                        (0xCU)
+#define CAN_GFC_ANFE_SHIFT                       (2U)
+/*! ANFE - Accept non-matching frames extended.
+ */
+#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK                        (0x30U)
+#define CAN_GFC_ANFS_SHIFT                       (4U)
+/*! ANFS - Accept non-matching frames standard.
+ */
+#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+/*! @} */
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+/*! @{ */
+#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
+/*! FLSSA - Filter list standard start address.
+ */
+#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT                      (16U)
+/*! LSS - List size standard 0 = No standard message ID filter.
+ */
+#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+/*! @} */
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+/*! @{ */
+#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT                    (2U)
+/*! FLESA - Filter list extended start address.
+ */
+#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT                      (16U)
+/*! LSE - List size extended 0 = No extended message ID filter.
+ */
+#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+/*! @} */
+
+/*! @name XIDAM - Extended ID AND Mask */
+/*! @{ */
+#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT                     (0U)
+/*! EIDM - Extended ID mask.
+ */
+#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+/*! @} */
+
+/*! @name HPMS - High Priority Message Status */
+/*! @{ */
+#define CAN_HPMS_BIDX_MASK                       (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT                      (0U)
+/*! BIDX - Buffer index.
+ */
+#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK                        (0xC0U)
+#define CAN_HPMS_MSI_SHIFT                       (6U)
+/*! MSI - Message storage indicator.
+ */
+#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT                      (8U)
+/*! FIDX - Filter index.
+ */
+#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK                       (0x8000U)
+#define CAN_HPMS_FLST_SHIFT                      (15U)
+/*! FLST - Filter list.
+ */
+#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+/*! @} */
+
+/*! @name NDAT1 - New Data 1 */
+/*! @{ */
+#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT                       (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+/*! @} */
+
+/*! @name NDAT2 - New Data 2 */
+/*! @{ */
+#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT                       (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+/*! @} */
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+/*! @{ */
+#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT                     (2U)
+/*! F0SA - Rx FIFO 0 start address.
+ */
+#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT                      (16U)
+/*! F0S - Rx FIFO 0 size.
+ */
+#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT                     (24U)
+/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT                     (31U)
+/*! F0OM - FIFO 0 operation mode.
+ */
+#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+/*! @} */
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+/*! @{ */
+#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT                     (0U)
+/*! F0FL - Rx FIFO 0 fill level.
+ */
+#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT                     (8U)
+/*! F0GI - Rx FIFO 0 get index.
+ */
+#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT                     (16U)
+/*! F0PI - Rx FIFO 0 put index.
+ */
+#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT                      (24U)
+/*! F0F - Rx FIFO 0 full.
+ */
+#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT                     (25U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+/*! @} */
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+/*! @{ */
+#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT                     (0U)
+/*! F0AI - Rx FIFO 0 acknowledge index.
+ */
+#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+/*! @} */
+
+/*! @name RXBC - Rx Buffer Configuration */
+/*! @{ */
+#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT                      (2U)
+/*! RBSA - Rx buffer start address.
+ */
+#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+/*! @} */
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+/*! @{ */
+#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT                     (2U)
+/*! F1SA - Rx FIFO 1 start address.
+ */
+#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT                      (16U)
+/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
+ */
+#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT                     (24U)
+/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT                     (31U)
+/*! F1OM - FIFO 1 operation mode.
+ */
+#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+/*! @} */
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+/*! @{ */
+#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT                     (0U)
+/*! F1FL - Rx FIFO 1 fill level.
+ */
+#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT                     (8U)
+/*! F1GI - Rx FIFO 1 get index.
+ */
+#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT                     (16U)
+/*! F1PI - Rx FIFO 1 put index.
+ */
+#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT                      (24U)
+/*! F1F - Rx FIFO 1 full.
+ */
+#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT                     (25U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+/*! @} */
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+/*! @{ */
+#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT                     (0U)
+/*! F1AI - Rx FIFO 1 acknowledge index.
+ */
+#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+/*! @} */
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+/*! @{ */
+#define CAN_RXESC_F0DS_MASK                      (0x7U)
+#define CAN_RXESC_F0DS_SHIFT                     (0U)
+/*! F0DS - Rx FIFO 0 data field size.
+ */
+#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK                      (0x70U)
+#define CAN_RXESC_F1DS_SHIFT                     (4U)
+/*! F1DS - Rx FIFO 1 data field size.
+ */
+#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK                      (0x700U)
+#define CAN_RXESC_RBDS_SHIFT                     (8U)
+/*! RBDS - .
+ */
+#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+/*! @} */
+
+/*! @name TXBC - Tx Buffer Configuration */
+/*! @{ */
+#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT                      (2U)
+/*! TBSA - Tx buffers start address.
+ */
+#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT                      (16U)
+/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
+ */
+#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT                      (24U)
+/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
+ */
+#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT                      (30U)
+/*! TFQM - Tx FIFO/queue mode.
+ */
+#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+/*! @} */
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+/*! @{ */
+#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT                     (8U)
+/*! TFGI - Tx FIFO get index.
+ */
+#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
+/*! TFQPI - Tx FIFO/queue put index.
+ */
+#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT                     (21U)
+/*! TFQF - Tx FIFO/queue full.
+ */
+#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+/*! @} */
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+/*! @{ */
+#define CAN_TXESC_TBDS_MASK                      (0x7U)
+#define CAN_TXESC_TBDS_SHIFT                     (0U)
+/*! TBDS - Tx buffer data field size.
+ */
+#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+/*! @} */
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+/*! @{ */
+#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT                      (0U)
+/*! TRP - Transmission request pending.
+ */
+#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+/*! @} */
+
+/*! @name TXBAR - Tx Buffer Add Request */
+/*! @{ */
+#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT                       (0U)
+/*! AR - Add request.
+ */
+#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+/*! @} */
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+/*! @{ */
+#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT                       (0U)
+/*! CR - Cancellation request.
+ */
+#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+/*! @} */
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+/*! @{ */
+#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT                       (0U)
+/*! TO - Transmission occurred.
+ */
+#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+/*! @} */
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+/*! @{ */
+#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT                       (0U)
+/*! TO - Cancellation finished.
+ */
+#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+/*! @} */
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+/*! @{ */
+#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT                     (0U)
+/*! TIE - Transmission interrupt enable.
+ */
+#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+/*! @} */
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+/*! @{ */
+#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
+/*! CFIE - Cancellation finished interrupt enable.
+ */
+#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+/*! @} */
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+/*! @{ */
+#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT                     (2U)
+/*! EFSA - Event FIFO start address.
+ */
+#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT                      (16U)
+/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
+ */
+#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT                     (24U)
+/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+/*! @} */
+
+/*! @name TXEFS - Tx Event FIFO Status */
+/*! @{ */
+#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT                     (0U)
+/*! EFFL - Event FIFO fill level.
+ */
+#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT                     (8U)
+/*! EFGI - Event FIFO get index.
+ */
+#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT                     (16U)
+/*! EFPI - Event FIFO put index.
+ */
+#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT                      (24U)
+/*! EFF - Event FIFO full.
+ */
+#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT                     (25U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+/*! @} */
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+/*! @{ */
+#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT                     (0U)
+/*! EFAI - Event FIFO acknowledge index.
+ */
+#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+/*! @} */
+
+/*! @name MRBA - CAN Message RAM Base Address */
+/*! @{ */
+#define CAN_MRBA_BA_MASK                         (0xFFFF0000U)
+#define CAN_MRBA_BA_SHIFT                        (16U)
+/*! BA - Base address for the message RAM in the chip memory map.
+ */
+#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+/*! @} */
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT                     (0U)
+/*! ETCP - External timestamp prescaler value.
+ */
+#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT                     (31U)
+/*! ETCE - External timestamp counter enable.
+ */
+#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+/*! @} */
+
+/*! @name ETSCV - External Timestamp Counter Value */
+/*! @{ */
+#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT                     (0U)
+/*! ETSC - External timestamp counter.
+ */
+#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
+ */
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
+ */
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
+ */
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ *    selected bit order and 1's complement pre-processes. A write access to this register will
+ *    overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
+ */
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ *    accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt flag for match channel 0.
+ */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt flag for match channel 1.
+ */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt flag for match channel 2.
+ */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt flag for match channel 3.
+ */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event.
+ */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event.
+ */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event.
+ */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event.
+ */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter enable.
+ *  0b0..Disabled.The counters are disabled.
+ *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter reset.
+ *  0b0..Disabled. Do nothing.
+ *  0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
+ *       the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale counter value.
+ */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
+ *    if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
+ *    Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
+ *    is incremented when the Prescale Counter matches the Prescale Register.
+ *  0b00..Timer Mode. Incremented every rising APB bus clock edge.
+ *  0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
+ *  0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
+ *  0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
+ *    CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
+ *    in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
+ *    programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
+ *    same timer.
+ *  0b00..Channel 0. CAPn.0 for CTIMERn
+ *  0b01..Channel 1. CAPn.1 for CTIMERn
+ *  0b10..Channel 2. CAPn.2 for CTIMERn
+ *  0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
+ *    capture-edge event specified in bits 7:5 occurs.
+ */
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
+ *    timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
+ *    0x3 and 0x6 to 0x7 are reserved.
+ *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+/*! SHADOWW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+/*! ENABLE - DMA controller master enable.
+ *  0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
+ *       disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
+ *  0b1..Enabled. The DMA controller is enabled.
+ */
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status. */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ *  0b0..Not pending. No enabled interrupts are pending.
+ *  0b1..Pending. At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ *  0b0..Not pending. No error interrupts are pending.
+ *  0b1..Pending. At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
+ *    table must begin on a 512 byte boundary.
+ */
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
+ *    the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
+ *    are reserved.
+ */
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
+ */
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
+ */
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
+ *    not active. 1 = error interrupt is active.
+ */
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
+ *    number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
+ *    interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
+ *    corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
+ *    reserved.
+ */
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt A is not active. 1 = the DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt B is not active. 1 = the DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
+ *    = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
+ *    VALIDPENDING control bit for DMA channel n
+ */
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
+ *    of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
+ *    sets the TRIG bit for DMA channel n.
+ */
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
+ *    1 = aborts DMA operations on channel n.
+ */
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
+ *    move, any peripheral DMA request associated with that channel can be disabled to prevent any
+ *    interaction between the peripheral and the DMA controller.
+ *  0b0..Disabled. Peripheral DMA requests are disabled.
+ *  0b1..Enabled. Peripheral DMA requests are enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.
+ *  0b0..Disabled. Hardware triggering is not used.
+ *  0b1..Enabled. Use hardware triggering.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
+ *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
+ *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ *  0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ *       0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
+ *       trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
+ *       is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
+ *       current BURSTPOWER length are completed.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
+ *  0b0..Single transfer. Hardware trigger causes a single transfer.
+ *  0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
+ *       burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
+ *       hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
+ *       complete.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
+ *    SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
+ *    When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
+ *    transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
+ *    contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
+ *    Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
+ *    1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
+ *    total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
+ *    multiple of the burst size.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
+ *    'wrapped', meaning that the source address range for each burst will be the same. As an example, this
+ *    could be used to read several sequential registers from a peripheral for each DMA burst,
+ *    reading the same registers again for each burst.
+ *  0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
+ *    'wrapped', meaning that the destination address range for each burst will be the same. As an
+ *    example, this could be used to write several sequential registers to a peripheral for each DMA
+ *    burst, writing the same registers again for each burst.
+ *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are p