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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/drivers/fsl_clock.h
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/drivers/fsl_clock.h
@@ -0,0 +1,1293 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020 , NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_CLOCK_H_
11#define _FSL_CLOCK_H_
12
13#include "fsl_common.h"
14
15/*! @addtogroup clock */
16/*! @{ */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24/*! @name Driver version */
25/*@{*/
26/*! @brief CLOCK driver version 2.3.2. */
27#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
28/*@}*/
29
30/*! @brief Configure whether driver controls clock
31 *
32 * When set to 0, peripheral drivers will enable clock in initialize function
33 * and disable clock in de-initialize function. When set to 1, peripheral
34 * driver will not control the clock, application could control the clock out of
35 * the driver.
36 *
37 * @note All drivers share this feature switcher. If it is set to 1, application
38 * should handle clock enable and disable for all drivers.
39 */
40#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
41#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
42#endif
43
44/*!
45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
46 *
47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
48 * would cache the recent calulation and accelerate the execution to get the
49 * right settings.
50 */
51#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
52#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
53#endif
54
55/* Definition for delay API in clock driver, users can redefine it to the real application. */
56#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
57#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
58#endif
59
60/*! @brief Clock ip name array for ADC. */
61#define ADC_CLOCKS \
62 { \
63 kCLOCK_Adc0 \
64 }
65/*! @brief Clock ip name array for ROM. */
66#define ROM_CLOCKS \
67 { \
68 kCLOCK_Rom \
69 }
70/*! @brief Clock ip name array for SRAM. */
71#define SRAM_CLOCKS \
72 { \
73 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
74 }
75/*! @brief Clock ip name array for FLASH. */
76#define FLASH_CLOCKS \
77 { \
78 kCLOCK_Flash \
79 }
80/*! @brief Clock ip name array for FMC. */
81#define FMC_CLOCKS \
82 { \
83 kCLOCK_Fmc \
84 }
85/*! @brief Clock ip name array for EEPROM. */
86#define EEPROM_CLOCKS \
87 { \
88 kCLOCK_Eeprom \
89 }
90/*! @brief Clock ip name array for SPIFI. */
91#define SPIFI_CLOCKS \
92 { \
93 kCLOCK_Spifi \
94 }
95/*! @brief Clock ip name array for INPUTMUX. */
96#define INPUTMUX_CLOCKS \
97 { \
98 kCLOCK_InputMux \
99 }
100/*! @brief Clock ip name array for IOCON. */
101#define IOCON_CLOCKS \
102 { \
103 kCLOCK_Iocon \
104 }
105/*! @brief Clock ip name array for GPIO. */
106#define GPIO_CLOCKS \
107 { \
108 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
109 }
110/*! @brief Clock ip name array for PINT. */
111#define PINT_CLOCKS \
112 { \
113 kCLOCK_Pint \
114 }
115/*! @brief Clock ip name array for GINT. */
116#define GINT_CLOCKS \
117 { \
118 kCLOCK_Gint, kCLOCK_Gint \
119 }
120/*! @brief Clock ip name array for DMA. */
121#define DMA_CLOCKS \
122 { \
123 kCLOCK_Dma \
124 }
125/*! @brief Clock ip name array for CRC. */
126#define CRC_CLOCKS \
127 { \
128 kCLOCK_Crc \
129 }
130/*! @brief Clock ip name array for WWDT. */
131#define WWDT_CLOCKS \
132 { \
133 kCLOCK_Wwdt \
134 }
135/*! @brief Clock ip name array for RTC. */
136#define RTC_CLOCKS \
137 { \
138 kCLOCK_Rtc \
139 }
140/*! @brief Clock ip name array for ADC0. */
141#define ADC0_CLOCKS \
142 { \
143 kCLOCK_Adc0 \
144 }
145/*! @brief Clock ip name array for MRT. */
146#define MRT_CLOCKS \
147 { \
148 kCLOCK_Mrt \
149 }
150/*! @brief Clock ip name array for RIT. */
151#define RIT_CLOCKS \
152 { \
153 kCLOCK_Rit \
154 }
155/*! @brief Clock ip name array for SCT0. */
156#define SCT_CLOCKS \
157 { \
158 kCLOCK_Sct0 \
159 }
160/*! @brief Clock ip name array for MCAN. */
161#define MCAN_CLOCKS \
162 { \
163 kCLOCK_Mcan0, kCLOCK_Mcan1 \
164 }
165/*! @brief Clock ip name array for UTICK. */
166#define UTICK_CLOCKS \
167 { \
168 kCLOCK_Utick \
169 }
170/*! @brief Clock ip name array for FLEXCOMM. */
171#define FLEXCOMM_CLOCKS \
172 { \
173 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
174 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \
175 }
176/*! @brief Clock ip name array for LPUART. */
177#define LPUART_CLOCKS \
178 { \
179 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
180 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
181 }
182
183/*! @brief Clock ip name array for BI2C. */
184#define BI2C_CLOCKS \
185 { \
186 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
187 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
188 }
189/*! @brief Clock ip name array for LSPI. */
190#define LPSI_CLOCKS \
191 { \
192 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
193 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
194 }
195/*! @brief Clock ip name array for FLEXI2S. */
196#define FLEXI2S_CLOCKS \
197 { \
198 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
199 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
200 }
201/*! @brief Clock ip name array for DMIC. */
202#define DMIC_CLOCKS \
203 { \
204 kCLOCK_DMic \
205 }
206/*! @brief Clock ip name array for CT32B. */
207#define CTIMER_CLOCKS \
208 { \
209 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
210 }
211/*! @brief Clock ip name array for LCD. */
212#define LCD_CLOCKS \
213 { \
214 kCLOCK_Lcd \
215 }
216/*! @brief Clock ip name array for SDIO. */
217#define SDIO_CLOCKS \
218 { \
219 kCLOCK_Sdio \
220 }
221/*! @brief Clock ip name array for USBRAM. */
222#define USBRAM_CLOCKS \
223 { \
224 kCLOCK_UsbRam1 \
225 }
226/*! @brief Clock ip name array for EMC. */
227#define EMC_CLOCKS \
228 { \
229 kCLOCK_Emc \
230 }
231/*! @brief Clock ip name array for ETH. */
232#define ETH_CLOCKS \
233 { \
234 kCLOCK_Eth \
235 }
236/*! @brief Clock ip name array for AES. */
237#define AES_CLOCKS \
238 { \
239 kCLOCK_Aes \
240 }
241/*! @brief Clock ip name array for OTP. */
242#define OTP_CLOCKS \
243 { \
244 kCLOCK_Otp \
245 }
246/*! @brief Clock ip name array for RNG. */
247#define RNG_CLOCKS \
248 { \
249 kCLOCK_Rng \
250 }
251/*! @brief Clock ip name array for USBHMR0. */
252#define USBHMR0_CLOCKS \
253 { \
254 kCLOCK_Usbhmr0 \
255 }
256/*! @brief Clock ip name array for USBHSL0. */
257#define USBHSL0_CLOCKS \
258 { \
259 kCLOCK_Usbhsl0 \
260 }
261/*! @brief Clock ip name array for SHA0. */
262#define SHA0_CLOCKS \
263 { \
264 kCLOCK_Sha0 \
265 }
266/*! @brief Clock ip name array for SMARTCARD. */
267#define SMARTCARD_CLOCKS \
268 { \
269 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
270 }
271/*! @brief Clock ip name array for USBD. */
272#define USBD_CLOCKS \
273 { \
274 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
275 }
276/*! @brief Clock ip name array for USBH. */
277#define USBH_CLOCKS \
278 { \
279 kCLOCK_Usbh1 \
280 }
281/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
282/*------------------------------------------------------------------------------
283 clock_ip_name_t definition:
284------------------------------------------------------------------------------*/
285
286#define CLK_GATE_REG_OFFSET_SHIFT 8U
287#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
288#define CLK_GATE_BIT_SHIFT_SHIFT 0U
289#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
290
291#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
292 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
293 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
294
295#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
296#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
297
298#define AHB_CLK_CTRL0 0
299#define AHB_CLK_CTRL1 1
300#define AHB_CLK_CTRL2 2
301#define ASYNC_CLK_CTRL0 3
302
303/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
304typedef enum _clock_ip_name
305{
306 kCLOCK_IpInvalid = 0U,
307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
308 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
309 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
310 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
311 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
312 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
313 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
314 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
315 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
316 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
317 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
318 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
319 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
320 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
321 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
322 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
323 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
324 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
325 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
326 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
327 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
328 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
329 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
330 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
331 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
332 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
333 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
334 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
335 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
336 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
337 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
338 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
339 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
340 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
341 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
342 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
343 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
344 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
345 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
346 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
347 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
348 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
349 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
350 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
351 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
352 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
353 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
354 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
355 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
356 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
357 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
358 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
359 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
360 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
361 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
362 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
363 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
364 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
365 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
366 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
367 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
368 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
369 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
370 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
371 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
372 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
373 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
374 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
375 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
376 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
377 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
378 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
379 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
380 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
381 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
382 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
383 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
384 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
385 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
386 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
387 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
388 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
389 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
390 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
391 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
392 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
393 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
394 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
395 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
396 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
397 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
398 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
399 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
400 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
401 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
402 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
403 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
404 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
405 kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
406
407 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
408 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
409} clock_ip_name_t;
410
411/*! @brief Clock name used to get clock frequency. */
412typedef enum _clock_name
413{
414 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
415 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
416 kCLOCK_ClockOut, /*!< CLOCKOUT */
417 kCLOCK_FroHf, /*!< FRO48/96 */
418 kCLOCK_UsbPll, /*!< USB1 PLL */
419 kCLOCK_Mclk, /*!< MCLK */
420 kCLOCK_Fro12M, /*!< FRO12M */
421 kCLOCK_ExtClk, /*!< External Clock */
422 kCLOCK_PllOut, /*!< PLL Output */
423 kCLOCK_UsbClk, /*!< USB input */
424 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
425 kCLOCK_Frg, /*!< Frg Clock */
426 kCLOCK_AsyncApbClk, /*!< Async APB clock */
427} clock_name_t;
428
429/**
430 * Clock source selections for the asynchronous APB clock
431 */
432typedef enum _async_clock_src
433{
434 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
435 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
436 kCLOCK_AsyncAudioPllClk,
437 kCLOCK_AsyncI2cClkFc6,
438
439} async_clock_src_t;
440
441/*! @brief Clock Mux Switches
442 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
443 * starting from LSB upwards
444 *
445 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
446 *
447 */
448
449#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
450#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
451#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
452
453#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
454#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
455#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
456#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
457#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
458
459#define CM_STICKCLKSEL 0
460#define CM_MAINCLKSELA 1
461#define CM_MAINCLKSELB 2
462#define CM_CLKOUTCLKSELA 3
463#define CM_SYSPLLCLKSEL 5
464#define CM_AUDPLLCLKSEL 7
465#define CM_SPIFICLKSEL 9
466#define CM_ADCASYNCCLKSEL 10
467#define CM_USB0CLKSEL 11
468#define CM_USB1CLKSEL 12
469#define CM_FXCOMCLKSEL0 13
470#define CM_FXCOMCLKSEL1 14
471#define CM_FXCOMCLKSEL2 15
472#define CM_FXCOMCLKSEL3 16
473#define CM_FXCOMCLKSEL4 17
474#define CM_FXCOMCLKSEL5 18
475#define CM_FXCOMCLKSEL6 19
476#define CM_FXCOMCLKSEL7 20
477#define CM_FXCOMCLKSEL8 21
478#define CM_FXCOMCLKSEL9 22
479#define CM_FXCOMCLKSEL10 23
480#define CM_MCLKCLKSEL 25
481#define CM_FRGCLKSEL 27
482#define CM_DMICCLKSEL 28
483#define CM_SCTCLKSEL 29
484#define CM_LCDCLKSEL 30
485#define CM_SDIOCLKSEL 31
486
487#define CM_ASYNCAPB 32U
488
489typedef enum _clock_attach_id
490{
491
492 kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),
493 kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1),
494 kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2),
495 kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3),
496 kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7),
497
498 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
499 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
500 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
501 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
502 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
503 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
504
505 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
506 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
507 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
508 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
509 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
510 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
511 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
512 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
513
514 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
515 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
516 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
517 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
518 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
519
520 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
521 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
522 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
523
524 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
525 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
526 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
527 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
528 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
529 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
530
531 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
532 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
533 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
534 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
535 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
536
537 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
538 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
539 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
540 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
541
542 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
543 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
544 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
545 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
546
547 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
548 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
549 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
550 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
551 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
552 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
553
554 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
555 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
556 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
557 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
558 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
559 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
560
561 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
562 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
563 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
564 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
565 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
566 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
567
568 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
569 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
570 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
571 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
572 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
573 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
574
575 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
576 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
577 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
578 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
579 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
580 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
581
582 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
583 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
584 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
585 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
586 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
587 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
588
589 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
590 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
591 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
592 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
593 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
594 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
595
596 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
597 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
598 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
599 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
600 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
601 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
602
603 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
604 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
605 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
606 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
607 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
608 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
609
610 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
611 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
612 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
613 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
614 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
615 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
616
617 kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0),
618 kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1),
619 kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2),
620 kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3),
621 kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),
622 kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7),
623
624 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
625 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
626 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
627
628 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
629 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
630 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
631 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
632 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
633
634 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
635 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
636 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
637 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
638 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
639 kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
640 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
641
642 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
643 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
644 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
645 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
646 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
647
648 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
649 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
650 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
651 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
652
653 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
654 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
655 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
656 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
657 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
658 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
659
660 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
661 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
662 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
663 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
664 kNONE_to_NONE = (int)0x80000000U,
665} clock_attach_id_t;
666
667/* Clock dividers */
668typedef enum _clock_div_name
669{
670 kCLOCK_DivSystickClk = 0,
671 kCLOCK_DivArmTrClkDiv = 1,
672 kCLOCK_DivCan0Clk = 2,
673 kCLOCK_DivCan1Clk = 3,
674 kCLOCK_DivSmartCard0Clk = 4,
675 kCLOCK_DivSmartCard1Clk = 5,
676 kCLOCK_DivAhbClk = 32,
677 kCLOCK_DivClkOut = 33,
678 kCLOCK_DivFrohfClk = 34,
679 kCLOCK_DivSpifiClk = 36,
680 kCLOCK_DivAdcAsyncClk = 37,
681 kCLOCK_DivUsb0Clk = 38,
682 kCLOCK_DivUsb1Clk = 39,
683 kCLOCK_DivFrg = 40,
684 kCLOCK_DivDmicClk = 42,
685 kCLOCK_DivMClk = 43,
686 kCLOCK_DivLcdClk = 44,
687 kCLOCK_DivSctClk = 45,
688 kCLOCK_DivEmcClk = 46,
689 kCLOCK_DivSdioClk = 47
690} clock_div_name_t;
691
692/*******************************************************************************
693 * API
694 ******************************************************************************/
695
696#if defined(__cplusplus)
697extern "C" {
698#endif /* __cplusplus */
699
700static inline void CLOCK_EnableClock(clock_ip_name_t clk)
701{
702 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
703 if (index < 3UL)
704 {
705 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
706 }
707 else
708 {
709 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
710 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
711 }
712}
713
714static inline void CLOCK_DisableClock(clock_ip_name_t clk)
715{
716 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
717 if (index < 3UL)
718 {
719 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
720 }
721 else
722 {
723 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
724 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
725 }
726}
727
728/**
729 * @brief
730 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
731 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
732 * output is enabled.
733 * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
734 * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
735 * implemented in ROM code and the FROHF TRIM value is stored in OTP
736 *
737 * @param froFreq target fro frequency.
738 * @return Nothing
739 */
740
741void CLOCK_SetupFROClocking(uint32_t froFreq);
742
743/**
744 * @brief Configure the clock selection muxes.
745 * @param connection : Clock to be configured.
746 * @return Nothing
747 */
748void CLOCK_AttachClk(clock_attach_id_t connection);
749/**
750 * @brief Get the actual clock attach id.
751 * This fuction uses the offset in input attach id, then it reads the actual source value in
752 * the register and combine the offset to obtain an actual attach id.
753 * @param attachId : Clock attach id to get.
754 * @return Clock source value.
755 */
756clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
757/**
758 * @brief Setup peripheral clock dividers.
759 * @param div_name : Clock divider name
760 * @param divided_by_value: Value to be divided
761 * @param reset : Whether to reset the divider counter.
762 * @return Nothing
763 */
764void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
765
766/*! @brief Return Frequency of selected clock
767 * @return Frequency of selected clock
768 */
769uint32_t CLOCK_GetFreq(clock_name_t clockName);
770/*! @brief Return Frequency of FRO 12MHz
771 * @return Frequency of FRO 12MHz
772 */
773uint32_t CLOCK_GetFro12MFreq(void);
774/*! @brief Return Frequency of ClockOut
775 * @return Frequency of ClockOut
776 */
777uint32_t CLOCK_GetClockOutClkFreq(void);
778/*! @brief Return Frequency of Spifi Clock
779 * @return Frequency of Spifi.
780 */
781uint32_t CLOCK_GetSpifiClkFreq(void);
782/*! @brief Return Frequency of Adc Clock
783 * @return Frequency of Adc Clock.
784 */
785uint32_t CLOCK_GetAdcClkFreq(void);
786/*! brief Return Frequency of MCAN Clock
787 * param MCanSel : 0U: MCAN0; 1U: MCAN1
788 * return Frequency of MCAN Clock
789 */
790uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
791/*! @brief Return Frequency of Usb0 Clock
792 * @return Frequency of Usb0 Clock.
793 */
794uint32_t CLOCK_GetUsb0ClkFreq(void);
795/*! @brief Return Frequency of Usb1 Clock
796 * @return Frequency of Usb1 Clock.
797 */
798uint32_t CLOCK_GetUsb1ClkFreq(void);
799/*! @brief Return Frequency of MClk Clock
800 * @return Frequency of MClk Clock.
801 */
802uint32_t CLOCK_GetMclkClkFreq(void);
803/*! @brief Return Frequency of SCTimer Clock
804 * @return Frequency of SCTimer Clock.
805 */
806uint32_t CLOCK_GetSctClkFreq(void);
807/*! @brief Return Frequency of SDIO Clock
808 * @return Frequency of SDIO Clock.
809 */
810uint32_t CLOCK_GetSdioClkFreq(void);
811/*! @brief Return Frequency of LCD Clock
812 * @return Frequency of LCD Clock.
813 */
814uint32_t CLOCK_GetLcdClkFreq(void);
815/*! @brief Return Frequency of LCD CLKIN Clock
816 * @return Frequency of LCD CLKIN Clock.
817 */
818uint32_t CLOCK_GetLcdClkIn(void);
819/*! @brief Return Frequency of External Clock
820 * @return Frequency of External Clock. If no external clock is used returns 0.
821 */
822uint32_t CLOCK_GetExtClkFreq(void);
823/*! @brief Return Frequency of Watchdog Oscillator
824 * @return Frequency of Watchdog Oscillator
825 */
826uint32_t CLOCK_GetWdtOscFreq(void);
827/*! @brief Return Frequency of High-Freq output of FRO
828 * @return Frequency of High-Freq output of FRO
829 */
830uint32_t CLOCK_GetFroHfFreq(void);
831/*! @brief Return Frequency of frg
832 * @return Frequency of FRG
833 */
834uint32_t CLOCK_GetFrgClkFreq(void);
835/*! @brief Return Frequency of dmic
836 * @return Frequency of DMIC
837 */
838uint32_t CLOCK_GetDmicClkFreq(void);
839
840/*!
841 * @brief Set FRG Clk
842 * @return
843 * 1: if set FRG CLK successfully.
844 * 0: if set FRG CLK fail.
845 */
846uint32_t CLOCK_SetFRGClock(uint32_t freq);
847
848/*! @brief Return Frequency of PLL
849 * @return Frequency of PLL
850 */
851uint32_t CLOCK_GetPllOutFreq(void);
852/*! @brief Return Frequency of USB PLL
853 * @return Frequency of PLL
854 */
855uint32_t CLOCK_GetUsbPllOutFreq(void);
856/*! @brief Return Frequency of AUDIO PLL
857 * @return Frequency of PLL
858 */
859uint32_t CLOCK_GetAudioPllOutFreq(void);
860/*! @brief Return Frequency of 32kHz osc
861 * @return Frequency of 32kHz osc
862 */
863uint32_t CLOCK_GetOsc32KFreq(void);
864/*! @brief Return Frequency of Core System
865 * @return Frequency of Core System
866 */
867uint32_t CLOCK_GetCoreSysClkFreq(void);
868/*! @brief Return Frequency of I2S MCLK Clock
869 * @return Frequency of I2S MCLK Clock
870 */
871uint32_t CLOCK_GetI2SMClkFreq(void);
872/*! @brief Return Frequency of Flexcomm functional Clock
873 * @return Frequency of Flexcomm functional Clock
874 */
875uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
876
877/*! @brief return FRG Clk
878 * @return Frequency of FRG CLK.
879 */
880uint32_t CLOCK_GetFRGInputClock(void);
881/*! @brief Return Asynchronous APB Clock source
882 * @return Asynchronous APB CLock source
883 */
884__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
885{
886 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
887}
888/*! @brief Return Frequency of Asynchronous APB Clock
889 * @return Frequency of Asynchronous APB Clock Clock
890 */
891uint32_t CLOCK_GetAsyncApbClkFreq(void);
892/*! @brief Return EMC source
893 * @return EMC source
894 */
895__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
896{
897 uint32_t freqtmp;
898
899 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
900 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
901}
902/*! @brief Return Audio PLL input clock rate
903 * @return Audio PLL input clock rate
904 */
905uint32_t CLOCK_GetAudioPLLInClockRate(void);
906/*! @brief Return System PLL input clock rate
907 * @return System PLL input clock rate
908 */
909uint32_t CLOCK_GetSystemPLLInClockRate(void);
910
911/*! @brief Return System PLL output clock rate
912 * @param recompute : Forces a PLL rate recomputation if true
913 * @return System PLL output clock rate
914 * @note The PLL rate is cached in the driver in a variable as
915 * the rate computation function can take some time to perform. It
916 * is recommended to use 'false' with the 'recompute' parameter.
917 */
918uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
919
920/*! @brief Return System AUDIO PLL output clock rate
921 * @param recompute : Forces a AUDIO PLL rate recomputation if true
922 * @return System AUDIO PLL output clock rate
923 * @note The AUDIO PLL rate is cached in the driver in a variable as
924 * the rate computation function can take some time to perform. It
925 * is recommended to use 'false' with the 'recompute' parameter.
926 */
927uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
928
929/*! @brief Return System USB PLL output clock rate
930 * @param recompute : Forces a USB PLL rate recomputation if true
931 * @return System USB PLL output clock rate
932 * @note The USB PLL rate is cached in the driver in a variable as
933 * the rate computation function can take some time to perform. It
934 * is recommended to use 'false' with the 'recompute' parameter.
935 */
936uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
937
938/*! @brief Enables and disables PLL bypass mode
939 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
940 * @return System PLL output clock rate
941 */
942__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
943{
944 if (bypass)
945 {
946 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
947 }
948 else
949 {
950 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
951 }
952}
953
954/*! @brief Check if PLL is locked or not
955 * @return true if the PLL is locked, false if not locked
956 */
957__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
958{
959 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
960}
961
962/*! @brief Check if USB PLL is locked or not
963 * @return true if the USB PLL is locked, false if not locked
964 */
965__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
966{
967 return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
968}
969
970/*! @brief Check if AUDIO PLL is locked or not
971 * @return true if the AUDIO PLL is locked, false if not locked
972 */
973__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
974{
975 return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
976}
977
978/*! @brief Enables and disables SYS OSC
979 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
980 */
981__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
982{
983 if (enable)
984 {
985 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
986 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
987 }
988
989 else
990 {
991 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
992 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
993 }
994}
995
996/*! @brief Store the current PLL rate
997 * @param rate: Current rate of the PLL
998 * @return Nothing
999 **/
1000void CLOCK_SetStoredPLLClockRate(uint32_t rate);
1001
1002/*! @brief Store the current AUDIO PLL rate
1003 * @param rate: Current rate of the PLL
1004 * @return Nothing
1005 **/
1006void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
1007
1008/*! @brief PLL configuration structure flags for 'flags' field
1009 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1010 *
1011 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1012 * configuration structure must be assigned with the expected PLL frequency. If the
1013 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1014 * function and the driver will determine the PLL rate from the currently selected
1015 * PLL source. This flag might be used to configure the PLL input clock more accurately
1016 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1017 *
1018 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1019 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1020 * are not used.<br>
1021 */
1022#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1023#define PLL_CONFIGFLAG_FORCENOFRACT \
1024 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
1025 SS hardware */
1026
1027/*! @brief PLL configuration structure
1028 *
1029 * This structure can be used to configure the settings for a PLL
1030 * setup structure. Fill in the desired configuration for the PLL
1031 * and call the PLL setup function to fill in a PLL setup structure.
1032 */
1033typedef struct _pll_config
1034{
1035 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1036 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1037 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1038} pll_config_t;
1039
1040/*! @brief PLL setup structure flags for 'flags' field
1041 * These flags control how the PLL setup function sets up the PLL
1042 */
1043#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1044#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1045#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1046
1047/*! @brief PLL setup structure
1048 * This structure can be used to pre-build a PLL setup configuration
1049 * at run-time and quickly set the PLL to the configuration. It can be
1050 * populated with the PLL setup function. If powering up or waiting
1051 * for PLL lock, the PLL input clock source should be configured prior
1052 * to PLL setup.
1053 */
1054typedef struct _pll_setup
1055{
1056 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
1057 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
1058 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
1059 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
1060 uint32_t pllRate; /*!< Acutal PLL rate */
1061 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
1062 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1063} pll_setup_t;
1064
1065/*! @brief PLL status definitions
1066 */
1067typedef enum _pll_error
1068{
1069 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1070 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1071 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1072 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1073 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1074 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1075 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1076 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1077} pll_error_t;
1078
1079/*! @brief USB clock source definition. */
1080typedef enum _clock_usb_src
1081{
1082 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
1083 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
1084 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1085 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
1086
1087 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
1088 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
1089} clock_usb_src_t;
1090
1091/*! @brief USB PDEL Divider. */
1092typedef enum _usb_pll_psel
1093{
1094 pSel_Divide_1 = 0U,
1095 pSel_Divide_2,
1096 pSel_Divide_4,
1097 pSel_Divide_8
1098} usb_pll_psel;
1099
1100/*! @brief PLL setup structure
1101 * This structure can be used to pre-build a USB PLL setup configuration
1102 * at run-time and quickly set the usb PLL to the configuration. It can be
1103 * populated with the USB PLL setup function. If powering up or waiting
1104 * for USB PLL lock, the PLL input clock source should be configured prior
1105 * to USB PLL setup.
1106 */
1107typedef struct _usb_pll_setup
1108{
1109 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
1110 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
1111 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
1112 bool direct; /*!< USB PLL CCO output control */
1113 bool bypass; /*!< USB PLL inout clock bypass control */
1114 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
1115 uint32_t inputRate; /*!< USB PLL input rate */
1116} usb_pll_setup_t;
1117
1118/*! @brief Return System PLL output clock rate from setup structure
1119 * @param pSetup : Pointer to a PLL setup structure
1120 * @return System PLL output clock rate the setup structure will generate
1121 */
1122uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
1123
1124/*! @brief Return System AUDIO PLL output clock rate from setup structure
1125 * @param pSetup : Pointer to a PLL setup structure
1126 * @return System PLL output clock rate the setup structure will generate
1127 */
1128uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
1129
1130/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
1131 * @param pSetup : Pointer to a PLL setup structure
1132 * @return System PLL output clock rate the setup structure will generate
1133 */
1134uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
1135
1136/*! @brief Return System USB PLL output clock rate from setup structure
1137 * @param pSetup : Pointer to a PLL setup structure
1138 * @return System PLL output clock rate the setup structure will generate
1139 */
1140uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
1141
1142/*! @brief Set PLL output based on the passed PLL setup data
1143 * @param pControl : Pointer to populated PLL control structure to generate setup with
1144 * @param pSetup : Pointer to PLL setup structure to be filled
1145 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1146 * @note Actual frequency for setup may vary from the desired frequency based on the
1147 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1148 */
1149pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1150
1151/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
1152 * @param pControl : Pointer to populated PLL control structure to generate setup with
1153 * @param pSetup : Pointer to PLL setup structure to be filled
1154 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1155 * @note Actual frequency for setup may vary from the desired frequency based on the
1156 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1157 */
1158pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1159
1160/*! @brief Set PLL output from PLL setup structure (precise frequency)
1161 * @param pSetup : Pointer to populated PLL setup structure
1162 * @param flagcfg : Flag configuration for PLL config structure
1163 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1164 * @note This function will power off the PLL, setup the PLL with the
1165 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1166 * and adjust system voltages to the new PLL rate. The function will not
1167 * alter any source clocks (ie, main systen clock) that may use the PLL,
1168 * so these should be setup prior to and after exiting the function.
1169 */
1170pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1171
1172/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
1173 * @param pSetup : Pointer to populated PLL setup structure
1174 * @param flagcfg : Flag configuration for PLL config structure
1175 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1176 * @note This function will power off the PLL, setup the PLL with the
1177 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1178 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1179 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1180 * so these should be setup prior to and after exiting the function.
1181 */
1182pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1183
1184/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
1185 * frequency)
1186 * @param pSetup : Pointer to populated PLL setup structure
1187 * @param flagcfg : Flag configuration for PLL config structure
1188 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1189 * @note This function will power off the PLL, setup the PLL with the
1190 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1191 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1192 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1193 * so these should be setup prior to and after exiting the function.
1194 */
1195pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
1196
1197/**
1198 * @brief Set PLL output from PLL setup structure (precise frequency)
1199 * @param pSetup : Pointer to populated PLL setup structure
1200 * @return kStatus_PLL_Success on success, or PLL setup error code
1201 * @note This function will power off the PLL, setup the PLL with the
1202 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1203 * and adjust system voltages to the new PLL rate. The function will not
1204 * alter any source clocks (ie, main systen clock) that may use the PLL,
1205 * so these should be setup prior to and after exiting the function.
1206 */
1207pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
1208
1209/**
1210 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
1211 * @param pSetup : Pointer to populated PLL setup structure
1212 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
1213 * @note This function will power off the PLL, setup the Audio PLL with the
1214 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
1215 * and adjust system voltages to the new PLL rate. The function will not
1216 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
1217 * so these should be setup prior to and after exiting the function.
1218 */
1219pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
1220
1221/**
1222 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
1223 * @param pSetup : Pointer to populated USB PLL setup structure
1224 * @return kStatus_PLL_Success on success, or USB PLL setup error code
1225 * @note This function will power off the USB PLL, setup the PLL with the
1226 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
1227 * and adjust system voltages to the new USB PLL rate. The function will not
1228 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
1229 * so these should be setup prior to and after exiting the function.
1230 */
1231pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
1232
1233/*! @brief Set PLL output based on the multiplier and input frequency
1234 * @param multiply_by : multiplier
1235 * @param input_freq : Clock input frequency of the PLL
1236 * @return Nothing
1237 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1238 * function does not disable or enable PLL power, wait for PLL lock,
1239 * or adjust system voltages. These must be done in the application.
1240 * The function will not alter any source clocks (ie, main systen clock)
1241 * that may use the PLL, so these should be setup prior to and after
1242 * exiting the function.
1243 */
1244void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
1245
1246/*! @brief Disable USB clock.
1247 *
1248 * Disable USB clock.
1249 */
1250static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1251{
1252 CLOCK_DisableClock(clk);
1253}
1254
1255/*! @brief Enable USB Device FS clock.
1256 * @param src : clock source
1257 * @param freq: clock frequency
1258 * Enable USB Device Full Speed clock.
1259 */
1260bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1261
1262/*! @brief Enable USB HOST FS clock.
1263 * @param src : clock source
1264 * @param freq: clock frequency
1265 * Enable USB HOST Full Speed clock.
1266 */
1267bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
1268
1269/*! @brief Set the current Usb PLL Rate
1270 */
1271void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
1272
1273/*! @brief Enable USB Device HS clock.
1274 * @param src : clock source
1275 * @param freq: clock frequency
1276 * Enable USB Device High Speed clock.
1277 */
1278bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1279
1280/*! @brief Enable USB HOST HS clock.
1281 * @param src : clock source
1282 * @param freq: clock frequency
1283 * Enable USB HOST High Speed clock.
1284 */
1285bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
1286
1287#if defined(__cplusplus)
1288}
1289#endif /* __cplusplus */
1290
1291/*! @} */
1292
1293#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:45 +0100