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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/system_LPC54018M.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54018M/system_LPC54018M.c
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1/*
2** ###################################################################
3** Processors: LPC54018J2MET180
4** LPC54018J4MET180
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC54018JxM/LPC54S018JxM User manual Rev.1.0 20 September 2018
12** Version: rev. 1.2, 2017-06-08
13** Build: b201015
14**
15** Abstract:
16** Provides a system configuration function and a global variable that
17** contains the system frequency. It configures the device and initializes
18** the oscillator (PLL) that is part of the microcontroller device.
19**
20** Copyright 2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2016-08-12)
31** Initial version.
32** - rev. 1.1 (2016-11-25)
33** Update CANFD and Classic CAN register.
34** Add MAC TIMERSTAMP registers.
35** - rev. 1.2 (2017-06-08)
36** Remove RTC_CTRL_RTC_OSC_BYPASS.
37** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
38** Remove RESET and HALT from SYSCON_AHBCLKDIV.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file LPC54018M
45 * @version 1.2
46 * @date 2017-06-08
47 * @brief Device specific configuration file for LPC54018M (implementation file)
48 *
49 * Provides a system configuration function and a global variable that contains
50 * the system frequency. It configures the device and initializes the oscillator
51 * (PLL) that is part of the microcontroller device.
52 */
53
54#include <stdint.h>
55#include "fsl_device_registers.h"
56
57#define NVALMAX (0x100)
58#define PVALMAX (0x20)
59#define MVALMAX (0x8000)
60#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
61#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
62#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
63#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
64#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
65#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
66
67static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
68 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
69/* Get WATCH DOG Clk */
70static uint32_t getWdtOscFreq(void)
71{
72 uint8_t freq_sel, div_sel;
73 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
74 {
75 return 0U;
76 }
77 else
78 {
79 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
80 freq_sel =
81 wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
82 return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
83 }
84}
85/* Find decoded N value for raw NDEC value */
86static uint32_t pllDecodeN(uint32_t NDEC)
87{
88 uint32_t n, x, i;
89
90 /* Find NDec */
91 switch (NDEC)
92 {
93 case 0x3FF:
94 n = 0UL;
95 break;
96 case 0x302:
97 n = 1UL;
98 break;
99 case 0x202:
100 n = 2UL;
101 break;
102 default:
103 x = 0x080UL;
104 n = 0xFFFFFFFFUL;
105 for (i = NVALMAX; i >= 3UL; i--)
106 {
107 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
108 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
109 {
110 /* Decoded value of NDEC */
111 n = i;
112 }
113 if (n != 0xFFFFFFFFUL)
114 {
115 break;
116 }
117 }
118 break;
119 }
120 return n;
121}
122
123/* Find decoded P value for raw PDEC value */
124static uint32_t pllDecodeP(uint32_t PDEC)
125{
126 uint32_t p, x, i;
127 /* Find PDec */
128 switch (PDEC)
129 {
130 case 0x7F:
131 p = 0UL;
132 break;
133 case 0x62:
134 p = 1UL;
135 break;
136 case 0x42:
137 p = 2UL;
138 break;
139 default:
140 x = 0x10UL;
141 p = 0xFFFFFFFFUL;
142 for (i = PVALMAX; i >= 3UL; i--)
143 {
144 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
145 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
146 {
147 /* Decoded value of PDEC */
148 p = i;
149 }
150 if (p != 0xFFFFFFFFUL)
151 {
152 break;
153 }
154 }
155 break;
156 }
157 return p;
158}
159
160/* Find decoded M value for raw MDEC value */
161static uint32_t pllDecodeM(uint32_t MDEC)
162{
163 uint32_t m, i, x;
164
165 /* Find MDec */
166 switch (MDEC)
167 {
168 case 0x1FFFF:
169 m = 0UL;
170 break;
171 case 0x18003:
172 m = 1UL;
173 break;
174 case 0x10003:
175 m = 2UL;
176 break;
177 default:
178 x = 0x04000UL;
179 m = 0xFFFFFFFFUL;
180 for (i = MVALMAX; i >= 3UL; i--)
181 {
182 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
183 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
184 {
185 /* Decoded value of MDEC */
186 m = i;
187 }
188 if (m != 0xFFFFFFFFUL)
189 {
190 break;
191 }
192 }
193 break;
194 }
195 return m;
196}
197
198/* Get predivider (N) from PLL NDEC setting */
199static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
200{
201 uint32_t preDiv = 1;
202
203 /* Direct input is not used? */
204 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
205 {
206 /* Decode NDEC value to get (N) pre divider */
207 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
208 if (preDiv == 0UL)
209 {
210 preDiv = 1;
211 }
212 }
213 /* Adjusted by 1, directi is used to bypass */
214 return preDiv;
215}
216
217/* Get postdivider (P) from PLL PDEC setting */
218static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
219{
220 uint32_t postDiv = 1;
221
222 /* Direct input is not used? */
223 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
224 {
225 /* Decode PDEC value to get (P) post divider */
226 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
227 if (postDiv == 0UL)
228 {
229 postDiv = 2;
230 }
231 }
232 /* Adjusted by 1, directo is used to bypass */
233 return postDiv;
234}
235
236/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
237static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
238{
239 uint32_t mMult = 1;
240
241 /* Decode MDEC value to get (M) multiplier */
242 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
243 if (mMult == 0UL)
244 {
245 mMult = 1;
246 }
247 return mMult;
248}
249
250/* ----------------------------------------------------------------------------
251 -- Core clock
252 ---------------------------------------------------------------------------- */
253
254uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
255
256/* ----------------------------------------------------------------------------
257 -- SystemInit()
258 ---------------------------------------------------------------------------- */
259
260void SystemInit(void)
261{
262#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
263 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
264#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
265
266#if defined(__MCUXPRESSO)
267 extern void (*const g_pfnVectors[])(void);
268 SCB->VTOR = (uint32_t)&g_pfnVectors;
269#else
270 extern void *__Vectors;
271 SCB->VTOR = (uint32_t)&__Vectors;
272#endif
273 SYSCON->ARMTRACECLKDIV = 0;
274/* Optionally enable RAM banks that may be off by default at reset */
275#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
276 SYSCON->AHBCLKCTRLSET[0] =
277 SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
278
279#endif
280 SYSCON->MAINCLKSELA = 0U;
281 SYSCON->MAINCLKSELB = 0U;
282 SystemInitHook();
283}
284
285/* ----------------------------------------------------------------------------
286 -- SystemCoreClockUpdate()
287 ---------------------------------------------------------------------------- */
288
289void SystemCoreClockUpdate(void)
290{
291 uint32_t clkRate = 0;
292 uint32_t prediv, postdiv;
293 uint64_t workRate;
294
295 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
296 {
297 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
298 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
299 {
300 case 0x00: /* FRO 12 MHz (fro_12m) */
301 clkRate = CLK_FRO_12MHZ;
302 break;
303 case 0x01: /* CLKIN Source (clk_in) */
304 clkRate = CLK_CLK_IN;
305 break;
306 case 0x02: /* Watchdog oscillator (wdt_clk) */
307 clkRate = getWdtOscFreq();
308 break;
309 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
310 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
311 {
312 clkRate = CLK_FRO_96MHZ;
313 }
314 else
315 {
316 clkRate = CLK_FRO_48MHZ;
317 }
318 break;
319 }
320 break;
321 case 0x02: /* System PLL clock (pll_clk)*/
322 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
323 {
324 case 0x00: /* FRO 12 MHz (fro_12m) */
325 clkRate = CLK_FRO_12MHZ;
326 break;
327 case 0x01: /* CLKIN Source (clk_in) */
328 clkRate = CLK_CLK_IN;
329 break;
330 case 0x02: /* Watchdog oscillator (wdt_clk) */
331 clkRate = getWdtOscFreq();
332 break;
333 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
334 clkRate = CLK_RTC_32K_CLK;
335 break;
336 default:
337 clkRate = 0UL;
338 break;
339 }
340 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
341 {
342 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
343 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
344 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
345 /* Adjust input clock */
346 clkRate = clkRate / prediv;
347
348 /* MDEC used for rate */
349 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
350 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
351 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
352 }
353 break;
354 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
355 clkRate = CLK_RTC_32K_CLK;
356 break;
357 default:
358 clkRate = 0UL;
359 break;
360 }
361 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
362}
363
364/* ----------------------------------------------------------------------------
365 -- SystemInitHook()
366 ---------------------------------------------------------------------------- */
367
368__attribute__((weak)) void SystemInitHook(void)
369{
370 /* Void implementation of the weak function. */
371}
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