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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/drivers/fsl_clock.h
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/drivers/fsl_clock.h
@@ -0,0 +1,1322 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_CLOCK_H_
11#define _FSL_CLOCK_H_
12
13#include "fsl_common.h"
14
15/*! @addtogroup clock */
16/*! @{ */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24/*! @name Driver version */
25/*@{*/
26/*! @brief CLOCK driver version. */
27#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
28/*@}*/
29
30/*! @brief Configure whether driver controls clock
31 *
32 * When set to 0, peripheral drivers will enable clock in initialize function
33 * and disable clock in de-initialize function. When set to 1, peripheral
34 * driver will not control the clock, application could control the clock out of
35 * the driver.
36 *
37 * @note All drivers share this feature switcher. If it is set to 1, application
38 * should handle clock enable and disable for all drivers.
39 */
40#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
41#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
42#endif
43
44/*!
45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
46 *
47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
48 * would cache the recent calulation and accelerate the execution to get the
49 * right settings.
50 */
51#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
52#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
53#endif
54
55/*! @brief FROHF clock setting API address in ROM. */
56#define CLOCK_FROHF_SETTING_API_ROM_ADDRESS (0x030091DFU)
57
58/* Definition for delay API in clock driver, users can redefine it to the real application. */
59#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
60#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
61#endif
62
63/**
64 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
65 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
66 * output is enabled.
67 * Usage: set_fro_frequency(frequency), (frequency must be one of 12, 48 or 96 MHz)
68 */
69
70#define set_fro_frequency(iFreq) (*((void (*)(uint32_t iFreq))(CLOCK_FROHF_SETTING_API_ROM_ADDRESS)))(iFreq)
71
72/*! @brief Clock ip name array for ROM. */
73#define ADC_CLOCKS \
74 { \
75 kCLOCK_Adc0 \
76 }
77/*! @brief Clock ip name array for ROM. */
78#define ROM_CLOCKS \
79 { \
80 kCLOCK_Rom \
81 }
82/*! @brief Clock ip name array for SRAM. */
83#define SRAM_CLOCKS \
84 { \
85 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
86 }
87/*! @brief Clock ip name array for FLASH. */
88#define FLASH_CLOCKS \
89 { \
90 kCLOCK_Flash \
91 }
92/*! @brief Clock ip name array for FMC. */
93#define FMC_CLOCKS \
94 { \
95 kCLOCK_Fmc \
96 }
97/*! @brief Clock ip name array for EEPROM. */
98#define EEPROM_CLOCKS \
99 { \
100 kCLOCK_Eeprom \
101 }
102/*! @brief Clock ip name array for SPIFI. */
103#define SPIFI_CLOCKS \
104 { \
105 kCLOCK_Spifi \
106 }
107/*! @brief Clock ip name array for INPUTMUX. */
108#define INPUTMUX_CLOCKS \
109 { \
110 kCLOCK_InputMux \
111 }
112/*! @brief Clock ip name array for IOCON. */
113#define IOCON_CLOCKS \
114 { \
115 kCLOCK_Iocon \
116 }
117/*! @brief Clock ip name array for GPIO. */
118#define GPIO_CLOCKS \
119 { \
120 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
121 }
122/*! @brief Clock ip name array for PINT. */
123#define PINT_CLOCKS \
124 { \
125 kCLOCK_Pint \
126 }
127/*! @brief Clock ip name array for GINT. */
128#define GINT_CLOCKS \
129 { \
130 kCLOCK_Gint, kCLOCK_Gint \
131 }
132/*! @brief Clock ip name array for DMA. */
133#define DMA_CLOCKS \
134 { \
135 kCLOCK_Dma \
136 }
137/*! @brief Clock ip name array for CRC. */
138#define CRC_CLOCKS \
139 { \
140 kCLOCK_Crc \
141 }
142/*! @brief Clock ip name array for WWDT. */
143#define WWDT_CLOCKS \
144 { \
145 kCLOCK_Wwdt \
146 }
147/*! @brief Clock ip name array for RTC. */
148#define RTC_CLOCKS \
149 { \
150 kCLOCK_Rtc \
151 }
152/*! @brief Clock ip name array for ADC0. */
153#define ADC0_CLOCKS \
154 { \
155 kCLOCK_Adc0 \
156 }
157/*! @brief Clock ip name array for MRT. */
158#define MRT_CLOCKS \
159 { \
160 kCLOCK_Mrt \
161 }
162/*! @brief Clock ip name array for RIT. */
163#define RIT_CLOCKS \
164 { \
165 kCLOCK_Rit \
166 }
167/*! @brief Clock ip name array for SCT0. */
168#define SCT_CLOCKS \
169 { \
170 kCLOCK_Sct0 \
171 }
172/*! @brief Clock ip name array for MCAN. */
173#define MCAN_CLOCKS \
174 { \
175 kCLOCK_Mcan0, kCLOCK_Mcan1 \
176 }
177/*! @brief Clock ip name array for UTICK. */
178#define UTICK_CLOCKS \
179 { \
180 kCLOCK_Utick \
181 }
182/*! @brief Clock ip name array for FLEXCOMM. */
183#define FLEXCOMM_CLOCKS \
184 { \
185 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
186 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
187 }
188/*! @brief Clock ip name array for LPUART. */
189#define LPUART_CLOCKS \
190 { \
191 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
192 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
193 }
194
195/*! @brief Clock ip name array for BI2C. */
196#define BI2C_CLOCKS \
197 { \
198 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
199 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
200 }
201/*! @brief Clock ip name array for LSPI. */
202#define LPSI_CLOCKS \
203 { \
204 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
205 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
206 }
207/*! @brief Clock ip name array for FLEXI2S. */
208#define FLEXI2S_CLOCKS \
209 { \
210 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
211 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
212 }
213/*! @brief Clock ip name array for DMIC. */
214#define DMIC_CLOCKS \
215 { \
216 kCLOCK_DMic \
217 }
218/*! @brief Clock ip name array for CT32B. */
219#define CTIMER_CLOCKS \
220 { \
221 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
222 }
223/*! @brief Clock ip name array for LCD. */
224#define LCD_CLOCKS \
225 { \
226 kCLOCK_Lcd \
227 }
228/*! @brief Clock ip name array for SDIO. */
229#define SDIO_CLOCKS \
230 { \
231 kCLOCK_Sdio \
232 }
233/*! @brief Clock ip name array for USBRAM. */
234#define USBRAM_CLOCKS \
235 { \
236 kCLOCK_UsbRam1 \
237 }
238/*! @brief Clock ip name array for EMC. */
239#define EMC_CLOCKS \
240 { \
241 kCLOCK_Emc \
242 }
243/*! @brief Clock ip name array for ETH. */
244#define ETH_CLOCKS \
245 { \
246 kCLOCK_Eth \
247 }
248/*! @brief Clock ip name array for AES. */
249#define AES_CLOCKS \
250 { \
251 kCLOCK_Aes \
252 }
253/*! @brief Clock ip name array for OTP. */
254#define OTP_CLOCKS \
255 { \
256 kCLOCK_Otp \
257 }
258/*! @brief Clock ip name array for RNG. */
259#define RNG_CLOCKS \
260 { \
261 kCLOCK_Rng \
262 }
263/*! @brief Clock ip name array for USBHMR0. */
264#define USBHMR0_CLOCKS \
265 { \
266 kCLOCK_Usbhmr0 \
267 }
268/*! @brief Clock ip name array for USBHSL0. */
269#define USBHSL0_CLOCKS \
270 { \
271 kCLOCK_Usbhsl0 \
272 }
273/*! @brief Clock ip name array for SHA0. */
274#define SHA0_CLOCKS \
275 { \
276 kCLOCK_Sha0 \
277 }
278/*! @brief Clock ip name array for SMARTCARD. */
279#define SMARTCARD_CLOCKS \
280 { \
281 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
282 }
283/*! @brief Clock ip name array for USBD. */
284#define USBD_CLOCKS \
285 { \
286 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
287 }
288/*! @brief Clock ip name array for USBH. */
289#define USBH_CLOCKS \
290 { \
291 kCLOCK_Usbh1 \
292 }
293/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
294/*------------------------------------------------------------------------------
295 clock_ip_name_t definition:
296------------------------------------------------------------------------------*/
297
298#define CLK_GATE_REG_OFFSET_SHIFT 8U
299#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
300#define CLK_GATE_BIT_SHIFT_SHIFT 0U
301#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
302
303#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
304 ((((uint32_t)(reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
305 (((uint32_t)(bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
306
307#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
308#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
309
310#define AHB_CLK_CTRL0 0U
311#define AHB_CLK_CTRL1 1U
312#define AHB_CLK_CTRL2 2U
313#define ASYNC_CLK_CTRL0 3U
314
315/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
316typedef enum _clock_ip_name
317{
318 kCLOCK_IpInvalid = 0U,
319 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
320 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
321 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
322 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
323 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
324 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
325 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9),
326 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
327 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
328 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
329 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
330 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
331 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
332 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
333 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
334 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
335 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
336 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
337 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
338 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
339 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
340 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
341 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
342 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
343 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
344 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
345 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
346 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
347 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
348 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
349 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
350 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
351 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
352 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
353 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
354 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
355 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
356 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
357 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
358 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
359 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
360 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
361 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
362 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
363 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
364 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
365 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
366 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
367 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
368 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
369 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
370 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
371 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
372 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
373 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
374 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
375 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
376 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
377 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
378 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
379 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
380 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
381 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
382 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
383 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
384 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
385 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
386 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
387 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
388 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
389 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
390 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
391 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
392 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
393 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
394 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
395 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
396 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
397 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
398 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
399 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
400 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
401 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
402 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
403 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
404 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
405 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
406 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
407 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
408 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
409 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
410 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
411 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
412 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
413 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
414 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
415 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
416 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
417 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
418 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
419 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
420
421 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
422 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
423} clock_ip_name_t;
424
425/*! @brief Clock name used to get clock frequency. */
426typedef enum _clock_name
427{
428 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
429 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
430 kCLOCK_ClockOut, /*!< CLOCKOUT */
431 kCLOCK_FroHf, /*!< FRO48/96 */
432 kCLOCK_UsbPll, /*!< USB1 PLL */
433 kCLOCK_Mclk, /*!< MCLK */
434 kCLOCK_Fro12M, /*!< FRO12M */
435 kCLOCK_ExtClk, /*!< External Clock */
436 kCLOCK_PllOut, /*!< PLL Output */
437 kCLOCK_UsbClk, /*!< USB input */
438 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
439 kCLOCK_Frg, /*!< Frg Clock */
440 kCLOCK_AsyncApbClk, /*!< Async APB clock */
441 kCLOCK_FlexI2S, /*!< FlexI2S clock */
442} clock_name_t;
443
444/**
445 * Clock source selections for the asynchronous APB clock
446 */
447typedef enum _async_clock_src
448{
449 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
450 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
451 kCLOCK_AsyncAudioPllClk,
452 kCLOCK_AsyncI2cClkFc6,
453
454} async_clock_src_t;
455
456/*! @brief Clock Mux Switches
457 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
458 * starting from LSB upwards
459 *
460 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
461 *
462 */
463
464#define CLK_ATTACH_ID(mux, sel, pos) \
465 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
466#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
467#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
468
469#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
470#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
471#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
472#define GET_ID_ITEM_SEL(connection) (uint8_t)(((((connection)&0xF00U) >> 8U) - 1U))
473#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
474
475#define CM_MAINCLKSELA 0
476#define CM_MAINCLKSELB 1
477#define CM_CLKOUTCLKSELA 2
478#define CM_SYSPLLCLKSEL 4
479#define CM_AUDPLLCLKSEL 6
480#define CM_SPIFICLKSEL 8
481#define CM_ADCASYNCCLKSEL 9
482#define CM_USB0CLKSEL 10
483#define CM_USB1CLKSEL 11
484#define CM_FXCOMCLKSEL0 12
485#define CM_FXCOMCLKSEL1 13
486#define CM_FXCOMCLKSEL2 14
487#define CM_FXCOMCLKSEL3 15
488#define CM_FXCOMCLKSEL4 16
489#define CM_FXCOMCLKSEL5 17
490#define CM_FXCOMCLKSEL6 18
491#define CM_FXCOMCLKSEL7 19
492#define CM_FXCOMCLKSEL8 20
493#define CM_FXCOMCLKSEL9 21
494#define CM_MCLKCLKSEL 24
495#define CM_FRGCLKSEL 26
496#define CM_DMICCLKSEL 27
497#define CM_SCTCLKSEL 28
498#define CM_LCDCLKSEL 29
499#define CM_SDIOCLKSEL 30
500
501#define CM_ASYNCAPB 31U
502
503typedef enum _clock_attach_id
504{
505
506 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
507 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
508 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
509 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
510 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
511 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
512
513 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
514 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
515 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
516 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
517 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
518 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
519 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
520 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
521
522 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
523 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
524 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
525 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
526 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
527
528 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
529 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
530 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
531
532 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
533 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
534 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
535 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
536 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
537 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
538
539 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
540 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
541 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
542 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
543 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
544
545 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
546 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
547 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
548 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
549
550 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
551 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
552 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
553 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
554
555 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
556 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
557 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
558 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
559 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
560 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
561
562 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
563 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
564 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
565 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
566 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
567 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
568
569 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
570 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
571 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
572 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
573 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
574 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
575
576 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
577 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
578 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
579 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
580 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
581 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
582
583 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
584 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
585 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
586 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
587 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
588 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
589
590 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
591 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
592 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
593 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
594 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
595 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
596
597 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
598 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
599 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
600 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
601 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
602 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
603
604 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
605 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
606 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
607 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
608 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
609 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
610
611 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
612 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
613 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
614 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
615 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
616 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
617
618 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
619 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
620 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
621 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
622 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
623 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
624
625 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
626 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
627 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
628
629 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
630 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
631 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
632 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
633 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
634
635 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
636 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
637 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
638 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
639 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
640
641 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
642 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
643 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
644 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
645 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
646
647 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
648 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
649 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
650 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
651 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
652 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
653
654 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
655 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
656 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
657 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
658
659 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
660 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
661 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
662 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
663 kNONE_to_NONE = (int)0x80000000U,
664} clock_attach_id_t;
665
666/* Clock dividers */
667typedef enum _clock_div_name
668{
669 kCLOCK_DivSystickClk = 0,
670 kCLOCK_DivArmTrClkDiv = 1,
671 kCLOCK_DivCan0Clk = 2,
672 kCLOCK_DivCan1Clk = 3,
673 kCLOCK_DivSmartCard0Clk = 4,
674 kCLOCK_DivSmartCard1Clk = 5,
675 kCLOCK_DivAhbClk = 32,
676 kCLOCK_DivClkOut = 33,
677 kCLOCK_DivFrohfClk = 34,
678 kCLOCK_DivSpifiClk = 36,
679 kCLOCK_DivAdcAsyncClk = 37,
680 kCLOCK_DivUsb0Clk = 38,
681 kCLOCK_DivUsb1Clk = 39,
682 kCLOCK_DivFrg = 40,
683 kCLOCK_DivDmicClk = 42,
684 kCLOCK_DivMClk = 43,
685 kCLOCK_DivLcdClk = 44,
686 kCLOCK_DivSctClk = 45,
687 kCLOCK_DivEmcClk = 46,
688 kCLOCK_DivSdioClk = 47
689} clock_div_name_t;
690
691/*******************************************************************************
692 * API
693 ******************************************************************************/
694
695#if defined(__cplusplus)
696extern "C" {
697#endif /* __cplusplus */
698
699static inline void CLOCK_EnableClock(clock_ip_name_t clk)
700{
701 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
702 if (index < 3U)
703 {
704 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
705 }
706 else
707 {
708 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
709 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
710 }
711}
712
713static inline void CLOCK_DisableClock(clock_ip_name_t clk)
714{
715 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
716 if (index < 3U)
717 {
718 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
719 }
720 else
721 {
722 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
723 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
724 }
725}
726/**
727 * @brief FLASH Access time definitions
728 */
729typedef enum _clock_flashtim
730{
731 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
732 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
733 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
734 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
735 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
736 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
737 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
738 kCLOCK_Flash8Cycle, /*!< Flash accesses use 8 CPU clocks */
739 kCLOCK_Flash9Cycle /*!< Flash accesses use 9 CPU clocks */
740} clock_flashtim_t;
741
742/**
743 * @brief Set FLASH memory access time in clocks
744 * @param clks : Clock cycles for FLASH access
745 * @return Nothing
746 */
747static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
748{
749 uint32_t tmp;
750
751 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
752
753 /* Don't alter lower bits */
754 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
755}
756
757/**
758 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
759 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
760 * enabled.
761 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
762 * @return returns success or fail status.
763 */
764status_t CLOCK_SetupFROClocking(uint32_t iFreq);
765/**
766 * @brief Configure the clock selection muxes.
767 * @param connection : Clock to be configured.
768 * @return Nothing
769 */
770void CLOCK_AttachClk(clock_attach_id_t connection);
771/**
772 * @brief Get the actual clock attach id.
773 * This fuction uses the offset in input attach id, then it reads the actual source value in
774 * the register and combine the offset to obtain an actual attach id.
775 * @param attachId : Clock attach id to get.
776 * @return Clock source value.
777 */
778clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
779/**
780 * @brief Setup peripheral clock dividers.
781 * @param div_name : Clock divider name
782 * @param divided_by_value: Value to be divided
783 * @param reset : Whether to reset the divider counter.
784 * @return Nothing
785 */
786void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
787/**
788 * @brief Set the flash wait states for the input freuqency.
789 * @param iFreq : Input frequency
790 * @return Nothing
791 */
792void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
793
794/**
795 * @brief Set the frg output frequency.
796 * @param freq : output frequency
797 * @return 0 : the frequency range is out of range.
798 * 1 : switch successfully.
799 */
800uint32_t CLOCK_SetFRGClock(uint32_t freq);
801
802/*! @brief Return Frequency of FRG input clock
803 * @return Frequency value
804 */
805uint32_t CLOCK_GetFRGInputClock(void);
806
807/*! @brief Return Frequency of selected clock
808 * @return Frequency of selected clock
809 */
810uint32_t CLOCK_GetFreq(clock_name_t clockName);
811/*! @brief Return Frequency of FRO 12MHz
812 * @return Frequency of FRO 12MHz
813 */
814uint32_t CLOCK_GetFro12MFreq(void);
815/*! @brief Return Frequency of ClockOut
816 * @return Frequency of ClockOut
817 */
818uint32_t CLOCK_GetClockOutClkFreq(void);
819/*! @brief Return Frequency of Spifi Clock
820 * @return Frequency of Spifi.
821 */
822uint32_t CLOCK_GetSpifiClkFreq(void);
823/*! @brief Return Frequency of Adc Clock
824 * @return Frequency of Adc Clock.
825 */
826uint32_t CLOCK_GetAdcClkFreq(void);
827/*! brief Return Frequency of MCAN Clock
828 * param MCanSel : 0U: MCAN0; 1U: MCAN1
829 * return Frequency of MCAN Clock
830 */
831uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
832/*! @brief Return Frequency of Usb0 Clock
833 * @return Frequency of Usb0 Clock.
834 */
835uint32_t CLOCK_GetUsb0ClkFreq(void);
836/*! @brief Return Frequency of Usb1 Clock
837 * @return Frequency of Usb1 Clock.
838 */
839uint32_t CLOCK_GetUsb1ClkFreq(void);
840/*! @brief Return Frequency of MClk Clock
841 * @return Frequency of MClk Clock.
842 */
843uint32_t CLOCK_GetMclkClkFreq(void);
844/*! @brief Return Frequency of SCTimer Clock
845 * @return Frequency of SCTimer Clock.
846 */
847uint32_t CLOCK_GetSctClkFreq(void);
848/*! @brief Return Frequency of SDIO Clock
849 * @return Frequency of SDIO Clock.
850 */
851uint32_t CLOCK_GetSdioClkFreq(void);
852/*! @brief Return Frequency of LCD Clock
853 * @return Frequency of LCD Clock.
854 */
855uint32_t CLOCK_GetLcdClkFreq(void);
856/*! @brief Return Frequency of LCD CLKIN Clock
857 * @return Frequency of LCD CLKIN Clock.
858 */
859uint32_t CLOCK_GetLcdClkIn(void);
860/*! @brief Return Frequency of External Clock
861 * @return Frequency of External Clock. If no external clock is used returns 0.
862 */
863uint32_t CLOCK_GetExtClkFreq(void);
864/*! @brief Return Frequency of Watchdog Oscillator
865 * @return Frequency of Watchdog Oscillator
866 */
867uint32_t CLOCK_GetWdtOscFreq(void);
868/*! @brief Return Frequency of High-Freq output of FRO
869 * @return Frequency of High-Freq output of FRO
870 */
871uint32_t CLOCK_GetFroHfFreq(void);
872/*! @brief Return Frequency of frg
873 * @return Frequency of FRG
874 */
875uint32_t CLOCK_GetFrgClkFreq(void);
876/*! @brief Return Frequency of dmic
877 * @return Frequency of DMIC
878 */
879uint32_t CLOCK_GetDmicClkFreq(void);
880/*! @brief Return Frequency of PLL
881 * @return Frequency of PLL
882 */
883uint32_t CLOCK_GetPllOutFreq(void);
884/*! @brief Return Frequency of USB PLL
885 * @return Frequency of PLL
886 */
887uint32_t CLOCK_GetUsbPllOutFreq(void);
888/*! @brief Return Frequency of AUDIO PLL
889 * @return Frequency of PLL
890 */
891uint32_t CLOCK_GetAudioPllOutFreq(void);
892/*! @brief Return Frequency of 32kHz osc
893 * @return Frequency of 32kHz osc
894 */
895uint32_t CLOCK_GetOsc32KFreq(void);
896/*! @brief Return Frequency of Core System
897 * @return Frequency of Core System
898 */
899uint32_t CLOCK_GetCoreSysClkFreq(void);
900/*! @brief Return Frequency of I2S MCLK Clock
901 * @return Frequency of I2S MCLK Clock
902 */
903uint32_t CLOCK_GetI2SMClkFreq(void);
904/*! @brief Return Frequency of Flexcomm functional Clock
905 * @return Frequency of Flexcomm functional Clock
906 */
907uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
908/*! @brief Return Asynchronous APB Clock source
909 * @return Asynchronous APB CLock source
910 */
911__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
912{
913 return (async_clock_src_t)(uint8_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
914}
915/*! @brief Return Frequency of Asynchronous APB Clock
916 * @return Frequency of Asynchronous APB Clock Clock
917 */
918uint32_t CLOCK_GetAsyncApbClkFreq(void);
919/*! @brief Return EMC source
920 * @return EMC source
921 */
922__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
923{
924 uint32_t freqtmp;
925
926 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
927 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
928}
929/*! @brief Return Audio PLL input clock rate
930 * @return Audio PLL input clock rate
931 */
932uint32_t CLOCK_GetAudioPLLInClockRate(void);
933/*! @brief Return System PLL input clock rate
934 * @return System PLL input clock rate
935 */
936uint32_t CLOCK_GetSystemPLLInClockRate(void);
937
938/*! @brief Return System PLL output clock rate
939 * @param recompute : Forces a PLL rate recomputation if true
940 * @return System PLL output clock rate
941 * @note The PLL rate is cached in the driver in a variable as
942 * the rate computation function can take some time to perform. It
943 * is recommended to use 'false' with the 'recompute' parameter.
944 */
945uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
946
947/*! @brief Return System AUDIO PLL output clock rate
948 * @param recompute : Forces a AUDIO PLL rate recomputation if true
949 * @return System AUDIO PLL output clock rate
950 * @note The AUDIO PLL rate is cached in the driver in a variable as
951 * the rate computation function can take some time to perform. It
952 * is recommended to use 'false' with the 'recompute' parameter.
953 */
954uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
955
956/*! @brief Return System USB PLL output clock rate
957 * @param recompute : Forces a USB PLL rate recomputation if true
958 * @return System USB PLL output clock rate
959 * @note The USB PLL rate is cached in the driver in a variable as
960 * the rate computation function can take some time to perform. It
961 * is recommended to use 'false' with the 'recompute' parameter.
962 */
963uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
964
965/*! @brief Enables and disables PLL bypass mode
966 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
967 * @return System PLL output clock rate
968 */
969__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
970{
971 if (bypass)
972 {
973 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
974 }
975 else
976 {
977 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
978 }
979}
980
981/*! @brief Check if PLL is locked or not
982 * @return true if the PLL is locked, false if not locked
983 */
984__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
985{
986 return ((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
987}
988
989/*! @brief Check if USB PLL is locked or not
990 * @return true if the USB PLL is locked, false if not locked
991 */
992__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
993{
994 return ((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
995}
996
997/*! @brief Check if AUDIO PLL is locked or not
998 * @return true if the AUDIO PLL is locked, false if not locked
999 */
1000__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
1001{
1002 return ((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
1003}
1004
1005/*! @brief Enables and disables SYS OSC
1006 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
1007 */
1008__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
1009{
1010 if (enable)
1011 {
1012 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1013 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1014 }
1015
1016 else
1017 {
1018 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
1019 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
1020 }
1021}
1022
1023/*! @brief Store the current PLL rate
1024 * @param rate: Current rate of the PLL
1025 * @return Nothing
1026 **/
1027void CLOCK_SetStoredPLLClockRate(uint32_t rate);
1028
1029/*! @brief Store the current AUDIO PLL rate
1030 * @param rate: Current rate of the PLL
1031 * @return Nothing
1032 **/
1033void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
1034
1035/*! @brief PLL configuration structure flags for 'flags' field
1036 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1037 *
1038 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1039 * configuration structure must be assigned with the expected PLL frequency. If the
1040 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1041 * function and the driver will determine the PLL rate from the currently selected
1042 * PLL source. This flag might be used to configure the PLL input clock more accurately
1043 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1044 *
1045 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1046 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1047 * are not used.<br>
1048 */
1049#define PLL_CONFIGFLAG_USEINRATE (1UL << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1050#define PLL_CONFIGFLAG_FORCENOFRACT \
1051 (1UL << 2U) /*!< Force non-fractional output mode, \
1052 PLL output will not use the fractional, \
1053 automatic bandwidth, or SS hardware */
1054
1055/*! @brief PLL configuration structure
1056 *
1057 * This structure can be used to configure the settings for a PLL
1058 * setup structure. Fill in the desired configuration for the PLL
1059 * and call the PLL setup function to fill in a PLL setup structure.
1060 */
1061typedef struct _pll_config
1062{
1063 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1064 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1065 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1066} pll_config_t;
1067
1068/*! @brief PLL setup structure flags for 'flags' field
1069 * These flags control how the PLL setup function sets up the PLL
1070 */
1071#define PLL_SETUPFLAG_POWERUP (1UL << 0U) /*!< Setup will power on the PLL after setup */
1072#define PLL_SETUPFLAG_WAITLOCK (1UL << 1U) /*!< Setup will wait for PLL lock, implying the PLL will be pwoered on */
1073#define PLL_SETUPFLAG_ADGVOLT (1UL << 2U) /*!< Optimize system voltage for the new PLL rate */
1074
1075/*! @brief PLL setup structure
1076 * This structure can be used to pre-build a PLL setup configuration
1077 * at run-time and quickly set the PLL to the configuration. It can be
1078 * populated with the PLL setup function. If powering up or waiting
1079 * for PLL lock, the PLL input clock source should be configured prior
1080 * to PLL setup.
1081 */
1082typedef struct _pll_setup
1083{
1084 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
1085 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
1086 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
1087 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
1088 uint32_t pllRate; /*!< Acutal PLL rate */
1089 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
1090 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1091} pll_setup_t;
1092
1093/*! @brief PLL status definitions
1094 */
1095typedef enum _pll_error
1096{
1097 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1098 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1099 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1100 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1101 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1102 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1103 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1104 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1105} pll_error_t;
1106
1107/*! @brief USB clock source definition. */
1108typedef enum _clock_usb_src
1109{
1110 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
1111 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
1112 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1113 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
1114
1115 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
1116 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
1117} clock_usb_src_t;
1118
1119/*! @brief USB PDEL Divider. */
1120typedef enum _usb_pll_psel
1121{
1122 pSel_Divide_1 = 0U,
1123 pSel_Divide_2,
1124 pSel_Divide_4,
1125 pSel_Divide_8
1126} usb_pll_psel;
1127
1128/*! @brief PLL setup structure
1129 * This structure can be used to pre-build a USB PLL setup configuration
1130 * at run-time and quickly set the usb PLL to the configuration. It can be
1131 * populated with the USB PLL setup function. If powering up or waiting
1132 * for USB PLL lock, the PLL input clock source should be configured prior
1133 * to USB PLL setup.
1134 */
1135typedef struct _usb_pll_setup
1136{
1137 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
1138 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
1139 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
1140 bool direct; /*!< USB PLL CCO output control */
1141 bool bypass; /*!< USB PLL inout clock bypass control */
1142 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
1143 uint32_t inputRate; /*!< USB PLL input rate */
1144} usb_pll_setup_t;
1145
1146/*! @brief Return System PLL output clock rate from setup structure
1147 * @param pSetup : Pointer to a PLL setup structure
1148 * @return System PLL output clock rate the setup structure will generate
1149 */
1150uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
1151
1152/*! @brief Return System AUDIO PLL output clock rate from setup structure
1153 * @param pSetup : Pointer to a PLL setup structure
1154 * @return System PLL output clock rate the setup structure will generate
1155 */
1156uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
1157
1158/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
1159 * @param pSetup : Pointer to a PLL setup structure
1160 * @return System PLL output clock rate the setup structure will generate
1161 */
1162uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
1163
1164/*! @brief Return System USB PLL output clock rate from setup structure
1165 * @param pSetup : Pointer to a PLL setup structure
1166 * @return System PLL output clock rate the setup structure will generate
1167 */
1168uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
1169
1170/*! @brief Set USB PLL output frequency
1171 * @param rate : frequency value
1172 *
1173 */
1174void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
1175/*! @brief Set PLL output based on the passed PLL setup data
1176 * @param pControl : Pointer to populated PLL control structure to generate setup with
1177 * @param pSetup : Pointer to PLL setup structure to be filled
1178 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1179 * @note Actual frequency for setup may vary from the desired frequency based on the
1180 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1181 */
1182pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1183
1184/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
1185 * @param pControl : Pointer to populated PLL control structure to generate setup with
1186 * @param pSetup : Pointer to PLL setup structure to be filled
1187 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1188 * @note Actual frequency for setup may vary from the desired frequency based on the
1189 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1190 */
1191pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1192
1193/*! @brief Set PLL output from PLL setup structure (precise frequency)
1194 * @param pSetup : Pointer to populated PLL setup structure
1195 * @param flagcfg : Flag configuration for PLL config structure
1196 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1197 * @note This function will power off the PLL, setup the PLL with the
1198 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1199 * and adjust system voltages to the new PLL rate. The function will not
1200 * alter any source clocks (ie, main systen clock) that may use the PLL,
1201 * so these should be setup prior to and after exiting the function.
1202 */
1203pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1204
1205/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
1206 * @param pSetup : Pointer to populated PLL setup structure
1207 * @param flagcfg : Flag configuration for PLL config structure
1208 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1209 * @note This function will power off the PLL, setup the PLL with the
1210 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1211 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1212 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1213 * so these should be setup prior to and after exiting the function.
1214 */
1215pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1216
1217/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
1218 * frequency)
1219 * @param pSetup : Pointer to populated PLL setup structure
1220 * @param flagcfg : Flag configuration for PLL config structure
1221 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1222 * @note This function will power off the PLL, setup the PLL with the
1223 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1224 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1225 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1226 * so these should be setup prior to and after exiting the function.
1227 */
1228pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
1229
1230/**
1231 * @brief Set PLL output from PLL setup structure (precise frequency)
1232 * @param pSetup : Pointer to populated PLL setup structure
1233 * @return kStatus_PLL_Success on success, or PLL setup error code
1234 * @note This function will power off the PLL, setup the PLL with the
1235 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1236 * and adjust system voltages to the new PLL rate. The function will not
1237 * alter any source clocks (ie, main systen clock) that may use the PLL,
1238 * so these should be setup prior to and after exiting the function.
1239 */
1240pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
1241
1242/**
1243 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
1244 * @param pSetup : Pointer to populated PLL setup structure
1245 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
1246 * @note This function will power off the PLL, setup the Audio PLL with the
1247 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
1248 * and adjust system voltages to the new PLL rate. The function will not
1249 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
1250 * so these should be setup prior to and after exiting the function.
1251 */
1252pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
1253
1254/**
1255 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
1256 * @param pSetup : Pointer to populated USB PLL setup structure
1257 * @return kStatus_PLL_Success on success, or USB PLL setup error code
1258 * @note This function will power off the USB PLL, setup the PLL with the
1259 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
1260 * and adjust system voltages to the new USB PLL rate. The function will not
1261 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
1262 * so these should be setup prior to and after exiting the function.
1263 */
1264pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
1265
1266/*! @brief Set PLL output based on the multiplier and input frequency
1267 * @param multiply_by : multiplier
1268 * @param input_freq : Clock input frequency of the PLL
1269 * @return Nothing
1270 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1271 * function does not disable or enable PLL power, wait for PLL lock,
1272 * or adjust system voltages. These must be done in the application.
1273 * The function will not alter any source clocks (ie, main systen clock)
1274 * that may use the PLL, so these should be setup prior to and after
1275 * exiting the function.
1276 */
1277void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
1278
1279/*! @brief Disable USB clock.
1280 *
1281 * Disable USB clock.
1282 */
1283static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1284{
1285 CLOCK_DisableClock(clk);
1286}
1287
1288/*! @brief Enable USB Device FS clock.
1289 * @param src : clock source
1290 * @param freq: clock frequency
1291 * Enable USB Device Full Speed clock.
1292 */
1293bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1294
1295/*! @brief Enable USB HOST FS clock.
1296 * @param src : clock source
1297 * @param freq: clock frequency
1298 * Enable USB HOST Full Speed clock.
1299 */
1300bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
1301
1302/*! @brief Enable USB Device HS clock.
1303 * @param src : clock source
1304 * @param freq: clock frequency
1305 * Enable USB Device High Speed clock.
1306 */
1307bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1308
1309/*! @brief Enable USB HOST HS clock.
1310 * @param src : clock source
1311 * @param freq: clock frequency
1312 * Enable USB HOST High Speed clock.
1313 */
1314bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
1315
1316#if defined(__cplusplus)
1317}
1318#endif /* __cplusplus */
1319
1320/*! @} */
1321
1322#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:05 +0100