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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608')
43 files changed, 33077 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/LPC54608.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/LPC54608.h new file mode 100644 index 000000000..c8fd17715 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/LPC54608.h | |||
| @@ -0,0 +1,21676 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: LPC54608J512BD208 | ||
| 4 | ** LPC54608J512ET180 | ||
| 5 | ** | ||
| 6 | ** Compilers: GNU C Compiler | ||
| 7 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 8 | ** Keil ARM C/C++ Compiler | ||
| 9 | ** MCUXpresso Compiler | ||
| 10 | ** | ||
| 11 | ** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 | ||
| 12 | ** Version: rev. 1.2, 2017-06-08 | ||
| 13 | ** Build: b200304 | ||
| 14 | ** | ||
| 15 | ** Abstract: | ||
| 16 | ** CMSIS Peripheral Access Layer for LPC54608 | ||
| 17 | ** | ||
| 18 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 19 | ** Copyright 2016-2020 NXP | ||
| 20 | ** All rights reserved. | ||
| 21 | ** | ||
| 22 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 23 | ** | ||
| 24 | ** http: www.nxp.com | ||
| 25 | ** mail: [email protected] | ||
| 26 | ** | ||
| 27 | ** Revisions: | ||
| 28 | ** - rev. 1.0 (2016-08-12) | ||
| 29 | ** Initial version. | ||
| 30 | ** - rev. 1.1 (2016-11-25) | ||
| 31 | ** Update CANFD and Classic CAN register. | ||
| 32 | ** Add MAC TIMERSTAMP registers. | ||
| 33 | ** - rev. 1.2 (2017-06-08) | ||
| 34 | ** Remove RTC_CTRL_RTC_OSC_BYPASS. | ||
| 35 | ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. | ||
| 36 | ** Remove RESET and HALT from SYSCON_AHBCLKDIV. | ||
| 37 | ** | ||
| 38 | ** ################################################################### | ||
| 39 | */ | ||
| 40 | |||
| 41 | /*! | ||
| 42 | * @file LPC54608.h | ||
| 43 | * @version 1.2 | ||
| 44 | * @date 2017-06-08 | ||
| 45 | * @brief CMSIS Peripheral Access Layer for LPC54608 | ||
| 46 | * | ||
| 47 | * CMSIS Peripheral Access Layer for LPC54608 | ||
| 48 | */ | ||
| 49 | |||
| 50 | #ifndef _LPC54608_H_ | ||
| 51 | #define _LPC54608_H_ /**< Symbol preventing repeated inclusion */ | ||
| 52 | |||
| 53 | /** Memory map major version (memory maps with equal major version number are | ||
| 54 | * compatible) */ | ||
| 55 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 56 | /** Memory map minor version */ | ||
| 57 | #define MCU_MEM_MAP_VERSION_MINOR 0x0002U | ||
| 58 | |||
| 59 | |||
| 60 | /* ---------------------------------------------------------------------------- | ||
| 61 | -- Interrupt vector numbers | ||
| 62 | ---------------------------------------------------------------------------- */ | ||
| 63 | |||
| 64 | /*! | ||
| 65 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 66 | * @{ | ||
| 67 | */ | ||
| 68 | |||
| 69 | /** Interrupt Number Definitions */ | ||
| 70 | #define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */ | ||
| 71 | |||
| 72 | typedef enum IRQn { | ||
| 73 | /* Auxiliary constants */ | ||
| 74 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 75 | |||
| 76 | /* Core interrupts */ | ||
| 77 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 78 | HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ | ||
| 79 | MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ | ||
| 80 | BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ | ||
| 81 | UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ | ||
| 82 | SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ | ||
| 83 | DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ | ||
| 84 | PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ | ||
| 85 | SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ | ||
| 86 | |||
| 87 | /* Device specific interrupts */ | ||
| 88 | WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ | ||
| 89 | DMA0_IRQn = 1, /**< DMA controller */ | ||
| 90 | GINT0_IRQn = 2, /**< GPIO group 0 */ | ||
| 91 | GINT1_IRQn = 3, /**< GPIO group 1 */ | ||
| 92 | PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ | ||
| 93 | PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ | ||
| 94 | PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ | ||
| 95 | PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ | ||
| 96 | UTICK0_IRQn = 8, /**< Micro-tick Timer */ | ||
| 97 | MRT0_IRQn = 9, /**< Multi-rate timer */ | ||
| 98 | CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ | ||
| 99 | CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ | ||
| 100 | SCT0_IRQn = 12, /**< SCTimer/PWM */ | ||
| 101 | CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ | ||
| 102 | FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 103 | FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 104 | FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 105 | FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 106 | FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 107 | FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ | ||
| 108 | FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ | ||
| 109 | FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ | ||
| 110 | ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ | ||
| 111 | ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ | ||
| 112 | ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ | ||
| 113 | DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ | ||
| 114 | HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ | ||
| 115 | USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ | ||
| 116 | USB0_IRQn = 28, /**< USB device */ | ||
| 117 | RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ | ||
| 118 | Reserved46_IRQn = 30, /**< Reserved interrupt */ | ||
| 119 | Reserved47_IRQn = 31, /**< Reserved interrupt */ | ||
| 120 | PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ | ||
| 121 | PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ | ||
| 122 | PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ | ||
| 123 | PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ | ||
| 124 | CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ | ||
| 125 | CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ | ||
| 126 | RIT_IRQn = 38, /**< Repetitive Interrupt Timer */ | ||
| 127 | SPIFI0_IRQn = 39, /**< SPI flash interface */ | ||
| 128 | FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 129 | FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ | ||
| 130 | SDIO_IRQn = 42, /**< SD/MMC */ | ||
| 131 | CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ | ||
| 132 | CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ | ||
| 133 | CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */ | ||
| 134 | CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */ | ||
| 135 | USB1_IRQn = 47, /**< USB1 interrupt */ | ||
| 136 | USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ | ||
| 137 | ETHERNET_IRQn = 49, /**< Ethernet */ | ||
| 138 | ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */ | ||
| 139 | ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */ | ||
| 140 | EEPROM_IRQn = 52, /**< EEPROM interrupt */ | ||
| 141 | LCD_IRQn = 53, /**< LCD interrupt */ | ||
| 142 | SHA_IRQn = 54, /**< SHA interrupt */ | ||
| 143 | SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */ | ||
| 144 | SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */ | ||
| 145 | } IRQn_Type; | ||
| 146 | |||
| 147 | /*! | ||
| 148 | * @} | ||
| 149 | */ /* end of group Interrupt_vector_numbers */ | ||
| 150 | |||
| 151 | |||
| 152 | /* ---------------------------------------------------------------------------- | ||
| 153 | -- Cortex M4 Core Configuration | ||
| 154 | ---------------------------------------------------------------------------- */ | ||
| 155 | |||
| 156 | /*! | ||
| 157 | * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration | ||
| 158 | * @{ | ||
| 159 | */ | ||
| 160 | |||
| 161 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 162 | #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ | ||
| 163 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 164 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 165 | |||
| 166 | #include "core_cm4.h" /* Core Peripheral Access Layer */ | ||
| 167 | #include "system_LPC54608.h" /* Device specific configuration file */ | ||
| 168 | |||
| 169 | /*! | ||
| 170 | * @} | ||
| 171 | */ /* end of group Cortex_Core_Configuration */ | ||
| 172 | |||
| 173 | |||
| 174 | /* ---------------------------------------------------------------------------- | ||
| 175 | -- Mapping Information | ||
| 176 | ---------------------------------------------------------------------------- */ | ||
| 177 | |||
| 178 | /*! | ||
| 179 | * @addtogroup Mapping_Information Mapping Information | ||
| 180 | * @{ | ||
| 181 | */ | ||
| 182 | |||
| 183 | /** Mapping Information */ | ||
| 184 | /*! | ||
| 185 | * @addtogroup dma_request | ||
| 186 | * @{ | ||
| 187 | */ | ||
| 188 | |||
| 189 | /******************************************************************************* | ||
| 190 | * Definitions | ||
| 191 | ******************************************************************************/ | ||
| 192 | |||
| 193 | /*! | ||
| 194 | * @brief Structure for the DMA hardware request | ||
| 195 | * | ||
| 196 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 197 | * hardware request to trigger the DMA transfer accordingly. The index | ||
| 198 | * of the hardware request varies according to the to SoC. | ||
| 199 | */ | ||
| 200 | typedef enum _dma_request_source | ||
| 201 | { | ||
| 202 | kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 203 | kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 204 | kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 205 | kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 206 | kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ | ||
| 207 | kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ | ||
| 208 | kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 209 | kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 210 | kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ | ||
| 211 | kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ | ||
| 212 | kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ | ||
| 213 | kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ | ||
| 214 | kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ | ||
| 215 | kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ | ||
| 216 | kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ | ||
| 217 | kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ | ||
| 218 | kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 channel 0 */ | ||
| 219 | kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 0 channel 1 */ | ||
| 220 | kDmaRequestSPIFI = 18U, /**< SPI Flash Interface */ | ||
| 221 | kDmaRequestSHA = 19U, /**< Reserved */ | ||
| 222 | kDmaRequestFlexcomm8Rx = 20U, /**< Flexcomm Interface 8 RX/I2C Slave */ | ||
| 223 | kDmaRequestFlexcomm8Tx = 21U, /**< Flexcomm Interface 8 TX/I2C Slave */ | ||
| 224 | kDmaRequestFlexcomm9Rx = 22U, /**< Flexcomm Interface 9 RX/I2C Slave */ | ||
| 225 | kDmaRequestFlexcomm9Tx = 23U, /**< Flexcomm Interface 9 TX/I2C Slave */ | ||
| 226 | kDmaRequestSMARTCARD0_RX = 24U, /**< SMARTCARD0 RX */ | ||
| 227 | kDmaRequestSMARTCARD0_TX = 25U, /**< SMARTCARD0 TX */ | ||
| 228 | kDmaRequestSMARTCARD1_RX = 26U, /**< SMARTCARD1 RX */ | ||
| 229 | kDmaRequestSMARTCARD1_TX = 27U, /**< SMARTCARD1 TX */ | ||
| 230 | kDmaRequestNoDMARequest28 = 28U, /**< No DMA request 28 */ | ||
| 231 | kDmaRequestNoDMARequest29 = 29U, /**< No DMA request 29 */ | ||
| 232 | } dma_request_source_t; | ||
| 233 | |||
| 234 | /* @} */ | ||
| 235 | |||
| 236 | |||
| 237 | /*! | ||
| 238 | * @} | ||
| 239 | */ /* end of group Mapping_Information */ | ||
| 240 | |||
| 241 | |||
| 242 | /* ---------------------------------------------------------------------------- | ||
| 243 | -- Device Peripheral Access Layer | ||
| 244 | ---------------------------------------------------------------------------- */ | ||
| 245 | |||
| 246 | /*! | ||
| 247 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 248 | * @{ | ||
| 249 | */ | ||
| 250 | |||
| 251 | |||
| 252 | /* | ||
| 253 | ** Start of section using anonymous unions | ||
| 254 | */ | ||
| 255 | |||
| 256 | #if defined(__ARMCC_VERSION) | ||
| 257 | #if (__ARMCC_VERSION >= 6010050) | ||
| 258 | #pragma clang diagnostic push | ||
| 259 | #else | ||
| 260 | #pragma push | ||
| 261 | #pragma anon_unions | ||
| 262 | #endif | ||
| 263 | #elif defined(__GNUC__) | ||
| 264 | /* anonymous unions are enabled by default */ | ||
| 265 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 266 | #pragma language=extended | ||
| 267 | #else | ||
| 268 | #error Not supported compiler type | ||
| 269 | #endif | ||
| 270 | |||
| 271 | /* ---------------------------------------------------------------------------- | ||
| 272 | -- ADC Peripheral Access Layer | ||
| 273 | ---------------------------------------------------------------------------- */ | ||
| 274 | |||
| 275 | /*! | ||
| 276 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 277 | * @{ | ||
| 278 | */ | ||
| 279 | |||
| 280 | /** ADC - Register Layout Typedef */ | ||
| 281 | typedef struct { | ||
| 282 | __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ | ||
| 283 | __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ | ||
| 284 | __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ | ||
| 285 | __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ | ||
| 286 | uint8_t RESERVED_0[8]; | ||
| 287 | __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ | ||
| 288 | __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ | ||
| 289 | __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ | ||
| 290 | __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ | ||
| 291 | __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ | ||
| 292 | __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ | ||
| 293 | __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ | ||
| 294 | __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ | ||
| 295 | __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ | ||
| 296 | __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ | ||
| 297 | } ADC_Type; | ||
| 298 | |||
| 299 | /* ---------------------------------------------------------------------------- | ||
| 300 | -- ADC Register Masks | ||
| 301 | ---------------------------------------------------------------------------- */ | ||
| 302 | |||
| 303 | /*! | ||
| 304 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 305 | * @{ | ||
| 306 | */ | ||
| 307 | |||
| 308 | /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ | ||
| 309 | /*! @{ */ | ||
| 310 | #define ADC_CTRL_CLKDIV_MASK (0xFFU) | ||
| 311 | #define ADC_CTRL_CLKDIV_SHIFT (0U) | ||
| 312 | /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce | ||
| 313 | * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, | ||
| 314 | * software should program the smallest value in this field that yields this maximum clock rate or | ||
| 315 | * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may | ||
| 316 | * be desirable. This field is ignored in the asynchronous operating mode. | ||
| 317 | */ | ||
| 318 | #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) | ||
| 319 | #define ADC_CTRL_ASYNMODE_MASK (0x100U) | ||
| 320 | #define ADC_CTRL_ASYNMODE_SHIFT (8U) | ||
| 321 | /*! ASYNMODE - Select clock mode. | ||
| 322 | * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in | ||
| 323 | * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to | ||
| 324 | * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. | ||
| 325 | * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC | ||
| 326 | * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger | ||
| 327 | * pulse. | ||
| 328 | * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. | ||
| 329 | */ | ||
| 330 | #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) | ||
| 331 | #define ADC_CTRL_RESOL_MASK (0x600U) | ||
| 332 | #define ADC_CTRL_RESOL_SHIFT (9U) | ||
| 333 | /*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher | ||
| 334 | * conversion rates. A single conversion (including one conversion in a burst or sequence) requires the | ||
| 335 | * selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when | ||
| 336 | * the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable | ||
| 337 | * results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate | ||
| 338 | * for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system | ||
| 339 | * clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution | ||
| 340 | * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. | ||
| 341 | * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. | ||
| 342 | * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. | ||
| 343 | * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. | ||
| 344 | */ | ||
| 345 | #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) | ||
| 346 | #define ADC_CTRL_BYPASSCAL_MASK (0x800U) | ||
| 347 | #define ADC_CTRL_BYPASSCAL_SHIFT (11U) | ||
| 348 | /*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset | ||
| 349 | * error is not a concern in the application. | ||
| 350 | * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for | ||
| 351 | * offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may | ||
| 352 | * be warranted periodically - especially if operating conditions have changed. | ||
| 353 | * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - | ||
| 354 | * particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. | ||
| 355 | */ | ||
| 356 | #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) | ||
| 357 | #define ADC_CTRL_TSAMP_MASK (0x7000U) | ||
| 358 | #define ADC_CTRL_TSAMP_SHIFT (12U) | ||
| 359 | /*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion | ||
| 360 | * is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions | ||
| 361 | * and the output impedance of the analog source, longer sampling times may be required. See | ||
| 362 | * Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to | ||
| 363 | * seven, by which the sample period will be extended. The total conversion time will increase by | ||
| 364 | * the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A | ||
| 365 | * complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will | ||
| 366 | * be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will | ||
| 367 | * require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock | ||
| 368 | * cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be | ||
| 369 | * extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require | ||
| 370 | * 22 ADC clocks. | ||
| 371 | */ | ||
| 372 | #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) | ||
| 373 | /*! @} */ | ||
| 374 | |||
| 375 | /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ | ||
| 376 | /*! @{ */ | ||
| 377 | #define ADC_INSEL_SEL_MASK (0x3U) | ||
| 378 | #define ADC_INSEL_SEL_SHIFT (0U) | ||
| 379 | /*! SEL - Selects the input source for channel 0. All other values are reserved. | ||
| 380 | * 0b00..ADC0_IN0 function. | ||
| 381 | * 0b11..Internal temperature sensor. | ||
| 382 | */ | ||
| 383 | #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) | ||
| 384 | /*! @} */ | ||
| 385 | |||
| 386 | /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ | ||
| 387 | /*! @{ */ | ||
| 388 | #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) | ||
| 389 | #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) | ||
| 390 | /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this | ||
| 391 | * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be | ||
| 392 | * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 | ||
| 393 | * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via | ||
| 394 | * software command, ADC conversions will be performed on each enabled channel, in sequence, | ||
| 395 | * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) | ||
| 396 | * is LOW. It is allowed to change this field and set bit 31 in the same write. | ||
| 397 | */ | ||
| 398 | #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) | ||
| 399 | #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) | ||
| 400 | #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) | ||
| 401 | /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion | ||
| 402 | * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order | ||
| 403 | * to avoid generating a spurious trigger, it is recommended writing to this field only when | ||
| 404 | * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. | ||
| 405 | */ | ||
| 406 | #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) | ||
| 407 | #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) | ||
| 408 | #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) | ||
| 409 | /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In | ||
| 410 | * order to avoid generating a spurious trigger, it is recommended writing to this field only when | ||
| 411 | * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. | ||
| 412 | * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. | ||
| 413 | * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. | ||
| 414 | */ | ||
| 415 | #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) | ||
| 416 | #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) | ||
| 417 | #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) | ||
| 418 | /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization | ||
| 419 | * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a | ||
| 420 | * conversion. There are slightly different criteria for whether or not this bit can be set | ||
| 421 | * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): | ||
| 422 | * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already | ||
| 423 | * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). | ||
| 424 | * Whether this bit is set or not, a trigger pulse must be maintained for at least one system | ||
| 425 | * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be | ||
| 426 | * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse | ||
| 427 | * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and | ||
| 428 | * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be | ||
| 429 | * maintained for one system clock period. | ||
| 430 | * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. | ||
| 431 | * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. | ||
| 432 | */ | ||
| 433 | #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) | ||
| 434 | #define ADC_SEQ_CTRL_START_MASK (0x4000000U) | ||
| 435 | #define ADC_SEQ_CTRL_START_SHIFT (26U) | ||
| 436 | /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The | ||
| 437 | * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this | ||
| 438 | * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a | ||
| 439 | * conversion sequence. It will consequently always read back as a zero. | ||
| 440 | */ | ||
| 441 | #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) | ||
| 442 | #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) | ||
| 443 | #define ADC_SEQ_CTRL_BURST_SHIFT (27U) | ||
| 444 | /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled | ||
| 445 | * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions | ||
| 446 | * can be halted by clearing this bit. The sequence currently in progress will be completed before | ||
| 447 | * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. | ||
| 448 | */ | ||
| 449 | #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) | ||
| 450 | #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) | ||
| 451 | #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) | ||
| 452 | /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a | ||
| 453 | * single conversion on the next channel in the sequence instead of the default response of | ||
| 454 | * launching an entire sequence of conversions. Once all of the channels comprising a sequence have | ||
| 455 | * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled | ||
| 456 | * channel. Interrupt generation will still occur either after each individual conversion or at | ||
| 457 | * the end of the entire sequence, depending on the state of the MODE bit. | ||
| 458 | */ | ||
| 459 | #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) | ||
| 460 | #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) | ||
| 461 | #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) | ||
| 462 | /*! LOWPRIO - Set priority for sequence A. | ||
| 463 | * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. | ||
| 464 | * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence | ||
| 465 | * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion | ||
| 466 | * currently in progress will be terminated. The A sequence that was interrupted will automatically resume | ||
| 467 | * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the | ||
| 468 | * conversion sequence will resume from that point. | ||
| 469 | */ | ||
| 470 | #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) | ||
| 471 | #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) | ||
| 472 | #define ADC_SEQ_CTRL_MODE_SHIFT (30U) | ||
| 473 | /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence | ||
| 474 | * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each | ||
| 475 | * conversion, or the individual channel result registers at the end of the entire sequence. Impacts | ||
| 476 | * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which | ||
| 477 | * overrun conditions contribute to an overrun interrupt as described below. | ||
| 478 | * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC | ||
| 479 | * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The | ||
| 480 | * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger | ||
| 481 | * if enabled. | ||
| 482 | * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A | ||
| 483 | * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in | ||
| 484 | * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun | ||
| 485 | * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. | ||
| 486 | */ | ||
| 487 | #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) | ||
| 488 | #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) | ||
| 489 | #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) | ||
| 490 | /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be | ||
| 491 | * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state | ||
| 492 | * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered | ||
| 493 | * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care | ||
| 494 | * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE | ||
| 495 | * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be | ||
| 496 | * triggered immediately upon being enabled. | ||
| 497 | * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence | ||
| 498 | * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is | ||
| 499 | * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. | ||
| 500 | * 0b1..Enabled. Sequence n is enabled. | ||
| 501 | */ | ||
| 502 | #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) | ||
| 503 | /*! @} */ | ||
| 504 | |||
| 505 | /* The count of ADC_SEQ_CTRL */ | ||
| 506 | #define ADC_SEQ_CTRL_COUNT (2U) | ||
| 507 | |||
| 508 | /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ | ||
| 509 | /*! @{ */ | ||
| 510 | #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) | ||
| 511 | #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) | ||
| 512 | /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion | ||
| 513 | * performed under conversion sequence associated with this register. The result is a binary | ||
| 514 | * fraction representing the voltage on the currently-selected input channel as it falls within the | ||
| 515 | * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less | ||
| 516 | * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input | ||
| 517 | * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this | ||
| 518 | * result has not yet been read. | ||
| 519 | */ | ||
| 520 | #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) | ||
| 521 | #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) | ||
| 522 | #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) | ||
| 523 | /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or | ||
| 524 | * within the range established by the designated threshold comparison registers (THRn_LOW and | ||
| 525 | * THRn_HIGH). | ||
| 526 | */ | ||
| 527 | #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) | ||
| 528 | #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) | ||
| 529 | #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) | ||
| 530 | /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a | ||
| 531 | * crossing of the threshold level established by the designated LOW threshold comparison register | ||
| 532 | * (THRn_LOW) and, if so, in what direction the crossing occurred. | ||
| 533 | */ | ||
| 534 | #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) | ||
| 535 | #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) | ||
| 536 | #define ADC_SEQ_GDAT_CHN_SHIFT (26U) | ||
| 537 | /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 | ||
| 538 | * identifies channel 0, 0001 channel 1, etc.). | ||
| 539 | */ | ||
| 540 | #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) | ||
| 541 | #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) | ||
| 542 | #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) | ||
| 543 | /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a | ||
| 544 | * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along | ||
| 545 | * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun | ||
| 546 | * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set | ||
| 547 | * to '0' (and if the overrun interrupt is enabled). | ||
| 548 | */ | ||
| 549 | #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) | ||
| 550 | #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) | ||
| 551 | #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) | ||
| 552 | /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded | ||
| 553 | * into the RESULT field. It is cleared whenever this register is read. This bit will cause a | ||
| 554 | * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that | ||
| 555 | * sequence is set to 0 (and if the interrupt is enabled). | ||
| 556 | */ | ||
| 557 | #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) | ||
| 558 | /*! @} */ | ||
| 559 | |||
| 560 | /* The count of ADC_SEQ_GDAT */ | ||
| 561 | #define ADC_SEQ_GDAT_COUNT (2U) | ||
| 562 | |||
| 563 | /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ | ||
| 564 | /*! @{ */ | ||
| 565 | #define ADC_DAT_RESULT_MASK (0xFFF0U) | ||
| 566 | #define ADC_DAT_RESULT_SHIFT (4U) | ||
| 567 | /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed | ||
| 568 | * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, | ||
| 569 | * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on | ||
| 570 | * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that | ||
| 571 | * the voltage on the input was close to, equal to, or greater than that on VREFP. | ||
| 572 | */ | ||
| 573 | #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) | ||
| 574 | #define ADC_DAT_THCMPRANGE_MASK (0x30000U) | ||
| 575 | #define ADC_DAT_THCMPRANGE_SHIFT (16U) | ||
| 576 | /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion | ||
| 577 | * was greater than or equal to the value programmed into the designated LOW threshold register | ||
| 578 | * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold | ||
| 579 | * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value | ||
| 580 | * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last | ||
| 581 | * completed conversion was greater than the value programmed into the designated HIGH threshold | ||
| 582 | * register (THRn_HIGH). 0x3 = Reserved. | ||
| 583 | */ | ||
| 584 | #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) | ||
| 585 | #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) | ||
| 586 | #define ADC_DAT_THCMPCROSS_SHIFT (18U) | ||
| 587 | /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The | ||
| 588 | * most recent completed conversion on this channel had the same relationship (above or below) to | ||
| 589 | * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the | ||
| 590 | * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing | ||
| 591 | * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the | ||
| 592 | * previous sample on this channel was above the threshold value established by the designated LOW | ||
| 593 | * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward | ||
| 594 | * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred | ||
| 595 | * - i.e. the previous sample on this channel was below the threshold value established by the | ||
| 596 | * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. | ||
| 597 | */ | ||
| 598 | #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) | ||
| 599 | #define ADC_DAT_CHANNEL_MASK (0x3C000000U) | ||
| 600 | #define ADC_DAT_CHANNEL_SHIFT (26U) | ||
| 601 | /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register | ||
| 602 | * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 | ||
| 603 | * register, etc) | ||
| 604 | */ | ||
| 605 | #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) | ||
| 606 | #define ADC_DAT_OVERRUN_MASK (0x40000000U) | ||
| 607 | #define ADC_DAT_OVERRUN_SHIFT (30U) | ||
| 608 | /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and | ||
| 609 | * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit | ||
| 610 | * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when | ||
| 611 | * the data related to this channel is read from either of the global SEQn_GDAT registers. This | ||
| 612 | * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if | ||
| 613 | * the overrun interrupt is enabled. While it is allowed to include the same channels in both | ||
| 614 | * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the | ||
| 615 | * data registers associated with any of the channels that are shared between the two sequences. Any | ||
| 616 | * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. | ||
| 617 | */ | ||
| 618 | #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) | ||
| 619 | #define ADC_DAT_DATAVALID_MASK (0x80000000U) | ||
| 620 | #define ADC_DAT_DATAVALID_SHIFT (31U) | ||
| 621 | /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is | ||
| 622 | * cleared whenever this register is read or when the data related to this channel is read from | ||
| 623 | * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in | ||
| 624 | * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in | ||
| 625 | * the data registers associated with any of the channels that are shared between the two | ||
| 626 | * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. | ||
| 627 | */ | ||
| 628 | #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) | ||
| 629 | /*! @} */ | ||
| 630 | |||
| 631 | /* The count of ADC_DAT */ | ||
| 632 | #define ADC_DAT_COUNT (12U) | ||
| 633 | |||
| 634 | /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ | ||
| 635 | /*! @{ */ | ||
| 636 | #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) | ||
| 637 | #define ADC_THR0_LOW_THRLOW_SHIFT (4U) | ||
| 638 | /*! THRLOW - Low threshold value against which ADC results will be compared | ||
| 639 | */ | ||
| 640 | #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) | ||
| 641 | /*! @} */ | ||
| 642 | |||
| 643 | /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ | ||
| 644 | /*! @{ */ | ||
| 645 | #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) | ||
| 646 | #define ADC_THR1_LOW_THRLOW_SHIFT (4U) | ||
| 647 | /*! THRLOW - Low threshold value against which ADC results will be compared | ||
| 648 | */ | ||
| 649 | #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) | ||
| 650 | /*! @} */ | ||
| 651 | |||
| 652 | /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ | ||
| 653 | /*! @{ */ | ||
| 654 | #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) | ||
| 655 | #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) | ||
| 656 | /*! THRHIGH - High threshold value against which ADC results will be compared | ||
| 657 | */ | ||
| 658 | #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) | ||
| 659 | /*! @} */ | ||
| 660 | |||
| 661 | /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ | ||
| 662 | /*! @{ */ | ||
| 663 | #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) | ||
| 664 | #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) | ||
| 665 | /*! THRHIGH - High threshold value against which ADC results will be compared | ||
| 666 | */ | ||
| 667 | #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) | ||
| 668 | /*! @} */ | ||
| 669 | |||
| 670 | /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ | ||
| 671 | /*! @{ */ | ||
| 672 | #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) | ||
| 673 | #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) | ||
| 674 | /*! CH0_THRSEL - Threshold select for channel 0. | ||
| 675 | * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. | ||
| 676 | * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. | ||
| 677 | */ | ||
| 678 | #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) | ||
| 679 | #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) | ||
| 680 | #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) | ||
| 681 | /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. | ||
| 682 | */ | ||
| 683 | #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) | ||
| 684 | #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) | ||
| 685 | #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) | ||
| 686 | /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. | ||
| 687 | */ | ||
| 688 | #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) | ||
| 689 | #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) | ||
| 690 | #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) | ||
| 691 | /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. | ||
| 692 | */ | ||
| 693 | #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) | ||
| 694 | #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) | ||
| 695 | #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) | ||
| 696 | /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. | ||
| 697 | */ | ||
| 698 | #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) | ||
| 699 | #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) | ||
| 700 | #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) | ||
| 701 | /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. | ||
| 702 | */ | ||
| 703 | #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) | ||
| 704 | #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) | ||
| 705 | #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) | ||
| 706 | /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. | ||
| 707 | */ | ||
| 708 | #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) | ||
| 709 | #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) | ||
| 710 | #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) | ||
| 711 | /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. | ||
| 712 | */ | ||
| 713 | #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) | ||
| 714 | #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) | ||
| 715 | #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) | ||
| 716 | /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. | ||
| 717 | */ | ||
| 718 | #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) | ||
| 719 | #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) | ||
| 720 | #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) | ||
| 721 | /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. | ||
| 722 | */ | ||
| 723 | #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) | ||
| 724 | #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) | ||
| 725 | #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) | ||
| 726 | /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. | ||
| 727 | */ | ||
| 728 | #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) | ||
| 729 | #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) | ||
| 730 | #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) | ||
| 731 | /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. | ||
| 732 | */ | ||
| 733 | #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) | ||
| 734 | /*! @} */ | ||
| 735 | |||
| 736 | /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ | ||
| 737 | /*! @{ */ | ||
| 738 | #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) | ||
| 739 | #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) | ||
| 740 | /*! SEQA_INTEN - Sequence A interrupt enable. | ||
| 741 | * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. | ||
| 742 | * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of | ||
| 743 | * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of | ||
| 744 | * conversions, depending on the MODE bit in the SEQA_CTRL register. | ||
| 745 | */ | ||
| 746 | #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) | ||
| 747 | #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) | ||
| 748 | #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) | ||
| 749 | /*! SEQB_INTEN - Sequence B interrupt enable. | ||
| 750 | * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. | ||
| 751 | * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of | ||
| 752 | * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of | ||
| 753 | * conversions, depending on the MODE bit in the SEQB_CTRL register. | ||
| 754 | */ | ||
| 755 | #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) | ||
| 756 | #define ADC_INTEN_OVR_INTEN_MASK (0x4U) | ||
| 757 | #define ADC_INTEN_OVR_INTEN_SHIFT (2U) | ||
| 758 | /*! OVR_INTEN - Overrun interrupt enable. | ||
| 759 | * 0b0..Disabled. The overrun interrupt is disabled. | ||
| 760 | * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel | ||
| 761 | * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular | ||
| 762 | * sequence is 0, then an overrun in the global data register for that sequence will also cause this | ||
| 763 | * interrupt/DMA trigger to be asserted. | ||
| 764 | */ | ||
| 765 | #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) | ||
| 766 | #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) | ||
| 767 | #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) | ||
| 768 | /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. | ||
| 769 | * 0b00..Disabled. | ||
| 770 | * 0b01..Outside threshold. | ||
| 771 | * 0b10..Crossing threshold. | ||
| 772 | * 0b11..Reserved | ||
| 773 | */ | ||
| 774 | #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) | ||
| 775 | #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) | ||
| 776 | #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) | ||
| 777 | /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. | ||
| 778 | */ | ||
| 779 | #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) | ||
| 780 | #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) | ||
| 781 | #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) | ||
| 782 | /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. | ||
| 783 | */ | ||
| 784 | #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) | ||
| 785 | #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) | ||
| 786 | #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) | ||
| 787 | /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. | ||
| 788 | */ | ||
| 789 | #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) | ||
| 790 | #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) | ||
| 791 | #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) | ||
| 792 | /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. | ||
| 793 | */ | ||
| 794 | #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) | ||
| 795 | #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) | ||
| 796 | #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) | ||
| 797 | /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. | ||
| 798 | */ | ||
| 799 | #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) | ||
| 800 | #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) | ||
| 801 | #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) | ||
| 802 | /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. | ||
| 803 | */ | ||
| 804 | #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) | ||
| 805 | #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) | ||
| 806 | #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) | ||
| 807 | /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. | ||
| 808 | */ | ||
| 809 | #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) | ||
| 810 | #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) | ||
| 811 | #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) | ||
| 812 | /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. | ||
| 813 | */ | ||
| 814 | #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) | ||
| 815 | #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) | ||
| 816 | #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) | ||
| 817 | /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. | ||
| 818 | */ | ||
| 819 | #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) | ||
| 820 | #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) | ||
| 821 | #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) | ||
| 822 | /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. | ||
| 823 | */ | ||
| 824 | #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) | ||
| 825 | #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) | ||
| 826 | #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) | ||
| 827 | /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. | ||
| 828 | */ | ||
| 829 | #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) | ||
| 830 | /*! @} */ | ||
| 831 | |||
| 832 | /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ | ||
| 833 | /*! @{ */ | ||
| 834 | #define ADC_FLAGS_THCMP0_MASK (0x1U) | ||
| 835 | #define ADC_FLAGS_THCMP0_SHIFT (0U) | ||
| 836 | /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or | ||
| 837 | * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by | ||
| 838 | * writing a 1. | ||
| 839 | */ | ||
| 840 | #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) | ||
| 841 | #define ADC_FLAGS_THCMP1_MASK (0x2U) | ||
| 842 | #define ADC_FLAGS_THCMP1_SHIFT (1U) | ||
| 843 | /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. | ||
| 844 | */ | ||
| 845 | #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) | ||
| 846 | #define ADC_FLAGS_THCMP2_MASK (0x4U) | ||
| 847 | #define ADC_FLAGS_THCMP2_SHIFT (2U) | ||
| 848 | /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. | ||
| 849 | */ | ||
| 850 | #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) | ||
| 851 | #define ADC_FLAGS_THCMP3_MASK (0x8U) | ||
| 852 | #define ADC_FLAGS_THCMP3_SHIFT (3U) | ||
| 853 | /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. | ||
| 854 | */ | ||
| 855 | #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) | ||
| 856 | #define ADC_FLAGS_THCMP4_MASK (0x10U) | ||
| 857 | #define ADC_FLAGS_THCMP4_SHIFT (4U) | ||
| 858 | /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. | ||
| 859 | */ | ||
| 860 | #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) | ||
| 861 | #define ADC_FLAGS_THCMP5_MASK (0x20U) | ||
| 862 | #define ADC_FLAGS_THCMP5_SHIFT (5U) | ||
| 863 | /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. | ||
| 864 | */ | ||
| 865 | #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) | ||
| 866 | #define ADC_FLAGS_THCMP6_MASK (0x40U) | ||
| 867 | #define ADC_FLAGS_THCMP6_SHIFT (6U) | ||
| 868 | /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. | ||
| 869 | */ | ||
| 870 | #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) | ||
| 871 | #define ADC_FLAGS_THCMP7_MASK (0x80U) | ||
| 872 | #define ADC_FLAGS_THCMP7_SHIFT (7U) | ||
| 873 | /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. | ||
| 874 | */ | ||
| 875 | #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) | ||
| 876 | #define ADC_FLAGS_THCMP8_MASK (0x100U) | ||
| 877 | #define ADC_FLAGS_THCMP8_SHIFT (8U) | ||
| 878 | /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. | ||
| 879 | */ | ||
| 880 | #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) | ||
| 881 | #define ADC_FLAGS_THCMP9_MASK (0x200U) | ||
| 882 | #define ADC_FLAGS_THCMP9_SHIFT (9U) | ||
| 883 | /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. | ||
| 884 | */ | ||
| 885 | #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) | ||
| 886 | #define ADC_FLAGS_THCMP10_MASK (0x400U) | ||
| 887 | #define ADC_FLAGS_THCMP10_SHIFT (10U) | ||
| 888 | /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. | ||
| 889 | */ | ||
| 890 | #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) | ||
| 891 | #define ADC_FLAGS_THCMP11_MASK (0x800U) | ||
| 892 | #define ADC_FLAGS_THCMP11_SHIFT (11U) | ||
| 893 | /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. | ||
| 894 | */ | ||
| 895 | #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) | ||
| 896 | #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) | ||
| 897 | #define ADC_FLAGS_OVERRUN0_SHIFT (12U) | ||
| 898 | /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 | ||
| 899 | */ | ||
| 900 | #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) | ||
| 901 | #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) | ||
| 902 | #define ADC_FLAGS_OVERRUN1_SHIFT (13U) | ||
| 903 | /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 | ||
| 904 | */ | ||
| 905 | #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) | ||
| 906 | #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) | ||
| 907 | #define ADC_FLAGS_OVERRUN2_SHIFT (14U) | ||
| 908 | /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 | ||
| 909 | */ | ||
| 910 | #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) | ||
| 911 | #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) | ||
| 912 | #define ADC_FLAGS_OVERRUN3_SHIFT (15U) | ||
| 913 | /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 | ||
| 914 | */ | ||
| 915 | #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) | ||
| 916 | #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) | ||
| 917 | #define ADC_FLAGS_OVERRUN4_SHIFT (16U) | ||
| 918 | /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 | ||
| 919 | */ | ||
| 920 | #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) | ||
| 921 | #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) | ||
| 922 | #define ADC_FLAGS_OVERRUN5_SHIFT (17U) | ||
| 923 | /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 | ||
| 924 | */ | ||
| 925 | #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) | ||
| 926 | #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) | ||
| 927 | #define ADC_FLAGS_OVERRUN6_SHIFT (18U) | ||
| 928 | /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 | ||
| 929 | */ | ||
| 930 | #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) | ||
| 931 | #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) | ||
| 932 | #define ADC_FLAGS_OVERRUN7_SHIFT (19U) | ||
| 933 | /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 | ||
| 934 | */ | ||
| 935 | #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) | ||
| 936 | #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) | ||
| 937 | #define ADC_FLAGS_OVERRUN8_SHIFT (20U) | ||
| 938 | /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 | ||
| 939 | */ | ||
| 940 | #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) | ||
| 941 | #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) | ||
| 942 | #define ADC_FLAGS_OVERRUN9_SHIFT (21U) | ||
| 943 | /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 | ||
| 944 | */ | ||
| 945 | #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) | ||
| 946 | #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) | ||
| 947 | #define ADC_FLAGS_OVERRUN10_SHIFT (22U) | ||
| 948 | /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 | ||
| 949 | */ | ||
| 950 | #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) | ||
| 951 | #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) | ||
| 952 | #define ADC_FLAGS_OVERRUN11_SHIFT (23U) | ||
| 953 | /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 | ||
| 954 | */ | ||
| 955 | #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) | ||
| 956 | #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) | ||
| 957 | #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) | ||
| 958 | /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register | ||
| 959 | */ | ||
| 960 | #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) | ||
| 961 | #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) | ||
| 962 | #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) | ||
| 963 | /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register | ||
| 964 | */ | ||
| 965 | #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) | ||
| 966 | #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) | ||
| 967 | #define ADC_FLAGS_SEQA_INT_SHIFT (28U) | ||
| 968 | /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, | ||
| 969 | * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which | ||
| 970 | * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared | ||
| 971 | * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register | ||
| 972 | * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be | ||
| 973 | * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN | ||
| 974 | * register. | ||
| 975 | */ | ||
| 976 | #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) | ||
| 977 | #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) | ||
| 978 | #define ADC_FLAGS_SEQB_INT_SHIFT (29U) | ||
| 979 | /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, | ||
| 980 | * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which | ||
| 981 | * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared | ||
| 982 | * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register | ||
| 983 | * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be | ||
| 984 | * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN | ||
| 985 | * register. | ||
| 986 | */ | ||
| 987 | #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) | ||
| 988 | #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) | ||
| 989 | #define ADC_FLAGS_THCMP_INT_SHIFT (30U) | ||
| 990 | /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in | ||
| 991 | * the lower bits of this register are set to 1 (due to an enabled out-of-range or | ||
| 992 | * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be | ||
| 993 | * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared | ||
| 994 | * when all of the individual threshold flags are cleared via writing 1s to those bits. | ||
| 995 | */ | ||
| 996 | #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) | ||
| 997 | #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) | ||
| 998 | #define ADC_FLAGS_OVR_INT_SHIFT (31U) | ||
| 999 | /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data | ||
| 1000 | * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers | ||
| 1001 | * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this | ||
| 1002 | * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all | ||
| 1003 | * of the individual overrun bits have been cleared via reading the corresponding data registers. | ||
| 1004 | */ | ||
| 1005 | #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) | ||
| 1006 | /*! @} */ | ||
| 1007 | |||
| 1008 | /*! @name STARTUP - ADC Startup register. */ | ||
| 1009 | /*! @{ */ | ||
| 1010 | #define ADC_STARTUP_ADC_ENA_MASK (0x1U) | ||
| 1011 | #define ADC_STARTUP_ADC_ENA_SHIFT (0U) | ||
| 1012 | /*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared | ||
| 1013 | * automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds | ||
| 1014 | * after the ADC is powered up (typically by altering a system-level ADC power control bit). | ||
| 1015 | */ | ||
| 1016 | #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) | ||
| 1017 | #define ADC_STARTUP_ADC_INIT_MASK (0x2U) | ||
| 1018 | #define ADC_STARTUP_ADC_INIT_SHIFT (1U) | ||
| 1019 | /*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine | ||
| 1020 | * will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not | ||
| 1021 | * calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is | ||
| 1022 | * required if a calibration is not performed. It will also reload the stored calibration value from | ||
| 1023 | * a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the | ||
| 1024 | * ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or | ||
| 1025 | * an ADC dummy conversion cycle is required. It should not be set during the same write that | ||
| 1026 | * sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically | ||
| 1027 | * when the 'dummy' conversion cycle completes. | ||
| 1028 | */ | ||
| 1029 | #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) | ||
| 1030 | /*! @} */ | ||
| 1031 | |||
| 1032 | /*! @name CALIB - ADC Calibration register. */ | ||
| 1033 | /*! @{ */ | ||
| 1034 | #define ADC_CALIB_CALIB_MASK (0x1U) | ||
| 1035 | #define ADC_CALIB_CALIB_SHIFT (0U) | ||
| 1036 | /*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can | ||
| 1037 | * only be set to a '1' by software. It is cleared automatically when the calibration cycle | ||
| 1038 | * completes. | ||
| 1039 | */ | ||
| 1040 | #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) | ||
| 1041 | #define ADC_CALIB_CALREQD_MASK (0x2U) | ||
| 1042 | #define ADC_CALIB_CALREQD_SHIFT (1U) | ||
| 1043 | /*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when | ||
| 1044 | * enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was | ||
| 1045 | * powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to | ||
| 1046 | * determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP | ||
| 1047 | * register) to launch the ADC initialization process which includes a 'dummy' conversion cycle. | ||
| 1048 | * Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks | ||
| 1049 | * required for calibration. | ||
| 1050 | */ | ||
| 1051 | #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) | ||
| 1052 | #define ADC_CALIB_CALVALUE_MASK (0x1FCU) | ||
| 1053 | #define ADC_CALIB_CALVALUE_SHIFT (2U) | ||
| 1054 | /*! CALVALUE - Calibration Value. This read-only field displays the calibration value established | ||
| 1055 | * during last calibration cycle. This value is not typically of any use to the user. | ||
| 1056 | */ | ||
| 1057 | #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) | ||
| 1058 | /*! @} */ | ||
| 1059 | |||
| 1060 | |||
| 1061 | /*! | ||
| 1062 | * @} | ||
| 1063 | */ /* end of group ADC_Register_Masks */ | ||
| 1064 | |||
| 1065 | |||
| 1066 | /* ADC - Peripheral instance base addresses */ | ||
| 1067 | /** Peripheral ADC0 base address */ | ||
| 1068 | #define ADC0_BASE (0x400A0000u) | ||
| 1069 | /** Peripheral ADC0 base pointer */ | ||
| 1070 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1071 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1072 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1073 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1074 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1075 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1076 | #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } | ||
| 1077 | #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } | ||
| 1078 | |||
| 1079 | /*! | ||
| 1080 | * @} | ||
| 1081 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1082 | |||
| 1083 | |||
| 1084 | /* ---------------------------------------------------------------------------- | ||
| 1085 | -- ASYNC_SYSCON Peripheral Access Layer | ||
| 1086 | ---------------------------------------------------------------------------- */ | ||
| 1087 | |||
| 1088 | /*! | ||
| 1089 | * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer | ||
| 1090 | * @{ | ||
| 1091 | */ | ||
| 1092 | |||
| 1093 | /** ASYNC_SYSCON - Register Layout Typedef */ | ||
| 1094 | typedef struct { | ||
| 1095 | __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ | ||
| 1096 | __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ | ||
| 1097 | __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ | ||
| 1098 | uint8_t RESERVED_0[4]; | ||
| 1099 | __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ | ||
| 1100 | __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ | ||
| 1101 | __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ | ||
| 1102 | uint8_t RESERVED_1[4]; | ||
| 1103 | __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ | ||
| 1104 | } ASYNC_SYSCON_Type; | ||
| 1105 | |||
| 1106 | /* ---------------------------------------------------------------------------- | ||
| 1107 | -- ASYNC_SYSCON Register Masks | ||
| 1108 | ---------------------------------------------------------------------------- */ | ||
| 1109 | |||
| 1110 | /*! | ||
| 1111 | * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks | ||
| 1112 | * @{ | ||
| 1113 | */ | ||
| 1114 | |||
| 1115 | /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ | ||
| 1116 | /*! @{ */ | ||
| 1117 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) | ||
| 1118 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) | ||
| 1119 | /*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. | ||
| 1120 | */ | ||
| 1121 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) | ||
| 1122 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) | ||
| 1123 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) | ||
| 1124 | /*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function. | ||
| 1125 | */ | ||
| 1126 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) | ||
| 1127 | /*! @} */ | ||
| 1128 | |||
| 1129 | /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ | ||
| 1130 | /*! @{ */ | ||
| 1131 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) | ||
| 1132 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) | ||
| 1133 | /*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the | ||
| 1134 | * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in | ||
| 1135 | * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. | ||
| 1136 | */ | ||
| 1137 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) | ||
| 1138 | /*! @} */ | ||
| 1139 | |||
| 1140 | /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ | ||
| 1141 | /*! @{ */ | ||
| 1142 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) | ||
| 1143 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) | ||
| 1144 | /*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the | ||
| 1145 | * ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in | ||
| 1146 | * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. | ||
| 1147 | */ | ||
| 1148 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) | ||
| 1149 | /*! @} */ | ||
| 1150 | |||
| 1151 | /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ | ||
| 1152 | /*! @{ */ | ||
| 1153 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) | ||
| 1154 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) | ||
| 1155 | /*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable. | ||
| 1156 | */ | ||
| 1157 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) | ||
| 1158 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) | ||
| 1159 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) | ||
| 1160 | /*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable. | ||
| 1161 | */ | ||
| 1162 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) | ||
| 1163 | /*! @} */ | ||
| 1164 | |||
| 1165 | /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ | ||
| 1166 | /*! @{ */ | ||
| 1167 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) | ||
| 1168 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) | ||
| 1169 | /*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the | ||
| 1170 | * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in | ||
| 1171 | * ASYNCPRESETCTRL are reserved and only zeroes should be written to them. | ||
| 1172 | */ | ||
| 1173 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) | ||
| 1174 | /*! @} */ | ||
| 1175 | |||
| 1176 | /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ | ||
| 1177 | /*! @{ */ | ||
| 1178 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) | ||
| 1179 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) | ||
| 1180 | /*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the | ||
| 1181 | * ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in | ||
| 1182 | * ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them. | ||
| 1183 | */ | ||
| 1184 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) | ||
| 1185 | /*! @} */ | ||
| 1186 | |||
| 1187 | /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ | ||
| 1188 | /*! @{ */ | ||
| 1189 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) | ||
| 1190 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) | ||
| 1191 | /*! SEL - Clock source for asynchronous clock source selector A | ||
| 1192 | * 0b00..Main clock (main_clk) | ||
| 1193 | * 0b01..FRO 12 MHz (fro_12m) | ||
| 1194 | * 0b10..Audio PLL clock.(AUDPLL_BYPASS) | ||
| 1195 | * 0b11..fc6 fclk (fc6_fclk) | ||
| 1196 | */ | ||
| 1197 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) | ||
| 1198 | /*! @} */ | ||
| 1199 | |||
| 1200 | |||
| 1201 | /*! | ||
| 1202 | * @} | ||
| 1203 | */ /* end of group ASYNC_SYSCON_Register_Masks */ | ||
| 1204 | |||
| 1205 | |||
| 1206 | /* ASYNC_SYSCON - Peripheral instance base addresses */ | ||
| 1207 | /** Peripheral ASYNC_SYSCON base address */ | ||
| 1208 | #define ASYNC_SYSCON_BASE (0x40040000u) | ||
| 1209 | /** Peripheral ASYNC_SYSCON base pointer */ | ||
| 1210 | #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) | ||
| 1211 | /** Array initializer of ASYNC_SYSCON peripheral base addresses */ | ||
| 1212 | #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } | ||
| 1213 | /** Array initializer of ASYNC_SYSCON peripheral base pointers */ | ||
| 1214 | #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } | ||
| 1215 | |||
| 1216 | /*! | ||
| 1217 | * @} | ||
| 1218 | */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ | ||
| 1219 | |||
| 1220 | |||
| 1221 | /* ---------------------------------------------------------------------------- | ||
| 1222 | -- CAN Peripheral Access Layer | ||
| 1223 | ---------------------------------------------------------------------------- */ | ||
| 1224 | |||
| 1225 | /*! | ||
| 1226 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 1227 | * @{ | ||
| 1228 | */ | ||
| 1229 | |||
| 1230 | /** CAN - Register Layout Typedef */ | ||
| 1231 | typedef struct { | ||
| 1232 | uint8_t RESERVED_0[16]; | ||
| 1233 | __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ | ||
| 1234 | uint8_t RESERVED_1[4]; | ||
| 1235 | __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ | ||
| 1236 | __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ | ||
| 1237 | __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ | ||
| 1238 | __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ | ||
| 1239 | __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ | ||
| 1240 | __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ | ||
| 1241 | uint8_t RESERVED_2[16]; | ||
| 1242 | __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ | ||
| 1243 | __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ | ||
| 1244 | __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ | ||
| 1245 | uint8_t RESERVED_3[4]; | ||
| 1246 | __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ | ||
| 1247 | __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ | ||
| 1248 | __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ | ||
| 1249 | __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ | ||
| 1250 | uint8_t RESERVED_4[32]; | ||
| 1251 | __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ | ||
| 1252 | __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ | ||
| 1253 | __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ | ||
| 1254 | uint8_t RESERVED_5[4]; | ||
| 1255 | __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ | ||
| 1256 | __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ | ||
| 1257 | __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ | ||
| 1258 | __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ | ||
| 1259 | __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ | ||
| 1260 | __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ | ||
| 1261 | __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ | ||
| 1262 | __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ | ||
| 1263 | __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ | ||
| 1264 | __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ | ||
| 1265 | __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ | ||
| 1266 | __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ | ||
| 1267 | __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ | ||
| 1268 | __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ | ||
| 1269 | __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ | ||
| 1270 | __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ | ||
| 1271 | __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ | ||
| 1272 | __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ | ||
| 1273 | __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ | ||
| 1274 | __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ | ||
| 1275 | __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ | ||
| 1276 | __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ | ||
| 1277 | uint8_t RESERVED_6[8]; | ||
| 1278 | __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ | ||
| 1279 | __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ | ||
| 1280 | __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ | ||
| 1281 | uint8_t RESERVED_7[260]; | ||
| 1282 | __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ | ||
| 1283 | uint8_t RESERVED_8[508]; | ||
| 1284 | __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ | ||
| 1285 | uint8_t RESERVED_9[508]; | ||
| 1286 | __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ | ||
| 1287 | } CAN_Type; | ||
| 1288 | |||
| 1289 | /* ---------------------------------------------------------------------------- | ||
| 1290 | -- CAN Register Masks | ||
| 1291 | ---------------------------------------------------------------------------- */ | ||
| 1292 | |||
| 1293 | /*! | ||
| 1294 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 1295 | * @{ | ||
| 1296 | */ | ||
| 1297 | |||
| 1298 | /*! @name TEST - Test Register */ | ||
| 1299 | /*! @{ */ | ||
| 1300 | #define CAN_TEST_LBCK_MASK (0x10U) | ||
| 1301 | #define CAN_TEST_LBCK_SHIFT (4U) | ||
| 1302 | /*! LBCK - Loop back mode. | ||
| 1303 | */ | ||
| 1304 | #define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) | ||
| 1305 | #define CAN_TEST_TX_MASK (0x60U) | ||
| 1306 | #define CAN_TEST_TX_SHIFT (5U) | ||
| 1307 | /*! TX - Control of transmit pin. | ||
| 1308 | */ | ||
| 1309 | #define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) | ||
| 1310 | #define CAN_TEST_RX_MASK (0x80U) | ||
| 1311 | #define CAN_TEST_RX_SHIFT (7U) | ||
| 1312 | /*! RX - Monitors the actual value of the CAN_RXD. | ||
| 1313 | */ | ||
| 1314 | #define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) | ||
| 1315 | /*! @} */ | ||
| 1316 | |||
| 1317 | /*! @name CCCR - CC Control Register */ | ||
| 1318 | /*! @{ */ | ||
| 1319 | #define CAN_CCCR_INIT_MASK (0x1U) | ||
| 1320 | #define CAN_CCCR_INIT_SHIFT (0U) | ||
| 1321 | /*! INIT - Initialization. | ||
| 1322 | */ | ||
| 1323 | #define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) | ||
| 1324 | #define CAN_CCCR_CCE_MASK (0x2U) | ||
| 1325 | #define CAN_CCCR_CCE_SHIFT (1U) | ||
| 1326 | /*! CCE - Configuration change enable. | ||
| 1327 | */ | ||
| 1328 | #define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) | ||
| 1329 | #define CAN_CCCR_ASM_MASK (0x4U) | ||
| 1330 | #define CAN_CCCR_ASM_SHIFT (2U) | ||
| 1331 | /*! ASM - Restricted operational mode. | ||
| 1332 | */ | ||
| 1333 | #define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) | ||
| 1334 | #define CAN_CCCR_CSA_MASK (0x8U) | ||
| 1335 | #define CAN_CCCR_CSA_SHIFT (3U) | ||
| 1336 | /*! CSA - Clock Stop Acknowledge. | ||
| 1337 | */ | ||
| 1338 | #define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) | ||
| 1339 | #define CAN_CCCR_CSR_MASK (0x10U) | ||
| 1340 | #define CAN_CCCR_CSR_SHIFT (4U) | ||
| 1341 | /*! CSR - Clock Stop Request. | ||
| 1342 | */ | ||
| 1343 | #define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) | ||
| 1344 | #define CAN_CCCR_MON_MASK (0x20U) | ||
| 1345 | #define CAN_CCCR_MON_SHIFT (5U) | ||
| 1346 | /*! MON - Bus monitoring mode. | ||
| 1347 | */ | ||
| 1348 | #define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) | ||
| 1349 | #define CAN_CCCR_DAR_MASK (0x40U) | ||
| 1350 | #define CAN_CCCR_DAR_SHIFT (6U) | ||
| 1351 | /*! DAR - Disable automatic retransmission. | ||
| 1352 | */ | ||
| 1353 | #define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) | ||
| 1354 | #define CAN_CCCR_TEST_MASK (0x80U) | ||
| 1355 | #define CAN_CCCR_TEST_SHIFT (7U) | ||
| 1356 | /*! TEST - Test mode enable. | ||
| 1357 | */ | ||
| 1358 | #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) | ||
| 1359 | #define CAN_CCCR_PXHD_MASK (0x1000U) | ||
| 1360 | #define CAN_CCCR_PXHD_SHIFT (12U) | ||
| 1361 | /*! PXHD - Protocol exception handling disable. | ||
| 1362 | */ | ||
| 1363 | #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) | ||
| 1364 | #define CAN_CCCR_EFBI_MASK (0x2000U) | ||
| 1365 | #define CAN_CCCR_EFBI_SHIFT (13U) | ||
| 1366 | /*! EFBI - Edge filtering during bus integration. | ||
| 1367 | */ | ||
| 1368 | #define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) | ||
| 1369 | #define CAN_CCCR_TXP_MASK (0x4000U) | ||
| 1370 | #define CAN_CCCR_TXP_SHIFT (14U) | ||
| 1371 | /*! TXP - Transmit pause. | ||
| 1372 | */ | ||
| 1373 | #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) | ||
| 1374 | /*! @} */ | ||
| 1375 | |||
| 1376 | /*! @name NBTP - Nominal Bit Timing and Prescaler Register */ | ||
| 1377 | /*! @{ */ | ||
| 1378 | #define CAN_NBTP_NTSEG2_MASK (0x7FU) | ||
| 1379 | #define CAN_NBTP_NTSEG2_SHIFT (0U) | ||
| 1380 | /*! NTSEG2 - Nominal time segment after sample point. | ||
| 1381 | */ | ||
| 1382 | #define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) | ||
| 1383 | #define CAN_NBTP_NTSEG1_MASK (0xFF00U) | ||
| 1384 | #define CAN_NBTP_NTSEG1_SHIFT (8U) | ||
| 1385 | /*! NTSEG1 - Nominal time segment before sample point. | ||
| 1386 | */ | ||
| 1387 | #define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) | ||
| 1388 | #define CAN_NBTP_NBRP_MASK (0x1FF0000U) | ||
| 1389 | #define CAN_NBTP_NBRP_SHIFT (16U) | ||
| 1390 | /*! NBRP - Nominal bit rate prescaler. | ||
| 1391 | */ | ||
| 1392 | #define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) | ||
| 1393 | #define CAN_NBTP_NSJW_MASK (0xFE000000U) | ||
| 1394 | #define CAN_NBTP_NSJW_SHIFT (25U) | ||
| 1395 | /*! NSJW - Nominal (re)synchronization jump width. | ||
| 1396 | */ | ||
| 1397 | #define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) | ||
| 1398 | /*! @} */ | ||
| 1399 | |||
| 1400 | /*! @name TSCC - Timestamp Counter Configuration */ | ||
| 1401 | /*! @{ */ | ||
| 1402 | #define CAN_TSCC_TSS_MASK (0x3U) | ||
| 1403 | #define CAN_TSCC_TSS_SHIFT (0U) | ||
| 1404 | /*! TSS - Timestamp select. | ||
| 1405 | */ | ||
| 1406 | #define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) | ||
| 1407 | #define CAN_TSCC_TCP_MASK (0xF0000U) | ||
| 1408 | #define CAN_TSCC_TCP_SHIFT (16U) | ||
| 1409 | /*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. | ||
| 1410 | */ | ||
| 1411 | #define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) | ||
| 1412 | /*! @} */ | ||
| 1413 | |||
| 1414 | /*! @name TSCV - Timestamp Counter Value */ | ||
| 1415 | /*! @{ */ | ||
| 1416 | #define CAN_TSCV_TSC_MASK (0xFFFFU) | ||
| 1417 | #define CAN_TSCV_TSC_SHIFT (0U) | ||
| 1418 | /*! TSC - Timestamp counter. | ||
| 1419 | */ | ||
| 1420 | #define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) | ||
| 1421 | /*! @} */ | ||
| 1422 | |||
| 1423 | /*! @name TOCC - Timeout Counter Configuration */ | ||
| 1424 | /*! @{ */ | ||
| 1425 | #define CAN_TOCC_ETOC_MASK (0x1U) | ||
| 1426 | #define CAN_TOCC_ETOC_SHIFT (0U) | ||
| 1427 | /*! ETOC - Enable timeout counter. | ||
| 1428 | */ | ||
| 1429 | #define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) | ||
| 1430 | #define CAN_TOCC_TOS_MASK (0x6U) | ||
| 1431 | #define CAN_TOCC_TOS_SHIFT (1U) | ||
| 1432 | /*! TOS - Timeout select. | ||
| 1433 | */ | ||
| 1434 | #define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) | ||
| 1435 | #define CAN_TOCC_TOP_MASK (0xFFFF0000U) | ||
| 1436 | #define CAN_TOCC_TOP_SHIFT (16U) | ||
| 1437 | /*! TOP - Timeout period. | ||
| 1438 | */ | ||
| 1439 | #define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) | ||
| 1440 | /*! @} */ | ||
| 1441 | |||
| 1442 | /*! @name TOCV - Timeout Counter Value */ | ||
| 1443 | /*! @{ */ | ||
| 1444 | #define CAN_TOCV_TOC_MASK (0xFFFFU) | ||
| 1445 | #define CAN_TOCV_TOC_SHIFT (0U) | ||
| 1446 | /*! TOC - Timeout counter. | ||
| 1447 | */ | ||
| 1448 | #define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) | ||
| 1449 | /*! @} */ | ||
| 1450 | |||
| 1451 | /*! @name ECR - Error Counter Register */ | ||
| 1452 | /*! @{ */ | ||
| 1453 | #define CAN_ECR_TEC_MASK (0xFFU) | ||
| 1454 | #define CAN_ECR_TEC_SHIFT (0U) | ||
| 1455 | /*! TEC - Transmit error counter. | ||
| 1456 | */ | ||
| 1457 | #define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) | ||
| 1458 | #define CAN_ECR_REC_MASK (0x7F00U) | ||
| 1459 | #define CAN_ECR_REC_SHIFT (8U) | ||
| 1460 | /*! REC - Receive error counter. | ||
| 1461 | */ | ||
| 1462 | #define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) | ||
| 1463 | #define CAN_ECR_RP_MASK (0x8000U) | ||
| 1464 | #define CAN_ECR_RP_SHIFT (15U) | ||
| 1465 | /*! RP - Receive error passive. | ||
| 1466 | */ | ||
| 1467 | #define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) | ||
| 1468 | #define CAN_ECR_CEL_MASK (0xFF0000U) | ||
| 1469 | #define CAN_ECR_CEL_SHIFT (16U) | ||
| 1470 | /*! CEL - CAN error logging. | ||
| 1471 | */ | ||
| 1472 | #define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) | ||
| 1473 | /*! @} */ | ||
| 1474 | |||
| 1475 | /*! @name PSR - Protocol Status Register */ | ||
| 1476 | /*! @{ */ | ||
| 1477 | #define CAN_PSR_LEC_MASK (0x7U) | ||
| 1478 | #define CAN_PSR_LEC_SHIFT (0U) | ||
| 1479 | /*! LEC - Last error code. | ||
| 1480 | */ | ||
| 1481 | #define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) | ||
| 1482 | #define CAN_PSR_ACT_MASK (0x18U) | ||
| 1483 | #define CAN_PSR_ACT_SHIFT (3U) | ||
| 1484 | /*! ACT - Activity. | ||
| 1485 | */ | ||
| 1486 | #define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) | ||
| 1487 | #define CAN_PSR_EP_MASK (0x20U) | ||
| 1488 | #define CAN_PSR_EP_SHIFT (5U) | ||
| 1489 | /*! EP - Error Passive. | ||
| 1490 | */ | ||
| 1491 | #define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) | ||
| 1492 | #define CAN_PSR_EW_MASK (0x40U) | ||
| 1493 | #define CAN_PSR_EW_SHIFT (6U) | ||
| 1494 | /*! EW - Warning status. | ||
| 1495 | */ | ||
| 1496 | #define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) | ||
| 1497 | #define CAN_PSR_BO_MASK (0x80U) | ||
| 1498 | #define CAN_PSR_BO_SHIFT (7U) | ||
| 1499 | /*! BO - Bus Off Status. | ||
| 1500 | */ | ||
| 1501 | #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) | ||
| 1502 | #define CAN_PSR_PXE_MASK (0x4000U) | ||
| 1503 | #define CAN_PSR_PXE_SHIFT (14U) | ||
| 1504 | /*! PXE - Protocol exception event. | ||
| 1505 | */ | ||
| 1506 | #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) | ||
| 1507 | #define CAN_PSR_TDCV_MASK (0x7F0000U) | ||
| 1508 | #define CAN_PSR_TDCV_SHIFT (16U) | ||
| 1509 | /*! TDCV - Transmitter delay compensation value. | ||
| 1510 | */ | ||
| 1511 | #define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) | ||
| 1512 | /*! @} */ | ||
| 1513 | |||
| 1514 | /*! @name TDCR - Transmitter Delay Compensator Register */ | ||
| 1515 | /*! @{ */ | ||
| 1516 | #define CAN_TDCR_TDCF_MASK (0x7FU) | ||
| 1517 | #define CAN_TDCR_TDCF_SHIFT (0U) | ||
| 1518 | /*! TDCF - Transmitter delay compensation filter window length. | ||
| 1519 | */ | ||
| 1520 | #define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) | ||
| 1521 | #define CAN_TDCR_TDCO_MASK (0x7F00U) | ||
| 1522 | #define CAN_TDCR_TDCO_SHIFT (8U) | ||
| 1523 | /*! TDCO - Transmitter delay compensation offset. | ||
| 1524 | */ | ||
| 1525 | #define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) | ||
| 1526 | /*! @} */ | ||
| 1527 | |||
| 1528 | /*! @name IR - Interrupt Register */ | ||
| 1529 | /*! @{ */ | ||
| 1530 | #define CAN_IR_RF0N_MASK (0x1U) | ||
| 1531 | #define CAN_IR_RF0N_SHIFT (0U) | ||
| 1532 | /*! RF0N - Rx FIFO 0 new message. | ||
| 1533 | */ | ||
| 1534 | #define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) | ||
| 1535 | #define CAN_IR_RF0W_MASK (0x2U) | ||
| 1536 | #define CAN_IR_RF0W_SHIFT (1U) | ||
| 1537 | /*! RF0W - Rx FIFO 0 watermark reached. | ||
| 1538 | */ | ||
| 1539 | #define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) | ||
| 1540 | #define CAN_IR_RF0F_MASK (0x4U) | ||
| 1541 | #define CAN_IR_RF0F_SHIFT (2U) | ||
| 1542 | /*! RF0F - Rx FIFO 0 full. | ||
| 1543 | */ | ||
| 1544 | #define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) | ||
| 1545 | #define CAN_IR_RF0L_MASK (0x8U) | ||
| 1546 | #define CAN_IR_RF0L_SHIFT (3U) | ||
| 1547 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 1548 | */ | ||
| 1549 | #define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) | ||
| 1550 | #define CAN_IR_RF1N_MASK (0x10U) | ||
| 1551 | #define CAN_IR_RF1N_SHIFT (4U) | ||
| 1552 | /*! RF1N - Rx FIFO 1 new message. | ||
| 1553 | */ | ||
| 1554 | #define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) | ||
| 1555 | #define CAN_IR_RF1W_MASK (0x20U) | ||
| 1556 | #define CAN_IR_RF1W_SHIFT (5U) | ||
| 1557 | /*! RF1W - Rx FIFO 1 watermark reached. | ||
| 1558 | */ | ||
| 1559 | #define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) | ||
| 1560 | #define CAN_IR_RF1F_MASK (0x40U) | ||
| 1561 | #define CAN_IR_RF1F_SHIFT (6U) | ||
| 1562 | /*! RF1F - Rx FIFO 1 full. | ||
| 1563 | */ | ||
| 1564 | #define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) | ||
| 1565 | #define CAN_IR_RF1L_MASK (0x80U) | ||
| 1566 | #define CAN_IR_RF1L_SHIFT (7U) | ||
| 1567 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 1568 | */ | ||
| 1569 | #define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) | ||
| 1570 | #define CAN_IR_HPM_MASK (0x100U) | ||
| 1571 | #define CAN_IR_HPM_SHIFT (8U) | ||
| 1572 | /*! HPM - High priority message. | ||
| 1573 | */ | ||
| 1574 | #define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) | ||
| 1575 | #define CAN_IR_TC_MASK (0x200U) | ||
| 1576 | #define CAN_IR_TC_SHIFT (9U) | ||
| 1577 | /*! TC - Transmission completed. | ||
| 1578 | */ | ||
| 1579 | #define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) | ||
| 1580 | #define CAN_IR_TCF_MASK (0x400U) | ||
| 1581 | #define CAN_IR_TCF_SHIFT (10U) | ||
| 1582 | /*! TCF - Transmission cancellation finished. | ||
| 1583 | */ | ||
| 1584 | #define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) | ||
| 1585 | #define CAN_IR_TFE_MASK (0x800U) | ||
| 1586 | #define CAN_IR_TFE_SHIFT (11U) | ||
| 1587 | /*! TFE - Tx FIFO empty. | ||
| 1588 | */ | ||
| 1589 | #define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) | ||
| 1590 | #define CAN_IR_TEFN_MASK (0x1000U) | ||
| 1591 | #define CAN_IR_TEFN_SHIFT (12U) | ||
| 1592 | /*! TEFN - Tx event FIFO new entry. | ||
| 1593 | */ | ||
| 1594 | #define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) | ||
| 1595 | #define CAN_IR_TEFW_MASK (0x2000U) | ||
| 1596 | #define CAN_IR_TEFW_SHIFT (13U) | ||
| 1597 | /*! TEFW - Tx event FIFO watermark reached. | ||
| 1598 | */ | ||
| 1599 | #define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) | ||
| 1600 | #define CAN_IR_TEFF_MASK (0x4000U) | ||
| 1601 | #define CAN_IR_TEFF_SHIFT (14U) | ||
| 1602 | /*! TEFF - Tx event FIFO full. | ||
| 1603 | */ | ||
| 1604 | #define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) | ||
| 1605 | #define CAN_IR_TEFL_MASK (0x8000U) | ||
| 1606 | #define CAN_IR_TEFL_SHIFT (15U) | ||
| 1607 | /*! TEFL - Tx event FIFO element lost. | ||
| 1608 | */ | ||
| 1609 | #define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) | ||
| 1610 | #define CAN_IR_TSW_MASK (0x10000U) | ||
| 1611 | #define CAN_IR_TSW_SHIFT (16U) | ||
| 1612 | /*! TSW - Timestamp wraparound. | ||
| 1613 | */ | ||
| 1614 | #define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) | ||
| 1615 | #define CAN_IR_MRAF_MASK (0x20000U) | ||
| 1616 | #define CAN_IR_MRAF_SHIFT (17U) | ||
| 1617 | /*! MRAF - Message RAM access failure. | ||
| 1618 | */ | ||
| 1619 | #define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) | ||
| 1620 | #define CAN_IR_TOO_MASK (0x40000U) | ||
| 1621 | #define CAN_IR_TOO_SHIFT (18U) | ||
| 1622 | /*! TOO - Timeout occurred. | ||
| 1623 | */ | ||
| 1624 | #define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) | ||
| 1625 | #define CAN_IR_DRX_MASK (0x80000U) | ||
| 1626 | #define CAN_IR_DRX_SHIFT (19U) | ||
| 1627 | /*! DRX - Message stored in dedicated Rx buffer. | ||
| 1628 | */ | ||
| 1629 | #define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) | ||
| 1630 | #define CAN_IR_BEC_MASK (0x100000U) | ||
| 1631 | #define CAN_IR_BEC_SHIFT (20U) | ||
| 1632 | /*! BEC - Bit error corrected. | ||
| 1633 | */ | ||
| 1634 | #define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) | ||
| 1635 | #define CAN_IR_BEU_MASK (0x200000U) | ||
| 1636 | #define CAN_IR_BEU_SHIFT (21U) | ||
| 1637 | /*! BEU - Bit error uncorrected. | ||
| 1638 | */ | ||
| 1639 | #define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) | ||
| 1640 | #define CAN_IR_ELO_MASK (0x400000U) | ||
| 1641 | #define CAN_IR_ELO_SHIFT (22U) | ||
| 1642 | /*! ELO - Error logging overflow. | ||
| 1643 | */ | ||
| 1644 | #define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) | ||
| 1645 | #define CAN_IR_EP_MASK (0x800000U) | ||
| 1646 | #define CAN_IR_EP_SHIFT (23U) | ||
| 1647 | /*! EP - Error passive. | ||
| 1648 | */ | ||
| 1649 | #define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) | ||
| 1650 | #define CAN_IR_EW_MASK (0x1000000U) | ||
| 1651 | #define CAN_IR_EW_SHIFT (24U) | ||
| 1652 | /*! EW - Warning status. | ||
| 1653 | */ | ||
| 1654 | #define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) | ||
| 1655 | #define CAN_IR_BO_MASK (0x2000000U) | ||
| 1656 | #define CAN_IR_BO_SHIFT (25U) | ||
| 1657 | /*! BO - Bus_Off Status. | ||
| 1658 | */ | ||
| 1659 | #define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) | ||
| 1660 | #define CAN_IR_WDI_MASK (0x4000000U) | ||
| 1661 | #define CAN_IR_WDI_SHIFT (26U) | ||
| 1662 | /*! WDI - Watchdog interrupt. | ||
| 1663 | */ | ||
| 1664 | #define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) | ||
| 1665 | #define CAN_IR_PEA_MASK (0x8000000U) | ||
| 1666 | #define CAN_IR_PEA_SHIFT (27U) | ||
| 1667 | /*! PEA - Protocol error in arbitration phase. | ||
| 1668 | */ | ||
| 1669 | #define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) | ||
| 1670 | #define CAN_IR_PED_MASK (0x10000000U) | ||
| 1671 | #define CAN_IR_PED_SHIFT (28U) | ||
| 1672 | /*! PED - Protocol error in data phase. | ||
| 1673 | */ | ||
| 1674 | #define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) | ||
| 1675 | #define CAN_IR_ARA_MASK (0x20000000U) | ||
| 1676 | #define CAN_IR_ARA_SHIFT (29U) | ||
| 1677 | /*! ARA - Access to reserved address. | ||
| 1678 | */ | ||
| 1679 | #define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) | ||
| 1680 | /*! @} */ | ||
| 1681 | |||
| 1682 | /*! @name IE - Interrupt Enable */ | ||
| 1683 | /*! @{ */ | ||
| 1684 | #define CAN_IE_RF0NE_MASK (0x1U) | ||
| 1685 | #define CAN_IE_RF0NE_SHIFT (0U) | ||
| 1686 | /*! RF0NE - Rx FIFO 0 new message interrupt enable. | ||
| 1687 | */ | ||
| 1688 | #define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) | ||
| 1689 | #define CAN_IE_RF0WE_MASK (0x2U) | ||
| 1690 | #define CAN_IE_RF0WE_SHIFT (1U) | ||
| 1691 | /*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. | ||
| 1692 | */ | ||
| 1693 | #define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) | ||
| 1694 | #define CAN_IE_RF0FE_MASK (0x4U) | ||
| 1695 | #define CAN_IE_RF0FE_SHIFT (2U) | ||
| 1696 | /*! RF0FE - Rx FIFO 0 full interrupt enable. | ||
| 1697 | */ | ||
| 1698 | #define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) | ||
| 1699 | #define CAN_IE_RF0LE_MASK (0x8U) | ||
| 1700 | #define CAN_IE_RF0LE_SHIFT (3U) | ||
| 1701 | /*! RF0LE - Rx FIFO 0 message lost interrupt enable. | ||
| 1702 | */ | ||
| 1703 | #define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) | ||
| 1704 | #define CAN_IE_RF1NE_MASK (0x10U) | ||
| 1705 | #define CAN_IE_RF1NE_SHIFT (4U) | ||
| 1706 | /*! RF1NE - Rx FIFO 1 new message interrupt enable. | ||
| 1707 | */ | ||
| 1708 | #define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) | ||
| 1709 | #define CAN_IE_RF1WE_MASK (0x20U) | ||
| 1710 | #define CAN_IE_RF1WE_SHIFT (5U) | ||
| 1711 | /*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. | ||
| 1712 | */ | ||
| 1713 | #define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) | ||
| 1714 | #define CAN_IE_RF1FE_MASK (0x40U) | ||
| 1715 | #define CAN_IE_RF1FE_SHIFT (6U) | ||
| 1716 | /*! RF1FE - Rx FIFO 1 full interrupt enable. | ||
| 1717 | */ | ||
| 1718 | #define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) | ||
| 1719 | #define CAN_IE_RF1LE_MASK (0x80U) | ||
| 1720 | #define CAN_IE_RF1LE_SHIFT (7U) | ||
| 1721 | /*! RF1LE - Rx FIFO 1 message lost interrupt enable. | ||
| 1722 | */ | ||
| 1723 | #define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) | ||
| 1724 | #define CAN_IE_HPME_MASK (0x100U) | ||
| 1725 | #define CAN_IE_HPME_SHIFT (8U) | ||
| 1726 | /*! HPME - High priority message interrupt enable. | ||
| 1727 | */ | ||
| 1728 | #define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) | ||
| 1729 | #define CAN_IE_TCE_MASK (0x200U) | ||
| 1730 | #define CAN_IE_TCE_SHIFT (9U) | ||
| 1731 | /*! TCE - Transmission completed interrupt enable. | ||
| 1732 | */ | ||
| 1733 | #define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) | ||
| 1734 | #define CAN_IE_TCFE_MASK (0x400U) | ||
| 1735 | #define CAN_IE_TCFE_SHIFT (10U) | ||
| 1736 | /*! TCFE - Transmission cancellation finished interrupt enable. | ||
| 1737 | */ | ||
| 1738 | #define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) | ||
| 1739 | #define CAN_IE_TFEE_MASK (0x800U) | ||
| 1740 | #define CAN_IE_TFEE_SHIFT (11U) | ||
| 1741 | /*! TFEE - Tx FIFO empty interrupt enable. | ||
| 1742 | */ | ||
| 1743 | #define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) | ||
| 1744 | #define CAN_IE_TEFNE_MASK (0x1000U) | ||
| 1745 | #define CAN_IE_TEFNE_SHIFT (12U) | ||
| 1746 | /*! TEFNE - Tx event FIFO new entry interrupt enable. | ||
| 1747 | */ | ||
| 1748 | #define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) | ||
| 1749 | #define CAN_IE_TEFWE_MASK (0x2000U) | ||
| 1750 | #define CAN_IE_TEFWE_SHIFT (13U) | ||
| 1751 | /*! TEFWE - Tx event FIFO watermark reached interrupt enable. | ||
| 1752 | */ | ||
| 1753 | #define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) | ||
| 1754 | #define CAN_IE_TEFFE_MASK (0x4000U) | ||
| 1755 | #define CAN_IE_TEFFE_SHIFT (14U) | ||
| 1756 | /*! TEFFE - Tx event FIFO full interrupt enable. | ||
| 1757 | */ | ||
| 1758 | #define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) | ||
| 1759 | #define CAN_IE_TEFLE_MASK (0x8000U) | ||
| 1760 | #define CAN_IE_TEFLE_SHIFT (15U) | ||
| 1761 | /*! TEFLE - Tx event FIFO element lost interrupt enable. | ||
| 1762 | */ | ||
| 1763 | #define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) | ||
| 1764 | #define CAN_IE_TSWE_MASK (0x10000U) | ||
| 1765 | #define CAN_IE_TSWE_SHIFT (16U) | ||
| 1766 | /*! TSWE - Timestamp wraparound interrupt enable. | ||
| 1767 | */ | ||
| 1768 | #define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) | ||
| 1769 | #define CAN_IE_MRAFE_MASK (0x20000U) | ||
| 1770 | #define CAN_IE_MRAFE_SHIFT (17U) | ||
| 1771 | /*! MRAFE - Message RAM access failure interrupt enable. | ||
| 1772 | */ | ||
| 1773 | #define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) | ||
| 1774 | #define CAN_IE_TOOE_MASK (0x40000U) | ||
| 1775 | #define CAN_IE_TOOE_SHIFT (18U) | ||
| 1776 | /*! TOOE - Timeout occurred interrupt enable. | ||
| 1777 | */ | ||
| 1778 | #define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) | ||
| 1779 | #define CAN_IE_DRXE_MASK (0x80000U) | ||
| 1780 | #define CAN_IE_DRXE_SHIFT (19U) | ||
| 1781 | /*! DRXE - Message stored in dedicated Rx buffer interrupt enable. | ||
| 1782 | */ | ||
| 1783 | #define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) | ||
| 1784 | #define CAN_IE_BECE_MASK (0x100000U) | ||
| 1785 | #define CAN_IE_BECE_SHIFT (20U) | ||
| 1786 | /*! BECE - Bit error corrected interrupt enable. | ||
| 1787 | */ | ||
| 1788 | #define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) | ||
| 1789 | #define CAN_IE_BEUE_MASK (0x200000U) | ||
| 1790 | #define CAN_IE_BEUE_SHIFT (21U) | ||
| 1791 | /*! BEUE - Bit error uncorrected interrupt enable. | ||
| 1792 | */ | ||
| 1793 | #define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) | ||
| 1794 | #define CAN_IE_ELOE_MASK (0x400000U) | ||
| 1795 | #define CAN_IE_ELOE_SHIFT (22U) | ||
| 1796 | /*! ELOE - Error logging overflow interrupt enable. | ||
| 1797 | */ | ||
| 1798 | #define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) | ||
| 1799 | #define CAN_IE_EPE_MASK (0x800000U) | ||
| 1800 | #define CAN_IE_EPE_SHIFT (23U) | ||
| 1801 | /*! EPE - Error passive interrupt enable. | ||
| 1802 | */ | ||
| 1803 | #define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) | ||
| 1804 | #define CAN_IE_EWE_MASK (0x1000000U) | ||
| 1805 | #define CAN_IE_EWE_SHIFT (24U) | ||
| 1806 | /*! EWE - Warning status interrupt enable. | ||
| 1807 | */ | ||
| 1808 | #define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) | ||
| 1809 | #define CAN_IE_BOE_MASK (0x2000000U) | ||
| 1810 | #define CAN_IE_BOE_SHIFT (25U) | ||
| 1811 | /*! BOE - Bus_Off Status interrupt enable. | ||
| 1812 | */ | ||
| 1813 | #define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) | ||
| 1814 | #define CAN_IE_WDIE_MASK (0x4000000U) | ||
| 1815 | #define CAN_IE_WDIE_SHIFT (26U) | ||
| 1816 | /*! WDIE - Watchdog interrupt enable. | ||
| 1817 | */ | ||
| 1818 | #define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) | ||
| 1819 | #define CAN_IE_PEAE_MASK (0x8000000U) | ||
| 1820 | #define CAN_IE_PEAE_SHIFT (27U) | ||
| 1821 | /*! PEAE - Protocol error in arbitration phase interrupt enable. | ||
| 1822 | */ | ||
| 1823 | #define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) | ||
| 1824 | #define CAN_IE_PEDE_MASK (0x10000000U) | ||
| 1825 | #define CAN_IE_PEDE_SHIFT (28U) | ||
| 1826 | /*! PEDE - Protocol error in data phase interrupt enable. | ||
| 1827 | */ | ||
| 1828 | #define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) | ||
| 1829 | #define CAN_IE_ARAE_MASK (0x20000000U) | ||
| 1830 | #define CAN_IE_ARAE_SHIFT (29U) | ||
| 1831 | /*! ARAE - Access to reserved address interrupt enable. | ||
| 1832 | */ | ||
| 1833 | #define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) | ||
| 1834 | /*! @} */ | ||
| 1835 | |||
| 1836 | /*! @name ILS - Interrupt Line Select */ | ||
| 1837 | /*! @{ */ | ||
| 1838 | #define CAN_ILS_RF0NL_MASK (0x1U) | ||
| 1839 | #define CAN_ILS_RF0NL_SHIFT (0U) | ||
| 1840 | /*! RF0NL - Rx FIFO 0 new message interrupt line. | ||
| 1841 | */ | ||
| 1842 | #define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) | ||
| 1843 | #define CAN_ILS_RF0WL_MASK (0x2U) | ||
| 1844 | #define CAN_ILS_RF0WL_SHIFT (1U) | ||
| 1845 | /*! RF0WL - Rx FIFO 0 watermark reached interrupt line. | ||
| 1846 | */ | ||
| 1847 | #define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) | ||
| 1848 | #define CAN_ILS_RF0FL_MASK (0x4U) | ||
| 1849 | #define CAN_ILS_RF0FL_SHIFT (2U) | ||
| 1850 | /*! RF0FL - Rx FIFO 0 full interrupt line. | ||
| 1851 | */ | ||
| 1852 | #define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) | ||
| 1853 | #define CAN_ILS_RF0LL_MASK (0x8U) | ||
| 1854 | #define CAN_ILS_RF0LL_SHIFT (3U) | ||
| 1855 | /*! RF0LL - Rx FIFO 0 message lost interrupt line. | ||
| 1856 | */ | ||
| 1857 | #define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) | ||
| 1858 | #define CAN_ILS_RF1NL_MASK (0x10U) | ||
| 1859 | #define CAN_ILS_RF1NL_SHIFT (4U) | ||
| 1860 | /*! RF1NL - Rx FIFO 1 new message interrupt line. | ||
| 1861 | */ | ||
| 1862 | #define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) | ||
| 1863 | #define CAN_ILS_RF1WL_MASK (0x20U) | ||
| 1864 | #define CAN_ILS_RF1WL_SHIFT (5U) | ||
| 1865 | /*! RF1WL - Rx FIFO 1 watermark reached interrupt line. | ||
| 1866 | */ | ||
| 1867 | #define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) | ||
| 1868 | #define CAN_ILS_RF1FL_MASK (0x40U) | ||
| 1869 | #define CAN_ILS_RF1FL_SHIFT (6U) | ||
| 1870 | /*! RF1FL - Rx FIFO 1 full interrupt line. | ||
| 1871 | */ | ||
| 1872 | #define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) | ||
| 1873 | #define CAN_ILS_RF1LL_MASK (0x80U) | ||
| 1874 | #define CAN_ILS_RF1LL_SHIFT (7U) | ||
| 1875 | /*! RF1LL - Rx FIFO 1 message lost interrupt line. | ||
| 1876 | */ | ||
| 1877 | #define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) | ||
| 1878 | #define CAN_ILS_HPML_MASK (0x100U) | ||
| 1879 | #define CAN_ILS_HPML_SHIFT (8U) | ||
| 1880 | /*! HPML - High priority message interrupt line. | ||
| 1881 | */ | ||
| 1882 | #define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) | ||
| 1883 | #define CAN_ILS_TCL_MASK (0x200U) | ||
| 1884 | #define CAN_ILS_TCL_SHIFT (9U) | ||
| 1885 | /*! TCL - Transmission completed interrupt line. | ||
| 1886 | */ | ||
| 1887 | #define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) | ||
| 1888 | #define CAN_ILS_TCFL_MASK (0x400U) | ||
| 1889 | #define CAN_ILS_TCFL_SHIFT (10U) | ||
| 1890 | /*! TCFL - Transmission cancellation finished interrupt line. | ||
| 1891 | */ | ||
| 1892 | #define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) | ||
| 1893 | #define CAN_ILS_TFEL_MASK (0x800U) | ||
| 1894 | #define CAN_ILS_TFEL_SHIFT (11U) | ||
| 1895 | /*! TFEL - Tx FIFO empty interrupt line. | ||
| 1896 | */ | ||
| 1897 | #define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) | ||
| 1898 | #define CAN_ILS_TEFNL_MASK (0x1000U) | ||
| 1899 | #define CAN_ILS_TEFNL_SHIFT (12U) | ||
| 1900 | /*! TEFNL - Tx event FIFO new entry interrupt line. | ||
| 1901 | */ | ||
| 1902 | #define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) | ||
| 1903 | #define CAN_ILS_TEFWL_MASK (0x2000U) | ||
| 1904 | #define CAN_ILS_TEFWL_SHIFT (13U) | ||
| 1905 | /*! TEFWL - Tx event FIFO watermark reached interrupt line. | ||
| 1906 | */ | ||
| 1907 | #define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) | ||
| 1908 | #define CAN_ILS_TEFFL_MASK (0x4000U) | ||
| 1909 | #define CAN_ILS_TEFFL_SHIFT (14U) | ||
| 1910 | /*! TEFFL - Tx event FIFO full interrupt line. | ||
| 1911 | */ | ||
| 1912 | #define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) | ||
| 1913 | #define CAN_ILS_TEFLL_MASK (0x8000U) | ||
| 1914 | #define CAN_ILS_TEFLL_SHIFT (15U) | ||
| 1915 | /*! TEFLL - Tx event FIFO element lost interrupt line. | ||
| 1916 | */ | ||
| 1917 | #define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) | ||
| 1918 | #define CAN_ILS_TSWL_MASK (0x10000U) | ||
| 1919 | #define CAN_ILS_TSWL_SHIFT (16U) | ||
| 1920 | /*! TSWL - Timestamp wraparound interrupt line. | ||
| 1921 | */ | ||
| 1922 | #define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) | ||
| 1923 | #define CAN_ILS_MRAFL_MASK (0x20000U) | ||
| 1924 | #define CAN_ILS_MRAFL_SHIFT (17U) | ||
| 1925 | /*! MRAFL - Message RAM access failure interrupt line. | ||
| 1926 | */ | ||
| 1927 | #define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) | ||
| 1928 | #define CAN_ILS_TOOL_MASK (0x40000U) | ||
| 1929 | #define CAN_ILS_TOOL_SHIFT (18U) | ||
| 1930 | /*! TOOL - Timeout occurred interrupt line. | ||
| 1931 | */ | ||
| 1932 | #define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) | ||
| 1933 | #define CAN_ILS_DRXL_MASK (0x80000U) | ||
| 1934 | #define CAN_ILS_DRXL_SHIFT (19U) | ||
| 1935 | /*! DRXL - Message stored in dedicated Rx buffer interrupt line. | ||
| 1936 | */ | ||
| 1937 | #define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) | ||
| 1938 | #define CAN_ILS_BECL_MASK (0x100000U) | ||
| 1939 | #define CAN_ILS_BECL_SHIFT (20U) | ||
| 1940 | /*! BECL - Bit error corrected interrupt line. | ||
| 1941 | */ | ||
| 1942 | #define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) | ||
| 1943 | #define CAN_ILS_BEUL_MASK (0x200000U) | ||
| 1944 | #define CAN_ILS_BEUL_SHIFT (21U) | ||
| 1945 | /*! BEUL - Bit error uncorrected interrupt line. | ||
| 1946 | */ | ||
| 1947 | #define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) | ||
| 1948 | #define CAN_ILS_ELOL_MASK (0x400000U) | ||
| 1949 | #define CAN_ILS_ELOL_SHIFT (22U) | ||
| 1950 | /*! ELOL - Error logging overflow interrupt line. | ||
| 1951 | */ | ||
| 1952 | #define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) | ||
| 1953 | #define CAN_ILS_EPL_MASK (0x800000U) | ||
| 1954 | #define CAN_ILS_EPL_SHIFT (23U) | ||
| 1955 | /*! EPL - Error passive interrupt line. | ||
| 1956 | */ | ||
| 1957 | #define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) | ||
| 1958 | #define CAN_ILS_EWL_MASK (0x1000000U) | ||
| 1959 | #define CAN_ILS_EWL_SHIFT (24U) | ||
| 1960 | /*! EWL - Warning status interrupt line. | ||
| 1961 | */ | ||
| 1962 | #define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) | ||
| 1963 | #define CAN_ILS_BOL_MASK (0x2000000U) | ||
| 1964 | #define CAN_ILS_BOL_SHIFT (25U) | ||
| 1965 | /*! BOL - Bus_Off Status interrupt line. | ||
| 1966 | */ | ||
| 1967 | #define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) | ||
| 1968 | #define CAN_ILS_WDIL_MASK (0x4000000U) | ||
| 1969 | #define CAN_ILS_WDIL_SHIFT (26U) | ||
| 1970 | /*! WDIL - Watchdog interrupt line. | ||
| 1971 | */ | ||
| 1972 | #define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) | ||
| 1973 | #define CAN_ILS_PEAL_MASK (0x8000000U) | ||
| 1974 | #define CAN_ILS_PEAL_SHIFT (27U) | ||
| 1975 | /*! PEAL - Protocol error in arbitration phase interrupt line. | ||
| 1976 | */ | ||
| 1977 | #define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) | ||
| 1978 | #define CAN_ILS_PEDL_MASK (0x10000000U) | ||
| 1979 | #define CAN_ILS_PEDL_SHIFT (28U) | ||
| 1980 | /*! PEDL - Protocol error in data phase interrupt line. | ||
| 1981 | */ | ||
| 1982 | #define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) | ||
| 1983 | #define CAN_ILS_ARAL_MASK (0x20000000U) | ||
| 1984 | #define CAN_ILS_ARAL_SHIFT (29U) | ||
| 1985 | /*! ARAL - Access to reserved address interrupt line. | ||
| 1986 | */ | ||
| 1987 | #define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) | ||
| 1988 | /*! @} */ | ||
| 1989 | |||
| 1990 | /*! @name ILE - Interrupt Line Enable */ | ||
| 1991 | /*! @{ */ | ||
| 1992 | #define CAN_ILE_EINT0_MASK (0x1U) | ||
| 1993 | #define CAN_ILE_EINT0_SHIFT (0U) | ||
| 1994 | /*! EINT0 - Enable interrupt line 0. | ||
| 1995 | */ | ||
| 1996 | #define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) | ||
| 1997 | #define CAN_ILE_EINT1_MASK (0x2U) | ||
| 1998 | #define CAN_ILE_EINT1_SHIFT (1U) | ||
| 1999 | /*! EINT1 - Enable interrupt line 1. | ||
| 2000 | */ | ||
| 2001 | #define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) | ||
| 2002 | /*! @} */ | ||
| 2003 | |||
| 2004 | /*! @name GFC - Global Filter Configuration */ | ||
| 2005 | /*! @{ */ | ||
| 2006 | #define CAN_GFC_RRFE_MASK (0x1U) | ||
| 2007 | #define CAN_GFC_RRFE_SHIFT (0U) | ||
| 2008 | /*! RRFE - Reject remote frames extended. | ||
| 2009 | */ | ||
| 2010 | #define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) | ||
| 2011 | #define CAN_GFC_RRFS_MASK (0x2U) | ||
| 2012 | #define CAN_GFC_RRFS_SHIFT (1U) | ||
| 2013 | /*! RRFS - Reject remote frames standard. | ||
| 2014 | */ | ||
| 2015 | #define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) | ||
| 2016 | #define CAN_GFC_ANFE_MASK (0xCU) | ||
| 2017 | #define CAN_GFC_ANFE_SHIFT (2U) | ||
| 2018 | /*! ANFE - Accept non-matching frames extended. | ||
| 2019 | */ | ||
| 2020 | #define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) | ||
| 2021 | #define CAN_GFC_ANFS_MASK (0x30U) | ||
| 2022 | #define CAN_GFC_ANFS_SHIFT (4U) | ||
| 2023 | /*! ANFS - Accept non-matching frames standard. | ||
| 2024 | */ | ||
| 2025 | #define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) | ||
| 2026 | /*! @} */ | ||
| 2027 | |||
| 2028 | /*! @name SIDFC - Standard ID Filter Configuration */ | ||
| 2029 | /*! @{ */ | ||
| 2030 | #define CAN_SIDFC_FLSSA_MASK (0xFFFCU) | ||
| 2031 | #define CAN_SIDFC_FLSSA_SHIFT (2U) | ||
| 2032 | /*! FLSSA - Filter list standard start address. | ||
| 2033 | */ | ||
| 2034 | #define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) | ||
| 2035 | #define CAN_SIDFC_LSS_MASK (0xFF0000U) | ||
| 2036 | #define CAN_SIDFC_LSS_SHIFT (16U) | ||
| 2037 | /*! LSS - List size standard 0 = No standard message ID filter. | ||
| 2038 | */ | ||
| 2039 | #define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) | ||
| 2040 | /*! @} */ | ||
| 2041 | |||
| 2042 | /*! @name XIDFC - Extended ID Filter Configuration */ | ||
| 2043 | /*! @{ */ | ||
| 2044 | #define CAN_XIDFC_FLESA_MASK (0xFFFCU) | ||
| 2045 | #define CAN_XIDFC_FLESA_SHIFT (2U) | ||
| 2046 | /*! FLESA - Filter list extended start address. | ||
| 2047 | */ | ||
| 2048 | #define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) | ||
| 2049 | #define CAN_XIDFC_LSE_MASK (0xFF0000U) | ||
| 2050 | #define CAN_XIDFC_LSE_SHIFT (16U) | ||
| 2051 | /*! LSE - List size extended 0 = No extended message ID filter. | ||
| 2052 | */ | ||
| 2053 | #define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) | ||
| 2054 | /*! @} */ | ||
| 2055 | |||
| 2056 | /*! @name XIDAM - Extended ID AND Mask */ | ||
| 2057 | /*! @{ */ | ||
| 2058 | #define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) | ||
| 2059 | #define CAN_XIDAM_EIDM_SHIFT (0U) | ||
| 2060 | /*! EIDM - Extended ID mask. | ||
| 2061 | */ | ||
| 2062 | #define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) | ||
| 2063 | /*! @} */ | ||
| 2064 | |||
| 2065 | /*! @name HPMS - High Priority Message Status */ | ||
| 2066 | /*! @{ */ | ||
| 2067 | #define CAN_HPMS_BIDX_MASK (0x3FU) | ||
| 2068 | #define CAN_HPMS_BIDX_SHIFT (0U) | ||
| 2069 | /*! BIDX - Buffer index. | ||
| 2070 | */ | ||
| 2071 | #define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) | ||
| 2072 | #define CAN_HPMS_MSI_MASK (0xC0U) | ||
| 2073 | #define CAN_HPMS_MSI_SHIFT (6U) | ||
| 2074 | /*! MSI - Message storage indicator. | ||
| 2075 | */ | ||
| 2076 | #define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) | ||
| 2077 | #define CAN_HPMS_FIDX_MASK (0x7F00U) | ||
| 2078 | #define CAN_HPMS_FIDX_SHIFT (8U) | ||
| 2079 | /*! FIDX - Filter index. | ||
| 2080 | */ | ||
| 2081 | #define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) | ||
| 2082 | #define CAN_HPMS_FLST_MASK (0x8000U) | ||
| 2083 | #define CAN_HPMS_FLST_SHIFT (15U) | ||
| 2084 | /*! FLST - Filter list. | ||
| 2085 | */ | ||
| 2086 | #define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) | ||
| 2087 | /*! @} */ | ||
| 2088 | |||
| 2089 | /*! @name NDAT1 - New Data 1 */ | ||
| 2090 | /*! @{ */ | ||
| 2091 | #define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) | ||
| 2092 | #define CAN_NDAT1_ND_SHIFT (0U) | ||
| 2093 | /*! ND - New Data. | ||
| 2094 | */ | ||
| 2095 | #define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) | ||
| 2096 | /*! @} */ | ||
| 2097 | |||
| 2098 | /*! @name NDAT2 - New Data 2 */ | ||
| 2099 | /*! @{ */ | ||
| 2100 | #define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) | ||
| 2101 | #define CAN_NDAT2_ND_SHIFT (0U) | ||
| 2102 | /*! ND - New Data. | ||
| 2103 | */ | ||
| 2104 | #define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) | ||
| 2105 | /*! @} */ | ||
| 2106 | |||
| 2107 | /*! @name RXF0C - Rx FIFO 0 Configuration */ | ||
| 2108 | /*! @{ */ | ||
| 2109 | #define CAN_RXF0C_F0SA_MASK (0xFFFCU) | ||
| 2110 | #define CAN_RXF0C_F0SA_SHIFT (2U) | ||
| 2111 | /*! F0SA - Rx FIFO 0 start address. | ||
| 2112 | */ | ||
| 2113 | #define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) | ||
| 2114 | #define CAN_RXF0C_F0S_MASK (0x7F0000U) | ||
| 2115 | #define CAN_RXF0C_F0S_SHIFT (16U) | ||
| 2116 | /*! F0S - Rx FIFO 0 size. | ||
| 2117 | */ | ||
| 2118 | #define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) | ||
| 2119 | #define CAN_RXF0C_F0WM_MASK (0x7F000000U) | ||
| 2120 | #define CAN_RXF0C_F0WM_SHIFT (24U) | ||
| 2121 | /*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. | ||
| 2122 | */ | ||
| 2123 | #define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) | ||
| 2124 | #define CAN_RXF0C_F0OM_MASK (0x80000000U) | ||
| 2125 | #define CAN_RXF0C_F0OM_SHIFT (31U) | ||
| 2126 | /*! F0OM - FIFO 0 operation mode. | ||
| 2127 | */ | ||
| 2128 | #define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) | ||
| 2129 | /*! @} */ | ||
| 2130 | |||
| 2131 | /*! @name RXF0S - Rx FIFO 0 Status */ | ||
| 2132 | /*! @{ */ | ||
| 2133 | #define CAN_RXF0S_F0FL_MASK (0x7FU) | ||
| 2134 | #define CAN_RXF0S_F0FL_SHIFT (0U) | ||
| 2135 | /*! F0FL - Rx FIFO 0 fill level. | ||
| 2136 | */ | ||
| 2137 | #define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) | ||
| 2138 | #define CAN_RXF0S_F0GI_MASK (0x3F00U) | ||
| 2139 | #define CAN_RXF0S_F0GI_SHIFT (8U) | ||
| 2140 | /*! F0GI - Rx FIFO 0 get index. | ||
| 2141 | */ | ||
| 2142 | #define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) | ||
| 2143 | #define CAN_RXF0S_F0PI_MASK (0x3F0000U) | ||
| 2144 | #define CAN_RXF0S_F0PI_SHIFT (16U) | ||
| 2145 | /*! F0PI - Rx FIFO 0 put index. | ||
| 2146 | */ | ||
| 2147 | #define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) | ||
| 2148 | #define CAN_RXF0S_F0F_MASK (0x1000000U) | ||
| 2149 | #define CAN_RXF0S_F0F_SHIFT (24U) | ||
| 2150 | /*! F0F - Rx FIFO 0 full. | ||
| 2151 | */ | ||
| 2152 | #define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) | ||
| 2153 | #define CAN_RXF0S_RF0L_MASK (0x2000000U) | ||
| 2154 | #define CAN_RXF0S_RF0L_SHIFT (25U) | ||
| 2155 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 2156 | */ | ||
| 2157 | #define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) | ||
| 2158 | /*! @} */ | ||
| 2159 | |||
| 2160 | /*! @name RXF0A - Rx FIFO 0 Acknowledge */ | ||
| 2161 | /*! @{ */ | ||
| 2162 | #define CAN_RXF0A_F0AI_MASK (0x3FU) | ||
| 2163 | #define CAN_RXF0A_F0AI_SHIFT (0U) | ||
| 2164 | /*! F0AI - Rx FIFO 0 acknowledge index. | ||
| 2165 | */ | ||
| 2166 | #define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) | ||
| 2167 | /*! @} */ | ||
| 2168 | |||
| 2169 | /*! @name RXBC - Rx Buffer Configuration */ | ||
| 2170 | /*! @{ */ | ||
| 2171 | #define CAN_RXBC_RBSA_MASK (0xFFFCU) | ||
| 2172 | #define CAN_RXBC_RBSA_SHIFT (2U) | ||
| 2173 | /*! RBSA - Rx buffer start address. | ||
| 2174 | */ | ||
| 2175 | #define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) | ||
| 2176 | /*! @} */ | ||
| 2177 | |||
| 2178 | /*! @name RXF1C - Rx FIFO 1 Configuration */ | ||
| 2179 | /*! @{ */ | ||
| 2180 | #define CAN_RXF1C_F1SA_MASK (0xFFFCU) | ||
| 2181 | #define CAN_RXF1C_F1SA_SHIFT (2U) | ||
| 2182 | /*! F1SA - Rx FIFO 1 start address. | ||
| 2183 | */ | ||
| 2184 | #define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) | ||
| 2185 | #define CAN_RXF1C_F1S_MASK (0x7F0000U) | ||
| 2186 | #define CAN_RXF1C_F1S_SHIFT (16U) | ||
| 2187 | /*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. | ||
| 2188 | */ | ||
| 2189 | #define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) | ||
| 2190 | #define CAN_RXF1C_F1WM_MASK (0x7F000000U) | ||
| 2191 | #define CAN_RXF1C_F1WM_SHIFT (24U) | ||
| 2192 | /*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. | ||
| 2193 | */ | ||
| 2194 | #define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) | ||
| 2195 | #define CAN_RXF1C_F1OM_MASK (0x80000000U) | ||
| 2196 | #define CAN_RXF1C_F1OM_SHIFT (31U) | ||
| 2197 | /*! F1OM - FIFO 1 operation mode. | ||
| 2198 | */ | ||
| 2199 | #define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) | ||
| 2200 | /*! @} */ | ||
| 2201 | |||
| 2202 | /*! @name RXF1S - Rx FIFO 1 Status */ | ||
| 2203 | /*! @{ */ | ||
| 2204 | #define CAN_RXF1S_F1FL_MASK (0x7FU) | ||
| 2205 | #define CAN_RXF1S_F1FL_SHIFT (0U) | ||
| 2206 | /*! F1FL - Rx FIFO 1 fill level. | ||
| 2207 | */ | ||
| 2208 | #define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) | ||
| 2209 | #define CAN_RXF1S_F1GI_MASK (0x3F00U) | ||
| 2210 | #define CAN_RXF1S_F1GI_SHIFT (8U) | ||
| 2211 | /*! F1GI - Rx FIFO 1 get index. | ||
| 2212 | */ | ||
| 2213 | #define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) | ||
| 2214 | #define CAN_RXF1S_F1PI_MASK (0x3F0000U) | ||
| 2215 | #define CAN_RXF1S_F1PI_SHIFT (16U) | ||
| 2216 | /*! F1PI - Rx FIFO 1 put index. | ||
| 2217 | */ | ||
| 2218 | #define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) | ||
| 2219 | #define CAN_RXF1S_F1F_MASK (0x1000000U) | ||
| 2220 | #define CAN_RXF1S_F1F_SHIFT (24U) | ||
| 2221 | /*! F1F - Rx FIFO 1 full. | ||
| 2222 | */ | ||
| 2223 | #define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) | ||
| 2224 | #define CAN_RXF1S_RF1L_MASK (0x2000000U) | ||
| 2225 | #define CAN_RXF1S_RF1L_SHIFT (25U) | ||
| 2226 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 2227 | */ | ||
| 2228 | #define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) | ||
| 2229 | /*! @} */ | ||
| 2230 | |||
| 2231 | /*! @name RXF1A - Rx FIFO 1 Acknowledge */ | ||
| 2232 | /*! @{ */ | ||
| 2233 | #define CAN_RXF1A_F1AI_MASK (0x3FU) | ||
| 2234 | #define CAN_RXF1A_F1AI_SHIFT (0U) | ||
| 2235 | /*! F1AI - Rx FIFO 1 acknowledge index. | ||
| 2236 | */ | ||
| 2237 | #define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) | ||
| 2238 | /*! @} */ | ||
| 2239 | |||
| 2240 | /*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ | ||
| 2241 | /*! @{ */ | ||
| 2242 | #define CAN_RXESC_F0DS_MASK (0x7U) | ||
| 2243 | #define CAN_RXESC_F0DS_SHIFT (0U) | ||
| 2244 | /*! F0DS - Rx FIFO 0 data field size. | ||
| 2245 | */ | ||
| 2246 | #define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) | ||
| 2247 | #define CAN_RXESC_F1DS_MASK (0x70U) | ||
| 2248 | #define CAN_RXESC_F1DS_SHIFT (4U) | ||
| 2249 | /*! F1DS - Rx FIFO 1 data field size. | ||
| 2250 | */ | ||
| 2251 | #define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) | ||
| 2252 | #define CAN_RXESC_RBDS_MASK (0x700U) | ||
| 2253 | #define CAN_RXESC_RBDS_SHIFT (8U) | ||
| 2254 | /*! RBDS - . | ||
| 2255 | */ | ||
| 2256 | #define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) | ||
| 2257 | /*! @} */ | ||
| 2258 | |||
| 2259 | /*! @name TXBC - Tx Buffer Configuration */ | ||
| 2260 | /*! @{ */ | ||
| 2261 | #define CAN_TXBC_TBSA_MASK (0xFFFCU) | ||
| 2262 | #define CAN_TXBC_TBSA_SHIFT (2U) | ||
| 2263 | /*! TBSA - Tx buffers start address. | ||
| 2264 | */ | ||
| 2265 | #define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) | ||
| 2266 | #define CAN_TXBC_NDTB_MASK (0x3F0000U) | ||
| 2267 | #define CAN_TXBC_NDTB_SHIFT (16U) | ||
| 2268 | /*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. | ||
| 2269 | */ | ||
| 2270 | #define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) | ||
| 2271 | #define CAN_TXBC_TFQS_MASK (0x3F000000U) | ||
| 2272 | #define CAN_TXBC_TFQS_SHIFT (24U) | ||
| 2273 | /*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. | ||
| 2274 | */ | ||
| 2275 | #define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) | ||
| 2276 | #define CAN_TXBC_TFQM_MASK (0x40000000U) | ||
| 2277 | #define CAN_TXBC_TFQM_SHIFT (30U) | ||
| 2278 | /*! TFQM - Tx FIFO/queue mode. | ||
| 2279 | */ | ||
| 2280 | #define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) | ||
| 2281 | /*! @} */ | ||
| 2282 | |||
| 2283 | /*! @name TXFQS - Tx FIFO/Queue Status */ | ||
| 2284 | /*! @{ */ | ||
| 2285 | #define CAN_TXFQS_TFGI_MASK (0x1F00U) | ||
| 2286 | #define CAN_TXFQS_TFGI_SHIFT (8U) | ||
| 2287 | /*! TFGI - Tx FIFO get index. | ||
| 2288 | */ | ||
| 2289 | #define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) | ||
| 2290 | #define CAN_TXFQS_TFQPI_MASK (0x1F0000U) | ||
| 2291 | #define CAN_TXFQS_TFQPI_SHIFT (16U) | ||
| 2292 | /*! TFQPI - Tx FIFO/queue put index. | ||
| 2293 | */ | ||
| 2294 | #define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) | ||
| 2295 | #define CAN_TXFQS_TFQF_MASK (0x200000U) | ||
| 2296 | #define CAN_TXFQS_TFQF_SHIFT (21U) | ||
| 2297 | /*! TFQF - Tx FIFO/queue full. | ||
| 2298 | */ | ||
| 2299 | #define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) | ||
| 2300 | /*! @} */ | ||
| 2301 | |||
| 2302 | /*! @name TXESC - Tx Buffer Element Size Configuration */ | ||
| 2303 | /*! @{ */ | ||
| 2304 | #define CAN_TXESC_TBDS_MASK (0x7U) | ||
| 2305 | #define CAN_TXESC_TBDS_SHIFT (0U) | ||
| 2306 | /*! TBDS - Tx buffer data field size. | ||
| 2307 | */ | ||
| 2308 | #define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) | ||
| 2309 | /*! @} */ | ||
| 2310 | |||
| 2311 | /*! @name TXBRP - Tx Buffer Request Pending */ | ||
| 2312 | /*! @{ */ | ||
| 2313 | #define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) | ||
| 2314 | #define CAN_TXBRP_TRP_SHIFT (0U) | ||
| 2315 | /*! TRP - Transmission request pending. | ||
| 2316 | */ | ||
| 2317 | #define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) | ||
| 2318 | /*! @} */ | ||
| 2319 | |||
| 2320 | /*! @name TXBAR - Tx Buffer Add Request */ | ||
| 2321 | /*! @{ */ | ||
| 2322 | #define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) | ||
| 2323 | #define CAN_TXBAR_AR_SHIFT (0U) | ||
| 2324 | /*! AR - Add request. | ||
| 2325 | */ | ||
| 2326 | #define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) | ||
| 2327 | /*! @} */ | ||
| 2328 | |||
| 2329 | /*! @name TXBCR - Tx Buffer Cancellation Request */ | ||
| 2330 | /*! @{ */ | ||
| 2331 | #define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) | ||
| 2332 | #define CAN_TXBCR_CR_SHIFT (0U) | ||
| 2333 | /*! CR - Cancellation request. | ||
| 2334 | */ | ||
| 2335 | #define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) | ||
| 2336 | /*! @} */ | ||
| 2337 | |||
| 2338 | /*! @name TXBTO - Tx Buffer Transmission Occurred */ | ||
| 2339 | /*! @{ */ | ||
| 2340 | #define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) | ||
| 2341 | #define CAN_TXBTO_TO_SHIFT (0U) | ||
| 2342 | /*! TO - Transmission occurred. | ||
| 2343 | */ | ||
| 2344 | #define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) | ||
| 2345 | /*! @} */ | ||
| 2346 | |||
| 2347 | /*! @name TXBCF - Tx Buffer Cancellation Finished */ | ||
| 2348 | /*! @{ */ | ||
| 2349 | #define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) | ||
| 2350 | #define CAN_TXBCF_TO_SHIFT (0U) | ||
| 2351 | /*! TO - Cancellation finished. | ||
| 2352 | */ | ||
| 2353 | #define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) | ||
| 2354 | /*! @} */ | ||
| 2355 | |||
| 2356 | /*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ | ||
| 2357 | /*! @{ */ | ||
| 2358 | #define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) | ||
| 2359 | #define CAN_TXBTIE_TIE_SHIFT (0U) | ||
| 2360 | /*! TIE - Transmission interrupt enable. | ||
| 2361 | */ | ||
| 2362 | #define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) | ||
| 2363 | /*! @} */ | ||
| 2364 | |||
| 2365 | /*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ | ||
| 2366 | /*! @{ */ | ||
| 2367 | #define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) | ||
| 2368 | #define CAN_TXBCIE_CFIE_SHIFT (0U) | ||
| 2369 | /*! CFIE - Cancellation finished interrupt enable. | ||
| 2370 | */ | ||
| 2371 | #define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) | ||
| 2372 | /*! @} */ | ||
| 2373 | |||
| 2374 | /*! @name TXEFC - Tx Event FIFO Configuration */ | ||
| 2375 | /*! @{ */ | ||
| 2376 | #define CAN_TXEFC_EFSA_MASK (0xFFFCU) | ||
| 2377 | #define CAN_TXEFC_EFSA_SHIFT (2U) | ||
| 2378 | /*! EFSA - Event FIFO start address. | ||
| 2379 | */ | ||
| 2380 | #define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) | ||
| 2381 | #define CAN_TXEFC_EFS_MASK (0x3F0000U) | ||
| 2382 | #define CAN_TXEFC_EFS_SHIFT (16U) | ||
| 2383 | /*! EFS - Event FIFO size 0 = Tx event FIFO disabled. | ||
| 2384 | */ | ||
| 2385 | #define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) | ||
| 2386 | #define CAN_TXEFC_EFWM_MASK (0x3F000000U) | ||
| 2387 | #define CAN_TXEFC_EFWM_SHIFT (24U) | ||
| 2388 | /*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. | ||
| 2389 | */ | ||
| 2390 | #define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) | ||
| 2391 | /*! @} */ | ||
| 2392 | |||
| 2393 | /*! @name TXEFS - Tx Event FIFO Status */ | ||
| 2394 | /*! @{ */ | ||
| 2395 | #define CAN_TXEFS_EFFL_MASK (0x3FU) | ||
| 2396 | #define CAN_TXEFS_EFFL_SHIFT (0U) | ||
| 2397 | /*! EFFL - Event FIFO fill level. | ||
| 2398 | */ | ||
| 2399 | #define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) | ||
| 2400 | #define CAN_TXEFS_EFGI_MASK (0x1F00U) | ||
| 2401 | #define CAN_TXEFS_EFGI_SHIFT (8U) | ||
| 2402 | /*! EFGI - Event FIFO get index. | ||
| 2403 | */ | ||
| 2404 | #define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) | ||
| 2405 | #define CAN_TXEFS_EFPI_MASK (0x3F0000U) | ||
| 2406 | #define CAN_TXEFS_EFPI_SHIFT (16U) | ||
| 2407 | /*! EFPI - Event FIFO put index. | ||
| 2408 | */ | ||
| 2409 | #define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) | ||
| 2410 | #define CAN_TXEFS_EFF_MASK (0x1000000U) | ||
| 2411 | #define CAN_TXEFS_EFF_SHIFT (24U) | ||
| 2412 | /*! EFF - Event FIFO full. | ||
| 2413 | */ | ||
| 2414 | #define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) | ||
| 2415 | #define CAN_TXEFS_TEFL_MASK (0x2000000U) | ||
| 2416 | #define CAN_TXEFS_TEFL_SHIFT (25U) | ||
| 2417 | /*! TEFL - Tx event FIFO element lost. | ||
| 2418 | */ | ||
| 2419 | #define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) | ||
| 2420 | /*! @} */ | ||
| 2421 | |||
| 2422 | /*! @name TXEFA - Tx Event FIFO Acknowledge */ | ||
| 2423 | /*! @{ */ | ||
| 2424 | #define CAN_TXEFA_EFAI_MASK (0x1FU) | ||
| 2425 | #define CAN_TXEFA_EFAI_SHIFT (0U) | ||
| 2426 | /*! EFAI - Event FIFO acknowledge index. | ||
| 2427 | */ | ||
| 2428 | #define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) | ||
| 2429 | /*! @} */ | ||
| 2430 | |||
| 2431 | /*! @name MRBA - CAN Message RAM Base Address */ | ||
| 2432 | /*! @{ */ | ||
| 2433 | #define CAN_MRBA_BA_MASK (0xFFFF0000U) | ||
| 2434 | #define CAN_MRBA_BA_SHIFT (16U) | ||
| 2435 | /*! BA - Base address for the message RAM in the chip memory map. | ||
| 2436 | */ | ||
| 2437 | #define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) | ||
| 2438 | /*! @} */ | ||
| 2439 | |||
| 2440 | /*! @name ETSCC - External Timestamp Counter Configuration */ | ||
| 2441 | /*! @{ */ | ||
| 2442 | #define CAN_ETSCC_ETCP_MASK (0x7FFU) | ||
| 2443 | #define CAN_ETSCC_ETCP_SHIFT (0U) | ||
| 2444 | /*! ETCP - External timestamp prescaler value. | ||
| 2445 | */ | ||
| 2446 | #define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) | ||
| 2447 | #define CAN_ETSCC_ETCE_MASK (0x80000000U) | ||
| 2448 | #define CAN_ETSCC_ETCE_SHIFT (31U) | ||
| 2449 | /*! ETCE - External timestamp counter enable. | ||
| 2450 | */ | ||
| 2451 | #define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) | ||
| 2452 | /*! @} */ | ||
| 2453 | |||
| 2454 | /*! @name ETSCV - External Timestamp Counter Value */ | ||
| 2455 | /*! @{ */ | ||
| 2456 | #define CAN_ETSCV_ETSC_MASK (0xFFFFU) | ||
| 2457 | #define CAN_ETSCV_ETSC_SHIFT (0U) | ||
| 2458 | /*! ETSC - External timestamp counter. | ||
| 2459 | */ | ||
| 2460 | #define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) | ||
| 2461 | /*! @} */ | ||
| 2462 | |||
| 2463 | |||
| 2464 | /*! | ||
| 2465 | * @} | ||
| 2466 | */ /* end of group CAN_Register_Masks */ | ||
| 2467 | |||
| 2468 | |||
| 2469 | /* CAN - Peripheral instance base addresses */ | ||
| 2470 | /** Peripheral CAN0 base address */ | ||
| 2471 | #define CAN0_BASE (0x4009D000u) | ||
| 2472 | /** Peripheral CAN0 base pointer */ | ||
| 2473 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 2474 | /** Peripheral CAN1 base address */ | ||
| 2475 | #define CAN1_BASE (0x4009E000u) | ||
| 2476 | /** Peripheral CAN1 base pointer */ | ||
| 2477 | #define CAN1 ((CAN_Type *)CAN1_BASE) | ||
| 2478 | /** Array initializer of CAN peripheral base addresses */ | ||
| 2479 | #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } | ||
| 2480 | /** Array initializer of CAN peripheral base pointers */ | ||
| 2481 | #define CAN_BASE_PTRS { CAN0, CAN1 } | ||
| 2482 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 2483 | #define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } } | ||
| 2484 | |||
| 2485 | /*! | ||
| 2486 | * @} | ||
| 2487 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 2488 | |||
| 2489 | |||
| 2490 | /* ---------------------------------------------------------------------------- | ||
| 2491 | -- CRC Peripheral Access Layer | ||
| 2492 | ---------------------------------------------------------------------------- */ | ||
| 2493 | |||
| 2494 | /*! | ||
| 2495 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 2496 | * @{ | ||
| 2497 | */ | ||
| 2498 | |||
| 2499 | /** CRC - Register Layout Typedef */ | ||
| 2500 | typedef struct { | ||
| 2501 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ | ||
| 2502 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ | ||
| 2503 | union { /* offset: 0x8 */ | ||
| 2504 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ | ||
| 2505 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ | ||
| 2506 | }; | ||
| 2507 | } CRC_Type; | ||
| 2508 | |||
| 2509 | /* ---------------------------------------------------------------------------- | ||
| 2510 | -- CRC Register Masks | ||
| 2511 | ---------------------------------------------------------------------------- */ | ||
| 2512 | |||
| 2513 | /*! | ||
| 2514 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 2515 | * @{ | ||
| 2516 | */ | ||
| 2517 | |||
| 2518 | /*! @name MODE - CRC mode register */ | ||
| 2519 | /*! @{ */ | ||
| 2520 | #define CRC_MODE_CRC_POLY_MASK (0x3U) | ||
| 2521 | #define CRC_MODE_CRC_POLY_SHIFT (0U) | ||
| 2522 | /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial | ||
| 2523 | */ | ||
| 2524 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) | ||
| 2525 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) | ||
| 2526 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) | ||
| 2527 | /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) | ||
| 2528 | */ | ||
| 2529 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) | ||
| 2530 | #define CRC_MODE_CMPL_WR_MASK (0x8U) | ||
| 2531 | #define CRC_MODE_CMPL_WR_SHIFT (3U) | ||
| 2532 | /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA | ||
| 2533 | */ | ||
| 2534 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) | ||
| 2535 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) | ||
| 2536 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) | ||
| 2537 | /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM | ||
| 2538 | */ | ||
| 2539 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) | ||
| 2540 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) | ||
| 2541 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) | ||
| 2542 | /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM | ||
| 2543 | */ | ||
| 2544 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) | ||
| 2545 | /*! @} */ | ||
| 2546 | |||
| 2547 | /*! @name SEED - CRC seed register */ | ||
| 2548 | /*! @{ */ | ||
| 2549 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) | ||
| 2550 | #define CRC_SEED_CRC_SEED_SHIFT (0U) | ||
| 2551 | /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with | ||
| 2552 | * selected bit order and 1's complement pre-processes. A write access to this register will | ||
| 2553 | * overrule the CRC calculation in progresses. | ||
| 2554 | */ | ||
| 2555 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) | ||
| 2556 | /*! @} */ | ||
| 2557 | |||
| 2558 | /*! @name SUM - CRC checksum register */ | ||
| 2559 | /*! @{ */ | ||
| 2560 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) | ||
| 2561 | #define CRC_SUM_CRC_SUM_SHIFT (0U) | ||
| 2562 | /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. | ||
| 2563 | */ | ||
| 2564 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) | ||
| 2565 | /*! @} */ | ||
| 2566 | |||
| 2567 | /*! @name WR_DATA - CRC data register */ | ||
| 2568 | /*! @{ */ | ||
| 2569 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) | ||
| 2570 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) | ||
| 2571 | /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with | ||
| 2572 | * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and | ||
| 2573 | * accept back-to-back transactions. | ||
| 2574 | */ | ||
| 2575 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) | ||
| 2576 | /*! @} */ | ||
| 2577 | |||
| 2578 | |||
| 2579 | /*! | ||
| 2580 | * @} | ||
| 2581 | */ /* end of group CRC_Register_Masks */ | ||
| 2582 | |||
| 2583 | |||
| 2584 | /* CRC - Peripheral instance base addresses */ | ||
| 2585 | /** Peripheral CRC_ENGINE base address */ | ||
| 2586 | #define CRC_ENGINE_BASE (0x40095000u) | ||
| 2587 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 2588 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 2589 | /** Array initializer of CRC peripheral base addresses */ | ||
| 2590 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 2591 | /** Array initializer of CRC peripheral base pointers */ | ||
| 2592 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 2593 | |||
| 2594 | /*! | ||
| 2595 | * @} | ||
| 2596 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 2597 | |||
| 2598 | |||
| 2599 | /* ---------------------------------------------------------------------------- | ||
| 2600 | -- CTIMER Peripheral Access Layer | ||
| 2601 | ---------------------------------------------------------------------------- */ | ||
| 2602 | |||
| 2603 | /*! | ||
| 2604 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer | ||
| 2605 | * @{ | ||
| 2606 | */ | ||
| 2607 | |||
| 2608 | /** CTIMER - Register Layout Typedef */ | ||
| 2609 | typedef struct { | ||
| 2610 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ | ||
| 2611 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ | ||
| 2612 | __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ | ||
| 2613 | __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ | ||
| 2614 | __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ | ||
| 2615 | __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ | ||
| 2616 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ | ||
| 2617 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ | ||
| 2618 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ | ||
| 2619 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ | ||
| 2620 | uint8_t RESERVED_0[48]; | ||
| 2621 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ | ||
| 2622 | __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ | ||
| 2623 | __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ | ||
| 2624 | } CTIMER_Type; | ||
| 2625 | |||
| 2626 | /* ---------------------------------------------------------------------------- | ||
| 2627 | -- CTIMER Register Masks | ||
| 2628 | ---------------------------------------------------------------------------- */ | ||
| 2629 | |||
| 2630 | /*! | ||
| 2631 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks | ||
| 2632 | * @{ | ||
| 2633 | */ | ||
| 2634 | |||
| 2635 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ | ||
| 2636 | /*! @{ */ | ||
| 2637 | #define CTIMER_IR_MR0INT_MASK (0x1U) | ||
| 2638 | #define CTIMER_IR_MR0INT_SHIFT (0U) | ||
| 2639 | /*! MR0INT - Interrupt flag for match channel 0. | ||
| 2640 | */ | ||
| 2641 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) | ||
| 2642 | #define CTIMER_IR_MR1INT_MASK (0x2U) | ||
| 2643 | #define CTIMER_IR_MR1INT_SHIFT (1U) | ||
| 2644 | /*! MR1INT - Interrupt flag for match channel 1. | ||
| 2645 | */ | ||
| 2646 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) | ||
| 2647 | #define CTIMER_IR_MR2INT_MASK (0x4U) | ||
| 2648 | #define CTIMER_IR_MR2INT_SHIFT (2U) | ||
| 2649 | /*! MR2INT - Interrupt flag for match channel 2. | ||
| 2650 | */ | ||
| 2651 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) | ||
| 2652 | #define CTIMER_IR_MR3INT_MASK (0x8U) | ||
| 2653 | #define CTIMER_IR_MR3INT_SHIFT (3U) | ||
| 2654 | /*! MR3INT - Interrupt flag for match channel 3. | ||
| 2655 | */ | ||
| 2656 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) | ||
| 2657 | #define CTIMER_IR_CR0INT_MASK (0x10U) | ||
| 2658 | #define CTIMER_IR_CR0INT_SHIFT (4U) | ||
| 2659 | /*! CR0INT - Interrupt flag for capture channel 0 event. | ||
| 2660 | */ | ||
| 2661 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) | ||
| 2662 | #define CTIMER_IR_CR1INT_MASK (0x20U) | ||
| 2663 | #define CTIMER_IR_CR1INT_SHIFT (5U) | ||
| 2664 | /*! CR1INT - Interrupt flag for capture channel 1 event. | ||
| 2665 | */ | ||
| 2666 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) | ||
| 2667 | #define CTIMER_IR_CR2INT_MASK (0x40U) | ||
| 2668 | #define CTIMER_IR_CR2INT_SHIFT (6U) | ||
| 2669 | /*! CR2INT - Interrupt flag for capture channel 2 event. | ||
| 2670 | */ | ||
| 2671 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) | ||
| 2672 | #define CTIMER_IR_CR3INT_MASK (0x80U) | ||
| 2673 | #define CTIMER_IR_CR3INT_SHIFT (7U) | ||
| 2674 | /*! CR3INT - Interrupt flag for capture channel 3 event. | ||
| 2675 | */ | ||
| 2676 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) | ||
| 2677 | /*! @} */ | ||
| 2678 | |||
| 2679 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ | ||
| 2680 | /*! @{ */ | ||
| 2681 | #define CTIMER_TCR_CEN_MASK (0x1U) | ||
| 2682 | #define CTIMER_TCR_CEN_SHIFT (0U) | ||
| 2683 | /*! CEN - Counter enable. | ||
| 2684 | * 0b0..Disabled.The counters are disabled. | ||
| 2685 | * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. | ||
| 2686 | */ | ||
| 2687 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) | ||
| 2688 | #define CTIMER_TCR_CRST_MASK (0x2U) | ||
| 2689 | #define CTIMER_TCR_CRST_SHIFT (1U) | ||
| 2690 | /*! CRST - Counter reset. | ||
| 2691 | * 0b0..Disabled. Do nothing. | ||
| 2692 | * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of | ||
| 2693 | * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. | ||
| 2694 | */ | ||
| 2695 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) | ||
| 2696 | /*! @} */ | ||
| 2697 | |||
| 2698 | /*! @name TC - Timer Counter */ | ||
| 2699 | /*! @{ */ | ||
| 2700 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) | ||
| 2701 | #define CTIMER_TC_TCVAL_SHIFT (0U) | ||
| 2702 | /*! TCVAL - Timer counter value. | ||
| 2703 | */ | ||
| 2704 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) | ||
| 2705 | /*! @} */ | ||
| 2706 | |||
| 2707 | /*! @name PR - Prescale Register */ | ||
| 2708 | /*! @{ */ | ||
| 2709 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) | ||
| 2710 | #define CTIMER_PR_PRVAL_SHIFT (0U) | ||
| 2711 | /*! PRVAL - Prescale counter value. | ||
| 2712 | */ | ||
| 2713 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) | ||
| 2714 | /*! @} */ | ||
| 2715 | |||
| 2716 | /*! @name PC - Prescale Counter */ | ||
| 2717 | /*! @{ */ | ||
| 2718 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) | ||
| 2719 | #define CTIMER_PC_PCVAL_SHIFT (0U) | ||
| 2720 | /*! PCVAL - Prescale counter value. | ||
| 2721 | */ | ||
| 2722 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) | ||
| 2723 | /*! @} */ | ||
| 2724 | |||
| 2725 | /*! @name MCR - Match Control Register */ | ||
| 2726 | /*! @{ */ | ||
| 2727 | #define CTIMER_MCR_MR0I_MASK (0x1U) | ||
| 2728 | #define CTIMER_MCR_MR0I_SHIFT (0U) | ||
| 2729 | /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. | ||
| 2730 | */ | ||
| 2731 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) | ||
| 2732 | #define CTIMER_MCR_MR0R_MASK (0x2U) | ||
| 2733 | #define CTIMER_MCR_MR0R_SHIFT (1U) | ||
| 2734 | /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. | ||
| 2735 | */ | ||
| 2736 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) | ||
| 2737 | #define CTIMER_MCR_MR0S_MASK (0x4U) | ||
| 2738 | #define CTIMER_MCR_MR0S_SHIFT (2U) | ||
| 2739 | /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. | ||
| 2740 | */ | ||
| 2741 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) | ||
| 2742 | #define CTIMER_MCR_MR1I_MASK (0x8U) | ||
| 2743 | #define CTIMER_MCR_MR1I_SHIFT (3U) | ||
| 2744 | /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. | ||
| 2745 | */ | ||
| 2746 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) | ||
| 2747 | #define CTIMER_MCR_MR1R_MASK (0x10U) | ||
| 2748 | #define CTIMER_MCR_MR1R_SHIFT (4U) | ||
| 2749 | /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. | ||
| 2750 | */ | ||
| 2751 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) | ||
| 2752 | #define CTIMER_MCR_MR1S_MASK (0x20U) | ||
| 2753 | #define CTIMER_MCR_MR1S_SHIFT (5U) | ||
| 2754 | /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. | ||
| 2755 | */ | ||
| 2756 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) | ||
| 2757 | #define CTIMER_MCR_MR2I_MASK (0x40U) | ||
| 2758 | #define CTIMER_MCR_MR2I_SHIFT (6U) | ||
| 2759 | /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. | ||
| 2760 | */ | ||
| 2761 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) | ||
| 2762 | #define CTIMER_MCR_MR2R_MASK (0x80U) | ||
| 2763 | #define CTIMER_MCR_MR2R_SHIFT (7U) | ||
| 2764 | /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. | ||
| 2765 | */ | ||
| 2766 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) | ||
| 2767 | #define CTIMER_MCR_MR2S_MASK (0x100U) | ||
| 2768 | #define CTIMER_MCR_MR2S_SHIFT (8U) | ||
| 2769 | /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. | ||
| 2770 | */ | ||
| 2771 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) | ||
| 2772 | #define CTIMER_MCR_MR3I_MASK (0x200U) | ||
| 2773 | #define CTIMER_MCR_MR3I_SHIFT (9U) | ||
| 2774 | /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. | ||
| 2775 | */ | ||
| 2776 | #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) | ||
| 2777 | #define CTIMER_MCR_MR3R_MASK (0x400U) | ||
| 2778 | #define CTIMER_MCR_MR3R_SHIFT (10U) | ||
| 2779 | /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. | ||
| 2780 | */ | ||
| 2781 | #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) | ||
| 2782 | #define CTIMER_MCR_MR3S_MASK (0x800U) | ||
| 2783 | #define CTIMER_MCR_MR3S_SHIFT (11U) | ||
| 2784 | /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. | ||
| 2785 | */ | ||
| 2786 | #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) | ||
| 2787 | #define CTIMER_MCR_MR0RL_MASK (0x1000000U) | ||
| 2788 | #define CTIMER_MCR_MR0RL_SHIFT (24U) | ||
| 2789 | /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero | ||
| 2790 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 2791 | */ | ||
| 2792 | #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) | ||
| 2793 | #define CTIMER_MCR_MR1RL_MASK (0x2000000U) | ||
| 2794 | #define CTIMER_MCR_MR1RL_SHIFT (25U) | ||
| 2795 | /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero | ||
| 2796 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 2797 | */ | ||
| 2798 | #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) | ||
| 2799 | #define CTIMER_MCR_MR2RL_MASK (0x4000000U) | ||
| 2800 | #define CTIMER_MCR_MR2RL_SHIFT (26U) | ||
| 2801 | /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero | ||
| 2802 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 2803 | */ | ||
| 2804 | #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) | ||
| 2805 | #define CTIMER_MCR_MR3RL_MASK (0x8000000U) | ||
| 2806 | #define CTIMER_MCR_MR3RL_SHIFT (27U) | ||
| 2807 | /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero | ||
| 2808 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 2809 | */ | ||
| 2810 | #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) | ||
| 2811 | /*! @} */ | ||
| 2812 | |||
| 2813 | /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ | ||
| 2814 | /*! @{ */ | ||
| 2815 | #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) | ||
| 2816 | #define CTIMER_MR_MATCH_SHIFT (0U) | ||
| 2817 | /*! MATCH - Timer counter match value. | ||
| 2818 | */ | ||
| 2819 | #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) | ||
| 2820 | /*! @} */ | ||
| 2821 | |||
| 2822 | /* The count of CTIMER_MR */ | ||
| 2823 | #define CTIMER_MR_COUNT (4U) | ||
| 2824 | |||
| 2825 | /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ | ||
| 2826 | /*! @{ */ | ||
| 2827 | #define CTIMER_CCR_CAP0RE_MASK (0x1U) | ||
| 2828 | #define CTIMER_CCR_CAP0RE_SHIFT (0U) | ||
| 2829 | /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with | ||
| 2830 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2831 | */ | ||
| 2832 | #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) | ||
| 2833 | #define CTIMER_CCR_CAP0FE_MASK (0x2U) | ||
| 2834 | #define CTIMER_CCR_CAP0FE_SHIFT (1U) | ||
| 2835 | /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with | ||
| 2836 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2837 | */ | ||
| 2838 | #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) | ||
| 2839 | #define CTIMER_CCR_CAP0I_MASK (0x4U) | ||
| 2840 | #define CTIMER_CCR_CAP0I_SHIFT (2U) | ||
| 2841 | /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. | ||
| 2842 | */ | ||
| 2843 | #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) | ||
| 2844 | #define CTIMER_CCR_CAP1RE_MASK (0x8U) | ||
| 2845 | #define CTIMER_CCR_CAP1RE_SHIFT (3U) | ||
| 2846 | /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with | ||
| 2847 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2848 | */ | ||
| 2849 | #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) | ||
| 2850 | #define CTIMER_CCR_CAP1FE_MASK (0x10U) | ||
| 2851 | #define CTIMER_CCR_CAP1FE_SHIFT (4U) | ||
| 2852 | /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with | ||
| 2853 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2854 | */ | ||
| 2855 | #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) | ||
| 2856 | #define CTIMER_CCR_CAP1I_MASK (0x20U) | ||
| 2857 | #define CTIMER_CCR_CAP1I_SHIFT (5U) | ||
| 2858 | /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. | ||
| 2859 | */ | ||
| 2860 | #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) | ||
| 2861 | #define CTIMER_CCR_CAP2RE_MASK (0x40U) | ||
| 2862 | #define CTIMER_CCR_CAP2RE_SHIFT (6U) | ||
| 2863 | /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with | ||
| 2864 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2865 | */ | ||
| 2866 | #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) | ||
| 2867 | #define CTIMER_CCR_CAP2FE_MASK (0x80U) | ||
| 2868 | #define CTIMER_CCR_CAP2FE_SHIFT (7U) | ||
| 2869 | /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with | ||
| 2870 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2871 | */ | ||
| 2872 | #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) | ||
| 2873 | #define CTIMER_CCR_CAP2I_MASK (0x100U) | ||
| 2874 | #define CTIMER_CCR_CAP2I_SHIFT (8U) | ||
| 2875 | /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. | ||
| 2876 | */ | ||
| 2877 | #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) | ||
| 2878 | #define CTIMER_CCR_CAP3RE_MASK (0x200U) | ||
| 2879 | #define CTIMER_CCR_CAP3RE_SHIFT (9U) | ||
| 2880 | /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with | ||
| 2881 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2882 | */ | ||
| 2883 | #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) | ||
| 2884 | #define CTIMER_CCR_CAP3FE_MASK (0x400U) | ||
| 2885 | #define CTIMER_CCR_CAP3FE_SHIFT (10U) | ||
| 2886 | /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with | ||
| 2887 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 2888 | */ | ||
| 2889 | #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) | ||
| 2890 | #define CTIMER_CCR_CAP3I_MASK (0x800U) | ||
| 2891 | #define CTIMER_CCR_CAP3I_SHIFT (11U) | ||
| 2892 | /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. | ||
| 2893 | */ | ||
| 2894 | #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) | ||
| 2895 | /*! @} */ | ||
| 2896 | |||
| 2897 | /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ | ||
| 2898 | /*! @{ */ | ||
| 2899 | #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) | ||
| 2900 | #define CTIMER_CR_CAP_SHIFT (0U) | ||
| 2901 | /*! CAP - Timer counter capture value. | ||
| 2902 | */ | ||
| 2903 | #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) | ||
| 2904 | /*! @} */ | ||
| 2905 | |||
| 2906 | /* The count of CTIMER_CR */ | ||
| 2907 | #define CTIMER_CR_COUNT (4U) | ||
| 2908 | |||
| 2909 | /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ | ||
| 2910 | /*! @{ */ | ||
| 2911 | #define CTIMER_EMR_EM0_MASK (0x1U) | ||
| 2912 | #define CTIMER_EMR_EM0_SHIFT (0U) | ||
| 2913 | /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output | ||
| 2914 | * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, | ||
| 2915 | * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if | ||
| 2916 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 2917 | */ | ||
| 2918 | #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) | ||
| 2919 | #define CTIMER_EMR_EM1_MASK (0x2U) | ||
| 2920 | #define CTIMER_EMR_EM1_SHIFT (1U) | ||
| 2921 | /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output | ||
| 2922 | * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, | ||
| 2923 | * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if | ||
| 2924 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 2925 | */ | ||
| 2926 | #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) | ||
| 2927 | #define CTIMER_EMR_EM2_MASK (0x4U) | ||
| 2928 | #define CTIMER_EMR_EM2_SHIFT (2U) | ||
| 2929 | /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output | ||
| 2930 | * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, | ||
| 2931 | * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if | ||
| 2932 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 2933 | */ | ||
| 2934 | #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) | ||
| 2935 | #define CTIMER_EMR_EM3_MASK (0x8U) | ||
| 2936 | #define CTIMER_EMR_EM3_SHIFT (3U) | ||
| 2937 | /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output | ||
| 2938 | * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, | ||
| 2939 | * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins | ||
| 2940 | * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 2941 | */ | ||
| 2942 | #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) | ||
| 2943 | #define CTIMER_EMR_EMC0_MASK (0x30U) | ||
| 2944 | #define CTIMER_EMR_EMC0_SHIFT (4U) | ||
| 2945 | /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. | ||
| 2946 | * 0b00..Do Nothing. | ||
| 2947 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). | ||
| 2948 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). | ||
| 2949 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 2950 | */ | ||
| 2951 | #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) | ||
| 2952 | #define CTIMER_EMR_EMC1_MASK (0xC0U) | ||
| 2953 | #define CTIMER_EMR_EMC1_SHIFT (6U) | ||
| 2954 | /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. | ||
| 2955 | * 0b00..Do Nothing. | ||
| 2956 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). | ||
| 2957 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). | ||
| 2958 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 2959 | */ | ||
| 2960 | #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) | ||
| 2961 | #define CTIMER_EMR_EMC2_MASK (0x300U) | ||
| 2962 | #define CTIMER_EMR_EMC2_SHIFT (8U) | ||
| 2963 | /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. | ||
| 2964 | * 0b00..Do Nothing. | ||
| 2965 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). | ||
| 2966 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). | ||
| 2967 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 2968 | */ | ||
| 2969 | #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) | ||
| 2970 | #define CTIMER_EMR_EMC3_MASK (0xC00U) | ||
| 2971 | #define CTIMER_EMR_EMC3_SHIFT (10U) | ||
| 2972 | /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. | ||
| 2973 | * 0b00..Do Nothing. | ||
| 2974 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). | ||
| 2975 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). | ||
| 2976 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 2977 | */ | ||
| 2978 | #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) | ||
| 2979 | /*! @} */ | ||
| 2980 | |||
| 2981 | /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ | ||
| 2982 | /*! @{ */ | ||
| 2983 | #define CTIMER_CTCR_CTMODE_MASK (0x3U) | ||
| 2984 | #define CTIMER_CTCR_CTMODE_SHIFT (0U) | ||
| 2985 | /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment | ||
| 2986 | * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC | ||
| 2987 | * is incremented when the Prescale Counter matches the Prescale Register. | ||
| 2988 | * 0b00..Timer Mode. Incremented every rising APB bus clock edge. | ||
| 2989 | * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. | ||
| 2990 | * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. | ||
| 2991 | * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. | ||
| 2992 | */ | ||
| 2993 | #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) | ||
| 2994 | #define CTIMER_CTCR_CINSEL_MASK (0xCU) | ||
| 2995 | #define CTIMER_CTCR_CINSEL_SHIFT (2U) | ||
| 2996 | /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which | ||
| 2997 | * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input | ||
| 2998 | * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be | ||
| 2999 | * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the | ||
| 3000 | * same timer. | ||
| 3001 | * 0b00..Channel 0. CAPn.0 for CTIMERn | ||
| 3002 | * 0b01..Channel 1. CAPn.1 for CTIMERn | ||
| 3003 | * 0b10..Channel 2. CAPn.2 for CTIMERn | ||
| 3004 | * 0b11..Channel 3. CAPn.3 for CTIMERn | ||
| 3005 | */ | ||
| 3006 | #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) | ||
| 3007 | #define CTIMER_CTCR_ENCC_MASK (0x10U) | ||
| 3008 | #define CTIMER_CTCR_ENCC_SHIFT (4U) | ||
| 3009 | /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the | ||
| 3010 | * capture-edge event specified in bits 7:5 occurs. | ||
| 3011 | */ | ||
| 3012 | #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) | ||
| 3013 | #define CTIMER_CTCR_SELCC_MASK (0xE0U) | ||
| 3014 | #define CTIMER_CTCR_SELCC_SHIFT (5U) | ||
| 3015 | /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the | ||
| 3016 | * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to | ||
| 3017 | * 0x3 and 0x6 to 0x7 are reserved. | ||
| 3018 | * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 3019 | * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 3020 | * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 3021 | * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 3022 | * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 3023 | * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 3024 | */ | ||
| 3025 | #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) | ||
| 3026 | /*! @} */ | ||
| 3027 | |||
| 3028 | /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ | ||
| 3029 | /*! @{ */ | ||
| 3030 | #define CTIMER_PWMC_PWMEN0_MASK (0x1U) | ||
| 3031 | #define CTIMER_PWMC_PWMEN0_SHIFT (0U) | ||
| 3032 | /*! PWMEN0 - PWM mode enable for channel0. | ||
| 3033 | * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. | ||
| 3034 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. | ||
| 3035 | */ | ||
| 3036 | #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) | ||
| 3037 | #define CTIMER_PWMC_PWMEN1_MASK (0x2U) | ||
| 3038 | #define CTIMER_PWMC_PWMEN1_SHIFT (1U) | ||
| 3039 | /*! PWMEN1 - PWM mode enable for channel1. | ||
| 3040 | * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. | ||
| 3041 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. | ||
| 3042 | */ | ||
| 3043 | #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) | ||
| 3044 | #define CTIMER_PWMC_PWMEN2_MASK (0x4U) | ||
| 3045 | #define CTIMER_PWMC_PWMEN2_SHIFT (2U) | ||
| 3046 | /*! PWMEN2 - PWM mode enable for channel2. | ||
| 3047 | * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. | ||
| 3048 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. | ||
| 3049 | */ | ||
| 3050 | #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) | ||
| 3051 | #define CTIMER_PWMC_PWMEN3_MASK (0x8U) | ||
| 3052 | #define CTIMER_PWMC_PWMEN3_SHIFT (3U) | ||
| 3053 | /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. | ||
| 3054 | * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. | ||
| 3055 | * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. | ||
| 3056 | */ | ||
| 3057 | #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) | ||
| 3058 | /*! @} */ | ||
| 3059 | |||
| 3060 | /*! @name MSR - Match Shadow Register */ | ||
| 3061 | /*! @{ */ | ||
| 3062 | #define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) | ||
| 3063 | #define CTIMER_MSR_SHADOWW_SHIFT (0U) | ||
| 3064 | /*! SHADOWW - Timer counter match shadow value. | ||
| 3065 | */ | ||
| 3066 | #define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) | ||
| 3067 | /*! @} */ | ||
| 3068 | |||
| 3069 | /* The count of CTIMER_MSR */ | ||
| 3070 | #define CTIMER_MSR_COUNT (4U) | ||
| 3071 | |||
| 3072 | |||
| 3073 | /*! | ||
| 3074 | * @} | ||
| 3075 | */ /* end of group CTIMER_Register_Masks */ | ||
| 3076 | |||
| 3077 | |||
| 3078 | /* CTIMER - Peripheral instance base addresses */ | ||
| 3079 | /** Peripheral CTIMER0 base address */ | ||
| 3080 | #define CTIMER0_BASE (0x40008000u) | ||
| 3081 | /** Peripheral CTIMER0 base pointer */ | ||
| 3082 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 3083 | /** Peripheral CTIMER1 base address */ | ||
| 3084 | #define CTIMER1_BASE (0x40009000u) | ||
| 3085 | /** Peripheral CTIMER1 base pointer */ | ||
| 3086 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) | ||
| 3087 | /** Peripheral CTIMER2 base address */ | ||
| 3088 | #define CTIMER2_BASE (0x40028000u) | ||
| 3089 | /** Peripheral CTIMER2 base pointer */ | ||
| 3090 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) | ||
| 3091 | /** Peripheral CTIMER3 base address */ | ||
| 3092 | #define CTIMER3_BASE (0x40048000u) | ||
| 3093 | /** Peripheral CTIMER3 base pointer */ | ||
| 3094 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) | ||
| 3095 | /** Peripheral CTIMER4 base address */ | ||
| 3096 | #define CTIMER4_BASE (0x40049000u) | ||
| 3097 | /** Peripheral CTIMER4 base pointer */ | ||
| 3098 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) | ||
| 3099 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 3100 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } | ||
| 3101 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 3102 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } | ||
| 3103 | /** Interrupt vectors for the CTIMER peripheral type */ | ||
| 3104 | #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } | ||
| 3105 | |||
| 3106 | /*! | ||
| 3107 | * @} | ||
| 3108 | */ /* end of group CTIMER_Peripheral_Access_Layer */ | ||
| 3109 | |||
| 3110 | |||
| 3111 | /* ---------------------------------------------------------------------------- | ||
| 3112 | -- DMA Peripheral Access Layer | ||
| 3113 | ---------------------------------------------------------------------------- */ | ||
| 3114 | |||
| 3115 | /*! | ||
| 3116 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 3117 | * @{ | ||
| 3118 | */ | ||
| 3119 | |||
| 3120 | /** DMA - Register Layout Typedef */ | ||
| 3121 | typedef struct { | ||
| 3122 | __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ | ||
| 3123 | __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ | ||
| 3124 | __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ | ||
| 3125 | uint8_t RESERVED_0[20]; | ||
| 3126 | struct { /* offset: 0x20, array step: 0x5C */ | ||
| 3127 | __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ | ||
| 3128 | uint8_t RESERVED_0[4]; | ||
| 3129 | __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ | ||
| 3130 | uint8_t RESERVED_1[4]; | ||
| 3131 | __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ | ||
| 3132 | uint8_t RESERVED_2[4]; | ||
| 3133 | __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ | ||
| 3134 | uint8_t RESERVED_3[4]; | ||
| 3135 | __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ | ||
| 3136 | uint8_t RESERVED_4[4]; | ||
| 3137 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ | ||
| 3138 | uint8_t RESERVED_5[4]; | ||
| 3139 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ | ||
| 3140 | uint8_t RESERVED_6[4]; | ||
| 3141 | __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ | ||
| 3142 | uint8_t RESERVED_7[4]; | ||
| 3143 | __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ | ||
| 3144 | uint8_t RESERVED_8[4]; | ||
| 3145 | __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ | ||
| 3146 | uint8_t RESERVED_9[4]; | ||
| 3147 | __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ | ||
| 3148 | uint8_t RESERVED_10[4]; | ||
| 3149 | __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ | ||
| 3150 | } COMMON[1]; | ||
| 3151 | uint8_t RESERVED_1[900]; | ||
| 3152 | struct { /* offset: 0x400, array step: 0x10 */ | ||
| 3153 | __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ | ||
| 3154 | __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ | ||
| 3155 | __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ | ||
| 3156 | uint8_t RESERVED_0[4]; | ||
| 3157 | } CHANNEL[30]; | ||
| 3158 | } DMA_Type; | ||
| 3159 | |||
| 3160 | /* ---------------------------------------------------------------------------- | ||
| 3161 | -- DMA Register Masks | ||
| 3162 | ---------------------------------------------------------------------------- */ | ||
| 3163 | |||
| 3164 | /*! | ||
| 3165 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 3166 | * @{ | ||
| 3167 | */ | ||
| 3168 | |||
| 3169 | /*! @name CTRL - DMA control. */ | ||
| 3170 | /*! @{ */ | ||
| 3171 | #define DMA_CTRL_ENABLE_MASK (0x1U) | ||
| 3172 | #define DMA_CTRL_ENABLE_SHIFT (0U) | ||
| 3173 | /*! ENABLE - DMA controller master enable. | ||
| 3174 | * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when | ||
| 3175 | * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. | ||
| 3176 | * 0b1..Enabled. The DMA controller is enabled. | ||
| 3177 | */ | ||
| 3178 | #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) | ||
| 3179 | /*! @} */ | ||
| 3180 | |||
| 3181 | /*! @name INTSTAT - Interrupt status. */ | ||
| 3182 | /*! @{ */ | ||
| 3183 | #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) | ||
| 3184 | #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) | ||
| 3185 | /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. | ||
| 3186 | * 0b0..Not pending. No enabled interrupts are pending. | ||
| 3187 | * 0b1..Pending. At least one enabled interrupt is pending. | ||
| 3188 | */ | ||
| 3189 | #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) | ||
| 3190 | #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) | ||
| 3191 | #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) | ||
| 3192 | /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. | ||
| 3193 | * 0b0..Not pending. No error interrupts are pending. | ||
| 3194 | * 0b1..Pending. At least one error interrupt is pending. | ||
| 3195 | */ | ||
| 3196 | #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) | ||
| 3197 | /*! @} */ | ||
| 3198 | |||
| 3199 | /*! @name SRAMBASE - SRAM address of the channel configuration table. */ | ||
| 3200 | /*! @{ */ | ||
| 3201 | #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) | ||
| 3202 | #define DMA_SRAMBASE_OFFSET_SHIFT (9U) | ||
| 3203 | /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the | ||
| 3204 | * table must begin on a 512 byte boundary. | ||
| 3205 | */ | ||
| 3206 | #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) | ||
| 3207 | /*! @} */ | ||
| 3208 | |||
| 3209 | /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ | ||
| 3210 | /*! @{ */ | ||
| 3211 | #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) | ||
| 3212 | #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) | ||
| 3213 | /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = | ||
| 3214 | * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. | ||
| 3215 | */ | ||
| 3216 | #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) | ||
| 3217 | /*! @} */ | ||
| 3218 | |||
| 3219 | /* The count of DMA_COMMON_ENABLESET */ | ||
| 3220 | #define DMA_COMMON_ENABLESET_COUNT (1U) | ||
| 3221 | |||
| 3222 | /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ | ||
| 3223 | /*! @{ */ | ||
| 3224 | #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) | ||
| 3225 | #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) | ||
| 3226 | /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears | ||
| 3227 | * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits | ||
| 3228 | * are reserved. | ||
| 3229 | */ | ||
| 3230 | #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) | ||
| 3231 | /*! @} */ | ||
| 3232 | |||
| 3233 | /* The count of DMA_COMMON_ENABLECLR */ | ||
| 3234 | #define DMA_COMMON_ENABLECLR_COUNT (1U) | ||
| 3235 | |||
| 3236 | /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ | ||
| 3237 | /*! @{ */ | ||
| 3238 | #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) | ||
| 3239 | #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) | ||
| 3240 | /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 3241 | * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. | ||
| 3242 | */ | ||
| 3243 | #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) | ||
| 3244 | /*! @} */ | ||
| 3245 | |||
| 3246 | /* The count of DMA_COMMON_ACTIVE */ | ||
| 3247 | #define DMA_COMMON_ACTIVE_COUNT (1U) | ||
| 3248 | |||
| 3249 | /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ | ||
| 3250 | /*! @{ */ | ||
| 3251 | #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) | ||
| 3252 | #define DMA_COMMON_BUSY_BSY_SHIFT (0U) | ||
| 3253 | /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 3254 | * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. | ||
| 3255 | */ | ||
| 3256 | #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) | ||
| 3257 | /*! @} */ | ||
| 3258 | |||
| 3259 | /* The count of DMA_COMMON_BUSY */ | ||
| 3260 | #define DMA_COMMON_BUSY_COUNT (1U) | ||
| 3261 | |||
| 3262 | /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ | ||
| 3263 | /*! @{ */ | ||
| 3264 | #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) | ||
| 3265 | #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) | ||
| 3266 | /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 3267 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is | ||
| 3268 | * not active. 1 = error interrupt is active. | ||
| 3269 | */ | ||
| 3270 | #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) | ||
| 3271 | /*! @} */ | ||
| 3272 | |||
| 3273 | /* The count of DMA_COMMON_ERRINT */ | ||
| 3274 | #define DMA_COMMON_ERRINT_COUNT (1U) | ||
| 3275 | |||
| 3276 | /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ | ||
| 3277 | /*! @{ */ | ||
| 3278 | #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) | ||
| 3279 | #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) | ||
| 3280 | /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The | ||
| 3281 | * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = | ||
| 3282 | * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. | ||
| 3283 | */ | ||
| 3284 | #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) | ||
| 3285 | /*! @} */ | ||
| 3286 | |||
| 3287 | /* The count of DMA_COMMON_INTENSET */ | ||
| 3288 | #define DMA_COMMON_INTENSET_COUNT (1U) | ||
| 3289 | |||
| 3290 | /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ | ||
| 3291 | /*! @{ */ | ||
| 3292 | #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) | ||
| 3293 | #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) | ||
| 3294 | /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n | ||
| 3295 | * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are | ||
| 3296 | * reserved. | ||
| 3297 | */ | ||
| 3298 | #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) | ||
| 3299 | /*! @} */ | ||
| 3300 | |||
| 3301 | /* The count of DMA_COMMON_INTENCLR */ | ||
| 3302 | #define DMA_COMMON_INTENCLR_COUNT (1U) | ||
| 3303 | |||
| 3304 | /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ | ||
| 3305 | /*! @{ */ | ||
| 3306 | #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) | ||
| 3307 | #define DMA_COMMON_INTA_IA_SHIFT (0U) | ||
| 3308 | /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 3309 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 3310 | * interrupt A is not active. 1 = the DMA channel interrupt A is active. | ||
| 3311 | */ | ||
| 3312 | #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) | ||
| 3313 | /*! @} */ | ||
| 3314 | |||
| 3315 | /* The count of DMA_COMMON_INTA */ | ||
| 3316 | #define DMA_COMMON_INTA_COUNT (1U) | ||
| 3317 | |||
| 3318 | /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ | ||
| 3319 | /*! @{ */ | ||
| 3320 | #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) | ||
| 3321 | #define DMA_COMMON_INTB_IB_SHIFT (0U) | ||
| 3322 | /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 3323 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 3324 | * interrupt B is not active. 1 = the DMA channel interrupt B is active. | ||
| 3325 | */ | ||
| 3326 | #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) | ||
| 3327 | /*! @} */ | ||
| 3328 | |||
| 3329 | /* The count of DMA_COMMON_INTB */ | ||
| 3330 | #define DMA_COMMON_INTB_COUNT (1U) | ||
| 3331 | |||
| 3332 | /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ | ||
| 3333 | /*! @{ */ | ||
| 3334 | #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) | ||
| 3335 | #define DMA_COMMON_SETVALID_SV_SHIFT (0U) | ||
| 3336 | /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits | ||
| 3337 | * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the | ||
| 3338 | * VALIDPENDING control bit for DMA channel n | ||
| 3339 | */ | ||
| 3340 | #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) | ||
| 3341 | /*! @} */ | ||
| 3342 | |||
| 3343 | /* The count of DMA_COMMON_SETVALID */ | ||
| 3344 | #define DMA_COMMON_SETVALID_COUNT (1U) | ||
| 3345 | |||
| 3346 | /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ | ||
| 3347 | /*! @{ */ | ||
| 3348 | #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) | ||
| 3349 | #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) | ||
| 3350 | /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number | ||
| 3351 | * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = | ||
| 3352 | * sets the TRIG bit for DMA channel n. | ||
| 3353 | */ | ||
| 3354 | #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) | ||
| 3355 | /*! @} */ | ||
| 3356 | |||
| 3357 | /* The count of DMA_COMMON_SETTRIG */ | ||
| 3358 | #define DMA_COMMON_SETTRIG_COUNT (1U) | ||
| 3359 | |||
| 3360 | /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ | ||
| 3361 | /*! @{ */ | ||
| 3362 | #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) | ||
| 3363 | #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) | ||
| 3364 | /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. | ||
| 3365 | * 1 = aborts DMA operations on channel n. | ||
| 3366 | */ | ||
| 3367 | #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) | ||
| 3368 | /*! @} */ | ||
| 3369 | |||
| 3370 | /* The count of DMA_COMMON_ABORT */ | ||
| 3371 | #define DMA_COMMON_ABORT_COUNT (1U) | ||
| 3372 | |||
| 3373 | /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ | ||
| 3374 | /*! @{ */ | ||
| 3375 | #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) | ||
| 3376 | #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) | ||
| 3377 | /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory | ||
| 3378 | * move, any peripheral DMA request associated with that channel can be disabled to prevent any | ||
| 3379 | * interaction between the peripheral and the DMA controller. | ||
| 3380 | * 0b0..Disabled. Peripheral DMA requests are disabled. | ||
| 3381 | * 0b1..Enabled. Peripheral DMA requests are enabled. | ||
| 3382 | */ | ||
| 3383 | #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) | ||
| 3384 | #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) | ||
| 3385 | #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) | ||
| 3386 | /*! HWTRIGEN - Hardware Triggering Enable for this channel. | ||
| 3387 | * 0b0..Disabled. Hardware triggering is not used. | ||
| 3388 | * 0b1..Enabled. Use hardware triggering. | ||
| 3389 | */ | ||
| 3390 | #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) | ||
| 3391 | #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) | ||
| 3392 | #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) | ||
| 3393 | /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. | ||
| 3394 | * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. | ||
| 3395 | * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. | ||
| 3396 | */ | ||
| 3397 | #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) | ||
| 3398 | #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) | ||
| 3399 | #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) | ||
| 3400 | /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. | ||
| 3401 | * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. | ||
| 3402 | * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = | ||
| 3403 | * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the | ||
| 3404 | * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger | ||
| 3405 | * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the | ||
| 3406 | * current BURSTPOWER length are completed. | ||
| 3407 | */ | ||
| 3408 | #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) | ||
| 3409 | #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) | ||
| 3410 | #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) | ||
| 3411 | /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. | ||
| 3412 | * 0b0..Single transfer. Hardware trigger causes a single transfer. | ||
| 3413 | * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a | ||
| 3414 | * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a | ||
| 3415 | * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is | ||
| 3416 | * complete. | ||
| 3417 | */ | ||
| 3418 | #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) | ||
| 3419 | #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) | ||
| 3420 | #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) | ||
| 3421 | /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when | ||
| 3422 | * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). | ||
| 3423 | * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many | ||
| 3424 | * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that | ||
| 3425 | * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: | ||
| 3426 | * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = | ||
| 3427 | * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The | ||
| 3428 | * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even | ||
| 3429 | * multiple of the burst size. | ||
| 3430 | */ | ||
| 3431 | #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) | ||
| 3432 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) | ||
| 3433 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) | ||
| 3434 | /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is | ||
| 3435 | * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this | ||
| 3436 | * could be used to read several sequential registers from a peripheral for each DMA burst, | ||
| 3437 | * reading the same registers again for each burst. | ||
| 3438 | * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. | ||
| 3439 | * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. | ||
| 3440 | */ | ||
| 3441 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) | ||
| 3442 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) | ||
| 3443 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) | ||
| 3444 | /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is | ||
| 3445 | * 'wrapped', meaning that the destination address range for each burst will be the same. As an | ||
| 3446 | * example, this could be used to write several sequential registers to a peripheral for each DMA | ||
| 3447 | * burst, writing the same registers again for each burst. | ||
| 3448 | * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. | ||
| 3449 | * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. | ||
| 3450 | */ | ||
| 3451 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) | ||
| 3452 | #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) | ||
| 3453 | #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) | ||
| 3454 | /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority | ||
| 3455 | * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. | ||
| 3456 | */ | ||
| 3457 | #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) | ||
| 3458 | /*! @} */ | ||
| 3459 | |||
| 3460 | /* The count of DMA_CHANNEL_CFG */ | ||
| 3461 | #define DMA_CHANNEL_CFG_COUNT (30U) | ||
| 3462 | |||
| 3463 | /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ | ||
| 3464 | /*! @{ */ | ||
| 3465 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) | ||
| 3466 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) | ||
| 3467 | /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the | ||
| 3468 | * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. | ||
| 3469 | * 0b0..No effect. No effect on DMA operation. | ||
| 3470 | * 0b1..Valid pending. | ||
| 3471 | */ | ||
| 3472 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) | ||
| 3473 | #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) | ||
| 3474 | #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) | ||
| 3475 | /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is | ||
| 3476 | * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. | ||
| 3477 | * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. | ||
| 3478 | * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. | ||
| 3479 | */ | ||
| 3480 | #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) | ||
| 3481 | /*! @} */ | ||
| 3482 | |||
| 3483 | /* The count of DMA_CHANNEL_CTLSTAT */ | ||
| 3484 | #define DMA_CHANNEL_CTLSTAT_COUNT (30U) | ||
| 3485 | |||
| 3486 | /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ | ||
| 3487 | /*! @{ */ | ||
| 3488 | #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) | ||
| 3489 | #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) | ||
| 3490 | /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor | ||
| 3491 | * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. | ||
| 3492 | * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. | ||
| 3493 | * 0b1..Valid. The current channel descriptor is considered valid. | ||
| 3494 | */ | ||
| 3495 | #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) | ||
| 3496 | #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) | ||
| 3497 | #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) | ||
| 3498 | /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current | ||
| 3499 | * descriptor is exhausted. Reloading allows ping-pong and linked transfers. | ||
| 3500 | * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. | ||
| 3501 | * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. | ||
| 3502 | */ | ||
| 3503 | #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) | ||
| 3504 | #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) | ||
| 3505 | #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) | ||
| 3506 | /*! SWTRIG - Software Trigger. | ||
| 3507 | * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by | ||
| 3508 | * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. | ||
| 3509 | * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not | ||
| 3510 | * be used with level triggering when TRIGBURST = 0. | ||
| 3511 | */ | ||
| 3512 | #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) | ||
| 3513 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) | ||
| 3514 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) | ||
| 3515 | /*! CLRTRIG - Clear Trigger. | ||
| 3516 | * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. | ||
| 3517 | * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted | ||
| 3518 | */ | ||
| 3519 | #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) | ||
| 3520 | #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) | ||
| 3521 | #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) | ||
| 3522 | /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between | ||
| 3523 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 3524 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 3525 | * 0b0..No effect. | ||
| 3526 | * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. | ||
| 3527 | */ | ||
| 3528 | #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) | ||
| 3529 | #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) | ||
| 3530 | #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) | ||
| 3531 | /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between | ||
| 3532 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 3533 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 3534 | * 0b0..No effect. | ||
| 3535 | * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. | ||
| 3536 | */ | ||
| 3537 | #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) | ||
| 3538 | #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) | ||
| 3539 | #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) | ||
| 3540 | /*! WIDTH - Transfer width used for this DMA channel. | ||
| 3541 | * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). | ||
| 3542 | * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). | ||
| 3543 | * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). | ||
| 3544 | * 0b11..Reserved. Reserved setting, do not use. | ||
| 3545 | */ | ||
| 3546 | #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) | ||
| 3547 | #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) | ||
| 3548 | #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) | ||
| 3549 | /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. | ||
| 3550 | * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. | ||
| 3551 | * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is | ||
| 3552 | * the usual case when the source is memory. | ||
| 3553 | * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 3554 | * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 3555 | */ | ||
| 3556 | #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) | ||
| 3557 | #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) | ||
| 3558 | #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) | ||
| 3559 | /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. | ||
| 3560 | * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when | ||
| 3561 | * the destination is a peripheral device. | ||
| 3562 | * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. | ||
| 3563 | * This is the usual case when the destination is memory. | ||
| 3564 | * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 3565 | * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 3566 | */ | ||
| 3567 | #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) | ||
| 3568 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) | ||
| 3569 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) | ||
| 3570 | /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes | ||
| 3571 | * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller | ||
| 3572 | * uses this bit field during transfer to count down. Hence, it cannot be used by software to read | ||
| 3573 | * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 | ||
| 3574 | * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of | ||
| 3575 | * 1,024 transfers will be performed. | ||
| 3576 | */ | ||
| 3577 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) | ||
| 3578 | /*! @} */ | ||
| 3579 | |||
| 3580 | /* The count of DMA_CHANNEL_XFERCFG */ | ||
| 3581 | #define DMA_CHANNEL_XFERCFG_COUNT (30U) | ||
| 3582 | |||
| 3583 | |||
| 3584 | /*! | ||
| 3585 | * @} | ||
| 3586 | */ /* end of group DMA_Register_Masks */ | ||
| 3587 | |||
| 3588 | |||
| 3589 | /* DMA - Peripheral instance base addresses */ | ||
| 3590 | /** Peripheral DMA0 base address */ | ||
| 3591 | #define DMA0_BASE (0x40082000u) | ||
| 3592 | /** Peripheral DMA0 base pointer */ | ||
| 3593 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 3594 | /** Array initializer of DMA peripheral base addresses */ | ||
| 3595 | #define DMA_BASE_ADDRS { DMA0_BASE } | ||
| 3596 | /** Array initializer of DMA peripheral base pointers */ | ||
| 3597 | #define DMA_BASE_PTRS { DMA0 } | ||
| 3598 | /** Interrupt vectors for the DMA peripheral type */ | ||
| 3599 | #define DMA_IRQS { DMA0_IRQn } | ||
| 3600 | |||
| 3601 | /*! | ||
| 3602 | * @} | ||
| 3603 | */ /* end of group DMA_Peripheral_Access_Layer */ | ||
| 3604 | |||
| 3605 | |||
| 3606 | /* ---------------------------------------------------------------------------- | ||
| 3607 | -- DMIC Peripheral Access Layer | ||
| 3608 | ---------------------------------------------------------------------------- */ | ||
| 3609 | |||
| 3610 | /*! | ||
| 3611 | * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer | ||
| 3612 | * @{ | ||
| 3613 | */ | ||
| 3614 | |||
| 3615 | /** DMIC - Register Layout Typedef */ | ||
| 3616 | typedef struct { | ||
| 3617 | struct { /* offset: 0x0, array step: 0x100 */ | ||
| 3618 | __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ | ||
| 3619 | __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ | ||
| 3620 | __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ | ||
| 3621 | __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ | ||
| 3622 | __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ | ||
| 3623 | uint8_t RESERVED_0[108]; | ||
| 3624 | __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ | ||
| 3625 | __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ | ||
| 3626 | __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ | ||
| 3627 | __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ | ||
| 3628 | __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ | ||
| 3629 | uint8_t RESERVED_1[108]; | ||
| 3630 | } CHANNEL[2]; | ||
| 3631 | uint8_t RESERVED_0[3328]; | ||
| 3632 | __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ | ||
| 3633 | uint8_t RESERVED_1[8]; | ||
| 3634 | __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ | ||
| 3635 | __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ | ||
| 3636 | uint8_t RESERVED_2[108]; | ||
| 3637 | __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ | ||
| 3638 | __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ | ||
| 3639 | __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ | ||
| 3640 | __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ | ||
| 3641 | __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ | ||
| 3642 | __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ | ||
| 3643 | __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ | ||
| 3644 | uint8_t RESERVED_3[96]; | ||
| 3645 | __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ | ||
| 3646 | } DMIC_Type; | ||
| 3647 | |||
| 3648 | /* ---------------------------------------------------------------------------- | ||
| 3649 | -- DMIC Register Masks | ||
| 3650 | ---------------------------------------------------------------------------- */ | ||
| 3651 | |||
| 3652 | /*! | ||
| 3653 | * @addtogroup DMIC_Register_Masks DMIC Register Masks | ||
| 3654 | * @{ | ||
| 3655 | */ | ||
| 3656 | |||
| 3657 | /*! @name CHANNEL_OSR - Oversample Rate register 0 */ | ||
| 3658 | /*! @{ */ | ||
| 3659 | #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) | ||
| 3660 | #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) | ||
| 3661 | /*! OSR - Selects the oversample rate for the related input channel. | ||
| 3662 | */ | ||
| 3663 | #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) | ||
| 3664 | /*! @} */ | ||
| 3665 | |||
| 3666 | /* The count of DMIC_CHANNEL_OSR */ | ||
| 3667 | #define DMIC_CHANNEL_OSR_COUNT (2U) | ||
| 3668 | |||
| 3669 | /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ | ||
| 3670 | /*! @{ */ | ||
| 3671 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) | ||
| 3672 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) | ||
| 3673 | /*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by | ||
| 3674 | * 4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = | ||
| 3675 | * divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others = | ||
| 3676 | * reserved. | ||
| 3677 | */ | ||
| 3678 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) | ||
| 3679 | /*! @} */ | ||
| 3680 | |||
| 3681 | /* The count of DMIC_CHANNEL_DIVHFCLK */ | ||
| 3682 | #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) | ||
| 3683 | |||
| 3684 | /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ | ||
| 3685 | /*! @{ */ | ||
| 3686 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) | ||
| 3687 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) | ||
| 3688 | /*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16 | ||
| 3689 | * 2 = Compensation = 15 3 = Compensation = 13 | ||
| 3690 | */ | ||
| 3691 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) | ||
| 3692 | /*! @} */ | ||
| 3693 | |||
| 3694 | /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ | ||
| 3695 | #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) | ||
| 3696 | |||
| 3697 | /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ | ||
| 3698 | /*! @{ */ | ||
| 3699 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) | ||
| 3700 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) | ||
| 3701 | /*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16 | ||
| 3702 | * 2 = Compensation = 15 3 = Compensation = 13 | ||
| 3703 | */ | ||
| 3704 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) | ||
| 3705 | /*! @} */ | ||
| 3706 | |||
| 3707 | /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ | ||
| 3708 | #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) | ||
| 3709 | |||
| 3710 | /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ | ||
| 3711 | /*! @{ */ | ||
| 3712 | #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) | ||
| 3713 | #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) | ||
| 3714 | /*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift. | ||
| 3715 | */ | ||
| 3716 | #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) | ||
| 3717 | /*! @} */ | ||
| 3718 | |||
| 3719 | /* The count of DMIC_CHANNEL_GAINSHIFT */ | ||
| 3720 | #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) | ||
| 3721 | |||
| 3722 | /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ | ||
| 3723 | /*! @{ */ | ||
| 3724 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) | ||
| 3725 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) | ||
| 3726 | /*! ENABLE - FIFO enable. | ||
| 3727 | * 0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being | ||
| 3728 | * streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a | ||
| 3729 | * period when the data was not needed. | ||
| 3730 | * 0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register. | ||
| 3731 | */ | ||
| 3732 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) | ||
| 3733 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) | ||
| 3734 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) | ||
| 3735 | /*! RESETN - FIFO reset. | ||
| 3736 | * 0b0..Reset the FIFO. | ||
| 3737 | * 0b1..Normal operation | ||
| 3738 | */ | ||
| 3739 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) | ||
| 3740 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) | ||
| 3741 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) | ||
| 3742 | /*! INTEN - Interrupt enable. | ||
| 3743 | * 0b0..FIFO level interrupts are not enabled. | ||
| 3744 | * 0b1..FIFO level interrupts are enabled. | ||
| 3745 | */ | ||
| 3746 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) | ||
| 3747 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) | ||
| 3748 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) | ||
| 3749 | /*! DMAEN - DMA enable | ||
| 3750 | * 0b0..DMA requests are not enabled. | ||
| 3751 | * 0b1..DMA requests based on FIFO level are enabled. | ||
| 3752 | */ | ||
| 3753 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) | ||
| 3754 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) | ||
| 3755 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) | ||
| 3756 | /*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If | ||
| 3757 | * enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then | ||
| 3758 | * return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 = | ||
| 3759 | * trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has | ||
| 3760 | * received two entries. 15 = trigger when the FIFO has received 16 entries (has become full). | ||
| 3761 | */ | ||
| 3762 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) | ||
| 3763 | /*! @} */ | ||
| 3764 | |||
| 3765 | /* The count of DMIC_CHANNEL_FIFO_CTRL */ | ||
| 3766 | #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) | ||
| 3767 | |||
| 3768 | /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ | ||
| 3769 | /*! @{ */ | ||
| 3770 | #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) | ||
| 3771 | #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) | ||
| 3772 | /*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL | ||
| 3773 | * register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC | ||
| 3774 | * subsystem must be running in order for an interrupt to occur. | ||
| 3775 | */ | ||
| 3776 | #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) | ||
| 3777 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) | ||
| 3778 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) | ||
| 3779 | /*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one | ||
| 3780 | * to this bit clears the flag. This flag does not cause an interrupt. | ||
| 3781 | */ | ||
| 3782 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) | ||
| 3783 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) | ||
| 3784 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) | ||
| 3785 | /*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag. | ||
| 3786 | */ | ||
| 3787 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) | ||
| 3788 | /*! @} */ | ||
| 3789 | |||
| 3790 | /* The count of DMIC_CHANNEL_FIFO_STATUS */ | ||
| 3791 | #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) | ||
| 3792 | |||
| 3793 | /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ | ||
| 3794 | /*! @{ */ | ||
| 3795 | #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) | ||
| 3796 | #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) | ||
| 3797 | /*! DATA - Data from the top of the input filter FIFO. | ||
| 3798 | */ | ||
| 3799 | #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) | ||
| 3800 | /*! @} */ | ||
| 3801 | |||
| 3802 | /* The count of DMIC_CHANNEL_FIFO_DATA */ | ||
| 3803 | #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) | ||
| 3804 | |||
| 3805 | /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ | ||
| 3806 | /*! @{ */ | ||
| 3807 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) | ||
| 3808 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) | ||
| 3809 | /*! PHY_FALL - Capture PDM_DATA | ||
| 3810 | * 0b0..Capture PDM_DATA on the rising edge of PDM_CLK. | ||
| 3811 | * 0b1..Capture PDM_DATA on the falling edge of PDM_CLK. | ||
| 3812 | */ | ||
| 3813 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) | ||
| 3814 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) | ||
| 3815 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) | ||
| 3816 | /*! PHY_HALF - Half rate sampling | ||
| 3817 | * 0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing. | ||
| 3818 | * 0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing. | ||
| 3819 | */ | ||
| 3820 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) | ||
| 3821 | /*! @} */ | ||
| 3822 | |||
| 3823 | /* The count of DMIC_CHANNEL_PHY_CTRL */ | ||
| 3824 | #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) | ||
| 3825 | |||
| 3826 | /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ | ||
| 3827 | /*! @{ */ | ||
| 3828 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) | ||
| 3829 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) | ||
| 3830 | /*! DCPOLE - DC block filter | ||
| 3831 | * 0b00..Flat response, no filter. | ||
| 3832 | * 0b01..155 Hz. | ||
| 3833 | * 0b10..78 Hz. | ||
| 3834 | * 0b11..39 Hz | ||
| 3835 | */ | ||
| 3836 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) | ||
| 3837 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) | ||
| 3838 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) | ||
| 3839 | /*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift. | ||
| 3840 | */ | ||
| 3841 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) | ||
| 3842 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) | ||
| 3843 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) | ||
| 3844 | /*! SATURATEAT16BIT - Selects 16-bit saturation. | ||
| 3845 | * 0b0..Results roll over if out range and do not saturate. | ||
| 3846 | * 0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow. | ||
| 3847 | */ | ||
| 3848 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) | ||
| 3849 | /*! @} */ | ||
| 3850 | |||
| 3851 | /* The count of DMIC_CHANNEL_DC_CTRL */ | ||
| 3852 | #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) | ||
| 3853 | |||
| 3854 | /*! @name CHANEN - Channel Enable register */ | ||
| 3855 | /*! @{ */ | ||
| 3856 | #define DMIC_CHANEN_EN_CH0_MASK (0x1U) | ||
| 3857 | #define DMIC_CHANEN_EN_CH0_SHIFT (0U) | ||
| 3858 | /*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled. | ||
| 3859 | */ | ||
| 3860 | #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) | ||
| 3861 | #define DMIC_CHANEN_EN_CH1_MASK (0x2U) | ||
| 3862 | #define DMIC_CHANEN_EN_CH1_SHIFT (1U) | ||
| 3863 | /*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled. | ||
| 3864 | */ | ||
| 3865 | #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) | ||
| 3866 | /*! @} */ | ||
| 3867 | |||
| 3868 | /*! @name IOCFG - I/O Configuration register */ | ||
| 3869 | /*! @{ */ | ||
| 3870 | #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) | ||
| 3871 | #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) | ||
| 3872 | /*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides | ||
| 3873 | * for the possibility of an external codec taking over the PDM bus. | ||
| 3874 | */ | ||
| 3875 | #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) | ||
| 3876 | #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) | ||
| 3877 | #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) | ||
| 3878 | /*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides | ||
| 3879 | * for the possibility of an external codec taking over the PDM bus. | ||
| 3880 | */ | ||
| 3881 | #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) | ||
| 3882 | #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) | ||
| 3883 | #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) | ||
| 3884 | /*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a | ||
| 3885 | * configuration that supports a single stereo digital microphone. | ||
| 3886 | */ | ||
| 3887 | #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) | ||
| 3888 | /*! @} */ | ||
| 3889 | |||
| 3890 | /*! @name USE2FS - Use 2FS register */ | ||
| 3891 | /*! @{ */ | ||
| 3892 | #define DMIC_USE2FS_USE2FS_MASK (0x1U) | ||
| 3893 | #define DMIC_USE2FS_USE2FS_SHIFT (0U) | ||
| 3894 | /*! USE2FS - Use 2FS register | ||
| 3895 | * 0b0..Use 1FS output for PCM data. | ||
| 3896 | * 0b1..Use 2FS output for PCM data. | ||
| 3897 | */ | ||
| 3898 | #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) | ||
| 3899 | /*! @} */ | ||
| 3900 | |||
| 3901 | /*! @name HWVADGAIN - HWVAD input gain register */ | ||
| 3902 | /*! @{ */ | ||
| 3903 | #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) | ||
| 3904 | #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) | ||
| 3905 | /*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04 | ||
| 3906 | * -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 | ||
| 3907 | * bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved. | ||
| 3908 | */ | ||
| 3909 | #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) | ||
| 3910 | /*! @} */ | ||
| 3911 | |||
| 3912 | /*! @name HWVADHPFS - HWVAD filter control register */ | ||
| 3913 | /*! @{ */ | ||
| 3914 | #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) | ||
| 3915 | #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) | ||
| 3916 | /*! HPFS - High pass filter | ||
| 3917 | * 0b00..First filter by-pass. | ||
| 3918 | * 0b01..High pass filter with -3dB cut-off at 1750Hz. | ||
| 3919 | * 0b10..High pass filter with -3dB cut-off at 215Hz. | ||
| 3920 | * 0b11..Reserved. | ||
| 3921 | */ | ||
| 3922 | #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) | ||
| 3923 | /*! @} */ | ||
| 3924 | |||
| 3925 | /*! @name HWVADST10 - HWVAD control register */ | ||
| 3926 | /*! @{ */ | ||
| 3927 | #define DMIC_HWVADST10_ST10_MASK (0x1U) | ||
| 3928 | #define DMIC_HWVADST10_ST10_SHIFT (0U) | ||
| 3929 | /*! ST10 - Stage 0 | ||
| 3930 | * 0b0..Normal operation, waiting for HWVAD trigger event (stage 0). | ||
| 3931 | * 0b1..Reset internal interrupt flag by writing a '1' pulse. | ||
| 3932 | */ | ||
| 3933 | #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) | ||
| 3934 | /*! @} */ | ||
| 3935 | |||
| 3936 | /*! @name HWVADRSTT - HWVAD filter reset register */ | ||
| 3937 | /*! @{ */ | ||
| 3938 | #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) | ||
| 3939 | #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) | ||
| 3940 | /*! RSTT - Writing a 1 resets all filter values | ||
| 3941 | */ | ||
| 3942 | #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) | ||
| 3943 | /*! @} */ | ||
| 3944 | |||
| 3945 | /*! @name HWVADTHGN - HWVAD noise estimator gain register */ | ||
| 3946 | /*! @{ */ | ||
| 3947 | #define DMIC_HWVADTHGN_THGN_MASK (0xFU) | ||
| 3948 | #define DMIC_HWVADTHGN_THGN_SHIFT (0U) | ||
| 3949 | /*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1. | ||
| 3950 | */ | ||
| 3951 | #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) | ||
| 3952 | /*! @} */ | ||
| 3953 | |||
| 3954 | /*! @name HWVADTHGS - HWVAD signal estimator gain register */ | ||
| 3955 | /*! @{ */ | ||
| 3956 | #define DMIC_HWVADTHGS_THGS_MASK (0xFU) | ||
| 3957 | #define DMIC_HWVADTHGS_THGS_SHIFT (0U) | ||
| 3958 | /*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1. | ||
| 3959 | */ | ||
| 3960 | #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) | ||
| 3961 | /*! @} */ | ||
| 3962 | |||
| 3963 | /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ | ||
| 3964 | /*! @{ */ | ||
| 3965 | #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) | ||
| 3966 | #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) | ||
| 3967 | /*! LOWZ - Noise envelope estimator value. | ||
| 3968 | */ | ||
| 3969 | #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) | ||
| 3970 | /*! @} */ | ||
| 3971 | |||
| 3972 | /*! @name ID - Module Identification register */ | ||
| 3973 | /*! @{ */ | ||
| 3974 | #define DMIC_ID_ID_MASK (0xFFFFFFFFU) | ||
| 3975 | #define DMIC_ID_ID_SHIFT (0U) | ||
| 3976 | /*! ID - Indicates module ID and the number of channels in this DMIC interface. | ||
| 3977 | */ | ||
| 3978 | #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) | ||
| 3979 | /*! @} */ | ||
| 3980 | |||
| 3981 | |||
| 3982 | /*! | ||
| 3983 | * @} | ||
| 3984 | */ /* end of group DMIC_Register_Masks */ | ||
| 3985 | |||
| 3986 | |||
| 3987 | /* DMIC - Peripheral instance base addresses */ | ||
| 3988 | /** Peripheral DMIC0 base address */ | ||
| 3989 | #define DMIC0_BASE (0x40090000u) | ||
| 3990 | /** Peripheral DMIC0 base pointer */ | ||
| 3991 | #define DMIC0 ((DMIC_Type *)DMIC0_BASE) | ||
| 3992 | /** Array initializer of DMIC peripheral base addresses */ | ||
| 3993 | #define DMIC_BASE_ADDRS { DMIC0_BASE } | ||
| 3994 | /** Array initializer of DMIC peripheral base pointers */ | ||
| 3995 | #define DMIC_BASE_PTRS { DMIC0 } | ||
| 3996 | /** Interrupt vectors for the DMIC peripheral type */ | ||
| 3997 | #define DMIC_IRQS { DMIC0_IRQn } | ||
| 3998 | #define DMIC_HWVAD_IRQS { HWVAD0_IRQn } | ||
| 3999 | |||
| 4000 | /*! | ||
| 4001 | * @} | ||
| 4002 | */ /* end of group DMIC_Peripheral_Access_Layer */ | ||
| 4003 | |||
| 4004 | |||
| 4005 | /* ---------------------------------------------------------------------------- | ||
| 4006 | -- EEPROM Peripheral Access Layer | ||
| 4007 | ---------------------------------------------------------------------------- */ | ||
| 4008 | |||
| 4009 | /*! | ||
| 4010 | * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer | ||
| 4011 | * @{ | ||
| 4012 | */ | ||
| 4013 | |||
| 4014 | /** EEPROM - Register Layout Typedef */ | ||
| 4015 | typedef struct { | ||
| 4016 | __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */ | ||
| 4017 | uint8_t RESERVED_0[4]; | ||
| 4018 | __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */ | ||
| 4019 | __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */ | ||
| 4020 | __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */ | ||
| 4021 | __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */ | ||
| 4022 | __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */ | ||
| 4023 | uint8_t RESERVED_1[4028]; | ||
| 4024 | __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */ | ||
| 4025 | __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */ | ||
| 4026 | __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */ | ||
| 4027 | __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */ | ||
| 4028 | __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */ | ||
| 4029 | __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */ | ||
| 4030 | } EEPROM_Type; | ||
| 4031 | |||
| 4032 | /* ---------------------------------------------------------------------------- | ||
| 4033 | -- EEPROM Register Masks | ||
| 4034 | ---------------------------------------------------------------------------- */ | ||
| 4035 | |||
| 4036 | /*! | ||
| 4037 | * @addtogroup EEPROM_Register_Masks EEPROM Register Masks | ||
| 4038 | * @{ | ||
| 4039 | */ | ||
| 4040 | |||
| 4041 | /*! @name CMD - EEPROM command register */ | ||
| 4042 | /*! @{ */ | ||
| 4043 | #define EEPROM_CMD_CMD_MASK (0x7U) | ||
| 4044 | #define EEPROM_CMD_CMD_SHIFT (0U) | ||
| 4045 | /*! CMD - Command. | ||
| 4046 | */ | ||
| 4047 | #define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK) | ||
| 4048 | /*! @} */ | ||
| 4049 | |||
| 4050 | /*! @name RWSTATE - EEPROM read wait state register */ | ||
| 4051 | /*! @{ */ | ||
| 4052 | #define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU) | ||
| 4053 | #define EEPROM_RWSTATE_RPHASE2_SHIFT (0U) | ||
| 4054 | /*! RPHASE2 - Wait states 2 (minus 1 encoded). | ||
| 4055 | */ | ||
| 4056 | #define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK) | ||
| 4057 | #define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U) | ||
| 4058 | #define EEPROM_RWSTATE_RPHASE1_SHIFT (8U) | ||
| 4059 | /*! RPHASE1 - Wait states 1 (minus 1 encoded). | ||
| 4060 | */ | ||
| 4061 | #define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK) | ||
| 4062 | /*! @} */ | ||
| 4063 | |||
| 4064 | /*! @name AUTOPROG - EEPROM auto programming register */ | ||
| 4065 | /*! @{ */ | ||
| 4066 | #define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U) | ||
| 4067 | #define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U) | ||
| 4068 | /*! AUTOPROG - Auto programming mode: 00 = auto programming off 01 = erase/program cycle is | ||
| 4069 | * triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address | ||
| 4070 | * ending with . | ||
| 4071 | */ | ||
| 4072 | #define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK) | ||
| 4073 | /*! @} */ | ||
| 4074 | |||
| 4075 | /*! @name WSTATE - EEPROM wait state register */ | ||
| 4076 | /*! @{ */ | ||
| 4077 | #define EEPROM_WSTATE_PHASE3_MASK (0xFFU) | ||
| 4078 | #define EEPROM_WSTATE_PHASE3_SHIFT (0U) | ||
| 4079 | /*! PHASE3 - Wait states for phase 3 (minus 1 encoded). | ||
| 4080 | */ | ||
| 4081 | #define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK) | ||
| 4082 | #define EEPROM_WSTATE_PHASE2_MASK (0xFF00U) | ||
| 4083 | #define EEPROM_WSTATE_PHASE2_SHIFT (8U) | ||
| 4084 | /*! PHASE2 - Wait states for phase 2 (minus 1 encoded). | ||
| 4085 | */ | ||
| 4086 | #define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK) | ||
| 4087 | #define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U) | ||
| 4088 | #define EEPROM_WSTATE_PHASE1_SHIFT (16U) | ||
| 4089 | /*! PHASE1 - Wait states for phase 1 (minus 1 encoded). | ||
| 4090 | */ | ||
| 4091 | #define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK) | ||
| 4092 | #define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U) | ||
| 4093 | #define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U) | ||
| 4094 | /*! LCK_PARWEP - Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV | ||
| 4095 | * registers have R/W access 1 = WSTATE and CLKDIV registers have R only access. | ||
| 4096 | */ | ||
| 4097 | #define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK) | ||
| 4098 | /*! @} */ | ||
| 4099 | |||
| 4100 | /*! @name CLKDIV - EEPROM clock divider register */ | ||
| 4101 | /*! @{ */ | ||
| 4102 | #define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU) | ||
| 4103 | #define EEPROM_CLKDIV_CLKDIV_SHIFT (0U) | ||
| 4104 | /*! CLKDIV - Division factor (minus 1 encoded). | ||
| 4105 | */ | ||
| 4106 | #define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK) | ||
| 4107 | /*! @} */ | ||
| 4108 | |||
| 4109 | /*! @name PWRDWN - EEPROM power-down register */ | ||
| 4110 | /*! @{ */ | ||
| 4111 | #define EEPROM_PWRDWN_PWRDWN_MASK (0x1U) | ||
| 4112 | #define EEPROM_PWRDWN_PWRDWN_SHIFT (0U) | ||
| 4113 | /*! PWRDWN - Power down mode bit. | ||
| 4114 | */ | ||
| 4115 | #define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK) | ||
| 4116 | /*! @} */ | ||
| 4117 | |||
| 4118 | /*! @name INTENCLR - EEPROM interrupt enable clear */ | ||
| 4119 | /*! @{ */ | ||
| 4120 | #define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U) | ||
| 4121 | #define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U) | ||
| 4122 | /*! PROG_CLR_EN - Clear program operation finished interrupt enable bit for EEPROM. | ||
| 4123 | */ | ||
| 4124 | #define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK) | ||
| 4125 | /*! @} */ | ||
| 4126 | |||
| 4127 | /*! @name INTENSET - EEPROM interrupt enable set */ | ||
| 4128 | /*! @{ */ | ||
| 4129 | #define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U) | ||
| 4130 | #define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U) | ||
| 4131 | /*! PROG_SET_EN - Set program operation finished interrupt enable bit for EEPROM device 1. | ||
| 4132 | */ | ||
| 4133 | #define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK) | ||
| 4134 | /*! @} */ | ||
| 4135 | |||
| 4136 | /*! @name INTSTAT - EEPROM interrupt status */ | ||
| 4137 | /*! @{ */ | ||
| 4138 | #define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U) | ||
| 4139 | #define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U) | ||
| 4140 | /*! END_OF_PROG - EEPROM program operation finished interrupt status bit. | ||
| 4141 | */ | ||
| 4142 | #define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK) | ||
| 4143 | /*! @} */ | ||
| 4144 | |||
| 4145 | /*! @name INTEN - EEPROM interrupt enable */ | ||
| 4146 | /*! @{ */ | ||
| 4147 | #define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U) | ||
| 4148 | #define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U) | ||
| 4149 | /*! EE_PROG_DONE - EEPROM program operation finished interrupt enable bit. | ||
| 4150 | */ | ||
| 4151 | #define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK) | ||
| 4152 | /*! @} */ | ||
| 4153 | |||
| 4154 | /*! @name INTSTATCLR - EEPROM interrupt status clear */ | ||
| 4155 | /*! @{ */ | ||
| 4156 | #define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U) | ||
| 4157 | #define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U) | ||
| 4158 | /*! PROG_CLR_ST - Clear program operation finished interrupt status bit for EEPROM device. | ||
| 4159 | */ | ||
| 4160 | #define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK) | ||
| 4161 | /*! @} */ | ||
| 4162 | |||
| 4163 | /*! @name INTSTATSET - EEPROM interrupt status set */ | ||
| 4164 | /*! @{ */ | ||
| 4165 | #define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U) | ||
| 4166 | #define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U) | ||
| 4167 | /*! PROG_SET_ST - Set program operation finished interrupt status bit for EEPROM device. | ||
| 4168 | */ | ||
| 4169 | #define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK) | ||
| 4170 | /*! @} */ | ||
| 4171 | |||
| 4172 | |||
| 4173 | /*! | ||
| 4174 | * @} | ||
| 4175 | */ /* end of group EEPROM_Register_Masks */ | ||
| 4176 | |||
| 4177 | |||
| 4178 | /* EEPROM - Peripheral instance base addresses */ | ||
| 4179 | /** Peripheral EEPROM base address */ | ||
| 4180 | #define EEPROM_BASE (0x40014000u) | ||
| 4181 | /** Peripheral EEPROM base pointer */ | ||
| 4182 | #define EEPROM ((EEPROM_Type *)EEPROM_BASE) | ||
| 4183 | /** Array initializer of EEPROM peripheral base addresses */ | ||
| 4184 | #define EEPROM_BASE_ADDRS { EEPROM_BASE } | ||
| 4185 | /** Array initializer of EEPROM peripheral base pointers */ | ||
| 4186 | #define EEPROM_BASE_PTRS { EEPROM } | ||
| 4187 | /** Interrupt vectors for the EEPROM peripheral type */ | ||
| 4188 | #define EEPROM_IRQS { EEPROM_IRQn } | ||
| 4189 | |||
| 4190 | /*! | ||
| 4191 | * @} | ||
| 4192 | */ /* end of group EEPROM_Peripheral_Access_Layer */ | ||
| 4193 | |||
| 4194 | |||
| 4195 | /* ---------------------------------------------------------------------------- | ||
| 4196 | -- EMC Peripheral Access Layer | ||
| 4197 | ---------------------------------------------------------------------------- */ | ||
| 4198 | |||
| 4199 | /*! | ||
| 4200 | * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer | ||
| 4201 | * @{ | ||
| 4202 | */ | ||
| 4203 | |||
| 4204 | /** EMC - Register Layout Typedef */ | ||
| 4205 | typedef struct { | ||
| 4206 | __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */ | ||
| 4207 | __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */ | ||
| 4208 | __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */ | ||
| 4209 | uint8_t RESERVED_0[20]; | ||
| 4210 | __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */ | ||
| 4211 | __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */ | ||
| 4212 | __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */ | ||
| 4213 | uint8_t RESERVED_1[4]; | ||
| 4214 | __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */ | ||
| 4215 | __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */ | ||
| 4216 | __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */ | ||
| 4217 | __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */ | ||
| 4218 | __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */ | ||
| 4219 | __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */ | ||
| 4220 | __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */ | ||
| 4221 | __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */ | ||
| 4222 | __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */ | ||
| 4223 | __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */ | ||
| 4224 | __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */ | ||
| 4225 | uint8_t RESERVED_2[36]; | ||
| 4226 | __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */ | ||
| 4227 | uint8_t RESERVED_3[124]; | ||
| 4228 | struct { /* offset: 0x100, array step: 0x20 */ | ||
| 4229 | __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */ | ||
| 4230 | __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */ | ||
| 4231 | uint8_t RESERVED_0[24]; | ||
| 4232 | } DYNAMIC[4]; | ||
| 4233 | uint8_t RESERVED_4[128]; | ||
| 4234 | struct { /* offset: 0x200, array step: 0x20 */ | ||
| 4235 | __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */ | ||
| 4236 | __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */ | ||
| 4237 | __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */ | ||
| 4238 | __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */ | ||
| 4239 | __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */ | ||
| 4240 | __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */ | ||
| 4241 | __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */ | ||
| 4242 | uint8_t RESERVED_0[4]; | ||
| 4243 | } STATIC[4]; | ||
| 4244 | } EMC_Type; | ||
| 4245 | |||
| 4246 | /* ---------------------------------------------------------------------------- | ||
| 4247 | -- EMC Register Masks | ||
| 4248 | ---------------------------------------------------------------------------- */ | ||
| 4249 | |||
| 4250 | /*! | ||
| 4251 | * @addtogroup EMC_Register_Masks EMC Register Masks | ||
| 4252 | * @{ | ||
| 4253 | */ | ||
| 4254 | |||
| 4255 | /*! @name CONTROL - Controls operation of the memory controller */ | ||
| 4256 | /*! @{ */ | ||
| 4257 | #define EMC_CONTROL_E_MASK (0x1U) | ||
| 4258 | #define EMC_CONTROL_E_SHIFT (0U) | ||
| 4259 | /*! E - EMC Enable. | ||
| 4260 | */ | ||
| 4261 | #define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK) | ||
| 4262 | #define EMC_CONTROL_M_MASK (0x2U) | ||
| 4263 | #define EMC_CONTROL_M_SHIFT (1U) | ||
| 4264 | /*! M - Address mirror. | ||
| 4265 | */ | ||
| 4266 | #define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK) | ||
| 4267 | #define EMC_CONTROL_L_MASK (0x4U) | ||
| 4268 | #define EMC_CONTROL_L_SHIFT (2U) | ||
| 4269 | /*! L - Low-power mode. | ||
| 4270 | */ | ||
| 4271 | #define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK) | ||
| 4272 | /*! @} */ | ||
| 4273 | |||
| 4274 | /*! @name STATUS - Provides EMC status information */ | ||
| 4275 | /*! @{ */ | ||
| 4276 | #define EMC_STATUS_B_MASK (0x1U) | ||
| 4277 | #define EMC_STATUS_B_SHIFT (0U) | ||
| 4278 | /*! B - Busy. | ||
| 4279 | */ | ||
| 4280 | #define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK) | ||
| 4281 | #define EMC_STATUS_S_MASK (0x2U) | ||
| 4282 | #define EMC_STATUS_S_SHIFT (1U) | ||
| 4283 | /*! S - Write buffer status. | ||
| 4284 | */ | ||
| 4285 | #define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK) | ||
| 4286 | #define EMC_STATUS_SA_MASK (0x4U) | ||
| 4287 | #define EMC_STATUS_SA_SHIFT (2U) | ||
| 4288 | /*! SA - Self-refresh acknowledge. | ||
| 4289 | */ | ||
| 4290 | #define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK) | ||
| 4291 | /*! @} */ | ||
| 4292 | |||
| 4293 | /*! @name CONFIG - Configures operation of the memory controller */ | ||
| 4294 | /*! @{ */ | ||
| 4295 | #define EMC_CONFIG_EM_MASK (0x1U) | ||
| 4296 | #define EMC_CONFIG_EM_SHIFT (0U) | ||
| 4297 | /*! EM - Endian mode. | ||
| 4298 | */ | ||
| 4299 | #define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK) | ||
| 4300 | #define EMC_CONFIG_CLKR_MASK (0x100U) | ||
| 4301 | #define EMC_CONFIG_CLKR_SHIFT (8U) | ||
| 4302 | /*! CLKR - This bit must contain 0 for proper operation of the EMC. | ||
| 4303 | */ | ||
| 4304 | #define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK) | ||
| 4305 | /*! @} */ | ||
| 4306 | |||
| 4307 | /*! @name DYNAMICCONTROL - Controls dynamic memory operation */ | ||
| 4308 | /*! @{ */ | ||
| 4309 | #define EMC_DYNAMICCONTROL_CE_MASK (0x1U) | ||
| 4310 | #define EMC_DYNAMICCONTROL_CE_SHIFT (0U) | ||
| 4311 | /*! CE - Dynamic memory clock enable. | ||
| 4312 | */ | ||
| 4313 | #define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK) | ||
| 4314 | #define EMC_DYNAMICCONTROL_CS_MASK (0x2U) | ||
| 4315 | #define EMC_DYNAMICCONTROL_CS_SHIFT (1U) | ||
| 4316 | /*! CS - Dynamic memory clock control. | ||
| 4317 | */ | ||
| 4318 | #define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK) | ||
| 4319 | #define EMC_DYNAMICCONTROL_SR_MASK (0x4U) | ||
| 4320 | #define EMC_DYNAMICCONTROL_SR_SHIFT (2U) | ||
| 4321 | /*! SR - Self-refresh request, EMCSREFREQ. | ||
| 4322 | */ | ||
| 4323 | #define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK) | ||
| 4324 | #define EMC_DYNAMICCONTROL_MMC_MASK (0x20U) | ||
| 4325 | #define EMC_DYNAMICCONTROL_MMC_SHIFT (5U) | ||
| 4326 | /*! MMC - Memory clock control. | ||
| 4327 | */ | ||
| 4328 | #define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK) | ||
| 4329 | #define EMC_DYNAMICCONTROL_I_MASK (0x180U) | ||
| 4330 | #define EMC_DYNAMICCONTROL_I_SHIFT (7U) | ||
| 4331 | /*! I - SDRAM initialization. | ||
| 4332 | */ | ||
| 4333 | #define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK) | ||
| 4334 | /*! @} */ | ||
| 4335 | |||
| 4336 | /*! @name DYNAMICREFRESH - Configures dynamic memory refresh */ | ||
| 4337 | /*! @{ */ | ||
| 4338 | #define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU) | ||
| 4339 | #define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U) | ||
| 4340 | /*! REFRESH - Refresh timer. | ||
| 4341 | */ | ||
| 4342 | #define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK) | ||
| 4343 | /*! @} */ | ||
| 4344 | |||
| 4345 | /*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */ | ||
| 4346 | /*! @{ */ | ||
| 4347 | #define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U) | ||
| 4348 | #define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U) | ||
| 4349 | /*! RD - Read data strategy. | ||
| 4350 | */ | ||
| 4351 | #define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK) | ||
| 4352 | /*! @} */ | ||
| 4353 | |||
| 4354 | /*! @name DYNAMICRP - Precharge command period */ | ||
| 4355 | /*! @{ */ | ||
| 4356 | #define EMC_DYNAMICRP_TRP_MASK (0xFU) | ||
| 4357 | #define EMC_DYNAMICRP_TRP_SHIFT (0U) | ||
| 4358 | /*! TRP - Precharge command period. | ||
| 4359 | */ | ||
| 4360 | #define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK) | ||
| 4361 | /*! @} */ | ||
| 4362 | |||
| 4363 | /*! @name DYNAMICRAS - Active to precharge command period */ | ||
| 4364 | /*! @{ */ | ||
| 4365 | #define EMC_DYNAMICRAS_TRAS_MASK (0xFU) | ||
| 4366 | #define EMC_DYNAMICRAS_TRAS_SHIFT (0U) | ||
| 4367 | /*! TRAS - Active to precharge command period. | ||
| 4368 | */ | ||
| 4369 | #define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK) | ||
| 4370 | /*! @} */ | ||
| 4371 | |||
| 4372 | /*! @name DYNAMICSREX - Self-refresh exit time */ | ||
| 4373 | /*! @{ */ | ||
| 4374 | #define EMC_DYNAMICSREX_TSREX_MASK (0xFU) | ||
| 4375 | #define EMC_DYNAMICSREX_TSREX_SHIFT (0U) | ||
| 4376 | /*! TSREX - Self-refresh exit time. | ||
| 4377 | */ | ||
| 4378 | #define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK) | ||
| 4379 | /*! @} */ | ||
| 4380 | |||
| 4381 | /*! @name DYNAMICAPR - Last-data-out to active command time */ | ||
| 4382 | /*! @{ */ | ||
| 4383 | #define EMC_DYNAMICAPR_TAPR_MASK (0xFU) | ||
| 4384 | #define EMC_DYNAMICAPR_TAPR_SHIFT (0U) | ||
| 4385 | /*! TAPR - Last-data-out to active command time. | ||
| 4386 | */ | ||
| 4387 | #define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK) | ||
| 4388 | /*! @} */ | ||
| 4389 | |||
| 4390 | /*! @name DYNAMICDAL - Data-in to active command time */ | ||
| 4391 | /*! @{ */ | ||
| 4392 | #define EMC_DYNAMICDAL_TDAL_MASK (0xFU) | ||
| 4393 | #define EMC_DYNAMICDAL_TDAL_SHIFT (0U) | ||
| 4394 | /*! TDAL - Data-in to active command. | ||
| 4395 | */ | ||
| 4396 | #define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK) | ||
| 4397 | /*! @} */ | ||
| 4398 | |||
| 4399 | /*! @name DYNAMICWR - Write recovery time */ | ||
| 4400 | /*! @{ */ | ||
| 4401 | #define EMC_DYNAMICWR_TWR_MASK (0xFU) | ||
| 4402 | #define EMC_DYNAMICWR_TWR_SHIFT (0U) | ||
| 4403 | /*! TWR - Write recovery time. | ||
| 4404 | */ | ||
| 4405 | #define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK) | ||
| 4406 | /*! @} */ | ||
| 4407 | |||
| 4408 | /*! @name DYNAMICRC - Selects the active to active command period */ | ||
| 4409 | /*! @{ */ | ||
| 4410 | #define EMC_DYNAMICRC_TRC_MASK (0x1FU) | ||
| 4411 | #define EMC_DYNAMICRC_TRC_SHIFT (0U) | ||
| 4412 | /*! TRC - Active to active command period. | ||
| 4413 | */ | ||
| 4414 | #define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK) | ||
| 4415 | /*! @} */ | ||
| 4416 | |||
| 4417 | /*! @name DYNAMICRFC - Selects the auto-refresh period */ | ||
| 4418 | /*! @{ */ | ||
| 4419 | #define EMC_DYNAMICRFC_TRFC_MASK (0x1FU) | ||
| 4420 | #define EMC_DYNAMICRFC_TRFC_SHIFT (0U) | ||
| 4421 | /*! TRFC - Auto-refresh period and auto-refresh to active command period. | ||
| 4422 | */ | ||
| 4423 | #define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK) | ||
| 4424 | /*! @} */ | ||
| 4425 | |||
| 4426 | /*! @name DYNAMICXSR - Time for exit self-refresh to active command */ | ||
| 4427 | /*! @{ */ | ||
| 4428 | #define EMC_DYNAMICXSR_TXSR_MASK (0x1FU) | ||
| 4429 | #define EMC_DYNAMICXSR_TXSR_SHIFT (0U) | ||
| 4430 | /*! TXSR - Exit self-refresh to active command time. | ||
| 4431 | */ | ||
| 4432 | #define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK) | ||
| 4433 | /*! @} */ | ||
| 4434 | |||
| 4435 | /*! @name DYNAMICRRD - Latency for active bank A to active bank B */ | ||
| 4436 | /*! @{ */ | ||
| 4437 | #define EMC_DYNAMICRRD_TRRD_MASK (0xFU) | ||
| 4438 | #define EMC_DYNAMICRRD_TRRD_SHIFT (0U) | ||
| 4439 | /*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. | ||
| 4440 | */ | ||
| 4441 | #define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK) | ||
| 4442 | /*! @} */ | ||
| 4443 | |||
| 4444 | /*! @name DYNAMICMRD - Time for load mode register to active command */ | ||
| 4445 | /*! @{ */ | ||
| 4446 | #define EMC_DYNAMICMRD_TMRD_MASK (0xFU) | ||
| 4447 | #define EMC_DYNAMICMRD_TMRD_SHIFT (0U) | ||
| 4448 | /*! TMRD - Load mode register to active command time. | ||
| 4449 | */ | ||
| 4450 | #define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK) | ||
| 4451 | /*! @} */ | ||
| 4452 | |||
| 4453 | /*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */ | ||
| 4454 | /*! @{ */ | ||
| 4455 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU) | ||
| 4456 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U) | ||
| 4457 | /*! EXTENDEDWAIT - Extended wait time out. | ||
| 4458 | */ | ||
| 4459 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK) | ||
| 4460 | /*! @} */ | ||
| 4461 | |||
| 4462 | /*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */ | ||
| 4463 | /*! @{ */ | ||
| 4464 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U) | ||
| 4465 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U) | ||
| 4466 | /*! MD - Memory device. | ||
| 4467 | */ | ||
| 4468 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK) | ||
| 4469 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U) | ||
| 4470 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U) | ||
| 4471 | /*! AM0 - See Table 933. | ||
| 4472 | */ | ||
| 4473 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK) | ||
| 4474 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U) | ||
| 4475 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U) | ||
| 4476 | /*! AM1 - See Table 933. | ||
| 4477 | */ | ||
| 4478 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) | ||
| 4479 | #define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U) | ||
| 4480 | #define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U) | ||
| 4481 | /*! B - Buffer enable. | ||
| 4482 | */ | ||
| 4483 | #define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK) | ||
| 4484 | #define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U) | ||
| 4485 | #define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U) | ||
| 4486 | /*! P - Write protect. | ||
| 4487 | */ | ||
| 4488 | #define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK) | ||
| 4489 | /*! @} */ | ||
| 4490 | |||
| 4491 | /* The count of EMC_DYNAMIC_DYNAMICCONFIG */ | ||
| 4492 | #define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U) | ||
| 4493 | |||
| 4494 | /*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */ | ||
| 4495 | /*! @{ */ | ||
| 4496 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U) | ||
| 4497 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U) | ||
| 4498 | /*! RAS - RAS latency (active to read/write delay). | ||
| 4499 | */ | ||
| 4500 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK) | ||
| 4501 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U) | ||
| 4502 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U) | ||
| 4503 | /*! CAS - CAS latency. | ||
| 4504 | */ | ||
| 4505 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK) | ||
| 4506 | /*! @} */ | ||
| 4507 | |||
| 4508 | /* The count of EMC_DYNAMIC_DYNAMICRASCAS */ | ||
| 4509 | #define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U) | ||
| 4510 | |||
| 4511 | /*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */ | ||
| 4512 | /*! @{ */ | ||
| 4513 | #define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U) | ||
| 4514 | #define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U) | ||
| 4515 | /*! MW - Memory width. | ||
| 4516 | */ | ||
| 4517 | #define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK) | ||
| 4518 | #define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U) | ||
| 4519 | #define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U) | ||
| 4520 | /*! PM - Page mode. | ||
| 4521 | */ | ||
| 4522 | #define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK) | ||
| 4523 | #define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U) | ||
| 4524 | #define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U) | ||
| 4525 | /*! PC - Chip select polarity. | ||
| 4526 | */ | ||
| 4527 | #define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK) | ||
| 4528 | #define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U) | ||
| 4529 | #define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U) | ||
| 4530 | /*! PB - Byte lane state. | ||
| 4531 | */ | ||
| 4532 | #define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK) | ||
| 4533 | #define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U) | ||
| 4534 | #define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U) | ||
| 4535 | /*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write | ||
| 4536 | * transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. | ||
| 4537 | */ | ||
| 4538 | #define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK) | ||
| 4539 | #define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U) | ||
| 4540 | #define EMC_STATIC_STATICCONFIG_B_SHIFT (19U) | ||
| 4541 | /*! B - Buffer enable [2]. | ||
| 4542 | */ | ||
| 4543 | #define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK) | ||
| 4544 | #define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U) | ||
| 4545 | #define EMC_STATIC_STATICCONFIG_P_SHIFT (20U) | ||
| 4546 | /*! P - Write protect. | ||
| 4547 | */ | ||
| 4548 | #define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK) | ||
| 4549 | /*! @} */ | ||
| 4550 | |||
| 4551 | /* The count of EMC_STATIC_STATICCONFIG */ | ||
| 4552 | #define EMC_STATIC_STATICCONFIG_COUNT (4U) | ||
| 4553 | |||
| 4554 | /*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */ | ||
| 4555 | /*! @{ */ | ||
| 4556 | #define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU) | ||
| 4557 | #define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U) | ||
| 4558 | /*! WAITWEN - Wait write enable. | ||
| 4559 | */ | ||
| 4560 | #define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK) | ||
| 4561 | /*! @} */ | ||
| 4562 | |||
| 4563 | /* The count of EMC_STATIC_STATICWAITWEN */ | ||
| 4564 | #define EMC_STATIC_STATICWAITWEN_COUNT (4U) | ||
| 4565 | |||
| 4566 | /*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */ | ||
| 4567 | /*! @{ */ | ||
| 4568 | #define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU) | ||
| 4569 | #define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U) | ||
| 4570 | /*! WAITOEN - Wait output enable. | ||
| 4571 | */ | ||
| 4572 | #define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK) | ||
| 4573 | /*! @} */ | ||
| 4574 | |||
| 4575 | /* The count of EMC_STATIC_STATICWAITOEN */ | ||
| 4576 | #define EMC_STATIC_STATICWAITOEN_COUNT (4U) | ||
| 4577 | |||
| 4578 | /*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */ | ||
| 4579 | /*! @{ */ | ||
| 4580 | #define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU) | ||
| 4581 | #define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U) | ||
| 4582 | /*! WAITRD - . | ||
| 4583 | */ | ||
| 4584 | #define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK) | ||
| 4585 | /*! @} */ | ||
| 4586 | |||
| 4587 | /* The count of EMC_STATIC_STATICWAITRD */ | ||
| 4588 | #define EMC_STATIC_STATICWAITRD_COUNT (4U) | ||
| 4589 | |||
| 4590 | /*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */ | ||
| 4591 | /*! @{ */ | ||
| 4592 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU) | ||
| 4593 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U) | ||
| 4594 | /*! WAITPAGE - Asynchronous page mode read after the first read wait states. | ||
| 4595 | */ | ||
| 4596 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK) | ||
| 4597 | /*! @} */ | ||
| 4598 | |||
| 4599 | /* The count of EMC_STATIC_STATICWAITPAGE */ | ||
| 4600 | #define EMC_STATIC_STATICWAITPAGE_COUNT (4U) | ||
| 4601 | |||
| 4602 | /*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */ | ||
| 4603 | /*! @{ */ | ||
| 4604 | #define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU) | ||
| 4605 | #define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U) | ||
| 4606 | /*! WAITWR - Write wait states. | ||
| 4607 | */ | ||
| 4608 | #define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK) | ||
| 4609 | /*! @} */ | ||
| 4610 | |||
| 4611 | /* The count of EMC_STATIC_STATICWAITWR */ | ||
| 4612 | #define EMC_STATIC_STATICWAITWR_COUNT (4U) | ||
| 4613 | |||
| 4614 | /*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */ | ||
| 4615 | /*! @{ */ | ||
| 4616 | #define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU) | ||
| 4617 | #define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U) | ||
| 4618 | /*! WAITTURN - Bus turn-around cycles. | ||
| 4619 | */ | ||
| 4620 | #define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK) | ||
| 4621 | /*! @} */ | ||
| 4622 | |||
| 4623 | /* The count of EMC_STATIC_STATICWAITTURN */ | ||
| 4624 | #define EMC_STATIC_STATICWAITTURN_COUNT (4U) | ||
| 4625 | |||
| 4626 | |||
| 4627 | /*! | ||
| 4628 | * @} | ||
| 4629 | */ /* end of group EMC_Register_Masks */ | ||
| 4630 | |||
| 4631 | |||
| 4632 | /* EMC - Peripheral instance base addresses */ | ||
| 4633 | /** Peripheral EMC base address */ | ||
| 4634 | #define EMC_BASE (0x40081000u) | ||
| 4635 | /** Peripheral EMC base pointer */ | ||
| 4636 | #define EMC ((EMC_Type *)EMC_BASE) | ||
| 4637 | /** Array initializer of EMC peripheral base addresses */ | ||
| 4638 | #define EMC_BASE_ADDRS { EMC_BASE } | ||
| 4639 | /** Array initializer of EMC peripheral base pointers */ | ||
| 4640 | #define EMC_BASE_PTRS { EMC } | ||
| 4641 | |||
| 4642 | /*! | ||
| 4643 | * @} | ||
| 4644 | */ /* end of group EMC_Peripheral_Access_Layer */ | ||
| 4645 | |||
| 4646 | |||
| 4647 | /* ---------------------------------------------------------------------------- | ||
| 4648 | -- ENET Peripheral Access Layer | ||
| 4649 | ---------------------------------------------------------------------------- */ | ||
| 4650 | |||
| 4651 | /*! | ||
| 4652 | * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer | ||
| 4653 | * @{ | ||
| 4654 | */ | ||
| 4655 | |||
| 4656 | /** ENET - Register Layout Typedef */ | ||
| 4657 | typedef struct { | ||
| 4658 | __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */ | ||
| 4659 | __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */ | ||
| 4660 | __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */ | ||
| 4661 | __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */ | ||
| 4662 | uint8_t RESERVED_0[64]; | ||
| 4663 | __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */ | ||
| 4664 | uint8_t RESERVED_1[28]; | ||
| 4665 | __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */ | ||
| 4666 | uint8_t RESERVED_2[24]; | ||
| 4667 | __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */ | ||
| 4668 | uint8_t RESERVED_3[4]; | ||
| 4669 | __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */ | ||
| 4670 | uint8_t RESERVED_4[4]; | ||
| 4671 | __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */ | ||
| 4672 | uint8_t RESERVED_5[4]; | ||
| 4673 | __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */ | ||
| 4674 | __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */ | ||
| 4675 | __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */ | ||
| 4676 | uint8_t RESERVED_6[4]; | ||
| 4677 | __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */ | ||
| 4678 | __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */ | ||
| 4679 | uint8_t RESERVED_7[8]; | ||
| 4680 | __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */ | ||
| 4681 | __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */ | ||
| 4682 | __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */ | ||
| 4683 | __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */ | ||
| 4684 | uint8_t RESERVED_8[48]; | ||
| 4685 | __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */ | ||
| 4686 | __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */ | ||
| 4687 | uint8_t RESERVED_9[4]; | ||
| 4688 | __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */ | ||
| 4689 | uint8_t RESERVED_10[216]; | ||
| 4690 | __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */ | ||
| 4691 | __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */ | ||
| 4692 | uint8_t RESERVED_11[248]; | ||
| 4693 | __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */ | ||
| 4694 | __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */ | ||
| 4695 | uint8_t RESERVED_12[2040]; | ||
| 4696 | __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */ | ||
| 4697 | __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */ | ||
| 4698 | __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */ | ||
| 4699 | __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */ | ||
| 4700 | __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */ | ||
| 4701 | __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */ | ||
| 4702 | __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */ | ||
| 4703 | __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */ | ||
| 4704 | __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */ | ||
| 4705 | uint8_t RESERVED_13[12]; | ||
| 4706 | __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */ | ||
| 4707 | __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */ | ||
| 4708 | uint8_t RESERVED_14[32]; | ||
| 4709 | __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */ | ||
| 4710 | __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */ | ||
| 4711 | uint8_t RESERVED_15[160]; | ||
| 4712 | __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */ | ||
| 4713 | uint8_t RESERVED_16[28]; | ||
| 4714 | __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */ | ||
| 4715 | uint8_t RESERVED_17[12]; | ||
| 4716 | __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */ | ||
| 4717 | uint8_t RESERVED_18[204]; | ||
| 4718 | struct { /* offset: 0xD00, array step: 0x40 */ | ||
| 4719 | __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */ | ||
| 4720 | __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */ | ||
| 4721 | __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */ | ||
| 4722 | uint8_t RESERVED_0[4]; | ||
| 4723 | __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */ | ||
| 4724 | __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */ | ||
| 4725 | __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */ | ||
| 4726 | __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */ | ||
| 4727 | __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */ | ||
| 4728 | __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */ | ||
| 4729 | uint8_t RESERVED_1[4]; | ||
| 4730 | __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */ | ||
| 4731 | __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */ | ||
| 4732 | __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */ | ||
| 4733 | __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */ | ||
| 4734 | __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */ | ||
| 4735 | } MTL_QUEUE[2]; | ||
| 4736 | uint8_t RESERVED_19[640]; | ||
| 4737 | __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */ | ||
| 4738 | __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */ | ||
| 4739 | __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */ | ||
| 4740 | __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */ | ||
| 4741 | uint8_t RESERVED_20[240]; | ||
| 4742 | struct { /* offset: 0x1100, array step: 0x80 */ | ||
| 4743 | __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */ | ||
| 4744 | __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */ | ||
| 4745 | __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */ | ||
| 4746 | uint8_t RESERVED_0[8]; | ||
| 4747 | __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */ | ||
| 4748 | uint8_t RESERVED_1[4]; | ||
| 4749 | __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */ | ||
| 4750 | __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */ | ||
| 4751 | uint8_t RESERVED_2[4]; | ||
| 4752 | __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */ | ||
| 4753 | __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */ | ||
| 4754 | __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */ | ||
| 4755 | __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */ | ||
| 4756 | __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ | ||
| 4757 | __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ | ||
| 4758 | uint8_t RESERVED_3[4]; | ||
| 4759 | __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */ | ||
| 4760 | uint8_t RESERVED_4[4]; | ||
| 4761 | __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */ | ||
| 4762 | uint8_t RESERVED_5[4]; | ||
| 4763 | __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */ | ||
| 4764 | uint8_t RESERVED_6[4]; | ||
| 4765 | __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ | ||
| 4766 | __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */ | ||
| 4767 | uint8_t RESERVED_7[28]; | ||
| 4768 | } DMA_CH[2]; | ||
| 4769 | } ENET_Type; | ||
| 4770 | |||
| 4771 | /* ---------------------------------------------------------------------------- | ||
| 4772 | -- ENET Register Masks | ||
| 4773 | ---------------------------------------------------------------------------- */ | ||
| 4774 | |||
| 4775 | /*! | ||
| 4776 | * @addtogroup ENET_Register_Masks ENET Register Masks | ||
| 4777 | * @{ | ||
| 4778 | */ | ||
| 4779 | |||
| 4780 | /*! @name MAC_CONFIG - MAC configuration register */ | ||
| 4781 | /*! @{ */ | ||
| 4782 | #define ENET_MAC_CONFIG_RE_MASK (0x1U) | ||
| 4783 | #define ENET_MAC_CONFIG_RE_SHIFT (0U) | ||
| 4784 | /*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for | ||
| 4785 | * receiving frames from the MII. | ||
| 4786 | */ | ||
| 4787 | #define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK) | ||
| 4788 | #define ENET_MAC_CONFIG_TE_MASK (0x2U) | ||
| 4789 | #define ENET_MAC_CONFIG_TE_SHIFT (1U) | ||
| 4790 | /*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. | ||
| 4791 | */ | ||
| 4792 | #define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK) | ||
| 4793 | #define ENET_MAC_CONFIG_PRELEN_MASK (0xCU) | ||
| 4794 | #define ENET_MAC_CONFIG_PRELEN_SHIFT (2U) | ||
| 4795 | /*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes | ||
| 4796 | * that are added to the beginning of every Tx packet. | ||
| 4797 | */ | ||
| 4798 | #define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK) | ||
| 4799 | #define ENET_MAC_CONFIG_DC_MASK (0x10U) | ||
| 4800 | #define ENET_MAC_CONFIG_DC_SHIFT (4U) | ||
| 4801 | /*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. | ||
| 4802 | */ | ||
| 4803 | #define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK) | ||
| 4804 | #define ENET_MAC_CONFIG_BL_MASK (0x60U) | ||
| 4805 | #define ENET_MAC_CONFIG_BL_SHIFT (5U) | ||
| 4806 | /*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time | ||
| 4807 | * delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before | ||
| 4808 | * rescheduling a transmission attempt during retries after a collision. | ||
| 4809 | */ | ||
| 4810 | #define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK) | ||
| 4811 | #define ENET_MAC_CONFIG_DR_MASK (0x100U) | ||
| 4812 | #define ENET_MAC_CONFIG_DR_SHIFT (8U) | ||
| 4813 | /*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission. | ||
| 4814 | */ | ||
| 4815 | #define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK) | ||
| 4816 | #define ENET_MAC_CONFIG_DCRS_MASK (0x200U) | ||
| 4817 | #define ENET_MAC_CONFIG_DCRS_SHIFT (9U) | ||
| 4818 | /*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter | ||
| 4819 | * ignores the MII CRS signal during packet transmission in the half-duplex mode. | ||
| 4820 | */ | ||
| 4821 | #define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK) | ||
| 4822 | #define ENET_MAC_CONFIG_DO_MASK (0x400U) | ||
| 4823 | #define ENET_MAC_CONFIG_DO_SHIFT (10U) | ||
| 4824 | /*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the | ||
| 4825 | * gmii_txen_o is asserted in Half-Duplex mode. | ||
| 4826 | */ | ||
| 4827 | #define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK) | ||
| 4828 | #define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U) | ||
| 4829 | #define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U) | ||
| 4830 | /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the | ||
| 4831 | * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. | ||
| 4832 | */ | ||
| 4833 | #define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK) | ||
| 4834 | #define ENET_MAC_CONFIG_LM_MASK (0x1000U) | ||
| 4835 | #define ENET_MAC_CONFIG_LM_SHIFT (12U) | ||
| 4836 | /*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. | ||
| 4837 | */ | ||
| 4838 | #define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK) | ||
| 4839 | #define ENET_MAC_CONFIG_DM_MASK (0x2000U) | ||
| 4840 | #define ENET_MAC_CONFIG_DM_SHIFT (13U) | ||
| 4841 | /*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can | ||
| 4842 | * transmit and receive simultaneously. | ||
| 4843 | */ | ||
| 4844 | #define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK) | ||
| 4845 | #define ENET_MAC_CONFIG_FES_MASK (0x4000U) | ||
| 4846 | #define ENET_MAC_CONFIG_FES_SHIFT (14U) | ||
| 4847 | /*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by | ||
| 4848 | * default and is enabled only when RMII/SMII is enabled during configuration. | ||
| 4849 | */ | ||
| 4850 | #define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK) | ||
| 4851 | #define ENET_MAC_CONFIG_PS_MASK (0x8000U) | ||
| 4852 | #define ENET_MAC_CONFIG_PS_SHIFT (15U) | ||
| 4853 | /*! PS - Portselect. | ||
| 4854 | */ | ||
| 4855 | #define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK) | ||
| 4856 | #define ENET_MAC_CONFIG_JE_MASK (0x10000U) | ||
| 4857 | #define ENET_MAC_CONFIG_JE_SHIFT (16U) | ||
| 4858 | /*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 | ||
| 4859 | * bytes for tagged frames) without reporting a giant frame error in the receive frame status. | ||
| 4860 | */ | ||
| 4861 | #define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK) | ||
| 4862 | #define ENET_MAC_CONFIG_JD_MASK (0x20000U) | ||
| 4863 | #define ENET_MAC_CONFIG_JD_SHIFT (17U) | ||
| 4864 | /*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, | ||
| 4865 | * and can transfer frames of up to 16,384 bytes. | ||
| 4866 | */ | ||
| 4867 | #define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK) | ||
| 4868 | #define ENET_MAC_CONFIG_BE_MASK (0x40000U) | ||
| 4869 | #define ENET_MAC_CONFIG_BE_SHIFT (18U) | ||
| 4870 | /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during | ||
| 4871 | * transmission in the MII half-duplex mode. | ||
| 4872 | */ | ||
| 4873 | #define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK) | ||
| 4874 | #define ENET_MAC_CONFIG_WD_MASK (0x80000U) | ||
| 4875 | #define ENET_MAC_CONFIG_WD_SHIFT (19U) | ||
| 4876 | /*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, | ||
| 4877 | * and can receive frames of up to 16,384 bytes. | ||
| 4878 | */ | ||
| 4879 | #define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK) | ||
| 4880 | #define ENET_MAC_CONFIG_ACS_MASK (0x100000U) | ||
| 4881 | #define ENET_MAC_CONFIG_ACS_SHIFT (20U) | ||
| 4882 | /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field | ||
| 4883 | * on the incoming packets only if the value of the length field is less than 1,536 bytes. | ||
| 4884 | */ | ||
| 4885 | #define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK) | ||
| 4886 | #define ENET_MAC_CONFIG_CST_MASK (0x200000U) | ||
| 4887 | #define ENET_MAC_CONFIG_CST_SHIFT (21U) | ||
| 4888 | /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all | ||
| 4889 | * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding | ||
| 4890 | * the packet to the application. | ||
| 4891 | */ | ||
| 4892 | #define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK) | ||
| 4893 | #define ENET_MAC_CONFIG_S2KP_MASK (0x400000U) | ||
| 4894 | #define ENET_MAC_CONFIG_S2KP_SHIFT (22U) | ||
| 4895 | /*! S2KP - IEEE 802. | ||
| 4896 | */ | ||
| 4897 | #define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK) | ||
| 4898 | #define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U) | ||
| 4899 | #define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U) | ||
| 4900 | /*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the | ||
| 4901 | * value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet. | ||
| 4902 | */ | ||
| 4903 | #define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK) | ||
| 4904 | #define ENET_MAC_CONFIG_IPG_MASK (0x7000000U) | ||
| 4905 | #define ENET_MAC_CONFIG_IPG_SHIFT (24U) | ||
| 4906 | /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission. | ||
| 4907 | */ | ||
| 4908 | #define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK) | ||
| 4909 | #define ENET_MAC_CONFIG_IPC_MASK (0x8000000U) | ||
| 4910 | #define ENET_MAC_CONFIG_IPC_SHIFT (27U) | ||
| 4911 | /*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or | ||
| 4912 | * IPv6 TCP, UDP, or ICMP payload checksum checking. | ||
| 4913 | */ | ||
| 4914 | #define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK) | ||
| 4915 | /*! @} */ | ||
| 4916 | |||
| 4917 | /*! @name MAC_EXT_CONFIG - */ | ||
| 4918 | /*! @{ */ | ||
| 4919 | #define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU) | ||
| 4920 | #define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U) | ||
| 4921 | /*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed | ||
| 4922 | * in this field in units of bytes, the MAC declares the received packet as Giant packet. | ||
| 4923 | */ | ||
| 4924 | #define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK) | ||
| 4925 | #define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U) | ||
| 4926 | #define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U) | ||
| 4927 | /*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does | ||
| 4928 | * not check the CRC field in the received packets. | ||
| 4929 | */ | ||
| 4930 | #define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK) | ||
| 4931 | #define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U) | ||
| 4932 | #define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U) | ||
| 4933 | /*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol | ||
| 4934 | * packets (Ether Type 0x8809) and provides the Rx status. | ||
| 4935 | */ | ||
| 4936 | #define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK) | ||
| 4937 | #define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U) | ||
| 4938 | #define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U) | ||
| 4939 | /*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow | ||
| 4940 | * Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and | ||
| 4941 | * MAC Address Low Table 748 registers. | ||
| 4942 | */ | ||
| 4943 | #define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK) | ||
| 4944 | /*! @} */ | ||
| 4945 | |||
| 4946 | /*! @name MAC_FRAME_FILTER - MAC frame filter register */ | ||
| 4947 | /*! @{ */ | ||
| 4948 | #define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U) | ||
| 4949 | #define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U) | ||
| 4950 | /*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames | ||
| 4951 | * regardless of its destination or source address. | ||
| 4952 | */ | ||
| 4953 | #define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK) | ||
| 4954 | #define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U) | ||
| 4955 | #define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U) | ||
| 4956 | /*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse | ||
| 4957 | * filtering mode for the DA address comparison for both unicast and multicast frames. | ||
| 4958 | */ | ||
| 4959 | #define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK) | ||
| 4960 | #define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U) | ||
| 4961 | #define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U) | ||
| 4962 | /*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast | ||
| 4963 | * destination address (first bit in the destination address field is '1') are passed. | ||
| 4964 | */ | ||
| 4965 | #define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK) | ||
| 4966 | #define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U) | ||
| 4967 | #define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U) | ||
| 4968 | /*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. | ||
| 4969 | */ | ||
| 4970 | #define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK) | ||
| 4971 | #define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U) | ||
| 4972 | #define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U) | ||
| 4973 | /*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including | ||
| 4974 | * unicast and multicast PAUSE frames). | ||
| 4975 | */ | ||
| 4976 | #define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK) | ||
| 4977 | #define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U) | ||
| 4978 | #define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U) | ||
| 4979 | /*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the | ||
| 4980 | * inverse filtering mode for SA address comparison. | ||
| 4981 | */ | ||
| 4982 | #define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK) | ||
| 4983 | #define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U) | ||
| 4984 | #define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U) | ||
| 4985 | /*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the | ||
| 4986 | * received packets with the values programmed in the enabled SA registers. | ||
| 4987 | */ | ||
| 4988 | #define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK) | ||
| 4989 | #define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U) | ||
| 4990 | #define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U) | ||
| 4991 | /*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all | ||
| 4992 | * frames received irrespective of whether they pass the address filter. | ||
| 4993 | */ | ||
| 4994 | #define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK) | ||
| 4995 | /*! @} */ | ||
| 4996 | |||
| 4997 | /*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */ | ||
| 4998 | /*! @{ */ | ||
| 4999 | #define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU) | ||
| 5000 | #define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U) | ||
| 5001 | /*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register | ||
| 5002 | * Table 722 is reset, this field is used as watchdog timeout for a received packet. | ||
| 5003 | */ | ||
| 5004 | #define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK) | ||
| 5005 | #define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U) | ||
| 5006 | #define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U) | ||
| 5007 | /*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration | ||
| 5008 | * register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet. | ||
| 5009 | */ | ||
| 5010 | #define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK) | ||
| 5011 | /*! @} */ | ||
| 5012 | |||
| 5013 | /*! @name MAC_VLAN_TAG - MAC vlan tag register */ | ||
| 5014 | /*! @{ */ | ||
| 5015 | #define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU) | ||
| 5016 | #define ENET_MAC_VLAN_TAG_VL_SHIFT (0U) | ||
| 5017 | /*! VL - VLAN Tag Identifier for Receive Packets. | ||
| 5018 | */ | ||
| 5019 | #define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK) | ||
| 5020 | #define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U) | ||
| 5021 | #define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U) | ||
| 5022 | /*! ETV - Enable 12-Bit VLAN Tag Comparison. | ||
| 5023 | */ | ||
| 5024 | #define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK) | ||
| 5025 | #define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U) | ||
| 5026 | #define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U) | ||
| 5027 | /*! VTIM - VLAN Tag Inverse Match Enable. | ||
| 5028 | */ | ||
| 5029 | #define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK) | ||
| 5030 | #define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U) | ||
| 5031 | #define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U) | ||
| 5032 | /*! ESVL - Enable S-VLAN. | ||
| 5033 | */ | ||
| 5034 | #define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK) | ||
| 5035 | #define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U) | ||
| 5036 | #define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) | ||
| 5037 | /*! ERSVLM - Enable Receive S-VLAN Match. | ||
| 5038 | */ | ||
| 5039 | #define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK) | ||
| 5040 | #define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U) | ||
| 5041 | #define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) | ||
| 5042 | /*! DOVLTC - Disable VLAN Type Check. | ||
| 5043 | */ | ||
| 5044 | #define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK) | ||
| 5045 | #define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U) | ||
| 5046 | #define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U) | ||
| 5047 | /*! EVLS - Enable VLAN Tag Stripping on Receive. | ||
| 5048 | */ | ||
| 5049 | #define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK) | ||
| 5050 | #define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U) | ||
| 5051 | #define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) | ||
| 5052 | /*! EVLRXS - Enable VLAN Tag in Rx status. | ||
| 5053 | */ | ||
| 5054 | #define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK) | ||
| 5055 | #define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U) | ||
| 5056 | #define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U) | ||
| 5057 | /*! VTHM - Disable VLAN Type Check. | ||
| 5058 | */ | ||
| 5059 | #define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK) | ||
| 5060 | #define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U) | ||
| 5061 | #define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U) | ||
| 5062 | /*! EDVLP - Enable Double VLAN Processing. | ||
| 5063 | */ | ||
| 5064 | #define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK) | ||
| 5065 | #define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U) | ||
| 5066 | #define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U) | ||
| 5067 | /*! ERIVLT - Enable Inner VLAN Tag. | ||
| 5068 | */ | ||
| 5069 | #define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK) | ||
| 5070 | #define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U) | ||
| 5071 | #define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U) | ||
| 5072 | /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive. | ||
| 5073 | */ | ||
| 5074 | #define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK) | ||
| 5075 | #define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U) | ||
| 5076 | #define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U) | ||
| 5077 | /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status. | ||
| 5078 | */ | ||
| 5079 | #define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK) | ||
| 5080 | /*! @} */ | ||
| 5081 | |||
| 5082 | /*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */ | ||
| 5083 | /*! @{ */ | ||
| 5084 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U) | ||
| 5085 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U) | ||
| 5086 | /*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application | ||
| 5087 | * (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is | ||
| 5088 | * cleared to 0 by the core (Self Clear). | ||
| 5089 | */ | ||
| 5090 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK) | ||
| 5091 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) | ||
| 5092 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) | ||
| 5093 | /*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables | ||
| 5094 | * the flow control operation to transmit Pause frames. | ||
| 5095 | */ | ||
| 5096 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK) | ||
| 5097 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) | ||
| 5098 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) | ||
| 5099 | /*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the | ||
| 5100 | * input flow control signal is checked for automatic retransmission of PAUSE Frame. | ||
| 5101 | */ | ||
| 5102 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK) | ||
| 5103 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) | ||
| 5104 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) | ||
| 5105 | /*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of | ||
| 5106 | * Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. | ||
| 5107 | */ | ||
| 5108 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) | ||
| 5109 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) | ||
| 5110 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) | ||
| 5111 | /*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. | ||
| 5112 | */ | ||
| 5113 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK) | ||
| 5114 | /*! @} */ | ||
| 5115 | |||
| 5116 | /* The count of ENET_MAC_TX_FLOW_CTRL_Q */ | ||
| 5117 | #define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U) | ||
| 5118 | |||
| 5119 | /*! @name MAC_RX_FLOW_CTRL - Receive flow control register */ | ||
| 5120 | /*! @{ */ | ||
| 5121 | #define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) | ||
| 5122 | #define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) | ||
| 5123 | /*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex | ||
| 5124 | * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified | ||
| 5125 | * (Pause) time. | ||
| 5126 | */ | ||
| 5127 | #define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) | ||
| 5128 | #define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) | ||
| 5129 | #define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) | ||
| 5130 | /*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast | ||
| 5131 | * address specified in the IEEE 802. | ||
| 5132 | */ | ||
| 5133 | #define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK) | ||
| 5134 | /*! @} */ | ||
| 5135 | |||
| 5136 | /*! @name MAC_TXQ_PRIO_MAP - */ | ||
| 5137 | /*! @{ */ | ||
| 5138 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU) | ||
| 5139 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U) | ||
| 5140 | /*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software. | ||
| 5141 | */ | ||
| 5142 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK) | ||
| 5143 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U) | ||
| 5144 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U) | ||
| 5145 | /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. | ||
| 5146 | */ | ||
| 5147 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK) | ||
| 5148 | /*! @} */ | ||
| 5149 | |||
| 5150 | /*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */ | ||
| 5151 | /*! @{ */ | ||
| 5152 | #define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) | ||
| 5153 | #define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) | ||
| 5154 | /*! AVCPQ - AV Untagged Control Packets Queue. | ||
| 5155 | */ | ||
| 5156 | #define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK) | ||
| 5157 | #define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) | ||
| 5158 | #define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) | ||
| 5159 | /*! PSRQ0 - Priorities Selected in the Receive Queue 0. | ||
| 5160 | */ | ||
| 5161 | #define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK) | ||
| 5162 | #define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) | ||
| 5163 | #define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) | ||
| 5164 | /*! RXQ0EN - Receive Queue 0 Enable. | ||
| 5165 | */ | ||
| 5166 | #define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK) | ||
| 5167 | #define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) | ||
| 5168 | #define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) | ||
| 5169 | /*! RXQ1EN - Receive Queue 1 Enable. | ||
| 5170 | */ | ||
| 5171 | #define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK) | ||
| 5172 | #define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U) | ||
| 5173 | #define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U) | ||
| 5174 | /*! AVPTPQ - AV PTP Packets Queue. | ||
| 5175 | */ | ||
| 5176 | #define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK) | ||
| 5177 | #define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) | ||
| 5178 | #define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) | ||
| 5179 | /*! PSRQ1 - Priorities Selected in the Receive Queue 1. | ||
| 5180 | */ | ||
| 5181 | #define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK) | ||
| 5182 | #define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) | ||
| 5183 | #define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U) | ||
| 5184 | /*! UPQ - Untagged Packet Queue. | ||
| 5185 | */ | ||
| 5186 | #define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK) | ||
| 5187 | #define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) | ||
| 5188 | #define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) | ||
| 5189 | /*! MCBCQ - Multicast and Broadcast Queue. | ||
| 5190 | */ | ||
| 5191 | #define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK) | ||
| 5192 | #define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) | ||
| 5193 | #define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) | ||
| 5194 | /*! PSRQ2 - Priorities Selected in the Receive Queue 2. | ||
| 5195 | */ | ||
| 5196 | #define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK) | ||
| 5197 | #define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) | ||
| 5198 | #define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) | ||
| 5199 | /*! MCBCQEN - Multicast and Broadcast Queue Enable. | ||
| 5200 | */ | ||
| 5201 | #define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK) | ||
| 5202 | #define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) | ||
| 5203 | #define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) | ||
| 5204 | /*! PSRQ3 - Priorities Selected in the Receive Queue 3. | ||
| 5205 | */ | ||
| 5206 | #define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK) | ||
| 5207 | /*! @} */ | ||
| 5208 | |||
| 5209 | /* The count of ENET_MAC_RXQ_CTRL */ | ||
| 5210 | #define ENET_MAC_RXQ_CTRL_COUNT (3U) | ||
| 5211 | |||
| 5212 | /*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */ | ||
| 5213 | /*! @{ */ | ||
| 5214 | #define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U) | ||
| 5215 | #define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U) | ||
| 5216 | /*! PHYIS - PHY Interrupt. | ||
| 5217 | */ | ||
| 5218 | #define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK) | ||
| 5219 | #define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U) | ||
| 5220 | #define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U) | ||
| 5221 | /*! PMTIS - PMT Interrupt Status. | ||
| 5222 | */ | ||
| 5223 | #define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK) | ||
| 5224 | #define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U) | ||
| 5225 | #define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U) | ||
| 5226 | /*! LPIIS - LPI Interrupt Status. | ||
| 5227 | */ | ||
| 5228 | #define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK) | ||
| 5229 | #define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U) | ||
| 5230 | #define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U) | ||
| 5231 | /*! TSIS - Timestamp interrupt status. | ||
| 5232 | */ | ||
| 5233 | #define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK) | ||
| 5234 | #define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U) | ||
| 5235 | #define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U) | ||
| 5236 | /*! TXSTSIS - Transmit Status Interrupt. | ||
| 5237 | */ | ||
| 5238 | #define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK) | ||
| 5239 | #define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U) | ||
| 5240 | #define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U) | ||
| 5241 | /*! RXSTSIS - Receive Status Interrupt. | ||
| 5242 | */ | ||
| 5243 | #define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK) | ||
| 5244 | /*! @} */ | ||
| 5245 | |||
| 5246 | /*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */ | ||
| 5247 | /*! @{ */ | ||
| 5248 | #define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U) | ||
| 5249 | #define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U) | ||
| 5250 | /*! PHYIE - PHY Interrupt Enable. | ||
| 5251 | */ | ||
| 5252 | #define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK) | ||
| 5253 | #define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U) | ||
| 5254 | #define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U) | ||
| 5255 | /*! PMTIE - PMT Interrupt Enable. | ||
| 5256 | */ | ||
| 5257 | #define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK) | ||
| 5258 | #define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U) | ||
| 5259 | #define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U) | ||
| 5260 | /*! LPIIE - LPI Interrupt Enable. | ||
| 5261 | */ | ||
| 5262 | #define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK) | ||
| 5263 | #define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U) | ||
| 5264 | #define ENET_MAC_INTR_EN_TSIE_SHIFT (12U) | ||
| 5265 | /*! TSIE - Timestamp Interrupt Enable. | ||
| 5266 | */ | ||
| 5267 | #define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK) | ||
| 5268 | #define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U) | ||
| 5269 | #define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U) | ||
| 5270 | /*! TXSTSIE - Transmit Status Interrupt Enable. | ||
| 5271 | */ | ||
| 5272 | #define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK) | ||
| 5273 | #define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U) | ||
| 5274 | #define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U) | ||
| 5275 | /*! RXSTSIS - Receive Status Interrupt Enable. | ||
| 5276 | */ | ||
| 5277 | #define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK) | ||
| 5278 | /*! @} */ | ||
| 5279 | |||
| 5280 | /*! @name MAC_RXTX_STAT - Receive Transmit Status register */ | ||
| 5281 | /*! @{ */ | ||
| 5282 | #define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U) | ||
| 5283 | #define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U) | ||
| 5284 | /*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt | ||
| 5285 | * signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731. | ||
| 5286 | */ | ||
| 5287 | #define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK) | ||
| 5288 | #define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U) | ||
| 5289 | #define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U) | ||
| 5290 | /*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this | ||
| 5291 | * bit indicates that the carrier signal from the PHY is not present at the end of preamble | ||
| 5292 | * transmission. | ||
| 5293 | */ | ||
| 5294 | #define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK) | ||
| 5295 | #define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U) | ||
| 5296 | #define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U) | ||
| 5297 | /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, | ||
| 5298 | * this bit indicates that the loss of carrier occurred during packet transmission, that is, the | ||
| 5299 | * PHY Carrier signal was inactive for one or more transmission clock periods during packet | ||
| 5300 | * transmission. | ||
| 5301 | */ | ||
| 5302 | #define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK) | ||
| 5303 | #define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U) | ||
| 5304 | #define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U) | ||
| 5305 | /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table | ||
| 5306 | * 758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that | ||
| 5307 | * the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when | ||
| 5308 | * Jumbo packet is enabled). | ||
| 5309 | */ | ||
| 5310 | #define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK) | ||
| 5311 | #define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U) | ||
| 5312 | #define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U) | ||
| 5313 | /*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758, | ||
| 5314 | * this bit indicates that the packet transmission aborted because a collision occurred after the | ||
| 5315 | * collision window (64 bytes including Preamble in MII mode). | ||
| 5316 | */ | ||
| 5317 | #define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK) | ||
| 5318 | #define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U) | ||
| 5319 | #define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U) | ||
| 5320 | /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table | ||
| 5321 | * 758, this bit indicates that the transmission aborted after 16 successive collisions while | ||
| 5322 | * attempting to transmit the current packet. | ||
| 5323 | */ | ||
| 5324 | #define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK) | ||
| 5325 | #define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U) | ||
| 5326 | #define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U) | ||
| 5327 | /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 | ||
| 5328 | * bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the | ||
| 5329 | * MAC Configuration register Table 722. | ||
| 5330 | */ | ||
| 5331 | #define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK) | ||
| 5332 | /*! @} */ | ||
| 5333 | |||
| 5334 | /*! @name MAC_PMT_CRTL_STAT - */ | ||
| 5335 | /*! @{ */ | ||
| 5336 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U) | ||
| 5337 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U) | ||
| 5338 | /*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has | ||
| 5339 | * entered the LPI state because of the setting of the LPIEN bit. | ||
| 5340 | */ | ||
| 5341 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK) | ||
| 5342 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U) | ||
| 5343 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U) | ||
| 5344 | /*! MGKPKTEN - Magic Packet Enable. | ||
| 5345 | */ | ||
| 5346 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK) | ||
| 5347 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U) | ||
| 5348 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U) | ||
| 5349 | /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is | ||
| 5350 | * generated when the MAC receives a remote wake-up packet. | ||
| 5351 | */ | ||
| 5352 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK) | ||
| 5353 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U) | ||
| 5354 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U) | ||
| 5355 | /*! MGKPRCVD - Magic Packet Received. | ||
| 5356 | */ | ||
| 5357 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK) | ||
| 5358 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U) | ||
| 5359 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U) | ||
| 5360 | /*! RWKPRCVD - Remote Wake-Up Packet Received. | ||
| 5361 | */ | ||
| 5362 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK) | ||
| 5363 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U) | ||
| 5364 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U) | ||
| 5365 | /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) | ||
| 5366 | * address recognition is detected as a remote wake-up packet. | ||
| 5367 | */ | ||
| 5368 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK) | ||
| 5369 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U) | ||
| 5370 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U) | ||
| 5371 | /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the | ||
| 5372 | * MAC receiver drops all received frames until it receives the expected wake-up frame. | ||
| 5373 | */ | ||
| 5374 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK) | ||
| 5375 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U) | ||
| 5376 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U) | ||
| 5377 | /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote | ||
| 5378 | * Wake-up Packet Filter register pointer. | ||
| 5379 | */ | ||
| 5380 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK) | ||
| 5381 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U) | ||
| 5382 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U) | ||
| 5383 | /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the | ||
| 5384 | * remote wake-up packet filter register pointer is reset to 3'b000. | ||
| 5385 | */ | ||
| 5386 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK) | ||
| 5387 | /*! @} */ | ||
| 5388 | |||
| 5389 | /*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */ | ||
| 5390 | /*! @{ */ | ||
| 5391 | #define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU) | ||
| 5392 | #define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U) | ||
| 5393 | /*! ADDR - WKUPFMFILTER address. | ||
| 5394 | */ | ||
| 5395 | #define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK) | ||
| 5396 | /*! @} */ | ||
| 5397 | |||
| 5398 | /*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */ | ||
| 5399 | /*! @{ */ | ||
| 5400 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U) | ||
| 5401 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U) | ||
| 5402 | /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has | ||
| 5403 | * entered the LPI state because of the setting of the LPIEN bit. | ||
| 5404 | */ | ||
| 5405 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK) | ||
| 5406 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U) | ||
| 5407 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U) | ||
| 5408 | /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited | ||
| 5409 | * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. | ||
| 5410 | */ | ||
| 5411 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK) | ||
| 5412 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U) | ||
| 5413 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U) | ||
| 5414 | /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received | ||
| 5415 | * an LPI pattern and entered the LPI state. | ||
| 5416 | */ | ||
| 5417 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK) | ||
| 5418 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U) | ||
| 5419 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U) | ||
| 5420 | /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped | ||
| 5421 | * receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal | ||
| 5422 | * reception. | ||
| 5423 | */ | ||
| 5424 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK) | ||
| 5425 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U) | ||
| 5426 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U) | ||
| 5427 | /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface. | ||
| 5428 | */ | ||
| 5429 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK) | ||
| 5430 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U) | ||
| 5431 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U) | ||
| 5432 | /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface. | ||
| 5433 | */ | ||
| 5434 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK) | ||
| 5435 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U) | ||
| 5436 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U) | ||
| 5437 | /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. | ||
| 5438 | */ | ||
| 5439 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK) | ||
| 5440 | #define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U) | ||
| 5441 | #define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U) | ||
| 5442 | /*! PLS - PHY Link Status This bit indicates the link status of the PHY. | ||
| 5443 | */ | ||
| 5444 | #define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK) | ||
| 5445 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U) | ||
| 5446 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U) | ||
| 5447 | /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming | ||
| 5448 | * out of the LPI mode on the Transmit side. | ||
| 5449 | */ | ||
| 5450 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK) | ||
| 5451 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U) | ||
| 5452 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U) | ||
| 5453 | /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. | ||
| 5454 | */ | ||
| 5455 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK) | ||
| 5456 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U) | ||
| 5457 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U) | ||
| 5458 | /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating | ||
| 5459 | * Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be | ||
| 5460 | * stopped. | ||
| 5461 | */ | ||
| 5462 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK) | ||
| 5463 | /*! @} */ | ||
| 5464 | |||
| 5465 | /*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */ | ||
| 5466 | /*! @{ */ | ||
| 5467 | #define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU) | ||
| 5468 | #define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U) | ||
| 5469 | /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC | ||
| 5470 | * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal | ||
| 5471 | * transmission. | ||
| 5472 | */ | ||
| 5473 | #define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK) | ||
| 5474 | #define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U) | ||
| 5475 | #define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U) | ||
| 5476 | /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link | ||
| 5477 | * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. | ||
| 5478 | */ | ||
| 5479 | #define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK) | ||
| 5480 | /*! @} */ | ||
| 5481 | |||
| 5482 | /*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */ | ||
| 5483 | /*! @{ */ | ||
| 5484 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U) | ||
| 5485 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U) | ||
| 5486 | /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter | ||
| 5487 | * LPI mode, after it has transmitted all the frames. | ||
| 5488 | */ | ||
| 5489 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK) | ||
| 5490 | /*! @} */ | ||
| 5491 | |||
| 5492 | /*! @name MAC_1US_TIC_COUNTR - */ | ||
| 5493 | /*! @{ */ | ||
| 5494 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU) | ||
| 5495 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U) | ||
| 5496 | /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. | ||
| 5497 | */ | ||
| 5498 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK) | ||
| 5499 | /*! @} */ | ||
| 5500 | |||
| 5501 | /*! @name MAC_VERSION - MAC version register */ | ||
| 5502 | /*! @{ */ | ||
| 5503 | #define ENET_MAC_VERSION_SNPVER_MASK (0xFFU) | ||
| 5504 | #define ENET_MAC_VERSION_SNPVER_SHIFT (0U) | ||
| 5505 | /*! SNPVER - NXP defined version. | ||
| 5506 | */ | ||
| 5507 | #define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK) | ||
| 5508 | #define ENET_MAC_VERSION_USERVER_MASK (0xFF00U) | ||
| 5509 | #define ENET_MAC_VERSION_USERVER_SHIFT (8U) | ||
| 5510 | /*! USERVER - User defined version. | ||
| 5511 | */ | ||
| 5512 | #define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK) | ||
| 5513 | /*! @} */ | ||
| 5514 | |||
| 5515 | /*! @name MAC_DBG - MAC debug register */ | ||
| 5516 | /*! @{ */ | ||
| 5517 | #define ENET_MAC_DBG_REPESTS_MASK (0x1U) | ||
| 5518 | #define ENET_MAC_DBG_REPESTS_SHIFT (0U) | ||
| 5519 | /*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC | ||
| 5520 | * MII receive protocol engine is actively receiving data, and it is not in the Idle state. | ||
| 5521 | */ | ||
| 5522 | #define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK) | ||
| 5523 | #define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U) | ||
| 5524 | #define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U) | ||
| 5525 | /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates | ||
| 5526 | * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet | ||
| 5527 | * Controller module. | ||
| 5528 | */ | ||
| 5529 | #define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK) | ||
| 5530 | #define ENET_MAC_DBG_TPESTS_MASK (0x10000U) | ||
| 5531 | #define ENET_MAC_DBG_TPESTS_SHIFT (16U) | ||
| 5532 | /*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC | ||
| 5533 | * or MII transmit protocol engine is actively transmitting data, and it is not in the Idle | ||
| 5534 | * state. | ||
| 5535 | */ | ||
| 5536 | #define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK) | ||
| 5537 | #define ENET_MAC_DBG_TFCSTS_MASK (0x60000U) | ||
| 5538 | #define ENET_MAC_DBG_TFCSTS_SHIFT (17U) | ||
| 5539 | /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. | ||
| 5540 | */ | ||
| 5541 | #define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK) | ||
| 5542 | /*! @} */ | ||
| 5543 | |||
| 5544 | /*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */ | ||
| 5545 | /*! @{ */ | ||
| 5546 | #define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U) | ||
| 5547 | #define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U) | ||
| 5548 | /*! MIISEL - 10 or 100 Mbps Support. | ||
| 5549 | */ | ||
| 5550 | #define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK) | ||
| 5551 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) | ||
| 5552 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) | ||
| 5553 | /*! RXFIFOSIZE - MTL Receive FIFO Size. | ||
| 5554 | */ | ||
| 5555 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK) | ||
| 5556 | #define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU) | ||
| 5557 | #define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U) | ||
| 5558 | /*! RXQCNT - Number of MTL Receive Queues. | ||
| 5559 | */ | ||
| 5560 | #define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK) | ||
| 5561 | #define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U) | ||
| 5562 | #define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U) | ||
| 5563 | /*! HDSEL - Half-duplex Support. | ||
| 5564 | */ | ||
| 5565 | #define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK) | ||
| 5566 | #define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U) | ||
| 5567 | #define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U) | ||
| 5568 | /*! VLHASH - Hash Table Based Filtering option. | ||
| 5569 | */ | ||
| 5570 | #define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK) | ||
| 5571 | #define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U) | ||
| 5572 | #define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U) | ||
| 5573 | /*! SMASEL - SMA (MDIO) Interface. | ||
| 5574 | */ | ||
| 5575 | #define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK) | ||
| 5576 | #define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U) | ||
| 5577 | #define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U) | ||
| 5578 | /*! RWKSEL - PMT Remote Wake-up Packet Detection. | ||
| 5579 | */ | ||
| 5580 | #define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK) | ||
| 5581 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) | ||
| 5582 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) | ||
| 5583 | /*! TXFIFOSIZE - MTL Transmit FIFO Size. | ||
| 5584 | */ | ||
| 5585 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) | ||
| 5586 | #define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) | ||
| 5587 | #define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U) | ||
| 5588 | /*! TXQCNT - Number of MTL Transmit Queues. | ||
| 5589 | */ | ||
| 5590 | #define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK) | ||
| 5591 | #define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U) | ||
| 5592 | #define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U) | ||
| 5593 | /*! MGKSEL - PMT magic packet detection. | ||
| 5594 | */ | ||
| 5595 | #define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK) | ||
| 5596 | #define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U) | ||
| 5597 | #define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U) | ||
| 5598 | /*! MMCSEL - RMON Module Enable. | ||
| 5599 | */ | ||
| 5600 | #define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK) | ||
| 5601 | #define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) | ||
| 5602 | #define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) | ||
| 5603 | /*! ARPOFFSEL - ARP Offload Enabled. | ||
| 5604 | */ | ||
| 5605 | #define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK) | ||
| 5606 | #define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U) | ||
| 5607 | #define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U) | ||
| 5608 | /*! OSTEN - One-Step Timestamping Feature. | ||
| 5609 | */ | ||
| 5610 | #define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK) | ||
| 5611 | #define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U) | ||
| 5612 | #define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U) | ||
| 5613 | /*! PTOEN - PTP OffLoad Feature. | ||
| 5614 | */ | ||
| 5615 | #define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK) | ||
| 5616 | #define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) | ||
| 5617 | #define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) | ||
| 5618 | /*! RXCHCNT - Number of DMA Receive Channels. | ||
| 5619 | */ | ||
| 5620 | #define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK) | ||
| 5621 | #define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U) | ||
| 5622 | #define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U) | ||
| 5623 | /*! TSSEL - IEEE 1588-2008 Timestamp support . | ||
| 5624 | */ | ||
| 5625 | #define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK) | ||
| 5626 | #define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) | ||
| 5627 | #define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) | ||
| 5628 | /*! ADVTHWORD - IEEE 1588 High Word Register Feature. | ||
| 5629 | */ | ||
| 5630 | #define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK) | ||
| 5631 | #define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U) | ||
| 5632 | #define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U) | ||
| 5633 | /*! EEESEL - Energy Efficient Ethernet Support . | ||
| 5634 | */ | ||
| 5635 | #define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK) | ||
| 5636 | #define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U) | ||
| 5637 | #define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U) | ||
| 5638 | /*! ADDR64 - Address width. | ||
| 5639 | */ | ||
| 5640 | #define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK) | ||
| 5641 | #define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) | ||
| 5642 | #define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) | ||
| 5643 | /*! TXCOESEL - Transmit Checksum Offload Support. | ||
| 5644 | */ | ||
| 5645 | #define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK) | ||
| 5646 | #define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U) | ||
| 5647 | #define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U) | ||
| 5648 | /*! DCBEN - Data Center Bridging feature. | ||
| 5649 | */ | ||
| 5650 | #define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK) | ||
| 5651 | #define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) | ||
| 5652 | #define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) | ||
| 5653 | /*! RXCOESEL - Receive Checksum Offload Support. | ||
| 5654 | */ | ||
| 5655 | #define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK) | ||
| 5656 | #define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U) | ||
| 5657 | #define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U) | ||
| 5658 | /*! SPEN - Split Header Structure feature. | ||
| 5659 | */ | ||
| 5660 | #define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK) | ||
| 5661 | #define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U) | ||
| 5662 | #define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U) | ||
| 5663 | /*! TSOEN - TCP Segment Offload Feature. | ||
| 5664 | */ | ||
| 5665 | #define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK) | ||
| 5666 | #define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) | ||
| 5667 | #define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) | ||
| 5668 | /*! TXCHCNT - Number of DMA Transmit Channels. | ||
| 5669 | */ | ||
| 5670 | #define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK) | ||
| 5671 | #define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) | ||
| 5672 | #define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) | ||
| 5673 | /*! DBGMEMA - DMA Debug Register Feature. | ||
| 5674 | */ | ||
| 5675 | #define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK) | ||
| 5676 | #define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U) | ||
| 5677 | #define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U) | ||
| 5678 | /*! AVSEL - Audio Video Bridging Feature. | ||
| 5679 | */ | ||
| 5680 | #define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK) | ||
| 5681 | #define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U) | ||
| 5682 | #define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U) | ||
| 5683 | /*! LPMODEEN - Low Power Mode Feature Support . | ||
| 5684 | */ | ||
| 5685 | #define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK) | ||
| 5686 | #define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) | ||
| 5687 | #define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) | ||
| 5688 | /*! HASHTBLSZ - Hash Table Size. | ||
| 5689 | */ | ||
| 5690 | #define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK) | ||
| 5691 | #define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) | ||
| 5692 | #define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) | ||
| 5693 | /*! PPSOUTNUM - Number of PPS Outputs. | ||
| 5694 | */ | ||
| 5695 | #define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK) | ||
| 5696 | #define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) | ||
| 5697 | #define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) | ||
| 5698 | /*! TSSTSSEL - Timestamp System Time Source. | ||
| 5699 | */ | ||
| 5700 | #define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK) | ||
| 5701 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U) | ||
| 5702 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U) | ||
| 5703 | /*! L3_L4_FILTER - Total Number of L3 and L4 Filters . | ||
| 5704 | */ | ||
| 5705 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK) | ||
| 5706 | #define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) | ||
| 5707 | #define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) | ||
| 5708 | /*! ACTPHYSEL - Active PHY Selected. | ||
| 5709 | */ | ||
| 5710 | #define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK) | ||
| 5711 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) | ||
| 5712 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) | ||
| 5713 | /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs. | ||
| 5714 | */ | ||
| 5715 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK) | ||
| 5716 | /*! @} */ | ||
| 5717 | |||
| 5718 | /* The count of ENET_MAC_HW_FEAT */ | ||
| 5719 | #define ENET_MAC_HW_FEAT_COUNT (3U) | ||
| 5720 | |||
| 5721 | /*! @name MAC_MDIO_ADDR - MIDO address Register */ | ||
| 5722 | /*! @{ */ | ||
| 5723 | #define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U) | ||
| 5724 | #define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U) | ||
| 5725 | /*! MB - MII busy. | ||
| 5726 | */ | ||
| 5727 | #define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK) | ||
| 5728 | #define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU) | ||
| 5729 | #define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U) | ||
| 5730 | /*! MOC - MII Operation Command. | ||
| 5731 | */ | ||
| 5732 | #define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK) | ||
| 5733 | #define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U) | ||
| 5734 | #define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U) | ||
| 5735 | /*! CR - CSR Clock Range. | ||
| 5736 | */ | ||
| 5737 | #define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK) | ||
| 5738 | #define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U) | ||
| 5739 | #define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U) | ||
| 5740 | /*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles | ||
| 5741 | * generated on MDC after the end of transmission of MDIO frame. | ||
| 5742 | */ | ||
| 5743 | #define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK) | ||
| 5744 | #define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U) | ||
| 5745 | #define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U) | ||
| 5746 | /*! RDA - Register/Device Address These bits select the PHY register in selected PHY device. | ||
| 5747 | */ | ||
| 5748 | #define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK) | ||
| 5749 | #define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U) | ||
| 5750 | #define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U) | ||
| 5751 | /*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing. | ||
| 5752 | */ | ||
| 5753 | #define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK) | ||
| 5754 | #define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U) | ||
| 5755 | #define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U) | ||
| 5756 | /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then | ||
| 5757 | * the MAC will inform the completion of a read or write command at the end of frame transfer | ||
| 5758 | * (before the trailing clocks are transmitted). | ||
| 5759 | */ | ||
| 5760 | #define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK) | ||
| 5761 | #define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U) | ||
| 5762 | #define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U) | ||
| 5763 | /*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit | ||
| 5764 | * preamble and transmit MDIO frames with only 1 preamble bit. | ||
| 5765 | */ | ||
| 5766 | #define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK) | ||
| 5767 | /*! @} */ | ||
| 5768 | |||
| 5769 | /*! @name MAC_MDIO_DATA - MDIO Data register */ | ||
| 5770 | /*! @{ */ | ||
| 5771 | #define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU) | ||
| 5772 | #define ENET_MAC_MDIO_DATA_MD_SHIFT (0U) | ||
| 5773 | /*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management | ||
| 5774 | * Read operation or the 16-bit data value to be written to the PHY before a Management Write | ||
| 5775 | * operation. | ||
| 5776 | */ | ||
| 5777 | #define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK) | ||
| 5778 | /*! @} */ | ||
| 5779 | |||
| 5780 | /*! @name MAC_ADDR_HIGH - MAC address0 high register */ | ||
| 5781 | /*! @{ */ | ||
| 5782 | #define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU) | ||
| 5783 | #define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U) | ||
| 5784 | /*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. | ||
| 5785 | */ | ||
| 5786 | #define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK) | ||
| 5787 | #define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U) | ||
| 5788 | #define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U) | ||
| 5789 | /*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose | ||
| 5790 | * DA matches the MAC Address content is routed. | ||
| 5791 | */ | ||
| 5792 | #define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK) | ||
| 5793 | #define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U) | ||
| 5794 | #define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) | ||
| 5795 | /*! AE - Address Enable. | ||
| 5796 | */ | ||
| 5797 | #define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK) | ||
| 5798 | /*! @} */ | ||
| 5799 | |||
| 5800 | /*! @name MAC_ADDR_LOW - MAC address0 low register */ | ||
| 5801 | /*! @{ */ | ||
| 5802 | #define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU) | ||
| 5803 | #define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U) | ||
| 5804 | /*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. | ||
| 5805 | */ | ||
| 5806 | #define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK) | ||
| 5807 | /*! @} */ | ||
| 5808 | |||
| 5809 | /*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */ | ||
| 5810 | /*! @{ */ | ||
| 5811 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U) | ||
| 5812 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U) | ||
| 5813 | /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. | ||
| 5814 | */ | ||
| 5815 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK) | ||
| 5816 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U) | ||
| 5817 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U) | ||
| 5818 | /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. | ||
| 5819 | */ | ||
| 5820 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK) | ||
| 5821 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U) | ||
| 5822 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U) | ||
| 5823 | /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten) | ||
| 5824 | * with the value specified in the MAC Register 80 (System Time Seconds Update. | ||
| 5825 | */ | ||
| 5826 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK) | ||
| 5827 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U) | ||
| 5828 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U) | ||
| 5829 | /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted) | ||
| 5830 | * with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time | ||
| 5831 | * Nanoseconds Update Table 754. | ||
| 5832 | */ | ||
| 5833 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) | ||
| 5834 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U) | ||
| 5835 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U) | ||
| 5836 | /*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is | ||
| 5837 | * generated when the System Time becomes greater than the value written in the Target Time register. | ||
| 5838 | */ | ||
| 5839 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK) | ||
| 5840 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U) | ||
| 5841 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U) | ||
| 5842 | /*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend | ||
| 5843 | * register is updated in the PTP block for fine correction. | ||
| 5844 | */ | ||
| 5845 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) | ||
| 5846 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U) | ||
| 5847 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U) | ||
| 5848 | /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is | ||
| 5849 | * enabled for all packets received by the MAC. | ||
| 5850 | */ | ||
| 5851 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK) | ||
| 5852 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U) | ||
| 5853 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U) | ||
| 5854 | /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low | ||
| 5855 | * register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments | ||
| 5856 | * the timestamp (High) seconds. | ||
| 5857 | */ | ||
| 5858 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) | ||
| 5859 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U) | ||
| 5860 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U) | ||
| 5861 | /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE | ||
| 5862 | * 1588 version 2 format is used to process the PTP packets. | ||
| 5863 | */ | ||
| 5864 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK) | ||
| 5865 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U) | ||
| 5866 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U) | ||
| 5867 | /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver | ||
| 5868 | * processes the PTP packets encapsulated directly in the Ethernet packets. | ||
| 5869 | */ | ||
| 5870 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK) | ||
| 5871 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U) | ||
| 5872 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U) | ||
| 5873 | /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC | ||
| 5874 | * receiver processes the PTP packets encapsulated in IPv6-UDP packets. | ||
| 5875 | */ | ||
| 5876 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK) | ||
| 5877 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U) | ||
| 5878 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U) | ||
| 5879 | /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC | ||
| 5880 | * receiver processes the PTP packets encapsulated in IPv4-UDP packets. | ||
| 5881 | */ | ||
| 5882 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK) | ||
| 5883 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U) | ||
| 5884 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U) | ||
| 5885 | /*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp | ||
| 5886 | * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). | ||
| 5887 | */ | ||
| 5888 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK) | ||
| 5889 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U) | ||
| 5890 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U) | ||
| 5891 | /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot | ||
| 5892 | * is taken only for the messages that are relevant to the master node. | ||
| 5893 | */ | ||
| 5894 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK) | ||
| 5895 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U) | ||
| 5896 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U) | ||
| 5897 | /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, | ||
| 5898 | * decide the set of PTP packet types for which snapshot needs to be taken. | ||
| 5899 | */ | ||
| 5900 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK) | ||
| 5901 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U) | ||
| 5902 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U) | ||
| 5903 | /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC | ||
| 5904 | * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is | ||
| 5905 | * directly sent over Ethernet. | ||
| 5906 | */ | ||
| 5907 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK) | ||
| 5908 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U) | ||
| 5909 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U) | ||
| 5910 | /*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier | ||
| 5911 | * transmit timestamp status even if it is not read by the software. | ||
| 5912 | */ | ||
| 5913 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK) | ||
| 5914 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U) | ||
| 5915 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U) | ||
| 5916 | /*! AV8021ASMEN - AV 802. | ||
| 5917 | */ | ||
| 5918 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK) | ||
| 5919 | /*! @} */ | ||
| 5920 | |||
| 5921 | /*! @name MAC_SUB_SCND_INCR - Sub-second increment register */ | ||
| 5922 | /*! @{ */ | ||
| 5923 | #define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U) | ||
| 5924 | #define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U) | ||
| 5925 | /*! SSINC - Sub-second increment value. | ||
| 5926 | */ | ||
| 5927 | #define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK) | ||
| 5928 | /*! @} */ | ||
| 5929 | |||
| 5930 | /*! @name MAC_SYS_TIME_SCND - System time seconds register */ | ||
| 5931 | /*! @{ */ | ||
| 5932 | #define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU) | ||
| 5933 | #define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U) | ||
| 5934 | /*! TSS - Time stamp second The value in this field indicates the current value in seconds of the | ||
| 5935 | * System Time maintained by the MAC. | ||
| 5936 | */ | ||
| 5937 | #define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK) | ||
| 5938 | /*! @} */ | ||
| 5939 | |||
| 5940 | /*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */ | ||
| 5941 | /*! @{ */ | ||
| 5942 | #define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU) | ||
| 5943 | #define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U) | ||
| 5944 | /*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0. | ||
| 5945 | */ | ||
| 5946 | #define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK) | ||
| 5947 | /*! @} */ | ||
| 5948 | |||
| 5949 | /*! @name MAC_SYS_TIME_SCND_UPD - */ | ||
| 5950 | /*! @{ */ | ||
| 5951 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU) | ||
| 5952 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U) | ||
| 5953 | /*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time. | ||
| 5954 | */ | ||
| 5955 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK) | ||
| 5956 | /*! @} */ | ||
| 5957 | |||
| 5958 | /*! @name MAC_SYS_TIME_NSCND_UPD - */ | ||
| 5959 | /*! @{ */ | ||
| 5960 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU) | ||
| 5961 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U) | ||
| 5962 | /*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0. | ||
| 5963 | */ | ||
| 5964 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK) | ||
| 5965 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U) | ||
| 5966 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U) | ||
| 5967 | /*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. | ||
| 5968 | */ | ||
| 5969 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK) | ||
| 5970 | /*! @} */ | ||
| 5971 | |||
| 5972 | /*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */ | ||
| 5973 | /*! @{ */ | ||
| 5974 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) | ||
| 5975 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U) | ||
| 5976 | /*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the | ||
| 5977 | * Accumulator register to achieve time synchronization. | ||
| 5978 | */ | ||
| 5979 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK) | ||
| 5980 | /*! @} */ | ||
| 5981 | |||
| 5982 | /*! @name MAC_SYS_TIME_HWORD_SCND - */ | ||
| 5983 | /*! @{ */ | ||
| 5984 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU) | ||
| 5985 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U) | ||
| 5986 | /*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. | ||
| 5987 | */ | ||
| 5988 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) | ||
| 5989 | /*! @} */ | ||
| 5990 | |||
| 5991 | /*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */ | ||
| 5992 | /*! @{ */ | ||
| 5993 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U) | ||
| 5994 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U) | ||
| 5995 | /*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time | ||
| 5996 | * stamp has overflowed beyond 0xFFFF_FFFF. | ||
| 5997 | */ | ||
| 5998 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK) | ||
| 5999 | /*! @} */ | ||
| 6000 | |||
| 6001 | /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */ | ||
| 6002 | /*! @{ */ | ||
| 6003 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU) | ||
| 6004 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U) | ||
| 6005 | /*! TXTSSTSLO - Transmit timestamp status low. | ||
| 6006 | */ | ||
| 6007 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK) | ||
| 6008 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U) | ||
| 6009 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U) | ||
| 6010 | /*! TXTSSTSMIS - Transmit timestamp status missed. | ||
| 6011 | */ | ||
| 6012 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK) | ||
| 6013 | /*! @} */ | ||
| 6014 | |||
| 6015 | /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */ | ||
| 6016 | /*! @{ */ | ||
| 6017 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU) | ||
| 6018 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U) | ||
| 6019 | /*! TXTSSTSHI - Transmit timestamp status high. | ||
| 6020 | */ | ||
| 6021 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK) | ||
| 6022 | /*! @} */ | ||
| 6023 | |||
| 6024 | /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */ | ||
| 6025 | /*! @{ */ | ||
| 6026 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) | ||
| 6027 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) | ||
| 6028 | /*! TSIC - Transmit ingress correction. | ||
| 6029 | */ | ||
| 6030 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) | ||
| 6031 | /*! @} */ | ||
| 6032 | |||
| 6033 | /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */ | ||
| 6034 | /*! @{ */ | ||
| 6035 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) | ||
| 6036 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) | ||
| 6037 | /*! TSEC - Transmit egress correction. | ||
| 6038 | */ | ||
| 6039 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) | ||
| 6040 | /*! @} */ | ||
| 6041 | |||
| 6042 | /*! @name MTL_OP_MODE - MTL Operation Mode Register */ | ||
| 6043 | /*! @{ */ | ||
| 6044 | #define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U) | ||
| 6045 | #define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U) | ||
| 6046 | /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. | ||
| 6047 | */ | ||
| 6048 | #define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK) | ||
| 6049 | #define ENET_MTL_OP_MODE_RAA_MASK (0x4U) | ||
| 6050 | #define ENET_MTL_OP_MODE_RAA_SHIFT (2U) | ||
| 6051 | /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. | ||
| 6052 | */ | ||
| 6053 | #define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK) | ||
| 6054 | #define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U) | ||
| 6055 | #define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U) | ||
| 6056 | /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR | ||
| 6057 | * algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm. | ||
| 6058 | */ | ||
| 6059 | #define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK) | ||
| 6060 | #define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U) | ||
| 6061 | #define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U) | ||
| 6062 | /*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and | ||
| 6063 | * MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0. | ||
| 6064 | */ | ||
| 6065 | #define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK) | ||
| 6066 | #define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U) | ||
| 6067 | #define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U) | ||
| 6068 | /*! CNTCLR - Counters Reset When this bit is set, all counters are reset. | ||
| 6069 | */ | ||
| 6070 | #define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK) | ||
| 6071 | /*! @} */ | ||
| 6072 | |||
| 6073 | /*! @name MTL_INTR_STAT - MTL Interrupt Status register */ | ||
| 6074 | /*! @{ */ | ||
| 6075 | #define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U) | ||
| 6076 | #define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U) | ||
| 6077 | /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. | ||
| 6078 | */ | ||
| 6079 | #define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK) | ||
| 6080 | #define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U) | ||
| 6081 | #define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U) | ||
| 6082 | /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. | ||
| 6083 | */ | ||
| 6084 | #define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK) | ||
| 6085 | /*! @} */ | ||
| 6086 | |||
| 6087 | /*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */ | ||
| 6088 | /*! @{ */ | ||
| 6089 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U) | ||
| 6090 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U) | ||
| 6091 | /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received | ||
| 6092 | * in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the | ||
| 6093 | * Q0DDMACH field is reset. | ||
| 6094 | */ | ||
| 6095 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK) | ||
| 6096 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U) | ||
| 6097 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U) | ||
| 6098 | /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that | ||
| 6099 | * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC | ||
| 6100 | * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the | ||
| 6101 | * Ethernet DA address. | ||
| 6102 | */ | ||
| 6103 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK) | ||
| 6104 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U) | ||
| 6105 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U) | ||
| 6106 | /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet | ||
| 6107 | * in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the | ||
| 6108 | * Q1DDMACH field is reset. | ||
| 6109 | */ | ||
| 6110 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK) | ||
| 6111 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U) | ||
| 6112 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U) | ||
| 6113 | /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that | ||
| 6114 | * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC | ||
| 6115 | * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the | ||
| 6116 | * Ethernet DA address. | ||
| 6117 | */ | ||
| 6118 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK) | ||
| 6119 | /*! @} */ | ||
| 6120 | |||
| 6121 | /*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */ | ||
| 6122 | /*! @{ */ | ||
| 6123 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) | ||
| 6124 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) | ||
| 6125 | /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. | ||
| 6126 | */ | ||
| 6127 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK) | ||
| 6128 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) | ||
| 6129 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) | ||
| 6130 | /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. | ||
| 6131 | */ | ||
| 6132 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK) | ||
| 6133 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) | ||
| 6134 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) | ||
| 6135 | /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0. | ||
| 6136 | */ | ||
| 6137 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK) | ||
| 6138 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) | ||
| 6139 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) | ||
| 6140 | /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. | ||
| 6141 | */ | ||
| 6142 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK) | ||
| 6143 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U) | ||
| 6144 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) | ||
| 6145 | /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. | ||
| 6146 | */ | ||
| 6147 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK) | ||
| 6148 | /*! @} */ | ||
| 6149 | |||
| 6150 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */ | ||
| 6151 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U) | ||
| 6152 | |||
| 6153 | /*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */ | ||
| 6154 | /*! @{ */ | ||
| 6155 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) | ||
| 6156 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) | ||
| 6157 | /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the | ||
| 6158 | * controller because of Tx Queue Underflow. | ||
| 6159 | */ | ||
| 6160 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) | ||
| 6161 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) | ||
| 6162 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) | ||
| 6163 | /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue | ||
| 6164 | * Underflow Packet Counter field overflows, that is, it has crossed the maximum count. | ||
| 6165 | */ | ||
| 6166 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) | ||
| 6167 | /*! @} */ | ||
| 6168 | |||
| 6169 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */ | ||
| 6170 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U) | ||
| 6171 | |||
| 6172 | /*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */ | ||
| 6173 | /*! @{ */ | ||
| 6174 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) | ||
| 6175 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) | ||
| 6176 | /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it | ||
| 6177 | * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because | ||
| 6178 | * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue | ||
| 6179 | * when PFC is enabled - Reception of 802. | ||
| 6180 | */ | ||
| 6181 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK) | ||
| 6182 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) | ||
| 6183 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) | ||
| 6184 | /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read | ||
| 6185 | * Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10: | ||
| 6186 | * Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the | ||
| 6187 | * Packet Abort request from the MAC. | ||
| 6188 | */ | ||
| 6189 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK) | ||
| 6190 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) | ||
| 6191 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) | ||
| 6192 | /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx | ||
| 6193 | * Queue Write Controller is active, and it is transferring the data to the Tx Queue. | ||
| 6194 | */ | ||
| 6195 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK) | ||
| 6196 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) | ||
| 6197 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) | ||
| 6198 | /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue | ||
| 6199 | * is not empty and some data is left for transmission. | ||
| 6200 | */ | ||
| 6201 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK) | ||
| 6202 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) | ||
| 6203 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) | ||
| 6204 | /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. | ||
| 6205 | */ | ||
| 6206 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK) | ||
| 6207 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) | ||
| 6208 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U) | ||
| 6209 | /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. | ||
| 6210 | */ | ||
| 6211 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK) | ||
| 6212 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U) | ||
| 6213 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U) | ||
| 6214 | /*! STSXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current | ||
| 6215 | * number of status in the Tx Status FIFO of this queue. | ||
| 6216 | */ | ||
| 6217 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK) | ||
| 6218 | /*! @} */ | ||
| 6219 | |||
| 6220 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */ | ||
| 6221 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U) | ||
| 6222 | |||
| 6223 | /*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */ | ||
| 6224 | /*! @{ */ | ||
| 6225 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) | ||
| 6226 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) | ||
| 6227 | /*! AVALG - AV Algorithm. | ||
| 6228 | */ | ||
| 6229 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK) | ||
| 6230 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) | ||
| 6231 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) | ||
| 6232 | /*! CC - Credit Control. | ||
| 6233 | */ | ||
| 6234 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK) | ||
| 6235 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) | ||
| 6236 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) | ||
| 6237 | /*! SLC - Credit Control. | ||
| 6238 | */ | ||
| 6239 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK) | ||
| 6240 | /*! @} */ | ||
| 6241 | |||
| 6242 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */ | ||
| 6243 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U) | ||
| 6244 | |||
| 6245 | /*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */ | ||
| 6246 | /*! @{ */ | ||
| 6247 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) | ||
| 6248 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) | ||
| 6249 | /*! ABS - Average Bits per Slot. | ||
| 6250 | */ | ||
| 6251 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK) | ||
| 6252 | /*! @} */ | ||
| 6253 | |||
| 6254 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */ | ||
| 6255 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U) | ||
| 6256 | |||
| 6257 | /*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */ | ||
| 6258 | /*! @{ */ | ||
| 6259 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) | ||
| 6260 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) | ||
| 6261 | /*! ISCQW - Average Bits per Slot. | ||
| 6262 | */ | ||
| 6263 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) | ||
| 6264 | /*! @} */ | ||
| 6265 | |||
| 6266 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */ | ||
| 6267 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U) | ||
| 6268 | |||
| 6269 | /*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */ | ||
| 6270 | /*! @{ */ | ||
| 6271 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) | ||
| 6272 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) | ||
| 6273 | /*! SSC - sendSlopeCredit. | ||
| 6274 | */ | ||
| 6275 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) | ||
| 6276 | /*! @} */ | ||
| 6277 | |||
| 6278 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */ | ||
| 6279 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) | ||
| 6280 | |||
| 6281 | /*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */ | ||
| 6282 | /*! @{ */ | ||
| 6283 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) | ||
| 6284 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) | ||
| 6285 | /*! HC - hiCredit. | ||
| 6286 | */ | ||
| 6287 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK) | ||
| 6288 | /*! @} */ | ||
| 6289 | |||
| 6290 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */ | ||
| 6291 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U) | ||
| 6292 | |||
| 6293 | /*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */ | ||
| 6294 | /*! @{ */ | ||
| 6295 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) | ||
| 6296 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) | ||
| 6297 | /*! LC - loCredit. | ||
| 6298 | */ | ||
| 6299 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK) | ||
| 6300 | /*! @} */ | ||
| 6301 | |||
| 6302 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */ | ||
| 6303 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U) | ||
| 6304 | |||
| 6305 | /*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */ | ||
| 6306 | /*! @{ */ | ||
| 6307 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) | ||
| 6308 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) | ||
| 6309 | /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue | ||
| 6310 | * had an underflow while transmitting the packet. | ||
| 6311 | */ | ||
| 6312 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) | ||
| 6313 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) | ||
| 6314 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) | ||
| 6315 | /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. | ||
| 6316 | */ | ||
| 6317 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) | ||
| 6318 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) | ||
| 6319 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) | ||
| 6320 | /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. | ||
| 6321 | */ | ||
| 6322 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) | ||
| 6323 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) | ||
| 6324 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) | ||
| 6325 | /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the | ||
| 6326 | * interrupt when the average bits per slot status is updated. | ||
| 6327 | */ | ||
| 6328 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) | ||
| 6329 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) | ||
| 6330 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) | ||
| 6331 | /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had | ||
| 6332 | * an overflow while receiving the packet. | ||
| 6333 | */ | ||
| 6334 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) | ||
| 6335 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) | ||
| 6336 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) | ||
| 6337 | /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. | ||
| 6338 | */ | ||
| 6339 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) | ||
| 6340 | /*! @} */ | ||
| 6341 | |||
| 6342 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */ | ||
| 6343 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U) | ||
| 6344 | |||
| 6345 | /*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */ | ||
| 6346 | /*! @{ */ | ||
| 6347 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) | ||
| 6348 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) | ||
| 6349 | /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue | ||
| 6350 | * (in bytes): 00: 64 01: 32 10: 96 11: 128 The packet received is transferred to the | ||
| 6351 | * application or DMA when the packet size within the MTL Rx queue is larger than the threshold. | ||
| 6352 | */ | ||
| 6353 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK) | ||
| 6354 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) | ||
| 6355 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) | ||
| 6356 | /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized | ||
| 6357 | * good packets (packets with no error and length less than 64 bytes), including pad-bytes and | ||
| 6358 | * CRC. | ||
| 6359 | */ | ||
| 6360 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK) | ||
| 6361 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) | ||
| 6362 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) | ||
| 6363 | /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status | ||
| 6364 | * (CRC error, Mll_ER, watchdog timeout, or overflow). | ||
| 6365 | */ | ||
| 6366 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK) | ||
| 6367 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) | ||
| 6368 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) | ||
| 6369 | /*! RSF - Receive Queue Store and Forward When this bit is set, the ethernet block on this chip | ||
| 6370 | * reads a packet from the Rx queue only after the complete packet has been written to it, ignoring | ||
| 6371 | * the RTC field of this register. | ||
| 6372 | */ | ||
| 6373 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK) | ||
| 6374 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) | ||
| 6375 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) | ||
| 6376 | /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC | ||
| 6377 | * does not drop the packets which only have the errors detected by the Receive Checksum Offload | ||
| 6378 | * engine. | ||
| 6379 | */ | ||
| 6380 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) | ||
| 6381 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U) | ||
| 6382 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) | ||
| 6383 | /*! RQS - This field indicates the size of the allocated Receive queues in blocks of 256 bytes. | ||
| 6384 | */ | ||
| 6385 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK) | ||
| 6386 | /*! @} */ | ||
| 6387 | |||
| 6388 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */ | ||
| 6389 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U) | ||
| 6390 | |||
| 6391 | /*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */ | ||
| 6392 | /*! @{ */ | ||
| 6393 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) | ||
| 6394 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) | ||
| 6395 | /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the | ||
| 6396 | * Ethernet block because of Receive queue overflow. | ||
| 6397 | */ | ||
| 6398 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) | ||
| 6399 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) | ||
| 6400 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) | ||
| 6401 | /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue | ||
| 6402 | * Overflow Packet Counter field crossed the maximum limit. | ||
| 6403 | */ | ||
| 6404 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) | ||
| 6405 | /*! @} */ | ||
| 6406 | |||
| 6407 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */ | ||
| 6408 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) | ||
| 6409 | |||
| 6410 | /*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */ | ||
| 6411 | /*! @{ */ | ||
| 6412 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) | ||
| 6413 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) | ||
| 6414 | /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL | ||
| 6415 | * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. | ||
| 6416 | */ | ||
| 6417 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK) | ||
| 6418 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) | ||
| 6419 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) | ||
| 6420 | /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read | ||
| 6421 | * controller: 00: Idle state 01: Reading packet data 10: Reading packet status (or timestamp) 11: | ||
| 6422 | * Flushing the packet data and status. | ||
| 6423 | */ | ||
| 6424 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK) | ||
| 6425 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) | ||
| 6426 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) | ||
| 6427 | /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx | ||
| 6428 | * Queue: 0x0: Rx Queue empty 0x1: Rx Queue fill-level below flow-control deactivate threshold | ||
| 6429 | * 0x2: Rx Queue fill-level above flow-control activate threshold 0x3: Rx Queue full. | ||
| 6430 | */ | ||
| 6431 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK) | ||
| 6432 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) | ||
| 6433 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U) | ||
| 6434 | /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. | ||
| 6435 | */ | ||
| 6436 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK) | ||
| 6437 | /*! @} */ | ||
| 6438 | |||
| 6439 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */ | ||
| 6440 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U) | ||
| 6441 | |||
| 6442 | /*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */ | ||
| 6443 | /*! @{ */ | ||
| 6444 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) | ||
| 6445 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) | ||
| 6446 | /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. | ||
| 6447 | */ | ||
| 6448 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK) | ||
| 6449 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) | ||
| 6450 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) | ||
| 6451 | /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the The ethernet block | ||
| 6452 | * drives the packet data to the ARI interface such that the entire packet data of | ||
| 6453 | * currently-selected queue is transmitted before switching to other queue. | ||
| 6454 | */ | ||
| 6455 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) | ||
| 6456 | /*! @} */ | ||
| 6457 | |||
| 6458 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */ | ||
| 6459 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U) | ||
| 6460 | |||
| 6461 | /*! @name DMA_MODE - DMA mode register */ | ||
| 6462 | /*! @{ */ | ||
| 6463 | #define ENET_DMA_MODE_SWR_MASK (0x1U) | ||
| 6464 | #define ENET_DMA_MODE_SWR_SHIFT (0U) | ||
| 6465 | /*! SWR - Software Reset When this bit is set, the MAC and the OMA controller reset the logic and | ||
| 6466 | * all internal registers of the OMA, MTL, and MAC. | ||
| 6467 | */ | ||
| 6468 | #define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK) | ||
| 6469 | #define ENET_DMA_MODE_DA_MASK (0x2U) | ||
| 6470 | #define ENET_DMA_MODE_DA_SHIFT (1U) | ||
| 6471 | /*! DA - DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the | ||
| 6472 | * Transmit and Receive paths of all channels: The Tx path has priority over the Rx path when the TXPR | ||
| 6473 | * bit is set. | ||
| 6474 | */ | ||
| 6475 | #define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK) | ||
| 6476 | #define ENET_DMA_MODE_TAA_MASK (0x1CU) | ||
| 6477 | #define ENET_DMA_MODE_TAA_SHIFT (2U) | ||
| 6478 | /*! TAA - Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for | ||
| 6479 | * the Transmit side when multiple Tx DMAs are selected. | ||
| 6480 | */ | ||
| 6481 | #define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK) | ||
| 6482 | #define ENET_DMA_MODE_TXPR_MASK (0x800U) | ||
| 6483 | #define ENET_DMA_MODE_TXPR_SHIFT (11U) | ||
| 6484 | /*! TXPR - Transmit Priority When set, this bit indicates that the Tx DMA has higher priority than | ||
| 6485 | * the Rx DMA during arbitration for the system-side bus. | ||
| 6486 | */ | ||
| 6487 | #define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK) | ||
| 6488 | #define ENET_DMA_MODE_PR_MASK (0x7000U) | ||
| 6489 | #define ENET_DMA_MODE_PR_SHIFT (12U) | ||
| 6490 | /*! PR - Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. | ||
| 6491 | */ | ||
| 6492 | #define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK) | ||
| 6493 | /*! @} */ | ||
| 6494 | |||
| 6495 | /*! @name DMA_SYSBUS_MODE - DMA System Bus mode */ | ||
| 6496 | /*! @{ */ | ||
| 6497 | #define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U) | ||
| 6498 | #define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U) | ||
| 6499 | /*! FB - Fixed Burst Length When this bit is set to 1, the AHB master will initiate burst transfers | ||
| 6500 | * of specified length (INCRx or SINGLE). | ||
| 6501 | */ | ||
| 6502 | #define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK) | ||
| 6503 | #define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) | ||
| 6504 | #define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U) | ||
| 6505 | /*! AAL - Address-Aligned Beats When this bit is set to 1, the AHB master performs address-aligned | ||
| 6506 | * burst transfers on Read and Write channels. | ||
| 6507 | */ | ||
| 6508 | #define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK) | ||
| 6509 | #define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U) | ||
| 6510 | #define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U) | ||
| 6511 | /*! MB - Mixed Burst When this bit is set high and the FB bit is low, the AHB master performs | ||
| 6512 | * undefined bursts transfers (INCR) for burst length of 16 or more. | ||
| 6513 | */ | ||
| 6514 | #define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK) | ||
| 6515 | #define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U) | ||
| 6516 | #define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U) | ||
| 6517 | /*! RB - Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT, RETRY, or | ||
| 6518 | * EarlyBurst Termination (EBT) response, the AHB master interface rebuilds the pending beats of any | ||
| 6519 | * initiated burst transfer with INCRx and SINGLEtransfers. | ||
| 6520 | */ | ||
| 6521 | #define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK) | ||
| 6522 | /*! @} */ | ||
| 6523 | |||
| 6524 | /*! @name DMA_INTR_STAT - DMA Interrupt status */ | ||
| 6525 | /*! @{ */ | ||
| 6526 | #define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U) | ||
| 6527 | #define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U) | ||
| 6528 | /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. | ||
| 6529 | */ | ||
| 6530 | #define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK) | ||
| 6531 | #define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U) | ||
| 6532 | #define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U) | ||
| 6533 | /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. | ||
| 6534 | */ | ||
| 6535 | #define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK) | ||
| 6536 | #define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U) | ||
| 6537 | #define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U) | ||
| 6538 | /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL. | ||
| 6539 | */ | ||
| 6540 | #define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK) | ||
| 6541 | #define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U) | ||
| 6542 | #define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U) | ||
| 6543 | /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC. | ||
| 6544 | */ | ||
| 6545 | #define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK) | ||
| 6546 | /*! @} */ | ||
| 6547 | |||
| 6548 | /*! @name DMA_DBG_STAT - DMA Debug Status */ | ||
| 6549 | /*! @{ */ | ||
| 6550 | #define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U) | ||
| 6551 | #define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U) | ||
| 6552 | /*! AHSTS - AHB Master Status When high, this bit indicates that the AHB master FSMs are in the non-idle state. | ||
| 6553 | */ | ||
| 6554 | #define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK) | ||
| 6555 | #define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U) | ||
| 6556 | #define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U) | ||
| 6557 | /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel | ||
| 6558 | * 0: 0x0: Stopped (Reset or Stop Receive Command issued) 0x1: Running (Fetching Rx Transfer ) | ||
| 6559 | * 0x2: Reserved 0x3: Running (Waiting for Rx packet) 0x4: Suspended (Rx Unavailable) 0x5: Running | ||
| 6560 | * (Closing the Rx) 0x6: Timestamp write state 0x7: Running (Transferring the received packet | ||
| 6561 | * data from the Rx buffer to the system memory) This field does not generate an interrupt. | ||
| 6562 | */ | ||
| 6563 | #define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK) | ||
| 6564 | #define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U) | ||
| 6565 | #define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U) | ||
| 6566 | /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for | ||
| 6567 | * Channel 0: 000: Stopped (Reset or Stop Transmit Command issued) 0x1: Running (Fetching Tx Transfer) | ||
| 6568 | * 0x2: Running (Waiting for status) 0x3: Running (Reading Data from system memory buffer and | ||
| 6569 | * queuing it to the Tx buffer (Tx FIFO)) 0x4: Timestamp write state 0x5: Reserved for future use | ||
| 6570 | * 0x6: Suspended (Tx Unavailable or Tx Buffer Underflow) 0x7: Running (Closing Tx ) This field | ||
| 6571 | * does not generate an interrupt. | ||
| 6572 | */ | ||
| 6573 | #define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK) | ||
| 6574 | #define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U) | ||
| 6575 | #define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U) | ||
| 6576 | /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. | ||
| 6577 | */ | ||
| 6578 | #define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK) | ||
| 6579 | #define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U) | ||
| 6580 | #define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U) | ||
| 6581 | /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. | ||
| 6582 | */ | ||
| 6583 | #define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK) | ||
| 6584 | /*! @} */ | ||
| 6585 | |||
| 6586 | /*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */ | ||
| 6587 | /*! @{ */ | ||
| 6588 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) | ||
| 6589 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U) | ||
| 6590 | /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in DMA Channel | ||
| 6591 | * Transmit Control Table 780 is multiplied eight times. | ||
| 6592 | */ | ||
| 6593 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) | ||
| 6594 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) | ||
| 6595 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U) | ||
| 6596 | /*! DSL - Skip Length This bit specifies the Word, Dword, or Lword number (depending on the 32- bit, | ||
| 6597 | * 64-bit, or 128-bit bus) to skip between two unchained s. | ||
| 6598 | */ | ||
| 6599 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK) | ||
| 6600 | /*! @} */ | ||
| 6601 | |||
| 6602 | /* The count of ENET_DMA_CH_DMA_CHX_CTRL */ | ||
| 6603 | #define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U) | ||
| 6604 | |||
| 6605 | /*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */ | ||
| 6606 | /*! @{ */ | ||
| 6607 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U) | ||
| 6608 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U) | ||
| 6609 | /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. | ||
| 6610 | */ | ||
| 6611 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK) | ||
| 6612 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) | ||
| 6613 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) | ||
| 6614 | /*! TCW - Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel. | ||
| 6615 | */ | ||
| 6616 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK) | ||
| 6617 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) | ||
| 6618 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) | ||
| 6619 | /*! OSF - Operate on Second Frame When this bit is set, it instructs the DMA to process the second | ||
| 6620 | * packet of the Transmit data even before the status for the first packet is obtained. | ||
| 6621 | */ | ||
| 6622 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK) | ||
| 6623 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) | ||
| 6624 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) | ||
| 6625 | /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be | ||
| 6626 | * transferred in one DMA data transfer. | ||
| 6627 | */ | ||
| 6628 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) | ||
| 6629 | /*! @} */ | ||
| 6630 | |||
| 6631 | /* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */ | ||
| 6632 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U) | ||
| 6633 | |||
| 6634 | /*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */ | ||
| 6635 | /*! @{ */ | ||
| 6636 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U) | ||
| 6637 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U) | ||
| 6638 | /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the from the receive | ||
| 6639 | * list and processes the incoming packets. | ||
| 6640 | */ | ||
| 6641 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK) | ||
| 6642 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U) | ||
| 6643 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U) | ||
| 6644 | /*! RBSZ - Receive Buffer size This field indicates the size of the Rx buffers specified in bytes. | ||
| 6645 | */ | ||
| 6646 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK) | ||
| 6647 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) | ||
| 6648 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) | ||
| 6649 | /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be | ||
| 6650 | * transferred in one DMA data transfer. | ||
| 6651 | */ | ||
| 6652 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK) | ||
| 6653 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) | ||
| 6654 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) | ||
| 6655 | /*! RPF - DMA Rx Channel 0 Packet Flush When this bit is set to 1, the DMA will automatically flush | ||
| 6656 | * the packet from the Rx Queues destined to DMA Rx Channel 0 when the DMA Rx Channel 0 is | ||
| 6657 | * stopped after a system bus error has occurred. | ||
| 6658 | */ | ||
| 6659 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK) | ||
| 6660 | /*! @} */ | ||
| 6661 | |||
| 6662 | /* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */ | ||
| 6663 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U) | ||
| 6664 | |||
| 6665 | /*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */ | ||
| 6666 | /*! @{ */ | ||
| 6667 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU) | ||
| 6668 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U) | ||
| 6669 | /*! STL - Start of transmit list This field contains the base address of the first in the Transmit list. | ||
| 6670 | */ | ||
| 6671 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK) | ||
| 6672 | /*! @} */ | ||
| 6673 | |||
| 6674 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */ | ||
| 6675 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) | ||
| 6676 | |||
| 6677 | /*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */ | ||
| 6678 | /*! @{ */ | ||
| 6679 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU) | ||
| 6680 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U) | ||
| 6681 | /*! SRL - Start of receive list This field contains the base address of the First in the Receive list. | ||
| 6682 | */ | ||
| 6683 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK) | ||
| 6684 | /*! @} */ | ||
| 6685 | |||
| 6686 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */ | ||
| 6687 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) | ||
| 6688 | |||
| 6689 | /*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */ | ||
| 6690 | /*! @{ */ | ||
| 6691 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) | ||
| 6692 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) | ||
| 6693 | /*! TDTP - Transmit Tail Pointer This field contains the tail pointer for the Tx ring. | ||
| 6694 | */ | ||
| 6695 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) | ||
| 6696 | /*! @} */ | ||
| 6697 | |||
| 6698 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */ | ||
| 6699 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) | ||
| 6700 | |||
| 6701 | /*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */ | ||
| 6702 | /*! @{ */ | ||
| 6703 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) | ||
| 6704 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) | ||
| 6705 | /*! RDTP - Receive Tail Pointer This field contains the tail pointer for the Rx ring. | ||
| 6706 | */ | ||
| 6707 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) | ||
| 6708 | /*! @} */ | ||
| 6709 | |||
| 6710 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */ | ||
| 6711 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) | ||
| 6712 | |||
| 6713 | /*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */ | ||
| 6714 | /*! @{ */ | ||
| 6715 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) | ||
| 6716 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) | ||
| 6717 | /*! TDRL - Transmit Ring Length This field sets the maximum number of Tx descriptors in the circular ring. | ||
| 6718 | */ | ||
| 6719 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) | ||
| 6720 | /*! @} */ | ||
| 6721 | |||
| 6722 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */ | ||
| 6723 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) | ||
| 6724 | |||
| 6725 | /*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */ | ||
| 6726 | /*! @{ */ | ||
| 6727 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) | ||
| 6728 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) | ||
| 6729 | /*! RDRL - Receive Ring Length This register sets the maximum number of Rx descriptors in the circular ring. | ||
| 6730 | */ | ||
| 6731 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK) | ||
| 6732 | /*! @} */ | ||
| 6733 | |||
| 6734 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */ | ||
| 6735 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U) | ||
| 6736 | |||
| 6737 | /*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */ | ||
| 6738 | /*! @{ */ | ||
| 6739 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) | ||
| 6740 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U) | ||
| 6741 | /*! TIE - Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit | ||
| 6742 | * 16 in this register), Transmit Interrupt is enabled. | ||
| 6743 | */ | ||
| 6744 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) | ||
| 6745 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U) | ||
| 6746 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U) | ||
| 6747 | /*! TSE - Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit | ||
| 6748 | * 15 in this register), Transmission Stopped Interrupt is enabled. | ||
| 6749 | */ | ||
| 6750 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK) | ||
| 6751 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U) | ||
| 6752 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U) | ||
| 6753 | /*! TBUE - Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary | ||
| 6754 | * Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. | ||
| 6755 | */ | ||
| 6756 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK) | ||
| 6757 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U) | ||
| 6758 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U) | ||
| 6759 | /*! RIE - Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 | ||
| 6760 | * in this register), Receive Interrupt is enabled. | ||
| 6761 | */ | ||
| 6762 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) | ||
| 6763 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U) | ||
| 6764 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U) | ||
| 6765 | /*! RBUE - Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary | ||
| 6766 | * Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. | ||
| 6767 | */ | ||
| 6768 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK) | ||
| 6769 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U) | ||
| 6770 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U) | ||
| 6771 | /*! RSE - Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit | ||
| 6772 | * 15 in this register), Receive Stopped Interrupt is enabled. | ||
| 6773 | */ | ||
| 6774 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK) | ||
| 6775 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U) | ||
| 6776 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U) | ||
| 6777 | /*! RWTE - Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary | ||
| 6778 | * Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. | ||
| 6779 | */ | ||
| 6780 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK) | ||
| 6781 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U) | ||
| 6782 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U) | ||
| 6783 | /*! ETIE - Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary | ||
| 6784 | * Enable (bit 15 in this register), Early Transmit Interrupt is enabled. | ||
| 6785 | */ | ||
| 6786 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) | ||
| 6787 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U) | ||
| 6788 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U) | ||
| 6789 | /*! ERIE - Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable | ||
| 6790 | * (bit 16 in this register), Early Receive Interrupt is enabled. | ||
| 6791 | */ | ||
| 6792 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) | ||
| 6793 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) | ||
| 6794 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U) | ||
| 6795 | /*! FBEE - Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit | ||
| 6796 | * 15 in this register), the Fatal Bus Error Interrupt is enabled. | ||
| 6797 | */ | ||
| 6798 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK) | ||
| 6799 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U) | ||
| 6800 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U) | ||
| 6801 | /*! AIE - Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt summary is enabled. | ||
| 6802 | */ | ||
| 6803 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK) | ||
| 6804 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U) | ||
| 6805 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U) | ||
| 6806 | /*! NIE - Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. | ||
| 6807 | */ | ||
| 6808 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK) | ||
| 6809 | /*! @} */ | ||
| 6810 | |||
| 6811 | /* The count of ENET_DMA_CH_DMA_CHX_INT_EN */ | ||
| 6812 | #define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U) | ||
| 6813 | |||
| 6814 | /*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */ | ||
| 6815 | /*! @{ */ | ||
| 6816 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU) | ||
| 6817 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U) | ||
| 6818 | /*! RIWT - Receive Interrupt Watchdog Timer Count Indicates the number of system clock cycles | ||
| 6819 | * multiplied by 256 for which the watchdog timer is set. | ||
| 6820 | */ | ||
| 6821 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK) | ||
| 6822 | /*! @} */ | ||
| 6823 | |||
| 6824 | /* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */ | ||
| 6825 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) | ||
| 6826 | |||
| 6827 | /*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */ | ||
| 6828 | /*! @{ */ | ||
| 6829 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) | ||
| 6830 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) | ||
| 6831 | /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers | ||
| 6832 | * programmed in the Tx descriptor with the current reference given in the RSN field. | ||
| 6833 | */ | ||
| 6834 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) | ||
| 6835 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) | ||
| 6836 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) | ||
| 6837 | /*! ASC - Advance Slot Check When set, this bit enables the D MA to fetch the data from the buffer | ||
| 6838 | * when the slot number (SLOTNUM) programmed in the Tx descriptor is equal to the reference slot | ||
| 6839 | * number given in the RSN field or, ahead of the reference slot number by up to two slots This | ||
| 6840 | * bit is applicable only when the ESC bit is set. | ||
| 6841 | */ | ||
| 6842 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) | ||
| 6843 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) | ||
| 6844 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) | ||
| 6845 | /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. | ||
| 6846 | */ | ||
| 6847 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) | ||
| 6848 | /*! @} */ | ||
| 6849 | |||
| 6850 | /* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */ | ||
| 6851 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) | ||
| 6852 | |||
| 6853 | /*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */ | ||
| 6854 | /*! @{ */ | ||
| 6855 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU) | ||
| 6856 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U) | ||
| 6857 | /*! HTD - Host Transmit descriptor Address Pointer Cleared on Reset. | ||
| 6858 | */ | ||
| 6859 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK) | ||
| 6860 | /*! @} */ | ||
| 6861 | |||
| 6862 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */ | ||
| 6863 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) | ||
| 6864 | |||
| 6865 | /*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */ | ||
| 6866 | /*! @{ */ | ||
| 6867 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU) | ||
| 6868 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U) | ||
| 6869 | /*! HRD - Host Receive descriptor Address Pointer Cleared on Reset. | ||
| 6870 | */ | ||
| 6871 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK) | ||
| 6872 | /*! @} */ | ||
| 6873 | |||
| 6874 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */ | ||
| 6875 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) | ||
| 6876 | |||
| 6877 | /*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */ | ||
| 6878 | /*! @{ */ | ||
| 6879 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU) | ||
| 6880 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U) | ||
| 6881 | /*! HTB - Host Transmit Buffer Address Pointer Cleared on Reset. | ||
| 6882 | */ | ||
| 6883 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK) | ||
| 6884 | /*! @} */ | ||
| 6885 | |||
| 6886 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */ | ||
| 6887 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) | ||
| 6888 | |||
| 6889 | /*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */ | ||
| 6890 | /*! @{ */ | ||
| 6891 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU) | ||
| 6892 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U) | ||
| 6893 | /*! HRB - Host Receive Buffer Address Pointer Cleared on Reset. | ||
| 6894 | */ | ||
| 6895 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK) | ||
| 6896 | /*! @} */ | ||
| 6897 | |||
| 6898 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */ | ||
| 6899 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) | ||
| 6900 | |||
| 6901 | /*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */ | ||
| 6902 | /*! @{ */ | ||
| 6903 | #define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) | ||
| 6904 | #define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) | ||
| 6905 | /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete. | ||
| 6906 | */ | ||
| 6907 | #define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) | ||
| 6908 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) | ||
| 6909 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) | ||
| 6910 | /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped. | ||
| 6911 | */ | ||
| 6912 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) | ||
| 6913 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) | ||
| 6914 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) | ||
| 6915 | /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next | ||
| 6916 | * descriptor in the transmit list, and the DMA cannot acquire it. | ||
| 6917 | */ | ||
| 6918 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) | ||
| 6919 | #define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) | ||
| 6920 | #define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) | ||
| 6921 | /*! RI - Receive Interrupt This bit indicates that the packet reception is complete. | ||
| 6922 | */ | ||
| 6923 | #define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) | ||
| 6924 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) | ||
| 6925 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) | ||
| 6926 | /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next in the | ||
| 6927 | * receive list, and the DMA cannot acquire it. | ||
| 6928 | */ | ||
| 6929 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) | ||
| 6930 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) | ||
| 6931 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) | ||
| 6932 | /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. | ||
| 6933 | */ | ||
| 6934 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) | ||
| 6935 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) | ||
| 6936 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) | ||
| 6937 | /*! RWT - Receive Watchdog time out This bit is asserted when a packet with length greater than | ||
| 6938 | * 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. | ||
| 6939 | */ | ||
| 6940 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) | ||
| 6941 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) | ||
| 6942 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) | ||
| 6943 | /*! ETI - Early Transmit Interrupt This bit indicates that the packet to be transmitted is fully transferred to the MTL Tx FIFO. | ||
| 6944 | */ | ||
| 6945 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) | ||
| 6946 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) | ||
| 6947 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) | ||
| 6948 | /*! ERI - Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet. | ||
| 6949 | */ | ||
| 6950 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) | ||
| 6951 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) | ||
| 6952 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) | ||
| 6953 | /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). | ||
| 6954 | */ | ||
| 6955 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) | ||
| 6956 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) | ||
| 6957 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) | ||
| 6958 | /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the | ||
| 6959 | * following when the corresponding interrupt bits are enabled in the DMA Channel Interrupt Enable | ||
| 6960 | * register Table 778: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: | ||
| 6961 | * Receive Process Stopped Bit 10: Ear1y Transmit Interrupt Bit 12: Fatal Bus Error Only unmasked | ||
| 6962 | * bits affect the Abnormal Interrupt Summary bit. | ||
| 6963 | */ | ||
| 6964 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) | ||
| 6965 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) | ||
| 6966 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) | ||
| 6967 | /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the | ||
| 6968 | * following bits when the corresponding interrupt bits are enabled in the DMA Channel Interrupt | ||
| 6969 | * Enable register Table 778: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: | ||
| 6970 | * Receive Interrupt Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which | ||
| 6971 | * interrupt enable is set in DMA Channel Interrupt Enable register Table 778) affect the Normal | ||
| 6972 | * Interrupt Summary bit. | ||
| 6973 | */ | ||
| 6974 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) | ||
| 6975 | #define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U) | ||
| 6976 | #define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U) | ||
| 6977 | /*! EB - DMA Error Bits This field indicates the type of error that caused a Bus Error. | ||
| 6978 | */ | ||
| 6979 | #define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK) | ||
| 6980 | /*! @} */ | ||
| 6981 | |||
| 6982 | /* The count of ENET_DMA_CH_DMA_CHX_STAT */ | ||
| 6983 | #define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) | ||
| 6984 | |||
| 6985 | |||
| 6986 | /*! | ||
| 6987 | * @} | ||
| 6988 | */ /* end of group ENET_Register_Masks */ | ||
| 6989 | |||
| 6990 | |||
| 6991 | /* ENET - Peripheral instance base addresses */ | ||
| 6992 | /** Peripheral ENET base address */ | ||
| 6993 | #define ENET_BASE (0x40092000u) | ||
| 6994 | /** Peripheral ENET base pointer */ | ||
| 6995 | #define ENET ((ENET_Type *)ENET_BASE) | ||
| 6996 | /** Array initializer of ENET peripheral base addresses */ | ||
| 6997 | #define ENET_BASE_ADDRS { ENET_BASE } | ||
| 6998 | /** Array initializer of ENET peripheral base pointers */ | ||
| 6999 | #define ENET_BASE_PTRS { ENET } | ||
| 7000 | /** Interrupt vectors for the ENET peripheral type */ | ||
| 7001 | #define ENET_IRQS { ETHERNET_IRQn } | ||
| 7002 | #define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } | ||
| 7003 | #define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } | ||
| 7004 | |||
| 7005 | /*! | ||
| 7006 | * @} | ||
| 7007 | */ /* end of group ENET_Peripheral_Access_Layer */ | ||
| 7008 | |||
| 7009 | |||
| 7010 | /* ---------------------------------------------------------------------------- | ||
| 7011 | -- FLEXCOMM Peripheral Access Layer | ||
| 7012 | ---------------------------------------------------------------------------- */ | ||
| 7013 | |||
| 7014 | /*! | ||
| 7015 | * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer | ||
| 7016 | * @{ | ||
| 7017 | */ | ||
| 7018 | |||
| 7019 | /** FLEXCOMM - Register Layout Typedef */ | ||
| 7020 | typedef struct { | ||
| 7021 | uint8_t RESERVED_0[4088]; | ||
| 7022 | __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ | ||
| 7023 | __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ | ||
| 7024 | } FLEXCOMM_Type; | ||
| 7025 | |||
| 7026 | /* ---------------------------------------------------------------------------- | ||
| 7027 | -- FLEXCOMM Register Masks | ||
| 7028 | ---------------------------------------------------------------------------- */ | ||
| 7029 | |||
| 7030 | /*! | ||
| 7031 | * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks | ||
| 7032 | * @{ | ||
| 7033 | */ | ||
| 7034 | |||
| 7035 | /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ | ||
| 7036 | /*! @{ */ | ||
| 7037 | #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) | ||
| 7038 | #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) | ||
| 7039 | /*! PERSEL - Peripheral Select. This field is writable by software. | ||
| 7040 | * 0b000..No peripheral selected. | ||
| 7041 | * 0b001..USART function selected. | ||
| 7042 | * 0b010..SPI function selected. | ||
| 7043 | * 0b011..I2C function selected. | ||
| 7044 | * 0b100..I2S transmit function selected. | ||
| 7045 | * 0b101..I2S receive function selected. | ||
| 7046 | * 0b110..Reserved | ||
| 7047 | * 0b111..Reserved | ||
| 7048 | */ | ||
| 7049 | #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) | ||
| 7050 | #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) | ||
| 7051 | #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) | ||
| 7052 | /*! LOCK - Lock the peripheral select. This field is writable by software. | ||
| 7053 | * 0b0..Peripheral select can be changed by software. | ||
| 7054 | * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. | ||
| 7055 | */ | ||
| 7056 | #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) | ||
| 7057 | #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) | ||
| 7058 | #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) | ||
| 7059 | /*! USARTPRESENT - USART present indicator. This field is Read-only. | ||
| 7060 | * 0b0..This Flexcomm does not include the USART function. | ||
| 7061 | * 0b1..This Flexcomm includes the USART function. | ||
| 7062 | */ | ||
| 7063 | #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) | ||
| 7064 | #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) | ||
| 7065 | #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) | ||
| 7066 | /*! SPIPRESENT - SPI present indicator. This field is Read-only. | ||
| 7067 | * 0b0..This Flexcomm does not include the SPI function. | ||
| 7068 | * 0b1..This Flexcomm includes the SPI function. | ||
| 7069 | */ | ||
| 7070 | #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) | ||
| 7071 | #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) | ||
| 7072 | #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) | ||
| 7073 | /*! I2CPRESENT - I2C present indicator. This field is Read-only. | ||
| 7074 | * 0b0..This Flexcomm does not include the I2C function. | ||
| 7075 | * 0b1..This Flexcomm includes the I2C function. | ||
| 7076 | */ | ||
| 7077 | #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) | ||
| 7078 | #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) | ||
| 7079 | #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) | ||
| 7080 | /*! I2SPRESENT - I 2S present indicator. This field is Read-only. | ||
| 7081 | * 0b0..This Flexcomm does not include the I2S function. | ||
| 7082 | * 0b1..This Flexcomm includes the I2S function. | ||
| 7083 | */ | ||
| 7084 | #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) | ||
| 7085 | #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) | ||
| 7086 | #define FLEXCOMM_PSELID_ID_SHIFT (12U) | ||
| 7087 | /*! ID - Flexcomm ID. | ||
| 7088 | */ | ||
| 7089 | #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) | ||
| 7090 | /*! @} */ | ||
| 7091 | |||
| 7092 | /*! @name PID - Peripheral identification register. */ | ||
| 7093 | /*! @{ */ | ||
| 7094 | #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) | ||
| 7095 | #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) | ||
| 7096 | /*! Minor_Rev - Minor revision of module implementation. | ||
| 7097 | */ | ||
| 7098 | #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) | ||
| 7099 | #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) | ||
| 7100 | #define FLEXCOMM_PID_Major_Rev_SHIFT (12U) | ||
| 7101 | /*! Major_Rev - Major revision of module implementation. | ||
| 7102 | */ | ||
| 7103 | #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) | ||
| 7104 | #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) | ||
| 7105 | #define FLEXCOMM_PID_ID_SHIFT (16U) | ||
| 7106 | /*! ID - Module identifier for the selected function. | ||
| 7107 | */ | ||
| 7108 | #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) | ||
| 7109 | /*! @} */ | ||
| 7110 | |||
| 7111 | |||
| 7112 | /*! | ||
| 7113 | * @} | ||
| 7114 | */ /* end of group FLEXCOMM_Register_Masks */ | ||
| 7115 | |||
| 7116 | |||
| 7117 | /* FLEXCOMM - Peripheral instance base addresses */ | ||
| 7118 | /** Peripheral FLEXCOMM0 base address */ | ||
| 7119 | #define FLEXCOMM0_BASE (0x40086000u) | ||
| 7120 | /** Peripheral FLEXCOMM0 base pointer */ | ||
| 7121 | #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) | ||
| 7122 | /** Peripheral FLEXCOMM1 base address */ | ||
| 7123 | #define FLEXCOMM1_BASE (0x40087000u) | ||
| 7124 | /** Peripheral FLEXCOMM1 base pointer */ | ||
| 7125 | #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) | ||
| 7126 | /** Peripheral FLEXCOMM2 base address */ | ||
| 7127 | #define FLEXCOMM2_BASE (0x40088000u) | ||
| 7128 | /** Peripheral FLEXCOMM2 base pointer */ | ||
| 7129 | #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) | ||
| 7130 | /** Peripheral FLEXCOMM3 base address */ | ||
| 7131 | #define FLEXCOMM3_BASE (0x40089000u) | ||
| 7132 | /** Peripheral FLEXCOMM3 base pointer */ | ||
| 7133 | #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) | ||
| 7134 | /** Peripheral FLEXCOMM4 base address */ | ||
| 7135 | #define FLEXCOMM4_BASE (0x4008A000u) | ||
| 7136 | /** Peripheral FLEXCOMM4 base pointer */ | ||
| 7137 | #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) | ||
| 7138 | /** Peripheral FLEXCOMM5 base address */ | ||
| 7139 | #define FLEXCOMM5_BASE (0x40096000u) | ||
| 7140 | /** Peripheral FLEXCOMM5 base pointer */ | ||
| 7141 | #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) | ||
| 7142 | /** Peripheral FLEXCOMM6 base address */ | ||
| 7143 | #define FLEXCOMM6_BASE (0x40097000u) | ||
| 7144 | /** Peripheral FLEXCOMM6 base pointer */ | ||
| 7145 | #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) | ||
| 7146 | /** Peripheral FLEXCOMM7 base address */ | ||
| 7147 | #define FLEXCOMM7_BASE (0x40098000u) | ||
| 7148 | /** Peripheral FLEXCOMM7 base pointer */ | ||
| 7149 | #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) | ||
| 7150 | /** Peripheral FLEXCOMM8 base address */ | ||
| 7151 | #define FLEXCOMM8_BASE (0x40099000u) | ||
| 7152 | /** Peripheral FLEXCOMM8 base pointer */ | ||
| 7153 | #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) | ||
| 7154 | /** Peripheral FLEXCOMM9 base address */ | ||
| 7155 | #define FLEXCOMM9_BASE (0x4009A000u) | ||
| 7156 | /** Peripheral FLEXCOMM9 base pointer */ | ||
| 7157 | #define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE) | ||
| 7158 | /** Array initializer of FLEXCOMM peripheral base addresses */ | ||
| 7159 | #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE } | ||
| 7160 | /** Array initializer of FLEXCOMM peripheral base pointers */ | ||
| 7161 | #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 } | ||
| 7162 | /** Interrupt vectors for the FLEXCOMM peripheral type */ | ||
| 7163 | #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } | ||
| 7164 | |||
| 7165 | /*! | ||
| 7166 | * @} | ||
| 7167 | */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ | ||
| 7168 | |||
| 7169 | |||
| 7170 | /* ---------------------------------------------------------------------------- | ||
| 7171 | -- FMC Peripheral Access Layer | ||
| 7172 | ---------------------------------------------------------------------------- */ | ||
| 7173 | |||
| 7174 | /*! | ||
| 7175 | * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer | ||
| 7176 | * @{ | ||
| 7177 | */ | ||
| 7178 | |||
| 7179 | /** FMC - Register Layout Typedef */ | ||
| 7180 | typedef struct { | ||
| 7181 | __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ | ||
| 7182 | uint8_t RESERVED_0[12]; | ||
| 7183 | __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ | ||
| 7184 | uint8_t RESERVED_1[12]; | ||
| 7185 | __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ | ||
| 7186 | __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ | ||
| 7187 | uint8_t RESERVED_2[4]; | ||
| 7188 | __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ | ||
| 7189 | uint8_t RESERVED_3[4004]; | ||
| 7190 | __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ | ||
| 7191 | uint8_t RESERVED_4[4]; | ||
| 7192 | __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ | ||
| 7193 | } FMC_Type; | ||
| 7194 | |||
| 7195 | /* ---------------------------------------------------------------------------- | ||
| 7196 | -- FMC Register Masks | ||
| 7197 | ---------------------------------------------------------------------------- */ | ||
| 7198 | |||
| 7199 | /*! | ||
| 7200 | * @addtogroup FMC_Register_Masks FMC Register Masks | ||
| 7201 | * @{ | ||
| 7202 | */ | ||
| 7203 | |||
| 7204 | /*! @name FCTR - Control register */ | ||
| 7205 | /*! @{ */ | ||
| 7206 | #define FMC_FCTR_FS_RD0_MASK (0x8U) | ||
| 7207 | #define FMC_FCTR_FS_RD0_SHIFT (3U) | ||
| 7208 | /*! FS_RD0 - Value must be 0 for signature generation. | ||
| 7209 | */ | ||
| 7210 | #define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) | ||
| 7211 | #define FMC_FCTR_FS_RD1_MASK (0x10U) | ||
| 7212 | #define FMC_FCTR_FS_RD1_SHIFT (4U) | ||
| 7213 | /*! FS_RD1 - Value must be 1 for signature generation. | ||
| 7214 | */ | ||
| 7215 | #define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) | ||
| 7216 | /*! @} */ | ||
| 7217 | |||
| 7218 | /*! @name FBWST - Wait state register */ | ||
| 7219 | /*! @{ */ | ||
| 7220 | #define FMC_FBWST_WAITSTATES_MASK (0xFFU) | ||
| 7221 | #define FMC_FBWST_WAITSTATES_SHIFT (0U) | ||
| 7222 | /*! WAITSTATES - Wait states for signature generation. | ||
| 7223 | */ | ||
| 7224 | #define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) | ||
| 7225 | /*! @} */ | ||
| 7226 | |||
| 7227 | /*! @name FMSSTART - Signature start address register */ | ||
| 7228 | /*! @{ */ | ||
| 7229 | #define FMC_FMSSTART_START_MASK (0x1FFFFU) | ||
| 7230 | #define FMC_FMSSTART_START_SHIFT (0U) | ||
| 7231 | /*! START - Signature generation start address (corresponds to AHB byte address bits[20:4]). | ||
| 7232 | */ | ||
| 7233 | #define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) | ||
| 7234 | /*! @} */ | ||
| 7235 | |||
| 7236 | /*! @name FMSSTOP - Signature stop-address register */ | ||
| 7237 | /*! @{ */ | ||
| 7238 | #define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) | ||
| 7239 | #define FMC_FMSSTOP_STOP_SHIFT (0U) | ||
| 7240 | /*! STOP - Stop address for signature generation (the word specified by STOP is included in the address range). | ||
| 7241 | */ | ||
| 7242 | #define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) | ||
| 7243 | #define FMC_FMSSTOP_SIG_START_MASK (0x20000U) | ||
| 7244 | #define FMC_FMSSTOP_SIG_START_SHIFT (17U) | ||
| 7245 | /*! SIG_START - When this bit is written to 1, signature generation starts. | ||
| 7246 | */ | ||
| 7247 | #define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) | ||
| 7248 | /*! @} */ | ||
| 7249 | |||
| 7250 | /*! @name FMSW - Words of 128-bit signature word */ | ||
| 7251 | /*! @{ */ | ||
| 7252 | #define FMC_FMSW_SW_MASK (0xFFFFFFFFU) | ||
| 7253 | #define FMC_FMSW_SW_SHIFT (0U) | ||
| 7254 | /*! SW - Words of 128-bit signature (bits). | ||
| 7255 | */ | ||
| 7256 | #define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) | ||
| 7257 | /*! @} */ | ||
| 7258 | |||
| 7259 | /* The count of FMC_FMSW */ | ||
| 7260 | #define FMC_FMSW_COUNT (4U) | ||
| 7261 | |||
| 7262 | /*! @name FMSTAT - Signature generation status register */ | ||
| 7263 | /*! @{ */ | ||
| 7264 | #define FMC_FMSTAT_SIG_DONE_MASK (0x4U) | ||
| 7265 | #define FMC_FMSTAT_SIG_DONE_SHIFT (2U) | ||
| 7266 | /*! SIG_DONE - When 1, a previously started signature generation has completed. | ||
| 7267 | */ | ||
| 7268 | #define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) | ||
| 7269 | /*! @} */ | ||
| 7270 | |||
| 7271 | /*! @name FMSTATCLR - Signature generation status clear register */ | ||
| 7272 | /*! @{ */ | ||
| 7273 | #define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) | ||
| 7274 | #define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) | ||
| 7275 | /*! SIG_DONE_CLR - Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. | ||
| 7276 | */ | ||
| 7277 | #define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) | ||
| 7278 | /*! @} */ | ||
| 7279 | |||
| 7280 | |||
| 7281 | /*! | ||
| 7282 | * @} | ||
| 7283 | */ /* end of group FMC_Register_Masks */ | ||
| 7284 | |||
| 7285 | |||
| 7286 | /* FMC - Peripheral instance base addresses */ | ||
| 7287 | /** Peripheral FMC base address */ | ||
| 7288 | #define FMC_BASE (0x40034000u) | ||
| 7289 | /** Peripheral FMC base pointer */ | ||
| 7290 | #define FMC ((FMC_Type *)FMC_BASE) | ||
| 7291 | /** Array initializer of FMC peripheral base addresses */ | ||
| 7292 | #define FMC_BASE_ADDRS { FMC_BASE } | ||
| 7293 | /** Array initializer of FMC peripheral base pointers */ | ||
| 7294 | #define FMC_BASE_PTRS { FMC } | ||
| 7295 | |||
| 7296 | /*! | ||
| 7297 | * @} | ||
| 7298 | */ /* end of group FMC_Peripheral_Access_Layer */ | ||
| 7299 | |||
| 7300 | |||
| 7301 | /* ---------------------------------------------------------------------------- | ||
| 7302 | -- GINT Peripheral Access Layer | ||
| 7303 | ---------------------------------------------------------------------------- */ | ||
| 7304 | |||
| 7305 | /*! | ||
| 7306 | * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer | ||
| 7307 | * @{ | ||
| 7308 | */ | ||
| 7309 | |||
| 7310 | /** GINT - Register Layout Typedef */ | ||
| 7311 | typedef struct { | ||
| 7312 | __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ | ||
| 7313 | uint8_t RESERVED_0[28]; | ||
| 7314 | __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ | ||
| 7315 | uint8_t RESERVED_1[24]; | ||
| 7316 | __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ | ||
| 7317 | } GINT_Type; | ||
| 7318 | |||
| 7319 | /* ---------------------------------------------------------------------------- | ||
| 7320 | -- GINT Register Masks | ||
| 7321 | ---------------------------------------------------------------------------- */ | ||
| 7322 | |||
| 7323 | /*! | ||
| 7324 | * @addtogroup GINT_Register_Masks GINT Register Masks | ||
| 7325 | * @{ | ||
| 7326 | */ | ||
| 7327 | |||
| 7328 | /*! @name CTRL - GPIO grouped interrupt control register */ | ||
| 7329 | /*! @{ */ | ||
| 7330 | #define GINT_CTRL_INT_MASK (0x1U) | ||
| 7331 | #define GINT_CTRL_INT_SHIFT (0U) | ||
| 7332 | /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. | ||
| 7333 | * 0b0..No request. No interrupt request is pending. | ||
| 7334 | * 0b1..Request active. Interrupt request is active. | ||
| 7335 | */ | ||
| 7336 | #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) | ||
| 7337 | #define GINT_CTRL_COMB_MASK (0x2U) | ||
| 7338 | #define GINT_CTRL_COMB_SHIFT (1U) | ||
| 7339 | /*! COMB - Combine enabled inputs for group interrupt | ||
| 7340 | * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). | ||
| 7341 | * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). | ||
| 7342 | */ | ||
| 7343 | #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) | ||
| 7344 | #define GINT_CTRL_TRIG_MASK (0x4U) | ||
| 7345 | #define GINT_CTRL_TRIG_SHIFT (2U) | ||
| 7346 | /*! TRIG - Group interrupt trigger | ||
| 7347 | * 0b0..Edge-triggered. | ||
| 7348 | * 0b1..Level-triggered. | ||
| 7349 | */ | ||
| 7350 | #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) | ||
| 7351 | /*! @} */ | ||
| 7352 | |||
| 7353 | /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ | ||
| 7354 | /*! @{ */ | ||
| 7355 | #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) | ||
| 7356 | #define GINT_PORT_POL_POL_SHIFT (0U) | ||
| 7357 | /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n | ||
| 7358 | * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to | ||
| 7359 | * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin | ||
| 7360 | * contributes to the group interrupt. | ||
| 7361 | */ | ||
| 7362 | #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) | ||
| 7363 | /*! @} */ | ||
| 7364 | |||
| 7365 | /* The count of GINT_PORT_POL */ | ||
| 7366 | #define GINT_PORT_POL_COUNT (2U) | ||
| 7367 | |||
| 7368 | /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ | ||
| 7369 | /*! @{ */ | ||
| 7370 | #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) | ||
| 7371 | #define GINT_PORT_ENA_ENA_SHIFT (0U) | ||
| 7372 | /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the | ||
| 7373 | * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is | ||
| 7374 | * enabled and contributes to the grouped interrupt. | ||
| 7375 | */ | ||
| 7376 | #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) | ||
| 7377 | /*! @} */ | ||
| 7378 | |||
| 7379 | /* The count of GINT_PORT_ENA */ | ||
| 7380 | #define GINT_PORT_ENA_COUNT (2U) | ||
| 7381 | |||
| 7382 | |||
| 7383 | /*! | ||
| 7384 | * @} | ||
| 7385 | */ /* end of group GINT_Register_Masks */ | ||
| 7386 | |||
| 7387 | |||
| 7388 | /* GINT - Peripheral instance base addresses */ | ||
| 7389 | /** Peripheral GINT0 base address */ | ||
| 7390 | #define GINT0_BASE (0x40002000u) | ||
| 7391 | /** Peripheral GINT0 base pointer */ | ||
| 7392 | #define GINT0 ((GINT_Type *)GINT0_BASE) | ||
| 7393 | /** Peripheral GINT1 base address */ | ||
| 7394 | #define GINT1_BASE (0x40003000u) | ||
| 7395 | /** Peripheral GINT1 base pointer */ | ||
| 7396 | #define GINT1 ((GINT_Type *)GINT1_BASE) | ||
| 7397 | /** Array initializer of GINT peripheral base addresses */ | ||
| 7398 | #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } | ||
| 7399 | /** Array initializer of GINT peripheral base pointers */ | ||
| 7400 | #define GINT_BASE_PTRS { GINT0, GINT1 } | ||
| 7401 | /** Interrupt vectors for the GINT peripheral type */ | ||
| 7402 | #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } | ||
| 7403 | |||
| 7404 | /*! | ||
| 7405 | * @} | ||
| 7406 | */ /* end of group GINT_Peripheral_Access_Layer */ | ||
| 7407 | |||
| 7408 | |||
| 7409 | /* ---------------------------------------------------------------------------- | ||
| 7410 | -- GPIO Peripheral Access Layer | ||
| 7411 | ---------------------------------------------------------------------------- */ | ||
| 7412 | |||
| 7413 | /*! | ||
| 7414 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer | ||
| 7415 | * @{ | ||
| 7416 | */ | ||
| 7417 | |||
| 7418 | /** GPIO - Register Layout Typedef */ | ||
| 7419 | typedef struct { | ||
| 7420 | __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ | ||
| 7421 | uint8_t RESERVED_0[3904]; | ||
| 7422 | __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ | ||
| 7423 | uint8_t RESERVED_1[3328]; | ||
| 7424 | __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ | ||
| 7425 | uint8_t RESERVED_2[104]; | ||
| 7426 | __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ | ||
| 7427 | uint8_t RESERVED_3[104]; | ||
| 7428 | __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ | ||
| 7429 | uint8_t RESERVED_4[104]; | ||
| 7430 | __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ | ||
| 7431 | uint8_t RESERVED_5[104]; | ||
| 7432 | __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ | ||
| 7433 | uint8_t RESERVED_6[104]; | ||
| 7434 | __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ | ||
| 7435 | uint8_t RESERVED_7[104]; | ||