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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/system_LPC54608.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54608/system_LPC54608.c
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1/*
2** ###################################################################
3** Processors: LPC54608J512BD208
4** LPC54608J512ET180
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
12** Version: rev. 1.2, 2017-06-08
13** Build: b201015
14**
15** Abstract:
16** Provides a system configuration function and a global variable that
17** contains the system frequency. It configures the device and initializes
18** the oscillator (PLL) that is part of the microcontroller device.
19**
20** Copyright 2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2016-08-12)
31** Initial version.
32** - rev. 1.1 (2016-11-25)
33** Update CANFD and Classic CAN register.
34** Add MAC TIMERSTAMP registers.
35** - rev. 1.2 (2017-06-08)
36** Remove RTC_CTRL_RTC_OSC_BYPASS.
37** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
38** Remove RESET and HALT from SYSCON_AHBCLKDIV.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file LPC54608
45 * @version 1.2
46 * @date 2017-06-08
47 * @brief Device specific configuration file for LPC54608 (implementation file)
48 *
49 * Provides a system configuration function and a global variable that contains
50 * the system frequency. It configures the device and initializes the oscillator
51 * (PLL) that is part of the microcontroller device.
52 */
53
54#include <stdint.h>
55#include "fsl_device_registers.h"
56
57#define NVALMAX (0x100)
58#define PVALMAX (0x20U)
59#define MVALMAX (0x8000U)
60#define PLL_MDEC_VAL_P (0U) /* MDEC is in bits 16:0 */
61#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
62#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
63#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
64#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
65#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
66
67static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
68 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
69/* Get WATCH DOG Clk */
70static uint32_t getWdtOscFreq(void)
71{
72 uint8_t freq_sel, div_sel;
73 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) == SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
74 {
75 return 0U;
76 }
77 else
78 {
79 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
80 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
81 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
82 }
83}
84/* Find decoded N value for raw NDEC value */
85static uint32_t pllDecodeN(uint32_t NDEC)
86{
87 uint32_t n, x, i;
88
89 /* Find NDec */
90 switch (NDEC)
91 {
92 case 0x3FFU:
93 n = 0UL;
94 break;
95 case 0x302U:
96 n = 1UL;
97 break;
98 case 0x202U:
99 n = 2UL;
100 break;
101 default:
102 x = 0x080UL;
103 n = 0xFFFFFFFFUL;
104 for (i = NVALMAX; i >= 3UL; i--)
105 {
106 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
107 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
108 {
109 /* Decoded value of NDEC */
110 n = i;
111 }
112 if (n != 0xFFFFFFFFUL)
113 {
114 break;
115 }
116 }
117 break;
118 }
119 return n;
120}
121
122/* Find decoded P value for raw PDEC value */
123static uint32_t pllDecodeP(uint32_t PDEC)
124{
125 uint32_t p, x, i;
126 /* Find PDec */
127 switch (PDEC)
128 {
129 case 0x7FU:
130 p = 0UL;
131 break;
132 case 0x62U:
133 p = 1UL;
134 break;
135 case 0x42U:
136 p = 2UL;
137 break;
138 default:
139 x = 0x10UL;
140 p = 0xFFFFFFFFUL;
141 for (i = PVALMAX; i >= 3UL; i--)
142 {
143 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
144 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
145 {
146 /* Decoded value of PDEC */
147 p = i;
148 }
149 if (p != 0xFFFFFFFFUL)
150 {
151 break;
152 }
153 }
154 break;
155 }
156 return p;
157}
158
159/* Find decoded M value for raw MDEC value */
160static uint32_t pllDecodeM(uint32_t MDEC)
161{
162 uint32_t m, i, x;
163
164 /* Find MDec */
165 switch (MDEC)
166 {
167 case 0x1FFFFU:
168 m = 0UL;
169 break;
170 case 0x18003U:
171 m = 1UL;
172 break;
173 case 0x10003U:
174 m = 2UL;
175 break;
176 default:
177 x = 0x04000UL;
178 m = 0xFFFFFFFFUL;
179 for (i = MVALMAX; i >= 3UL; i--)
180 {
181 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
182 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
183 {
184 /* Decoded value of MDEC */
185 m = i;
186 }
187 if (m != 0xFFFFFFFFUL)
188 {
189 break;
190 }
191 }
192 break;
193 }
194 return m;
195}
196
197/* Get predivider (N) from PLL NDEC setting */
198static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
199{
200 uint32_t preDiv = 1U;
201
202 /* Direct input is not used? */
203 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0U)
204 {
205 /* Decode NDEC value to get (N) pre divider */
206 preDiv = pllDecodeN(nDecReg & 0x3FFU);
207 if (preDiv == 0U)
208 {
209 preDiv = 1U;
210 }
211 }
212 /* Adjusted by 1, directi is used to bypass */
213 return preDiv;
214}
215
216/* Get postdivider (P) from PLL PDEC setting */
217static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
218{
219 uint32_t postDiv = 1U;
220
221 /* Direct input is not used? */
222 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
223 {
224 /* Decode PDEC value to get (P) post divider */
225 postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
226 if (postDiv == 0U)
227 {
228 postDiv = 2U;
229 }
230 }
231 /* Adjusted by 1, directo is used to bypass */
232 return postDiv;
233}
234
235/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
236static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
237{
238 uint32_t mMult = 1U;
239
240 /* Decode MDEC value to get (M) multiplier */
241 mMult = pllDecodeM(mDecReg & 0x1FFFFU);
242 if (mMult == 0U)
243 {
244 mMult = 1U;
245 }
246 return mMult;
247}
248
249
250
251/* ----------------------------------------------------------------------------
252 -- Core clock
253 ---------------------------------------------------------------------------- */
254
255uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
256
257/* ----------------------------------------------------------------------------
258 -- SystemInit()
259 ---------------------------------------------------------------------------- */
260
261void SystemInit (void) {
262#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
263 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
264#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
265
266#if defined(__MCUXPRESSO)
267 extern void(*const g_pfnVectors[]) (void);
268 SCB->VTOR = (uint32_t) &g_pfnVectors;
269#else
270 extern void *__Vectors;
271 SCB->VTOR = (uint32_t) &__Vectors;
272#endif
273 SYSCON->ARMTRACECLKDIV = 0U;
274/* Optionally enable RAM banks that may be off by default at reset */
275#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
276 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
277#endif
278 SystemInitHook();
279}
280
281/* ----------------------------------------------------------------------------
282 -- SystemCoreClockUpdate()
283 ---------------------------------------------------------------------------- */
284
285void SystemCoreClockUpdate (void) {
286uint32_t clkRate = 0U;
287 uint32_t prediv, postdiv;
288 uint64_t workRate;
289
290 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
291 {
292 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
293 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
294 {
295 case 0x00U: /* FRO 12 MHz (fro_12m) */
296 clkRate = CLK_FRO_12MHZ;
297 break;
298 case 0x01U: /* CLKIN Source (clk_in) */
299 clkRate = CLK_CLK_IN;
300 break;
301 case 0x02U: /* Watchdog oscillator (wdt_clk) */
302 clkRate = getWdtOscFreq();
303 break;
304 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
305 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
306 {
307 clkRate = CLK_FRO_96MHZ;
308 }
309 else
310 {
311 clkRate = CLK_FRO_48MHZ;
312 }
313 break;
314 }
315 break;
316 case 0x02U: /* System PLL clock (pll_clk)*/
317 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
318 {
319 case 0x00U: /* FRO 12 MHz (fro_12m) */
320 clkRate = CLK_FRO_12MHZ;
321 break;
322 case 0x01U: /* CLKIN Source (clk_in) */
323 clkRate = CLK_CLK_IN;
324 break;
325 case 0x02U: /* Watchdog oscillator (wdt_clk) */
326 clkRate = getWdtOscFreq();
327 break;
328 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
329 clkRate = CLK_RTC_32K_CLK;
330 break;
331 default:
332 clkRate = 0U;
333 break;
334 }
335 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0U)
336 {
337 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
338 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
339 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
340 /* Adjust input clock */
341 clkRate = clkRate / prediv;
342
343 /* MDEC used for rate */
344 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
345 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
346 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
347 }
348 break;
349 case 0x03U: /* RTC oscillator 32 kHz output (32k_clk) */
350 clkRate = CLK_RTC_32K_CLK;
351 break;
352 default:
353 clkRate = 0U;
354 break;
355 }
356 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
357}
358
359/* ----------------------------------------------------------------------------
360 -- SystemInitHook()
361 ---------------------------------------------------------------------------- */
362
363__attribute__ ((weak)) void SystemInitHook (void) {
364 /* Void implementation of the weak function. */
365}
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