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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/drivers/fsl_clock.h
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/drivers/fsl_clock.h
@@ -0,0 +1,1296 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10#ifndef _FSL_CLOCK_H_
11#define _FSL_CLOCK_H_
12
13#include "fsl_common.h"
14
15/*! @addtogroup clock */
16/*! @{ */
17
18/*! @file */
19
20/*******************************************************************************
21 * Definitions
22 *****************************************************************************/
23
24/*! @name Driver version */
25/*@{*/
26/*! @brief CLOCK driver version 2.3.2. */
27#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
28/*@}*/
29
30/*! @brief Configure whether driver controls clock
31 *
32 * When set to 0, peripheral drivers will enable clock in initialize function
33 * and disable clock in de-initialize function. When set to 1, peripheral
34 * driver will not control the clock, application could control the clock out of
35 * the driver.
36 *
37 * @note All drivers share this feature switcher. If it is set to 1, application
38 * should handle clock enable and disable for all drivers.
39 */
40#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
41#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
42#endif
43
44/*!
45 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
46 *
47 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
48 * would cache the recent calulation and accelerate the execution to get the
49 * right settings.
50 */
51#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
52#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
53#endif
54
55/* Definition for delay API in clock driver, users can redefine it to the real application. */
56#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
57#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
58#endif
59
60/*! @brief Clock ip name array for ADC. */
61#define ADC_CLOCKS \
62 { \
63 kCLOCK_Adc0 \
64 }
65/*! @brief Clock ip name array for ROM. */
66#define ROM_CLOCKS \
67 { \
68 kCLOCK_Rom \
69 }
70/*! @brief Clock ip name array for SRAM. */
71#define SRAM_CLOCKS \
72 { \
73 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
74 }
75/*! @brief Clock ip name array for FLASH. */
76#define FLASH_CLOCKS \
77 { \
78 kCLOCK_Flash \
79 }
80/*! @brief Clock ip name array for FMC. */
81#define FMC_CLOCKS \
82 { \
83 kCLOCK_Fmc \
84 }
85/*! @brief Clock ip name array for EEPROM. */
86#define EEPROM_CLOCKS \
87 { \
88 kCLOCK_Eeprom \
89 }
90/*! @brief Clock ip name array for SPIFI. */
91#define SPIFI_CLOCKS \
92 { \
93 kCLOCK_Spifi \
94 }
95/*! @brief Clock ip name array for INPUTMUX. */
96#define INPUTMUX_CLOCKS \
97 { \
98 kCLOCK_InputMux \
99 }
100/*! @brief Clock ip name array for IOCON. */
101#define IOCON_CLOCKS \
102 { \
103 kCLOCK_Iocon \
104 }
105/*! @brief Clock ip name array for GPIO. */
106#define GPIO_CLOCKS \
107 { \
108 kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
109 }
110/*! @brief Clock ip name array for PINT. */
111#define PINT_CLOCKS \
112 { \
113 kCLOCK_Pint \
114 }
115/*! @brief Clock ip name array for GINT. */
116#define GINT_CLOCKS \
117 { \
118 kCLOCK_Gint, kCLOCK_Gint \
119 }
120/*! @brief Clock ip name array for DMA. */
121#define DMA_CLOCKS \
122 { \
123 kCLOCK_Dma \
124 }
125/*! @brief Clock ip name array for CRC. */
126#define CRC_CLOCKS \
127 { \
128 kCLOCK_Crc \
129 }
130/*! @brief Clock ip name array for WWDT. */
131#define WWDT_CLOCKS \
132 { \
133 kCLOCK_Wwdt \
134 }
135/*! @brief Clock ip name array for RTC. */
136#define RTC_CLOCKS \
137 { \
138 kCLOCK_Rtc \
139 }
140/*! @brief Clock ip name array for ADC0. */
141#define ADC0_CLOCKS \
142 { \
143 kCLOCK_Adc0 \
144 }
145/*! @brief Clock ip name array for MRT. */
146#define MRT_CLOCKS \
147 { \
148 kCLOCK_Mrt \
149 }
150/*! @brief Clock ip name array for RIT. */
151#define RIT_CLOCKS \
152 { \
153 kCLOCK_Rit \
154 }
155/*! @brief Clock ip name array for SCT0. */
156#define SCT_CLOCKS \
157 { \
158 kCLOCK_Sct0 \
159 }
160/*! @brief Clock ip name array for MCAN. */
161#define MCAN_CLOCKS \
162 { \
163 kCLOCK_Mcan0, kCLOCK_Mcan1 \
164 }
165/*! @brief Clock ip name array for UTICK. */
166#define UTICK_CLOCKS \
167 { \
168 kCLOCK_Utick \
169 }
170/*! @brief Clock ip name array for FLEXCOMM. */
171#define FLEXCOMM_CLOCKS \
172 { \
173 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
174 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9, kCLOCK_FlexComm10 \
175 }
176/*! @brief Clock ip name array for LPUART. */
177#define LPUART_CLOCKS \
178 { \
179 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
180 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \
181 }
182
183/*! @brief Clock ip name array for BI2C. */
184#define BI2C_CLOCKS \
185 { \
186 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \
187 kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \
188 }
189/*! @brief Clock ip name array for LSPI. */
190#define LPSI_CLOCKS \
191 { \
192 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \
193 kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \
194 }
195/*! @brief Clock ip name array for FLEXI2S. */
196#define FLEXI2S_CLOCKS \
197 { \
198 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
199 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
200 }
201/*! @brief Clock ip name array for DMIC. */
202#define DMIC_CLOCKS \
203 { \
204 kCLOCK_DMic \
205 }
206/*! @brief Clock ip name array for CT32B. */
207#define CTIMER_CLOCKS \
208 { \
209 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
210 }
211/*! @brief Clock ip name array for LCD. */
212#define LCD_CLOCKS \
213 { \
214 kCLOCK_Lcd \
215 }
216/*! @brief Clock ip name array for SDIO. */
217#define SDIO_CLOCKS \
218 { \
219 kCLOCK_Sdio \
220 }
221/*! @brief Clock ip name array for USBRAM. */
222#define USBRAM_CLOCKS \
223 { \
224 kCLOCK_UsbRam1 \
225 }
226/*! @brief Clock ip name array for EMC. */
227#define EMC_CLOCKS \
228 { \
229 kCLOCK_Emc \
230 }
231/*! @brief Clock ip name array for ETH. */
232#define ETH_CLOCKS \
233 { \
234 kCLOCK_Eth \
235 }
236/*! @brief Clock ip name array for AES. */
237#define AES_CLOCKS \
238 { \
239 kCLOCK_Aes \
240 }
241/*! @brief Clock ip name array for OTP. */
242#define OTP_CLOCKS \
243 { \
244 kCLOCK_Otp \
245 }
246/*! @brief Clock ip name array for RNG. */
247#define RNG_CLOCKS \
248 { \
249 kCLOCK_Rng \
250 }
251/*! @brief Clock ip name array for USBHMR0. */
252#define USBHMR0_CLOCKS \
253 { \
254 kCLOCK_Usbhmr0 \
255 }
256/*! @brief Clock ip name array for USBHSL0. */
257#define USBHSL0_CLOCKS \
258 { \
259 kCLOCK_Usbhsl0 \
260 }
261/*! @brief Clock ip name array for SHA0. */
262#define SHA0_CLOCKS \
263 { \
264 kCLOCK_Sha0 \
265 }
266/*! @brief Clock ip name array for SMARTCARD. */
267#define SMARTCARD_CLOCKS \
268 { \
269 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
270 }
271/*! @brief Clock ip name array for USBD. */
272#define USBD_CLOCKS \
273 { \
274 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
275 }
276/*! @brief Clock ip name array for USBH. */
277#define USBH_CLOCKS \
278 { \
279 kCLOCK_Usbh1 \
280 }
281/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
282/*------------------------------------------------------------------------------
283 clock_ip_name_t definition:
284------------------------------------------------------------------------------*/
285
286#define CLK_GATE_REG_OFFSET_SHIFT 8U
287#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
288#define CLK_GATE_BIT_SHIFT_SHIFT 0U
289#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
290
291#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
292 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
293 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
294
295#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
296#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
297
298#define AHB_CLK_CTRL0 0
299#define AHB_CLK_CTRL1 1
300#define AHB_CLK_CTRL2 2
301#define ASYNC_CLK_CTRL0 3
302
303/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
304typedef enum _clock_ip_name
305{
306 kCLOCK_IpInvalid = 0U,
307 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
308 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
309 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
310 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
311 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
312 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
313 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
314 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
315 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
316 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
317 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
318 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
319 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
320 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
321 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
322 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
323 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
324 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
325 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
326 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
327 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
328 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
329 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
330 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
331 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
332 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
333 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
334 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
335 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
336 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
337 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
338 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
339 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
340 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
341 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
342 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
343 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
344 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
345 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
346 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
347 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
348 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
349 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
350 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
351 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
352 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
353 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
354 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
355 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
356 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
357 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
358 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
359 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
360 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
361 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
362 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
363 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
364 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
365 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
366 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
367 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
368 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
369 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
370 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
371 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
372 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
373 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
374 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
375 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
376 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
377 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
378 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
379 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
380 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
381 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
382 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
383 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
384 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
385 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
386 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
387 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
388 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
389 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
390 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
391 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
392 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
393 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
394 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
395 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
396 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
397 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
398 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
399 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
400 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
401 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
402 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
403 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
404 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
405 kCLOCK_FlexComm10 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
406 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
407
408 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
409 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
410} clock_ip_name_t;
411
412/*! @brief Clock name used to get clock frequency. */
413typedef enum _clock_name
414{
415 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
416 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
417 kCLOCK_ClockOut, /*!< CLOCKOUT */
418 kCLOCK_FroHf, /*!< FRO48/96 */
419 kCLOCK_UsbPll, /*!< USB1 PLL */
420 kCLOCK_Mclk, /*!< MCLK */
421 kCLOCK_Fro12M, /*!< FRO12M */
422 kCLOCK_ExtClk, /*!< External Clock */
423 kCLOCK_PllOut, /*!< PLL Output */
424 kCLOCK_UsbClk, /*!< USB input */
425 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
426 kCLOCK_Frg, /*!< Frg Clock */
427 kCLOCK_AsyncApbClk, /*!< Async APB clock */
428} clock_name_t;
429
430/**
431 * Clock source selections for the asynchronous APB clock
432 */
433typedef enum _async_clock_src
434{
435 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
436 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
437 kCLOCK_AsyncAudioPllClk,
438 kCLOCK_AsyncI2cClkFc6,
439
440} async_clock_src_t;
441
442/*! @brief Clock Mux Switches
443 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
444 * starting from LSB upwards
445 *
446 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
447 *
448 */
449
450#define CLK_ATTACH_ID(mux, sel, pos) ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((pos)*12U))
451#define MUX_A_OFFSET(mux) ((mux) << 0U)
452#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
453#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
454
455#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
456#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
457#define GET_ID_ITEM_MUX(connection) ((uint8_t)((connection)&0xFFU))
458#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((connection)&0xF00U) >> 8U) - 1U))
459#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
460#define CLR_ID_ITEM_SEL(connection) ((connection) &= 0xFFFFF0FFU)
461
462#define CM_STICKCLKSEL 0
463#define CM_MAINCLKSELA 1
464#define CM_MAINCLKSELB 2
465#define CM_CLKOUTCLKSELA 3
466#define CM_SYSPLLCLKSEL 5
467#define CM_AUDPLLCLKSEL 7
468#define CM_SPIFICLKSEL 9
469#define CM_ADCASYNCCLKSEL 10
470#define CM_USB0CLKSEL 11
471#define CM_USB1CLKSEL 12
472#define CM_FXCOMCLKSEL0 13
473#define CM_FXCOMCLKSEL1 14
474#define CM_FXCOMCLKSEL2 15
475#define CM_FXCOMCLKSEL3 16
476#define CM_FXCOMCLKSEL4 17
477#define CM_FXCOMCLKSEL5 18
478#define CM_FXCOMCLKSEL6 19
479#define CM_FXCOMCLKSEL7 20
480#define CM_FXCOMCLKSEL8 21
481#define CM_FXCOMCLKSEL9 22
482#define CM_FXCOMCLKSEL10 23
483#define CM_MCLKCLKSEL 25
484#define CM_FRGCLKSEL 27
485#define CM_DMICCLKSEL 28
486#define CM_SCTCLKSEL 29
487#define CM_LCDCLKSEL 30
488#define CM_SDIOCLKSEL 31
489
490#define CM_ASYNCAPB 32U
491
492typedef enum _clock_attach_id
493{
494
495 kSYSTICK_DIV_CLK_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 0),
496 kWDT_OSC_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 1),
497 kOSC32K_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 2),
498 kFRO12M_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 3),
499 kNONE_to_SYSTICKCLK = MUX_A(CM_STICKCLKSEL, 7),
500
501 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
502 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
503 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
504 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
505 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
506 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
507
508 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
509 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
510 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
511 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
512 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
513 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
514 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
515 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
516
517 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
518 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
519 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
520 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
521 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
522
523 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
524 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
525 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
526
527 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
528 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
529 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
530 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
531 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
532 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
533
534 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
535 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
536 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
537 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
538 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
539
540 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
541 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
542 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
543 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
544
545 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
546 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
547 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
548 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
549
550 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
551 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
552 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
553 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
554 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
555 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
556
557 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
558 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
559 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
560 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
561 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
562 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
563
564 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
565 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
566 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
567 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
568 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
569 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
570
571 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
572 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
573 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
574 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
575 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
576 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
577
578 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
579 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
580 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
581 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
582 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
583 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
584
585 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
586 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
587 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
588 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
589 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
590 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
591
592 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
593 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
594 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
595 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
596 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
597 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
598
599 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
600 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
601 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
602 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
603 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
604 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
605
606 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
607 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
608 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
609 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
610 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
611 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
612
613 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
614 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
615 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
616 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
617 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
618 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
619
620 kMAIN_CLK_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 0),
621 kSYS_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 1),
622 kUSB_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 2),
623 kFRO_HF_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 3),
624 kAUDIO_PLL_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 4),
625 kNONE_to_FLEXCOMM10 = MUX_A(CM_FXCOMCLKSEL10, 7),
626
627 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
628 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
629 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
630
631 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
632 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
633 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
634 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
635 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
636
637 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
638 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
639 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
640 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
641 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
642 kWDT_OSC_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
643 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
644
645 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
646 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
647 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
648 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
649 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
650
651 kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
652 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
653 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
654 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
655
656 kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
657 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
658 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
659 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
660 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
661 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
662
663 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
664 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
665 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
666 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
667 kNONE_to_NONE = (int)0x80000000U,
668} clock_attach_id_t;
669
670/* Clock dividers */
671typedef enum _clock_div_name
672{
673 kCLOCK_DivSystickClk = 0,
674 kCLOCK_DivArmTrClkDiv = 1,
675 kCLOCK_DivCan0Clk = 2,
676 kCLOCK_DivCan1Clk = 3,
677 kCLOCK_DivSmartCard0Clk = 4,
678 kCLOCK_DivSmartCard1Clk = 5,
679 kCLOCK_DivAhbClk = 32,
680 kCLOCK_DivClkOut = 33,
681 kCLOCK_DivFrohfClk = 34,
682 kCLOCK_DivSpifiClk = 36,
683 kCLOCK_DivAdcAsyncClk = 37,
684 kCLOCK_DivUsb0Clk = 38,
685 kCLOCK_DivUsb1Clk = 39,
686 kCLOCK_DivFrg = 40,
687 kCLOCK_DivDmicClk = 42,
688 kCLOCK_DivMClk = 43,
689 kCLOCK_DivLcdClk = 44,
690 kCLOCK_DivSctClk = 45,
691 kCLOCK_DivEmcClk = 46,
692 kCLOCK_DivSdioClk = 47
693} clock_div_name_t;
694
695/*******************************************************************************
696 * API
697 ******************************************************************************/
698
699#if defined(__cplusplus)
700extern "C" {
701#endif /* __cplusplus */
702
703static inline void CLOCK_EnableClock(clock_ip_name_t clk)
704{
705 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
706 if (index < 3UL)
707 {
708 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
709 }
710 else
711 {
712 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
713 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
714 }
715}
716
717static inline void CLOCK_DisableClock(clock_ip_name_t clk)
718{
719 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
720 if (index < 3UL)
721 {
722 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
723 }
724 else
725 {
726 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
727 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
728 }
729}
730
731/**
732 * @brief
733 * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code.
734 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed
735 * output is enabled.
736 * Usage: CLOCK_SetupFROClocking(frequency), (frequency must be one of 12, 48 or 96 MHz)
737 * Note: Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is
738 * implemented in ROM code and the FROHF TRIM value is stored in OTP
739 *
740 * @param froFreq target fro frequency.
741 * @return Nothing
742 */
743
744void CLOCK_SetupFROClocking(uint32_t froFreq);
745
746/**
747 * @brief Configure the clock selection muxes.
748 * @param connection : Clock to be configured.
749 * @return Nothing
750 */
751void CLOCK_AttachClk(clock_attach_id_t connection);
752/**
753 * @brief Get the actual clock attach id.
754 * This fuction uses the offset in input attach id, then it reads the actual source value in
755 * the register and combine the offset to obtain an actual attach id.
756 * @param attachId : Clock attach id to get.
757 * @return Clock source value.
758 */
759clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
760/**
761 * @brief Setup peripheral clock dividers.
762 * @param div_name : Clock divider name
763 * @param divided_by_value: Value to be divided
764 * @param reset : Whether to reset the divider counter.
765 * @return Nothing
766 */
767void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
768
769/*! @brief Return Frequency of selected clock
770 * @return Frequency of selected clock
771 */
772uint32_t CLOCK_GetFreq(clock_name_t clockName);
773/*! @brief Return Frequency of FRO 12MHz
774 * @return Frequency of FRO 12MHz
775 */
776uint32_t CLOCK_GetFro12MFreq(void);
777/*! @brief Return Frequency of ClockOut
778 * @return Frequency of ClockOut
779 */
780uint32_t CLOCK_GetClockOutClkFreq(void);
781/*! @brief Return Frequency of Spifi Clock
782 * @return Frequency of Spifi.
783 */
784uint32_t CLOCK_GetSpifiClkFreq(void);
785/*! @brief Return Frequency of Adc Clock
786 * @return Frequency of Adc Clock.
787 */
788uint32_t CLOCK_GetAdcClkFreq(void);
789/*! brief Return Frequency of MCAN Clock
790 * param MCanSel : 0U: MCAN0; 1U: MCAN1
791 * return Frequency of MCAN Clock
792 */
793uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel);
794/*! @brief Return Frequency of Usb0 Clock
795 * @return Frequency of Usb0 Clock.
796 */
797uint32_t CLOCK_GetUsb0ClkFreq(void);
798/*! @brief Return Frequency of Usb1 Clock
799 * @return Frequency of Usb1 Clock.
800 */
801uint32_t CLOCK_GetUsb1ClkFreq(void);
802/*! @brief Return Frequency of MClk Clock
803 * @return Frequency of MClk Clock.
804 */
805uint32_t CLOCK_GetMclkClkFreq(void);
806/*! @brief Return Frequency of SCTimer Clock
807 * @return Frequency of SCTimer Clock.
808 */
809uint32_t CLOCK_GetSctClkFreq(void);
810/*! @brief Return Frequency of SDIO Clock
811 * @return Frequency of SDIO Clock.
812 */
813uint32_t CLOCK_GetSdioClkFreq(void);
814/*! @brief Return Frequency of LCD Clock
815 * @return Frequency of LCD Clock.
816 */
817uint32_t CLOCK_GetLcdClkFreq(void);
818/*! @brief Return Frequency of LCD CLKIN Clock
819 * @return Frequency of LCD CLKIN Clock.
820 */
821uint32_t CLOCK_GetLcdClkIn(void);
822/*! @brief Return Frequency of External Clock
823 * @return Frequency of External Clock. If no external clock is used returns 0.
824 */
825uint32_t CLOCK_GetExtClkFreq(void);
826/*! @brief Return Frequency of Watchdog Oscillator
827 * @return Frequency of Watchdog Oscillator
828 */
829uint32_t CLOCK_GetWdtOscFreq(void);
830/*! @brief Return Frequency of High-Freq output of FRO
831 * @return Frequency of High-Freq output of FRO
832 */
833uint32_t CLOCK_GetFroHfFreq(void);
834/*! @brief Return Frequency of frg
835 * @return Frequency of FRG
836 */
837uint32_t CLOCK_GetFrgClkFreq(void);
838/*! @brief Return Frequency of dmic
839 * @return Frequency of DMIC
840 */
841uint32_t CLOCK_GetDmicClkFreq(void);
842
843/*!
844 * @brief Set FRG Clk
845 * @return
846 * 1: if set FRG CLK successfully.
847 * 0: if set FRG CLK fail.
848 */
849uint32_t CLOCK_SetFRGClock(uint32_t freq);
850
851/*! @brief Return Frequency of PLL
852 * @return Frequency of PLL
853 */
854uint32_t CLOCK_GetPllOutFreq(void);
855/*! @brief Return Frequency of USB PLL
856 * @return Frequency of PLL
857 */
858uint32_t CLOCK_GetUsbPllOutFreq(void);
859/*! @brief Return Frequency of AUDIO PLL
860 * @return Frequency of PLL
861 */
862uint32_t CLOCK_GetAudioPllOutFreq(void);
863/*! @brief Return Frequency of 32kHz osc
864 * @return Frequency of 32kHz osc
865 */
866uint32_t CLOCK_GetOsc32KFreq(void);
867/*! @brief Return Frequency of Core System
868 * @return Frequency of Core System
869 */
870uint32_t CLOCK_GetCoreSysClkFreq(void);
871/*! @brief Return Frequency of I2S MCLK Clock
872 * @return Frequency of I2S MCLK Clock
873 */
874uint32_t CLOCK_GetI2SMClkFreq(void);
875/*! @brief Return Frequency of Flexcomm functional Clock
876 * @return Frequency of Flexcomm functional Clock
877 */
878uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
879
880/*! @brief return FRG Clk
881 * @return Frequency of FRG CLK.
882 */
883uint32_t CLOCK_GetFRGInputClock(void);
884/*! @brief Return Asynchronous APB Clock source
885 * @return Asynchronous APB CLock source
886 */
887__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
888{
889 return (async_clock_src_t)(uint32_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3U);
890}
891/*! @brief Return Frequency of Asynchronous APB Clock
892 * @return Frequency of Asynchronous APB Clock Clock
893 */
894uint32_t CLOCK_GetAsyncApbClkFreq(void);
895/*! @brief Return EMC source
896 * @return EMC source
897 */
898__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void)
899{
900 uint32_t freqtmp;
901
902 freqtmp = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
903 return freqtmp / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
904}
905/*! @brief Return Audio PLL input clock rate
906 * @return Audio PLL input clock rate
907 */
908uint32_t CLOCK_GetAudioPLLInClockRate(void);
909/*! @brief Return System PLL input clock rate
910 * @return System PLL input clock rate
911 */
912uint32_t CLOCK_GetSystemPLLInClockRate(void);
913
914/*! @brief Return System PLL output clock rate
915 * @param recompute : Forces a PLL rate recomputation if true
916 * @return System PLL output clock rate
917 * @note The PLL rate is cached in the driver in a variable as
918 * the rate computation function can take some time to perform. It
919 * is recommended to use 'false' with the 'recompute' parameter.
920 */
921uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
922
923/*! @brief Return System AUDIO PLL output clock rate
924 * @param recompute : Forces a AUDIO PLL rate recomputation if true
925 * @return System AUDIO PLL output clock rate
926 * @note The AUDIO PLL rate is cached in the driver in a variable as
927 * the rate computation function can take some time to perform. It
928 * is recommended to use 'false' with the 'recompute' parameter.
929 */
930uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
931
932/*! @brief Return System USB PLL output clock rate
933 * @param recompute : Forces a USB PLL rate recomputation if true
934 * @return System USB PLL output clock rate
935 * @note The USB PLL rate is cached in the driver in a variable as
936 * the rate computation function can take some time to perform. It
937 * is recommended to use 'false' with the 'recompute' parameter.
938 */
939uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute);
940
941/*! @brief Enables and disables PLL bypass mode
942 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
943 * @return System PLL output clock rate
944 */
945__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
946{
947 if (bypass)
948 {
949 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
950 }
951 else
952 {
953 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
954 }
955}
956
957/*! @brief Check if PLL is locked or not
958 * @return true if the PLL is locked, false if not locked
959 */
960__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
961{
962 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
963}
964
965/*! @brief Check if USB PLL is locked or not
966 * @return true if the USB PLL is locked, false if not locked
967 */
968__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
969{
970 return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0U);
971}
972
973/*! @brief Check if AUDIO PLL is locked or not
974 * @return true if the AUDIO PLL is locked, false if not locked
975 */
976__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
977{
978 return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0U);
979}
980
981/*! @brief Enables and disables SYS OSC
982 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
983 */
984__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
985{
986 if (enable)
987 {
988 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
989 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
990 }
991
992 else
993 {
994 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
995 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
996 }
997}
998
999/*! @brief Store the current PLL rate
1000 * @param rate: Current rate of the PLL
1001 * @return Nothing
1002 **/
1003void CLOCK_SetStoredPLLClockRate(uint32_t rate);
1004
1005/*! @brief Store the current AUDIO PLL rate
1006 * @param rate: Current rate of the PLL
1007 * @return Nothing
1008 **/
1009void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
1010
1011/*! @brief PLL configuration structure flags for 'flags' field
1012 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1013 *
1014 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1015 * configuration structure must be assigned with the expected PLL frequency. If the
1016 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1017 * function and the driver will determine the PLL rate from the currently selected
1018 * PLL source. This flag might be used to configure the PLL input clock more accurately
1019 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1020 *
1021 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1022 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1023 * are not used.<br>
1024 */
1025#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1026#define PLL_CONFIGFLAG_FORCENOFRACT \
1027 (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
1028 SS hardware */
1029
1030/*! @brief PLL configuration structure
1031 *
1032 * This structure can be used to configure the settings for a PLL
1033 * setup structure. Fill in the desired configuration for the PLL
1034 * and call the PLL setup function to fill in a PLL setup structure.
1035 */
1036typedef struct _pll_config
1037{
1038 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1039 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1040 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1041} pll_config_t;
1042
1043/*! @brief PLL setup structure flags for 'flags' field
1044 * These flags control how the PLL setup function sets up the PLL
1045 */
1046#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1047#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1048#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1049
1050/*! @brief PLL setup structure
1051 * This structure can be used to pre-build a PLL setup configuration
1052 * at run-time and quickly set the PLL to the configuration. It can be
1053 * populated with the PLL setup function. If powering up or waiting
1054 * for PLL lock, the PLL input clock source should be configured prior
1055 * to PLL setup.
1056 */
1057typedef struct _pll_setup
1058{
1059 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
1060 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
1061 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
1062 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
1063 uint32_t pllRate; /*!< Acutal PLL rate */
1064 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
1065 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1066} pll_setup_t;
1067
1068/*! @brief PLL status definitions
1069 */
1070typedef enum _pll_error
1071{
1072 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1073 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1074 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1075 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1076 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1077 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1078 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1079 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1080} pll_error_t;
1081
1082/*! @brief USB clock source definition. */
1083typedef enum _clock_usb_src
1084{
1085 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
1086 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
1087 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1088 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
1089
1090 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(
1091 7U) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
1092} clock_usb_src_t;
1093
1094/*! @brief USB PDEL Divider. */
1095typedef enum _usb_pll_psel
1096{
1097 pSel_Divide_1 = 0U,
1098 pSel_Divide_2,
1099 pSel_Divide_4,
1100 pSel_Divide_8
1101} usb_pll_psel;
1102
1103/*! @brief PLL setup structure
1104 * This structure can be used to pre-build a USB PLL setup configuration
1105 * at run-time and quickly set the usb PLL to the configuration. It can be
1106 * populated with the USB PLL setup function. If powering up or waiting
1107 * for USB PLL lock, the PLL input clock source should be configured prior
1108 * to USB PLL setup.
1109 */
1110typedef struct _usb_pll_setup
1111{
1112 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
1113 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
1114 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
1115 bool direct; /*!< USB PLL CCO output control */
1116 bool bypass; /*!< USB PLL inout clock bypass control */
1117 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
1118 uint32_t inputRate; /*!< USB PLL input rate */
1119} usb_pll_setup_t;
1120
1121/*! @brief Return System PLL output clock rate from setup structure
1122 * @param pSetup : Pointer to a PLL setup structure
1123 * @return System PLL output clock rate the setup structure will generate
1124 */
1125uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
1126
1127/*! @brief Return System AUDIO PLL output clock rate from setup structure
1128 * @param pSetup : Pointer to a PLL setup structure
1129 * @return System PLL output clock rate the setup structure will generate
1130 */
1131uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
1132
1133/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
1134 * @param pSetup : Pointer to a PLL setup structure
1135 * @return System PLL output clock rate the setup structure will generate
1136 */
1137uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
1138
1139/*! @brief Return System USB PLL output clock rate from setup structure
1140 * @param pSetup : Pointer to a PLL setup structure
1141 * @return System PLL output clock rate the setup structure will generate
1142 */
1143uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
1144
1145/*! @brief Set PLL output based on the passed PLL setup data
1146 * @param pControl : Pointer to populated PLL control structure to generate setup with
1147 * @param pSetup : Pointer to PLL setup structure to be filled
1148 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1149 * @note Actual frequency for setup may vary from the desired frequency based on the
1150 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1151 */
1152pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1153
1154/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
1155 * @param pControl : Pointer to populated PLL control structure to generate setup with
1156 * @param pSetup : Pointer to PLL setup structure to be filled
1157 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1158 * @note Actual frequency for setup may vary from the desired frequency based on the
1159 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1160 */
1161pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
1162
1163/*! @brief Set PLL output from PLL setup structure (precise frequency)
1164 * @param pSetup : Pointer to populated PLL setup structure
1165 * @param flagcfg : Flag configuration for PLL config structure
1166 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1167 * @note This function will power off the PLL, setup the PLL with the
1168 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1169 * and adjust system voltages to the new PLL rate. The function will not
1170 * alter any source clocks (ie, main systen clock) that may use the PLL,
1171 * so these should be setup prior to and after exiting the function.
1172 */
1173pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1174
1175/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
1176 * @param pSetup : Pointer to populated PLL setup structure
1177 * @param flagcfg : Flag configuration for PLL config structure
1178 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1179 * @note This function will power off the PLL, setup the PLL with the
1180 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1181 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1182 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1183 * so these should be setup prior to and after exiting the function.
1184 */
1185pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
1186
1187/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise
1188 * frequency)
1189 * @param pSetup : Pointer to populated PLL setup structure
1190 * @param flagcfg : Flag configuration for PLL config structure
1191 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1192 * @note This function will power off the PLL, setup the PLL with the
1193 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
1194 * and adjust system voltages to the new AUDIOPLL rate. The function will not
1195 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
1196 * so these should be setup prior to and after exiting the function.
1197 */
1198pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
1199
1200/**
1201 * @brief Set PLL output from PLL setup structure (precise frequency)
1202 * @param pSetup : Pointer to populated PLL setup structure
1203 * @return kStatus_PLL_Success on success, or PLL setup error code
1204 * @note This function will power off the PLL, setup the PLL with the
1205 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1206 * and adjust system voltages to the new PLL rate. The function will not
1207 * alter any source clocks (ie, main systen clock) that may use the PLL,
1208 * so these should be setup prior to and after exiting the function.
1209 */
1210pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
1211
1212/**
1213 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
1214 * @param pSetup : Pointer to populated PLL setup structure
1215 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
1216 * @note This function will power off the PLL, setup the Audio PLL with the
1217 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
1218 * and adjust system voltages to the new PLL rate. The function will not
1219 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
1220 * so these should be setup prior to and after exiting the function.
1221 */
1222pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
1223
1224/**
1225 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
1226 * @param pSetup : Pointer to populated USB PLL setup structure
1227 * @return kStatus_PLL_Success on success, or USB PLL setup error code
1228 * @note This function will power off the USB PLL, setup the PLL with the
1229 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
1230 * and adjust system voltages to the new USB PLL rate. The function will not
1231 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
1232 * so these should be setup prior to and after exiting the function.
1233 */
1234pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
1235
1236/*! @brief Set PLL output based on the multiplier and input frequency
1237 * @param multiply_by : multiplier
1238 * @param input_freq : Clock input frequency of the PLL
1239 * @return Nothing
1240 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1241 * function does not disable or enable PLL power, wait for PLL lock,
1242 * or adjust system voltages. These must be done in the application.
1243 * The function will not alter any source clocks (ie, main systen clock)
1244 * that may use the PLL, so these should be setup prior to and after
1245 * exiting the function.
1246 */
1247void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
1248
1249/*! @brief Disable USB clock.
1250 *
1251 * Disable USB clock.
1252 */
1253static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1254{
1255 CLOCK_DisableClock(clk);
1256}
1257
1258/*! @brief Enable USB Device FS clock.
1259 * @param src : clock source
1260 * @param freq: clock frequency
1261 * Enable USB Device Full Speed clock.
1262 */
1263bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1264
1265/*! @brief Enable USB HOST FS clock.
1266 * @param src : clock source
1267 * @param freq: clock frequency
1268 * Enable USB HOST Full Speed clock.
1269 */
1270bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
1271
1272/*! @brief Set the current Usb PLL Rate
1273 */
1274void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate);
1275
1276/*! @brief Enable USB Device HS clock.
1277 * @param src : clock source
1278 * @param freq: clock frequency
1279 * Enable USB Device High Speed clock.
1280 */
1281bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
1282
1283/*! @brief Enable USB HOST HS clock.
1284 * @param src : clock source
1285 * @param freq: clock frequency
1286 * Enable USB HOST High Speed clock.
1287 */
1288bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
1289
1290#if defined(__cplusplus)
1291}
1292#endif /* __cplusplus */
1293
1294/*! @} */
1295
1296#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:17:21 +0100