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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/LPC54S018.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/LPC54S018.h
new file mode 100644
index 000000000..21d1abacc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/LPC54S018.h
@@ -0,0 +1,22108 @@
+/*
+** ###################################################################
+**     Processors:          LPC54S018JBD208
+**                          LPC54S018JET180
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.0, 2018-04-20
+**     Build:               b200304
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54S018
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2018-04-20)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54S018.h
+ * @version 1.0
+ * @date 2018-04-20
+ * @brief CMSIS Peripheral Access Layer for LPC54S018
+ *
+ * CMSIS Peripheral Access Layer for LPC54S018
+ */
+
+#ifndef _LPC54S018_H_
+#define _LPC54S018_H_                            /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 75                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  FLEXCOMM10_IRQn              = 30,               /**< Flexcomm Interface 10 (SPI, FLEXCOMM) */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56,               /**< Smart card 1 interrupt */
+  Reserved73_IRQn              = 57,               /**< Reserved interrupt */
+  PUF_IRQn                     = 58                /**< PUF interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54S018.h"          /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestFlexcomm0Rx          = 0U,          /**< Flexcomm Interface 0 RX/I2C Slave */
+    kDmaRequestFlexcomm0Tx          = 1U,          /**< Flexcomm Interface 0 TX/I2C Master */
+    kDmaRequestFlexcomm1Rx          = 2U,          /**< Flexcomm Interface 1 RX/I2C Slave */
+    kDmaRequestFlexcomm1Tx          = 3U,          /**< Flexcomm Interface 1 TX/I2C Master */
+    kDmaRequestFlexcomm2Rx          = 4U,          /**< Flexcomm Interface 2 RX/I2C Slave */
+    kDmaRequestFlexcomm2Tx          = 5U,          /**< Flexcomm Interface 2 TX/I2C Master */
+    kDmaRequestFlexcomm3Rx          = 6U,          /**< Flexcomm Interface 3 RX/I2C Slave */
+    kDmaRequestFlexcomm3Tx          = 7U,          /**< Flexcomm Interface 3 TX/I2C Master */
+    kDmaRequestFlexcomm4Rx          = 8U,          /**< Flexcomm Interface 4 RX/I2C Slave */
+    kDmaRequestFlexcomm4Tx          = 9U,          /**< Flexcomm Interface 4 TX/I2C Master */
+    kDmaRequestFlexcomm5Rx          = 10U,         /**< Flexcomm Interface 5 RX/I2C Slave */
+    kDmaRequestFlexcomm5Tx          = 11U,         /**< Flexcomm Interface 5 TX/I2C Master */
+    kDmaRequestFlexcomm6Rx          = 12U,         /**< Flexcomm Interface 6 RX/I2C Slave */
+    kDmaRequestFlexcomm6Tx          = 13U,         /**< Flexcomm Interface 6 TX/I2C Master */
+    kDmaRequestFlexcomm7Rx          = 14U,         /**< Flexcomm Interface 7 RX/I2C Slave */
+    kDmaRequestFlexcomm7Tx          = 15U,         /**< Flexcomm Interface 7 TX/I2C Master */
+    kDmaRequestDMIC0                = 16U,         /**< Digital microphone interface 0 channel 0 */
+    kDmaRequestDMIC1                = 17U,         /**< Digital microphone interface 0 channel 1 */
+    kDmaRequestSPIFI                = 18U,         /**< SPI Flash Interface */
+    kDmaRequestSHA                  = 19U,         /**< Secure Hash Algorithm */
+    kDmaRequestFlexcomm8Rx          = 20U,         /**< Flexcomm Interface 8 RX/I2C Slave */
+    kDmaRequestFlexcomm8Tx          = 21U,         /**< Flexcomm Interface 8 TX/I2C Slave */
+    kDmaRequestFlexcomm9Rx          = 22U,         /**< Flexcomm Interface 9 RX/I2C Slave */
+    kDmaRequestFlexcomm9Tx          = 23U,         /**< Flexcomm Interface 9 TX/I2C Slave */
+    kDmaRequestSMARTCARD0_RX        = 24U,         /**< SMARTCARD0 RX */
+    kDmaRequestSMARTCARD0_TX        = 25U,         /**< SMARTCARD0 TX */
+    kDmaRequestSMARTCARD1_RX        = 26U,         /**< SMARTCARD1 RX */
+    kDmaRequestSMARTCARD1_TX        = 27U,         /**< SMARTCARD1 TX */
+    kDmaRequestFlexcomm10Rx         = 28U,         /**< Flexcomm Interface 10 RX */
+    kDmaRequestFlexcomm10Tx         = 29U,         /**< Flexcomm Interface 10 TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+/*! @{ */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
+ *    the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
+ *    software should program the smallest value in this field that yields this maximum clock rate or
+ *    slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
+ *    be desirable. This field is ignored in the asynchronous operating mode.
+ */
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+/*! ASYNMODE - Select clock mode.
+ *  0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in
+ *       the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to
+ *       eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger.
+ *       In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC
+ *       input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger
+ *       pulse.
+ *  0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
+ */
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher
+ *    conversion rates. A single conversion (including one conversion in a burst or sequence) requires the
+ *    selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when
+ *    the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable
+ *    results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate
+ *    for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system
+ *    clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
+ *  0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field.
+ *  0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field.
+ */
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset
+ *    error is not a concern in the application.
+ *  0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for
+ *       offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may
+ *       be warranted periodically - especially if operating conditions have changed.
+ *  0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC -
+ *       particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set.
+ */
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+/*! TSAMP - Sample Time. The default sampling period (TSAMP = '000') at the start of each conversion
+ *    is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions
+ *    and the output impedance of the analog source, longer sampling times may be required. See
+ *    Section 28.7.10. The TSAMP field specifies the number of additional ADC clock cycles, from zero to
+ *    seven, by which the sample period will be extended. The total conversion time will increase by
+ *    the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A
+ *    complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will
+ *    be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will
+ *    require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock
+ *    cycles. A complete 12-bit conversion will require 17 ADC clocks. 111 - The sample period will be
+ *    extended by seven clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require
+ *    22 ADC clocks.
+ */
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+/*! @} */
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+/*! @{ */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+/*! SEL - Selects the input source for channel 0. All other values are reserved.
+ *  0b00..ADC0_IN0 function.
+ *  0b11..Internal temperature sensor.
+ */
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+/*! @{ */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
+ *    sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
+ *    included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
+ *    and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
+ *    software command, ADC conversions will be performed on each enabled channel, in sequence,
+ *    beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
+ *    is LOW. It is allowed to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
+ *    sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
+ *    to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ */
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
+ *    order to avoid generating a spurious trigger, it is recommended writing to this field only when
+ *    SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
+ *  0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
+ *  0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
+ */
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
+ *    flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
+ *    conversion. There are slightly different criteria for whether or not this bit can be set
+ *    depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
+ *    Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
+ *    synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
+ *    Whether this bit is set or not, a trigger pulse must be maintained for at least one system
+ *    clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
+ *    bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
+ *    will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
+ *    on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
+ *    maintained for one system clock period.
+ *  0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
+ *  0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
+ */
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
+ *    behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
+ *    bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
+ *    conversion sequence. It will consequently always read back as a zero.
+ */
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
+ *    through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
+ *    can be halted by clearing this bit. The sequence currently in progress will be completed before
+ *    conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
+ */
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
+ *    single conversion on the next channel in the sequence instead of the default response of
+ *    launching an entire sequence of conversions. Once all of the channels comprising a sequence have
+ *    been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
+ *    channel. Interrupt generation will still occur either after each individual conversion or at
+ *    the end of the entire sequence, depending on the state of the MODE bit.
+ */
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+/*! LOWPRIO - Set priority for sequence A.
+ *  0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
+ *  0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
+ *       software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
+ *       currently in progress will be terminated. The A sequence that was interrupted will automatically resume
+ *       after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
+ *       conversion sequence will resume from that point.
+ */
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
+ *    will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
+ *    conversion, or the individual channel result registers at the end of the entire sequence. Impacts
+ *    when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
+ *    overrun conditions contribute to an overrun interrupt as described below.
+ *  0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
+ *       conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
+ *       OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
+ *       if enabled.
+ *  0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
+ *       conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
+ *       this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
+ *       interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
+ */
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
+ *    taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
+ *    (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
+ *    immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
+ *    should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
+ *    state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
+ *    triggered immediately upon being enabled.
+ *  0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
+ *       n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
+ *       re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
+ *  0b1..Enabled. Sequence n is enabled.
+ */
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+/*! @{ */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
+ *    performed under conversion sequence associated with this register. The result is a binary
+ *    fraction representing the voltage on the currently-selected input channel as it falls within the
+ *    range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
+ *    than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
+ *    was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
+ *    result has not yet been read.
+ */
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
+ *    within the range established by the designated threshold comparison registers (THRn_LOW and
+ *    THRn_HIGH).
+ */
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
+ *    crossing of the threshold level established by the designated LOW threshold comparison register
+ *    (THRn_LOW) and, if so, in what direction the crossing occurred.
+ */
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
+ *    identifies channel 0, 0001 channel 1, etc.).
+ */
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
+ *    previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
+ *    with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
+ *    interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
+ *    to '0' (and if the overrun interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
+ *    into the RESULT field. It is cleared whenever this register is read. This bit will cause a
+ *    conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
+ *    sequence is set to 0 (and if the interrupt is enabled).
+ */
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+/*! @{ */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
+ *    on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
+ *    as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
+ *    the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
+ *    the voltage on the input was close to, equal to, or greater than that on VREFP.
+ */
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
+ *    was greater than or equal to the value programmed into the designated LOW threshold register
+ *    (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
+ *    programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
+ *    completed conversion was greater than the value programmed into the designated HIGH threshold
+ *    register (THRn_HIGH). 0x3 = Reserved.
+ */
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
+ *    most recent completed conversion on this channel had the same relationship (above or below) to
+ *    the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
+ *    previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
+ *    Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
+ *    previous sample on this channel was above the threshold value established by the designated LOW
+ *    threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
+ *    Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
+ *    - i.e. the previous sample on this channel was below the threshold value established by the
+ *    designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
+ */
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
+ *    relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
+ *    register, etc)
+ */
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
+ *    overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
+ *    is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
+ *    the data related to this channel is read from either of the global SEQn_GDAT registers. This
+ *    bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
+ *    the overrun interrupt is enabled. While it is allowed to include the same channels in both
+ *    conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
+ *    data registers associated with any of the channels that are shared between the two sequences. Any
+ *    erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
+ *    cleared whenever this register is read or when the data related to this channel is read from
+ *    either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
+ *    both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
+ *    the data registers associated with any of the channels that are shared between the two
+ *    sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
+ */
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+/*! @} */
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+/*! THRLOW - Low threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+/*! @} */
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+/*! @{ */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+/*! @{ */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+/*! THRHIGH - High threshold value against which ADC results will be compared
+ */
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+/*! @} */
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+/*! @{ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+/*! CH0_THRSEL - Threshold select for channel 0.
+ *  0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
+ *  0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
+ */
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+/*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+/*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+/*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+/*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+/*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+/*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+/*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+/*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+/*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+/*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+/*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0.
+ */
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+/*! @} */
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+/*! @{ */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+/*! SEQA_INTEN - Sequence A interrupt enable.
+ *  0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
+ *       conversions, depending on the MODE bit in the SEQA_CTRL register.
+ */
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+/*! SEQB_INTEN - Sequence B interrupt enable.
+ *  0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
+ *  0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
+ *       each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
+ *       conversions, depending on the MODE bit in the SEQB_CTRL register.
+ */
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+/*! OVR_INTEN - Overrun interrupt enable.
+ *  0b0..Disabled. The overrun interrupt is disabled.
+ *  0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
+ *       data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
+ *       sequence is 0, then an overrun in the global data register for that sequence will also cause this
+ *       interrupt/DMA trigger to be asserted.
+ */
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
+ *  0b00..Disabled.
+ *  0b01..Outside threshold.
+ *  0b10..Crossing threshold.
+ *  0b11..Reserved
+ */
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+/*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0.
+ */
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+/*! @} */
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+/*! @{ */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
+ *    a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
+ *    writing a 1.
+ */
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
+ */
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
+ */
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
+ */
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
+ */
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
+ */
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
+ */
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
+ */
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
+ */
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
+ */
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
+ */
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
+ */
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
+ */
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
+ */
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
+ */
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
+ */
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
+ *    automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
+ *    is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
+ *    this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
+ *    is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
+ *    automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
+ *    is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
+ *    cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
+ *    register.
+ */
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
+ *    the lower bits of this register are set to 1 (due to an enabled out-of-range or
+ *    threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
+ *    individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
+ *    when all of the individual threshold flags are cleared via writing 1s to those bits.
+ */
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
+ *    registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
+ *    is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
+ *    interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
+ *    of the individual overrun bits have been cleared via reading the corresponding data registers.
+ */
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+/*! @} */
+
+/*! @name STARTUP - ADC Startup register. */
+/*! @{ */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+/*! ADC_ENA - ADC Enable bit. This bit can only be set to a 1 by software. It is cleared
+ *    automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds
+ *    after the ADC is powered up (typically by altering a system-level ADC power control bit).
+ */
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+/*! ADC_INIT - ADC Initialization. After enabling the ADC (setting the ADC_ENA bit), the API routine
+ *    will EITHER set this bit or the CALIB bit in the CALIB register, depending on whether or not
+ *    calibration is required. Setting this bit will launch the 'dummy' conversion cycle that is
+ *    required if a calibration is not performed. It will also reload the stored calibration value from
+ *    a previous calibration unless the BYPASSCAL bit is set. This bit should only be set AFTER the
+ *    ADC_ENA bit is set and after the CALIREQD bit is tested to determine whether a calibration or
+ *    an ADC dummy conversion cycle is required. It should not be set during the same write that
+ *    sets the ADC_ENA bit. This bit can only be set to a '1' by software. It is cleared automatically
+ *    when the 'dummy' conversion cycle completes.
+ */
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+/*! @} */
+
+/*! @name CALIB - ADC Calibration register. */
+/*! @{ */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+/*! CALIB - Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can
+ *    only be set to a '1' by software. It is cleared automatically when the calibration cycle
+ *    completes.
+ */
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+/*! CALREQD - Calibration required. This read-only bit indicates if calibration is required when
+ *    enabling the ADC. CALREQD will be '1' if no calibration has been run since the chip was
+ *    powered-up and if the BYPASSCAL bit in the CTRL register is low. Software will test this bit to
+ *    determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the STARTUP
+ *    register) to launch the ADC initialization process which includes a 'dummy' conversion cycle.
+ *    Note: A 'dummy' conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks
+ *    required for calibration.
+ */
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+/*! CALVALUE - Calibration Value. This read-only field displays the calibration value established
+ *    during last calibration cycle. This value is not typically of any use to the user.
+ */
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AES Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Peripheral_Access_Layer AES Peripheral Access Layer
+ * @{
+ */
+
+/** AES - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t CFG;                               /**< AES Configuration register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      union {                                          /* offset: 0x0 */
+        __IO uint16_t CFG0_15;                           /**< AES Configuration register 0:15, offset: 0x0 */
+        struct {                                         /* offset: 0x0 */
+          __IO uint8_t CFG0_7;                             /**< AES Configuration register 0:7, offset: 0x0 */
+          __IO uint8_t CFG8_15;                            /**< AES Configuration register 8:15, offset: 0x1 */
+        } CFGL;
+      };
+      __IO uint16_t CFG16_31;                          /**< AES Configuration register 16:31, offset: 0x2 */
+    } CFG0_32;
+  };
+  __IO uint32_t CMD;                               /**< AES Command register, offset: 0x4 */
+  __IO uint32_t STAT;                              /**< AES Status register, offset: 0x8 */
+  __IO uint32_t CTR_INCR;                          /**< Counter Increment, offset: 0xC */
+       uint8_t RESERVED_0[16];
+  __O  uint32_t KEY[8];                            /**< Bits of the AES key, array offset: 0x20, array step: 0x4 */
+  __O  uint32_t INTEXT[4];                         /**< Input text bits, array offset: 0x40, array step: 0x4 */
+  __O  uint32_t HOLDING[4];                        /**< Holding register bits, array offset: 0x50, array step: 0x4 */
+  __I  uint32_t OUTTEXT[4];                        /**< Output text bits, array offset: 0x60, array step: 0x4 */
+  __O  uint32_t GF128_Y[4];                        /**< Y bits input of GF128 hash, array offset: 0x70, array step: 0x4 */
+  __I  uint32_t GF128_Z[4];                        /**< Result bits of GF128 hash, array offset: 0x80, array step: 0x4 */
+  __I  uint32_t GCM_TAG[4];                        /**< GCM Tag bits, array offset: 0x90, array step: 0x4 */
+} AES_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AES Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Register_Masks AES Register Masks
+ * @{
+ */
+
+/*! @name CFG - AES Configuration register */
+/*! @{ */
+#define AES_CFG_PROC_EN_MASK                     (0x3U)
+#define AES_CFG_PROC_EN_SHIFT                    (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG_PROC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << AES_CFG_PROC_EN_SHIFT)) & AES_CFG_PROC_EN_MASK)
+#define AES_CFG_GF128_SEL_MASK                   (0x4U)
+#define AES_CFG_GF128_SEL_SHIFT                  (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG_GF128_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CFG_GF128_SEL_SHIFT)) & AES_CFG_GF128_SEL_MASK)
+#define AES_CFG_INTEXT_BSWAP_MASK                (0x10U)
+#define AES_CFG_INTEXT_BSWAP_SHIFT               (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG_INTEXT_BSWAP(x)                  (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_BSWAP_SHIFT)) & AES_CFG_INTEXT_BSWAP_MASK)
+#define AES_CFG_INTEXT_WSWAP_MASK                (0x20U)
+#define AES_CFG_INTEXT_WSWAP_SHIFT               (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG_INTEXT_WSWAP(x)                  (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_WSWAP_SHIFT)) & AES_CFG_INTEXT_WSWAP_MASK)
+#define AES_CFG_OUTTEXT_BSWAP_MASK               (0x40U)
+#define AES_CFG_OUTTEXT_BSWAP_SHIFT              (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG_OUTTEXT_BSWAP(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_BSWAP_SHIFT)) & AES_CFG_OUTTEXT_BSWAP_MASK)
+#define AES_CFG_OUTTEXT_WSWAP_MASK               (0x80U)
+#define AES_CFG_OUTTEXT_WSWAP_SHIFT              (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG_OUTTEXT_WSWAP(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_WSWAP_SHIFT)) & AES_CFG_OUTTEXT_WSWAP_MASK)
+#define AES_CFG_KEY_CFG_MASK                     (0x300U)
+#define AES_CFG_KEY_CFG_SHIFT                    (8U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG_KEY_CFG(x)                       (((uint32_t)(((uint32_t)(x)) << AES_CFG_KEY_CFG_SHIFT)) & AES_CFG_KEY_CFG_MASK)
+#define AES_CFG_INBLK_SEL_MASK                   (0x30000U)
+#define AES_CFG_INBLK_SEL_SHIFT                  (16U)
+/*! INBLK_SEL - Input block select.
+ */
+#define AES_CFG_INBLK_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CFG_INBLK_SEL_SHIFT)) & AES_CFG_INBLK_SEL_MASK)
+#define AES_CFG_HOLD_SEL_MASK                    (0x300000U)
+#define AES_CFG_HOLD_SEL_SHIFT                   (20U)
+/*! HOLD_SEL - Holding register source select.
+ */
+#define AES_CFG_HOLD_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << AES_CFG_HOLD_SEL_SHIFT)) & AES_CFG_HOLD_SEL_MASK)
+#define AES_CFG_OUTTEXT_SEL_MASK                 (0x3000000U)
+#define AES_CFG_OUTTEXT_SEL_SHIFT                (24U)
+/*! OUTTEXT_SEL - Output text source select.
+ */
+#define AES_CFG_OUTTEXT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_SEL_SHIFT)) & AES_CFG_OUTTEXT_SEL_MASK)
+/*! @} */
+
+/*! @name CFG0_15 - AES Configuration register 0:15 */
+/*! @{ */
+#define AES_CFG0_15_PROC_EN_MASK                 (0x3U)
+#define AES_CFG0_15_PROC_EN_SHIFT                (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG0_15_PROC_EN(x)                   (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_PROC_EN_SHIFT)) & AES_CFG0_15_PROC_EN_MASK)
+#define AES_CFG0_15_GF128_SEL_MASK               (0x4U)
+#define AES_CFG0_15_GF128_SEL_SHIFT              (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG0_15_GF128_SEL(x)                 (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_GF128_SEL_SHIFT)) & AES_CFG0_15_GF128_SEL_MASK)
+#define AES_CFG0_15_INTEXT_BSWAP_MASK            (0x10U)
+#define AES_CFG0_15_INTEXT_BSWAP_SHIFT           (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG0_15_INTEXT_BSWAP(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_BSWAP_SHIFT)) & AES_CFG0_15_INTEXT_BSWAP_MASK)
+#define AES_CFG0_15_INTEXT_WSWAP_MASK            (0x20U)
+#define AES_CFG0_15_INTEXT_WSWAP_SHIFT           (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG0_15_INTEXT_WSWAP(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_WSWAP_SHIFT)) & AES_CFG0_15_INTEXT_WSWAP_MASK)
+#define AES_CFG0_15_OUTTEXT_BSWAP_MASK           (0x40U)
+#define AES_CFG0_15_OUTTEXT_BSWAP_SHIFT          (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG0_15_OUTTEXT_BSWAP(x)             (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_BSWAP_MASK)
+#define AES_CFG0_15_OUTTEXT_WSWAP_MASK           (0x80U)
+#define AES_CFG0_15_OUTTEXT_WSWAP_SHIFT          (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG0_15_OUTTEXT_WSWAP(x)             (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_WSWAP_MASK)
+#define AES_CFG0_15_KEY_CFG_MASK                 (0x300U)
+#define AES_CFG0_15_KEY_CFG_SHIFT                (8U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG0_15_KEY_CFG(x)                   (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_KEY_CFG_SHIFT)) & AES_CFG0_15_KEY_CFG_MASK)
+/*! @} */
+
+/*! @name CFG0_7 - AES Configuration register 0:7 */
+/*! @{ */
+#define AES_CFG0_7_PROC_EN_MASK                  (0x3U)
+#define AES_CFG0_7_PROC_EN_SHIFT                 (0U)
+/*! PROC_EN - Process type enable.
+ */
+#define AES_CFG0_7_PROC_EN(x)                    (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_PROC_EN_SHIFT)) & AES_CFG0_7_PROC_EN_MASK)
+#define AES_CFG0_7_GF128_SEL_MASK                (0x4U)
+#define AES_CFG0_7_GF128_SEL_SHIFT               (2U)
+/*! GF128_SEL - GF128 hash selection.
+ */
+#define AES_CFG0_7_GF128_SEL(x)                  (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_GF128_SEL_SHIFT)) & AES_CFG0_7_GF128_SEL_MASK)
+#define AES_CFG0_7_INTEXT_BSWAP_MASK             (0x10U)
+#define AES_CFG0_7_INTEXT_BSWAP_SHIFT            (4U)
+/*! INTEXT_BSWAP - Byte swap input text.
+ */
+#define AES_CFG0_7_INTEXT_BSWAP(x)               (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_BSWAP_SHIFT)) & AES_CFG0_7_INTEXT_BSWAP_MASK)
+#define AES_CFG0_7_INTEXT_WSWAP_MASK             (0x20U)
+#define AES_CFG0_7_INTEXT_WSWAP_SHIFT            (5U)
+/*! INTEXT_WSWAP - Word swap input text.
+ */
+#define AES_CFG0_7_INTEXT_WSWAP(x)               (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_WSWAP_SHIFT)) & AES_CFG0_7_INTEXT_WSWAP_MASK)
+#define AES_CFG0_7_OUTTEXT_BSWAP_MASK            (0x40U)
+#define AES_CFG0_7_OUTTEXT_BSWAP_SHIFT           (6U)
+/*! OUTTEXT_BSWAP - Byte swap output text.
+ */
+#define AES_CFG0_7_OUTTEXT_BSWAP(x)              (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_BSWAP_MASK)
+#define AES_CFG0_7_OUTTEXT_WSWAP_MASK            (0x80U)
+#define AES_CFG0_7_OUTTEXT_WSWAP_SHIFT           (7U)
+/*! OUTTEXT_WSWAP - Word swap output text.
+ */
+#define AES_CFG0_7_OUTTEXT_WSWAP(x)              (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_WSWAP_MASK)
+/*! @} */
+
+/*! @name CFG8_15 - AES Configuration register 8:15 */
+/*! @{ */
+#define AES_CFG8_15_KEY_CFG_MASK                 (0x3U)
+#define AES_CFG8_15_KEY_CFG_SHIFT                (0U)
+/*! KEY_CFG - Key Configuration.
+ */
+#define AES_CFG8_15_KEY_CFG(x)                   (((uint8_t)(((uint8_t)(x)) << AES_CFG8_15_KEY_CFG_SHIFT)) & AES_CFG8_15_KEY_CFG_MASK)
+/*! @} */
+
+/*! @name CFG16_31 - AES Configuration register 16:31 */
+/*! @{ */
+#define AES_CFG16_31_INBLK_SEL_MASK              (0x3U)
+#define AES_CFG16_31_INBLK_SEL_SHIFT             (0U)
+/*! INBLK_SEL - Input block select.
+ */
+#define AES_CFG16_31_INBLK_SEL(x)                (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_INBLK_SEL_SHIFT)) & AES_CFG16_31_INBLK_SEL_MASK)
+#define AES_CFG16_31_HOLD_SEL_MASK               (0x30U)
+#define AES_CFG16_31_HOLD_SEL_SHIFT              (4U)
+/*! HOLD_SEL - Holding register source select.
+ */
+#define AES_CFG16_31_HOLD_SEL(x)                 (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_HOLD_SEL_SHIFT)) & AES_CFG16_31_HOLD_SEL_MASK)
+#define AES_CFG16_31_OUTTEXT_SEL_MASK            (0x300U)
+#define AES_CFG16_31_OUTTEXT_SEL_SHIFT           (8U)
+/*! OUTTEXT_SEL - Output text source select.
+ */
+#define AES_CFG16_31_OUTTEXT_SEL(x)              (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_OUTTEXT_SEL_SHIFT)) & AES_CFG16_31_OUTTEXT_SEL_MASK)
+/*! @} */
+
+/*! @name CMD - AES Command register */
+/*! @{ */
+#define AES_CMD_COPY_TO_Y_MASK                   (0x2U)
+#define AES_CMD_COPY_TO_Y_SHIFT                  (1U)
+/*! COPY_TO_Y - Copy output text to GF128Y.
+ */
+#define AES_CMD_COPY_TO_Y(x)                     (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_TO_Y_SHIFT)) & AES_CMD_COPY_TO_Y_MASK)
+#define AES_CMD_SWITCH_MODE_MASK                 (0x10U)
+#define AES_CMD_SWITCH_MODE_SHIFT                (4U)
+/*! SWITCH_MODE - When this bit is set the mode switches from forward mode (encryption) to reverse
+ *    mode (decryption) or reverse mode to forward mode.
+ */
+#define AES_CMD_SWITCH_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << AES_CMD_SWITCH_MODE_SHIFT)) & AES_CMD_SWITCH_MODE_MASK)
+#define AES_CMD_ABORT_MASK                       (0x100U)
+#define AES_CMD_ABORT_SHIFT                      (8U)
+/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash operation.
+ */
+#define AES_CMD_ABORT(x)                         (((uint32_t)(((uint32_t)(x)) << AES_CMD_ABORT_SHIFT)) & AES_CMD_ABORT_MASK)
+#define AES_CMD_WIPE_MASK                        (0x200U)
+#define AES_CMD_WIPE_SHIFT                       (9U)
+/*! WIPE - When set this bit performs abort, clears KEY and GF128_Y registers and disables cipher.
+ */
+#define AES_CMD_WIPE(x)                          (((uint32_t)(((uint32_t)(x)) << AES_CMD_WIPE_SHIFT)) & AES_CMD_WIPE_MASK)
+/*! @} */
+
+/*! @name STAT - AES Status register */
+/*! @{ */
+#define AES_STAT_IDLE_MASK                       (0x1U)
+#define AES_STAT_IDLE_SHIFT                      (0U)
+/*! IDLE - AES engine Idle.
+ */
+#define AES_STAT_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << AES_STAT_IDLE_SHIFT)) & AES_STAT_IDLE_MASK)
+#define AES_STAT_IN_READY_MASK                   (0x2U)
+#define AES_STAT_IN_READY_SHIFT                  (1U)
+/*! IN_READY - Input text ready.
+ */
+#define AES_STAT_IN_READY(x)                     (((uint32_t)(((uint32_t)(x)) << AES_STAT_IN_READY_SHIFT)) & AES_STAT_IN_READY_MASK)
+#define AES_STAT_OUT_READY_MASK                  (0x4U)
+#define AES_STAT_OUT_READY_SHIFT                 (2U)
+/*! OUT_READY - Output text ready.
+ */
+#define AES_STAT_OUT_READY(x)                    (((uint32_t)(((uint32_t)(x)) << AES_STAT_OUT_READY_SHIFT)) & AES_STAT_OUT_READY_MASK)
+#define AES_STAT_REVERSE_MASK                    (0x10U)
+#define AES_STAT_REVERSE_SHIFT                   (4U)
+/*! REVERSE - Reverse mode.
+ */
+#define AES_STAT_REVERSE(x)                      (((uint32_t)(((uint32_t)(x)) << AES_STAT_REVERSE_SHIFT)) & AES_STAT_REVERSE_MASK)
+#define AES_STAT_KEY_VALID_MASK                  (0x20U)
+#define AES_STAT_KEY_VALID_SHIFT                 (5U)
+/*! KEY_VALID - Key valid.
+ */
+#define AES_STAT_KEY_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << AES_STAT_KEY_VALID_SHIFT)) & AES_STAT_KEY_VALID_MASK)
+/*! @} */
+
+/*! @name CTR_INCR - Counter Increment */
+/*! @{ */
+#define AES_CTR_INCR_CTR_INCR_MASK               (0xFFFFFFFFU)
+#define AES_CTR_INCR_CTR_INCR_SHIFT              (0U)
+/*! CTR_INCR - Increment value for HOLDING register when in counter modes.
+ */
+#define AES_CTR_INCR_CTR_INCR(x)                 (((uint32_t)(((uint32_t)(x)) << AES_CTR_INCR_CTR_INCR_SHIFT)) & AES_CTR_INCR_CTR_INCR_MASK)
+/*! @} */
+
+/*! @name KEY - Bits of the AES key */
+/*! @{ */
+#define AES_KEY_KEY_MASK                         (0xFFFFFFFFU)
+#define AES_KEY_KEY_SHIFT                        (0U)
+/*! KEY - Contains the bits of the AES key.
+ */
+#define AES_KEY_KEY(x)                           (((uint32_t)(((uint32_t)(x)) << AES_KEY_KEY_SHIFT)) & AES_KEY_KEY_MASK)
+/*! @} */
+
+/* The count of AES_KEY */
+#define AES_KEY_COUNT                            (8U)
+
+/*! @name INTEXT - Input text bits */
+/*! @{ */
+#define AES_INTEXT_INTEXT_MASK                   (0xFFFFFFFFU)
+#define AES_INTEXT_INTEXT_SHIFT                  (0U)
+/*! INTEXT - Contains bits of the AES key.
+ */
+#define AES_INTEXT_INTEXT(x)                     (((uint32_t)(((uint32_t)(x)) << AES_INTEXT_INTEXT_SHIFT)) & AES_INTEXT_INTEXT_MASK)
+/*! @} */
+
+/* The count of AES_INTEXT */
+#define AES_INTEXT_COUNT                         (4U)
+
+/*! @name HOLDING - Holding register bits */
+/*! @{ */
+#define AES_HOLDING_HOLDING_MASK                 (0xFFFFFFFFU)
+#define AES_HOLDING_HOLDING_SHIFT                (0U)
+/*! HOLDING - Contains the first word (bits 31:0) of the 128 bit Holding value.
+ */
+#define AES_HOLDING_HOLDING(x)                   (((uint32_t)(((uint32_t)(x)) << AES_HOLDING_HOLDING_SHIFT)) & AES_HOLDING_HOLDING_MASK)
+/*! @} */
+
+/* The count of AES_HOLDING */
+#define AES_HOLDING_COUNT                        (4U)
+
+/*! @name OUTTEXT - Output text bits */
+/*! @{ */
+#define AES_OUTTEXT_OUTTEXT_MASK                 (0xFFFFFFFFU)
+#define AES_OUTTEXT_OUTTEXT_SHIFT                (0U)
+/*! OUTTEXT - Contains the bits of the 128 bit Output text data.
+ */
+#define AES_OUTTEXT_OUTTEXT(x)                   (((uint32_t)(((uint32_t)(x)) << AES_OUTTEXT_OUTTEXT_SHIFT)) & AES_OUTTEXT_OUTTEXT_MASK)
+/*! @} */
+
+/* The count of AES_OUTTEXT */
+#define AES_OUTTEXT_COUNT                        (4U)
+
+/*! @name GF128_Y - Y bits input of GF128 hash */
+/*! @{ */
+#define AES_GF128_Y_GF128_Y_MASK                 (0xFFFFFFFFU)
+#define AES_GF128_Y_GF128_Y_SHIFT                (0U)
+/*! GF128_Y - Contains the bits of the Y input of GF128 hash.
+ */
+#define AES_GF128_Y_GF128_Y(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GF128_Y_GF128_Y_SHIFT)) & AES_GF128_Y_GF128_Y_MASK)
+/*! @} */
+
+/* The count of AES_GF128_Y */
+#define AES_GF128_Y_COUNT                        (4U)
+
+/*! @name GF128_Z - Result bits of GF128 hash */
+/*! @{ */
+#define AES_GF128_Z_GF128_Z_MASK                 (0xFFFFFFFFU)
+#define AES_GF128_Z_GF128_Z_SHIFT                (0U)
+/*! GF128_Z - Contains bits of the result of GF128 hash.
+ */
+#define AES_GF128_Z_GF128_Z(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GF128_Z_GF128_Z_SHIFT)) & AES_GF128_Z_GF128_Z_MASK)
+/*! @} */
+
+/* The count of AES_GF128_Z */
+#define AES_GF128_Z_COUNT                        (4U)
+
+/*! @name GCM_TAG - GCM Tag bits */
+/*! @{ */
+#define AES_GCM_TAG_GCM_TAG_MASK                 (0xFFFFFFFFU)
+#define AES_GCM_TAG_GCM_TAG_SHIFT                (0U)
+/*! GCM_TAG - Contains bits of the 128 bit GCM tag.
+ */
+#define AES_GCM_TAG_GCM_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << AES_GCM_TAG_GCM_TAG_SHIFT)) & AES_GCM_TAG_GCM_TAG_MASK)
+/*! @} */
+
+/* The count of AES_GCM_TAG */
+#define AES_GCM_TAG_COUNT                        (4U)
+
+
+/*!
+ * @}
+ */ /* end of group AES_Register_Masks */
+
+
+/* AES - Peripheral instance base addresses */
+/** Peripheral AES0 base address */
+#define AES0_BASE                                (0x400A1000u)
+/** Peripheral AES0 base pointer */
+#define AES0                                     ((AES_Type *)AES0_BASE)
+/** Array initializer of AES peripheral base addresses */
+#define AES_BASE_ADDRS                           { AES0_BASE }
+/** Array initializer of AES peripheral base pointers */
+#define AES_BASE_PTRS                            { AES0 }
+
+/*!
+ * @}
+ */ /* end of group AES_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+/*! ARST_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+/*! ARST_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+/*! CTIMER3 - Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+/*! CTIMER4 - Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+/*! ACLK_SET - Writing ones to this register sets the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+/*! ACLK_CLR - Writing ones to this register clears the corresponding bit or bits in the
+ *    ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in
+ *    ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+/*! @} */
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+/*! @{ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+/*! SEL - Clock source for asynchronous clock source selector A
+ *  0b00..Main clock (main_clk)
+ *  0b01..FRO 12 MHz (fro_12m)
+ *  0b10..Audio PLL clock.(AUDPLL_BYPASS)
+ *  0b11..fc6 fclk (fc6_fclk)
+ */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DBTP;                              /**< Data Bit Timing Prescaler Register, offset: 0xC */
+  __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
+  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
+  __I  uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
+  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
+  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
+       uint8_t RESERVED_2[16];
+  __I  uint32_t ECR;                               /**< Error Counter Register, offset: 0x40 */
+  __I  uint32_t PSR;                               /**< Protocol Status Register, offset: 0x44 */
+  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator Register, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x50 */
+  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
+  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
+  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
+       uint8_t RESERVED_4[32];
+  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
+  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
+  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
+  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
+  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
+  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
+  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+  __I  uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
+  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
+  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
+  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
+  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
+  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+  __I  uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
+  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
+  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+  __I  uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+  __I  uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+       uint8_t RESERVED_6[8];
+  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
+  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
+  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+       uint8_t RESERVED_7[260];
+  __IO uint32_t MRBA;                              /**< CAN Message RAM Base Address, offset: 0x200 */
+       uint8_t RESERVED_8[508];
+  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
+       uint8_t RESERVED_9[508];
+  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+/*! @{ */
+#define CAN_DBTP_DSJW_MASK                       (0xFU)
+#define CAN_DBTP_DSJW_SHIFT                      (0U)
+/*! DSJW - Data (re)synchronization jump width.
+ */
+#define CAN_DBTP_DSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK                     (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT                    (4U)
+/*! DTSEG2 - Data time segment after sample point.
+ */
+#define CAN_DBTP_DTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK                     (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT                    (8U)
+/*! DTSEG1 - Data time segment before sample point.
+ */
+#define CAN_DBTP_DTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK                       (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT                      (16U)
+/*! DBRP - Data bit rate prescaler.
+ */
+#define CAN_DBTP_DBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK                        (0x800000U)
+#define CAN_DBTP_TDC_SHIFT                       (23U)
+/*! TDC - Transmitter delay compensation.
+ */
+#define CAN_DBTP_TDC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+/*! @} */
+
+/*! @name TEST - Test Register */
+/*! @{ */
+#define CAN_TEST_LBCK_MASK                       (0x10U)
+#define CAN_TEST_LBCK_SHIFT                      (4U)
+/*! LBCK - Loop back mode.
+ */
+#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK                         (0x60U)
+#define CAN_TEST_TX_SHIFT                        (5U)
+/*! TX - Control of transmit pin.
+ */
+#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK                         (0x80U)
+#define CAN_TEST_RX_SHIFT                        (7U)
+/*! RX - Monitors the actual value of the CAN_RXD.
+ */
+#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+/*! @} */
+
+/*! @name CCCR - CC Control Register */
+/*! @{ */
+#define CAN_CCCR_INIT_MASK                       (0x1U)
+#define CAN_CCCR_INIT_SHIFT                      (0U)
+/*! INIT - Initialization.
+ */
+#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK                        (0x2U)
+#define CAN_CCCR_CCE_SHIFT                       (1U)
+/*! CCE - Configuration change enable.
+ */
+#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK                        (0x4U)
+#define CAN_CCCR_ASM_SHIFT                       (2U)
+/*! ASM - Restricted operational mode.
+ */
+#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK                        (0x8U)
+#define CAN_CCCR_CSA_SHIFT                       (3U)
+/*! CSA - Clock Stop Acknowledge.
+ */
+#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK                        (0x10U)
+#define CAN_CCCR_CSR_SHIFT                       (4U)
+/*! CSR - Clock Stop Request.
+ */
+#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK                        (0x20U)
+#define CAN_CCCR_MON_SHIFT                       (5U)
+/*! MON - Bus monitoring mode.
+ */
+#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK                        (0x40U)
+#define CAN_CCCR_DAR_SHIFT                       (6U)
+/*! DAR - Disable automatic retransmission.
+ */
+#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK                       (0x80U)
+#define CAN_CCCR_TEST_SHIFT                      (7U)
+/*! TEST - Test mode enable.
+ */
+#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK                       (0x100U)
+#define CAN_CCCR_FDOE_SHIFT                      (8U)
+/*! FDOE - CAN FD operation enable.
+ */
+#define CAN_CCCR_FDOE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK                       (0x200U)
+#define CAN_CCCR_BRSE_SHIFT                      (9U)
+/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated.
+ */
+#define CAN_CCCR_BRSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
+#define CAN_CCCR_PXHD_MASK                       (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT                      (12U)
+/*! PXHD - Protocol exception handling disable.
+ */
+#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK                       (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT                      (13U)
+/*! EFBI - Edge filtering during bus integration.
+ */
+#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK                        (0x4000U)
+#define CAN_CCCR_TXP_SHIFT                       (14U)
+/*! TXP - Transmit pause.
+ */
+#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK                       (0x8000U)
+#define CAN_CCCR_NISO_SHIFT                      (15U)
+/*! NISO - Non ISO operation.
+ */
+#define CAN_CCCR_NISO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
+/*! @} */
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+/*! @{ */
+#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
+/*! NTSEG2 - Nominal time segment after sample point.
+ */
+#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
+/*! NTSEG1 - Nominal time segment before sample point.
+ */
+#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT                      (16U)
+/*! NBRP - Nominal bit rate prescaler.
+ */
+#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT                      (25U)
+/*! NSJW - Nominal (re)synchronization jump width.
+ */
+#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+/*! @} */
+
+/*! @name TSCC - Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_TSCC_TSS_MASK                        (0x3U)
+#define CAN_TSCC_TSS_SHIFT                       (0U)
+/*! TSS - Timestamp select.
+ */
+#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK                        (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT                       (16U)
+/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
+ */
+#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+/*! @} */
+
+/*! @name TSCV - Timestamp Counter Value */
+/*! @{ */
+#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT                       (0U)
+/*! TSC - Timestamp counter.
+ */
+#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+/*! @} */
+
+/*! @name TOCC - Timeout Counter Configuration */
+/*! @{ */
+#define CAN_TOCC_ETOC_MASK                       (0x1U)
+#define CAN_TOCC_ETOC_SHIFT                      (0U)
+/*! ETOC - Enable timeout counter.
+ */
+#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK                        (0x6U)
+#define CAN_TOCC_TOS_SHIFT                       (1U)
+/*! TOS - Timeout select.
+ */
+#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT                       (16U)
+/*! TOP - Timeout period.
+ */
+#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+/*! @} */
+
+/*! @name TOCV - Timeout Counter Value */
+/*! @{ */
+#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT                       (0U)
+/*! TOC - Timeout counter.
+ */
+#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter Register */
+/*! @{ */
+#define CAN_ECR_TEC_MASK                         (0xFFU)
+#define CAN_ECR_TEC_SHIFT                        (0U)
+/*! TEC - Transmit error counter.
+ */
+#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK                         (0x7F00U)
+#define CAN_ECR_REC_SHIFT                        (8U)
+/*! REC - Receive error counter.
+ */
+#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK                          (0x8000U)
+#define CAN_ECR_RP_SHIFT                         (15U)
+/*! RP - Receive error passive.
+ */
+#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK                         (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT                        (16U)
+/*! CEL - CAN error logging.
+ */
+#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+/*! @} */
+
+/*! @name PSR - Protocol Status Register */
+/*! @{ */
+#define CAN_PSR_LEC_MASK                         (0x7U)
+#define CAN_PSR_LEC_SHIFT                        (0U)
+/*! LEC - Last error code.
+ */
+#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK                         (0x18U)
+#define CAN_PSR_ACT_SHIFT                        (3U)
+/*! ACT - Activity.
+ */
+#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK                          (0x20U)
+#define CAN_PSR_EP_SHIFT                         (5U)
+/*! EP - Error Passive.
+ */
+#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK                          (0x40U)
+#define CAN_PSR_EW_SHIFT                         (6U)
+/*! EW - Warning status.
+ */
+#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK                          (0x80U)
+#define CAN_PSR_BO_SHIFT                         (7U)
+/*! BO - Bus Off Status.
+ */
+#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK                        (0x700U)
+#define CAN_PSR_DLEC_SHIFT                       (8U)
+/*! DLEC - Data phase last error code.
+ */
+#define CAN_PSR_DLEC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK                        (0x800U)
+#define CAN_PSR_RESI_SHIFT                       (11U)
+/*! RESI - ESI flag of the last received CAN FD message.
+ */
+#define CAN_PSR_RESI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK                        (0x1000U)
+#define CAN_PSR_RBRS_SHIFT                       (12U)
+/*! RBRS - BRS flag of last received CAN FD message.
+ */
+#define CAN_PSR_RBRS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK                        (0x2000U)
+#define CAN_PSR_RFDF_SHIFT                       (13U)
+/*! RFDF - Received a CAN FD message.
+ */
+#define CAN_PSR_RFDF(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
+#define CAN_PSR_PXE_MASK                         (0x4000U)
+#define CAN_PSR_PXE_SHIFT                        (14U)
+/*! PXE - Protocol exception event.
+ */
+#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT                       (16U)
+/*! TDCV - Transmitter delay compensation value.
+ */
+#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+/*! @} */
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+/*! @{ */
+#define CAN_TDCR_TDCF_MASK                       (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT                      (0U)
+/*! TDCF - Transmitter delay compensation filter window length.
+ */
+#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT                      (8U)
+/*! TDCO - Transmitter delay compensation offset.
+ */
+#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+/*! @} */
+
+/*! @name IR - Interrupt Register */
+/*! @{ */
+#define CAN_IR_RF0N_MASK                         (0x1U)
+#define CAN_IR_RF0N_SHIFT                        (0U)
+/*! RF0N - Rx FIFO 0 new message.
+ */
+#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK                         (0x2U)
+#define CAN_IR_RF0W_SHIFT                        (1U)
+/*! RF0W - Rx FIFO 0 watermark reached.
+ */
+#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK                         (0x4U)
+#define CAN_IR_RF0F_SHIFT                        (2U)
+/*! RF0F - Rx FIFO 0 full.
+ */
+#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK                         (0x8U)
+#define CAN_IR_RF0L_SHIFT                        (3U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK                         (0x10U)
+#define CAN_IR_RF1N_SHIFT                        (4U)
+/*! RF1N - Rx FIFO 1 new message.
+ */
+#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK                         (0x20U)
+#define CAN_IR_RF1W_SHIFT                        (5U)
+/*! RF1W - Rx FIFO 1 watermark reached.
+ */
+#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK                         (0x40U)
+#define CAN_IR_RF1F_SHIFT                        (6U)
+/*! RF1F - Rx FIFO 1 full.
+ */
+#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK                         (0x80U)
+#define CAN_IR_RF1L_SHIFT                        (7U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK                          (0x100U)
+#define CAN_IR_HPM_SHIFT                         (8U)
+/*! HPM - High priority message.
+ */
+#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK                           (0x200U)
+#define CAN_IR_TC_SHIFT                          (9U)
+/*! TC - Transmission completed.
+ */
+#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK                          (0x400U)
+#define CAN_IR_TCF_SHIFT                         (10U)
+/*! TCF - Transmission cancellation finished.
+ */
+#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK                          (0x800U)
+#define CAN_IR_TFE_SHIFT                         (11U)
+/*! TFE - Tx FIFO empty.
+ */
+#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK                         (0x1000U)
+#define CAN_IR_TEFN_SHIFT                        (12U)
+/*! TEFN - Tx event FIFO new entry.
+ */
+#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK                         (0x2000U)
+#define CAN_IR_TEFW_SHIFT                        (13U)
+/*! TEFW - Tx event FIFO watermark reached.
+ */
+#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK                         (0x4000U)
+#define CAN_IR_TEFF_SHIFT                        (14U)
+/*! TEFF - Tx event FIFO full.
+ */
+#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK                         (0x8000U)
+#define CAN_IR_TEFL_SHIFT                        (15U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK                          (0x10000U)
+#define CAN_IR_TSW_SHIFT                         (16U)
+/*! TSW - Timestamp wraparound.
+ */
+#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK                         (0x20000U)
+#define CAN_IR_MRAF_SHIFT                        (17U)
+/*! MRAF - Message RAM access failure.
+ */
+#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK                          (0x40000U)
+#define CAN_IR_TOO_SHIFT                         (18U)
+/*! TOO - Timeout occurred.
+ */
+#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK                          (0x80000U)
+#define CAN_IR_DRX_SHIFT                         (19U)
+/*! DRX - Message stored in dedicated Rx buffer.
+ */
+#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK                          (0x100000U)
+#define CAN_IR_BEC_SHIFT                         (20U)
+/*! BEC - Bit error corrected.
+ */
+#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK                          (0x200000U)
+#define CAN_IR_BEU_SHIFT                         (21U)
+/*! BEU - Bit error uncorrected.
+ */
+#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK                          (0x400000U)
+#define CAN_IR_ELO_SHIFT                         (22U)
+/*! ELO - Error logging overflow.
+ */
+#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK                           (0x800000U)
+#define CAN_IR_EP_SHIFT                          (23U)
+/*! EP - Error passive.
+ */
+#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK                           (0x1000000U)
+#define CAN_IR_EW_SHIFT                          (24U)
+/*! EW - Warning status.
+ */
+#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK                           (0x2000000U)
+#define CAN_IR_BO_SHIFT                          (25U)
+/*! BO - Bus_Off Status.
+ */
+#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK                          (0x4000000U)
+#define CAN_IR_WDI_SHIFT                         (26U)
+/*! WDI - Watchdog interrupt.
+ */
+#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK                          (0x8000000U)
+#define CAN_IR_PEA_SHIFT                         (27U)
+/*! PEA - Protocol error in arbitration phase.
+ */
+#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK                          (0x10000000U)
+#define CAN_IR_PED_SHIFT                         (28U)
+/*! PED - Protocol error in data phase.
+ */
+#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK                          (0x20000000U)
+#define CAN_IR_ARA_SHIFT                         (29U)
+/*! ARA - Access to reserved address.
+ */
+#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable */
+/*! @{ */
+#define CAN_IE_RF0NE_MASK                        (0x1U)
+#define CAN_IE_RF0NE_SHIFT                       (0U)
+/*! RF0NE - Rx FIFO 0 new message interrupt enable.
+ */
+#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK                        (0x2U)
+#define CAN_IE_RF0WE_SHIFT                       (1U)
+/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK                        (0x4U)
+#define CAN_IE_RF0FE_SHIFT                       (2U)
+/*! RF0FE - Rx FIFO 0 full interrupt enable.
+ */
+#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK                        (0x8U)
+#define CAN_IE_RF0LE_SHIFT                       (3U)
+/*! RF0LE - Rx FIFO 0 message lost interrupt enable.
+ */
+#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK                        (0x10U)
+#define CAN_IE_RF1NE_SHIFT                       (4U)
+/*! RF1NE - Rx FIFO 1 new message interrupt enable.
+ */
+#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK                        (0x20U)
+#define CAN_IE_RF1WE_SHIFT                       (5U)
+/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable.
+ */
+#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK                        (0x40U)
+#define CAN_IE_RF1FE_SHIFT                       (6U)
+/*! RF1FE - Rx FIFO 1 full interrupt enable.
+ */
+#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK                        (0x80U)
+#define CAN_IE_RF1LE_SHIFT                       (7U)
+/*! RF1LE - Rx FIFO 1 message lost interrupt enable.
+ */
+#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK                         (0x100U)
+#define CAN_IE_HPME_SHIFT                        (8U)
+/*! HPME - High priority message interrupt enable.
+ */
+#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK                          (0x200U)
+#define CAN_IE_TCE_SHIFT                         (9U)
+/*! TCE - Transmission completed interrupt enable.
+ */
+#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK                         (0x400U)
+#define CAN_IE_TCFE_SHIFT                        (10U)
+/*! TCFE - Transmission cancellation finished interrupt enable.
+ */
+#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK                         (0x800U)
+#define CAN_IE_TFEE_SHIFT                        (11U)
+/*! TFEE - Tx FIFO empty interrupt enable.
+ */
+#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK                        (0x1000U)
+#define CAN_IE_TEFNE_SHIFT                       (12U)
+/*! TEFNE - Tx event FIFO new entry interrupt enable.
+ */
+#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK                        (0x2000U)
+#define CAN_IE_TEFWE_SHIFT                       (13U)
+/*! TEFWE - Tx event FIFO watermark reached interrupt enable.
+ */
+#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK                        (0x4000U)
+#define CAN_IE_TEFFE_SHIFT                       (14U)
+/*! TEFFE - Tx event FIFO full interrupt enable.
+ */
+#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK                        (0x8000U)
+#define CAN_IE_TEFLE_SHIFT                       (15U)
+/*! TEFLE - Tx event FIFO element lost interrupt enable.
+ */
+#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK                         (0x10000U)
+#define CAN_IE_TSWE_SHIFT                        (16U)
+/*! TSWE - Timestamp wraparound interrupt enable.
+ */
+#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK                        (0x20000U)
+#define CAN_IE_MRAFE_SHIFT                       (17U)
+/*! MRAFE - Message RAM access failure interrupt enable.
+ */
+#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK                         (0x40000U)
+#define CAN_IE_TOOE_SHIFT                        (18U)
+/*! TOOE - Timeout occurred interrupt enable.
+ */
+#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK                         (0x80000U)
+#define CAN_IE_DRXE_SHIFT                        (19U)
+/*! DRXE - Message stored in dedicated Rx buffer interrupt enable.
+ */
+#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK                         (0x100000U)
+#define CAN_IE_BECE_SHIFT                        (20U)
+/*! BECE - Bit error corrected interrupt enable.
+ */
+#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK                         (0x200000U)
+#define CAN_IE_BEUE_SHIFT                        (21U)
+/*! BEUE - Bit error uncorrected interrupt enable.
+ */
+#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK                         (0x400000U)
+#define CAN_IE_ELOE_SHIFT                        (22U)
+/*! ELOE - Error logging overflow interrupt enable.
+ */
+#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK                          (0x800000U)
+#define CAN_IE_EPE_SHIFT                         (23U)
+/*! EPE - Error passive interrupt enable.
+ */
+#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK                          (0x1000000U)
+#define CAN_IE_EWE_SHIFT                         (24U)
+/*! EWE - Warning status interrupt enable.
+ */
+#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK                          (0x2000000U)
+#define CAN_IE_BOE_SHIFT                         (25U)
+/*! BOE - Bus_Off Status interrupt enable.
+ */
+#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK                         (0x4000000U)
+#define CAN_IE_WDIE_SHIFT                        (26U)
+/*! WDIE - Watchdog interrupt enable.
+ */
+#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK                         (0x8000000U)
+#define CAN_IE_PEAE_SHIFT                        (27U)
+/*! PEAE - Protocol error in arbitration phase interrupt enable.
+ */
+#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK                         (0x10000000U)
+#define CAN_IE_PEDE_SHIFT                        (28U)
+/*! PEDE - Protocol error in data phase interrupt enable.
+ */
+#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK                         (0x20000000U)
+#define CAN_IE_ARAE_SHIFT                        (29U)
+/*! ARAE - Access to reserved address interrupt enable.
+ */
+#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+/*! @} */
+
+/*! @name ILS - Interrupt Line Select */
+/*! @{ */
+#define CAN_ILS_RF0NL_MASK                       (0x1U)
+#define CAN_ILS_RF0NL_SHIFT                      (0U)
+/*! RF0NL - Rx FIFO 0 new message interrupt line.
+ */
+#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK                       (0x2U)
+#define CAN_ILS_RF0WL_SHIFT                      (1U)
+/*! RF0WL - Rx FIFO 0 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK                       (0x4U)
+#define CAN_ILS_RF0FL_SHIFT                      (2U)
+/*! RF0FL - Rx FIFO 0 full interrupt line.
+ */
+#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK                       (0x8U)
+#define CAN_ILS_RF0LL_SHIFT                      (3U)
+/*! RF0LL - Rx FIFO 0 message lost interrupt line.
+ */
+#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK                       (0x10U)
+#define CAN_ILS_RF1NL_SHIFT                      (4U)
+/*! RF1NL - Rx FIFO 1 new message interrupt line.
+ */
+#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK                       (0x20U)
+#define CAN_ILS_RF1WL_SHIFT                      (5U)
+/*! RF1WL - Rx FIFO 1 watermark reached interrupt line.
+ */
+#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK                       (0x40U)
+#define CAN_ILS_RF1FL_SHIFT                      (6U)
+/*! RF1FL - Rx FIFO 1 full interrupt line.
+ */
+#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK                       (0x80U)
+#define CAN_ILS_RF1LL_SHIFT                      (7U)
+/*! RF1LL - Rx FIFO 1 message lost interrupt line.
+ */
+#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK                        (0x100U)
+#define CAN_ILS_HPML_SHIFT                       (8U)
+/*! HPML - High priority message interrupt line.
+ */
+#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK                         (0x200U)
+#define CAN_ILS_TCL_SHIFT                        (9U)
+/*! TCL - Transmission completed interrupt line.
+ */
+#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK                        (0x400U)
+#define CAN_ILS_TCFL_SHIFT                       (10U)
+/*! TCFL - Transmission cancellation finished interrupt line.
+ */
+#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK                        (0x800U)
+#define CAN_ILS_TFEL_SHIFT                       (11U)
+/*! TFEL - Tx FIFO empty interrupt line.
+ */
+#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK                       (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT                      (12U)
+/*! TEFNL - Tx event FIFO new entry interrupt line.
+ */
+#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK                       (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT                      (13U)
+/*! TEFWL - Tx event FIFO watermark reached interrupt line.
+ */
+#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK                       (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT                      (14U)
+/*! TEFFL - Tx event FIFO full interrupt line.
+ */
+#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK                       (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT                      (15U)
+/*! TEFLL - Tx event FIFO element lost interrupt line.
+ */
+#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK                        (0x10000U)
+#define CAN_ILS_TSWL_SHIFT                       (16U)
+/*! TSWL - Timestamp wraparound interrupt line.
+ */
+#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK                       (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT                      (17U)
+/*! MRAFL - Message RAM access failure interrupt line.
+ */
+#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK                        (0x40000U)
+#define CAN_ILS_TOOL_SHIFT                       (18U)
+/*! TOOL - Timeout occurred interrupt line.
+ */
+#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK                        (0x80000U)
+#define CAN_ILS_DRXL_SHIFT                       (19U)
+/*! DRXL - Message stored in dedicated Rx buffer interrupt line.
+ */
+#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK                        (0x100000U)
+#define CAN_ILS_BECL_SHIFT                       (20U)
+/*! BECL - Bit error corrected interrupt line.
+ */
+#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK                        (0x200000U)
+#define CAN_ILS_BEUL_SHIFT                       (21U)
+/*! BEUL - Bit error uncorrected interrupt line.
+ */
+#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK                        (0x400000U)
+#define CAN_ILS_ELOL_SHIFT                       (22U)
+/*! ELOL - Error logging overflow interrupt line.
+ */
+#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK                         (0x800000U)
+#define CAN_ILS_EPL_SHIFT                        (23U)
+/*! EPL - Error passive interrupt line.
+ */
+#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK                         (0x1000000U)
+#define CAN_ILS_EWL_SHIFT                        (24U)
+/*! EWL - Warning status interrupt line.
+ */
+#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK                         (0x2000000U)
+#define CAN_ILS_BOL_SHIFT                        (25U)
+/*! BOL - Bus_Off Status interrupt line.
+ */
+#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK                        (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT                       (26U)
+/*! WDIL - Watchdog interrupt line.
+ */
+#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK                        (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT                       (27U)
+/*! PEAL - Protocol error in arbitration phase interrupt line.
+ */
+#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK                        (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT                       (28U)
+/*! PEDL - Protocol error in data phase interrupt line.
+ */
+#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK                        (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT                       (29U)
+/*! ARAL - Access to reserved address interrupt line.
+ */
+#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+/*! @} */
+
+/*! @name ILE - Interrupt Line Enable */
+/*! @{ */
+#define CAN_ILE_EINT0_MASK                       (0x1U)
+#define CAN_ILE_EINT0_SHIFT                      (0U)
+/*! EINT0 - Enable interrupt line 0.
+ */
+#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK                       (0x2U)
+#define CAN_ILE_EINT1_SHIFT                      (1U)
+/*! EINT1 - Enable interrupt line 1.
+ */
+#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+/*! @} */
+
+/*! @name GFC - Global Filter Configuration */
+/*! @{ */
+#define CAN_GFC_RRFE_MASK                        (0x1U)
+#define CAN_GFC_RRFE_SHIFT                       (0U)
+/*! RRFE - Reject remote frames extended.
+ */
+#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK                        (0x2U)
+#define CAN_GFC_RRFS_SHIFT                       (1U)
+/*! RRFS - Reject remote frames standard.
+ */
+#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK                        (0xCU)
+#define CAN_GFC_ANFE_SHIFT                       (2U)
+/*! ANFE - Accept non-matching frames extended.
+ */
+#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK                        (0x30U)
+#define CAN_GFC_ANFS_SHIFT                       (4U)
+/*! ANFS - Accept non-matching frames standard.
+ */
+#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+/*! @} */
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+/*! @{ */
+#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
+/*! FLSSA - Filter list standard start address.
+ */
+#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT                      (16U)
+/*! LSS - List size standard 0 = No standard message ID filter.
+ */
+#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+/*! @} */
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+/*! @{ */
+#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT                    (2U)
+/*! FLESA - Filter list extended start address.
+ */
+#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT                      (16U)
+/*! LSE - List size extended 0 = No extended message ID filter.
+ */
+#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+/*! @} */
+
+/*! @name XIDAM - Extended ID AND Mask */
+/*! @{ */
+#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT                     (0U)
+/*! EIDM - Extended ID mask.
+ */
+#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+/*! @} */
+
+/*! @name HPMS - High Priority Message Status */
+/*! @{ */
+#define CAN_HPMS_BIDX_MASK                       (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT                      (0U)
+/*! BIDX - Buffer index.
+ */
+#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK                        (0xC0U)
+#define CAN_HPMS_MSI_SHIFT                       (6U)
+/*! MSI - Message storage indicator.
+ */
+#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT                      (8U)
+/*! FIDX - Filter index.
+ */
+#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK                       (0x8000U)
+#define CAN_HPMS_FLST_SHIFT                      (15U)
+/*! FLST - Filter list.
+ */
+#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+/*! @} */
+
+/*! @name NDAT1 - New Data 1 */
+/*! @{ */
+#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT                       (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+/*! @} */
+
+/*! @name NDAT2 - New Data 2 */
+/*! @{ */
+#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT                       (0U)
+/*! ND - New Data.
+ */
+#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+/*! @} */
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+/*! @{ */
+#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT                     (2U)
+/*! F0SA - Rx FIFO 0 start address.
+ */
+#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT                      (16U)
+/*! F0S - Rx FIFO 0 size.
+ */
+#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT                     (24U)
+/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT                     (31U)
+/*! F0OM - FIFO 0 operation mode.
+ */
+#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+/*! @} */
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+/*! @{ */
+#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT                     (0U)
+/*! F0FL - Rx FIFO 0 fill level.
+ */
+#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT                     (8U)
+/*! F0GI - Rx FIFO 0 get index.
+ */
+#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT                     (16U)
+/*! F0PI - Rx FIFO 0 put index.
+ */
+#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT                      (24U)
+/*! F0F - Rx FIFO 0 full.
+ */
+#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT                     (25U)
+/*! RF0L - Rx FIFO 0 message lost.
+ */
+#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+/*! @} */
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+/*! @{ */
+#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT                     (0U)
+/*! F0AI - Rx FIFO 0 acknowledge index.
+ */
+#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+/*! @} */
+
+/*! @name RXBC - Rx Buffer Configuration */
+/*! @{ */
+#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT                      (2U)
+/*! RBSA - Rx buffer start address.
+ */
+#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+/*! @} */
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+/*! @{ */
+#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT                     (2U)
+/*! F1SA - Rx FIFO 1 start address.
+ */
+#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT                      (16U)
+/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1.
+ */
+#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT                     (24U)
+/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT                     (31U)
+/*! F1OM - FIFO 1 operation mode.
+ */
+#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+/*! @} */
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+/*! @{ */
+#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT                     (0U)
+/*! F1FL - Rx FIFO 1 fill level.
+ */
+#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT                     (8U)
+/*! F1GI - Rx FIFO 1 get index.
+ */
+#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT                     (16U)
+/*! F1PI - Rx FIFO 1 put index.
+ */
+#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT                      (24U)
+/*! F1F - Rx FIFO 1 full.
+ */
+#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT                     (25U)
+/*! RF1L - Rx FIFO 1 message lost.
+ */
+#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+/*! @} */
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+/*! @{ */
+#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT                     (0U)
+/*! F1AI - Rx FIFO 1 acknowledge index.
+ */
+#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+/*! @} */
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+/*! @{ */
+#define CAN_RXESC_F0DS_MASK                      (0x7U)
+#define CAN_RXESC_F0DS_SHIFT                     (0U)
+/*! F0DS - Rx FIFO 0 data field size.
+ */
+#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK                      (0x70U)
+#define CAN_RXESC_F1DS_SHIFT                     (4U)
+/*! F1DS - Rx FIFO 1 data field size.
+ */
+#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK                      (0x700U)
+#define CAN_RXESC_RBDS_SHIFT                     (8U)
+/*! RBDS - .
+ */
+#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+/*! @} */
+
+/*! @name TXBC - Tx Buffer Configuration */
+/*! @{ */
+#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT                      (2U)
+/*! TBSA - Tx buffers start address.
+ */
+#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT                      (16U)
+/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
+ */
+#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT                      (24U)
+/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue.
+ */
+#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT                      (30U)
+/*! TFQM - Tx FIFO/queue mode.
+ */
+#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+/*! @} */
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+/*! @{ */
+#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT                     (8U)
+/*! TFGI - Tx FIFO get index.
+ */
+#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
+/*! TFQPI - Tx FIFO/queue put index.
+ */
+#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT                     (21U)
+/*! TFQF - Tx FIFO/queue full.
+ */
+#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+/*! @} */
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+/*! @{ */
+#define CAN_TXESC_TBDS_MASK                      (0x7U)
+#define CAN_TXESC_TBDS_SHIFT                     (0U)
+/*! TBDS - Tx buffer data field size.
+ */
+#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+/*! @} */
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+/*! @{ */
+#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT                      (0U)
+/*! TRP - Transmission request pending.
+ */
+#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+/*! @} */
+
+/*! @name TXBAR - Tx Buffer Add Request */
+/*! @{ */
+#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT                       (0U)
+/*! AR - Add request.
+ */
+#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+/*! @} */
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+/*! @{ */
+#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT                       (0U)
+/*! CR - Cancellation request.
+ */
+#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+/*! @} */
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+/*! @{ */
+#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT                       (0U)
+/*! TO - Transmission occurred.
+ */
+#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+/*! @} */
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+/*! @{ */
+#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT                       (0U)
+/*! TO - Cancellation finished.
+ */
+#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+/*! @} */
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+/*! @{ */
+#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT                     (0U)
+/*! TIE - Transmission interrupt enable.
+ */
+#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+/*! @} */
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+/*! @{ */
+#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
+/*! CFIE - Cancellation finished interrupt enable.
+ */
+#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+/*! @} */
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+/*! @{ */
+#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT                     (2U)
+/*! EFSA - Event FIFO start address.
+ */
+#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT                      (16U)
+/*! EFS - Event FIFO size 0 = Tx event FIFO disabled.
+ */
+#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT                     (24U)
+/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled.
+ */
+#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+/*! @} */
+
+/*! @name TXEFS - Tx Event FIFO Status */
+/*! @{ */
+#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT                     (0U)
+/*! EFFL - Event FIFO fill level.
+ */
+#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT                     (8U)
+/*! EFGI - Event FIFO get index.
+ */
+#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT                     (16U)
+/*! EFPI - Event FIFO put index.
+ */
+#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT                      (24U)
+/*! EFF - Event FIFO full.
+ */
+#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT                     (25U)
+/*! TEFL - Tx event FIFO element lost.
+ */
+#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+/*! @} */
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+/*! @{ */
+#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT                     (0U)
+/*! EFAI - Event FIFO acknowledge index.
+ */
+#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+/*! @} */
+
+/*! @name MRBA - CAN Message RAM Base Address */
+/*! @{ */
+#define CAN_MRBA_BA_MASK                         (0xFFFF0000U)
+#define CAN_MRBA_BA_SHIFT                        (16U)
+/*! BA - Base address for the message RAM in the chip memory map.
+ */
+#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+/*! @} */
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+/*! @{ */
+#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT                     (0U)
+/*! ETCP - External timestamp prescaler value.
+ */
+#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT                     (31U)
+/*! ETCE - External timestamp counter enable.
+ */
+#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+/*! @} */
+
+/*! @name ETSCV - External Timestamp Counter Value */
+/*! @{ */
+#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT                     (0U)
+/*! ETSC - External timestamp counter.
+ */
+#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+/*! @{ */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
+ */
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
+ */
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
+ */
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
+ */
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
+ */
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+/*! @} */
+
+/*! @name SEED - CRC seed register */
+/*! @{ */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
+ *    selected bit order and 1's complement pre-processes. A write access to this register will
+ *    overrule the CRC calculation in progresses.
+ */
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name SUM - CRC checksum register */
+/*! @{ */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
+ */
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+/*! @} */
+
+/*! @name WR_DATA - CRC data register */
+/*! @{ */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
+ *    selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
+ *    accept back-to-back transactions.
+ */
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+/*! @{ */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+/*! MR0INT - Interrupt flag for match channel 0.
+ */
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+/*! MR1INT - Interrupt flag for match channel 1.
+ */
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+/*! MR2INT - Interrupt flag for match channel 2.
+ */
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+/*! MR3INT - Interrupt flag for match channel 3.
+ */
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+/*! CR0INT - Interrupt flag for capture channel 0 event.
+ */
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+/*! CR1INT - Interrupt flag for capture channel 1 event.
+ */
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+/*! CR2INT - Interrupt flag for capture channel 2 event.
+ */
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+/*! CR3INT - Interrupt flag for capture channel 3 event.
+ */
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+/*! @} */
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+/*! @{ */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+/*! CEN - Counter enable.
+ *  0b0..Disabled.The counters are disabled.
+ *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
+ */
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+/*! CRST - Counter reset.
+ *  0b0..Disabled. Do nothing.
+ *  0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
+ *       the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
+ */
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+/*! @} */
+
+/*! @name TC - Timer Counter */
+/*! @{ */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+/*! TCVAL - Timer counter value.
+ */
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+/*! @} */
+
+/*! @name PR - Prescale Register */
+/*! @{ */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+/*! PRVAL - Prescale counter value.
+ */
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+/*! @} */
+
+/*! @name PC - Prescale Counter */
+/*! @{ */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+/*! PCVAL - Prescale counter value.
+ */
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+/*! @} */
+
+/*! @name MCR - Match Control Register */
+/*! @{ */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
+ */
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+ */
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
+ */
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+ */
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
+ */
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
+ */
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
+ */
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
+ */
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+ */
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
+ *    (either via a match event or a write to bit 1 of the TCR).
+ */
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+/*! @} */
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+/*! @{ */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+/*! MATCH - Timer counter match value.
+ */
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+/*! @} */
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @{ */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
+ *    the contents of TC. 0 = disabled. 1 = enabled.
+ */
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
+ */
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+/*! @} */
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+/*! @{ */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+/*! CAP - Timer counter capture value.
+ */
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+/*! @} */
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+/*! @{ */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
+ *    the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
+ *    is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
+ *    go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
+ *    if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ */
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
+ *  0b00..Do Nothing.
+ *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
+ *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
+ *  0b11..Toggle. Toggle the corresponding External Match bit/output.
+ */
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+/*! @} */
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+/*! @{ */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
+ *    Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
+ *    is incremented when the Prescale Counter matches the Prescale Register.
+ *  0b00..Timer Mode. Incremented every rising APB bus clock edge.
+ *  0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
+ *  0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
+ *  0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
+ */
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
+ *    CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
+ *    in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
+ *    programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
+ *    same timer.
+ *  0b00..Channel 0. CAPn.0 for CTIMERn
+ *  0b01..Channel 1. CAPn.1 for CTIMERn
+ *  0b10..Channel 2. CAPn.2 for CTIMERn
+ *  0b11..Channel 3. CAPn.3 for CTIMERn
+ */
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
+ *    capture-edge event specified in bits 7:5 occurs.
+ */
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
+ *    timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
+ *    0x3 and 0x6 to 0x7 are reserved.
+ *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
+ *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
+ *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
+ */
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+/*! @} */
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+/*! @{ */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+/*! PWMEN0 - PWM mode enable for channel0.
+ *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
+ */
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+/*! PWMEN1 - PWM mode enable for channel1.
+ *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
+ */
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+/*! PWMEN2 - PWM mode enable for channel2.
+ *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
+ *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
+ */
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
+ *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
+ *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
+ */
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+/*! @} */
+
+/*! @name MSR - Match Shadow Register */
+/*! @{ */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+/*! SHADOWW - Timer counter match shadow value.
+ */
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+/*! @} */
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+/*! @{ */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+/*! ENABLE - DMA controller master enable.
+ *  0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
+ *       disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
+ *  0b1..Enabled. The DMA controller is enabled.
+ */
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+/*! @} */
+
+/*! @name INTSTAT - Interrupt status. */
+/*! @{ */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
+ *  0b0..Not pending. No enabled interrupts are pending.
+ *  0b1..Pending. At least one enabled interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
+ *  0b0..Not pending. No error interrupts are pending.
+ *  0b1..Pending. At least one error interrupt is pending.
+ */
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+/*! @} */
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+/*! @{ */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
+ *    table must begin on a 512 byte boundary.
+ */
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+/*! @} */
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
+ */
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
+ *    the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
+ *    are reserved.
+ */
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
+ */
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
+ *    number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
+ */
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
+ *    not active. 1 = error interrupt is active.
+ */
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
+ *    number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
+ *    interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
+ */
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
+ *    corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
+ *    reserved.
+ */
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt A is not active. 1 = the DMA channel interrupt A is active.
+ */
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
+ *    bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
+ *    interrupt B is not active. 1 = the DMA channel interrupt B is active.
+ */
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
+ *    = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
+ *    VALIDPENDING control bit for DMA channel n
+ */
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
+ *    of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
+ *    sets the TRIG bit for DMA channel n.
+ */
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+/*! @{ */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
+ *    1 = aborts DMA operations on channel n.
+ */
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+/*! @} */
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
+ *    move, any peripheral DMA request associated with that channel can be disabled to prevent any
+ *    interaction between the peripheral and the DMA controller.
+ *  0b0..Disabled. Peripheral DMA requests are disabled.
+ *  0b1..Enabled. Peripheral DMA requests are enabled.
+ */
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.
+ *  0b0..Disabled. Hardware triggering is not used.
+ *  0b1..Enabled. Use hardware triggering.
+ */
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
+ *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
+ *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
+ */
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
+ *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ *  0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ *       0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
+ *       trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
+ *       is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
+ *       current BURSTPOWER length are completed.
+ */
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
+ *  0b0..Single transfer. Hardware trigger causes a single transfer.
+ *  0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
+ *       burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
+ *       hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
+ *       complete.
+ */
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
+ *    SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
+ *    When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
+ *    transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
+ *    contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
+ *    Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
+ *    1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
+ *    total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
+ *    multiple of the burst size.
+ */
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
+ *    'wrapped', meaning that the source address range for each burst will be the same. As an example, this
+ *    could be used to read several sequential registers from a peripheral for each DMA burst,
+ *    reading the same registers again for each burst.
+ *  0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
+ *    'wrapped', meaning that the destination address range for each burst will be the same. As an
+ *    example, this could be used to write several sequential registers to a peripheral for each DMA
+ *    burst, writing the same registers again for each burst.
+ *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
+ *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
+ */
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
+ *    levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
+ */
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (32U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
+ *    corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
+ *  0b0..No effect. No effect on DMA operation.
+ *  0b1..Valid pending.
+ */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
+ *    cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
+ *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
+ *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
+ */
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (32U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+/*! @{ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
+ *    is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
+ *  0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
+ *  0b1..Valid. The current channel descriptor is considered valid.
+ */
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
+ *    descriptor is exhausted. Reloading allows ping-pong and linked transfers.
+ *  0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
+ *  0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+/*! SWTRIG - Software Trigger.
+ *  0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
+ *       the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
+ *  0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
+ *       be used with level triggering when TRIGBURST = 0.
+ */
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+/*! CLRTRIG - Clear Trigger.
+ *  0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
+ *  0b1..Cleared. The trigger is cleared when this descriptor is exhausted
+ */
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
+ *    interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
+ *    convention, interrupt A may be used when only one interrupt flag is needed.
+ *  0b0..No effect.
+ *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
+ */
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+/*! WIDTH - Transfer width used for this DMA channel.
+ *  0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
+ *  0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
+ *  0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
+ *  0b11..Reserved. Reserved setting, do not use.
+ */
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
+ *  0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
+ *  0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
+ *        the usual case when the source is memory.
+ *  0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
+ *  0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
+ *        the destination is a peripheral device.
+ *  0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
+ *        This is the usual case when the destination is memory.
+ *  0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
+ *  0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
+ *    transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
+ *    uses this bit field during transfer to count down. Hence, it cannot be used by software to read
+ *    back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
+ *    transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
+ *    1,024 transfers will be performed.
+ */
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+/*! @} */
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+/*! OSR - Selects the oversample rate for the related input channel.
+ */
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+/*! PDMDIV - PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 = divide by 3 3 = divide by
+ *    4 4 = divide by 6 5 = divide by 8 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 =
+ *    divide by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96 13 = divide by 128 others =
+ *    reserved.
+ */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+/*! @{ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+/*! COMP - Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation = 0 1 = Compensation = 16
+ *    2 = Compensation = 15 3 = Compensation = 13
+ */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+/*! @{ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+/*! GAIN - Gain control, as a positive or negative (two's complement) number of bits to shift.
+ */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+/*! ENABLE - FIFO enable.
+ *  0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
+ *       streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
+ *       period when the data was not needed.
+ *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+/*! RESETN - FIFO reset.
+ *  0b0..Reset the FIFO.
+ *  0b1..Normal operation
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+/*! INTEN - Interrupt enable.
+ *  0b0..FIFO level interrupts are not enabled.
+ *  0b1..FIFO level interrupts are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+/*! DMAEN - DMA enable
+ *  0b0..DMA requests are not enabled.
+ *  0b1..DMA requests based on FIFO level are enabled.
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+/*! TRIGLVL - FIFO trigger level. Selects the data trigger level for interrupt or DMA operation. If
+ *    enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then
+ *    return to the reduced power mode See Section 4.5.66 'Hardware Wake-up control register'. 0 =
+ *    trigger when the FIFO has received one entry (is no longer empty). 1 = trigger when the FIFO has
+ *    received two entries. 15 = trigger when the FIFO has received 16 entries (has become full).
+ */
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+/*! INT - Interrupt flag. Asserted when FIFO data reaches the level specified in the FIFOCTRL
+ *    register. Writing a one to this bit clears the flag. Remark: note that the bus clock to the DMIC
+ *    subsystem must be running in order for an interrupt to occur.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+/*! OVERRUN - Overrun flag. Indicates that a FIFO overflow has occurred at some point. Writing a one
+ *    to this bit clears the flag. This flag does not cause an interrupt.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+/*! UNDERRUN - Underrun flag. Indicates that a FIFO underflow has occurred at some point. Writing a one to this bit clears the flag.
+ */
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+/*! DATA - Data from the top of the input filter FIFO.
+ */
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+/*! PHY_FALL - Capture PDM_DATA
+ *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
+ *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+/*! PHY_HALF - Half rate sampling
+ *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
+ *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate as the decimator is providing.
+ */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+/*! @{ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+/*! DCPOLE - DC block filter
+ *  0b00..Flat response, no filter.
+ *  0b01..155 Hz.
+ *  0b10..78 Hz.
+ *  0b11..39 Hz
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+/*! DCGAIN - Fine gain adjustment in the form of a number of bits to downshift.
+ */
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+/*! SATURATEAT16BIT - Selects 16-bit saturation.
+ *  0b0..Results roll over if out range and do not saturate.
+ *  0b1..If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
+ */
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+/*! @} */
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+/*! @{ */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+/*! EN_CH0 - Enable channel 0. When 1, PDM channel 0 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+/*! EN_CH1 - Enable channel 1. When 1, PDM channel 1 is enabled.
+ */
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+/*! @} */
+
+/*! @name IOCFG - I/O Configuration register */
+/*! @{ */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+/*! CLK_BYPASS0 - Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel 0. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+/*! CLK_BYPASS1 - Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel 1. This provides
+ *    for the possibility of an external codec taking over the PDM bus.
+ */
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+/*! STEREO_DATA0 - Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels in a
+ *    configuration that supports a single stereo digital microphone.
+ */
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+/*! @} */
+
+/*! @name USE2FS - Use 2FS register */
+/*! @{ */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+/*! USE2FS - Use 2FS register
+ *  0b0..Use 1FS output for PCM data.
+ *  0b1..Use 2FS output for PCM data.
+ */
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+/*! @} */
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+/*! @{ */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+/*! INPUTGAIN - Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6 bits 0x03 -4 bits 0x04
+ *    -2 bits 0x05 0 bits (default) 0x06 +2 bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10
+ *    bits 0x0B +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved.
+ */
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+/*! @} */
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+/*! @{ */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+/*! HPFS - High pass filter
+ *  0b00..First filter by-pass.
+ *  0b01..High pass filter with -3dB cut-off at 1750Hz.
+ *  0b10..High pass filter with -3dB cut-off at 215Hz.
+ *  0b11..Reserved.
+ */
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+/*! @} */
+
+/*! @name HWVADST10 - HWVAD control register */
+/*! @{ */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+/*! ST10 - Stage 0
+ *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
+ *  0b1..Reset internal interrupt flag by writing a '1' pulse.
+ */
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+/*! @} */
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+/*! @{ */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+/*! RSTT - Writing a 1 resets all filter values
+ */
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+/*! @} */
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+/*! THGN - Gain value for the noise estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+/*! @} */
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+/*! @{ */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+/*! THGS - Gain value for the signal estimator. Values 0 to 14. 0 corresponds to a gain of 1.
+ */
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+/*! @} */
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+/*! @{ */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+/*! LOWZ - Noise envelope estimator value.
+ */
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+/*! @} */
+
+/*! @name ID - Module Identification register */
+/*! @{ */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+/*! ID - Indicates module ID and the number of channels in this DMIC interface.
+ */
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
+  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
+  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
+  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
+  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
+  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
+  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
+  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
+  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
+  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
+  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
+  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
+  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
+  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
+       uint8_t RESERVED_3[124];
+  struct {                                         /* offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+         uint8_t RESERVED_0[24];
+  } DYNAMIC[4];
+       uint8_t RESERVED_4[128];
+  struct {                                         /* offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+         uint8_t RESERVED_0[4];
+  } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+/*! @{ */
+#define EMC_CONTROL_E_MASK                       (0x1U)
+#define EMC_CONTROL_E_SHIFT                      (0U)
+/*! E - EMC Enable.
+ */
+#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK                       (0x2U)
+#define EMC_CONTROL_M_SHIFT                      (1U)
+/*! M - Address mirror.
+ */
+#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK                       (0x4U)
+#define EMC_CONTROL_L_SHIFT                      (2U)
+/*! L - Low-power mode.
+ */
+#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+/*! @} */
+
+/*! @name STATUS - Provides EMC status information */
+/*! @{ */
+#define EMC_STATUS_B_MASK                        (0x1U)
+#define EMC_STATUS_B_SHIFT                       (0U)
+/*! B - Busy.
+ */
+#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK                        (0x2U)
+#define EMC_STATUS_S_SHIFT                       (1U)
+/*! S - Write buffer status.
+ */
+#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK                       (0x4U)
+#define EMC_STATUS_SA_SHIFT                      (2U)
+/*! SA - Self-refresh acknowledge.
+ */
+#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+/*! @} */
+
+/*! @name CONFIG - Configures operation of the memory controller */
+/*! @{ */
+#define EMC_CONFIG_EM_MASK                       (0x1U)
+#define EMC_CONFIG_EM_SHIFT                      (0U)
+/*! EM - Endian mode.
+ */
+#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK                     (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT                    (8U)
+/*! CLKR - This bit must contain 0 for proper operation of the EMC.
+ */
+#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+/*! @} */
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+/*! @{ */
+#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
+/*! CE - Dynamic memory clock enable.
+ */
+#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
+/*! CS - Dynamic memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
+/*! SR - Self-refresh request, EMCSREFREQ.
+ */
+#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
+/*! MMC - Memory clock control.
+ */
+#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
+/*! I - SDRAM initialization.
+ */
+#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+/*! @} */
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+/*! @{ */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
+/*! REFRESH - Refresh timer.
+ */
+#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+/*! @} */
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+/*! @{ */
+#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
+/*! RD - Read data strategy.
+ */
+#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+/*! @} */
+
+/*! @name DYNAMICRP - Precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
+/*! TRP - Precharge command period.
+ */
+#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+/*! @} */
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+/*! @{ */
+#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
+/*! TRAS - Active to precharge command period.
+ */
+#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+/*! @} */
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+/*! @{ */
+#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
+/*! TSREX - Self-refresh exit time.
+ */
+#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+/*! @} */
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+/*! @{ */
+#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
+/*! TAPR - Last-data-out to active command time.
+ */
+#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+/*! @} */
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+/*! @{ */
+#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
+/*! TDAL - Data-in to active command.
+ */
+#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+/*! @} */
+
+/*! @name DYNAMICWR - Write recovery time */
+/*! @{ */
+#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
+/*! TWR - Write recovery time.
+ */
+#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+/*! @{ */
+#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
+/*! TRC - Active to active command period.
+ */
+#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+/*! @} */
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+/*! @{ */
+#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
+/*! TRFC - Auto-refresh period and auto-refresh to active command period.
+ */
+#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+/*! @} */
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+/*! @{ */
+#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
+/*! TXSR - Exit self-refresh to active command time.
+ */
+#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+/*! @} */
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+/*! @{ */
+#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
+/*! TRRD - Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
+ */
+#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+/*! @} */
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+/*! @{ */
+#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
+/*! TMRD - Load mode register to active command time.
+ */
+#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+/*! @} */
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+/*! @{ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+/*! EXTENDEDWAIT - Extended wait time out.
+ */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+/*! @} */
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
+/*! MD - Memory device.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
+/*! AM0 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
+/*! AM1 - See Table 933.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
+/*! B - Buffer enable.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
+/*! P - Write protect.
+ */
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+/*! @{ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
+/*! RAS - RAS latency (active to read/write delay).
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
+/*! CAS - CAS latency.
+ */
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+/*! @} */
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
+/*! MW - Memory width.
+ */
+#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
+/*! PM - Page mode.
+ */
+#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
+/*! PC - Chip select polarity.
+ */
+#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
+/*! PB - Byte lane state.
+ */
+#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
+/*! EW - Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write
+ *    transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
+ */
+#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
+/*! B - Buffer enable [2].
+ */
+#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
+/*! P - Write protect.
+ */
+#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
+/*! WAITWEN - Wait write enable.
+ */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+/*! @{ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
+/*! WAITOEN - Wait output enable.
+ */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
+/*! WAITRD - .
+ */
+#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+/*! WAITPAGE - Asynchronous page mode read after the first read wait states.
+ */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+/*! @{ */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
+/*! WAITWR - Write wait states.
+ */
+#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+/*! @{ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+/*! WAITTURN - Bus turn-around cycles.
+ */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+/*! @} */
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE                                 (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC                                      ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS                           { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS                            { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MAC_CONFIG;                        /**< MAC configuration register, offset: 0x0 */
+  __IO uint32_t MAC_EXT_CONFIG;                    /**< , offset: 0x4 */
+  __IO uint32_t MAC_FRAME_FILTER;                  /**< MAC frame filter register, offset: 0x8 */
+  __IO uint32_t MAC_WD_TIMEROUT;                   /**< MAC watchdog Timeout register, offset: 0xC */
+       uint8_t RESERVED_0[64];
+  __IO uint32_t MAC_VLAN_TAG;                      /**< MAC vlan tag register, offset: 0x50 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t MAC_TX_FLOW_CTRL_Q[2];             /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< Receive flow control register, offset: 0x90 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MAC_TXQ_PRIO_MAP;                  /**< , offset: 0x98 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MAC_RXQ_CTRL[3];                   /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[4];
+  __I  uint32_t MAC_INTR_STAT;                     /**< Interrupt status register 0x0000, offset: 0xB0 */
+  __IO uint32_t MAC_INTR_EN;                       /**< Interrupt enable register 0x0000, offset: 0xB4 */
+  __I  uint32_t MAC_RXTX_STAT;                     /**< Receive Transmit Status register, offset: 0xB8 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t MAC_PMT_CRTL_STAT;                 /**< , offset: 0xC0 */
+  __IO uint32_t MAC_RWAKE_FRFLT;                   /**< Remote wake-up frame filter, offset: 0xC4 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t MAC_LPI_CTRL_STAT;                 /**< LPI Control and Status Register, offset: 0xD0 */
+  __IO uint32_t MAC_LPI_TIMER_CTRL;                /**< LPI Timers Control register, offset: 0xD4 */
+  __IO uint32_t MAC_LPI_ENTR_TIMR;                 /**< LPI entry Timer register, offset: 0xD8 */
+  __IO uint32_t MAC_1US_TIC_COUNTR;                /**< , offset: 0xDC */
+       uint8_t RESERVED_8[48];
+  __I  uint32_t MAC_VERSION;                       /**< MAC version register, offset: 0x110 */
+  __I  uint32_t MAC_DBG;                           /**< MAC debug register, offset: 0x114 */
+       uint8_t RESERVED_9[4];
+  __I  uint32_t MAC_HW_FEAT[3];                    /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
+       uint8_t RESERVED_10[216];
+  __IO uint32_t MAC_MDIO_ADDR;                     /**< MIDO address Register, offset: 0x200 */
+  __IO uint32_t MAC_MDIO_DATA;                     /**< MDIO Data register, offset: 0x204 */
+       uint8_t RESERVED_11[248];
+  __IO uint32_t MAC_ADDR_HIGH;                     /**< MAC address0 high register, offset: 0x300 */
+  __IO uint32_t MAC_ADDR_LOW;                      /**< MAC address0 low register, offset: 0x304 */
+       uint8_t RESERVED_12[2040];
+  __IO uint32_t MAC_TIMESTAMP_CTRL;                /**< Time stamp control register, offset: 0xB00 */
+  __IO uint32_t MAC_SUB_SCND_INCR;                 /**< Sub-second increment register, offset: 0xB04 */
+  __I  uint32_t MAC_SYS_TIME_SCND;                 /**< System time seconds register, offset: 0xB08 */
+  __I  uint32_t MAC_SYS_TIME_NSCND;                /**< System time nanoseconds register, offset: 0xB0C */
+  __IO uint32_t MAC_SYS_TIME_SCND_UPD;             /**< , offset: 0xB10 */
+  __IO uint32_t MAC_SYS_TIME_NSCND_UPD;            /**< , offset: 0xB14 */
+  __IO uint32_t MAC_SYS_TIMESTMP_ADDEND;           /**< Time stamp addend register, offset: 0xB18 */
+  __IO uint32_t MAC_SYS_TIME_HWORD_SCND;           /**< , offset: 0xB1C */
+  __I  uint32_t MAC_SYS_TIMESTMP_STAT;             /**< Time stamp status register, offset: 0xB20 */
+       uint8_t RESERVED_13[12];
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Tx timestamp status seconds, offset: 0xB34 */
+       uint8_t RESERVED_14[32];
+  __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
+  __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
+       uint8_t RESERVED_15[160];
+  __IO uint32_t MTL_OP_MODE;                       /**< MTL Operation Mode Register, offset: 0xC00 */
+       uint8_t RESERVED_16[28];
+  __I  uint32_t MTL_INTR_STAT;                     /**< MTL Interrupt Status register, offset: 0xC20 */
+       uint8_t RESERVED_17[12];
+  __IO uint32_t MTL_RXQ_DMA_MAP;                   /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
+       uint8_t RESERVED_18[204];
+  struct {                                         /* offset: 0xD00, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_OP_MODE;                  /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_DBG;                      /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
+         uint8_t RESERVED_0[4];
+    __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< , array offset: 0xD18, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< , array offset: 0xD2C, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_OP_MODE;                  /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
+    __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
+    __I  uint32_t MTL_RXQX_DBG;                      /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_CTRL;                     /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
+  } MTL_QUEUE[2];
+       uint8_t RESERVED_19[640];
+  __IO uint32_t DMA_MODE;                          /**< DMA mode register, offset: 0x1000 */
+  __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus mode, offset: 0x1004 */
+  __IO uint32_t DMA_INTR_STAT;                     /**< DMA Interrupt status, offset: 0x1008 */
+  __I  uint32_t DMA_DBG_STAT;                      /**< DMA Debug Status, offset: 0x100C */
+       uint8_t RESERVED_20[240];
+  struct {                                         /* offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< , array offset: 0x1114, array step: 0x80 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< , array offset: 0x111C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< , array offset: 0x1120, array step: 0x80 */
+         uint8_t RESERVED_2[4];
+    __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< , array offset: 0x1128, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< , array offset: 0x112C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
+    __IO uint32_t DMA_CHX_INT_EN;                    /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
+    __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
+         uint8_t RESERVED_3[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
+         uint8_t RESERVED_4[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< , array offset: 0x114C, array step: 0x80 */
+         uint8_t RESERVED_5[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< , array offset: 0x1154, array step: 0x80 */
+         uint8_t RESERVED_6[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_STAT;                      /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
+         uint8_t RESERVED_7[8];
+    __IO uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channelx missed frame count., array offset: 0x116C, array step: 0x80 */
+         uint8_t RESERVED_8[16];
+  } DMA_CH[2];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name MAC_CONFIG - MAC configuration register */
+/*! @{ */
+#define ENET_MAC_CONFIG_RE_MASK                  (0x1U)
+#define ENET_MAC_CONFIG_RE_SHIFT                 (0U)
+/*! RE - Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for
+ *    receiving frames from the MII.
+ */
+#define ENET_MAC_CONFIG_RE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
+#define ENET_MAC_CONFIG_TE_MASK                  (0x2U)
+#define ENET_MAC_CONFIG_TE_SHIFT                 (1U)
+/*! TE - Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII.
+ */
+#define ENET_MAC_CONFIG_TE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
+#define ENET_MAC_CONFIG_PRELEN_MASK              (0xCU)
+#define ENET_MAC_CONFIG_PRELEN_SHIFT             (2U)
+/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes
+ *    that are added to the beginning of every Tx packet.
+ */
+#define ENET_MAC_CONFIG_PRELEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
+#define ENET_MAC_CONFIG_DC_MASK                  (0x10U)
+#define ENET_MAC_CONFIG_DC_SHIFT                 (4U)
+/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC.
+ */
+#define ENET_MAC_CONFIG_DC(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
+#define ENET_MAC_CONFIG_BL_MASK                  (0x60U)
+#define ENET_MAC_CONFIG_BL_SHIFT                 (5U)
+/*! BL - Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time
+ *    delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before
+ *    rescheduling a transmission attempt during retries after a collision.
+ */
+#define ENET_MAC_CONFIG_BL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
+#define ENET_MAC_CONFIG_DR_MASK                  (0x100U)
+#define ENET_MAC_CONFIG_DR_SHIFT                 (8U)
+/*! DR - Disable Retry When this bit is set, the MAC will attempt only one transmission.
+ */
+#define ENET_MAC_CONFIG_DR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
+#define ENET_MAC_CONFIG_DCRS_MASK                (0x200U)
+#define ENET_MAC_CONFIG_DCRS_SHIFT               (9U)
+/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter
+ *    ignores the MII CRS signal during packet transmission in the half-duplex mode.
+ */
+#define ENET_MAC_CONFIG_DCRS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
+#define ENET_MAC_CONFIG_DO_MASK                  (0x400U)
+#define ENET_MAC_CONFIG_DO_SHIFT                 (10U)
+/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of frames when the
+ *    gmii_txen_o is asserted in Half-Duplex mode.
+ */
+#define ENET_MAC_CONFIG_DO(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
+#define ENET_MAC_CONFIG_ECRSFD_MASK              (0x800U)
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT             (11U)
+/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the
+ *    MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode.
+ */
+#define ENET_MAC_CONFIG_ECRSFD(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
+#define ENET_MAC_CONFIG_LM_MASK                  (0x1000U)
+#define ENET_MAC_CONFIG_LM_SHIFT                 (12U)
+/*! LM - Loopback Mode When this bit is set, the MAC operates in loopback mode at MII.
+ */
+#define ENET_MAC_CONFIG_LM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
+#define ENET_MAC_CONFIG_DM_MASK                  (0x2000U)
+#define ENET_MAC_CONFIG_DM_SHIFT                 (13U)
+/*! DM - Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can
+ *    transmit and receive simultaneously.
+ */
+#define ENET_MAC_CONFIG_DM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
+#define ENET_MAC_CONFIG_FES_MASK                 (0x4000U)
+#define ENET_MAC_CONFIG_FES_SHIFT                (14U)
+/*! FES - Speed Indicates the speed in Fast Ethernet (MII) mode: This bit is reserved (RO) by
+ *    default and is enabled only when RMII/SMII is enabled during configuration.
+ */
+#define ENET_MAC_CONFIG_FES(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
+#define ENET_MAC_CONFIG_PS_MASK                  (0x8000U)
+#define ENET_MAC_CONFIG_PS_SHIFT                 (15U)
+/*! PS - Portselect.
+ */
+#define ENET_MAC_CONFIG_PS(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
+#define ENET_MAC_CONFIG_JE_MASK                  (0x10000U)
+#define ENET_MAC_CONFIG_JE_SHIFT                 (16U)
+/*! JE - Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022
+ *    bytes for tagged frames) without reporting a giant frame error in the receive frame status.
+ */
+#define ENET_MAC_CONFIG_JE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
+#define ENET_MAC_CONFIG_JD_MASK                  (0x20000U)
+#define ENET_MAC_CONFIG_JD_SHIFT                 (17U)
+/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter,
+ *    and can transfer frames of up to 16,384 bytes.
+ */
+#define ENET_MAC_CONFIG_JD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
+#define ENET_MAC_CONFIG_BE_MASK                  (0x40000U)
+#define ENET_MAC_CONFIG_BE_SHIFT                 (18U)
+/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
+ *    transmission in the MII half-duplex mode.
+ */
+#define ENET_MAC_CONFIG_BE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
+#define ENET_MAC_CONFIG_WD_MASK                  (0x80000U)
+#define ENET_MAC_CONFIG_WD_SHIFT                 (19U)
+/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver,
+ *    and can receive frames of up to 16,384 bytes.
+ */
+#define ENET_MAC_CONFIG_WD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
+#define ENET_MAC_CONFIG_ACS_MASK                 (0x100000U)
+#define ENET_MAC_CONFIG_ACS_SHIFT                (20U)
+/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
+ *    on the incoming packets only if the value of the length field is less than 1,536 bytes.
+ */
+#define ENET_MAC_CONFIG_ACS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
+#define ENET_MAC_CONFIG_CST_MASK                 (0x200000U)
+#define ENET_MAC_CONFIG_CST_SHIFT                (21U)
+/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
+ *    packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
+ *    the packet to the application.
+ */
+#define ENET_MAC_CONFIG_CST(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
+#define ENET_MAC_CONFIG_S2KP_MASK                (0x400000U)
+#define ENET_MAC_CONFIG_S2KP_SHIFT               (22U)
+/*! S2KP - IEEE 802.
+ */
+#define ENET_MAC_CONFIG_S2KP(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
+#define ENET_MAC_CONFIG_GPSLCE_MASK              (0x800000U)
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT             (23U)
+/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the
+ *    value in GPSL field in MAC Ext Configuration register to declare a received packet as Giant packet.
+ */
+#define ENET_MAC_CONFIG_GPSLCE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
+#define ENET_MAC_CONFIG_IPG_MASK                 (0x7000000U)
+#define ENET_MAC_CONFIG_IPG_SHIFT                (24U)
+/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
+ */
+#define ENET_MAC_CONFIG_IPG(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
+#define ENET_MAC_CONFIG_IPC_MASK                 (0x8000000U)
+#define ENET_MAC_CONFIG_IPC_SHIFT                (27U)
+/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or
+ *    IPv6 TCP, UDP, or ICMP payload checksum checking.
+ */
+#define ENET_MAC_CONFIG_IPC(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
+/*! @} */
+
+/*! @name MAC_EXT_CONFIG -  */
+/*! @{ */
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK            (0x3FFFU)
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT           (0U)
+/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed
+ *    in this field in units of bytes, the MAC declares the received packet as Giant packet.
+ */
+#define ENET_MAC_EXT_CONFIG_GPSL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK           (0x10000U)
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT          (16U)
+/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does
+ *    not check the CRC field in the received packets.
+ */
+#define ENET_MAC_EXT_CONFIG_DCRCC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK            (0x20000U)
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT           (17U)
+/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol
+ *    packets (Ether Type 0x8809) and provides the Rx status.
+ */
+#define ENET_MAC_EXT_CONFIG_SPEN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
+#define ENET_MAC_EXT_CONFIG_USP_MASK             (0x40000U)
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT            (18U)
+/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow
+ *    Protocol packets with unicast address of the station specified in the MAC Address High Table 747 and
+ *    MAC Address Low Table 748 registers.
+ */
+#define ENET_MAC_EXT_CONFIG_USP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
+/*! @} */
+
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */
+/*! @{ */
+#define ENET_MAC_FRAME_FILTER_PR_MASK            (0x1U)
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT           (0U)
+/*! PR - Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames
+ *    regardless of its destination or source address.
+ */
+#define ENET_MAC_FRAME_FILTER_PR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK          (0x8U)
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT         (3U)
+/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse
+ *    filtering mode for the DA address comparison for both unicast and multicast frames.
+ */
+#define ENET_MAC_FRAME_FILTER_DAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_PM_MASK            (0x10U)
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT           (4U)
+/*! PM - Pass All Multicast When set, this bit indicates that all received frames with a multicast
+ *    destination address (first bit in the destination address field is '1') are passed.
+ */
+#define ENET_MAC_FRAME_FILTER_PM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
+#define ENET_MAC_FRAME_FILTER_DBF_MASK           (0x20U)
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT          (5U)
+/*! DBF - Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames.
+ */
+#define ENET_MAC_FRAME_FILTER_DBF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
+#define ENET_MAC_FRAME_FILTER_PCF_MASK           (0xC0U)
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT          (6U)
+/*! PCF - Pass Control Frames These bits control the forwarding of all control frames (including
+ *    unicast and multicast PAUSE frames).
+ */
+#define ENET_MAC_FRAME_FILTER_PCF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK          (0x100U)
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT         (8U)
+/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the
+ *    inverse filtering mode for SA address comparison.
+ */
+#define ENET_MAC_FRAME_FILTER_SAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAF_MASK           (0x200U)
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT          (9U)
+/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the
+ *    received packets with the values programmed in the enabled SA registers.
+ */
+#define ENET_MAC_FRAME_FILTER_SAF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
+#define ENET_MAC_FRAME_FILTER_RA_MASK            (0x80000000U)
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT           (31U)
+/*! RA - Receive all When this bit is set, the MAC Receiver module passes to the Application all
+ *    frames received irrespective of whether they pass the address filter.
+ */
+#define ENET_MAC_FRAME_FILTER_RA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
+/*! @} */
+
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
+/*! @{ */
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK            (0xFU)
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT           (0U)
+/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC Configuration register
+ *    Table 722 is reset, this field is used as watchdog timeout for a received packet.
+ */
+#define ENET_MAC_WD_TIMEROUT_WTO(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK            (0x100U)
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT           (8U)
+/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC Configuration
+ *    register Table 722 is reset, the WTO field is used as watchdog timeout for a received packet.
+ */
+#define ENET_MAC_WD_TIMEROUT_PWE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
+/*! @} */
+
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */
+/*! @{ */
+#define ENET_MAC_VLAN_TAG_VL_MASK                (0xFFFFU)
+#define ENET_MAC_VLAN_TAG_VL_SHIFT               (0U)
+/*! VL - VLAN Tag Identifier for Receive Packets.
+ */
+#define ENET_MAC_VLAN_TAG_VL(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
+#define ENET_MAC_VLAN_TAG_ETV_MASK               (0x10000U)
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT              (16U)
+/*! ETV - Enable 12-Bit VLAN Tag Comparison.
+ */
+#define ENET_MAC_VLAN_TAG_ETV(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
+#define ENET_MAC_VLAN_TAG_VTIM_MASK              (0x20000U)
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT             (17U)
+/*! VTIM - VLAN Tag Inverse Match Enable.
+ */
+#define ENET_MAC_VLAN_TAG_VTIM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
+#define ENET_MAC_VLAN_TAG_ESVL_MASK              (0x40000U)
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT             (18U)
+/*! ESVL - Enable S-VLAN.
+ */
+#define ENET_MAC_VLAN_TAG_ESVL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK            (0x80000U)
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT           (19U)
+/*! ERSVLM - Enable Receive S-VLAN Match.
+ */
+#define ENET_MAC_VLAN_TAG_ERSVLM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK            (0x100000U)
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT           (20U)
+/*! DOVLTC - Disable VLAN Type Check.
+ */
+#define ENET_MAC_VLAN_TAG_DOVLTC(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
+#define ENET_MAC_VLAN_TAG_EVLS_MASK              (0x600000U)
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT             (21U)
+/*! EVLS - Enable VLAN Tag Stripping on Receive.
+ */
+#define ENET_MAC_VLAN_TAG_EVLS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK            (0x1000000U)
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT           (24U)
+/*! EVLRXS - Enable VLAN Tag in Rx status.
+ */
+#define ENET_MAC_VLAN_TAG_EVLRXS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
+#define ENET_MAC_VLAN_TAG_VTHM_MASK              (0x2000000U)
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT             (25U)
+/*! VTHM - Disable VLAN Type Check.
+ */
+#define ENET_MAC_VLAN_TAG_VTHM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK             (0x4000000U)
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT            (26U)
+/*! EDVLP - Enable Double VLAN Processing.
+ */
+#define ENET_MAC_VLAN_TAG_EDVLP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK            (0x8000000U)
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT           (27U)
+/*! ERIVLT - Enable Inner VLAN Tag.
+ */
+#define ENET_MAC_VLAN_TAG_ERIVLT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK             (0x30000000U)
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT            (28U)
+/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive.
+ */
+#define ENET_MAC_VLAN_TAG_EIVLS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK           (0x80000000U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT          (31U)
+/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status.
+ */
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
+/*! @} */
+
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
+/*! @{ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK         (0x1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT        (0U)
+/*! FCB - Flow Control Busy/Backpressure Activate This register field can be read by the application
+ *    (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is
+ *    cleared to 0 by the core (Self Clear).
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK         (0x2U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT        (1U)
+/*! TFE - Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables
+ *    the flow control operation to transmit Pause frames.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK         (0x70U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT        (4U)
+/*! PLT - Pause Low Threshold This field configures the threshold of the PAUSE timer at which the
+ *    input flow control signal is checked for automatic retransmission of PAUSE Frame.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK        (0x80U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT       (7U)
+/*! DZPQ - Disable Zero-Quanta Pause When set, this bit disables the automatic generation of
+ *    Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK          (0xFFFF0000U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT         (16U)
+/*! PT - Pause time This field holds the value to be used in the Pause Time field in the transmit control frame.
+ */
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT            (2U)
+
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
+/*! @{ */
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK           (0x1U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT          (0U)
+/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex
+ *    mode, the MAC decodes the received Pause packet and disables its transmitter for a specified
+ *    (Pause) time.
+ */
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK            (0x2U)
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT           (1U)
+/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast
+ *    address specified in the IEEE 802.
+ */
+#define ENET_MAC_RX_FLOW_CTRL_UP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
+/*! @} */
+
+/*! @name MAC_TXQ_PRIO_MAP -  */
+/*! @{ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK         (0xFFU)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT        (0U)
+/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software.
+ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK         (0xFF00U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT        (8U)
+/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
+ */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
+/*! @} */
+
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
+/*! @{ */
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK             (0x7U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT            (0U)
+/*! AVCPQ - AV Untagged Control Packets Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK             (0xFFU)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT            (0U)
+/*! PSRQ0 - Priorities Selected in the Receive Queue 0.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK            (0x3U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT           (0U)
+/*! RXQ0EN - Receive Queue 0 Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK            (0xCU)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT           (2U)
+/*! RXQ1EN - Receive Queue 1 Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK            (0x70U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT           (4U)
+/*! AVPTPQ - AV PTP Packets Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK             (0xFF00U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT            (8U)
+/*! PSRQ1 - Priorities Selected in the Receive Queue 1.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK               (0x7000U)
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT              (12U)
+/*! UPQ - Untagged Packet Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_UPQ(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK             (0x70000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT            (16U)
+/*! MCBCQ - Multicast and Broadcast Queue.
+ */
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK             (0xFF0000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT            (16U)
+/*! PSRQ2 - Priorities Selected in the Receive Queue 2.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK           (0x100000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT          (20U)
+/*! MCBCQEN - Multicast and Broadcast Queue Enable.
+ */
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK             (0xFF000000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT            (24U)
+/*! PSRQ3 - Priorities Selected in the Receive Queue 3.
+ */
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_RXQ_CTRL */
+#define ENET_MAC_RXQ_CTRL_COUNT                  (3U)
+
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
+/*! @{ */
+#define ENET_MAC_INTR_STAT_PHYIS_MASK            (0x8U)
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT           (3U)
+/*! PHYIS - PHY Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_PHYIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
+#define ENET_MAC_INTR_STAT_PMTIS_MASK            (0x10U)
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT           (4U)
+/*! PMTIS - PMT Interrupt Status.
+ */
+#define ENET_MAC_INTR_STAT_PMTIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
+#define ENET_MAC_INTR_STAT_LPIIS_MASK            (0x20U)
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT           (5U)
+/*! LPIIS - LPI Interrupt Status.
+ */
+#define ENET_MAC_INTR_STAT_LPIIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
+#define ENET_MAC_INTR_STAT_TSIS_MASK             (0x1000U)
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT            (12U)
+/*! TSIS - Timestamp interrupt status.
+ */
+#define ENET_MAC_INTR_STAT_TSIS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK          (0x2000U)
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT         (13U)
+/*! TXSTSIS - Transmit Status Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_TXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK          (0x4000U)
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT         (14U)
+/*! RXSTSIS - Receive Status Interrupt.
+ */
+#define ENET_MAC_INTR_STAT_RXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
+/*! @} */
+
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
+/*! @{ */
+#define ENET_MAC_INTR_EN_PHYIE_MASK              (0x8U)
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT             (3U)
+/*! PHYIE - PHY Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_PHYIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
+#define ENET_MAC_INTR_EN_PMTIE_MASK              (0x10U)
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT             (4U)
+/*! PMTIE - PMT Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_PMTIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
+#define ENET_MAC_INTR_EN_LPIIE_MASK              (0x20U)
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT             (5U)
+/*! LPIIE - LPI Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_LPIIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
+#define ENET_MAC_INTR_EN_TSIE_MASK               (0x1000U)
+#define ENET_MAC_INTR_EN_TSIE_SHIFT              (12U)
+/*! TSIE - Timestamp Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_TSIE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK            (0x2000U)
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT           (13U)
+/*! TXSTSIE - Transmit Status Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_TXSTSIE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK            (0x4000U)
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT           (14U)
+/*! RXSTSIS - Receive Status Interrupt Enable.
+ */
+#define ENET_MAC_INTR_EN_RXSTSIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
+/*! @} */
+
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
+/*! @{ */
+#define ENET_MAC_RXTX_STAT_TJT_MASK              (0x1U)
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT             (0U)
+/*! TJT - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
+ *    signal because of the setting of PHYIS bit in MAC Interrupt Status register Table 731.
+ */
+#define ENET_MAC_RXTX_STAT_TJT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
+#define ENET_MAC_RXTX_STAT_NCARR_MASK            (0x2U)
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT           (1U)
+/*! NCARR - No Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758, this
+ *    bit indicates that the carrier signal from the PHY is not present at the end of preamble
+ *    transmission.
+ */
+#define ENET_MAC_RXTX_STAT_NCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
+#define ENET_MAC_RXTX_STAT_LCARR_MASK            (0x4U)
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT           (2U)
+/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
+ *    this bit indicates that the loss of carrier occurred during packet transmission, that is, the
+ *    PHY Carrier signal was inactive for one or more transmission clock periods during packet
+ *    transmission.
+ */
+#define ENET_MAC_RXTX_STAT_LCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK            (0x8U)
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT           (3U)
+/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MTL Operation Mode register Table
+ *    758 and the DC bit is set in the MAC Configuration register Table 758, this bit indicates that
+ *    the transmission ended because of excessive deferral of over 24,288 bit times (155,680 when
+ *    Jumbo packet is enabled).
+ */
+#define ENET_MAC_RXTX_STAT_EXDEF(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
+#define ENET_MAC_RXTX_STAT_LCOL_MASK             (0x10U)
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT            (4U)
+/*! LCOL - Late Collision When the DTXSTS bit is set in the MTL Operation Mode register Table 758,
+ *    this bit indicates that the packet transmission aborted because a collision occurred after the
+ *    collision window (64 bytes including Preamble in MII mode).
+ */
+#define ENET_MAC_RXTX_STAT_LCOL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK            (0x20U)
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT           (5U)
+/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MTL Operation Mode register Table
+ *    758, this bit indicates that the transmission aborted after 16 successive collisions while
+ *    attempting to transmit the current packet.
+ */
+#define ENET_MAC_RXTX_STAT_EXCOL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
+#define ENET_MAC_RXTX_STAT_RWT_MASK              (0x100U)
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT             (8U)
+/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
+ *    bytes is received (10,240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
+ *    MAC Configuration register Table 722.
+ */
+#define ENET_MAC_RXTX_STAT_RWT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
+/*! @} */
+
+/*! @name MAC_PMT_CRTL_STAT -  */
+/*! @{ */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK       (0x1U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT      (0U)
+/*! PWRDWN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
+ *    entered the LPI state because of the setting of the LPIEN bit.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK     (0x2U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT    (1U)
+/*! MGKPKTEN - Magic Packet Enable.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK     (0x4U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT    (2U)
+/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
+ *    generated when the MAC receives a remote wake-up packet.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK     (0x20U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT    (5U)
+/*! MGKPRCVD - Magic Packet Received.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK     (0x40U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT    (6U)
+/*! RWKPRCVD - Remote Wake-Up Packet Received.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK    (0x200U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT   (9U)
+/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
+ *    address recognition is detected as a remote wake-up packet.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK       (0x400U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT      (10U)
+/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
+ *    MAC receiver drops all received frames until it receives the expected wake-up frame.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK       (0x1F000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT      (24U)
+/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7) of the Remote
+ *    Wake-up Packet Filter register pointer.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK   (0x80000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT  (31U)
+/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
+ *    remote wake-up packet filter register pointer is reset to 3'b000.
+ */
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
+/*! @} */
+
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
+/*! @{ */
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK           (0xFFFFFFFFU)
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT          (0U)
+/*! ADDR - WKUPFMFILTER address.
+ */
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
+/*! @{ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK       (0x1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT      (0U)
+/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
+ *    entered the LPI state because of the setting of the LPIEN bit.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK       (0x2U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT      (1U)
+/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
+ *    the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK       (0x4U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT      (2U)
+/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
+ *    an LPI pattern and entered the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK       (0x8U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT      (3U)
+/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
+ *    receiving the LPI pattern on the MII interface, exited the LPI state, and resumed the normal
+ *    reception.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK       (0x100U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT      (8U)
+/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the LPI pattern on the MII interface.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK       (0x200U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT      (9U)
+/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the MII interface.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK        (0x10000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT       (16U)
+/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK          (0x20000U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT         (17U)
+/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK       (0x80000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT      (19U)
+/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
+ *    out of the LPI mode on the Transmit side.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK       (0x100000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT      (20U)
+/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK      (0x200000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT     (21U)
+/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts LPI Tx Clock Gating
+ *    Control signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be
+ *    stopped.
+ */
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
+/*! @{ */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK         (0xFFFFU)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT        (0U)
+/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
+ *    waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
+ *    transmission.
+ */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK         (0x3FF0000U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT        (16U)
+/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
+ *    status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
+ */
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
+/*! @} */
+
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
+/*! @{ */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK        (0xFFFF8U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT       (3U)
+/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC will wait to enter
+ *    LPI mode, after it has transmitted all the frames.
+ */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
+/*! @} */
+
+/*! @name MAC_1US_TIC_COUNTR -  */
+/*! @{ */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
+/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
+ */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
+/*! @} */
+
+/*! @name MAC_VERSION - MAC version register */
+/*! @{ */
+#define ENET_MAC_VERSION_SNPVER_MASK             (0xFFU)
+#define ENET_MAC_VERSION_SNPVER_SHIFT            (0U)
+/*! SNPVER - NXP defined version.
+ */
+#define ENET_MAC_VERSION_SNPVER(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
+#define ENET_MAC_VERSION_USERVER_MASK            (0xFF00U)
+#define ENET_MAC_VERSION_USERVER_SHIFT           (8U)
+/*! USERVER - User defined version.
+ */
+#define ENET_MAC_VERSION_USERVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
+/*! @} */
+
+/*! @name MAC_DBG - MAC debug register */
+/*! @{ */
+#define ENET_MAC_DBG_REPESTS_MASK                (0x1U)
+#define ENET_MAC_DBG_REPESTS_SHIFT               (0U)
+/*! REPESTS - MAC MII Receive Protocol Engine Status When this bit is set, it indicates that the MAC
+ *    MII receive protocol engine is actively receiving data, and it is not in the Idle state.
+ */
+#define ENET_MAC_DBG_REPESTS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
+#define ENET_MAC_DBG_RFCFCSTS_MASK               (0x6U)
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT              (1U)
+/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
+ *    the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
+ *    Controller module.
+ */
+#define ENET_MAC_DBG_RFCFCSTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
+#define ENET_MAC_DBG_TPESTS_MASK                 (0x10000U)
+#define ENET_MAC_DBG_TPESTS_SHIFT                (16U)
+/*! TPESTS - MAC MII Transmit Protocol Engine Status When this bit is set, it indicates that the MAC
+ *    or MII transmit protocol engine is actively transmitting data, and it is not in the Idle
+ *    state.
+ */
+#define ENET_MAC_DBG_TPESTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
+#define ENET_MAC_DBG_TFCSTS_MASK                 (0x60000U)
+#define ENET_MAC_DBG_TFCSTS_SHIFT                (17U)
+/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
+ */
+#define ENET_MAC_DBG_TFCSTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
+/*! @} */
+
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
+/*! @{ */
+#define ENET_MAC_HW_FEAT_MIISEL_MASK             (0x1U)
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT            (0U)
+/*! MIISEL - 10 or 100 Mbps Support.
+ */
+#define ENET_MAC_HW_FEAT_MIISEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK         (0x1FU)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT        (0U)
+/*! RXFIFOSIZE - MTL Receive FIFO Size.
+ */
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK             (0xFU)
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT            (0U)
+/*! RXQCNT - Number of MTL Receive Queues.
+ */
+#define ENET_MAC_HW_FEAT_RXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_HDSEL_MASK              (0x4U)
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT             (2U)
+/*! HDSEL - Half-duplex Support.
+ */
+#define ENET_MAC_HW_FEAT_HDSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
+#define ENET_MAC_HW_FEAT_VLHASH_MASK             (0x10U)
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT            (4U)
+/*! VLHASH - Hash Table Based Filtering option.
+ */
+#define ENET_MAC_HW_FEAT_VLHASH(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
+#define ENET_MAC_HW_FEAT_SMASEL_MASK             (0x20U)
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT            (5U)
+/*! SMASEL - SMA (MDIO) Interface.
+ */
+#define ENET_MAC_HW_FEAT_SMASEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK             (0x40U)
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT            (6U)
+/*! RWKSEL - PMT Remote Wake-up Packet Detection.
+ */
+#define ENET_MAC_HW_FEAT_RWKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK         (0x7C0U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT        (6U)
+/*! TXFIFOSIZE - MTL Transmit FIFO Size.
+ */
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK             (0x3C0U)
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT            (6U)
+/*! TXQCNT - Number of MTL Transmit Queues.
+ */
+#define ENET_MAC_HW_FEAT_TXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK             (0x80U)
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT            (7U)
+/*! MGKSEL - PMT magic packet detection.
+ */
+#define ENET_MAC_HW_FEAT_MGKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK             (0x100U)
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT            (8U)
+/*! MMCSEL - RMON Module Enable.
+ */
+#define ENET_MAC_HW_FEAT_MMCSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK          (0x200U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT         (9U)
+/*! ARPOFFSEL - ARP Offload Enabled.
+ */
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
+#define ENET_MAC_HW_FEAT_OSTEN_MASK              (0x800U)
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT             (11U)
+/*! OSTEN - One-Step Timestamping Feature.
+ */
+#define ENET_MAC_HW_FEAT_OSTEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
+#define ENET_MAC_HW_FEAT_PTOEN_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT             (12U)
+/*! PTOEN - PTP OffLoad Feature.
+ */
+#define ENET_MAC_HW_FEAT_PTOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK            (0xF000U)
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT           (12U)
+/*! RXCHCNT - Number of DMA Receive Channels.
+ */
+#define ENET_MAC_HW_FEAT_RXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSSEL_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT             (12U)
+/*! TSSEL - IEEE 1588-2008 Timestamp support .
+ */
+#define ENET_MAC_HW_FEAT_TSSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK          (0x2000U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT         (13U)
+/*! ADVTHWORD - IEEE 1588 High Word Register Feature.
+ */
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
+#define ENET_MAC_HW_FEAT_EEESEL_MASK             (0x2000U)
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT            (13U)
+/*! EEESEL - Energy Efficient Ethernet Support .
+ */
+#define ENET_MAC_HW_FEAT_EEESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
+#define ENET_MAC_HW_FEAT_ADDR64_MASK             (0xC000U)
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT            (14U)
+/*! ADDR64 - Address width.
+ */
+#define ENET_MAC_HW_FEAT_ADDR64(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK           (0x4000U)
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT          (14U)
+/*! TXCOESEL - Transmit Checksum Offload Support.
+ */
+#define ENET_MAC_HW_FEAT_TXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_DCBEN_MASK              (0x10000U)
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT             (16U)
+/*! DCBEN - Data Center Bridging feature.
+ */
+#define ENET_MAC_HW_FEAT_DCBEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK           (0x10000U)
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT          (16U)
+/*! RXCOESEL - Receive Checksum Offload Support.
+ */
+#define ENET_MAC_HW_FEAT_RXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_SPEN_MASK               (0x20000U)
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT              (17U)
+/*! SPEN - Split Header Structure feature.
+ */
+#define ENET_MAC_HW_FEAT_SPEN(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
+#define ENET_MAC_HW_FEAT_TSOEN_MASK              (0x40000U)
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT             (18U)
+/*! TSOEN - TCP Segment Offload Feature.
+ */
+#define ENET_MAC_HW_FEAT_TSOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK            (0x3C0000U)
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT           (18U)
+/*! TXCHCNT - Number of DMA Transmit Channels.
+ */
+#define ENET_MAC_HW_FEAT_TXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK            (0x80000U)
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT           (19U)
+/*! DBGMEMA - DMA Debug Register Feature.
+ */
+#define ENET_MAC_HW_FEAT_DBGMEMA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
+#define ENET_MAC_HW_FEAT_AVSEL_MASK              (0x100000U)
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT             (20U)
+/*! AVSEL - Audio Video Bridging Feature.
+ */
+#define ENET_MAC_HW_FEAT_AVSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK           (0x800000U)
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT          (23U)
+/*! LPMODEEN - Low Power Mode Feature Support .
+ */
+#define ENET_MAC_HW_FEAT_LPMODEEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK          (0x3000000U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT         (24U)
+/*! HASHTBLSZ - Hash Table Size.
+ */
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK          (0x7000000U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT         (24U)
+/*! PPSOUTNUM - Number of PPS Outputs.
+ */
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK           (0x6000000U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT          (25U)
+/*! TSSTSSEL - Timestamp System Time Source.
+ */
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK       (0x78000000U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT      (27U)
+/*! L3_L4_FILTER - Total Number of L3 and L4 Filters .
+ */
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK          (0x70000000U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT         (28U)
+/*! ACTPHYSEL - Active PHY Selected.
+ */
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK         (0x70000000U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT        (28U)
+/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs.
+ */
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
+/*! @} */
+
+/* The count of ENET_MAC_HW_FEAT */
+#define ENET_MAC_HW_FEAT_COUNT                   (3U)
+
+/*! @name MAC_MDIO_ADDR - MIDO address Register */
+/*! @{ */
+#define ENET_MAC_MDIO_ADDR_MB_MASK               (0x1U)
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT              (0U)
+/*! MB - MII busy.
+ */
+#define ENET_MAC_MDIO_ADDR_MB(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
+#define ENET_MAC_MDIO_ADDR_MOC_MASK              (0xCU)
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT             (2U)
+/*! MOC - MII Operation Command.
+ */
+#define ENET_MAC_MDIO_ADDR_MOC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
+#define ENET_MAC_MDIO_ADDR_CR_MASK               (0xF00U)
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT              (8U)
+/*! CR - CSR Clock Range.
+ */
+#define ENET_MAC_MDIO_ADDR_CR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
+#define ENET_MAC_MDIO_ADDR_NTC_MASK              (0x7000U)
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT             (12U)
+/*! NTC - Number of Training Clocks This field controls the number of trailing clock cycles
+ *    generated on MDC after the end of transmission of MDIO frame.
+ */
+#define ENET_MAC_MDIO_ADDR_NTC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
+#define ENET_MAC_MDIO_ADDR_RDA_MASK              (0x1F0000U)
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT             (16U)
+/*! RDA - Register/Device Address These bits select the PHY register in selected PHY device.
+ */
+#define ENET_MAC_MDIO_ADDR_RDA(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
+#define ENET_MAC_MDIO_ADDR_PA_MASK               (0x3E00000U)
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT              (21U)
+/*! PA - Physical Layer Address This field indicates which PHY devices (out of 32 devices) the MAC is accessing.
+ */
+#define ENET_MAC_MDIO_ADDR_PA(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
+#define ENET_MAC_MDIO_ADDR_BTB_MASK              (0x4000000U)
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT             (26U)
+/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
+ *    the MAC will inform the completion of a read or write command at the end of frame transfer
+ *    (before the trailing clocks are transmitted).
+ */
+#define ENET_MAC_MDIO_ADDR_BTB(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
+#define ENET_MAC_MDIO_ADDR_PSE_MASK              (0x8000000U)
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT             (27U)
+/*! PSE - Preamble Suppression Enable When this bit is set, the SMA will suppress the 32-bit
+ *    preamble and transmit MDIO frames with only 1 preamble bit.
+ */
+#define ENET_MAC_MDIO_ADDR_PSE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
+/*! @} */
+
+/*! @name MAC_MDIO_DATA - MDIO Data register */
+/*! @{ */
+#define ENET_MAC_MDIO_DATA_MD_MASK               (0xFFFFU)
+#define ENET_MAC_MDIO_DATA_MD_SHIFT              (0U)
+/*! MD - MII Data This field contains the 16-bit data value read from the PHY after a Management
+ *    Read operation or the 16-bit data value to be written to the PHY before a Management Write
+ *    operation.
+ */
+#define ENET_MAC_MDIO_DATA_MD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
+/*! @} */
+
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */
+/*! @{ */
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK           (0xFFFFU)
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT          (0U)
+/*! A47_32 - MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address.
+ */
+#define ENET_MAC_ADDR_HIGH_A47_32(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
+#define ENET_MAC_ADDR_HIGH_DCS_MASK              (0x10000U)
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT             (16U)
+/*! DCS - DMA Channel Select This field contains the DMA Channel number to which the Rx packet whose
+ *    DA matches the MAC Address content is routed.
+ */
+#define ENET_MAC_ADDR_HIGH_DCS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
+#define ENET_MAC_ADDR_HIGH_AE_MASK               (0x80000000U)
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT              (31U)
+/*! AE - Address Enable.
+ */
+#define ENET_MAC_ADDR_HIGH_AE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
+/*! @} */
+
+/*! @name MAC_ADDR_LOW - MAC address0 low register */
+/*! @{ */
+#define ENET_MAC_ADDR_LOW_A31_0_MASK             (0xFFFFFFFFU)
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT            (0U)
+/*! A31_0 - MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address.
+ */
+#define ENET_MAC_ADDR_LOW_A31_0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK       (0x1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT      (0U)
+/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK    (0x2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT   (1U)
+/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK      (0x4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT     (2U)
+/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
+ *    with the value specified in the MAC Register 80 (System Time Seconds Update.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK      (0x8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT     (3U)
+/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
+ *    with the value specified in MAC System Time Seconds Update Table 753 and MAC System Time
+ *    Nanoseconds Update Table 754.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK      (0x10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT     (4U)
+/*! TSTRIG - Enable Timestamp Interrupt Trigger When this bit is set, the timestamp interrupt is
+ *    generated when the System Time becomes greater than the value written in the Target Time register.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK     (0x20U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT    (5U)
+/*! TADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
+ *    register is updated in the PTP block for fine correction.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK     (0x100U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT    (8U)
+/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
+ *    enabled for all packets received by the MAC.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK   (0x200U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT  (9U)
+/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
+ *    register rolls over after 0x3B9AC9FF value (that is, 1 nanosecond accuracy) and increments
+ *    the timestamp (High) seconds.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK   (0x400U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT  (10U)
+/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
+ *    1588 version 2 format is used to process the PTP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK     (0x800U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT    (11U)
+/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
+ *    processes the PTP packets encapsulated directly in the Ethernet packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK   (0x1000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT  (12U)
+/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over 1Pv6-UDP When this bit is set, the MAC
+ *    receiver processes the PTP packets encapsulated in IPv6-UDP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK   (0x2000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT  (13U)
+/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
+ *    receiver processes the PTP packets encapsulated in IPv4-UDP packets.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK    (0x4000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT   (14U)
+/*! TSEVTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
+ *    snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK   (0x8000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT  (15U)
+/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
+ *    is taken only for the messages that are relevant to the master node.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK  (0x30000U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
+/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
+ *    decide the set of PTP packet types for which snapshot needs to be taken.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
+/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
+ *    address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
+ *    directly sent over Ethernet.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK   (0x1000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT  (24U)
+/*! TXTTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
+ *    transmit timestamp status even if it is not read by the software.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
+/*! AV8021ASMEN - AV 802.
+ */
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
+/*! @} */
+
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
+/*! @{ */
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK        (0xFF0000U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT       (16U)
+/*! SSINC - Sub-second increment value.
+ */
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK          (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT         (0U)
+/*! TSS - Time stamp second The value in this field indicates the current value in seconds of the
+ *    System Time maintained by the MAC.
+ */
+#define ENET_MAC_SYS_TIME_SCND_TSS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK        (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT       (0U)
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_SCND_UPD -  */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK      (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT     (0U)
+/*! TSS - Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.
+ */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_NSCND_UPD -  */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK    (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT   (0U)
+/*! TSSS - Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK  (0x80000000U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
+/*! ADDSUB - Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register.
+ */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
+/*! @{ */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK   (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT  (0U)
+/*! TSAR - Time stamp addend This register indicates the 32-bit time value to be added to the
+ *    Accumulator register to achieve time synchronization.
+ */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIME_HWORD_SCND -  */
+/*! @{ */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK  (0xFFFFU)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
+/*! TSHWR - Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value.
+ */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
+/*! @} */
+
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
+/*! @{ */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK   (0x1U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT  (0U)
+/*! TSSOVF - Time stamp seconds overflow When set, indicates that the seconds value of the Time
+ *    stamp has overflowed beyond 0xFFFF_FFFF.
+ */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
+/*! @} */
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
+/*! @{ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
+/*! TXTSSTSLO - Transmit timestamp status low.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
+/*! TXTSSTSMIS - Transmit timestamp status missed.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
+/*! @} */
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
+/*! @{ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
+/*! TXTSSTSHI - Transmit timestamp status high.
+ */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
+/*! TSIC - Transmit ingress correction.
+ */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+/*! @} */
+
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
+/*! @{ */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
+/*! TSEC - Transmit egress correction.
+ */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+/*! @} */
+
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */
+/*! @{ */
+#define ENET_MTL_OP_MODE_DTXSTS_MASK             (0x2U)
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT            (1U)
+/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
+ */
+#define ENET_MTL_OP_MODE_DTXSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
+#define ENET_MTL_OP_MODE_RAA_MASK                (0x4U)
+#define ENET_MTL_OP_MODE_RAA_SHIFT               (2U)
+/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
+ */
+#define ENET_MTL_OP_MODE_RAA(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
+#define ENET_MTL_OP_MODE_SCHALG_MASK             (0x60U)
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT            (5U)
+/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x00: WRR
+ *    algorithm 0x1: Reserved 0x2: Reserved 0x3: Strict priority algorithm.
+ */
+#define ENET_MTL_OP_MODE_SCHALG(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
+#define ENET_MTL_OP_MODE_CNTPRST_MASK            (0x100U)
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT           (8U)
+/*! CNTPRST - Counters Preset When this bit is set, MTL TxQ0 Underflow register (Table 762) and
+ *    MTL_TxQ1_Underflow (Table 762) registers are initialized/preset to 0x7F0.
+ */
+#define ENET_MTL_OP_MODE_CNTPRST(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
+#define ENET_MTL_OP_MODE_CNTCLR_MASK             (0x200U)
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT            (9U)
+/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
+ */
+#define ENET_MTL_OP_MODE_CNTCLR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
+/*! @} */
+
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
+/*! @{ */
+#define ENET_MTL_INTR_STAT_Q0IS_MASK             (0x1U)
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT            (0U)
+/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
+ */
+#define ENET_MTL_INTR_STAT_Q0IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
+#define ENET_MTL_INTR_STAT_Q1IS_MASK             (0x2U)
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT            (1U)
+/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
+ */
+#define ENET_MTL_INTR_STAT_Q1IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
+/*! @} */
+
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
+/*! @{ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK       (0x1U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT      (0U)
+/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
+ *    in Queue 0 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
+ *    Q0DDMACH field is reset.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK       (0x10U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT      (4U)
+/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
+ *    the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
+ *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
+ *    Ethernet DA address.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK       (0x100U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT      (8U)
+/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
+ *    in Queue 1 to the DMA channel: 0: DMA Channel 0 1: DMA Channel 1 This field is valid when the
+ *    Q1DDMACH field is reset.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK       (0x1000U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT      (12U)
+/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
+ *    the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
+ *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
+ *    Ethernet DA address.
+ */
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
+/*! @} */
+
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
+/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
+/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
+/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
+/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
+/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
+/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
+ *    controller because of Tx Queue Underflow.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
+/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
+ *    Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
+/*! @} */
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
+/*! @{ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
+/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
+ *    indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
+ *    of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
+ *    when PFC is enabled - Reception of 802.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK  (0x6U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
+/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read
+ *    Controller: 00: Idle state 01: Read state (transferring data to the MAC transmitter) 10:
+ *    Waiting for pending Tx Status from the MAC transmitter 11: Flushing the Tx queue because of the
+ *    Packet Abort request from the MAC.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK  (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
+/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
+ *    Queue Write Controller is active, and it is transferring the data to the Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK  (0x10U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
+/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
+ *    is not empty and some data is left for transmission.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
+/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK    (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT   (16U)
+/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
+ */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
+/*! STSXSTSF - Number of Status Word