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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/system_LPC54S018.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC54S018/system_LPC54S018.c
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1/*
2** ###################################################################
3** Processors: LPC54S018JBD208
4** LPC54S018JET180
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9** MCUXpresso Compiler
10**
11** Reference manual: LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
12** Version: rev. 1.0, 2018-04-20
13** Build: b201015
14**
15** Abstract:
16** Provides a system configuration function and a global variable that
17** contains the system frequency. It configures the device and initializes
18** the oscillator (PLL) that is part of the microcontroller device.
19**
20** Copyright 2016 Freescale Semiconductor, Inc.
21** Copyright 2016-2020 NXP
22** All rights reserved.
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2018-04-20)
31** Initial version.
32**
33** ###################################################################
34*/
35
36/*!
37 * @file LPC54S018
38 * @version 1.0
39 * @date 2018-04-20
40 * @brief Device specific configuration file for LPC54S018 (implementation file)
41 *
42 * Provides a system configuration function and a global variable that contains
43 * the system frequency. It configures the device and initializes the oscillator
44 * (PLL) that is part of the microcontroller device.
45 */
46
47#include <stdint.h>
48#include "fsl_device_registers.h"
49
50#define NVALMAX (0x100)
51#define PVALMAX (0x20)
52#define MVALMAX (0x8000)
53#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
54#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
55#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
56#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
57#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
58#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
59
60static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
61 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
62/* Get WATCH DOG Clk */
63static uint32_t getWdtOscFreq(void)
64{
65 uint8_t freq_sel, div_sel;
66 if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) != 0UL)
67 {
68 return 0U;
69 }
70 else
71 {
72 div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
73 freq_sel =
74 wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
75 return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
76 }
77}
78/* Find decoded N value for raw NDEC value */
79static uint32_t pllDecodeN(uint32_t NDEC)
80{
81 uint32_t n, x, i;
82
83 /* Find NDec */
84 switch (NDEC)
85 {
86 case 0x3FF:
87 n = 0UL;
88 break;
89 case 0x302:
90 n = 1UL;
91 break;
92 case 0x202:
93 n = 2UL;
94 break;
95 default:
96 x = 0x080UL;
97 n = 0xFFFFFFFFUL;
98 for (i = NVALMAX; i >= 3UL; i--)
99 {
100 x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
101 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
102 {
103 /* Decoded value of NDEC */
104 n = i;
105 }
106 if (n != 0xFFFFFFFFUL)
107 {
108 break;
109 }
110 }
111 break;
112 }
113 return n;
114}
115
116/* Find decoded P value for raw PDEC value */
117static uint32_t pllDecodeP(uint32_t PDEC)
118{
119 uint32_t p, x, i;
120 /* Find PDec */
121 switch (PDEC)
122 {
123 case 0x7F:
124 p = 0UL;
125 break;
126 case 0x62:
127 p = 1UL;
128 break;
129 case 0x42:
130 p = 2UL;
131 break;
132 default:
133 x = 0x10UL;
134 p = 0xFFFFFFFFUL;
135 for (i = PVALMAX; i >= 3UL; i--)
136 {
137 x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
138 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
139 {
140 /* Decoded value of PDEC */
141 p = i;
142 }
143 if (p != 0xFFFFFFFFUL)
144 {
145 break;
146 }
147 }
148 break;
149 }
150 return p;
151}
152
153/* Find decoded M value for raw MDEC value */
154static uint32_t pllDecodeM(uint32_t MDEC)
155{
156 uint32_t m, i, x;
157
158 /* Find MDec */
159 switch (MDEC)
160 {
161 case 0x1FFFF:
162 m = 0UL;
163 break;
164 case 0x18003:
165 m = 1UL;
166 break;
167 case 0x10003:
168 m = 2UL;
169 break;
170 default:
171 x = 0x04000UL;
172 m = 0xFFFFFFFFUL;
173 for (i = MVALMAX; i >= 3UL; i--)
174 {
175 x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
176 if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
177 {
178 /* Decoded value of MDEC */
179 m = i;
180 }
181 if (m != 0xFFFFFFFFUL)
182 {
183 break;
184 }
185 }
186 break;
187 }
188 return m;
189}
190
191/* Get predivider (N) from PLL NDEC setting */
192static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
193{
194 uint32_t preDiv = 1;
195
196 /* Direct input is not used? */
197 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
198 {
199 /* Decode NDEC value to get (N) pre divider */
200 preDiv = pllDecodeN(nDecReg & 0x3FFUL);
201 if (preDiv == 0UL)
202 {
203 preDiv = 1;
204 }
205 }
206 /* Adjusted by 1, directi is used to bypass */
207 return preDiv;
208}
209
210/* Get postdivider (P) from PLL PDEC setting */
211static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
212{
213 uint32_t postDiv = 1;
214
215 /* Direct input is not used? */
216 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
217 {
218 /* Decode PDEC value to get (P) post divider */
219 postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
220 if (postDiv == 0UL)
221 {
222 postDiv = 2;
223 }
224 }
225 /* Adjusted by 1, directo is used to bypass */
226 return postDiv;
227}
228
229/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
230static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
231{
232 uint32_t mMult = 1;
233
234 /* Decode MDEC value to get (M) multiplier */
235 mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
236 if (mMult == 0UL)
237 {
238 mMult = 1;
239 }
240 return mMult;
241}
242
243/* ----------------------------------------------------------------------------
244 -- Core clock
245 ---------------------------------------------------------------------------- */
246
247uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
248
249/* ----------------------------------------------------------------------------
250 -- SystemInit()
251 ---------------------------------------------------------------------------- */
252
253void SystemInit(void)
254{
255#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
256 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
257#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
258
259#if defined(__MCUXPRESSO)
260 extern void (*const g_pfnVectors[])(void);
261 SCB->VTOR = (uint32_t)&g_pfnVectors;
262#else
263 extern void *__Vectors;
264 SCB->VTOR = (uint32_t)&__Vectors;
265#endif
266 SYSCON->ARMTRACECLKDIV = 0;
267/* Optionally enable RAM banks that may be off by default at reset */
268#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
269 SYSCON->AHBCLKCTRLSET[0] =
270 SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
271
272#endif
273 SYSCON->MAINCLKSELA = 0U;
274 SYSCON->MAINCLKSELB = 0U;
275 SystemInitHook();
276}
277
278/* ----------------------------------------------------------------------------
279 -- SystemCoreClockUpdate()
280 ---------------------------------------------------------------------------- */
281
282void SystemCoreClockUpdate(void)
283{
284 uint32_t clkRate = 0;
285 uint32_t prediv, postdiv;
286 uint64_t workRate;
287
288 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
289 {
290 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
291 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
292 {
293 case 0x00: /* FRO 12 MHz (fro_12m) */
294 clkRate = CLK_FRO_12MHZ;
295 break;
296 case 0x01: /* CLKIN Source (clk_in) */
297 clkRate = CLK_CLK_IN;
298 break;
299 case 0x02: /* Watchdog oscillator (wdt_clk) */
300 clkRate = getWdtOscFreq();
301 break;
302 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
303 if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
304 {
305 clkRate = CLK_FRO_96MHZ;
306 }
307 else
308 {
309 clkRate = CLK_FRO_48MHZ;
310 }
311 break;
312 }
313 break;
314 case 0x02: /* System PLL clock (pll_clk)*/
315 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
316 {
317 case 0x00: /* FRO 12 MHz (fro_12m) */
318 clkRate = CLK_FRO_12MHZ;
319 break;
320 case 0x01: /* CLKIN Source (clk_in) */
321 clkRate = CLK_CLK_IN;
322 break;
323 case 0x02: /* Watchdog oscillator (wdt_clk) */
324 clkRate = getWdtOscFreq();
325 break;
326 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
327 clkRate = CLK_RTC_32K_CLK;
328 break;
329 default:
330 clkRate = 0UL;
331 break;
332 }
333 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
334 {
335 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
336 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
337 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
338 /* Adjust input clock */
339 clkRate = clkRate / prediv;
340
341 /* MDEC used for rate */
342 workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
343 clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
344 clkRate = clkRate * 2UL; /* PLL CCO output is divided by 2 before to M-Divider */
345 }
346 break;
347 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
348 clkRate = CLK_RTC_32K_CLK;
349 break;
350 default:
351 clkRate = 0UL;
352 break;
353 }
354 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
355}
356
357/* ----------------------------------------------------------------------------
358 -- SystemInitHook()
359 ---------------------------------------------------------------------------- */
360
361__attribute__((weak)) void SystemInitHook(void)
362{
363 /* Void implementation of the weak function. */
364}
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