diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516')
37 files changed, 38527 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/LPC5516.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/LPC5516.h new file mode 100644 index 000000000..95c1f67ec --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/LPC5516.h | |||
| @@ -0,0 +1,27047 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: LPC5516JBD100 | ||
| 4 | ** LPC5516JBD64 | ||
| 5 | ** LPC5516JEV98 | ||
| 6 | ** | ||
| 7 | ** Compilers: GNU C Compiler | ||
| 8 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 9 | ** Keil ARM C/C++ Compiler | ||
| 10 | ** MCUXpresso Compiler | ||
| 11 | ** | ||
| 12 | ** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 | ||
| 13 | ** Version: rev. 1.1, 2019-12-03 | ||
| 14 | ** Build: b200311 | ||
| 15 | ** | ||
| 16 | ** Abstract: | ||
| 17 | ** CMSIS Peripheral Access Layer for LPC5516 | ||
| 18 | ** | ||
| 19 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 20 | ** Copyright 2016-2020 NXP | ||
| 21 | ** All rights reserved. | ||
| 22 | ** | ||
| 23 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 24 | ** | ||
| 25 | ** http: www.nxp.com | ||
| 26 | ** mail: [email protected] | ||
| 27 | ** | ||
| 28 | ** Revisions: | ||
| 29 | ** - rev. 1.0 (2018-08-22) | ||
| 30 | ** Initial version based on v0.2UM | ||
| 31 | ** - rev. 1.1 (2019-12-03) | ||
| 32 | ** Initial version based on v0.6UM | ||
| 33 | ** | ||
| 34 | ** ################################################################### | ||
| 35 | */ | ||
| 36 | |||
| 37 | /*! | ||
| 38 | * @file LPC5516.h | ||
| 39 | * @version 1.1 | ||
| 40 | * @date 2019-12-03 | ||
| 41 | * @brief CMSIS Peripheral Access Layer for LPC5516 | ||
| 42 | * | ||
| 43 | * CMSIS Peripheral Access Layer for LPC5516 | ||
| 44 | */ | ||
| 45 | |||
| 46 | #ifndef _LPC5516_H_ | ||
| 47 | #define _LPC5516_H_ /**< Symbol preventing repeated inclusion */ | ||
| 48 | |||
| 49 | /** Memory map major version (memory maps with equal major version number are | ||
| 50 | * compatible) */ | ||
| 51 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 52 | /** Memory map minor version */ | ||
| 53 | #define MCU_MEM_MAP_VERSION_MINOR 0x0001U | ||
| 54 | |||
| 55 | |||
| 56 | /* ---------------------------------------------------------------------------- | ||
| 57 | -- Interrupt vector numbers | ||
| 58 | ---------------------------------------------------------------------------- */ | ||
| 59 | |||
| 60 | /*! | ||
| 61 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 62 | * @{ | ||
| 63 | */ | ||
| 64 | |||
| 65 | /** Interrupt Number Definitions */ | ||
| 66 | #define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */ | ||
| 67 | |||
| 68 | typedef enum IRQn { | ||
| 69 | /* Auxiliary constants */ | ||
| 70 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 71 | |||
| 72 | /* Core interrupts */ | ||
| 73 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 74 | HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ | ||
| 75 | MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ | ||
| 76 | BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ | ||
| 77 | UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ | ||
| 78 | SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ | ||
| 79 | SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ | ||
| 80 | DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ | ||
| 81 | PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ | ||
| 82 | SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ | ||
| 83 | |||
| 84 | /* Device specific interrupts */ | ||
| 85 | WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ | ||
| 86 | DMA0_IRQn = 1, /**< DMA0 controller */ | ||
| 87 | GINT0_IRQn = 2, /**< GPIO group 0 */ | ||
| 88 | GINT1_IRQn = 3, /**< GPIO group 1 */ | ||
| 89 | PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ | ||
| 90 | PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ | ||
| 91 | PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ | ||
| 92 | PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ | ||
| 93 | UTICK0_IRQn = 8, /**< Micro-tick Timer */ | ||
| 94 | MRT0_IRQn = 9, /**< Multi-rate timer */ | ||
| 95 | CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ | ||
| 96 | CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ | ||
| 97 | SCT0_IRQn = 12, /**< SCTimer/PWM */ | ||
| 98 | CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ | ||
| 99 | FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 100 | FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 101 | FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 102 | FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 103 | FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 104 | FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 105 | FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 106 | FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 107 | ADC0_IRQn = 22, /**< ADC0 */ | ||
| 108 | Reserved39_IRQn = 23, /**< Reserved interrupt */ | ||
| 109 | ACMP_IRQn = 24, /**< ACMP interrupts */ | ||
| 110 | Reserved41_IRQn = 25, /**< Reserved interrupt */ | ||
| 111 | Reserved42_IRQn = 26, /**< Reserved interrupt */ | ||
| 112 | USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ | ||
| 113 | USB0_IRQn = 28, /**< USB device */ | ||
| 114 | RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ | ||
| 115 | Reserved46_IRQn = 30, /**< Reserved interrupt */ | ||
| 116 | Reserved47_IRQn = 31, /**< Reserved interrupt */ | ||
| 117 | PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ | ||
| 118 | PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ | ||
| 119 | PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ | ||
| 120 | PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ | ||
| 121 | CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ | ||
| 122 | CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ | ||
| 123 | OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ | ||
| 124 | Reserved55_IRQn = 39, /**< Reserved interrupt */ | ||
| 125 | Reserved56_IRQn = 40, /**< Reserved interrupt */ | ||
| 126 | Reserved57_IRQn = 41, /**< Reserved interrupt */ | ||
| 127 | Reserved58_IRQn = 42, /**< Reserved interrupt */ | ||
| 128 | CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ | ||
| 129 | CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ | ||
| 130 | Reserved61_IRQn = 45, /**< Reserved interrupt */ | ||
| 131 | USB1_PHY_IRQn = 46, /**< USB1_PHY */ | ||
| 132 | USB1_IRQn = 47, /**< USB1 interrupt */ | ||
| 133 | USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ | ||
| 134 | SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ | ||
| 135 | SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ | ||
| 136 | SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ | ||
| 137 | PLU_IRQn = 52, /**< PLU interrupt */ | ||
| 138 | SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ | ||
| 139 | Reserved70_IRQn = 54, /**< Reserved interrupt */ | ||
| 140 | CASER_IRQn = 55, /**< CASPER interrupt */ | ||
| 141 | PUF_IRQn = 56, /**< PUF interrupt */ | ||
| 142 | Reserved73_IRQn = 57, /**< Reserved interrupt */ | ||
| 143 | DMA1_IRQn = 58, /**< DMA1 interrupt */ | ||
| 144 | FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ | ||
| 145 | CodeWDG_IRQn = 60 /**< CodeWDG interrupt */ | ||
| 146 | } IRQn_Type; | ||
| 147 | |||
| 148 | /*! | ||
| 149 | * @} | ||
| 150 | */ /* end of group Interrupt_vector_numbers */ | ||
| 151 | |||
| 152 | |||
| 153 | /* ---------------------------------------------------------------------------- | ||
| 154 | -- Cortex M33 Core Configuration | ||
| 155 | ---------------------------------------------------------------------------- */ | ||
| 156 | |||
| 157 | /*! | ||
| 158 | * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration | ||
| 159 | * @{ | ||
| 160 | */ | ||
| 161 | |||
| 162 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 163 | #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ | ||
| 164 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 165 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 166 | #define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ | ||
| 167 | #define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ | ||
| 168 | |||
| 169 | #include "core_cm33.h" /* Core Peripheral Access Layer */ | ||
| 170 | #include "system_LPC5516.h" /* Device specific configuration file */ | ||
| 171 | |||
| 172 | /*! | ||
| 173 | * @} | ||
| 174 | */ /* end of group Cortex_Core_Configuration */ | ||
| 175 | |||
| 176 | |||
| 177 | /* ---------------------------------------------------------------------------- | ||
| 178 | -- Mapping Information | ||
| 179 | ---------------------------------------------------------------------------- */ | ||
| 180 | |||
| 181 | /*! | ||
| 182 | * @addtogroup Mapping_Information Mapping Information | ||
| 183 | * @{ | ||
| 184 | */ | ||
| 185 | |||
| 186 | /** Mapping Information */ | ||
| 187 | /*! | ||
| 188 | * @addtogroup dma_request | ||
| 189 | * @{ | ||
| 190 | */ | ||
| 191 | |||
| 192 | /******************************************************************************* | ||
| 193 | * Definitions | ||
| 194 | ******************************************************************************/ | ||
| 195 | |||
| 196 | /*! | ||
| 197 | * @brief Structure for the DMA hardware request | ||
| 198 | * | ||
| 199 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 200 | * hardware request to trigger the DMA transfer accordingly. The index | ||
| 201 | * of the hardware request varies according to the to SoC. | ||
| 202 | */ | ||
| 203 | typedef enum _dma_request_source | ||
| 204 | { | ||
| 205 | kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 206 | kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 207 | kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 208 | kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 209 | kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 210 | kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 211 | kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 212 | kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 213 | kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 214 | kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 215 | kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 216 | kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 217 | kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 218 | kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 219 | kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 220 | kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 221 | kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 222 | kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 223 | kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ | ||
| 224 | kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ | ||
| 225 | kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ | ||
| 226 | kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ | ||
| 227 | kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ | ||
| 228 | kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ | ||
| 229 | kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ | ||
| 230 | kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ | ||
| 231 | kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ | ||
| 232 | kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ | ||
| 233 | kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ | ||
| 234 | kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ | ||
| 235 | kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ | ||
| 236 | } dma_request_source_t; | ||
| 237 | |||
| 238 | /* @} */ | ||
| 239 | |||
| 240 | |||
| 241 | /*! | ||
| 242 | * @} | ||
| 243 | */ /* end of group Mapping_Information */ | ||
| 244 | |||
| 245 | |||
| 246 | /* ---------------------------------------------------------------------------- | ||
| 247 | -- Device Peripheral Access Layer | ||
| 248 | ---------------------------------------------------------------------------- */ | ||
| 249 | |||
| 250 | /*! | ||
| 251 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 252 | * @{ | ||
| 253 | */ | ||
| 254 | |||
| 255 | |||
| 256 | /* | ||
| 257 | ** Start of section using anonymous unions | ||
| 258 | */ | ||
| 259 | |||
| 260 | #if defined(__ARMCC_VERSION) | ||
| 261 | #if (__ARMCC_VERSION >= 6010050) | ||
| 262 | #pragma clang diagnostic push | ||
| 263 | #else | ||
| 264 | #pragma push | ||
| 265 | #pragma anon_unions | ||
| 266 | #endif | ||
| 267 | #elif defined(__GNUC__) | ||
| 268 | /* anonymous unions are enabled by default */ | ||
| 269 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 270 | #pragma language=extended | ||
| 271 | #else | ||
| 272 | #error Not supported compiler type | ||
| 273 | #endif | ||
| 274 | |||
| 275 | /* ---------------------------------------------------------------------------- | ||
| 276 | -- ADC Peripheral Access Layer | ||
| 277 | ---------------------------------------------------------------------------- */ | ||
| 278 | |||
| 279 | /*! | ||
| 280 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 281 | * @{ | ||
| 282 | */ | ||
| 283 | |||
| 284 | /** ADC - Register Layout Typedef */ | ||
| 285 | typedef struct { | ||
| 286 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ | ||
| 287 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ | ||
| 288 | uint8_t RESERVED_0[8]; | ||
| 289 | __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ | ||
| 290 | __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ | ||
| 291 | __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ | ||
| 292 | __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ | ||
| 293 | __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ | ||
| 294 | __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ | ||
| 295 | uint8_t RESERVED_1[12]; | ||
| 296 | __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ | ||
| 297 | __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ | ||
| 298 | uint8_t RESERVED_2[4]; | ||
| 299 | __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ | ||
| 300 | uint8_t RESERVED_3[92]; | ||
| 301 | __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ | ||
| 302 | __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ | ||
| 303 | uint8_t RESERVED_4[8]; | ||
| 304 | __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ | ||
| 305 | __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ | ||
| 306 | struct { /* offset: 0x100, array step: 0x8 */ | ||
| 307 | __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ | ||
| 308 | __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ | ||
| 309 | } CMD[15]; | ||
| 310 | uint8_t RESERVED_5[136]; | ||
| 311 | __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ | ||
| 312 | uint8_t RESERVED_6[240]; | ||
| 313 | __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ | ||
| 314 | uint8_t RESERVED_7[248]; | ||
| 315 | __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ | ||
| 316 | uint8_t RESERVED_8[124]; | ||
| 317 | __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ | ||
| 318 | } ADC_Type; | ||
| 319 | |||
| 320 | /* ---------------------------------------------------------------------------- | ||
| 321 | -- ADC Register Masks | ||
| 322 | ---------------------------------------------------------------------------- */ | ||
| 323 | |||
| 324 | /*! | ||
| 325 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 326 | * @{ | ||
| 327 | */ | ||
| 328 | |||
| 329 | /*! @name VERID - Version ID Register */ | ||
| 330 | /*! @{ */ | ||
| 331 | #define ADC_VERID_RES_MASK (0x1U) | ||
| 332 | #define ADC_VERID_RES_SHIFT (0U) | ||
| 333 | /*! RES - Resolution | ||
| 334 | * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. | ||
| 335 | * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. | ||
| 336 | */ | ||
| 337 | #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) | ||
| 338 | #define ADC_VERID_DIFFEN_MASK (0x2U) | ||
| 339 | #define ADC_VERID_DIFFEN_SHIFT (1U) | ||
| 340 | /*! DIFFEN - Differential Supported | ||
| 341 | * 0b0..Differential operation not supported. | ||
| 342 | * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. | ||
| 343 | */ | ||
| 344 | #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) | ||
| 345 | #define ADC_VERID_MVI_MASK (0x8U) | ||
| 346 | #define ADC_VERID_MVI_SHIFT (3U) | ||
| 347 | /*! MVI - Multi Vref Implemented | ||
| 348 | * 0b0..Single voltage reference high (VREFH) input supported. | ||
| 349 | * 0b1..Multiple voltage reference high (VREFH) inputs supported. | ||
| 350 | */ | ||
| 351 | #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) | ||
| 352 | #define ADC_VERID_CSW_MASK (0x70U) | ||
| 353 | #define ADC_VERID_CSW_SHIFT (4U) | ||
| 354 | /*! CSW - Channel Scale Width | ||
| 355 | * 0b000..Channel scaling not supported. | ||
| 356 | * 0b001..Channel scaling supported. 1-bit CSCALE control field. | ||
| 357 | * 0b110..Channel scaling supported. 6-bit CSCALE control field. | ||
| 358 | */ | ||
| 359 | #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) | ||
| 360 | #define ADC_VERID_VR1RNGI_MASK (0x100U) | ||
| 361 | #define ADC_VERID_VR1RNGI_SHIFT (8U) | ||
| 362 | /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented | ||
| 363 | * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. | ||
| 364 | * 0b1..Range control required. CFG[VREF1RNG] is implemented. | ||
| 365 | */ | ||
| 366 | #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) | ||
| 367 | #define ADC_VERID_IADCKI_MASK (0x200U) | ||
| 368 | #define ADC_VERID_IADCKI_SHIFT (9U) | ||
| 369 | /*! IADCKI - Internal ADC Clock implemented | ||
| 370 | * 0b0..Internal clock source not implemented. | ||
| 371 | * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. | ||
| 372 | */ | ||
| 373 | #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) | ||
| 374 | #define ADC_VERID_CALOFSI_MASK (0x400U) | ||
| 375 | #define ADC_VERID_CALOFSI_SHIFT (10U) | ||
| 376 | /*! CALOFSI - Calibration Function Implemented | ||
| 377 | * 0b0..Calibration Not Implemented. | ||
| 378 | * 0b1..Calibration Implemented. | ||
| 379 | */ | ||
| 380 | #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) | ||
| 381 | #define ADC_VERID_NUM_SEC_MASK (0x800U) | ||
| 382 | #define ADC_VERID_NUM_SEC_SHIFT (11U) | ||
| 383 | /*! NUM_SEC - Number of Single Ended Outputs Supported | ||
| 384 | * 0b0..This design supports one single ended conversion at a time. | ||
| 385 | * 0b1..This design supports two simultanious single ended conversions. | ||
| 386 | */ | ||
| 387 | #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) | ||
| 388 | #define ADC_VERID_NUM_FIFO_MASK (0x7000U) | ||
| 389 | #define ADC_VERID_NUM_FIFO_SHIFT (12U) | ||
| 390 | /*! NUM_FIFO - Number of FIFOs | ||
| 391 | * 0b000..N/A | ||
| 392 | * 0b001..This design supports one result FIFO. | ||
| 393 | * 0b010..This design supports two result FIFOs. | ||
| 394 | * 0b011..This design supports three result FIFOs. | ||
| 395 | * 0b100..This design supports four result FIFOs. | ||
| 396 | */ | ||
| 397 | #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) | ||
| 398 | #define ADC_VERID_MINOR_MASK (0xFF0000U) | ||
| 399 | #define ADC_VERID_MINOR_SHIFT (16U) | ||
| 400 | /*! MINOR - Minor Version Number | ||
| 401 | */ | ||
| 402 | #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) | ||
| 403 | #define ADC_VERID_MAJOR_MASK (0xFF000000U) | ||
| 404 | #define ADC_VERID_MAJOR_SHIFT (24U) | ||
| 405 | /*! MAJOR - Major Version Number | ||
| 406 | */ | ||
| 407 | #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) | ||
| 408 | /*! @} */ | ||
| 409 | |||
| 410 | /*! @name PARAM - Parameter Register */ | ||
| 411 | /*! @{ */ | ||
| 412 | #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) | ||
| 413 | #define ADC_PARAM_TRIG_NUM_SHIFT (0U) | ||
| 414 | /*! TRIG_NUM - Trigger Number | ||
| 415 | */ | ||
| 416 | #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) | ||
| 417 | #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) | ||
| 418 | #define ADC_PARAM_FIFOSIZE_SHIFT (8U) | ||
| 419 | /*! FIFOSIZE - Result FIFO Depth | ||
| 420 | * 0b00000001..Result FIFO depth = 1 dataword. | ||
| 421 | * 0b00000100..Result FIFO depth = 4 datawords. | ||
| 422 | * 0b00001000..Result FIFO depth = 8 datawords. | ||
| 423 | * 0b00010000..Result FIFO depth = 16 datawords. | ||
| 424 | * 0b00100000..Result FIFO depth = 32 datawords. | ||
| 425 | * 0b01000000..Result FIFO depth = 64 datawords. | ||
| 426 | */ | ||
| 427 | #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) | ||
| 428 | #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) | ||
| 429 | #define ADC_PARAM_CV_NUM_SHIFT (16U) | ||
| 430 | /*! CV_NUM - Compare Value Number | ||
| 431 | */ | ||
| 432 | #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) | ||
| 433 | #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) | ||
| 434 | #define ADC_PARAM_CMD_NUM_SHIFT (24U) | ||
| 435 | /*! CMD_NUM - Command Buffer Number | ||
| 436 | */ | ||
| 437 | #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) | ||
| 438 | /*! @} */ | ||
| 439 | |||
| 440 | /*! @name CTRL - ADC Control Register */ | ||
| 441 | /*! @{ */ | ||
| 442 | #define ADC_CTRL_ADCEN_MASK (0x1U) | ||
| 443 | #define ADC_CTRL_ADCEN_SHIFT (0U) | ||
| 444 | /*! ADCEN - ADC Enable | ||
| 445 | * 0b0..ADC is disabled. | ||
| 446 | * 0b1..ADC is enabled. | ||
| 447 | */ | ||
| 448 | #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) | ||
| 449 | #define ADC_CTRL_RST_MASK (0x2U) | ||
| 450 | #define ADC_CTRL_RST_SHIFT (1U) | ||
| 451 | /*! RST - Software Reset | ||
| 452 | * 0b0..ADC logic is not reset. | ||
| 453 | * 0b1..ADC logic is reset. | ||
| 454 | */ | ||
| 455 | #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) | ||
| 456 | #define ADC_CTRL_DOZEN_MASK (0x4U) | ||
| 457 | #define ADC_CTRL_DOZEN_SHIFT (2U) | ||
| 458 | /*! DOZEN - Doze Enable | ||
| 459 | * 0b0..ADC is enabled in Doze mode. | ||
| 460 | * 0b1..ADC is disabled in Doze mode. | ||
| 461 | */ | ||
| 462 | #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) | ||
| 463 | #define ADC_CTRL_CAL_REQ_MASK (0x8U) | ||
| 464 | #define ADC_CTRL_CAL_REQ_SHIFT (3U) | ||
| 465 | /*! CAL_REQ - Auto-Calibration Request | ||
| 466 | * 0b0..No request for auto-calibration has been made. | ||
| 467 | * 0b1..A request for auto-calibration has been made | ||
| 468 | */ | ||
| 469 | #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) | ||
| 470 | #define ADC_CTRL_CALOFS_MASK (0x10U) | ||
| 471 | #define ADC_CTRL_CALOFS_SHIFT (4U) | ||
| 472 | /*! CALOFS - Configure for offset calibration function | ||
| 473 | * 0b0..Calibration function disabled | ||
| 474 | * 0b1..Request for offset calibration function | ||
| 475 | */ | ||
| 476 | #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) | ||
| 477 | #define ADC_CTRL_RSTFIFO0_MASK (0x100U) | ||
| 478 | #define ADC_CTRL_RSTFIFO0_SHIFT (8U) | ||
| 479 | /*! RSTFIFO0 - Reset FIFO 0 | ||
| 480 | * 0b0..No effect. | ||
| 481 | * 0b1..FIFO 0 is reset. | ||
| 482 | */ | ||
| 483 | #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) | ||
| 484 | #define ADC_CTRL_RSTFIFO1_MASK (0x200U) | ||
| 485 | #define ADC_CTRL_RSTFIFO1_SHIFT (9U) | ||
| 486 | /*! RSTFIFO1 - Reset FIFO 1 | ||
| 487 | * 0b0..No effect. | ||
| 488 | * 0b1..FIFO 1 is reset. | ||
| 489 | */ | ||
| 490 | #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) | ||
| 491 | #define ADC_CTRL_CAL_AVGS_MASK (0x70000U) | ||
| 492 | #define ADC_CTRL_CAL_AVGS_SHIFT (16U) | ||
| 493 | /*! CAL_AVGS - Auto-Calibration Averages | ||
| 494 | * 0b000..Single conversion. | ||
| 495 | * 0b001..2 conversions averaged. | ||
| 496 | * 0b010..4 conversions averaged. | ||
| 497 | * 0b011..8 conversions averaged. | ||
| 498 | * 0b100..16 conversions averaged. | ||
| 499 | * 0b101..32 conversions averaged. | ||
| 500 | * 0b110..64 conversions averaged. | ||
| 501 | * 0b111..128 conversions averaged. | ||
| 502 | */ | ||
| 503 | #define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) | ||
| 504 | /*! @} */ | ||
| 505 | |||
| 506 | /*! @name STAT - ADC Status Register */ | ||
| 507 | /*! @{ */ | ||
| 508 | #define ADC_STAT_RDY0_MASK (0x1U) | ||
| 509 | #define ADC_STAT_RDY0_SHIFT (0U) | ||
| 510 | /*! RDY0 - Result FIFO 0 Ready Flag | ||
| 511 | * 0b0..Result FIFO 0 data level not above watermark level. | ||
| 512 | * 0b1..Result FIFO 0 holding data above watermark level. | ||
| 513 | */ | ||
| 514 | #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) | ||
| 515 | #define ADC_STAT_FOF0_MASK (0x2U) | ||
| 516 | #define ADC_STAT_FOF0_SHIFT (1U) | ||
| 517 | /*! FOF0 - Result FIFO 0 Overflow Flag | ||
| 518 | * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 519 | * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 520 | */ | ||
| 521 | #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) | ||
| 522 | #define ADC_STAT_RDY1_MASK (0x4U) | ||
| 523 | #define ADC_STAT_RDY1_SHIFT (2U) | ||
| 524 | /*! RDY1 - Result FIFO1 Ready Flag | ||
| 525 | * 0b0..Result FIFO1 data level not above watermark level. | ||
| 526 | * 0b1..Result FIFO1 holding data above watermark level. | ||
| 527 | */ | ||
| 528 | #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) | ||
| 529 | #define ADC_STAT_FOF1_MASK (0x8U) | ||
| 530 | #define ADC_STAT_FOF1_SHIFT (3U) | ||
| 531 | /*! FOF1 - Result FIFO1 Overflow Flag | ||
| 532 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 533 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 534 | */ | ||
| 535 | #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) | ||
| 536 | #define ADC_STAT_TEXC_INT_MASK (0x100U) | ||
| 537 | #define ADC_STAT_TEXC_INT_SHIFT (8U) | ||
| 538 | /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception | ||
| 539 | * 0b0..No trigger exceptions have occurred. | ||
| 540 | * 0b1..A trigger exception has occurred and is pending acknowledgement. | ||
| 541 | */ | ||
| 542 | #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) | ||
| 543 | #define ADC_STAT_TCOMP_INT_MASK (0x200U) | ||
| 544 | #define ADC_STAT_TCOMP_INT_SHIFT (9U) | ||
| 545 | /*! TCOMP_INT - Interrupt Flag For Trigger Completion | ||
| 546 | * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. | ||
| 547 | * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. | ||
| 548 | */ | ||
| 549 | #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) | ||
| 550 | #define ADC_STAT_CAL_RDY_MASK (0x400U) | ||
| 551 | #define ADC_STAT_CAL_RDY_SHIFT (10U) | ||
| 552 | /*! CAL_RDY - Calibration Ready | ||
| 553 | * 0b0..Calibration is incomplete or hasn't been ran. | ||
| 554 | * 0b1..The ADC is calibrated. | ||
| 555 | */ | ||
| 556 | #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) | ||
| 557 | #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) | ||
| 558 | #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) | ||
| 559 | /*! ADC_ACTIVE - ADC Active | ||
| 560 | * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. | ||
| 561 | * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. | ||
| 562 | */ | ||
| 563 | #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) | ||
| 564 | #define ADC_STAT_TRGACT_MASK (0xF0000U) | ||
| 565 | #define ADC_STAT_TRGACT_SHIFT (16U) | ||
| 566 | /*! TRGACT - Trigger Active | ||
| 567 | * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. | ||
| 568 | * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. | ||
| 569 | * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. | ||
| 570 | * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. | ||
| 571 | */ | ||
| 572 | #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) | ||
| 573 | #define ADC_STAT_CMDACT_MASK (0xF000000U) | ||
| 574 | #define ADC_STAT_CMDACT_SHIFT (24U) | ||
| 575 | /*! CMDACT - Command Active | ||
| 576 | * 0b0000..No command is currently in progress. | ||
| 577 | * 0b0001..Command 1 currently being executed. | ||
| 578 | * 0b0010..Command 2 currently being executed. | ||
| 579 | * 0b0011-0b1111..Associated command number is currently being executed. | ||
| 580 | */ | ||
| 581 | #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) | ||
| 582 | /*! @} */ | ||
| 583 | |||
| 584 | /*! @name IE - Interrupt Enable Register */ | ||
| 585 | /*! @{ */ | ||
| 586 | #define ADC_IE_FWMIE0_MASK (0x1U) | ||
| 587 | #define ADC_IE_FWMIE0_SHIFT (0U) | ||
| 588 | /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable | ||
| 589 | * 0b0..FIFO 0 watermark interrupts are not enabled. | ||
| 590 | * 0b1..FIFO 0 watermark interrupts are enabled. | ||
| 591 | */ | ||
| 592 | #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) | ||
| 593 | #define ADC_IE_FOFIE0_MASK (0x2U) | ||
| 594 | #define ADC_IE_FOFIE0_SHIFT (1U) | ||
| 595 | /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable | ||
| 596 | * 0b0..FIFO 0 overflow interrupts are not enabled. | ||
| 597 | * 0b1..FIFO 0 overflow interrupts are enabled. | ||
| 598 | */ | ||
| 599 | #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) | ||
| 600 | #define ADC_IE_FWMIE1_MASK (0x4U) | ||
| 601 | #define ADC_IE_FWMIE1_SHIFT (2U) | ||
| 602 | /*! FWMIE1 - FIFO1 Watermark Interrupt Enable | ||
| 603 | * 0b0..FIFO1 watermark interrupts are not enabled. | ||
| 604 | * 0b1..FIFO1 watermark interrupts are enabled. | ||
| 605 | */ | ||
| 606 | #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) | ||
| 607 | #define ADC_IE_FOFIE1_MASK (0x8U) | ||
| 608 | #define ADC_IE_FOFIE1_SHIFT (3U) | ||
| 609 | /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable | ||
| 610 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 611 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 612 | */ | ||
| 613 | #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) | ||
| 614 | #define ADC_IE_TEXC_IE_MASK (0x100U) | ||
| 615 | #define ADC_IE_TEXC_IE_SHIFT (8U) | ||
| 616 | /*! TEXC_IE - Trigger Exception Interrupt Enable | ||
| 617 | * 0b0..Trigger exception interrupts are disabled. | ||
| 618 | * 0b1..Trigger exception interrupts are enabled. | ||
| 619 | */ | ||
| 620 | #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) | ||
| 621 | #define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) | ||
| 622 | #define ADC_IE_TCOMP_IE_SHIFT (16U) | ||
| 623 | /*! TCOMP_IE - Trigger Completion Interrupt Enable | ||
| 624 | * 0b0000000000000000..Trigger completion interrupts are disabled. | ||
| 625 | * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. | ||
| 626 | * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. | ||
| 627 | * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. | ||
| 628 | * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. | ||
| 629 | */ | ||
| 630 | #define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) | ||
| 631 | /*! @} */ | ||
| 632 | |||
| 633 | /*! @name DE - DMA Enable Register */ | ||
| 634 | /*! @{ */ | ||
| 635 | #define ADC_DE_FWMDE0_MASK (0x1U) | ||
| 636 | #define ADC_DE_FWMDE0_SHIFT (0U) | ||
| 637 | /*! FWMDE0 - FIFO 0 Watermark DMA Enable | ||
| 638 | * 0b0..DMA request disabled. | ||
| 639 | * 0b1..DMA request enabled. | ||
| 640 | */ | ||
| 641 | #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) | ||
| 642 | #define ADC_DE_FWMDE1_MASK (0x2U) | ||
| 643 | #define ADC_DE_FWMDE1_SHIFT (1U) | ||
| 644 | /*! FWMDE1 - FIFO1 Watermark DMA Enable | ||
| 645 | * 0b0..DMA request disabled. | ||
| 646 | * 0b1..DMA request enabled. | ||
| 647 | */ | ||
| 648 | #define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) | ||
| 649 | /*! @} */ | ||
| 650 | |||
| 651 | /*! @name CFG - ADC Configuration Register */ | ||
| 652 | /*! @{ */ | ||
| 653 | #define ADC_CFG_TPRICTRL_MASK (0x3U) | ||
| 654 | #define ADC_CFG_TPRICTRL_SHIFT (0U) | ||
| 655 | /*! TPRICTRL - ADC trigger priority control | ||
| 656 | * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted | ||
| 657 | * and the new command specified by the trigger is started. | ||
| 658 | * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after | ||
| 659 | * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. | ||
| 660 | * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. | ||
| 661 | * 0b10..If a higher priority trigger is received during command processing, the current command will be | ||
| 662 | * completed (averaging, looping, compare) before servicing the higher priority trigger. | ||
| 663 | * 0b11..RESERVED | ||
| 664 | */ | ||
| 665 | #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) | ||
| 666 | #define ADC_CFG_PWRSEL_MASK (0x30U) | ||
| 667 | #define ADC_CFG_PWRSEL_SHIFT (4U) | ||
| 668 | /*! PWRSEL - Power Configuration Select | ||
| 669 | * 0b00..Lowest power setting. | ||
| 670 | * 0b01..Higher power setting than 0b0. | ||
| 671 | * 0b10..Higher power setting than 0b1. | ||
| 672 | * 0b11..Highest power setting. | ||
| 673 | */ | ||
| 674 | #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) | ||
| 675 | #define ADC_CFG_REFSEL_MASK (0xC0U) | ||
| 676 | #define ADC_CFG_REFSEL_SHIFT (6U) | ||
| 677 | /*! REFSEL - Voltage Reference Selection | ||
| 678 | * 0b00..(Default) Option 1 setting. | ||
| 679 | * 0b01..Option 2 setting. | ||
| 680 | * 0b10..Option 3 setting. | ||
| 681 | * 0b11..Reserved | ||
| 682 | */ | ||
| 683 | #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) | ||
| 684 | #define ADC_CFG_TRES_MASK (0x100U) | ||
| 685 | #define ADC_CFG_TRES_SHIFT (8U) | ||
| 686 | /*! TRES - Trigger Resume Enable | ||
| 687 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. | ||
| 688 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. | ||
| 689 | */ | ||
| 690 | #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) | ||
| 691 | #define ADC_CFG_TCMDRES_MASK (0x200U) | ||
| 692 | #define ADC_CFG_TCMDRES_SHIFT (9U) | ||
| 693 | /*! TCMDRES - Trigger Command Resume | ||
| 694 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. | ||
| 695 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. | ||
| 696 | */ | ||
| 697 | #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) | ||
| 698 | #define ADC_CFG_HPT_EXDI_MASK (0x400U) | ||
| 699 | #define ADC_CFG_HPT_EXDI_SHIFT (10U) | ||
| 700 | /*! HPT_EXDI - High Priority Trigger Exception Disable | ||
| 701 | * 0b0..High priority trigger exceptions are enabled. | ||
| 702 | * 0b1..High priority trigger exceptions are disabled. | ||
| 703 | */ | ||
| 704 | #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) | ||
| 705 | #define ADC_CFG_PUDLY_MASK (0xFF0000U) | ||
| 706 | #define ADC_CFG_PUDLY_SHIFT (16U) | ||
| 707 | /*! PUDLY - Power Up Delay | ||
| 708 | */ | ||
| 709 | #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) | ||
| 710 | #define ADC_CFG_PWREN_MASK (0x10000000U) | ||
| 711 | #define ADC_CFG_PWREN_SHIFT (28U) | ||
| 712 | /*! PWREN - ADC Analog Pre-Enable | ||
| 713 | * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. | ||
| 714 | * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost | ||
| 715 | * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN | ||
| 716 | * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. | ||
| 717 | * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be | ||
| 718 | * executed. | ||
| 719 | */ | ||
| 720 | #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) | ||
| 721 | /*! @} */ | ||
| 722 | |||
| 723 | /*! @name PAUSE - ADC Pause Register */ | ||
| 724 | /*! @{ */ | ||
| 725 | #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) | ||
| 726 | #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) | ||
| 727 | /*! PAUSEDLY - Pause Delay | ||
| 728 | */ | ||
| 729 | #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) | ||
| 730 | #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) | ||
| 731 | #define ADC_PAUSE_PAUSEEN_SHIFT (31U) | ||
| 732 | /*! PAUSEEN - PAUSE Option Enable | ||
| 733 | * 0b0..Pause operation disabled | ||
| 734 | * 0b1..Pause operation enabled | ||
| 735 | */ | ||
| 736 | #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) | ||
| 737 | /*! @} */ | ||
| 738 | |||
| 739 | /*! @name SWTRIG - Software Trigger Register */ | ||
| 740 | /*! @{ */ | ||
| 741 | #define ADC_SWTRIG_SWT0_MASK (0x1U) | ||
| 742 | #define ADC_SWTRIG_SWT0_SHIFT (0U) | ||
| 743 | /*! SWT0 - Software trigger 0 event | ||
| 744 | * 0b0..No trigger 0 event generated. | ||
| 745 | * 0b1..Trigger 0 event generated. | ||
| 746 | */ | ||
| 747 | #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) | ||
| 748 | #define ADC_SWTRIG_SWT1_MASK (0x2U) | ||
| 749 | #define ADC_SWTRIG_SWT1_SHIFT (1U) | ||
| 750 | /*! SWT1 - Software trigger 1 event | ||
| 751 | * 0b0..No trigger 1 event generated. | ||
| 752 | * 0b1..Trigger 1 event generated. | ||
| 753 | */ | ||
| 754 | #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) | ||
| 755 | #define ADC_SWTRIG_SWT2_MASK (0x4U) | ||
| 756 | #define ADC_SWTRIG_SWT2_SHIFT (2U) | ||
| 757 | /*! SWT2 - Software trigger 2 event | ||
| 758 | * 0b0..No trigger 2 event generated. | ||
| 759 | * 0b1..Trigger 2 event generated. | ||
| 760 | */ | ||
| 761 | #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) | ||
| 762 | #define ADC_SWTRIG_SWT3_MASK (0x8U) | ||
| 763 | #define ADC_SWTRIG_SWT3_SHIFT (3U) | ||
| 764 | /*! SWT3 - Software trigger 3 event | ||
| 765 | * 0b0..No trigger 3 event generated. | ||
| 766 | * 0b1..Trigger 3 event generated. | ||
| 767 | */ | ||
| 768 | #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) | ||
| 769 | #define ADC_SWTRIG_SWT4_MASK (0x10U) | ||
| 770 | #define ADC_SWTRIG_SWT4_SHIFT (4U) | ||
| 771 | /*! SWT4 - Software trigger 4 event | ||
| 772 | * 0b0..No trigger 4 event generated. | ||
| 773 | * 0b1..Trigger 4 event generated. | ||
| 774 | */ | ||
| 775 | #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) | ||
| 776 | #define ADC_SWTRIG_SWT5_MASK (0x20U) | ||
| 777 | #define ADC_SWTRIG_SWT5_SHIFT (5U) | ||
| 778 | /*! SWT5 - Software trigger 5 event | ||
| 779 | * 0b0..No trigger 5 event generated. | ||
| 780 | * 0b1..Trigger 5 event generated. | ||
| 781 | */ | ||
| 782 | #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) | ||
| 783 | #define ADC_SWTRIG_SWT6_MASK (0x40U) | ||
| 784 | #define ADC_SWTRIG_SWT6_SHIFT (6U) | ||
| 785 | /*! SWT6 - Software trigger 6 event | ||
| 786 | * 0b0..No trigger 6 event generated. | ||
| 787 | * 0b1..Trigger 6 event generated. | ||
| 788 | */ | ||
| 789 | #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) | ||
| 790 | #define ADC_SWTRIG_SWT7_MASK (0x80U) | ||
| 791 | #define ADC_SWTRIG_SWT7_SHIFT (7U) | ||
| 792 | /*! SWT7 - Software trigger 7 event | ||
| 793 | * 0b0..No trigger 7 event generated. | ||
| 794 | * 0b1..Trigger 7 event generated. | ||
| 795 | */ | ||
| 796 | #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) | ||
| 797 | #define ADC_SWTRIG_SWT8_MASK (0x100U) | ||
| 798 | #define ADC_SWTRIG_SWT8_SHIFT (8U) | ||
| 799 | /*! SWT8 - Software trigger 8 event | ||
| 800 | * 0b0..No trigger 8 event generated. | ||
| 801 | * 0b1..Trigger 8 event generated. | ||
| 802 | */ | ||
| 803 | #define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) | ||
| 804 | #define ADC_SWTRIG_SWT9_MASK (0x200U) | ||
| 805 | #define ADC_SWTRIG_SWT9_SHIFT (9U) | ||
| 806 | /*! SWT9 - Software trigger 9 event | ||
| 807 | * 0b0..No trigger 9 event generated. | ||
| 808 | * 0b1..Trigger 9 event generated. | ||
| 809 | */ | ||
| 810 | #define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) | ||
| 811 | #define ADC_SWTRIG_SWT10_MASK (0x400U) | ||
| 812 | #define ADC_SWTRIG_SWT10_SHIFT (10U) | ||
| 813 | /*! SWT10 - Software trigger 10 event | ||
| 814 | * 0b0..No trigger 10 event generated. | ||
| 815 | * 0b1..Trigger 10 event generated. | ||
| 816 | */ | ||
| 817 | #define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) | ||
| 818 | #define ADC_SWTRIG_SWT11_MASK (0x800U) | ||
| 819 | #define ADC_SWTRIG_SWT11_SHIFT (11U) | ||
| 820 | /*! SWT11 - Software trigger 11 event | ||
| 821 | * 0b0..No trigger 11 event generated. | ||
| 822 | * 0b1..Trigger 11 event generated. | ||
| 823 | */ | ||
| 824 | #define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) | ||
| 825 | #define ADC_SWTRIG_SWT12_MASK (0x1000U) | ||
| 826 | #define ADC_SWTRIG_SWT12_SHIFT (12U) | ||
| 827 | /*! SWT12 - Software trigger 12 event | ||
| 828 | * 0b0..No trigger 12 event generated. | ||
| 829 | * 0b1..Trigger 12 event generated. | ||
| 830 | */ | ||
| 831 | #define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) | ||
| 832 | #define ADC_SWTRIG_SWT13_MASK (0x2000U) | ||
| 833 | #define ADC_SWTRIG_SWT13_SHIFT (13U) | ||
| 834 | /*! SWT13 - Software trigger 13 event | ||
| 835 | * 0b0..No trigger 13 event generated. | ||
| 836 | * 0b1..Trigger 13 event generated. | ||
| 837 | */ | ||
| 838 | #define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) | ||
| 839 | #define ADC_SWTRIG_SWT14_MASK (0x4000U) | ||
| 840 | #define ADC_SWTRIG_SWT14_SHIFT (14U) | ||
| 841 | /*! SWT14 - Software trigger 14 event | ||
| 842 | * 0b0..No trigger 14 event generated. | ||
| 843 | * 0b1..Trigger 14 event generated. | ||
| 844 | */ | ||
| 845 | #define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) | ||
| 846 | #define ADC_SWTRIG_SWT15_MASK (0x8000U) | ||
| 847 | #define ADC_SWTRIG_SWT15_SHIFT (15U) | ||
| 848 | /*! SWT15 - Software trigger 15 event | ||
| 849 | * 0b0..No trigger 15 event generated. | ||
| 850 | * 0b1..Trigger 15 event generated. | ||
| 851 | */ | ||
| 852 | #define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) | ||
| 853 | /*! @} */ | ||
| 854 | |||
| 855 | /*! @name TSTAT - Trigger Status Register */ | ||
| 856 | /*! @{ */ | ||
| 857 | #define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) | ||
| 858 | #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) | ||
| 859 | /*! TEXC_NUM - Trigger Exception Number | ||
| 860 | * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. | ||
| 861 | * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. | ||
| 862 | * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. | ||
| 863 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. | ||
| 864 | * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. | ||
| 865 | */ | ||
| 866 | #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) | ||
| 867 | #define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) | ||
| 868 | #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) | ||
| 869 | /*! TCOMP_FLAG - Trigger Completion Flag | ||
| 870 | * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. | ||
| 871 | * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. | ||
| 872 | * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. | ||
| 873 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. | ||
| 874 | * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. | ||
| 875 | */ | ||
| 876 | #define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) | ||
| 877 | /*! @} */ | ||
| 878 | |||
| 879 | /*! @name OFSTRIM - ADC Offset Trim Register */ | ||
| 880 | /*! @{ */ | ||
| 881 | #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) | ||
| 882 | #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) | ||
| 883 | /*! OFSTRIM_A - Trim for offset | ||
| 884 | */ | ||
| 885 | #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) | ||
| 886 | #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) | ||
| 887 | #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) | ||
| 888 | /*! OFSTRIM_B - Trim for offset | ||
| 889 | */ | ||
| 890 | #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) | ||
| 891 | /*! @} */ | ||
| 892 | |||
| 893 | /*! @name TCTRL - Trigger Control Register */ | ||
| 894 | /*! @{ */ | ||
| 895 | #define ADC_TCTRL_HTEN_MASK (0x1U) | ||
| 896 | #define ADC_TCTRL_HTEN_SHIFT (0U) | ||
| 897 | /*! HTEN - Trigger enable | ||
| 898 | * 0b0..Hardware trigger source disabled | ||
| 899 | * 0b1..Hardware trigger source enabled | ||
| 900 | */ | ||
| 901 | #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) | ||
| 902 | #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) | ||
| 903 | #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) | ||
| 904 | /*! FIFO_SEL_A - SAR Result Destination For Channel A | ||
| 905 | * 0b0..Result written to FIFO 0 | ||
| 906 | * 0b1..Result written to FIFO 1 | ||
| 907 | */ | ||
| 908 | #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) | ||
| 909 | #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) | ||
| 910 | #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) | ||
| 911 | /*! FIFO_SEL_B - SAR Result Destination For Channel B | ||
| 912 | * 0b0..Result written to FIFO 0 | ||
| 913 | * 0b1..Result written to FIFO 1 | ||
| 914 | */ | ||
| 915 | #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) | ||
| 916 | #define ADC_TCTRL_TPRI_MASK (0xF00U) | ||
| 917 | #define ADC_TCTRL_TPRI_SHIFT (8U) | ||
| 918 | /*! TPRI - Trigger priority setting | ||
| 919 | * 0b0000..Set to highest priority, Level 1 | ||
| 920 | * 0b0001-0b1110..Set to corresponding priority level | ||
| 921 | * 0b1111..Set to lowest priority, Level 16 | ||
| 922 | */ | ||
| 923 | #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) | ||
| 924 | #define ADC_TCTRL_RSYNC_MASK (0x8000U) | ||
| 925 | #define ADC_TCTRL_RSYNC_SHIFT (15U) | ||
| 926 | /*! RSYNC - Trigger Resync | ||
| 927 | */ | ||
| 928 | #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) | ||
| 929 | #define ADC_TCTRL_TDLY_MASK (0xF0000U) | ||
| 930 | #define ADC_TCTRL_TDLY_SHIFT (16U) | ||
| 931 | /*! TDLY - Trigger delay select | ||
| 932 | */ | ||
| 933 | #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) | ||
| 934 | #define ADC_TCTRL_TCMD_MASK (0xF000000U) | ||
| 935 | #define ADC_TCTRL_TCMD_SHIFT (24U) | ||
| 936 | /*! TCMD - Trigger command select | ||
| 937 | * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. | ||
| 938 | * 0b0001..CMD1 is executed | ||
| 939 | * 0b0010-0b1110..Corresponding CMD is executed | ||
| 940 | * 0b1111..CMD15 is executed | ||
| 941 | */ | ||
| 942 | #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) | ||
| 943 | /*! @} */ | ||
| 944 | |||
| 945 | /* The count of ADC_TCTRL */ | ||
| 946 | #define ADC_TCTRL_COUNT (16U) | ||
| 947 | |||
| 948 | /*! @name FCTRL - FIFO Control Register */ | ||
| 949 | /*! @{ */ | ||
| 950 | #define ADC_FCTRL_FCOUNT_MASK (0x1FU) | ||
| 951 | #define ADC_FCTRL_FCOUNT_SHIFT (0U) | ||
| 952 | /*! FCOUNT - Result FIFO counter | ||
| 953 | */ | ||
| 954 | #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) | ||
| 955 | #define ADC_FCTRL_FWMARK_MASK (0xF0000U) | ||
| 956 | #define ADC_FCTRL_FWMARK_SHIFT (16U) | ||
| 957 | /*! FWMARK - Watermark level selection | ||
| 958 | */ | ||
| 959 | #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) | ||
| 960 | /*! @} */ | ||
| 961 | |||
| 962 | /* The count of ADC_FCTRL */ | ||
| 963 | #define ADC_FCTRL_COUNT (2U) | ||
| 964 | |||
| 965 | /*! @name GCC - Gain Calibration Control */ | ||
| 966 | /*! @{ */ | ||
| 967 | #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) | ||
| 968 | #define ADC_GCC_GAIN_CAL_SHIFT (0U) | ||
| 969 | /*! GAIN_CAL - Gain Calibration Value | ||
| 970 | */ | ||
| 971 | #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) | ||
| 972 | #define ADC_GCC_RDY_MASK (0x1000000U) | ||
| 973 | #define ADC_GCC_RDY_SHIFT (24U) | ||
| 974 | /*! RDY - Gain Calibration Value Valid | ||
| 975 | * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. | ||
| 976 | * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. | ||
| 977 | */ | ||
| 978 | #define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) | ||
| 979 | /*! @} */ | ||
| 980 | |||
| 981 | /* The count of ADC_GCC */ | ||
| 982 | #define ADC_GCC_COUNT (2U) | ||
| 983 | |||
| 984 | /*! @name GCR - Gain Calculation Result */ | ||
| 985 | /*! @{ */ | ||
| 986 | #define ADC_GCR_GCALR_MASK (0xFFFFU) | ||
| 987 | #define ADC_GCR_GCALR_SHIFT (0U) | ||
| 988 | /*! GCALR - Gain Calculation Result | ||
| 989 | */ | ||
| 990 | #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) | ||
| 991 | #define ADC_GCR_RDY_MASK (0x1000000U) | ||
| 992 | #define ADC_GCR_RDY_SHIFT (24U) | ||
| 993 | /*! RDY - Gain Calculation Ready | ||
| 994 | * 0b0..The gain offset calculation value is invalid. | ||
| 995 | * 0b1..The gain calibration value is valid. | ||
| 996 | */ | ||
| 997 | #define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) | ||
| 998 | /*! @} */ | ||
| 999 | |||
| 1000 | /* The count of ADC_GCR */ | ||
| 1001 | #define ADC_GCR_COUNT (2U) | ||
| 1002 | |||
| 1003 | /*! @name CMDL - ADC Command Low Buffer Register */ | ||
| 1004 | /*! @{ */ | ||
| 1005 | #define ADC_CMDL_ADCH_MASK (0x1FU) | ||
| 1006 | #define ADC_CMDL_ADCH_SHIFT (0U) | ||
| 1007 | /*! ADCH - Input channel select | ||
| 1008 | * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. | ||
| 1009 | * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. | ||
| 1010 | * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. | ||
| 1011 | * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. | ||
| 1012 | * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. | ||
| 1013 | * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. | ||
| 1014 | * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. | ||
| 1015 | */ | ||
| 1016 | #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) | ||
| 1017 | #define ADC_CMDL_CTYPE_MASK (0x60U) | ||
| 1018 | #define ADC_CMDL_CTYPE_SHIFT (5U) | ||
| 1019 | /*! CTYPE - Conversion Type | ||
| 1020 | * 0b00..Single-Ended Mode. Only A side channel is converted. | ||
| 1021 | * 0b01..Single-Ended Mode. Only B side channel is converted. | ||
| 1022 | * 0b10..Differential Mode. A-B. | ||
| 1023 | * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. | ||
| 1024 | */ | ||
| 1025 | #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) | ||
| 1026 | #define ADC_CMDL_MODE_MASK (0x80U) | ||
| 1027 | #define ADC_CMDL_MODE_SHIFT (7U) | ||
| 1028 | /*! MODE - Select resolution of conversions | ||
| 1029 | * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. | ||
| 1030 | * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. | ||
| 1031 | */ | ||
| 1032 | #define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) | ||
| 1033 | /*! @} */ | ||
| 1034 | |||
| 1035 | /* The count of ADC_CMDL */ | ||
| 1036 | #define ADC_CMDL_COUNT (15U) | ||
| 1037 | |||
| 1038 | /*! @name CMDH - ADC Command High Buffer Register */ | ||
| 1039 | /*! @{ */ | ||
| 1040 | #define ADC_CMDH_CMPEN_MASK (0x3U) | ||
| 1041 | #define ADC_CMDH_CMPEN_SHIFT (0U) | ||
| 1042 | /*! CMPEN - Compare Function Enable | ||
| 1043 | * 0b00..Compare disabled. | ||
| 1044 | * 0b01..Reserved | ||
| 1045 | * 0b10..Compare enabled. Store on true. | ||
| 1046 | * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. | ||
| 1047 | */ | ||
| 1048 | #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) | ||
| 1049 | #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) | ||
| 1050 | #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) | ||
| 1051 | /*! WAIT_TRIG - Wait for trigger assertion before execution. | ||
| 1052 | * 0b0..This command will be automatically executed. | ||
| 1053 | * 0b1..The active trigger must be asserted again before executing this command. | ||
| 1054 | */ | ||
| 1055 | #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) | ||
| 1056 | #define ADC_CMDH_LWI_MASK (0x80U) | ||
| 1057 | #define ADC_CMDH_LWI_SHIFT (7U) | ||
| 1058 | /*! LWI - Loop with Increment | ||
| 1059 | * 0b0..Auto channel increment disabled | ||
| 1060 | * 0b1..Auto channel increment enabled | ||
| 1061 | */ | ||
| 1062 | #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) | ||
| 1063 | #define ADC_CMDH_STS_MASK (0x700U) | ||
| 1064 | #define ADC_CMDH_STS_SHIFT (8U) | ||
| 1065 | /*! STS - Sample Time Select | ||
| 1066 | * 0b000..Minimum sample time of 3 ADCK cycles. | ||
| 1067 | * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. | ||
| 1068 | * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. | ||
| 1069 | * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. | ||
| 1070 | * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. | ||
| 1071 | * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. | ||
| 1072 | * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. | ||
| 1073 | * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. | ||
| 1074 | */ | ||
| 1075 | #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) | ||
| 1076 | #define ADC_CMDH_AVGS_MASK (0x7000U) | ||
| 1077 | #define ADC_CMDH_AVGS_SHIFT (12U) | ||
| 1078 | /*! AVGS - Hardware Average Select | ||
| 1079 | * 0b000..Single conversion. | ||
| 1080 | * 0b001..2 conversions averaged. | ||
| 1081 | * 0b010..4 conversions averaged. | ||
| 1082 | * 0b011..8 conversions averaged. | ||
| 1083 | * 0b100..16 conversions averaged. | ||
| 1084 | * 0b101..32 conversions averaged. | ||
| 1085 | * 0b110..64 conversions averaged. | ||
| 1086 | * 0b111..128 conversions averaged. | ||
| 1087 | */ | ||
| 1088 | #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) | ||
| 1089 | #define ADC_CMDH_LOOP_MASK (0xF0000U) | ||
| 1090 | #define ADC_CMDH_LOOP_SHIFT (16U) | ||
| 1091 | /*! LOOP - Loop Count Select | ||
| 1092 | * 0b0000..Looping not enabled. Command executes 1 time. | ||
| 1093 | * 0b0001..Loop 1 time. Command executes 2 times. | ||
| 1094 | * 0b0010..Loop 2 times. Command executes 3 times. | ||
| 1095 | * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. | ||
| 1096 | * 0b1111..Loop 15 times. Command executes 16 times. | ||
| 1097 | */ | ||
| 1098 | #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) | ||
| 1099 | #define ADC_CMDH_NEXT_MASK (0xF000000U) | ||
| 1100 | #define ADC_CMDH_NEXT_SHIFT (24U) | ||
| 1101 | /*! NEXT - Next Command Select | ||
| 1102 | * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority | ||
| 1103 | * trigger pending, begin command associated with lower priority trigger. | ||
| 1104 | * 0b0001..Select CMD1 command buffer register as next command. | ||
| 1105 | * 0b0010-0b1110..Select corresponding CMD command buffer register as next command | ||
| 1106 | * 0b1111..Select CMD15 command buffer register as next command. | ||
| 1107 | */ | ||
| 1108 | #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) | ||
| 1109 | /*! @} */ | ||
| 1110 | |||
| 1111 | /* The count of ADC_CMDH */ | ||
| 1112 | #define ADC_CMDH_COUNT (15U) | ||
| 1113 | |||
| 1114 | /*! @name CV - Compare Value Register */ | ||
| 1115 | /*! @{ */ | ||
| 1116 | #define ADC_CV_CVL_MASK (0xFFFFU) | ||
| 1117 | #define ADC_CV_CVL_SHIFT (0U) | ||
| 1118 | /*! CVL - Compare Value Low. | ||
| 1119 | */ | ||
| 1120 | #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) | ||
| 1121 | #define ADC_CV_CVH_MASK (0xFFFF0000U) | ||
| 1122 | #define ADC_CV_CVH_SHIFT (16U) | ||
| 1123 | /*! CVH - Compare Value High. | ||
| 1124 | */ | ||
| 1125 | #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) | ||
| 1126 | /*! @} */ | ||
| 1127 | |||
| 1128 | /* The count of ADC_CV */ | ||
| 1129 | #define ADC_CV_COUNT (4U) | ||
| 1130 | |||
| 1131 | /*! @name RESFIFO - ADC Data Result FIFO Register */ | ||
| 1132 | /*! @{ */ | ||
| 1133 | #define ADC_RESFIFO_D_MASK (0xFFFFU) | ||
| 1134 | #define ADC_RESFIFO_D_SHIFT (0U) | ||
| 1135 | /*! D - Data result | ||
| 1136 | */ | ||
| 1137 | #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) | ||
| 1138 | #define ADC_RESFIFO_TSRC_MASK (0xF0000U) | ||
| 1139 | #define ADC_RESFIFO_TSRC_SHIFT (16U) | ||
| 1140 | /*! TSRC - Trigger Source | ||
| 1141 | * 0b0000..Trigger source 0 initiated this conversion. | ||
| 1142 | * 0b0001..Trigger source 1 initiated this conversion. | ||
| 1143 | * 0b0010-0b1110..Corresponding trigger source initiated this conversion. | ||
| 1144 | * 0b1111..Trigger source 15 initiated this conversion. | ||
| 1145 | */ | ||
| 1146 | #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) | ||
| 1147 | #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) | ||
| 1148 | #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) | ||
| 1149 | /*! LOOPCNT - Loop count value | ||
| 1150 | * 0b0000..Result is from initial conversion in command. | ||
| 1151 | * 0b0001..Result is from second conversion in command. | ||
| 1152 | * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. | ||
| 1153 | * 0b1111..Result is from 16th conversion in command. | ||
| 1154 | */ | ||
| 1155 | #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) | ||
| 1156 | #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) | ||
| 1157 | #define ADC_RESFIFO_CMDSRC_SHIFT (24U) | ||
| 1158 | /*! CMDSRC - Command Buffer Source | ||
| 1159 | * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state | ||
| 1160 | * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. | ||
| 1161 | * 0b0001..CMD1 buffer used as control settings for this conversion. | ||
| 1162 | * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. | ||
| 1163 | * 0b1111..CMD15 buffer used as control settings for this conversion. | ||
| 1164 | */ | ||
| 1165 | #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) | ||
| 1166 | #define ADC_RESFIFO_VALID_MASK (0x80000000U) | ||
| 1167 | #define ADC_RESFIFO_VALID_SHIFT (31U) | ||
| 1168 | /*! VALID - FIFO entry is valid | ||
| 1169 | * 0b0..FIFO is empty. Discard any read from RESFIFO. | ||
| 1170 | * 0b1..FIFO record read from RESFIFO is valid. | ||
| 1171 | */ | ||
| 1172 | #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) | ||
| 1173 | /*! @} */ | ||
| 1174 | |||
| 1175 | /* The count of ADC_RESFIFO */ | ||
| 1176 | #define ADC_RESFIFO_COUNT (2U) | ||
| 1177 | |||
| 1178 | /*! @name CAL_GAR - Calibration General A-Side Registers */ | ||
| 1179 | /*! @{ */ | ||
| 1180 | #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) | ||
| 1181 | #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) | ||
| 1182 | /*! CAL_GAR_VAL - Calibration General A Side Register Element | ||
| 1183 | */ | ||
| 1184 | #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) | ||
| 1185 | /*! @} */ | ||
| 1186 | |||
| 1187 | /* The count of ADC_CAL_GAR */ | ||
| 1188 | #define ADC_CAL_GAR_COUNT (33U) | ||
| 1189 | |||
| 1190 | /*! @name CAL_GBR - Calibration General B-Side Registers */ | ||
| 1191 | /*! @{ */ | ||
| 1192 | #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) | ||
| 1193 | #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) | ||
| 1194 | /*! CAL_GBR_VAL - Calibration General B Side Register Element | ||
| 1195 | */ | ||
| 1196 | #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) | ||
| 1197 | /*! @} */ | ||
| 1198 | |||
| 1199 | /* The count of ADC_CAL_GBR */ | ||
| 1200 | #define ADC_CAL_GBR_COUNT (33U) | ||
| 1201 | |||
| 1202 | |||
| 1203 | /*! | ||
| 1204 | * @} | ||
| 1205 | */ /* end of group ADC_Register_Masks */ | ||
| 1206 | |||
| 1207 | |||
| 1208 | /* ADC - Peripheral instance base addresses */ | ||
| 1209 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 1210 | /** Peripheral ADC0 base address */ | ||
| 1211 | #define ADC0_BASE (0x500A0000u) | ||
| 1212 | /** Peripheral ADC0 base address */ | ||
| 1213 | #define ADC0_BASE_NS (0x400A0000u) | ||
| 1214 | /** Peripheral ADC0 base pointer */ | ||
| 1215 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1216 | /** Peripheral ADC0 base pointer */ | ||
| 1217 | #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) | ||
| 1218 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1219 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1220 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1221 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1222 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1223 | #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } | ||
| 1224 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1225 | #define ADC_BASE_PTRS_NS { ADC0_NS } | ||
| 1226 | #else | ||
| 1227 | /** Peripheral ADC0 base address */ | ||
| 1228 | #define ADC0_BASE (0x400A0000u) | ||
| 1229 | /** Peripheral ADC0 base pointer */ | ||
| 1230 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1231 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1232 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1233 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1234 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1235 | #endif | ||
| 1236 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1237 | #define ADC_IRQS { ADC0_IRQn } | ||
| 1238 | |||
| 1239 | /*! | ||
| 1240 | * @} | ||
| 1241 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1242 | |||
| 1243 | |||
| 1244 | /* ---------------------------------------------------------------------------- | ||
| 1245 | -- AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1246 | ---------------------------------------------------------------------------- */ | ||
| 1247 | |||
| 1248 | /*! | ||
| 1249 | * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1250 | * @{ | ||
| 1251 | */ | ||
| 1252 | |||
| 1253 | /** AHB_SECURE_CTRL - Register Layout Typedef */ | ||
| 1254 | typedef struct { | ||
| 1255 | struct { /* offset: 0x0, array step: 0x30 */ | ||
| 1256 | __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ | ||
| 1257 | uint8_t RESERVED_0[12]; | ||
| 1258 | __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ | ||
| 1259 | uint8_t RESERVED_1[12]; | ||
| 1260 | __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ | ||
| 1261 | } SEC_CTRL_FLASH_ROM[1]; | ||
| 1262 | struct { /* offset: 0x30, array step: 0x14 */ | ||
| 1263 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ | ||
| 1264 | uint8_t RESERVED_0[12]; | ||
| 1265 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ | ||
| 1266 | } SEC_CTRL_RAMX[1]; | ||
| 1267 | uint8_t RESERVED_0[12]; | ||
| 1268 | struct { /* offset: 0x50, array step: 0x14 */ | ||
| 1269 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */ | ||
| 1270 | uint8_t RESERVED_0[12]; | ||
| 1271 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */ | ||
| 1272 | } SEC_CTRL_RAM0[1]; | ||
| 1273 | uint8_t RESERVED_1[12]; | ||
| 1274 | struct { /* offset: 0x70, array step: 0x14 */ | ||
| 1275 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */ | ||
| 1276 | uint8_t RESERVED_0[12]; | ||
| 1277 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */ | ||
| 1278 | } SEC_CTRL_RAM1[1]; | ||
| 1279 | uint8_t RESERVED_2[12]; | ||
| 1280 | struct { /* offset: 0x90, array step: 0x14 */ | ||
| 1281 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */ | ||
| 1282 | uint8_t RESERVED_0[12]; | ||
| 1283 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */ | ||
| 1284 | } SEC_CTRL_RAM2[1]; | ||
| 1285 | uint8_t RESERVED_3[12]; | ||
| 1286 | struct { /* offset: 0xB0, array step: 0x14 */ | ||
| 1287 | __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0xB0, array step: 0x14 */ | ||
| 1288 | uint8_t RESERVED_0[12]; | ||
| 1289 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0xC0, array step: index*0x14, index2*0x4 */ | ||
| 1290 | } SEC_CTRL_USB_HS[1]; | ||
| 1291 | uint8_t RESERVED_4[12]; | ||
| 1292 | struct { /* offset: 0xD0, array step: 0x30 */ | ||
| 1293 | __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */ | ||
| 1294 | uint8_t RESERVED_0[12]; | ||
| 1295 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */ | ||
| 1296 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */ | ||
| 1297 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */ | ||
| 1298 | uint8_t RESERVED_1[4]; | ||
| 1299 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */ | ||
| 1300 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */ | ||
| 1301 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */ | ||
| 1302 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */ | ||
| 1303 | } SEC_CTRL_APB_BRIDGE[1]; | ||
| 1304 | __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */ | ||
| 1305 | __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */ | ||
| 1306 | uint8_t RESERVED_5[8]; | ||
| 1307 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */ | ||
| 1308 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */ | ||
| 1309 | uint8_t RESERVED_6[8]; | ||
| 1310 | struct { /* offset: 0x120, array step: 0x14 */ | ||
| 1311 | __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */ | ||
| 1312 | __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */ | ||
| 1313 | uint8_t RESERVED_0[8]; | ||
| 1314 | __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */ | ||
| 1315 | } SEC_CTRL_AHB_PORT9[1]; | ||
| 1316 | uint8_t RESERVED_7[3276]; | ||
| 1317 | __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ | ||
| 1318 | uint8_t RESERVED_8[88]; | ||
| 1319 | __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ | ||
| 1320 | uint8_t RESERVED_9[88]; | ||
| 1321 | __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ | ||
| 1322 | uint8_t RESERVED_10[124]; | ||
| 1323 | __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ | ||
| 1324 | __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ | ||
| 1325 | uint8_t RESERVED_11[52]; | ||
| 1326 | __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ | ||
| 1327 | uint8_t RESERVED_12[16]; | ||
| 1328 | __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ | ||
| 1329 | __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ | ||
| 1330 | uint8_t RESERVED_13[20]; | ||
| 1331 | __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ | ||
| 1332 | uint8_t RESERVED_14[8]; | ||
| 1333 | __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ | ||
| 1334 | __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ | ||
| 1335 | } AHB_SECURE_CTRL_Type; | ||
| 1336 | |||
| 1337 | /* ---------------------------------------------------------------------------- | ||
| 1338 | -- AHB_SECURE_CTRL Register Masks | ||
| 1339 | ---------------------------------------------------------------------------- */ | ||
| 1340 | |||
| 1341 | /*! | ||
| 1342 | * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks | ||
| 1343 | * @{ | ||
| 1344 | */ | ||
| 1345 | |||
| 1346 | /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ | ||
| 1347 | /*! @{ */ | ||
| 1348 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) | ||
| 1349 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) | ||
| 1350 | /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF | ||
| 1351 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1352 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1353 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1354 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1355 | */ | ||
| 1356 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) | ||
| 1357 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) | ||
| 1358 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) | ||
| 1359 | /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF | ||
| 1360 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1361 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1362 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1363 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1364 | */ | ||
| 1365 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) | ||
| 1366 | /*! @} */ | ||
| 1367 | |||
| 1368 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ | ||
| 1369 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) | ||
| 1370 | |||
| 1371 | /*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */ | ||
| 1372 | /*! @{ */ | ||
| 1373 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1374 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1375 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1376 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1377 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1378 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1379 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1380 | */ | ||
| 1381 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) | ||
| 1382 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1383 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1384 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1385 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1386 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1387 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1388 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1389 | */ | ||
| 1390 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) | ||
| 1391 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1392 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1393 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1394 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1395 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1396 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1397 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1398 | */ | ||
| 1399 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) | ||
| 1400 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1401 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1402 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1403 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1404 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1405 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1406 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1407 | */ | ||
| 1408 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) | ||
| 1409 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1410 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1411 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1412 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1413 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1414 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1415 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1416 | */ | ||
| 1417 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) | ||
| 1418 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1419 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1420 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1421 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1422 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1423 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1424 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1425 | */ | ||
| 1426 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) | ||
| 1427 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1428 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1429 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1430 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1431 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1432 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1433 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1434 | */ | ||
| 1435 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) | ||
| 1436 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1437 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1438 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1439 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1440 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1441 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1442 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1443 | */ | ||
| 1444 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) | ||
| 1445 | /*! @} */ | ||
| 1446 | |||
| 1447 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1448 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) | ||
| 1449 | |||
| 1450 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1451 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U) | ||
| 1452 | |||
| 1453 | /*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ | ||
| 1454 | /*! @{ */ | ||
| 1455 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1456 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1457 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1458 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1459 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1460 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1461 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1462 | */ | ||
| 1463 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) | ||
| 1464 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1465 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1466 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1467 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1468 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1469 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1470 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1471 | */ | ||
| 1472 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) | ||
| 1473 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1474 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1475 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1476 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1477 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1478 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1479 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1480 | */ | ||
| 1481 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) | ||
| 1482 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1483 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1484 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1485 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1486 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1487 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1488 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1489 | */ | ||
| 1490 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) | ||
| 1491 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1492 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1493 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1494 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1495 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1496 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1497 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1498 | */ | ||
| 1499 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) | ||
| 1500 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1501 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1502 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1503 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1504 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1505 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1506 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1507 | */ | ||
| 1508 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) | ||
| 1509 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1510 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1511 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1512 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1513 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1514 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1515 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1516 | */ | ||
| 1517 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) | ||
| 1518 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1519 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1520 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1521 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1522 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1523 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1524 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1525 | */ | ||
| 1526 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) | ||
| 1527 | /*! @} */ | ||
| 1528 | |||
| 1529 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1530 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) | ||
| 1531 | |||
| 1532 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1533 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) | ||
| 1534 | |||
| 1535 | /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ | ||
| 1536 | /*! @{ */ | ||
| 1537 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) | ||
| 1538 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) | ||
| 1539 | /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF | ||
| 1540 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1541 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1542 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1543 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1544 | */ | ||
| 1545 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) | ||
| 1546 | /*! @} */ | ||
| 1547 | |||
| 1548 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ | ||
| 1549 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) | ||
| 1550 | |||
| 1551 | /*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ | ||
| 1552 | /*! @{ */ | ||
| 1553 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1554 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1555 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1556 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1557 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1558 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1559 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1560 | */ | ||
| 1561 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) | ||
| 1562 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1563 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1564 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1565 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1566 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1567 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1568 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1569 | */ | ||
| 1570 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) | ||
| 1571 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1572 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1573 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1574 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1575 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1576 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1577 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1578 | */ | ||
| 1579 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) | ||
| 1580 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1581 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1582 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1583 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1584 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1585 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1586 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1587 | */ | ||
| 1588 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) | ||
| 1589 | /*! @} */ | ||
| 1590 | |||
| 1591 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1592 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) | ||
| 1593 | |||
| 1594 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1595 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) | ||
| 1596 | |||
| 1597 | /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ | ||
| 1598 | /*! @{ */ | ||
| 1599 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) | ||
| 1600 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) | ||
| 1601 | /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF | ||
| 1602 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1603 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1604 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1605 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1606 | */ | ||
| 1607 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) | ||
| 1608 | /*! @} */ | ||
| 1609 | |||
| 1610 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ | ||
| 1611 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) | ||
| 1612 | |||
| 1613 | /*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ | ||
| 1614 | /*! @{ */ | ||
| 1615 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1616 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1617 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1618 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1619 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1620 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1621 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1622 | */ | ||
| 1623 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) | ||
| 1624 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1625 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1626 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1627 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1628 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1629 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1630 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1631 | */ | ||
| 1632 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) | ||
| 1633 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1634 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1635 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1636 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1637 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1638 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1639 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1640 | */ | ||
| 1641 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) | ||
| 1642 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1643 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1644 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1645 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1646 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1647 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1648 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1649 | */ | ||
| 1650 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) | ||
| 1651 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1652 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1653 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1654 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1655 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1656 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1657 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1658 | */ | ||
| 1659 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) | ||
| 1660 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1661 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1662 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1663 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1664 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1665 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1666 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1667 | */ | ||
| 1668 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) | ||
| 1669 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1670 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1671 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1672 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1673 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1674 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1675 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1676 | */ | ||
| 1677 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) | ||
| 1678 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1679 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1680 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1681 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1682 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1683 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1684 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1685 | */ | ||
| 1686 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) | ||
| 1687 | /*! @} */ | ||
| 1688 | |||
| 1689 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1690 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) | ||
| 1691 | |||
| 1692 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1693 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U) | ||
| 1694 | |||
| 1695 | /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ | ||
| 1696 | /*! @{ */ | ||
| 1697 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) | ||
| 1698 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) | ||
| 1699 | /*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF | ||
| 1700 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1701 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1702 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1703 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1704 | */ | ||
| 1705 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) | ||
| 1706 | /*! @} */ | ||
| 1707 | |||
| 1708 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ | ||
| 1709 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) | ||
| 1710 | |||
| 1711 | /*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ | ||
| 1712 | /*! @{ */ | ||
| 1713 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1714 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1715 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1716 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1717 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1718 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1719 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1720 | */ | ||
| 1721 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) | ||
| 1722 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1723 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1724 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1725 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1726 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1727 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1728 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1729 | */ | ||
| 1730 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) | ||
| 1731 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1732 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1733 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1734 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1735 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1736 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1737 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1738 | */ | ||
| 1739 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) | ||
| 1740 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1741 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1742 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1743 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1744 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1745 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1746 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1747 | */ | ||
| 1748 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) | ||
| 1749 | /*! @} */ | ||
| 1750 | |||
| 1751 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1752 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) | ||
| 1753 | |||
| 1754 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1755 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U) | ||
| 1756 | |||
| 1757 | /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ | ||
| 1758 | /*! @{ */ | ||
| 1759 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) | ||
| 1760 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) | ||
| 1761 | /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF | ||
| 1762 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1763 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1764 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1765 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1766 | */ | ||
| 1767 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) | ||
| 1768 | /*! @} */ | ||
| 1769 | |||
| 1770 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ | ||
| 1771 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) | ||
| 1772 | |||
| 1773 | /*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ | ||
| 1774 | /*! @{ */ | ||
| 1775 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1776 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1777 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1778 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1779 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1780 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1781 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1782 | */ | ||
| 1783 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) | ||
| 1784 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1785 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1786 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1787 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1788 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1789 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1790 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1791 | */ | ||
| 1792 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) | ||
| 1793 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1794 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1795 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1796 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1797 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1798 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1799 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1800 | */ | ||
| 1801 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) | ||
| 1802 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1803 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1804 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1805 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1806 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1807 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1808 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1809 | */ | ||
| 1810 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) | ||
| 1811 | /*! @} */ | ||
| 1812 | |||
| 1813 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1814 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) | ||
| 1815 | |||
| 1816 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1817 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U) | ||
| 1818 | |||
| 1819 | /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ | ||
| 1820 | /*! @{ */ | ||
| 1821 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) | ||
| 1822 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) | ||
| 1823 | /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF | ||
| 1824 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1825 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1826 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1827 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1828 | */ | ||
| 1829 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) | ||
| 1830 | /*! @} */ | ||
| 1831 | |||
| 1832 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ | ||
| 1833 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) | ||
| 1834 | |||
| 1835 | /*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ | ||
| 1836 | /*! @{ */ | ||
| 1837 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) | ||
| 1838 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) | ||
| 1839 | /*! SRAM_SECT_0_RULE - Address space: 0x2001_0000 - 0x2001_0FFF | ||
| 1840 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1841 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1842 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1843 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1844 | */ | ||
| 1845 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) | ||
| 1846 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) | ||
| 1847 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) | ||
| 1848 | /*! SRAM_SECT_1_RULE - Address space: 0x2001_1000 - 0x2001_1FFF | ||
| 1849 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1850 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1851 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1852 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1853 | */ | ||
| 1854 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) | ||
| 1855 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) | ||
| 1856 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) | ||
| 1857 | /*! SRAM_SECT_2_RULE - Address space: 0x2001_2000 - 0x2001_2FFF | ||
| 1858 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1859 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1860 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1861 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1862 | */ | ||
| 1863 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) | ||
| 1864 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) | ||
| 1865 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) | ||
| 1866 | /*! SRAM_SECT_3_RULE - Address space: 0x2001_3000 - 0x2001_3FFF | ||
| 1867 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1868 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1869 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1870 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1871 | */ | ||
| 1872 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) | ||
| 1873 | /*! @} */ | ||
| 1874 | |||
| 1875 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 1876 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) | ||
| 1877 | |||
| 1878 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 1879 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) | ||
| 1880 | |||
| 1881 | /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ | ||
| 1882 | /*! @{ */ | ||
| 1883 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) | ||
| 1884 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) | ||
| 1885 | /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 | ||
| 1886 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1887 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1888 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1889 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1890 | */ | ||
| 1891 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) | ||
| 1892 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) | ||
| 1893 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) | ||
| 1894 | /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 | ||
| 1895 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1896 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1897 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1898 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1899 | */ | ||
| 1900 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) | ||
| 1901 | /*! @} */ | ||
| 1902 | |||
| 1903 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ | ||
| 1904 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) | ||
| 1905 | |||
| 1906 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 1907 | /*! @{ */ | ||
| 1908 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) | ||
| 1909 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) | ||
| 1910 | /*! SYSCON_RULE - System Configuration | ||
| 1911 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1912 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1913 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1914 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1915 | */ | ||
| 1916 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) | ||
| 1917 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) | ||
| 1918 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) | ||
| 1919 | /*! IOCON_RULE - I/O Configuration | ||
| 1920 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1921 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1922 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1923 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1924 | */ | ||
| 1925 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) | ||
| 1926 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) | ||
| 1927 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) | ||
| 1928 | /*! GINT0_RULE - GPIO input Interrupt 0 | ||
| 1929 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1930 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1931 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1932 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1933 | */ | ||
| 1934 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) | ||
| 1935 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) | ||
| 1936 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) | ||
| 1937 | /*! GINT1_RULE - GPIO input Interrupt 1 | ||
| 1938 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1939 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1940 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1941 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1942 | */ | ||
| 1943 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) | ||
| 1944 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) | ||
| 1945 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) | ||
| 1946 | /*! PINT_RULE - Pin Interrupt and Pattern match | ||
| 1947 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1948 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1949 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1950 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1951 | */ | ||
| 1952 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) | ||
| 1953 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) | ||
| 1954 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) | ||
| 1955 | /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match | ||
| 1956 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1957 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1958 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1959 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1960 | */ | ||
| 1961 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) | ||
| 1962 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) | ||
| 1963 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) | ||
| 1964 | /*! INPUTMUX_RULE - Peripheral input multiplexing | ||
| 1965 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1966 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1967 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1968 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1969 | */ | ||
| 1970 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) | ||
| 1971 | /*! @} */ | ||
| 1972 | |||
| 1973 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ | ||
| 1974 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) | ||
| 1975 | |||
| 1976 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 1977 | /*! @{ */ | ||
| 1978 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) | ||
| 1979 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) | ||
| 1980 | /*! CTIMER0_RULE - Standard counter/Timer 0 | ||
| 1981 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1982 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1983 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1984 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1985 | */ | ||
| 1986 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) | ||
| 1987 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) | ||
| 1988 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) | ||
| 1989 | /*! CTIMER1_RULE - Standard counter/Timer 1 | ||
| 1990 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1991 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1992 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1993 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1994 | */ | ||
| 1995 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) | ||
| 1996 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) | ||
| 1997 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) | ||
| 1998 | /*! WWDT_RULE - Windiwed wtachdog Timer | ||
| 1999 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2000 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2001 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2002 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2003 | */ | ||
| 2004 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) | ||
| 2005 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) | ||
| 2006 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) | ||
| 2007 | /*! MRT_RULE - Multi-rate Timer | ||
| 2008 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2009 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2010 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2011 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2012 | */ | ||
| 2013 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) | ||
| 2014 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) | ||
| 2015 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) | ||
| 2016 | /*! UTICK_RULE - Micro-Timer | ||
| 2017 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2018 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2019 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2020 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2021 | */ | ||
| 2022 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) | ||
| 2023 | /*! @} */ | ||
| 2024 | |||
| 2025 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ | ||
| 2026 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) | ||
| 2027 | |||
| 2028 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 2029 | /*! @{ */ | ||
| 2030 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) | ||
| 2031 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) | ||
| 2032 | /*! ANACTRL_RULE - Analog Modules controller | ||
| 2033 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2034 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2035 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2036 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2037 | */ | ||
| 2038 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) | ||
| 2039 | /*! @} */ | ||
| 2040 | |||
| 2041 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ | ||
| 2042 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) | ||
| 2043 | |||
| 2044 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2045 | /*! @{ */ | ||
| 2046 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) | ||
| 2047 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) | ||
| 2048 | /*! PMC_RULE - Power Management Controller | ||
| 2049 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2050 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2051 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2052 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2053 | */ | ||
| 2054 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) | ||
| 2055 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) | ||
| 2056 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) | ||
| 2057 | /*! SYSCTRL_RULE - System Controller | ||
| 2058 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2059 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2060 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2061 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2062 | */ | ||
| 2063 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) | ||
| 2064 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U) | ||
| 2065 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U) | ||
| 2066 | /*! SPI_FILTER_RULE - SPI FILTER control | ||
| 2067 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2068 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2069 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2070 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2071 | */ | ||
| 2072 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK) | ||
| 2073 | /*! @} */ | ||
| 2074 | |||
| 2075 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ | ||
| 2076 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) | ||
| 2077 | |||
| 2078 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2079 | /*! @{ */ | ||
| 2080 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) | ||
| 2081 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) | ||
| 2082 | /*! CTIMER2_RULE - Standard counter/Timer 2 | ||
| 2083 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2084 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2085 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2086 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2087 | */ | ||
| 2088 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) | ||
| 2089 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) | ||
| 2090 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) | ||
| 2091 | /*! CTIMER3_RULE - Standard counter/Timer 3 | ||
| 2092 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2093 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2094 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2095 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2096 | */ | ||
| 2097 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) | ||
| 2098 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) | ||
| 2099 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) | ||
| 2100 | /*! CTIMER4_RULE - Standard counter/Timer 4 | ||
| 2101 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2102 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2103 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2104 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2105 | */ | ||
| 2106 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) | ||
| 2107 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) | ||
| 2108 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) | ||
| 2109 | /*! RTC_RULE - Real Time Counter | ||
| 2110 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2111 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2112 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2113 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2114 | */ | ||
| 2115 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) | ||
| 2116 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) | ||
| 2117 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) | ||
| 2118 | /*! OSEVENT_RULE - OS Event Timer | ||
| 2119 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2120 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2121 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2122 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2123 | */ | ||
| 2124 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) | ||
| 2125 | /*! @} */ | ||
| 2126 | |||
| 2127 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ | ||
| 2128 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) | ||
| 2129 | |||
| 2130 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2131 | /*! @{ */ | ||
| 2132 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) | ||
| 2133 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) | ||
| 2134 | /*! FLASH_CTRL_RULE - Flash Controller | ||
| 2135 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2136 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2137 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2138 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2139 | */ | ||
| 2140 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) | ||
| 2141 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) | ||
| 2142 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) | ||
| 2143 | /*! PRINCE_RULE - Prince | ||
| 2144 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2145 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2146 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2147 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2148 | */ | ||
| 2149 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) | ||
| 2150 | /*! @} */ | ||
| 2151 | |||
| 2152 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ | ||
| 2153 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) | ||
| 2154 | |||
| 2155 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2156 | /*! @{ */ | ||
| 2157 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) | ||
| 2158 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) | ||
| 2159 | /*! USBHPHY_RULE - USB High Speed Phy controller | ||
| 2160 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2161 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2162 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2163 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2164 | */ | ||
| 2165 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) | ||
| 2166 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) | ||
| 2167 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) | ||
| 2168 | /*! RNG_RULE - True Random Number Generator | ||
| 2169 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2170 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2171 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2172 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2173 | */ | ||
| 2174 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) | ||
| 2175 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) | ||
| 2176 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) | ||
| 2177 | /*! PUF_RULE - PUF | ||
| 2178 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2179 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2180 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2181 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2182 | */ | ||
| 2183 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) | ||
| 2184 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) | ||
| 2185 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) | ||
| 2186 | /*! PLU_RULE - Programmable Look-Up logic | ||
| 2187 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2188 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2189 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2190 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2191 | */ | ||
| 2192 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) | ||
| 2193 | /*! @} */ | ||
| 2194 | |||
| 2195 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ | ||
| 2196 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) | ||
| 2197 | |||
| 2198 | /*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2199 | /*! @{ */ | ||
| 2200 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) | ||
| 2201 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) | ||
| 2202 | /*! DMA0_RULE - DMA Controller | ||
| 2203 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2204 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2205 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2206 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2207 | */ | ||
| 2208 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK) | ||
| 2209 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) | ||
| 2210 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) | ||
| 2211 | /*! FS_USB_DEV_RULE - USB Full-speed device | ||
| 2212 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2213 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2214 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2215 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2216 | */ | ||
| 2217 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) | ||
| 2218 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) | ||
| 2219 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U) | ||
| 2220 | /*! SCT_RULE - SCTimer | ||
| 2221 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2222 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2223 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2224 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2225 | */ | ||
| 2226 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK) | ||
| 2227 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) | ||
| 2228 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) | ||
| 2229 | /*! FLEXCOMM0_RULE - Flexcomm interface 0 | ||
| 2230 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2231 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2232 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2233 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2234 | */ | ||
| 2235 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) | ||
| 2236 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) | ||
| 2237 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) | ||
| 2238 | /*! FLEXCOMM1_RULE - Flexcomm interface 1 | ||
| 2239 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2240 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2241 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2242 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2243 | */ | ||
| 2244 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) | ||
| 2245 | /*! @} */ | ||
| 2246 | |||
| 2247 | /*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2248 | /*! @{ */ | ||
| 2249 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) | ||
| 2250 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) | ||
| 2251 | /*! FLEXCOMM2_RULE - Flexcomm interface 2 | ||
| 2252 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2253 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2254 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2255 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2256 | */ | ||
| 2257 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) | ||
| 2258 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) | ||
| 2259 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) | ||
| 2260 | /*! FLEXCOMM3_RULE - Flexcomm interface 3 | ||
| 2261 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2262 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2263 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2264 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2265 | */ | ||
| 2266 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) | ||
| 2267 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) | ||
| 2268 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) | ||
| 2269 | /*! FLEXCOMM4_RULE - Flexcomm interface 4 | ||
| 2270 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2271 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2272 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2273 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2274 | */ | ||
| 2275 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) | ||
| 2276 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) | ||
| 2277 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) | ||
| 2278 | /*! GPIO0_RULE - High Speed GPIO | ||
| 2279 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2280 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2281 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2282 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2283 | */ | ||
| 2284 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK) | ||
| 2285 | /*! @} */ | ||
| 2286 | |||
| 2287 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2288 | /*! @{ */ | ||
| 2289 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) | ||
| 2290 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) | ||
| 2291 | /*! USB_HS_DEV_RULE - USB high Speed device registers | ||
| 2292 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2293 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2294 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2295 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2296 | */ | ||
| 2297 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) | ||
| 2298 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) | ||
| 2299 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U) | ||
| 2300 | /*! CRC_RULE - CRC engine | ||
| 2301 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2302 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2303 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2304 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2305 | */ | ||
| 2306 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK) | ||
| 2307 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) | ||
| 2308 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) | ||
| 2309 | /*! FLEXCOMM5_RULE - Flexcomm interface 5 | ||
| 2310 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2311 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2312 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2313 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2314 | */ | ||
| 2315 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) | ||
| 2316 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) | ||
| 2317 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) | ||
| 2318 | /*! FLEXCOMM6_RULE - Flexcomm interface 6 | ||
| 2319 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2320 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2321 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2322 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2323 | */ | ||
| 2324 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) | ||
| 2325 | /*! @} */ | ||
| 2326 | |||
| 2327 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2328 | /*! @{ */ | ||
| 2329 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) | ||
| 2330 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) | ||
| 2331 | /*! FLEXCOMM7_RULE - Flexcomm interface 7 | ||
| 2332 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2333 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2334 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2335 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2336 | */ | ||
| 2337 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) | ||
| 2338 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) | ||
| 2339 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) | ||
| 2340 | /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) | ||
| 2341 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2342 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2343 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2344 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2345 | */ | ||
| 2346 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) | ||
| 2347 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U) | ||
| 2348 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U) | ||
| 2349 | /*! CAN0_RULE - CAN-FD | ||
| 2350 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2351 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2352 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2353 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2354 | */ | ||
| 2355 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK) | ||
| 2356 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) | ||
| 2357 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) | ||
| 2358 | /*! HS_LSPI_RULE - High Speed SPI | ||
| 2359 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2360 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2361 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2362 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2363 | */ | ||
| 2364 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK) | ||
| 2365 | /*! @} */ | ||
| 2366 | |||
| 2367 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2368 | /*! @{ */ | ||
| 2369 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U) | ||
| 2370 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U) | ||
| 2371 | /*! ADC_RULE - ADC | ||
| 2372 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2373 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2374 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2375 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2376 | */ | ||
| 2377 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK) | ||
| 2378 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) | ||
| 2379 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) | ||
| 2380 | /*! USB_FS_HOST_RULE - USB Full Speed Host registers. | ||
| 2381 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2382 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2383 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2384 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2385 | */ | ||
| 2386 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) | ||
| 2387 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) | ||
| 2388 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) | ||
| 2389 | /*! USB_HS_HOST_RULE - USB High speed host registers | ||
| 2390 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2391 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2392 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2393 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2394 | */ | ||
| 2395 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) | ||
| 2396 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) | ||
| 2397 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U) | ||
| 2398 | /*! HASH_RULE - SHA-2 crypto registers | ||
| 2399 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2400 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2401 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2402 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2403 | */ | ||
| 2404 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK) | ||
| 2405 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) | ||
| 2406 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) | ||
| 2407 | /*! CASPER_RULE - RSA/ECC crypto accelerator | ||
| 2408 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2409 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2410 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2411 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2412 | */ | ||
| 2413 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK) | ||
| 2414 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) | ||
| 2415 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) | ||
| 2416 | /*! DMA1_RULE - DMA Controller (Secure) | ||
| 2417 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2418 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2419 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2420 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2421 | */ | ||
| 2422 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK) | ||
| 2423 | /*! @} */ | ||
| 2424 | |||
| 2425 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */ | ||
| 2426 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U) | ||
| 2427 | |||
| 2428 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2429 | /*! @{ */ | ||
| 2430 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) | ||
| 2431 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) | ||
| 2432 | /*! GPIO1_RULE - Secure High Speed GPIO | ||
| 2433 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2434 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2435 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2436 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2437 | */ | ||
| 2438 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK) | ||
| 2439 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) | ||
| 2440 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) | ||
| 2441 | /*! AHB_SEC_CTRL_RULE - AHB Secure Controller | ||
| 2442 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2443 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2444 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2445 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2446 | */ | ||
| 2447 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) | ||
| 2448 | /*! @} */ | ||
| 2449 | |||
| 2450 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */ | ||
| 2451 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U) | ||
| 2452 | |||
| 2453 | /*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ | ||
| 2454 | /*! @{ */ | ||
| 2455 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) | ||
| 2456 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) | ||
| 2457 | /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF | ||
| 2458 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2459 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2460 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2461 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2462 | */ | ||
| 2463 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) | ||
| 2464 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) | ||
| 2465 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) | ||
| 2466 | /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF | ||
| 2467 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2468 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2469 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2470 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2471 | */ | ||
| 2472 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) | ||
| 2473 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) | ||
| 2474 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) | ||
| 2475 | /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF | ||
| 2476 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2477 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2478 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2479 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2480 | */ | ||
| 2481 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) | ||
| 2482 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) | ||
| 2483 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) | ||
| 2484 | /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF | ||
| 2485 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2486 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2487 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2488 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2489 | */ | ||
| 2490 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) | ||
| 2491 | /*! @} */ | ||
| 2492 | |||
| 2493 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2494 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) | ||
| 2495 | |||
| 2496 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2497 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) | ||
| 2498 | |||
| 2499 | /*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ | ||
| 2500 | /*! @{ */ | ||
| 2501 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) | ||
| 2502 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) | ||
| 2503 | /*! SEC_VIO_ADDR - security violation address for AHB layer | ||
| 2504 | */ | ||
| 2505 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) | ||
| 2506 | /*! @} */ | ||
| 2507 | |||
| 2508 | /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ | ||
| 2509 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U) | ||
| 2510 | |||
| 2511 | /*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ | ||
| 2512 | /*! @{ */ | ||
| 2513 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) | ||
| 2514 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) | ||
| 2515 | /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. | ||
| 2516 | * 0b0..Read access. | ||
| 2517 | * 0b1..Write access. | ||
| 2518 | */ | ||
| 2519 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) | ||
| 2520 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) | ||
| 2521 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) | ||
| 2522 | /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. | ||
| 2523 | * 0b0..Code access. | ||
| 2524 | * 0b1..Data access. | ||
| 2525 | */ | ||
| 2526 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) | ||
| 2527 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) | ||
| 2528 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) | ||
| 2529 | /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level | ||
| 2530 | */ | ||
| 2531 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) | ||
| 2532 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) | ||
| 2533 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) | ||
| 2534 | /*! SEC_VIO_INFO_MASTER - security violation master number | ||
| 2535 | * 0b0000..CPU0 Code. | ||
| 2536 | * 0b0001..CPU0 System. | ||
| 2537 | * 0b0100..USB-HS Device. | ||
| 2538 | * 0b0101..SDMA0. | ||
| 2539 | * 0b1010..HASH. | ||
| 2540 | * 0b1011..USB-FS Host. | ||
| 2541 | * 0b1100..SDMA1. | ||
| 2542 | * 0b1101..CAN-FD. | ||
| 2543 | */ | ||
| 2544 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) | ||
| 2545 | /*! @} */ | ||
| 2546 | |||
| 2547 | /* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ | ||
| 2548 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U) | ||
| 2549 | |||
| 2550 | /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ | ||
| 2551 | /*! @{ */ | ||
| 2552 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) | ||
| 2553 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) | ||
| 2554 | /*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. | ||
| 2555 | * 0b0..Not valid. | ||
| 2556 | * 0b1..Valid (violation occurred). | ||
| 2557 | */ | ||
| 2558 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) | ||
| 2559 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) | ||
| 2560 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) | ||
| 2561 | /*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. | ||
| 2562 | * 0b0..Not valid. | ||
| 2563 | * 0b1..Valid (violation occurred). | ||
| 2564 | */ | ||
| 2565 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) | ||
| 2566 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) | ||
| 2567 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) | ||
| 2568 | /*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. | ||
| 2569 | * 0b0..Not valid. | ||
| 2570 | * 0b1..Valid (violation occurred). | ||
| 2571 | */ | ||
| 2572 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) | ||
| 2573 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) | ||
| 2574 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) | ||
| 2575 | /*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. | ||
| 2576 | * 0b0..Not valid. | ||
| 2577 | * 0b1..Valid (violation occurred). | ||
| 2578 | */ | ||
| 2579 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) | ||
| 2580 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) | ||
| 2581 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) | ||
| 2582 | /*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. | ||
| 2583 | * 0b0..Not valid. | ||
| 2584 | * 0b1..Valid (violation occurred). | ||
| 2585 | */ | ||
| 2586 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) | ||
| 2587 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) | ||
| 2588 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) | ||
| 2589 | /*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. | ||
| 2590 | * 0b0..Not valid. | ||
| 2591 | * 0b1..Valid (violation occurred). | ||
| 2592 | */ | ||
| 2593 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) | ||
| 2594 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) | ||
| 2595 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) | ||
| 2596 | /*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. | ||
| 2597 | * 0b0..Not valid. | ||
| 2598 | * 0b1..Valid (violation occurred). | ||
| 2599 | */ | ||
| 2600 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) | ||
| 2601 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) | ||
| 2602 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) | ||
| 2603 | /*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. | ||
| 2604 | * 0b0..Not valid. | ||
| 2605 | * 0b1..Valid (violation occurred). | ||
| 2606 | */ | ||
| 2607 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) | ||
| 2608 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) | ||
| 2609 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) | ||
| 2610 | /*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. | ||
| 2611 | * 0b0..Not valid. | ||
| 2612 | * 0b1..Valid (violation occurred). | ||
| 2613 | */ | ||
| 2614 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) | ||
| 2615 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) | ||
| 2616 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) | ||
| 2617 | /*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. | ||
| 2618 | * 0b0..Not valid. | ||
| 2619 | * 0b1..Valid (violation occurred). | ||
| 2620 | */ | ||
| 2621 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) | ||
| 2622 | /*! @} */ | ||
| 2623 | |||
| 2624 | /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ | ||
| 2625 | /*! @{ */ | ||
| 2626 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) | ||
| 2627 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) | ||
| 2628 | /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 | ||
| 2629 | * 0b1..Pin state is readable by non-secure world. | ||
| 2630 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2631 | */ | ||
| 2632 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) | ||
| 2633 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) | ||
| 2634 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) | ||
| 2635 | /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 | ||
| 2636 | * 0b1..Pin state is readable by non-secure world. | ||
| 2637 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2638 | */ | ||
| 2639 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) | ||
| 2640 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) | ||
| 2641 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) | ||
| 2642 | /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 | ||
| 2643 | * 0b1..Pin state is readable by non-secure world. | ||
| 2644 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2645 | */ | ||
| 2646 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) | ||
| 2647 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) | ||
| 2648 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) | ||
| 2649 | /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 | ||
| 2650 | * 0b1..Pin state is readable by non-secure world. | ||
| 2651 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2652 | */ | ||
| 2653 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) | ||
| 2654 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) | ||
| 2655 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) | ||
| 2656 | /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 | ||
| 2657 | * 0b1..Pin state is readable by non-secure world. | ||
| 2658 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2659 | */ | ||
| 2660 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) | ||
| 2661 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) | ||
| 2662 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) | ||
| 2663 | /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 | ||
| 2664 | * 0b1..Pin state is readable by non-secure world. | ||
| 2665 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2666 | */ | ||
| 2667 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) | ||
| 2668 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) | ||
| 2669 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) | ||
| 2670 | /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 | ||
| 2671 | * 0b1..Pin state is readable by non-secure world. | ||
| 2672 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2673 | */ | ||
| 2674 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) | ||
| 2675 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) | ||
| 2676 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) | ||
| 2677 | /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 | ||
| 2678 | * 0b1..Pin state is readable by non-secure world. | ||
| 2679 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2680 | */ | ||
| 2681 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) | ||
| 2682 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) | ||
| 2683 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) | ||
| 2684 | /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 | ||
| 2685 | * 0b1..Pin state is readable by non-secure world. | ||
| 2686 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2687 | */ | ||
| 2688 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) | ||
| 2689 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) | ||
| 2690 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) | ||
| 2691 | /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 | ||
| 2692 | * 0b1..Pin state is readable by non-secure world. | ||
| 2693 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2694 | */ | ||
| 2695 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) | ||
| 2696 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) | ||
| 2697 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) | ||
| 2698 | /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 | ||
| 2699 | * 0b1..Pin state is readable by non-secure world. | ||
| 2700 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2701 | */ | ||
| 2702 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) | ||
| 2703 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) | ||
| 2704 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) | ||
| 2705 | /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 | ||
| 2706 | * 0b1..Pin state is readable by non-secure world. | ||
| 2707 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2708 | */ | ||
| 2709 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) | ||
| 2710 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 2711 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) | ||
| 2712 | /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 | ||
| 2713 | * 0b1..Pin state is readable by non-secure world. | ||
| 2714 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2715 | */ | ||
| 2716 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) | ||
| 2717 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 2718 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) | ||
| 2719 | /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 | ||
| 2720 | * 0b1..Pin state is readable by non-secure world. | ||
| 2721 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2722 | */ | ||
| 2723 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) | ||
| 2724 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 2725 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) | ||
| 2726 | /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 | ||
| 2727 | * 0b1..Pin state is readable by non-secure world. | ||
| 2728 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2729 | */ | ||
| 2730 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) | ||
| 2731 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 2732 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) | ||
| 2733 | /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 | ||
| 2734 | * 0b1..Pin state is readable by non-secure world. | ||
| 2735 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2736 | */ | ||
| 2737 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) | ||
| 2738 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 2739 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) | ||
| 2740 | /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 | ||
| 2741 | * 0b1..Pin state is readable by non-secure world. | ||
| 2742 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2743 | */ | ||
| 2744 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) | ||
| 2745 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 2746 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) | ||
| 2747 | /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 | ||
| 2748 | * 0b1..Pin state is readable by non-secure world. | ||
| 2749 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2750 | */ | ||
| 2751 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) | ||
| 2752 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 2753 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) | ||
| 2754 | /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 | ||
| 2755 | * 0b1..Pin state is readable by non-secure world. | ||
| 2756 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2757 | */ | ||
| 2758 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) | ||
| 2759 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 2760 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) | ||
| 2761 | /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 | ||
| 2762 | * 0b1..Pin state is readable by non-secure world. | ||
| 2763 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2764 | */ | ||
| 2765 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) | ||
| 2766 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 2767 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) | ||
| 2768 | /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 | ||
| 2769 | * 0b1..Pin state is readable by non-secure world. | ||
| 2770 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2771 | */ | ||
| 2772 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) | ||
| 2773 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 2774 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) | ||
| 2775 | /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 | ||
| 2776 | * 0b1..Pin state is readable by non-secure world. | ||
| 2777 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2778 | */ | ||
| 2779 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) | ||
| 2780 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 2781 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) | ||
| 2782 | /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 | ||
| 2783 | * 0b1..Pin state is readable by non-secure world. | ||
| 2784 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2785 | */ | ||
| 2786 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) | ||
| 2787 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 2788 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) | ||
| 2789 | /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 | ||
| 2790 | * 0b1..Pin state is readable by non-secure world. | ||
| 2791 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2792 | */ | ||
| 2793 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) | ||
| 2794 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 2795 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) | ||
| 2796 | /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 | ||
| 2797 | * 0b1..Pin state is readable by non-secure world. | ||
| 2798 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2799 | */ | ||
| 2800 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) | ||
| 2801 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 2802 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) | ||
| 2803 | /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 | ||
| 2804 | * 0b1..Pin state is readable by non-secure world. | ||
| 2805 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2806 | */ | ||
| 2807 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) | ||
| 2808 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 2809 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) | ||
| 2810 | /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 | ||
| 2811 | * 0b1..Pin state is readable by non-secure world. | ||
| 2812 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2813 | */ | ||
| 2814 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) | ||
| 2815 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 2816 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) | ||
| 2817 | /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 | ||
| 2818 | * 0b1..Pin state is readable by non-secure world. | ||
| 2819 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2820 | */ | ||
| 2821 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) | ||
| 2822 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 2823 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) | ||
| 2824 | /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 | ||
| 2825 | * 0b1..Pin state is readable by non-secure world. | ||
| 2826 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2827 | */ | ||
| 2828 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) | ||
| 2829 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 2830 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) | ||
| 2831 | /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 | ||
| 2832 | * 0b1..Pin state is readable by non-secure world. | ||
| 2833 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2834 | */ | ||
| 2835 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) | ||
| 2836 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 2837 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) | ||
| 2838 | /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 | ||
| 2839 | * 0b1..Pin state is readable by non-secure world. | ||
| 2840 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2841 | */ | ||
| 2842 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) | ||
| 2843 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 2844 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) | ||
| 2845 | /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 | ||
| 2846 | * 0b1..Pin state is readable by non-secure world. | ||
| 2847 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2848 | */ | ||
| 2849 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) | ||
| 2850 | /*! @} */ | ||
| 2851 | |||
| 2852 | /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ | ||
| 2853 | /*! @{ */ | ||
| 2854 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) | ||
| 2855 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) | ||
| 2856 | /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 | ||
| 2857 | * 0b1..Pin state is readable by non-secure world. | ||
| 2858 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2859 | */ | ||
| 2860 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) | ||
| 2861 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) | ||
| 2862 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) | ||
| 2863 | /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 | ||
| 2864 | * 0b1..Pin state is readable by non-secure world. | ||
| 2865 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2866 | */ | ||
| 2867 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) | ||
| 2868 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) | ||
| 2869 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) | ||
| 2870 | /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 | ||
| 2871 | * 0b1..Pin state is readable by non-secure world. | ||
| 2872 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2873 | */ | ||
| 2874 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) | ||
| 2875 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) | ||
| 2876 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) | ||
| 2877 | /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 | ||
| 2878 | * 0b1..Pin state is readable by non-secure world. | ||
| 2879 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2880 | */ | ||
| 2881 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) | ||
| 2882 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) | ||
| 2883 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) | ||
| 2884 | /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 | ||
| 2885 | * 0b1..Pin state is readable by non-secure world. | ||
| 2886 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2887 | */ | ||
| 2888 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) | ||
| 2889 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) | ||
| 2890 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) | ||
| 2891 | /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 | ||
| 2892 | * 0b1..Pin state is readable by non-secure world. | ||
| 2893 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2894 | */ | ||
| 2895 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) | ||
| 2896 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) | ||
| 2897 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) | ||
| 2898 | /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 | ||
| 2899 | * 0b1..Pin state is readable by non-secure world. | ||
| 2900 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2901 | */ | ||
| 2902 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) | ||
| 2903 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) | ||
| 2904 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) | ||
| 2905 | /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 | ||
| 2906 | * 0b1..Pin state is readable by non-secure world. | ||
| 2907 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2908 | */ | ||
| 2909 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) | ||
| 2910 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) | ||
| 2911 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) | ||
| 2912 | /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 | ||
| 2913 | * 0b1..Pin state is readable by non-secure world. | ||
| 2914 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2915 | */ | ||
| 2916 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) | ||
| 2917 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) | ||
| 2918 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) | ||
| 2919 | /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 | ||
| 2920 | * 0b1..Pin state is readable by non-secure world. | ||
| 2921 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2922 | */ | ||
| 2923 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) | ||
| 2924 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) | ||
| 2925 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) | ||
| 2926 | /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 | ||
| 2927 | * 0b1..Pin state is readable by non-secure world. | ||
| 2928 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2929 | */ | ||
| 2930 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) | ||
| 2931 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) | ||
| 2932 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) | ||
| 2933 | /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 | ||
| 2934 | * 0b1..Pin state is readable by non-secure world. | ||
| 2935 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2936 | */ | ||
| 2937 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) | ||
| 2938 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 2939 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) | ||
| 2940 | /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 | ||
| 2941 | * 0b1..Pin state is readable by non-secure world. | ||
| 2942 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2943 | */ | ||
| 2944 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) | ||
| 2945 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 2946 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) | ||
| 2947 | /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 | ||
| 2948 | * 0b1..Pin state is readable by non-secure world. | ||
| 2949 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2950 | */ | ||
| 2951 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) | ||
| 2952 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 2953 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) | ||
| 2954 | /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 | ||
| 2955 | * 0b1..Pin state is readable by non-secure world. | ||
| 2956 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2957 | */ | ||
| 2958 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) | ||
| 2959 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 2960 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) | ||
| 2961 | /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 | ||
| 2962 | * 0b1..Pin state is readable by non-secure world. | ||
| 2963 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2964 | */ | ||
| 2965 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) | ||
| 2966 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 2967 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) | ||
| 2968 | /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 | ||
| 2969 | * 0b1..Pin state is readable by non-secure world. | ||
| 2970 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2971 | */ | ||
| 2972 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) | ||
| 2973 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 2974 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) | ||
| 2975 | /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 | ||
| 2976 | * 0b1..Pin state is readable by non-secure world. | ||
| 2977 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2978 | */ | ||
| 2979 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) | ||
| 2980 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 2981 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) | ||
| 2982 | /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 | ||
| 2983 | * 0b1..Pin state is readable by non-secure world. | ||
| 2984 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2985 | */ | ||
| 2986 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) | ||
| 2987 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 2988 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) | ||
| 2989 | /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 | ||
| 2990 | * 0b1..Pin state is readable by non-secure world. | ||
| 2991 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2992 | */ | ||
| 2993 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) | ||
| 2994 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 2995 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) | ||
| 2996 | /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 | ||
| 2997 | * 0b1..Pin state is readable by non-secure world. | ||
| 2998 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2999 | */ | ||
| 3000 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) | ||
| 3001 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 3002 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) | ||
| 3003 | /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 | ||
| 3004 | * 0b1..Pin state is readable by non-secure world. | ||
| 3005 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3006 | */ | ||
| 3007 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) | ||
| 3008 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 3009 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) | ||
| 3010 | /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 | ||
| 3011 | * 0b1..Pin state is readable by non-secure world. | ||
| 3012 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3013 | */ | ||
| 3014 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) | ||
| 3015 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 3016 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) | ||
| 3017 | /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 | ||
| 3018 | * 0b1..Pin state is readable by non-secure world. | ||
| 3019 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3020 | */ | ||
| 3021 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) | ||
| 3022 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 3023 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) | ||
| 3024 | /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 | ||
| 3025 | * 0b1..Pin state is readable by non-secure world. | ||
| 3026 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3027 | */ | ||
| 3028 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) | ||
| 3029 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 3030 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) | ||
| 3031 | /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 | ||
| 3032 | * 0b1..Pin state is readable by non-secure world. | ||
| 3033 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3034 | */ | ||
| 3035 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) | ||
| 3036 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 3037 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) | ||
| 3038 | /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 | ||
| 3039 | * 0b1..Pin state is readable by non-secure world. | ||
| 3040 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3041 | */ | ||
| 3042 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) | ||
| 3043 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 3044 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) | ||
| 3045 | /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 | ||
| 3046 | * 0b1..Pin state is readable by non-secure world. | ||
| 3047 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3048 | */ | ||
| 3049 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) | ||
| 3050 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 3051 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) | ||
| 3052 | /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 | ||
| 3053 | * 0b1..Pin state is readable by non-secure world. | ||
| 3054 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3055 | */ | ||
| 3056 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) | ||
| 3057 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 3058 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) | ||
| 3059 | /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 | ||
| 3060 | * 0b1..Pin state is readable by non-secure world. | ||
| 3061 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3062 | */ | ||
| 3063 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) | ||
| 3064 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 3065 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) | ||
| 3066 | /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 | ||
| 3067 | * 0b1..Pin state is readable by non-secure world. | ||
| 3068 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3069 | */ | ||
| 3070 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) | ||
| 3071 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 3072 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) | ||
| 3073 | /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 | ||
| 3074 | * 0b1..Pin state is readable by non-secure world. | ||
| 3075 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3076 | */ | ||
| 3077 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) | ||
| 3078 | /*! @} */ | ||
| 3079 | |||
| 3080 | /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ | ||
| 3081 | /*! @{ */ | ||
| 3082 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) | ||
| 3083 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) | ||
| 3084 | /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. | ||
| 3085 | * 0b10..Writable. | ||
| 3086 | * 0b01..Restricted mode. | ||
| 3087 | */ | ||
| 3088 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) | ||
| 3089 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) | ||
| 3090 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) | ||
| 3091 | /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. | ||
| 3092 | * 0b10..Writable. | ||
| 3093 | * 0b01..Restricted mode. | ||
| 3094 | */ | ||
| 3095 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) | ||
| 3096 | /*! @} */ | ||
| 3097 | |||
| 3098 | /*! @name MASTER_SEC_LEVEL - master secure level register */ | ||
| 3099 | /*! @{ */ | ||
| 3100 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) | ||
| 3101 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) | ||
| 3102 | /*! USBFSD - USB Full Speed Device. | ||
| 3103 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3104 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3105 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3106 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3107 | */ | ||
| 3108 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) | ||
| 3109 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) | ||
| 3110 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) | ||
| 3111 | /*! SDMA0 - System DMA 0. | ||
| 3112 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3113 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3114 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3115 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3116 | */ | ||
| 3117 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) | ||
| 3118 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) | ||
| 3119 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) | ||
| 3120 | /*! HASH - Hash. | ||
| 3121 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3122 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3123 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3124 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3125 | */ | ||
| 3126 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) | ||
| 3127 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) | ||
| 3128 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) | ||
| 3129 | /*! USBFSH - USB Full speed Host. | ||
| 3130 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3131 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3132 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3133 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3134 | */ | ||
| 3135 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) | ||
| 3136 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) | ||
| 3137 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) | ||
| 3138 | /*! SDMA1 - System DMA 1 security level. | ||
| 3139 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3140 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3141 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3142 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3143 | */ | ||
| 3144 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) | ||
| 3145 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U) | ||
| 3146 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U) | ||
| 3147 | /*! CANFD - CAN FD. | ||
| 3148 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3149 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3150 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3151 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3152 | */ | ||
| 3153 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK) | ||
| 3154 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) | ||
| 3155 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) | ||
| 3156 | /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. | ||
| 3157 | * 0b10..Writable. | ||
| 3158 | * 0b01..Restricted mode. | ||
| 3159 | */ | ||
| 3160 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) | ||
| 3161 | /*! @} */ | ||
| 3162 | |||
| 3163 | /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ | ||
| 3164 | /*! @{ */ | ||
| 3165 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) | ||
| 3166 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) | ||
| 3167 | /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) | ||
| 3168 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3169 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3170 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3171 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3172 | */ | ||
| 3173 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) | ||
| 3174 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) | ||
| 3175 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) | ||
| 3176 | /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) | ||
| 3177 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3178 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3179 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3180 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3181 | */ | ||
| 3182 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) | ||
| 3183 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) | ||
| 3184 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) | ||
| 3185 | /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) | ||
| 3186 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3187 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3188 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3189 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3190 | */ | ||
| 3191 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) | ||
| 3192 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) | ||
| 3193 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) | ||
| 3194 | /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) | ||
| 3195 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3196 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3197 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3198 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3199 | */ | ||
| 3200 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) | ||
| 3201 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) | ||
| 3202 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) | ||
| 3203 | /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) | ||
| 3204 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3205 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3206 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3207 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3208 | */ | ||
| 3209 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) | ||
| 3210 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U) | ||
| 3211 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U) | ||
| 3212 | /*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) | ||
| 3213 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3214 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3215 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3216 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3217 | */ | ||
| 3218 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK) | ||
| 3219 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) | ||
| 3220 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) | ||
| 3221 | /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. | ||
| 3222 | * 0b10..Writable. | ||
| 3223 | * 0b01..Restricted mode. | ||
| 3224 | */ | ||
| 3225 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) | ||
| 3226 | /*! @} */ | ||
| 3227 | |||
| 3228 | /*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ | ||
| 3229 | /*! @{ */ | ||
| 3230 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) | ||
| 3231 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) | ||
| 3232 | /*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. | ||
| 3233 | * 0b10..Writable. | ||
| 3234 | * 0b01..Restricted mode. | ||
| 3235 | */ | ||
| 3236 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) | ||
| 3237 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) | ||
| 3238 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) | ||
| 3239 | /*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. | ||
| 3240 | * 0b10..Writable. | ||
| 3241 | * 0b01..Restricted mode. | ||
| 3242 | */ | ||
| 3243 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) | ||
| 3244 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) | ||
| 3245 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) | ||
| 3246 | /*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. | ||
| 3247 | * 0b10..Writable. | ||
| 3248 | * 0b01..Restricted mode. | ||
| 3249 | */ | ||
| 3250 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) | ||
| 3251 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) | ||
| 3252 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) | ||
| 3253 | /*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. | ||
| 3254 | * 0b10..Writable. | ||
| 3255 | * 0b01..Restricted mode. | ||
| 3256 | */ | ||
| 3257 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) | ||
| 3258 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) | ||
| 3259 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) | ||
| 3260 | /*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. | ||
| 3261 | * 0b10..Writable. | ||
| 3262 | * 0b01..Restricted mode. | ||
| 3263 | */ | ||
| 3264 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) | ||
| 3265 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) | ||
| 3266 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) | ||
| 3267 | /*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. | ||
| 3268 | * 0b10..Writable. | ||
| 3269 | * 0b01..Restricted mode. | ||
| 3270 | */ | ||
| 3271 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) | ||
| 3272 | /*! @} */ | ||
| 3273 | |||
| 3274 | /*! @name MISC_CTRL_DP_REG - secure control duplicate register */ | ||
| 3275 | /*! @{ */ | ||
| 3276 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) | ||
| 3277 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) | ||
| 3278 | /*! WRITE_LOCK - Write lock. | ||
| 3279 | * 0b10..Secure control registers can be written. | ||
| 3280 | * 0b01..Restricted mode. | ||
| 3281 | */ | ||
| 3282 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) | ||
| 3283 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 3284 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 3285 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 3286 | * 0b10..Disable check. | ||
| 3287 | * 0b01..Restricted mode. | ||
| 3288 | */ | ||
| 3289 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 3290 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 3291 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 3292 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 3293 | * 0b10..Disable check. | ||
| 3294 | * 0b01..Restricted mode. | ||
| 3295 | */ | ||
| 3296 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 3297 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 3298 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 3299 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 3300 | * 0b10..Disable check. | ||
| 3301 | * 0b01..Restricted mode. | ||
| 3302 | */ | ||
| 3303 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 3304 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 3305 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 3306 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 3307 | * 0b10..Enable abort fort secure checker. | ||
| 3308 | * 0b01..Disable abort fort secure checker. | ||
| 3309 | */ | ||
| 3310 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 3311 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 3312 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 3313 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 3314 | * 0b10..Simple master in strict mode. | ||
| 3315 | * 0b01..Simple master in tier mode. | ||
| 3316 | */ | ||
| 3317 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 3318 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 3319 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 3320 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 3321 | * 0b10..Smart master in strict mode. | ||
| 3322 | * 0b01..Smart master in tier mode. | ||
| 3323 | */ | ||
| 3324 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 3325 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 3326 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 3327 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 3328 | * 0b10..IDAU is enabled. | ||
| 3329 | * 0b01..IDAU is disable. | ||
| 3330 | */ | ||
| 3331 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) | ||
| 3332 | /*! @} */ | ||
| 3333 | |||
| 3334 | /*! @name MISC_CTRL_REG - secure control register */ | ||
| 3335 | /*! @{ */ | ||
| 3336 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) | ||
| 3337 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) | ||
| 3338 | /*! WRITE_LOCK - Write lock. | ||
| 3339 | * 0b10..Secure control registers can be written. | ||
| 3340 | * 0b01..Restricted mode. | ||
| 3341 | */ | ||
| 3342 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) | ||
| 3343 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 3344 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 3345 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 3346 | * 0b10..Disable check. | ||
| 3347 | * 0b01..Restricted mode. | ||
| 3348 | */ | ||
| 3349 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 3350 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 3351 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 3352 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 3353 | * 0b10..Disable check. | ||
| 3354 | * 0b01..Restricted mode. | ||
| 3355 | */ | ||
| 3356 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 3357 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 3358 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 3359 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 3360 | * 0b10..Disable check. | ||
| 3361 | * 0b01..Restricted mode. | ||
| 3362 | */ | ||
| 3363 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 3364 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 3365 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 3366 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 3367 | * 0b10..Enable abort fort secure checker. | ||
| 3368 | * 0b01..Disable abort fort secure checker. | ||
| 3369 | */ | ||
| 3370 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 3371 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 3372 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 3373 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 3374 | * 0b10..Simple master in strict mode. | ||
| 3375 | * 0b01..Simple master in tier mode. | ||
| 3376 | */ | ||
| 3377 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 3378 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 3379 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 3380 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 3381 | * 0b10..Smart master in strict mode. | ||
| 3382 | * 0b01..Smart master in tier mode. | ||
| 3383 | */ | ||
| 3384 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 3385 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 3386 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 3387 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 3388 | * 0b10..IDAU is enabled. | ||
| 3389 | * 0b01..IDAU is disable. | ||
| 3390 | */ | ||
| 3391 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) | ||
| 3392 | /*! @} */ | ||
| 3393 | |||
| 3394 | |||
| 3395 | /*! | ||
| 3396 | * @} | ||
| 3397 | */ /* end of group AHB_SECURE_CTRL_Register_Masks */ | ||
| 3398 | |||
| 3399 | |||
| 3400 | /* AHB_SECURE_CTRL - Peripheral instance base addresses */ | ||
| 3401 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 3402 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3403 | #define AHB_SECURE_CTRL_BASE (0x500AC000u) | ||
| 3404 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3405 | #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) | ||
| 3406 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3407 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 3408 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3409 | #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) | ||
| 3410 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3411 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 3412 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3413 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 3414 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3415 | #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } | ||
| 3416 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3417 | #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } | ||
| 3418 | #else | ||
| 3419 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3420 | #define AHB_SECURE_CTRL_BASE (0x400AC000u) | ||
| 3421 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3422 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 3423 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3424 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 3425 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3426 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 3427 | #endif | ||
| 3428 | |||
| 3429 | /*! | ||
| 3430 | * @} | ||
| 3431 | */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ | ||
| 3432 | |||
| 3433 | |||
| 3434 | /* ---------------------------------------------------------------------------- | ||
| 3435 | -- ANACTRL Peripheral Access Layer | ||
| 3436 | ---------------------------------------------------------------------------- */ | ||
| 3437 | |||
| 3438 | /*! | ||
| 3439 | * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer | ||
| 3440 | * @{ | ||
| 3441 | */ | ||
| 3442 | |||
| 3443 | /** ANACTRL - Register Layout Typedef */ | ||
| 3444 | typedef struct { | ||
| 3445 | uint8_t RESERVED_0[4]; | ||
| 3446 | __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ | ||
| 3447 | uint8_t RESERVED_1[4]; | ||
| 3448 | __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ | ||
| 3449 | __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ | ||
| 3450 | __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ | ||
| 3451 | uint8_t RESERVED_2[8]; | ||
| 3452 | __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ | ||
| 3453 | __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ | ||
| 3454 | uint8_t RESERVED_3[8]; | ||
| 3455 | __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ | ||
| 3456 | __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ | ||
| 3457 | uint8_t RESERVED_4[192]; | ||
| 3458 | __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ | ||
| 3459 | } ANACTRL_Type; | ||
| 3460 | |||
| 3461 | /* ---------------------------------------------------------------------------- | ||
| 3462 | -- ANACTRL Register Masks | ||
| 3463 | ---------------------------------------------------------------------------- */ | ||
| 3464 | |||
| 3465 | /*! | ||
| 3466 | * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks | ||
| 3467 | * @{ | ||
| 3468 | */ | ||
| 3469 | |||
| 3470 | /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ | ||
| 3471 | /*! @{ */ | ||
| 3472 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) | ||
| 3473 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) | ||
| 3474 | /*! FLASH_PWRDWN - Flash Power Down status. | ||
| 3475 | * 0b0..Flash is not in power down mode. | ||
| 3476 | * 0b1..Flash is in power down mode. | ||
| 3477 | */ | ||
| 3478 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) | ||
| 3479 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) | ||
| 3480 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) | ||
| 3481 | /*! FLASH_INIT_ERROR - Flash initialization error status. | ||
| 3482 | * 0b0..No error. | ||
| 3483 | * 0b1..At least one error occured during flash initialization.. | ||
| 3484 | */ | ||
| 3485 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) | ||
| 3486 | /*! @} */ | ||
| 3487 | |||
| 3488 | /*! @name FREQ_ME_CTRL - Frequency Measure function control register */ | ||
| 3489 | /*! @{ */ | ||
| 3490 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) | ||
| 3491 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) | ||
| 3492 | /*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale | ||
| 3493 | */ | ||
| 3494 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) | ||
| 3495 | #define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) | ||
| 3496 | #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) | ||
| 3497 | /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit | ||
| 3498 | * when the measurement cycle has completed and there is valid capture data in the CAPVAL field | ||
| 3499 | * (bits 30:0). | ||
| 3500 | */ | ||
| 3501 | #define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) | ||
| 3502 | /*! @} */ | ||
| 3503 | |||
| 3504 | /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ | ||
| 3505 | /*! @{ */ | ||
| 3506 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) | ||
| 3507 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) | ||
| 3508 | /*! ENA_12MHZCLK - 12 MHz clock control. | ||
| 3509 | * 0b0..12 MHz clock is disabled. | ||
| 3510 | * 0b1..12 MHz clock is enabled. | ||
| 3511 | */ | ||
| 3512 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) | ||
| 3513 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) | ||
| 3514 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) | ||
| 3515 | /*! DAC_TRIM - Frequency trim. | ||
| 3516 | */ | ||
| 3517 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) | ||
| 3518 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) | ||
| 3519 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) | ||
| 3520 | /*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, | ||
| 3521 | * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF | ||
| 3522 | * packets. | ||
| 3523 | */ | ||
| 3524 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) | ||
| 3525 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) | ||
| 3526 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) | ||
| 3527 | /*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. | ||
| 3528 | */ | ||
| 3529 | #define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) | ||
| 3530 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) | ||
| 3531 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) | ||
| 3532 | /*! ENA_96MHZCLK - 96 MHz clock control. | ||
| 3533 | * 0b0..96 MHz clock is disabled. | ||
| 3534 | * 0b1..96 MHz clock is enabled. | ||
| 3535 | */ | ||
| 3536 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) | ||
| 3537 | /*! @} */ | ||
| 3538 | |||
| 3539 | /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ | ||
| 3540 | /*! @{ */ | ||
| 3541 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) | ||
| 3542 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) | ||
| 3543 | /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. | ||
| 3544 | * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). | ||
| 3545 | * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by | ||
| 3546 | * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). | ||
| 3547 | */ | ||
| 3548 | #define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) | ||
| 3549 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) | ||
| 3550 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) | ||
| 3551 | /*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses | ||
| 3552 | * the threshold voltage of a SLVT transistor, this output signal will go high. It is also | ||
| 3553 | * possible to observe the clk_valid signal. | ||
| 3554 | */ | ||
| 3555 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) | ||
| 3556 | /*! @} */ | ||
| 3557 | |||
| 3558 | /*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ | ||
| 3559 | /*! @{ */ | ||
| 3560 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) | ||
| 3561 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) | ||
| 3562 | /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. | ||
| 3563 | * 0b0..XO AC buffer bypass is disabled. | ||
| 3564 | * 0b1..XO AC buffer bypass is enabled. | ||
| 3565 | */ | ||
| 3566 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) | ||
| 3567 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) | ||
| 3568 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) | ||
| 3569 | /*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. | ||
| 3570 | * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. | ||
| 3571 | * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. | ||
| 3572 | */ | ||
| 3573 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) | ||
| 3574 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) | ||
| 3575 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) | ||
| 3576 | /*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. | ||
| 3577 | * 0b0..High speed Crystal oscillator output to CPU system is disabled. | ||
| 3578 | * 0b1..High speed Crystal oscillator output to CPU system is enabled. | ||
| 3579 | */ | ||
| 3580 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) | ||
| 3581 | /*! @} */ | ||
| 3582 | |||
| 3583 | /*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ | ||
| 3584 | /*! @{ */ | ||
| 3585 | #define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) | ||
| 3586 | #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) | ||
| 3587 | /*! XO_READY - Indicates XO out frequency statibilty. | ||
| 3588 | * 0b0..XO output frequency is not yet stable. | ||
| 3589 | * 0b1..XO output frequency is stable. | ||
| 3590 | */ | ||
| 3591 | #define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) | ||
| 3592 | /*! @} */ | ||
| 3593 | |||
| 3594 | /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ | ||
| 3595 | /*! @{ */ | ||
| 3596 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) | ||
| 3597 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) | ||
| 3598 | /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. | ||
| 3599 | * 0b0..BOD VBAT interrupt is disabled. | ||
| 3600 | * 0b1..BOD VBAT interrupt is enabled. | ||
| 3601 | */ | ||
| 3602 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) | ||
| 3603 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) | ||
| 3604 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) | ||
| 3605 | /*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3606 | */ | ||
| 3607 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) | ||
| 3608 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) | ||
| 3609 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) | ||
| 3610 | /*! BODCORE_INT_ENABLE - BOD CORE interrupt control. | ||
| 3611 | * 0b0..BOD CORE interrupt is disabled. | ||
| 3612 | * 0b1..BOD CORE interrupt is enabled. | ||
| 3613 | */ | ||
| 3614 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) | ||
| 3615 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) | ||
| 3616 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) | ||
| 3617 | /*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3618 | */ | ||
| 3619 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) | ||
| 3620 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) | ||
| 3621 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) | ||
| 3622 | /*! DCDC_INT_ENABLE - DCDC interrupt control. | ||
| 3623 | * 0b0..DCDC interrupt is disabled. | ||
| 3624 | * 0b1..DCDC interrupt is enabled. | ||
| 3625 | */ | ||
| 3626 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) | ||
| 3627 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) | ||
| 3628 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) | ||
| 3629 | /*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3630 | */ | ||
| 3631 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) | ||
| 3632 | /*! @} */ | ||
| 3633 | |||
| 3634 | /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ | ||
| 3635 | /*! @{ */ | ||
| 3636 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) | ||
| 3637 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) | ||
| 3638 | /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. | ||
| 3639 | * 0b0..No interrupt pending.. | ||
| 3640 | * 0b1..Interrupt pending.. | ||
| 3641 | */ | ||
| 3642 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) | ||
| 3643 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) | ||
| 3644 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) | ||
| 3645 | /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. | ||
| 3646 | * 0b0..No interrupt pending.. | ||
| 3647 | * 0b1..Interrupt pending.. | ||
| 3648 | */ | ||
| 3649 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) | ||
| 3650 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) | ||
| 3651 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) | ||
| 3652 | /*! BODVBAT_VAL - Current value of BOD VBAT power status output. | ||
| 3653 | * 0b0..VBAT voltage level is below the threshold. | ||
| 3654 | * 0b1..VBAT voltage level is above the threshold. | ||
| 3655 | */ | ||
| 3656 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) | ||
| 3657 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) | ||
| 3658 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) | ||
| 3659 | /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. | ||
| 3660 | * 0b0..No interrupt pending.. | ||
| 3661 | * 0b1..Interrupt pending.. | ||
| 3662 | */ | ||
| 3663 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) | ||
| 3664 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) | ||
| 3665 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) | ||
| 3666 | /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. | ||
| 3667 | * 0b0..No interrupt pending.. | ||
| 3668 | * 0b1..Interrupt pending.. | ||
| 3669 | */ | ||
| 3670 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) | ||
| 3671 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) | ||
| 3672 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) | ||
| 3673 | /*! BODCORE_VAL - Current value of BOD CORE power status output. | ||
| 3674 | * 0b0..CORE voltage level is below the threshold. | ||
| 3675 | * 0b1..CORE voltage level is above the threshold. | ||
| 3676 | */ | ||
| 3677 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) | ||
| 3678 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) | ||
| 3679 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) | ||
| 3680 | /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. | ||
| 3681 | * 0b0..No interrupt pending.. | ||
| 3682 | * 0b1..Interrupt pending.. | ||
| 3683 | */ | ||
| 3684 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) | ||
| 3685 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) | ||
| 3686 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) | ||
| 3687 | /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. | ||
| 3688 | * 0b0..No interrupt pending.. | ||
| 3689 | * 0b1..Interrupt pending.. | ||
| 3690 | */ | ||
| 3691 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) | ||
| 3692 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) | ||
| 3693 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) | ||
| 3694 | /*! DCDC_VAL - Current value of DCDC power status output. | ||
| 3695 | * 0b0..DCDC output Voltage is below the targeted regulation level. | ||
| 3696 | * 0b1..DCDC output Voltage is above the targeted regulation level. | ||
| 3697 | */ | ||
| 3698 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) | ||
| 3699 | /*! @} */ | ||
| 3700 | |||
| 3701 | /*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ | ||
| 3702 | /*! @{ */ | ||
| 3703 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) | ||
| 3704 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) | ||
| 3705 | /*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. | ||
| 3706 | * 0b00..High speed Crystal oscillator output to ADC is disabled. | ||
| 3707 | * 0b01..High speed Crystal oscillator output to ADC is enable. | ||
| 3708 | */ | ||
| 3709 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) | ||
| 3710 | /*! @} */ | ||
| 3711 | |||
| 3712 | |||
| 3713 | /*! | ||
| 3714 | * @} | ||
| 3715 | */ /* end of group ANACTRL_Register_Masks */ | ||
| 3716 | |||
| 3717 | |||
| 3718 | /* ANACTRL - Peripheral instance base addresses */ | ||
| 3719 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 3720 | /** Peripheral ANACTRL base address */ | ||
| 3721 | #define ANACTRL_BASE (0x50013000u) | ||
| 3722 | /** Peripheral ANACTRL base address */ | ||
| 3723 | #define ANACTRL_BASE_NS (0x40013000u) | ||
| 3724 | /** Peripheral ANACTRL base pointer */ | ||
| 3725 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 3726 | /** Peripheral ANACTRL base pointer */ | ||
| 3727 | #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) | ||
| 3728 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3729 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 3730 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3731 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 3732 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3733 | #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } | ||
| 3734 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3735 | #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } | ||
| 3736 | #else | ||
| 3737 | /** Peripheral ANACTRL base address */ | ||
| 3738 | #define ANACTRL_BASE (0x40013000u) | ||
| 3739 | /** Peripheral ANACTRL base pointer */ | ||
| 3740 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 3741 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3742 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 3743 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3744 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 3745 | #endif | ||
| 3746 | |||
| 3747 | /*! | ||
| 3748 | * @} | ||
| 3749 | */ /* end of group ANACTRL_Peripheral_Access_Layer */ | ||
| 3750 | |||
| 3751 | |||
| 3752 | /* ---------------------------------------------------------------------------- | ||
| 3753 | -- CAN Peripheral Access Layer | ||
| 3754 | ---------------------------------------------------------------------------- */ | ||
| 3755 | |||
| 3756 | /*! | ||
| 3757 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 3758 | * @{ | ||
| 3759 | */ | ||
| 3760 | |||
| 3761 | /** CAN - Register Layout Typedef */ | ||
| 3762 | typedef struct { | ||
| 3763 | uint8_t RESERVED_0[12]; | ||
| 3764 | __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ | ||
| 3765 | __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ | ||
| 3766 | uint8_t RESERVED_1[4]; | ||
| 3767 | __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ | ||
| 3768 | __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ | ||
| 3769 | __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ | ||
| 3770 | __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ | ||
| 3771 | __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ | ||
| 3772 | __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ | ||
| 3773 | uint8_t RESERVED_2[16]; | ||
| 3774 | __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ | ||
| 3775 | __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ | ||
| 3776 | __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ | ||
| 3777 | uint8_t RESERVED_3[4]; | ||
| 3778 | __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ | ||
| 3779 | __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ | ||
| 3780 | __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ | ||
| 3781 | __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ | ||
| 3782 | uint8_t RESERVED_4[32]; | ||
| 3783 | __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ | ||
| 3784 | __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ | ||
| 3785 | __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ | ||
| 3786 | uint8_t RESERVED_5[4]; | ||
| 3787 | __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ | ||
| 3788 | __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ | ||
| 3789 | __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ | ||
| 3790 | __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ | ||
| 3791 | __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ | ||
| 3792 | __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ | ||
| 3793 | __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ | ||
| 3794 | __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ | ||
| 3795 | __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ | ||
| 3796 | __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ | ||
| 3797 | __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ | ||
| 3798 | __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ | ||
| 3799 | __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ | ||
| 3800 | __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ | ||
| 3801 | __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ | ||
| 3802 | __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ | ||
| 3803 | __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ | ||
| 3804 | __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ | ||
| 3805 | __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ | ||
| 3806 | __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ | ||
| 3807 | __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ | ||
| 3808 | __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ | ||
| 3809 | uint8_t RESERVED_6[8]; | ||
| 3810 | __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ | ||
| 3811 | __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ | ||
| 3812 | __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ | ||
| 3813 | uint8_t RESERVED_7[260]; | ||
| 3814 | __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ | ||
| 3815 | uint8_t RESERVED_8[508]; | ||
| 3816 | __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ | ||
| 3817 | uint8_t RESERVED_9[508]; | ||
| 3818 | __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ | ||
| 3819 | } CAN_Type; | ||
| 3820 | |||
| 3821 | /* ---------------------------------------------------------------------------- | ||
| 3822 | -- CAN Register Masks | ||
| 3823 | ---------------------------------------------------------------------------- */ | ||
| 3824 | |||
| 3825 | /*! | ||
| 3826 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 3827 | * @{ | ||
| 3828 | */ | ||
| 3829 | |||
| 3830 | /*! @name DBTP - Data Bit Timing Prescaler Register */ | ||
| 3831 | /*! @{ */ | ||
| 3832 | #define CAN_DBTP_DSJW_MASK (0xFU) | ||
| 3833 | #define CAN_DBTP_DSJW_SHIFT (0U) | ||
| 3834 | /*! DSJW - Data (re)synchronization jump width. | ||
| 3835 | */ | ||
| 3836 | #define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) | ||
| 3837 | #define CAN_DBTP_DTSEG2_MASK (0xF0U) | ||
| 3838 | #define CAN_DBTP_DTSEG2_SHIFT (4U) | ||
| 3839 | /*! DTSEG2 - Data time segment after sample point. | ||
| 3840 | */ | ||
| 3841 | #define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) | ||
| 3842 | #define CAN_DBTP_DTSEG1_MASK (0x1F00U) | ||
| 3843 | #define CAN_DBTP_DTSEG1_SHIFT (8U) | ||
| 3844 | /*! DTSEG1 - Data time segment before sample point. | ||
| 3845 | */ | ||
| 3846 | #define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) | ||
| 3847 | #define CAN_DBTP_DBRP_MASK (0x1F0000U) | ||
| 3848 | #define CAN_DBTP_DBRP_SHIFT (16U) | ||
| 3849 | /*! DBRP - Data bit rate prescaler. | ||
| 3850 | */ | ||
| 3851 | #define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) | ||
| 3852 | #define CAN_DBTP_TDC_MASK (0x800000U) | ||
| 3853 | #define CAN_DBTP_TDC_SHIFT (23U) | ||
| 3854 | /*! TDC - Transmitter delay compensation. | ||
| 3855 | */ | ||
| 3856 | #define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) | ||
| 3857 | /*! @} */ | ||
| 3858 | |||
| 3859 | /*! @name TEST - Test Register */ | ||
| 3860 | /*! @{ */ | ||
| 3861 | #define CAN_TEST_LBCK_MASK (0x10U) | ||
| 3862 | #define CAN_TEST_LBCK_SHIFT (4U) | ||
| 3863 | /*! LBCK - Loop back mode. | ||
| 3864 | */ | ||
| 3865 | #define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) | ||
| 3866 | #define CAN_TEST_TX_MASK (0x60U) | ||
| 3867 | #define CAN_TEST_TX_SHIFT (5U) | ||
| 3868 | /*! TX - Control of transmit pin. | ||
| 3869 | */ | ||
| 3870 | #define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) | ||
| 3871 | #define CAN_TEST_RX_MASK (0x80U) | ||
| 3872 | #define CAN_TEST_RX_SHIFT (7U) | ||
| 3873 | /*! RX - Monitors the actual value of the CAN_RXD. | ||
| 3874 | */ | ||
| 3875 | #define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) | ||
| 3876 | /*! @} */ | ||
| 3877 | |||
| 3878 | /*! @name CCCR - CC Control Register */ | ||
| 3879 | /*! @{ */ | ||
| 3880 | #define CAN_CCCR_INIT_MASK (0x1U) | ||
| 3881 | #define CAN_CCCR_INIT_SHIFT (0U) | ||
| 3882 | /*! INIT - Initialization. | ||
| 3883 | */ | ||
| 3884 | #define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) | ||
| 3885 | #define CAN_CCCR_CCE_MASK (0x2U) | ||
| 3886 | #define CAN_CCCR_CCE_SHIFT (1U) | ||
| 3887 | /*! CCE - Configuration change enable. | ||
| 3888 | */ | ||
| 3889 | #define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) | ||
| 3890 | #define CAN_CCCR_ASM_MASK (0x4U) | ||
| 3891 | #define CAN_CCCR_ASM_SHIFT (2U) | ||
| 3892 | /*! ASM - Restricted operational mode. | ||
| 3893 | */ | ||
| 3894 | #define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) | ||
| 3895 | #define CAN_CCCR_CSA_MASK (0x8U) | ||
| 3896 | #define CAN_CCCR_CSA_SHIFT (3U) | ||
| 3897 | /*! CSA - Clock Stop Acknowledge. | ||
| 3898 | */ | ||
| 3899 | #define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) | ||
| 3900 | #define CAN_CCCR_CSR_MASK (0x10U) | ||
| 3901 | #define CAN_CCCR_CSR_SHIFT (4U) | ||
| 3902 | /*! CSR - Clock Stop Request. | ||
| 3903 | */ | ||
| 3904 | #define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) | ||
| 3905 | #define CAN_CCCR_MON_MASK (0x20U) | ||
| 3906 | #define CAN_CCCR_MON_SHIFT (5U) | ||
| 3907 | /*! MON - Bus monitoring mode. | ||
| 3908 | */ | ||
| 3909 | #define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) | ||
| 3910 | #define CAN_CCCR_DAR_MASK (0x40U) | ||
| 3911 | #define CAN_CCCR_DAR_SHIFT (6U) | ||
| 3912 | /*! DAR - Disable automatic retransmission. | ||
| 3913 | */ | ||
| 3914 | #define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) | ||
| 3915 | #define CAN_CCCR_TEST_MASK (0x80U) | ||
| 3916 | #define CAN_CCCR_TEST_SHIFT (7U) | ||
| 3917 | /*! TEST - Test mode enable. | ||
| 3918 | */ | ||
| 3919 | #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) | ||
| 3920 | #define CAN_CCCR_FDOE_MASK (0x100U) | ||
| 3921 | #define CAN_CCCR_FDOE_SHIFT (8U) | ||
| 3922 | /*! FDOE - CAN FD operation enable. | ||
| 3923 | */ | ||
| 3924 | #define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) | ||
| 3925 | #define CAN_CCCR_BRSE_MASK (0x200U) | ||
| 3926 | #define CAN_CCCR_BRSE_SHIFT (9U) | ||
| 3927 | /*! BRSE - When CAN FD operation is disabled, this bit is not evaluated. | ||
| 3928 | */ | ||
| 3929 | #define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) | ||
| 3930 | #define CAN_CCCR_PXHD_MASK (0x1000U) | ||
| 3931 | #define CAN_CCCR_PXHD_SHIFT (12U) | ||
| 3932 | /*! PXHD - Protocol exception handling disable. | ||
| 3933 | */ | ||
| 3934 | #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) | ||
| 3935 | #define CAN_CCCR_EFBI_MASK (0x2000U) | ||
| 3936 | #define CAN_CCCR_EFBI_SHIFT (13U) | ||
| 3937 | /*! EFBI - Edge filtering during bus integration. | ||
| 3938 | */ | ||
| 3939 | #define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) | ||
| 3940 | #define CAN_CCCR_TXP_MASK (0x4000U) | ||
| 3941 | #define CAN_CCCR_TXP_SHIFT (14U) | ||
| 3942 | /*! TXP - Transmit pause. | ||
| 3943 | */ | ||
| 3944 | #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) | ||
| 3945 | #define CAN_CCCR_NISO_MASK (0x8000U) | ||
| 3946 | #define CAN_CCCR_NISO_SHIFT (15U) | ||
| 3947 | /*! NISO - Non ISO operation. | ||
| 3948 | */ | ||
| 3949 | #define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) | ||
| 3950 | /*! @} */ | ||
| 3951 | |||
| 3952 | /*! @name NBTP - Nominal Bit Timing and Prescaler Register */ | ||
| 3953 | /*! @{ */ | ||
| 3954 | #define CAN_NBTP_NTSEG2_MASK (0x7FU) | ||
| 3955 | #define CAN_NBTP_NTSEG2_SHIFT (0U) | ||
| 3956 | /*! NTSEG2 - Nominal time segment after sample point. | ||
| 3957 | */ | ||
| 3958 | #define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) | ||
| 3959 | #define CAN_NBTP_NTSEG1_MASK (0xFF00U) | ||
| 3960 | #define CAN_NBTP_NTSEG1_SHIFT (8U) | ||
| 3961 | /*! NTSEG1 - Nominal time segment before sample point. | ||
| 3962 | */ | ||
| 3963 | #define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) | ||
| 3964 | #define CAN_NBTP_NBRP_MASK (0x1FF0000U) | ||
| 3965 | #define CAN_NBTP_NBRP_SHIFT (16U) | ||
| 3966 | /*! NBRP - Nominal bit rate prescaler. | ||
| 3967 | */ | ||
| 3968 | #define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) | ||
| 3969 | #define CAN_NBTP_NSJW_MASK (0xFE000000U) | ||
| 3970 | #define CAN_NBTP_NSJW_SHIFT (25U) | ||
| 3971 | /*! NSJW - Nominal (re)synchronization jump width. | ||
| 3972 | */ | ||
| 3973 | #define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) | ||
| 3974 | /*! @} */ | ||
| 3975 | |||
| 3976 | /*! @name TSCC - Timestamp Counter Configuration */ | ||
| 3977 | /*! @{ */ | ||
| 3978 | #define CAN_TSCC_TSS_MASK (0x3U) | ||
| 3979 | #define CAN_TSCC_TSS_SHIFT (0U) | ||
| 3980 | /*! TSS - Timestamp select. | ||
| 3981 | */ | ||
| 3982 | #define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) | ||
| 3983 | #define CAN_TSCC_TCP_MASK (0xF0000U) | ||
| 3984 | #define CAN_TSCC_TCP_SHIFT (16U) | ||
| 3985 | /*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. | ||
| 3986 | */ | ||
| 3987 | #define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) | ||
| 3988 | /*! @} */ | ||
| 3989 | |||
| 3990 | /*! @name TSCV - Timestamp Counter Value */ | ||
| 3991 | /*! @{ */ | ||
| 3992 | #define CAN_TSCV_TSC_MASK (0xFFFFU) | ||
| 3993 | #define CAN_TSCV_TSC_SHIFT (0U) | ||
| 3994 | /*! TSC - Timestamp counter. | ||
| 3995 | */ | ||
| 3996 | #define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) | ||
| 3997 | /*! @} */ | ||
| 3998 | |||
| 3999 | /*! @name TOCC - Timeout Counter Configuration */ | ||
| 4000 | /*! @{ */ | ||
| 4001 | #define CAN_TOCC_ETOC_MASK (0x1U) | ||
| 4002 | #define CAN_TOCC_ETOC_SHIFT (0U) | ||
| 4003 | /*! ETOC - Enable timeout counter. | ||
| 4004 | */ | ||
| 4005 | #define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) | ||
| 4006 | #define CAN_TOCC_TOS_MASK (0x6U) | ||
| 4007 | #define CAN_TOCC_TOS_SHIFT (1U) | ||
| 4008 | /*! TOS - Timeout select. | ||
| 4009 | */ | ||
| 4010 | #define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) | ||
| 4011 | #define CAN_TOCC_TOP_MASK (0xFFFF0000U) | ||
| 4012 | #define CAN_TOCC_TOP_SHIFT (16U) | ||
| 4013 | /*! TOP - Timeout period. | ||
| 4014 | */ | ||
| 4015 | #define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) | ||
| 4016 | /*! @} */ | ||
| 4017 | |||
| 4018 | /*! @name TOCV - Timeout Counter Value */ | ||
| 4019 | /*! @{ */ | ||
| 4020 | #define CAN_TOCV_TOC_MASK (0xFFFFU) | ||
| 4021 | #define CAN_TOCV_TOC_SHIFT (0U) | ||
| 4022 | /*! TOC - Timeout counter. | ||
| 4023 | */ | ||
| 4024 | #define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) | ||
| 4025 | /*! @} */ | ||
| 4026 | |||
| 4027 | /*! @name ECR - Error Counter Register */ | ||
| 4028 | /*! @{ */ | ||
| 4029 | #define CAN_ECR_TEC_MASK (0xFFU) | ||
| 4030 | #define CAN_ECR_TEC_SHIFT (0U) | ||
| 4031 | /*! TEC - Transmit error counter. | ||
| 4032 | */ | ||
| 4033 | #define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) | ||
| 4034 | #define CAN_ECR_REC_MASK (0x7F00U) | ||
| 4035 | #define CAN_ECR_REC_SHIFT (8U) | ||
| 4036 | /*! REC - Receive error counter. | ||
| 4037 | */ | ||
| 4038 | #define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) | ||
| 4039 | #define CAN_ECR_RP_MASK (0x8000U) | ||
| 4040 | #define CAN_ECR_RP_SHIFT (15U) | ||
| 4041 | /*! RP - Receive error passive. | ||
| 4042 | */ | ||
| 4043 | #define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) | ||
| 4044 | #define CAN_ECR_CEL_MASK (0xFF0000U) | ||
| 4045 | #define CAN_ECR_CEL_SHIFT (16U) | ||
| 4046 | /*! CEL - CAN error logging. | ||
| 4047 | */ | ||
| 4048 | #define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) | ||
| 4049 | /*! @} */ | ||
| 4050 | |||
| 4051 | /*! @name PSR - Protocol Status Register */ | ||
| 4052 | /*! @{ */ | ||
| 4053 | #define CAN_PSR_LEC_MASK (0x7U) | ||
| 4054 | #define CAN_PSR_LEC_SHIFT (0U) | ||
| 4055 | /*! LEC - Last error code. | ||
| 4056 | */ | ||
| 4057 | #define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) | ||
| 4058 | #define CAN_PSR_ACT_MASK (0x18U) | ||
| 4059 | #define CAN_PSR_ACT_SHIFT (3U) | ||
| 4060 | /*! ACT - Activity. | ||
| 4061 | */ | ||
| 4062 | #define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) | ||
| 4063 | #define CAN_PSR_EP_MASK (0x20U) | ||
| 4064 | #define CAN_PSR_EP_SHIFT (5U) | ||
| 4065 | /*! EP - Error Passive. | ||
| 4066 | */ | ||
| 4067 | #define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) | ||
| 4068 | #define CAN_PSR_EW_MASK (0x40U) | ||
| 4069 | #define CAN_PSR_EW_SHIFT (6U) | ||
| 4070 | /*! EW - Warning status. | ||
| 4071 | */ | ||
| 4072 | #define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) | ||
| 4073 | #define CAN_PSR_BO_MASK (0x80U) | ||
| 4074 | #define CAN_PSR_BO_SHIFT (7U) | ||
| 4075 | /*! BO - Bus Off Status. | ||
| 4076 | */ | ||
| 4077 | #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) | ||
| 4078 | #define CAN_PSR_DLEC_MASK (0x700U) | ||
| 4079 | #define CAN_PSR_DLEC_SHIFT (8U) | ||
| 4080 | /*! DLEC - Data phase last error code. | ||
| 4081 | */ | ||
| 4082 | #define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) | ||
| 4083 | #define CAN_PSR_RESI_MASK (0x800U) | ||
| 4084 | #define CAN_PSR_RESI_SHIFT (11U) | ||
| 4085 | /*! RESI - ESI flag of the last received CAN FD message. | ||
| 4086 | */ | ||
| 4087 | #define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) | ||
| 4088 | #define CAN_PSR_RBRS_MASK (0x1000U) | ||
| 4089 | #define CAN_PSR_RBRS_SHIFT (12U) | ||
| 4090 | /*! RBRS - BRS flag of last received CAN FD message. | ||
| 4091 | */ | ||
| 4092 | #define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) | ||
| 4093 | #define CAN_PSR_RFDF_MASK (0x2000U) | ||
| 4094 | #define CAN_PSR_RFDF_SHIFT (13U) | ||
| 4095 | /*! RFDF - Received a CAN FD message. | ||
| 4096 | */ | ||
| 4097 | #define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) | ||
| 4098 | #define CAN_PSR_PXE_MASK (0x4000U) | ||
| 4099 | #define CAN_PSR_PXE_SHIFT (14U) | ||
| 4100 | /*! PXE - Protocol exception event. | ||
| 4101 | */ | ||
| 4102 | #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) | ||
| 4103 | #define CAN_PSR_TDCV_MASK (0x7F0000U) | ||
| 4104 | #define CAN_PSR_TDCV_SHIFT (16U) | ||
| 4105 | /*! TDCV - Transmitter delay compensation value. | ||
| 4106 | */ | ||
| 4107 | #define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) | ||
| 4108 | /*! @} */ | ||
| 4109 | |||
| 4110 | /*! @name TDCR - Transmitter Delay Compensator Register */ | ||
| 4111 | /*! @{ */ | ||
| 4112 | #define CAN_TDCR_TDCF_MASK (0x7FU) | ||
| 4113 | #define CAN_TDCR_TDCF_SHIFT (0U) | ||
| 4114 | /*! TDCF - Transmitter delay compensation filter window length. | ||
| 4115 | */ | ||
| 4116 | #define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) | ||
| 4117 | #define CAN_TDCR_TDCO_MASK (0x7F00U) | ||
| 4118 | #define CAN_TDCR_TDCO_SHIFT (8U) | ||
| 4119 | /*! TDCO - Transmitter delay compensation offset. | ||
| 4120 | */ | ||
| 4121 | #define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) | ||
| 4122 | /*! @} */ | ||
| 4123 | |||
| 4124 | /*! @name IR - Interrupt Register */ | ||
| 4125 | /*! @{ */ | ||
| 4126 | #define CAN_IR_RF0N_MASK (0x1U) | ||
| 4127 | #define CAN_IR_RF0N_SHIFT (0U) | ||
| 4128 | /*! RF0N - Rx FIFO 0 new message. | ||
| 4129 | */ | ||
| 4130 | #define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) | ||
| 4131 | #define CAN_IR_RF0W_MASK (0x2U) | ||
| 4132 | #define CAN_IR_RF0W_SHIFT (1U) | ||
| 4133 | /*! RF0W - Rx FIFO 0 watermark reached. | ||
| 4134 | */ | ||
| 4135 | #define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) | ||
| 4136 | #define CAN_IR_RF0F_MASK (0x4U) | ||
| 4137 | #define CAN_IR_RF0F_SHIFT (2U) | ||
| 4138 | /*! RF0F - Rx FIFO 0 full. | ||
| 4139 | */ | ||
| 4140 | #define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) | ||
| 4141 | #define CAN_IR_RF0L_MASK (0x8U) | ||
| 4142 | #define CAN_IR_RF0L_SHIFT (3U) | ||
| 4143 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 4144 | */ | ||
| 4145 | #define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) | ||
| 4146 | #define CAN_IR_RF1N_MASK (0x10U) | ||
| 4147 | #define CAN_IR_RF1N_SHIFT (4U) | ||
| 4148 | /*! RF1N - Rx FIFO 1 new message. | ||
| 4149 | */ | ||
| 4150 | #define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) | ||
| 4151 | #define CAN_IR_RF1W_MASK (0x20U) | ||
| 4152 | #define CAN_IR_RF1W_SHIFT (5U) | ||
| 4153 | /*! RF1W - Rx FIFO 1 watermark reached. | ||
| 4154 | */ | ||
| 4155 | #define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) | ||
| 4156 | #define CAN_IR_RF1F_MASK (0x40U) | ||
| 4157 | #define CAN_IR_RF1F_SHIFT (6U) | ||
| 4158 | /*! RF1F - Rx FIFO 1 full. | ||
| 4159 | */ | ||
| 4160 | #define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) | ||
| 4161 | #define CAN_IR_RF1L_MASK (0x80U) | ||
| 4162 | #define CAN_IR_RF1L_SHIFT (7U) | ||
| 4163 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 4164 | */ | ||
| 4165 | #define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) | ||
| 4166 | #define CAN_IR_HPM_MASK (0x100U) | ||
| 4167 | #define CAN_IR_HPM_SHIFT (8U) | ||
| 4168 | /*! HPM - High priority message. | ||
| 4169 | */ | ||
| 4170 | #define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) | ||
| 4171 | #define CAN_IR_TC_MASK (0x200U) | ||
| 4172 | #define CAN_IR_TC_SHIFT (9U) | ||
| 4173 | /*! TC - Transmission completed. | ||
| 4174 | */ | ||
| 4175 | #define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) | ||
| 4176 | #define CAN_IR_TCF_MASK (0x400U) | ||
| 4177 | #define CAN_IR_TCF_SHIFT (10U) | ||
| 4178 | /*! TCF - Transmission cancellation finished. | ||
| 4179 | */ | ||
| 4180 | #define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) | ||
| 4181 | #define CAN_IR_TFE_MASK (0x800U) | ||
| 4182 | #define CAN_IR_TFE_SHIFT (11U) | ||
| 4183 | /*! TFE - Tx FIFO empty. | ||
| 4184 | */ | ||
| 4185 | #define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) | ||
| 4186 | #define CAN_IR_TEFN_MASK (0x1000U) | ||
| 4187 | #define CAN_IR_TEFN_SHIFT (12U) | ||
| 4188 | /*! TEFN - Tx event FIFO new entry. | ||
| 4189 | */ | ||
| 4190 | #define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) | ||
| 4191 | #define CAN_IR_TEFW_MASK (0x2000U) | ||
| 4192 | #define CAN_IR_TEFW_SHIFT (13U) | ||
| 4193 | /*! TEFW - Tx event FIFO watermark reached. | ||
| 4194 | */ | ||
| 4195 | #define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) | ||
| 4196 | #define CAN_IR_TEFF_MASK (0x4000U) | ||
| 4197 | #define CAN_IR_TEFF_SHIFT (14U) | ||
| 4198 | /*! TEFF - Tx event FIFO full. | ||
| 4199 | */ | ||
| 4200 | #define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) | ||
| 4201 | #define CAN_IR_TEFL_MASK (0x8000U) | ||
| 4202 | #define CAN_IR_TEFL_SHIFT (15U) | ||
| 4203 | /*! TEFL - Tx event FIFO element lost. | ||
| 4204 | */ | ||
| 4205 | #define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) | ||
| 4206 | #define CAN_IR_TSW_MASK (0x10000U) | ||
| 4207 | #define CAN_IR_TSW_SHIFT (16U) | ||
| 4208 | /*! TSW - Timestamp wraparound. | ||
| 4209 | */ | ||
| 4210 | #define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) | ||
| 4211 | #define CAN_IR_MRAF_MASK (0x20000U) | ||
| 4212 | #define CAN_IR_MRAF_SHIFT (17U) | ||
| 4213 | /*! MRAF - Message RAM access failure. | ||
| 4214 | */ | ||
| 4215 | #define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) | ||
| 4216 | #define CAN_IR_TOO_MASK (0x40000U) | ||
| 4217 | #define CAN_IR_TOO_SHIFT (18U) | ||
| 4218 | /*! TOO - Timeout occurred. | ||
| 4219 | */ | ||
| 4220 | #define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) | ||
| 4221 | #define CAN_IR_DRX_MASK (0x80000U) | ||
| 4222 | #define CAN_IR_DRX_SHIFT (19U) | ||
| 4223 | /*! DRX - Message stored in dedicated Rx buffer. | ||
| 4224 | */ | ||
| 4225 | #define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) | ||
| 4226 | #define CAN_IR_BEC_MASK (0x100000U) | ||
| 4227 | #define CAN_IR_BEC_SHIFT (20U) | ||
| 4228 | /*! BEC - Bit error corrected. | ||
| 4229 | */ | ||
| 4230 | #define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) | ||
| 4231 | #define CAN_IR_BEU_MASK (0x200000U) | ||
| 4232 | #define CAN_IR_BEU_SHIFT (21U) | ||
| 4233 | /*! BEU - Bit error uncorrected. | ||
| 4234 | */ | ||
| 4235 | #define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) | ||
| 4236 | #define CAN_IR_ELO_MASK (0x400000U) | ||
| 4237 | #define CAN_IR_ELO_SHIFT (22U) | ||
| 4238 | /*! ELO - Error logging overflow. | ||
| 4239 | */ | ||
| 4240 | #define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) | ||
| 4241 | #define CAN_IR_EP_MASK (0x800000U) | ||
| 4242 | #define CAN_IR_EP_SHIFT (23U) | ||
| 4243 | /*! EP - Error passive. | ||
| 4244 | */ | ||
| 4245 | #define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) | ||
| 4246 | #define CAN_IR_EW_MASK (0x1000000U) | ||
| 4247 | #define CAN_IR_EW_SHIFT (24U) | ||
| 4248 | /*! EW - Warning status. | ||
| 4249 | */ | ||
| 4250 | #define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) | ||
| 4251 | #define CAN_IR_BO_MASK (0x2000000U) | ||
| 4252 | #define CAN_IR_BO_SHIFT (25U) | ||
| 4253 | /*! BO - Bus_Off Status. | ||
| 4254 | */ | ||
| 4255 | #define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) | ||
| 4256 | #define CAN_IR_WDI_MASK (0x4000000U) | ||
| 4257 | #define CAN_IR_WDI_SHIFT (26U) | ||
| 4258 | /*! WDI - Watchdog interrupt. | ||
| 4259 | */ | ||
| 4260 | #define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) | ||
| 4261 | #define CAN_IR_PEA_MASK (0x8000000U) | ||
| 4262 | #define CAN_IR_PEA_SHIFT (27U) | ||
| 4263 | /*! PEA - Protocol error in arbitration phase. | ||
| 4264 | */ | ||
| 4265 | #define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) | ||
| 4266 | #define CAN_IR_PED_MASK (0x10000000U) | ||
| 4267 | #define CAN_IR_PED_SHIFT (28U) | ||
| 4268 | /*! PED - Protocol error in data phase. | ||
| 4269 | */ | ||
| 4270 | #define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) | ||
| 4271 | #define CAN_IR_ARA_MASK (0x20000000U) | ||
| 4272 | #define CAN_IR_ARA_SHIFT (29U) | ||
| 4273 | /*! ARA - Access to reserved address. | ||
| 4274 | */ | ||
| 4275 | #define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) | ||
| 4276 | /*! @} */ | ||
| 4277 | |||
| 4278 | /*! @name IE - Interrupt Enable */ | ||
| 4279 | /*! @{ */ | ||
| 4280 | #define CAN_IE_RF0NE_MASK (0x1U) | ||
| 4281 | #define CAN_IE_RF0NE_SHIFT (0U) | ||
| 4282 | /*! RF0NE - Rx FIFO 0 new message interrupt enable. | ||
| 4283 | */ | ||
| 4284 | #define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) | ||
| 4285 | #define CAN_IE_RF0WE_MASK (0x2U) | ||
| 4286 | #define CAN_IE_RF0WE_SHIFT (1U) | ||
| 4287 | /*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. | ||
| 4288 | */ | ||
| 4289 | #define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) | ||
| 4290 | #define CAN_IE_RF0FE_MASK (0x4U) | ||
| 4291 | #define CAN_IE_RF0FE_SHIFT (2U) | ||
| 4292 | /*! RF0FE - Rx FIFO 0 full interrupt enable. | ||
| 4293 | */ | ||
| 4294 | #define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) | ||
| 4295 | #define CAN_IE_RF0LE_MASK (0x8U) | ||
| 4296 | #define CAN_IE_RF0LE_SHIFT (3U) | ||
| 4297 | /*! RF0LE - Rx FIFO 0 message lost interrupt enable. | ||
| 4298 | */ | ||
| 4299 | #define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) | ||
| 4300 | #define CAN_IE_RF1NE_MASK (0x10U) | ||
| 4301 | #define CAN_IE_RF1NE_SHIFT (4U) | ||
| 4302 | /*! RF1NE - Rx FIFO 1 new message interrupt enable. | ||
| 4303 | */ | ||
| 4304 | #define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) | ||
| 4305 | #define CAN_IE_RF1WE_MASK (0x20U) | ||
| 4306 | #define CAN_IE_RF1WE_SHIFT (5U) | ||
| 4307 | /*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. | ||
| 4308 | */ | ||
| 4309 | #define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) | ||
| 4310 | #define CAN_IE_RF1FE_MASK (0x40U) | ||
| 4311 | #define CAN_IE_RF1FE_SHIFT (6U) | ||
| 4312 | /*! RF1FE - Rx FIFO 1 full interrupt enable. | ||
| 4313 | */ | ||
| 4314 | #define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) | ||
| 4315 | #define CAN_IE_RF1LE_MASK (0x80U) | ||
| 4316 | #define CAN_IE_RF1LE_SHIFT (7U) | ||
| 4317 | /*! RF1LE - Rx FIFO 1 message lost interrupt enable. | ||
| 4318 | */ | ||
| 4319 | #define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) | ||
| 4320 | #define CAN_IE_HPME_MASK (0x100U) | ||
| 4321 | #define CAN_IE_HPME_SHIFT (8U) | ||
| 4322 | /*! HPME - High priority message interrupt enable. | ||
| 4323 | */ | ||
| 4324 | #define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) | ||
| 4325 | #define CAN_IE_TCE_MASK (0x200U) | ||
| 4326 | #define CAN_IE_TCE_SHIFT (9U) | ||
| 4327 | /*! TCE - Transmission completed interrupt enable. | ||
| 4328 | */ | ||
| 4329 | #define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) | ||
| 4330 | #define CAN_IE_TCFE_MASK (0x400U) | ||
| 4331 | #define CAN_IE_TCFE_SHIFT (10U) | ||
| 4332 | /*! TCFE - Transmission cancellation finished interrupt enable. | ||
| 4333 | */ | ||
| 4334 | #define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) | ||
| 4335 | #define CAN_IE_TFEE_MASK (0x800U) | ||
| 4336 | #define CAN_IE_TFEE_SHIFT (11U) | ||
| 4337 | /*! TFEE - Tx FIFO empty interrupt enable. | ||
| 4338 | */ | ||
| 4339 | #define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) | ||
| 4340 | #define CAN_IE_TEFNE_MASK (0x1000U) | ||
| 4341 | #define CAN_IE_TEFNE_SHIFT (12U) | ||
| 4342 | /*! TEFNE - Tx event FIFO new entry interrupt enable. | ||
| 4343 | */ | ||
| 4344 | #define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) | ||
| 4345 | #define CAN_IE_TEFWE_MASK (0x2000U) | ||
| 4346 | #define CAN_IE_TEFWE_SHIFT (13U) | ||
| 4347 | /*! TEFWE - Tx event FIFO watermark reached interrupt enable. | ||
| 4348 | */ | ||
| 4349 | #define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) | ||
| 4350 | #define CAN_IE_TEFFE_MASK (0x4000U) | ||
| 4351 | #define CAN_IE_TEFFE_SHIFT (14U) | ||
| 4352 | /*! TEFFE - Tx event FIFO full interrupt enable. | ||
| 4353 | */ | ||
| 4354 | #define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) | ||
| 4355 | #define CAN_IE_TEFLE_MASK (0x8000U) | ||
| 4356 | #define CAN_IE_TEFLE_SHIFT (15U) | ||
| 4357 | /*! TEFLE - Tx event FIFO element lost interrupt enable. | ||
| 4358 | */ | ||
| 4359 | #define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) | ||
| 4360 | #define CAN_IE_TSWE_MASK (0x10000U) | ||
| 4361 | #define CAN_IE_TSWE_SHIFT (16U) | ||
| 4362 | /*! TSWE - Timestamp wraparound interrupt enable. | ||
| 4363 | */ | ||
| 4364 | #define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) | ||
| 4365 | #define CAN_IE_MRAFE_MASK (0x20000U) | ||
| 4366 | #define CAN_IE_MRAFE_SHIFT (17U) | ||
| 4367 | /*! MRAFE - Message RAM access failure interrupt enable. | ||
| 4368 | */ | ||
| 4369 | #define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) | ||
| 4370 | #define CAN_IE_TOOE_MASK (0x40000U) | ||
| 4371 | #define CAN_IE_TOOE_SHIFT (18U) | ||
| 4372 | /*! TOOE - Timeout occurred interrupt enable. | ||
| 4373 | */ | ||
| 4374 | #define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) | ||
| 4375 | #define CAN_IE_DRXE_MASK (0x80000U) | ||
| 4376 | #define CAN_IE_DRXE_SHIFT (19U) | ||
| 4377 | /*! DRXE - Message stored in dedicated Rx buffer interrupt enable. | ||
| 4378 | */ | ||
| 4379 | #define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) | ||
| 4380 | #define CAN_IE_BECE_MASK (0x100000U) | ||
| 4381 | #define CAN_IE_BECE_SHIFT (20U) | ||
| 4382 | /*! BECE - Bit error corrected interrupt enable. | ||
| 4383 | */ | ||
| 4384 | #define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) | ||
| 4385 | #define CAN_IE_BEUE_MASK (0x200000U) | ||
| 4386 | #define CAN_IE_BEUE_SHIFT (21U) | ||
| 4387 | /*! BEUE - Bit error uncorrected interrupt enable. | ||
| 4388 | */ | ||
| 4389 | #define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) | ||
| 4390 | #define CAN_IE_ELOE_MASK (0x400000U) | ||
| 4391 | #define CAN_IE_ELOE_SHIFT (22U) | ||
| 4392 | /*! ELOE - Error logging overflow interrupt enable. | ||
| 4393 | */ | ||
| 4394 | #define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) | ||
| 4395 | #define CAN_IE_EPE_MASK (0x800000U) | ||
| 4396 | #define CAN_IE_EPE_SHIFT (23U) | ||
| 4397 | /*! EPE - Error passive interrupt enable. | ||
| 4398 | */ | ||
| 4399 | #define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) | ||
| 4400 | #define CAN_IE_EWE_MASK (0x1000000U) | ||
| 4401 | #define CAN_IE_EWE_SHIFT (24U) | ||
| 4402 | /*! EWE - Warning status interrupt enable. | ||
| 4403 | */ | ||
| 4404 | #define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) | ||
| 4405 | #define CAN_IE_BOE_MASK (0x2000000U) | ||
| 4406 | #define CAN_IE_BOE_SHIFT (25U) | ||
| 4407 | /*! BOE - Bus_Off Status interrupt enable. | ||
| 4408 | */ | ||
| 4409 | #define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) | ||
| 4410 | #define CAN_IE_WDIE_MASK (0x4000000U) | ||
| 4411 | #define CAN_IE_WDIE_SHIFT (26U) | ||
| 4412 | /*! WDIE - Watchdog interrupt enable. | ||
| 4413 | */ | ||
| 4414 | #define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) | ||
| 4415 | #define CAN_IE_PEAE_MASK (0x8000000U) | ||
| 4416 | #define CAN_IE_PEAE_SHIFT (27U) | ||
| 4417 | /*! PEAE - Protocol error in arbitration phase interrupt enable. | ||
| 4418 | */ | ||
| 4419 | #define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) | ||
| 4420 | #define CAN_IE_PEDE_MASK (0x10000000U) | ||
| 4421 | #define CAN_IE_PEDE_SHIFT (28U) | ||
| 4422 | /*! PEDE - Protocol error in data phase interrupt enable. | ||
| 4423 | */ | ||
| 4424 | #define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) | ||
| 4425 | #define CAN_IE_ARAE_MASK (0x20000000U) | ||
| 4426 | #define CAN_IE_ARAE_SHIFT (29U) | ||
| 4427 | /*! ARAE - Access to reserved address interrupt enable. | ||
| 4428 | */ | ||
| 4429 | #define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) | ||
| 4430 | /*! @} */ | ||
| 4431 | |||
| 4432 | /*! @name ILS - Interrupt Line Select */ | ||
| 4433 | /*! @{ */ | ||
| 4434 | #define CAN_ILS_RF0NL_MASK (0x1U) | ||
| 4435 | #define CAN_ILS_RF0NL_SHIFT (0U) | ||
| 4436 | /*! RF0NL - Rx FIFO 0 new message interrupt line. | ||
| 4437 | */ | ||
| 4438 | #define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) | ||
| 4439 | #define CAN_ILS_RF0WL_MASK (0x2U) | ||
| 4440 | #define CAN_ILS_RF0WL_SHIFT (1U) | ||
| 4441 | /*! RF0WL - Rx FIFO 0 watermark reached interrupt line. | ||
| 4442 | */ | ||
| 4443 | #define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) | ||
| 4444 | #define CAN_ILS_RF0FL_MASK (0x4U) | ||
| 4445 | #define CAN_ILS_RF0FL_SHIFT (2U) | ||
| 4446 | /*! RF0FL - Rx FIFO 0 full interrupt line. | ||
| 4447 | */ | ||
| 4448 | #define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) | ||
| 4449 | #define CAN_ILS_RF0LL_MASK (0x8U) | ||
| 4450 | #define CAN_ILS_RF0LL_SHIFT (3U) | ||
| 4451 | /*! RF0LL - Rx FIFO 0 message lost interrupt line. | ||
| 4452 | */ | ||
| 4453 | #define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) | ||
| 4454 | #define CAN_ILS_RF1NL_MASK (0x10U) | ||
| 4455 | #define CAN_ILS_RF1NL_SHIFT (4U) | ||
| 4456 | /*! RF1NL - Rx FIFO 1 new message interrupt line. | ||
| 4457 | */ | ||
| 4458 | #define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) | ||
| 4459 | #define CAN_ILS_RF1WL_MASK (0x20U) | ||
| 4460 | #define CAN_ILS_RF1WL_SHIFT (5U) | ||
| 4461 | /*! RF1WL - Rx FIFO 1 watermark reached interrupt line. | ||
| 4462 | */ | ||
| 4463 | #define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) | ||
| 4464 | #define CAN_ILS_RF1FL_MASK (0x40U) | ||
| 4465 | #define CAN_ILS_RF1FL_SHIFT (6U) | ||
| 4466 | /*! RF1FL - Rx FIFO 1 full interrupt line. | ||
| 4467 | */ | ||
| 4468 | #define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) | ||
| 4469 | #define CAN_ILS_RF1LL_MASK (0x80U) | ||
| 4470 | #define CAN_ILS_RF1LL_SHIFT (7U) | ||
| 4471 | /*! RF1LL - Rx FIFO 1 message lost interrupt line. | ||
| 4472 | */ | ||
| 4473 | #define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) | ||
| 4474 | #define CAN_ILS_HPML_MASK (0x100U) | ||
| 4475 | #define CAN_ILS_HPML_SHIFT (8U) | ||
| 4476 | /*! HPML - High priority message interrupt line. | ||
| 4477 | */ | ||
| 4478 | #define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) | ||
| 4479 | #define CAN_ILS_TCL_MASK (0x200U) | ||
| 4480 | #define CAN_ILS_TCL_SHIFT (9U) | ||
| 4481 | /*! TCL - Transmission completed interrupt line. | ||
| 4482 | */ | ||
| 4483 | #define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) | ||
| 4484 | #define CAN_ILS_TCFL_MASK (0x400U) | ||
| 4485 | #define CAN_ILS_TCFL_SHIFT (10U) | ||
| 4486 | /*! TCFL - Transmission cancellation finished interrupt line. | ||
| 4487 | */ | ||
| 4488 | #define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) | ||
| 4489 | #define CAN_ILS_TFEL_MASK (0x800U) | ||
| 4490 | #define CAN_ILS_TFEL_SHIFT (11U) | ||
| 4491 | /*! TFEL - Tx FIFO empty interrupt line. | ||
| 4492 | */ | ||
| 4493 | #define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) | ||
| 4494 | #define CAN_ILS_TEFNL_MASK (0x1000U) | ||
| 4495 | #define CAN_ILS_TEFNL_SHIFT (12U) | ||
| 4496 | /*! TEFNL - Tx event FIFO new entry interrupt line. | ||
| 4497 | */ | ||
| 4498 | #define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) | ||
| 4499 | #define CAN_ILS_TEFWL_MASK (0x2000U) | ||
| 4500 | #define CAN_ILS_TEFWL_SHIFT (13U) | ||
| 4501 | /*! TEFWL - Tx event FIFO watermark reached interrupt line. | ||
| 4502 | */ | ||
| 4503 | #define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) | ||
| 4504 | #define CAN_ILS_TEFFL_MASK (0x4000U) | ||
| 4505 | #define CAN_ILS_TEFFL_SHIFT (14U) | ||
| 4506 | /*! TEFFL - Tx event FIFO full interrupt line. | ||
| 4507 | */ | ||
| 4508 | #define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) | ||
| 4509 | #define CAN_ILS_TEFLL_MASK (0x8000U) | ||
| 4510 | #define CAN_ILS_TEFLL_SHIFT (15U) | ||
| 4511 | /*! TEFLL - Tx event FIFO element lost interrupt line. | ||
| 4512 | */ | ||
| 4513 | #define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) | ||
| 4514 | #define CAN_ILS_TSWL_MASK (0x10000U) | ||
| 4515 | #define CAN_ILS_TSWL_SHIFT (16U) | ||
| 4516 | /*! TSWL - Timestamp wraparound interrupt line. | ||
| 4517 | */ | ||
| 4518 | #define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) | ||
| 4519 | #define CAN_ILS_MRAFL_MASK (0x20000U) | ||
| 4520 | #define CAN_ILS_MRAFL_SHIFT (17U) | ||
| 4521 | /*! MRAFL - Message RAM access failure interrupt line. | ||
| 4522 | */ | ||
| 4523 | #define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) | ||
| 4524 | #define CAN_ILS_TOOL_MASK (0x40000U) | ||
| 4525 | #define CAN_ILS_TOOL_SHIFT (18U) | ||
| 4526 | /*! TOOL - Timeout occurred interrupt line. | ||
| 4527 | */ | ||
| 4528 | #define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) | ||
| 4529 | #define CAN_ILS_DRXL_MASK (0x80000U) | ||
| 4530 | #define CAN_ILS_DRXL_SHIFT (19U) | ||
| 4531 | /*! DRXL - Message stored in dedicated Rx buffer interrupt line. | ||
| 4532 | */ | ||
| 4533 | #define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) | ||
| 4534 | #define CAN_ILS_BECL_MASK (0x100000U) | ||
| 4535 | #define CAN_ILS_BECL_SHIFT (20U) | ||
| 4536 | /*! BECL - Bit error corrected interrupt line. | ||
| 4537 | */ | ||
| 4538 | #define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) | ||
| 4539 | #define CAN_ILS_BEUL_MASK (0x200000U) | ||
| 4540 | #define CAN_ILS_BEUL_SHIFT (21U) | ||
| 4541 | /*! BEUL - Bit error uncorrected interrupt line. | ||
| 4542 | */ | ||
| 4543 | #define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) | ||
| 4544 | #define CAN_ILS_ELOL_MASK (0x400000U) | ||
| 4545 | #define CAN_ILS_ELOL_SHIFT (22U) | ||
| 4546 | /*! ELOL - Error logging overflow interrupt line. | ||
| 4547 | */ | ||
| 4548 | #define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) | ||
| 4549 | #define CAN_ILS_EPL_MASK (0x800000U) | ||
| 4550 | #define CAN_ILS_EPL_SHIFT (23U) | ||
| 4551 | /*! EPL - Error passive interrupt line. | ||
| 4552 | */ | ||
| 4553 | #define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) | ||
| 4554 | #define CAN_ILS_EWL_MASK (0x1000000U) | ||
| 4555 | #define CAN_ILS_EWL_SHIFT (24U) | ||
| 4556 | /*! EWL - Warning status interrupt line. | ||
| 4557 | */ | ||
| 4558 | #define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) | ||
| 4559 | #define CAN_ILS_BOL_MASK (0x2000000U) | ||
| 4560 | #define CAN_ILS_BOL_SHIFT (25U) | ||
| 4561 | /*! BOL - Bus_Off Status interrupt line. | ||
| 4562 | */ | ||
| 4563 | #define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) | ||
| 4564 | #define CAN_ILS_WDIL_MASK (0x4000000U) | ||
| 4565 | #define CAN_ILS_WDIL_SHIFT (26U) | ||
| 4566 | /*! WDIL - Watchdog interrupt line. | ||
| 4567 | */ | ||
| 4568 | #define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) | ||
| 4569 | #define CAN_ILS_PEAL_MASK (0x8000000U) | ||
| 4570 | #define CAN_ILS_PEAL_SHIFT (27U) | ||
| 4571 | /*! PEAL - Protocol error in arbitration phase interrupt line. | ||
| 4572 | */ | ||
| 4573 | #define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) | ||
| 4574 | #define CAN_ILS_PEDL_MASK (0x10000000U) | ||
| 4575 | #define CAN_ILS_PEDL_SHIFT (28U) | ||
| 4576 | /*! PEDL - Protocol error in data phase interrupt line. | ||
| 4577 | */ | ||
| 4578 | #define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) | ||
| 4579 | #define CAN_ILS_ARAL_MASK (0x20000000U) | ||
| 4580 | #define CAN_ILS_ARAL_SHIFT (29U) | ||
| 4581 | /*! ARAL - Access to reserved address interrupt line. | ||
| 4582 | */ | ||
| 4583 | #define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) | ||
| 4584 | /*! @} */ | ||
| 4585 | |||
| 4586 | /*! @name ILE - Interrupt Line Enable */ | ||
| 4587 | /*! @{ */ | ||
| 4588 | #define CAN_ILE_EINT0_MASK (0x1U) | ||
| 4589 | #define CAN_ILE_EINT0_SHIFT (0U) | ||
| 4590 | /*! EINT0 - Enable interrupt line 0. | ||
| 4591 | */ | ||
| 4592 | #define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) | ||
| 4593 | #define CAN_ILE_EINT1_MASK (0x2U) | ||
| 4594 | #define CAN_ILE_EINT1_SHIFT (1U) | ||
| 4595 | /*! EINT1 - Enable interrupt line 1. | ||
| 4596 | */ | ||
| 4597 | #define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) | ||
| 4598 | /*! @} */ | ||
| 4599 | |||
| 4600 | /*! @name GFC - Global Filter Configuration */ | ||
| 4601 | /*! @{ */ | ||
| 4602 | #define CAN_GFC_RRFE_MASK (0x1U) | ||
| 4603 | #define CAN_GFC_RRFE_SHIFT (0U) | ||
| 4604 | /*! RRFE - Reject remote frames extended. | ||
| 4605 | */ | ||
| 4606 | #define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) | ||
| 4607 | #define CAN_GFC_RRFS_MASK (0x2U) | ||
| 4608 | #define CAN_GFC_RRFS_SHIFT (1U) | ||
| 4609 | /*! RRFS - Reject remote frames standard. | ||
| 4610 | */ | ||
| 4611 | #define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) | ||
| 4612 | #define CAN_GFC_ANFE_MASK (0xCU) | ||
| 4613 | #define CAN_GFC_ANFE_SHIFT (2U) | ||
| 4614 | /*! ANFE - Accept non-matching frames extended. | ||
| 4615 | */ | ||
| 4616 | #define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) | ||
| 4617 | #define CAN_GFC_ANFS_MASK (0x30U) | ||
| 4618 | #define CAN_GFC_ANFS_SHIFT (4U) | ||
| 4619 | /*! ANFS - Accept non-matching frames standard. | ||
| 4620 | */ | ||
| 4621 | #define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) | ||
| 4622 | /*! @} */ | ||
| 4623 | |||
| 4624 | /*! @name SIDFC - Standard ID Filter Configuration */ | ||
| 4625 | /*! @{ */ | ||
| 4626 | #define CAN_SIDFC_FLSSA_MASK (0xFFFCU) | ||
| 4627 | #define CAN_SIDFC_FLSSA_SHIFT (2U) | ||
| 4628 | /*! FLSSA - Filter list standard start address. | ||
| 4629 | */ | ||
| 4630 | #define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) | ||
| 4631 | #define CAN_SIDFC_LSS_MASK (0xFF0000U) | ||
| 4632 | #define CAN_SIDFC_LSS_SHIFT (16U) | ||
| 4633 | /*! LSS - List size standard 0 = No standard message ID filter. | ||
| 4634 | */ | ||
| 4635 | #define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) | ||
| 4636 | /*! @} */ | ||
| 4637 | |||
| 4638 | /*! @name XIDFC - Extended ID Filter Configuration */ | ||
| 4639 | /*! @{ */ | ||
| 4640 | #define CAN_XIDFC_FLESA_MASK (0xFFFCU) | ||
| 4641 | #define CAN_XIDFC_FLESA_SHIFT (2U) | ||
| 4642 | /*! FLESA - Filter list extended start address. | ||
| 4643 | */ | ||
| 4644 | #define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) | ||
| 4645 | #define CAN_XIDFC_LSE_MASK (0xFF0000U) | ||
| 4646 | #define CAN_XIDFC_LSE_SHIFT (16U) | ||
| 4647 | /*! LSE - List size extended 0 = No extended message ID filter. | ||
| 4648 | */ | ||
| 4649 | #define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) | ||
| 4650 | /*! @} */ | ||
| 4651 | |||
| 4652 | /*! @name XIDAM - Extended ID AND Mask */ | ||
| 4653 | /*! @{ */ | ||
| 4654 | #define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) | ||
| 4655 | #define CAN_XIDAM_EIDM_SHIFT (0U) | ||
| 4656 | /*! EIDM - Extended ID mask. | ||
| 4657 | */ | ||
| 4658 | #define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) | ||
| 4659 | /*! @} */ | ||
| 4660 | |||
| 4661 | /*! @name HPMS - High Priority Message Status */ | ||
| 4662 | /*! @{ */ | ||
| 4663 | #define CAN_HPMS_BIDX_MASK (0x3FU) | ||
| 4664 | #define CAN_HPMS_BIDX_SHIFT (0U) | ||
| 4665 | /*! BIDX - Buffer index. | ||
| 4666 | */ | ||
| 4667 | #define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) | ||
| 4668 | #define CAN_HPMS_MSI_MASK (0xC0U) | ||
| 4669 | #define CAN_HPMS_MSI_SHIFT (6U) | ||
| 4670 | /*! MSI - Message storage indicator. | ||
| 4671 | */ | ||
| 4672 | #define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) | ||
| 4673 | #define CAN_HPMS_FIDX_MASK (0x7F00U) | ||
| 4674 | #define CAN_HPMS_FIDX_SHIFT (8U) | ||
| 4675 | /*! FIDX - Filter index. | ||
| 4676 | */ | ||
| 4677 | #define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) | ||
| 4678 | #define CAN_HPMS_FLST_MASK (0x8000U) | ||
| 4679 | #define CAN_HPMS_FLST_SHIFT (15U) | ||
| 4680 | /*! FLST - Filter list. | ||
| 4681 | */ | ||
| 4682 | #define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) | ||
| 4683 | /*! @} */ | ||
| 4684 | |||
| 4685 | /*! @name NDAT1 - New Data 1 */ | ||
| 4686 | /*! @{ */ | ||
| 4687 | #define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) | ||
| 4688 | #define CAN_NDAT1_ND_SHIFT (0U) | ||
| 4689 | /*! ND - New Data. | ||
| 4690 | */ | ||
| 4691 | #define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) | ||
| 4692 | /*! @} */ | ||
| 4693 | |||
| 4694 | /*! @name NDAT2 - New Data 2 */ | ||
| 4695 | /*! @{ */ | ||
| 4696 | #define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) | ||
| 4697 | #define CAN_NDAT2_ND_SHIFT (0U) | ||
| 4698 | /*! ND - New Data. | ||
| 4699 | */ | ||
| 4700 | #define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) | ||
| 4701 | /*! @} */ | ||
| 4702 | |||
| 4703 | /*! @name RXF0C - Rx FIFO 0 Configuration */ | ||
| 4704 | /*! @{ */ | ||
| 4705 | #define CAN_RXF0C_F0SA_MASK (0xFFFCU) | ||
| 4706 | #define CAN_RXF0C_F0SA_SHIFT (2U) | ||
| 4707 | /*! F0SA - Rx FIFO 0 start address. | ||
| 4708 | */ | ||
| 4709 | #define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) | ||
| 4710 | #define CAN_RXF0C_F0S_MASK (0x7F0000U) | ||
| 4711 | #define CAN_RXF0C_F0S_SHIFT (16U) | ||
| 4712 | /*! F0S - Rx FIFO 0 size. | ||
| 4713 | */ | ||
| 4714 | #define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) | ||
| 4715 | #define CAN_RXF0C_F0WM_MASK (0x7F000000U) | ||
| 4716 | #define CAN_RXF0C_F0WM_SHIFT (24U) | ||
| 4717 | /*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. | ||
| 4718 | */ | ||
| 4719 | #define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) | ||
| 4720 | #define CAN_RXF0C_F0OM_MASK (0x80000000U) | ||
| 4721 | #define CAN_RXF0C_F0OM_SHIFT (31U) | ||
| 4722 | /*! F0OM - FIFO 0 operation mode. | ||
| 4723 | */ | ||
| 4724 | #define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) | ||
| 4725 | /*! @} */ | ||
| 4726 | |||
| 4727 | /*! @name RXF0S - Rx FIFO 0 Status */ | ||
| 4728 | /*! @{ */ | ||
| 4729 | #define CAN_RXF0S_F0FL_MASK (0x7FU) | ||
| 4730 | #define CAN_RXF0S_F0FL_SHIFT (0U) | ||
| 4731 | /*! F0FL - Rx FIFO 0 fill level. | ||
| 4732 | */ | ||
| 4733 | #define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) | ||
| 4734 | #define CAN_RXF0S_F0GI_MASK (0x3F00U) | ||
| 4735 | #define CAN_RXF0S_F0GI_SHIFT (8U) | ||
| 4736 | /*! F0GI - Rx FIFO 0 get index. | ||
| 4737 | */ | ||
| 4738 | #define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) | ||
| 4739 | #define CAN_RXF0S_F0PI_MASK (0x3F0000U) | ||
| 4740 | #define CAN_RXF0S_F0PI_SHIFT (16U) | ||
| 4741 | /*! F0PI - Rx FIFO 0 put index. | ||
| 4742 | */ | ||
| 4743 | #define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) | ||
| 4744 | #define CAN_RXF0S_F0F_MASK (0x1000000U) | ||
| 4745 | #define CAN_RXF0S_F0F_SHIFT (24U) | ||
| 4746 | /*! F0F - Rx FIFO 0 full. | ||
| 4747 | */ | ||
| 4748 | #define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) | ||
| 4749 | #define CAN_RXF0S_RF0L_MASK (0x2000000U) | ||
| 4750 | #define CAN_RXF0S_RF0L_SHIFT (25U) | ||
| 4751 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 4752 | */ | ||
| 4753 | #define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) | ||
| 4754 | /*! @} */ | ||
| 4755 | |||
| 4756 | /*! @name RXF0A - Rx FIFO 0 Acknowledge */ | ||
| 4757 | /*! @{ */ | ||
| 4758 | #define CAN_RXF0A_F0AI_MASK (0x3FU) | ||
| 4759 | #define CAN_RXF0A_F0AI_SHIFT (0U) | ||
| 4760 | /*! F0AI - Rx FIFO 0 acknowledge index. | ||
| 4761 | */ | ||
| 4762 | #define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) | ||
| 4763 | /*! @} */ | ||
| 4764 | |||
| 4765 | /*! @name RXBC - Rx Buffer Configuration */ | ||
| 4766 | /*! @{ */ | ||
| 4767 | #define CAN_RXBC_RBSA_MASK (0xFFFCU) | ||
| 4768 | #define CAN_RXBC_RBSA_SHIFT (2U) | ||
| 4769 | /*! RBSA - Rx buffer start address. | ||
| 4770 | */ | ||
| 4771 | #define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) | ||
| 4772 | /*! @} */ | ||
| 4773 | |||
| 4774 | /*! @name RXF1C - Rx FIFO 1 Configuration */ | ||
| 4775 | /*! @{ */ | ||
| 4776 | #define CAN_RXF1C_F1SA_MASK (0xFFFCU) | ||
| 4777 | #define CAN_RXF1C_F1SA_SHIFT (2U) | ||
| 4778 | /*! F1SA - Rx FIFO 1 start address. | ||
| 4779 | */ | ||
| 4780 | #define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) | ||
| 4781 | #define CAN_RXF1C_F1S_MASK (0x7F0000U) | ||
| 4782 | #define CAN_RXF1C_F1S_SHIFT (16U) | ||
| 4783 | /*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. | ||
| 4784 | */ | ||
| 4785 | #define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) | ||
| 4786 | #define CAN_RXF1C_F1WM_MASK (0x7F000000U) | ||
| 4787 | #define CAN_RXF1C_F1WM_SHIFT (24U) | ||
| 4788 | /*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. | ||
| 4789 | */ | ||
| 4790 | #define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) | ||
| 4791 | #define CAN_RXF1C_F1OM_MASK (0x80000000U) | ||
| 4792 | #define CAN_RXF1C_F1OM_SHIFT (31U) | ||
| 4793 | /*! F1OM - FIFO 1 operation mode. | ||
| 4794 | */ | ||
| 4795 | #define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) | ||
| 4796 | /*! @} */ | ||
| 4797 | |||
| 4798 | /*! @name RXF1S - Rx FIFO 1 Status */ | ||
| 4799 | /*! @{ */ | ||
| 4800 | #define CAN_RXF1S_F1FL_MASK (0x7FU) | ||
| 4801 | #define CAN_RXF1S_F1FL_SHIFT (0U) | ||
| 4802 | /*! F1FL - Rx FIFO 1 fill level. | ||
| 4803 | */ | ||
| 4804 | #define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) | ||
| 4805 | #define CAN_RXF1S_F1GI_MASK (0x3F00U) | ||
| 4806 | #define CAN_RXF1S_F1GI_SHIFT (8U) | ||
| 4807 | /*! F1GI - Rx FIFO 1 get index. | ||
| 4808 | */ | ||
| 4809 | #define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) | ||
| 4810 | #define CAN_RXF1S_F1PI_MASK (0x3F0000U) | ||
| 4811 | #define CAN_RXF1S_F1PI_SHIFT (16U) | ||
| 4812 | /*! F1PI - Rx FIFO 1 put index. | ||
| 4813 | */ | ||
| 4814 | #define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) | ||
| 4815 | #define CAN_RXF1S_F1F_MASK (0x1000000U) | ||
| 4816 | #define CAN_RXF1S_F1F_SHIFT (24U) | ||
| 4817 | /*! F1F - Rx FIFO 1 full. | ||
| 4818 | */ | ||
| 4819 | #define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) | ||
| 4820 | #define CAN_RXF1S_RF1L_MASK (0x2000000U) | ||
| 4821 | #define CAN_RXF1S_RF1L_SHIFT (25U) | ||
| 4822 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 4823 | */ | ||
| 4824 | #define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) | ||
| 4825 | /*! @} */ | ||
| 4826 | |||
| 4827 | /*! @name RXF1A - Rx FIFO 1 Acknowledge */ | ||
| 4828 | /*! @{ */ | ||
| 4829 | #define CAN_RXF1A_F1AI_MASK (0x3FU) | ||
| 4830 | #define CAN_RXF1A_F1AI_SHIFT (0U) | ||
| 4831 | /*! F1AI - Rx FIFO 1 acknowledge index. | ||
| 4832 | */ | ||
| 4833 | #define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) | ||
| 4834 | /*! @} */ | ||
| 4835 | |||
| 4836 | /*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ | ||
| 4837 | /*! @{ */ | ||
| 4838 | #define CAN_RXESC_F0DS_MASK (0x7U) | ||
| 4839 | #define CAN_RXESC_F0DS_SHIFT (0U) | ||
| 4840 | /*! F0DS - Rx FIFO 0 data field size. | ||
| 4841 | */ | ||
| 4842 | #define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) | ||
| 4843 | #define CAN_RXESC_F1DS_MASK (0x70U) | ||
| 4844 | #define CAN_RXESC_F1DS_SHIFT (4U) | ||
| 4845 | /*! F1DS - Rx FIFO 1 data field size. | ||
| 4846 | */ | ||
| 4847 | #define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) | ||
| 4848 | #define CAN_RXESC_RBDS_MASK (0x700U) | ||
| 4849 | #define CAN_RXESC_RBDS_SHIFT (8U) | ||
| 4850 | /*! RBDS - . | ||
| 4851 | */ | ||
| 4852 | #define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) | ||
| 4853 | /*! @} */ | ||
| 4854 | |||
| 4855 | /*! @name TXBC - Tx Buffer Configuration */ | ||
| 4856 | /*! @{ */ | ||
| 4857 | #define CAN_TXBC_TBSA_MASK (0xFFFCU) | ||
| 4858 | #define CAN_TXBC_TBSA_SHIFT (2U) | ||
| 4859 | /*! TBSA - Tx buffers start address. | ||
| 4860 | */ | ||
| 4861 | #define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) | ||
| 4862 | #define CAN_TXBC_NDTB_MASK (0x3F0000U) | ||
| 4863 | #define CAN_TXBC_NDTB_SHIFT (16U) | ||
| 4864 | /*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. | ||
| 4865 | */ | ||
| 4866 | #define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) | ||
| 4867 | #define CAN_TXBC_TFQS_MASK (0x3F000000U) | ||
| 4868 | #define CAN_TXBC_TFQS_SHIFT (24U) | ||
| 4869 | /*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. | ||
| 4870 | */ | ||
| 4871 | #define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) | ||
| 4872 | #define CAN_TXBC_TFQM_MASK (0x40000000U) | ||
| 4873 | #define CAN_TXBC_TFQM_SHIFT (30U) | ||
| 4874 | /*! TFQM - Tx FIFO/queue mode. | ||
| 4875 | */ | ||
| 4876 | #define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) | ||
| 4877 | /*! @} */ | ||
| 4878 | |||
| 4879 | /*! @name TXFQS - Tx FIFO/Queue Status */ | ||
| 4880 | /*! @{ */ | ||
| 4881 | #define CAN_TXFQS_TFGI_MASK (0x1F00U) | ||
| 4882 | #define CAN_TXFQS_TFGI_SHIFT (8U) | ||
| 4883 | /*! TFGI - Tx FIFO get index. | ||
| 4884 | */ | ||
| 4885 | #define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) | ||
| 4886 | #define CAN_TXFQS_TFQPI_MASK (0x1F0000U) | ||
| 4887 | #define CAN_TXFQS_TFQPI_SHIFT (16U) | ||
| 4888 | /*! TFQPI - Tx FIFO/queue put index. | ||
| 4889 | */ | ||
| 4890 | #define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) | ||
| 4891 | #define CAN_TXFQS_TFQF_MASK (0x200000U) | ||
| 4892 | #define CAN_TXFQS_TFQF_SHIFT (21U) | ||
| 4893 | /*! TFQF - Tx FIFO/queue full. | ||
| 4894 | */ | ||
| 4895 | #define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) | ||
| 4896 | /*! @} */ | ||
| 4897 | |||
| 4898 | /*! @name TXESC - Tx Buffer Element Size Configuration */ | ||
| 4899 | /*! @{ */ | ||
| 4900 | #define CAN_TXESC_TBDS_MASK (0x7U) | ||
| 4901 | #define CAN_TXESC_TBDS_SHIFT (0U) | ||
| 4902 | /*! TBDS - Tx buffer data field size. | ||
| 4903 | */ | ||
| 4904 | #define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) | ||
| 4905 | /*! @} */ | ||
| 4906 | |||
| 4907 | /*! @name TXBRP - Tx Buffer Request Pending */ | ||
| 4908 | /*! @{ */ | ||
| 4909 | #define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) | ||
| 4910 | #define CAN_TXBRP_TRP_SHIFT (0U) | ||
| 4911 | /*! TRP - Transmission request pending. | ||
| 4912 | */ | ||
| 4913 | #define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) | ||
| 4914 | /*! @} */ | ||
| 4915 | |||
| 4916 | /*! @name TXBAR - Tx Buffer Add Request */ | ||
| 4917 | /*! @{ */ | ||
| 4918 | #define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) | ||
| 4919 | #define CAN_TXBAR_AR_SHIFT (0U) | ||
| 4920 | /*! AR - Add request. | ||
| 4921 | */ | ||
| 4922 | #define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) | ||
| 4923 | /*! @} */ | ||
| 4924 | |||
| 4925 | /*! @name TXBCR - Tx Buffer Cancellation Request */ | ||
| 4926 | /*! @{ */ | ||
| 4927 | #define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) | ||
| 4928 | #define CAN_TXBCR_CR_SHIFT (0U) | ||
| 4929 | /*! CR - Cancellation request. | ||
| 4930 | */ | ||
| 4931 | #define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) | ||
| 4932 | /*! @} */ | ||
| 4933 | |||
| 4934 | /*! @name TXBTO - Tx Buffer Transmission Occurred */ | ||
| 4935 | /*! @{ */ | ||
| 4936 | #define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) | ||
| 4937 | #define CAN_TXBTO_TO_SHIFT (0U) | ||
| 4938 | /*! TO - Transmission occurred. | ||
| 4939 | */ | ||
| 4940 | #define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) | ||
| 4941 | /*! @} */ | ||
| 4942 | |||
| 4943 | /*! @name TXBCF - Tx Buffer Cancellation Finished */ | ||
| 4944 | /*! @{ */ | ||
| 4945 | #define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) | ||
| 4946 | #define CAN_TXBCF_TO_SHIFT (0U) | ||
| 4947 | /*! TO - Cancellation finished. | ||
| 4948 | */ | ||
| 4949 | #define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) | ||
| 4950 | /*! @} */ | ||
| 4951 | |||
| 4952 | /*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ | ||
| 4953 | /*! @{ */ | ||
| 4954 | #define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) | ||
| 4955 | #define CAN_TXBTIE_TIE_SHIFT (0U) | ||
| 4956 | /*! TIE - Transmission interrupt enable. | ||
| 4957 | */ | ||
| 4958 | #define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) | ||
| 4959 | /*! @} */ | ||
| 4960 | |||
| 4961 | /*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ | ||
| 4962 | /*! @{ */ | ||
| 4963 | #define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) | ||
| 4964 | #define CAN_TXBCIE_CFIE_SHIFT (0U) | ||
| 4965 | /*! CFIE - Cancellation finished interrupt enable. | ||
| 4966 | */ | ||
| 4967 | #define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) | ||
| 4968 | /*! @} */ | ||
| 4969 | |||
| 4970 | /*! @name TXEFC - Tx Event FIFO Configuration */ | ||
| 4971 | /*! @{ */ | ||
| 4972 | #define CAN_TXEFC_EFSA_MASK (0xFFFCU) | ||
| 4973 | #define CAN_TXEFC_EFSA_SHIFT (2U) | ||
| 4974 | /*! EFSA - Event FIFO start address. | ||
| 4975 | */ | ||
| 4976 | #define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) | ||
| 4977 | #define CAN_TXEFC_EFS_MASK (0x3F0000U) | ||
| 4978 | #define CAN_TXEFC_EFS_SHIFT (16U) | ||
| 4979 | /*! EFS - Event FIFO size 0 = Tx event FIFO disabled. | ||
| 4980 | */ | ||
| 4981 | #define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) | ||
| 4982 | #define CAN_TXEFC_EFWM_MASK (0x3F000000U) | ||
| 4983 | #define CAN_TXEFC_EFWM_SHIFT (24U) | ||
| 4984 | /*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. | ||
| 4985 | */ | ||
| 4986 | #define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) | ||
| 4987 | /*! @} */ | ||
| 4988 | |||
| 4989 | /*! @name TXEFS - Tx Event FIFO Status */ | ||
| 4990 | /*! @{ */ | ||
| 4991 | #define CAN_TXEFS_EFFL_MASK (0x3FU) | ||
| 4992 | #define CAN_TXEFS_EFFL_SHIFT (0U) | ||
| 4993 | /*! EFFL - Event FIFO fill level. | ||
| 4994 | */ | ||
| 4995 | #define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) | ||
| 4996 | #define CAN_TXEFS_EFGI_MASK (0x1F00U) | ||
| 4997 | #define CAN_TXEFS_EFGI_SHIFT (8U) | ||
| 4998 | /*! EFGI - Event FIFO get index. | ||
| 4999 | */ | ||
| 5000 | #define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) | ||
| 5001 | #define CAN_TXEFS_EFPI_MASK (0x3F0000U) | ||
| 5002 | #define CAN_TXEFS_EFPI_SHIFT (16U) | ||
| 5003 | /*! EFPI - Event FIFO put index. | ||
| 5004 | */ | ||
| 5005 | #define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) | ||
| 5006 | #define CAN_TXEFS_EFF_MASK (0x1000000U) | ||
| 5007 | #define CAN_TXEFS_EFF_SHIFT (24U) | ||
| 5008 | /*! EFF - Event FIFO full. | ||
| 5009 | */ | ||
| 5010 | #define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) | ||
| 5011 | #define CAN_TXEFS_TEFL_MASK (0x2000000U) | ||
| 5012 | #define CAN_TXEFS_TEFL_SHIFT (25U) | ||
| 5013 | /*! TEFL - Tx event FIFO element lost. | ||
| 5014 | */ | ||
| 5015 | #define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) | ||
| 5016 | /*! @} */ | ||
| 5017 | |||
| 5018 | /*! @name TXEFA - Tx Event FIFO Acknowledge */ | ||
| 5019 | /*! @{ */ | ||
| 5020 | #define CAN_TXEFA_EFAI_MASK (0x1FU) | ||
| 5021 | #define CAN_TXEFA_EFAI_SHIFT (0U) | ||
| 5022 | /*! EFAI - Event FIFO acknowledge index. | ||
| 5023 | */ | ||
| 5024 | #define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) | ||
| 5025 | /*! @} */ | ||
| 5026 | |||
| 5027 | /*! @name MRBA - CAN Message RAM Base Address */ | ||
| 5028 | /*! @{ */ | ||
| 5029 | #define CAN_MRBA_BA_MASK (0xFFFF0000U) | ||
| 5030 | #define CAN_MRBA_BA_SHIFT (16U) | ||
| 5031 | /*! BA - Base address for the message RAM in the chip memory map. | ||
| 5032 | */ | ||
| 5033 | #define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) | ||
| 5034 | /*! @} */ | ||
| 5035 | |||
| 5036 | /*! @name ETSCC - External Timestamp Counter Configuration */ | ||
| 5037 | /*! @{ */ | ||
| 5038 | #define CAN_ETSCC_ETCP_MASK (0x7FFU) | ||
| 5039 | #define CAN_ETSCC_ETCP_SHIFT (0U) | ||
| 5040 | /*! ETCP - External timestamp prescaler value. | ||
| 5041 | */ | ||
| 5042 | #define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) | ||
| 5043 | #define CAN_ETSCC_ETCE_MASK (0x80000000U) | ||
| 5044 | #define CAN_ETSCC_ETCE_SHIFT (31U) | ||
| 5045 | /*! ETCE - External timestamp counter enable. | ||
| 5046 | */ | ||
| 5047 | #define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) | ||
| 5048 | /*! @} */ | ||
| 5049 | |||
| 5050 | /*! @name ETSCV - External Timestamp Counter Value */ | ||
| 5051 | /*! @{ */ | ||
| 5052 | #define CAN_ETSCV_ETSC_MASK (0xFFFFU) | ||
| 5053 | #define CAN_ETSCV_ETSC_SHIFT (0U) | ||
| 5054 | /*! ETSC - External timestamp counter. | ||
| 5055 | */ | ||
| 5056 | #define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) | ||
| 5057 | /*! @} */ | ||
| 5058 | |||
| 5059 | |||
| 5060 | /*! | ||
| 5061 | * @} | ||
| 5062 | */ /* end of group CAN_Register_Masks */ | ||
| 5063 | |||
| 5064 | |||
| 5065 | /* CAN - Peripheral instance base addresses */ | ||
| 5066 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5067 | /** Peripheral CAN0 base address */ | ||
| 5068 | #define CAN0_BASE (0x5009D000u) | ||
| 5069 | /** Peripheral CAN0 base address */ | ||
| 5070 | #define CAN0_BASE_NS (0x4009D000u) | ||
| 5071 | /** Peripheral CAN0 base pointer */ | ||
| 5072 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 5073 | /** Peripheral CAN0 base pointer */ | ||
| 5074 | #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) | ||
| 5075 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5076 | #define CAN_BASE_ADDRS { CAN0_BASE } | ||
| 5077 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5078 | #define CAN_BASE_PTRS { CAN0 } | ||
| 5079 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5080 | #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } | ||
| 5081 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5082 | #define CAN_BASE_PTRS_NS { CAN0_NS } | ||
| 5083 | #else | ||
| 5084 | /** Peripheral CAN0 base address */ | ||
| 5085 | #define CAN0_BASE (0x4009D000u) | ||
| 5086 | /** Peripheral CAN0 base pointer */ | ||
| 5087 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 5088 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5089 | #define CAN_BASE_ADDRS { CAN0_BASE } | ||
| 5090 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5091 | #define CAN_BASE_PTRS { CAN0 } | ||
| 5092 | #endif | ||
| 5093 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 5094 | #define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } | ||
| 5095 | |||
| 5096 | /*! | ||
| 5097 | * @} | ||
| 5098 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 5099 | |||
| 5100 | |||
| 5101 | /* ---------------------------------------------------------------------------- | ||
| 5102 | -- CDOG Peripheral Access Layer | ||
| 5103 | ---------------------------------------------------------------------------- */ | ||
| 5104 | |||
| 5105 | /*! | ||
| 5106 | * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer | ||
| 5107 | * @{ | ||
| 5108 | */ | ||
| 5109 | |||
| 5110 | /** CDOG - Register Layout Typedef */ | ||
| 5111 | typedef struct { | ||
| 5112 | __IO uint32_t CONTROL; /**< The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself., offset: 0x0 */ | ||
| 5113 | __IO uint32_t RELOAD; /**< Instruction timer reload, offset: 0x4 */ | ||
| 5114 | __IO uint32_t INSTRUCTION_TIMER; /**< The INSTRUCTION TIMER itself, offset: 0x8 */ | ||
| 5115 | __IO uint32_t SECURE_COUNTER; /**< Also known as SEC_CNT, offset: 0xC */ | ||
| 5116 | __I uint32_t STATUS; /**< Status register (1 of 2), offset: 0x10 */ | ||
| 5117 | __I uint32_t STATUS2; /**< STATUS register (2 of 2), offset: 0x14 */ | ||
| 5118 | __IO uint32_t FLAGS; /**< Hardware flags, offset: 0x18 */ | ||
| 5119 | __IO uint32_t PERSISTENT; /**< Persistent (Ad. Hoc., quasi-NV) data storage, offset: 0x1C */ | ||
| 5120 | __O uint32_t START; /**< Write address for issuing the START command., offset: 0x20 */ | ||
| 5121 | __O uint32_t STOP; /**< Write address for issuing the STOP command., offset: 0x24 */ | ||
| 5122 | __O uint32_t RESTART; /**< Write address for issuing the RESTART command., offset: 0x28 */ | ||
| 5123 | __O uint32_t ADD; /**< Write address for issuing the ADD command., offset: 0x2C */ | ||
| 5124 | __O uint32_t ADD1; /**< Write address for issuing the ADD1 command., offset: 0x30 */ | ||
| 5125 | __O uint32_t ADD16; /**< Write address for issuing the ADD16 command., offset: 0x34 */ | ||
| 5126 | __O uint32_t ADD256; /**< Write address for issuing the ADD16 command., offset: 0x38 */ | ||
| 5127 | __O uint32_t SUB; /**< Write address for issuing the SUB command., offset: 0x3C */ | ||
| 5128 | __O uint32_t SUB1; /**< Write address for issuing the SUB1 command., offset: 0x40 */ | ||
| 5129 | __O uint32_t SUB16; /**< Write address for issuing the SUB16 command., offset: 0x44 */ | ||
| 5130 | __O uint32_t SUB256; /**< Write address for issuing the SUB256 command., offset: 0x48 */ | ||
| 5131 | } CDOG_Type; | ||
| 5132 | |||
| 5133 | /* ---------------------------------------------------------------------------- | ||
| 5134 | -- CDOG Register Masks | ||
| 5135 | ---------------------------------------------------------------------------- */ | ||
| 5136 | |||
| 5137 | /*! | ||
| 5138 | * @addtogroup CDOG_Register_Masks CDOG Register Masks | ||
| 5139 | * @{ | ||
| 5140 | */ | ||
| 5141 | |||
| 5142 | /*! @name CONTROL - The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. */ | ||
| 5143 | /*! @{ */ | ||
| 5144 | #define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) | ||
| 5145 | #define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) | ||
| 5146 | /*! LOCK_CTRL - Lock control field | ||
| 5147 | */ | ||
| 5148 | #define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) | ||
| 5149 | #define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) | ||
| 5150 | #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) | ||
| 5151 | /*! TIMEOUT_CTRL - TIMEOUT control | ||
| 5152 | */ | ||
| 5153 | #define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) | ||
| 5154 | #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) | ||
| 5155 | #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) | ||
| 5156 | /*! MISCOMPARE_CTRL - MISCOMPARE control field | ||
| 5157 | */ | ||
| 5158 | #define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) | ||
| 5159 | #define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) | ||
| 5160 | #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) | ||
| 5161 | /*! SEQUENCE_CTRL - SEQUENCE control field | ||
| 5162 | */ | ||
| 5163 | #define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) | ||
| 5164 | #define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) | ||
| 5165 | #define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) | ||
| 5166 | /*! CONTROL_CTRL - CONTROL control field | ||
| 5167 | */ | ||
| 5168 | #define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) | ||
| 5169 | #define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) | ||
| 5170 | #define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) | ||
| 5171 | /*! STATE_CTRL - STATE control field | ||
| 5172 | */ | ||
| 5173 | #define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) | ||
| 5174 | #define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) | ||
| 5175 | #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) | ||
| 5176 | /*! ADDRESS_CTRL - ADDRESS control field | ||
| 5177 | */ | ||
| 5178 | #define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) | ||
| 5179 | #define CDOG_CONTROL_Un_Imps_MASK (0xFF00000U) | ||
| 5180 | #define CDOG_CONTROL_Un_Imps_SHIFT (20U) | ||
| 5181 | /*! Un_Imps - The un-imps are un-IMPs! | ||
| 5182 | */ | ||
| 5183 | #define CDOG_CONTROL_Un_Imps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_Un_Imps_SHIFT)) & CDOG_CONTROL_Un_Imps_MASK) | ||
| 5184 | #define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) | ||
| 5185 | #define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) | ||
| 5186 | /*! IRQ_PAUSE - IRQ pause control field | ||
| 5187 | */ | ||
| 5188 | #define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) | ||
| 5189 | #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) | ||
| 5190 | #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) | ||
| 5191 | /*! DEBUG_HALT_CTRL - DEBUG_HALT control field | ||
| 5192 | */ | ||
| 5193 | #define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) | ||
| 5194 | /*! @} */ | ||
| 5195 | |||
| 5196 | /*! @name RELOAD - Instruction timer reload */ | ||
| 5197 | /*! @{ */ | ||
| 5198 | #define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) | ||
| 5199 | #define CDOG_RELOAD_RLOAD_SHIFT (0U) | ||
| 5200 | /*! RLOAD - Inst. Timer reload value | ||
| 5201 | */ | ||
| 5202 | #define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) | ||
| 5203 | /*! @} */ | ||
| 5204 | |||
| 5205 | /*! @name INSTRUCTION_TIMER - The INSTRUCTION TIMER itself */ | ||
| 5206 | /*! @{ */ | ||
| 5207 | #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) | ||
| 5208 | #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) | ||
| 5209 | /*! INSTIM - INSTRUCTION TIMER 32-bit value | ||
| 5210 | */ | ||
| 5211 | #define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) | ||
| 5212 | /*! @} */ | ||
| 5213 | |||
| 5214 | /*! @name SECURE_COUNTER - Also known as SEC_CNT */ | ||
| 5215 | /*! @{ */ | ||
| 5216 | #define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) | ||
| 5217 | #define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) | ||
| 5218 | /*! SECCNT - Secure Counter | ||
| 5219 | */ | ||
| 5220 | #define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) | ||
| 5221 | /*! @} */ | ||
| 5222 | |||
| 5223 | /*! @name STATUS - Status register (1 of 2) */ | ||
| 5224 | /*! @{ */ | ||
| 5225 | #define CDOG_STATUS_NUMTOF_MASK (0xFFU) | ||
| 5226 | #define CDOG_STATUS_NUMTOF_SHIFT (0U) | ||
| 5227 | /*! NUMTOF - Number of Timeout Faults | ||
| 5228 | */ | ||
| 5229 | #define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) | ||
| 5230 | #define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) | ||
| 5231 | #define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) | ||
| 5232 | /*! NUMMISCOMPF - Number of Miscompare Faults | ||
| 5233 | */ | ||
| 5234 | #define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) | ||
| 5235 | #define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) | ||
| 5236 | #define CDOG_STATUS_NUMILSEQF_SHIFT (16U) | ||
| 5237 | /*! NUMILSEQF - Number of illegal sequence faults | ||
| 5238 | */ | ||
| 5239 | #define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) | ||
| 5240 | #define CDOG_STATUS_CURST_MASK (0xF000000U) | ||
| 5241 | #define CDOG_STATUS_CURST_SHIFT (24U) | ||
| 5242 | /*! CURST - Current State | ||
| 5243 | */ | ||
| 5244 | #define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) | ||
| 5245 | #define CDOG_STATUS_uN_iMps_MASK (0xF0000000U) | ||
| 5246 | #define CDOG_STATUS_uN_iMps_SHIFT (28U) | ||
| 5247 | /*! uN_iMps - Un implemented | ||
| 5248 | */ | ||
| 5249 | #define CDOG_STATUS_uN_iMps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_uN_iMps_SHIFT)) & CDOG_STATUS_uN_iMps_MASK) | ||
| 5250 | /*! @} */ | ||
| 5251 | |||
| 5252 | /*! @name STATUS2 - STATUS register (2 of 2) */ | ||
| 5253 | /*! @{ */ | ||
| 5254 | #define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) | ||
| 5255 | #define CDOG_STATUS2_NUMCNTF_SHIFT (0U) | ||
| 5256 | /*! NUMCNTF - Number (of) control faults | ||
| 5257 | */ | ||
| 5258 | #define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) | ||
| 5259 | #define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) | ||
| 5260 | #define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) | ||
| 5261 | /*! NUMILLSTF - Number (of) state faults | ||
| 5262 | */ | ||
| 5263 | #define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) | ||
| 5264 | #define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) | ||
| 5265 | #define CDOG_STATUS2_NUMILLA_SHIFT (16U) | ||
| 5266 | /*! NUMILLA - Number of (illegal) address faults | ||
| 5267 | */ | ||
| 5268 | #define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) | ||
| 5269 | #define CDOG_STATUS2_un_imPs_MASK (0xFF000000U) | ||
| 5270 | #define CDOG_STATUS2_un_imPs_SHIFT (24U) | ||
| 5271 | /*! un_imPs - Unimplemented bits, such as these here, aren't there. | ||
| 5272 | */ | ||
| 5273 | #define CDOG_STATUS2_un_imPs(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_un_imPs_SHIFT)) & CDOG_STATUS2_un_imPs_MASK) | ||
| 5274 | /*! @} */ | ||
| 5275 | |||
| 5276 | /*! @name FLAGS - Hardware flags */ | ||
| 5277 | /*! @{ */ | ||
| 5278 | #define CDOG_FLAGS_TO_FLAG_MASK (0x1U) | ||
| 5279 | #define CDOG_FLAGS_TO_FLAG_SHIFT (0U) | ||
| 5280 | /*! TO_FLAG - Timeout flag | ||
| 5281 | */ | ||
| 5282 | #define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) | ||
| 5283 | #define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) | ||
| 5284 | #define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) | ||
| 5285 | /*! MISCOM_FLAG - Miscompare flag | ||
| 5286 | */ | ||
| 5287 | #define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) | ||
| 5288 | #define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) | ||
| 5289 | #define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) | ||
| 5290 | /*! SEQ_FLAG - Sequence flag | ||
| 5291 | */ | ||
| 5292 | #define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) | ||
| 5293 | #define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) | ||
| 5294 | #define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) | ||
| 5295 | /*! CNT_FLAG - Control (fault) flag | ||
| 5296 | */ | ||
| 5297 | #define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) | ||
| 5298 | #define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) | ||
| 5299 | #define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) | ||
| 5300 | /*! STATE_FLAG - State flag | ||
| 5301 | */ | ||
| 5302 | #define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) | ||
| 5303 | #define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) | ||
| 5304 | #define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) | ||
| 5305 | /*! ADDR_FLAG - Address flag | ||
| 5306 | */ | ||
| 5307 | #define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) | ||
| 5308 | #define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) | ||
| 5309 | #define CDOG_FLAGS_POR_FLAG_SHIFT (16U) | ||
| 5310 | /*! POR_FLAG - Power-on reset flag | ||
| 5311 | */ | ||
| 5312 | #define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) | ||
| 5313 | /*! @} */ | ||
| 5314 | |||
| 5315 | /*! @name PERSISTENT - Persistent (Ad. Hoc., quasi-NV) data storage */ | ||
| 5316 | /*! @{ */ | ||
| 5317 | #define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) | ||
| 5318 | #define CDOG_PERSISTENT_PERSIS_SHIFT (0U) | ||
| 5319 | /*! PERSIS - 32 regs free for user SW to enjoy | ||
| 5320 | */ | ||
| 5321 | #define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) | ||
| 5322 | /*! @} */ | ||
| 5323 | |||
| 5324 | /*! @name START - Write address for issuing the START command. */ | ||
| 5325 | /*! @{ */ | ||
| 5326 | #define CDOG_START_STRT_MASK (0xFFFFFFFFU) | ||
| 5327 | #define CDOG_START_STRT_SHIFT (0U) | ||
| 5328 | /*! STRT - Address of start command access | ||
| 5329 | */ | ||
| 5330 | #define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) | ||
| 5331 | /*! @} */ | ||
| 5332 | |||
| 5333 | /*! @name STOP - Write address for issuing the STOP command. */ | ||
| 5334 | /*! @{ */ | ||
| 5335 | #define CDOG_STOP_STP_MASK (0xFFFFFFFFU) | ||
| 5336 | #define CDOG_STOP_STP_SHIFT (0U) | ||
| 5337 | /*! STP - Address of stop command access | ||
| 5338 | */ | ||
| 5339 | #define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) | ||
| 5340 | /*! @} */ | ||
| 5341 | |||
| 5342 | /*! @name RESTART - Write address for issuing the RESTART command. */ | ||
| 5343 | /*! @{ */ | ||
| 5344 | #define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) | ||
| 5345 | #define CDOG_RESTART_RSTRT_SHIFT (0U) | ||
| 5346 | /*! RSTRT - Write address for issuing the RESTART command. | ||
| 5347 | */ | ||
| 5348 | #define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) | ||
| 5349 | /*! @} */ | ||
| 5350 | |||
| 5351 | /*! @name ADD - Write address for issuing the ADD command. */ | ||
| 5352 | /*! @{ */ | ||
| 5353 | #define CDOG_ADD_AD_MASK (0xFFFFFFFFU) | ||
| 5354 | #define CDOG_ADD_AD_SHIFT (0U) | ||
| 5355 | /*! AD - Address of ADD command | ||
| 5356 | */ | ||
| 5357 | #define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) | ||
| 5358 | /*! @} */ | ||
| 5359 | |||
| 5360 | /*! @name ADD1 - Write address for issuing the ADD1 command. */ | ||
| 5361 | /*! @{ */ | ||
| 5362 | #define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) | ||
| 5363 | #define CDOG_ADD1_AD1_SHIFT (0U) | ||
| 5364 | /*! AD1 - Address of ADD1 command. | ||
| 5365 | */ | ||
| 5366 | #define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) | ||
| 5367 | /*! @} */ | ||
| 5368 | |||
| 5369 | /*! @name ADD16 - Write address for issuing the ADD16 command. */ | ||
| 5370 | /*! @{ */ | ||
| 5371 | #define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) | ||
| 5372 | #define CDOG_ADD16_AD16_SHIFT (0U) | ||
| 5373 | /*! AD16 - Address of ADD16 | ||
| 5374 | */ | ||
| 5375 | #define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) | ||
| 5376 | /*! @} */ | ||
| 5377 | |||
| 5378 | /*! @name ADD256 - Write address for issuing the ADD16 command. */ | ||
| 5379 | /*! @{ */ | ||
| 5380 | #define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) | ||
| 5381 | #define CDOG_ADD256_AD256_SHIFT (0U) | ||
| 5382 | /*! AD256 - Address of ADD256 command | ||
| 5383 | */ | ||
| 5384 | #define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) | ||
| 5385 | /*! @} */ | ||
| 5386 | |||
| 5387 | /*! @name SUB - Write address for issuing the SUB command. */ | ||
| 5388 | /*! @{ */ | ||
| 5389 | #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) | ||
| 5390 | #define CDOG_SUB_S0B_SHIFT (0U) | ||
| 5391 | /*! S0B - Address of SUB command. | ||
| 5392 | */ | ||
| 5393 | #define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) | ||
| 5394 | /*! @} */ | ||
| 5395 | |||
| 5396 | /*! @name SUB1 - Write address for issuing the SUB1 command. */ | ||
| 5397 | /*! @{ */ | ||
| 5398 | #define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) | ||
| 5399 | #define CDOG_SUB1_S1B_SHIFT (0U) | ||
| 5400 | /*! S1B - Address of SUB1 command. | ||
| 5401 | */ | ||
| 5402 | #define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) | ||
| 5403 | /*! @} */ | ||
| 5404 | |||
| 5405 | /*! @name SUB16 - Write address for issuing the SUB16 command. */ | ||
| 5406 | /*! @{ */ | ||
| 5407 | #define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) | ||
| 5408 | #define CDOG_SUB16_SB16_SHIFT (0U) | ||
| 5409 | /*! SB16 - Address of SUB16 command. | ||
| 5410 | */ | ||
| 5411 | #define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) | ||
| 5412 | /*! @} */ | ||
| 5413 | |||
| 5414 | /*! @name SUB256 - Write address for issuing the SUB256 command. */ | ||
| 5415 | /*! @{ */ | ||
| 5416 | #define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) | ||
| 5417 | #define CDOG_SUB256_SB256_SHIFT (0U) | ||
| 5418 | /*! SB256 - Address of (you guessed it) SUB256 command. | ||
| 5419 | */ | ||
| 5420 | #define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) | ||
| 5421 | /*! @} */ | ||
| 5422 | |||
| 5423 | |||
| 5424 | /*! | ||
| 5425 | * @} | ||
| 5426 | */ /* end of group CDOG_Register_Masks */ | ||
| 5427 | |||
| 5428 | |||
| 5429 | /* CDOG - Peripheral instance base addresses */ | ||
| 5430 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5431 | /** Peripheral CDOG base address */ | ||
| 5432 | #define CDOG_BASE (0x500A1000u) | ||
| 5433 | /** Peripheral CDOG base address */ | ||
| 5434 | #define CDOG_BASE_NS (0x400A1000u) | ||
| 5435 | /** Peripheral CDOG base pointer */ | ||
| 5436 | #define CDOG ((CDOG_Type *)CDOG_BASE) | ||
| 5437 | /** Peripheral CDOG base pointer */ | ||
| 5438 | #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) | ||
| 5439 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5440 | #define CDOG_BASE_ADDRS { CDOG_BASE } | ||
| 5441 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5442 | #define CDOG_BASE_PTRS { CDOG } | ||
| 5443 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5444 | #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } | ||
| 5445 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5446 | #define CDOG_BASE_PTRS_NS { CDOG_NS } | ||
| 5447 | #else | ||
| 5448 | /** Peripheral CDOG base address */ | ||
| 5449 | #define CDOG_BASE (0x400A1000u) | ||
| 5450 | /** Peripheral CDOG base pointer */ | ||
| 5451 | #define CDOG ((CDOG_Type *)CDOG_BASE) | ||
| 5452 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5453 | #define CDOG_BASE_ADDRS { CDOG_BASE } | ||
| 5454 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5455 | #define CDOG_BASE_PTRS { CDOG } | ||
| 5456 | #endif | ||
| 5457 | |||
| 5458 | /*! | ||
| 5459 | * @} | ||
| 5460 | */ /* end of group CDOG_Peripheral_Access_Layer */ | ||
| 5461 | |||
| 5462 | |||
| 5463 | /* ---------------------------------------------------------------------------- | ||
| 5464 | -- CRC Peripheral Access Layer | ||
| 5465 | ---------------------------------------------------------------------------- */ | ||
| 5466 | |||
| 5467 | /*! | ||
| 5468 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 5469 | * @{ | ||
| 5470 | */ | ||
| 5471 | |||
| 5472 | /** CRC - Register Layout Typedef */ | ||
| 5473 | typedef struct { | ||
| 5474 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ | ||
| 5475 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ | ||
| 5476 | union { /* offset: 0x8 */ | ||
| 5477 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ | ||
| 5478 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ | ||
| 5479 | }; | ||
| 5480 | } CRC_Type; | ||
| 5481 | |||
| 5482 | /* ---------------------------------------------------------------------------- | ||
| 5483 | -- CRC Register Masks | ||
| 5484 | ---------------------------------------------------------------------------- */ | ||
| 5485 | |||
| 5486 | /*! | ||
| 5487 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 5488 | * @{ | ||
| 5489 | */ | ||
| 5490 | |||
| 5491 | /*! @name MODE - CRC mode register */ | ||
| 5492 | /*! @{ */ | ||
| 5493 | #define CRC_MODE_CRC_POLY_MASK (0x3U) | ||
| 5494 | #define CRC_MODE_CRC_POLY_SHIFT (0U) | ||
| 5495 | /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial | ||
| 5496 | */ | ||
| 5497 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) | ||
| 5498 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) | ||
| 5499 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) | ||
| 5500 | /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) | ||
| 5501 | */ | ||
| 5502 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) | ||
| 5503 | #define CRC_MODE_CMPL_WR_MASK (0x8U) | ||
| 5504 | #define CRC_MODE_CMPL_WR_SHIFT (3U) | ||
| 5505 | /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA | ||
| 5506 | */ | ||
| 5507 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) | ||
| 5508 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) | ||
| 5509 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) | ||
| 5510 | /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM | ||
| 5511 | */ | ||
| 5512 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) | ||
| 5513 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) | ||
| 5514 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) | ||
| 5515 | /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM | ||
| 5516 | */ | ||
| 5517 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) | ||
| 5518 | /*! @} */ | ||
| 5519 | |||
| 5520 | /*! @name SEED - CRC seed register */ | ||
| 5521 | /*! @{ */ | ||
| 5522 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) | ||
| 5523 | #define CRC_SEED_CRC_SEED_SHIFT (0U) | ||
| 5524 | /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with | ||
| 5525 | * selected bit order and 1's complement pre-processes. A write access to this register will | ||
| 5526 | * overrule the CRC calculation in progresses. | ||
| 5527 | */ | ||
| 5528 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) | ||
| 5529 | /*! @} */ | ||
| 5530 | |||
| 5531 | /*! @name SUM - CRC checksum register */ | ||
| 5532 | /*! @{ */ | ||
| 5533 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) | ||
| 5534 | #define CRC_SUM_CRC_SUM_SHIFT (0U) | ||
| 5535 | /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. | ||
| 5536 | */ | ||
| 5537 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) | ||
| 5538 | /*! @} */ | ||
| 5539 | |||
| 5540 | /*! @name WR_DATA - CRC data register */ | ||
| 5541 | /*! @{ */ | ||
| 5542 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) | ||
| 5543 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) | ||
| 5544 | /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with | ||
| 5545 | * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and | ||
| 5546 | * accept back-to-back transactions. | ||
| 5547 | */ | ||
| 5548 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) | ||
| 5549 | /*! @} */ | ||
| 5550 | |||
| 5551 | |||
| 5552 | /*! | ||
| 5553 | * @} | ||
| 5554 | */ /* end of group CRC_Register_Masks */ | ||
| 5555 | |||
| 5556 | |||
| 5557 | /* CRC - Peripheral instance base addresses */ | ||
| 5558 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5559 | /** Peripheral CRC_ENGINE base address */ | ||
| 5560 | #define CRC_ENGINE_BASE (0x50095000u) | ||
| 5561 | /** Peripheral CRC_ENGINE base address */ | ||
| 5562 | #define CRC_ENGINE_BASE_NS (0x40095000u) | ||
| 5563 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5564 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5565 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5566 | #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) | ||
| 5567 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5568 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5569 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5570 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5571 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5572 | #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } | ||
| 5573 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5574 | #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } | ||
| 5575 | #else | ||
| 5576 | /** Peripheral CRC_ENGINE base address */ | ||
| 5577 | #define CRC_ENGINE_BASE (0x40095000u) | ||
| 5578 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5579 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5580 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5581 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5582 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5583 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5584 | #endif | ||
| 5585 | |||
| 5586 | /*! | ||
| 5587 | * @} | ||
| 5588 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 5589 | |||
| 5590 | |||
| 5591 | /* ---------------------------------------------------------------------------- | ||
| 5592 | -- CTIMER Peripheral Access Layer | ||
| 5593 | ---------------------------------------------------------------------------- */ | ||
| 5594 | |||
| 5595 | /*! | ||
| 5596 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer | ||
| 5597 | * @{ | ||
| 5598 | */ | ||
| 5599 | |||
| 5600 | /** CTIMER - Register Layout Typedef */ | ||
| 5601 | typedef struct { | ||
| 5602 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ | ||
| 5603 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ | ||
| 5604 | __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ | ||
| 5605 | __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ | ||
| 5606 | __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ | ||
| 5607 | __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ | ||
| 5608 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ | ||
| 5609 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ | ||
| 5610 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ | ||
| 5611 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ | ||
| 5612 | uint8_t RESERVED_0[48]; | ||
| 5613 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ | ||
| 5614 | __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ | ||
| 5615 | __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ | ||
| 5616 | } CTIMER_Type; | ||
| 5617 | |||
| 5618 | /* ---------------------------------------------------------------------------- | ||
| 5619 | -- CTIMER Register Masks | ||
| 5620 | ---------------------------------------------------------------------------- */ | ||
| 5621 | |||
| 5622 | /*! | ||
| 5623 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks | ||
| 5624 | * @{ | ||
| 5625 | */ | ||
| 5626 | |||
| 5627 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ | ||
| 5628 | /*! @{ */ | ||
| 5629 | #define CTIMER_IR_MR0INT_MASK (0x1U) | ||
| 5630 | #define CTIMER_IR_MR0INT_SHIFT (0U) | ||
| 5631 | /*! MR0INT - Interrupt flag for match channel 0. | ||
| 5632 | */ | ||
| 5633 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) | ||
| 5634 | #define CTIMER_IR_MR1INT_MASK (0x2U) | ||
| 5635 | #define CTIMER_IR_MR1INT_SHIFT (1U) | ||
| 5636 | /*! MR1INT - Interrupt flag for match channel 1. | ||
| 5637 | */ | ||
| 5638 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) | ||
| 5639 | #define CTIMER_IR_MR2INT_MASK (0x4U) | ||
| 5640 | #define CTIMER_IR_MR2INT_SHIFT (2U) | ||
| 5641 | /*! MR2INT - Interrupt flag for match channel 2. | ||
| 5642 | */ | ||
| 5643 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) | ||
| 5644 | #define CTIMER_IR_MR3INT_MASK (0x8U) | ||
| 5645 | #define CTIMER_IR_MR3INT_SHIFT (3U) | ||
| 5646 | /*! MR3INT - Interrupt flag for match channel 3. | ||
| 5647 | */ | ||
| 5648 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) | ||
| 5649 | #define CTIMER_IR_CR0INT_MASK (0x10U) | ||
| 5650 | #define CTIMER_IR_CR0INT_SHIFT (4U) | ||
| 5651 | /*! CR0INT - Interrupt flag for capture channel 0 event. | ||
| 5652 | */ | ||
| 5653 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) | ||
| 5654 | #define CTIMER_IR_CR1INT_MASK (0x20U) | ||
| 5655 | #define CTIMER_IR_CR1INT_SHIFT (5U) | ||
| 5656 | /*! CR1INT - Interrupt flag for capture channel 1 event. | ||
| 5657 | */ | ||
| 5658 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) | ||
| 5659 | #define CTIMER_IR_CR2INT_MASK (0x40U) | ||
| 5660 | #define CTIMER_IR_CR2INT_SHIFT (6U) | ||
| 5661 | /*! CR2INT - Interrupt flag for capture channel 2 event. | ||
| 5662 | */ | ||
| 5663 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) | ||
| 5664 | #define CTIMER_IR_CR3INT_MASK (0x80U) | ||
| 5665 | #define CTIMER_IR_CR3INT_SHIFT (7U) | ||
| 5666 | /*! CR3INT - Interrupt flag for capture channel 3 event. | ||
| 5667 | */ | ||
| 5668 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) | ||
| 5669 | /*! @} */ | ||
| 5670 | |||
| 5671 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ | ||
| 5672 | /*! @{ */ | ||
| 5673 | #define CTIMER_TCR_CEN_MASK (0x1U) | ||
| 5674 | #define CTIMER_TCR_CEN_SHIFT (0U) | ||
| 5675 | /*! CEN - Counter enable. | ||
| 5676 | * 0b0..Disabled.The counters are disabled. | ||
| 5677 | * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. | ||
| 5678 | */ | ||
| 5679 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) | ||
| 5680 | #define CTIMER_TCR_CRST_MASK (0x2U) | ||
| 5681 | #define CTIMER_TCR_CRST_SHIFT (1U) | ||
| 5682 | /*! CRST - Counter reset. | ||
| 5683 | * 0b0..Disabled. Do nothing. | ||
| 5684 | * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of | ||
| 5685 | * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. | ||
| 5686 | */ | ||
| 5687 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) | ||
| 5688 | /*! @} */ | ||
| 5689 | |||
| 5690 | /*! @name TC - Timer Counter */ | ||
| 5691 | /*! @{ */ | ||
| 5692 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) | ||
| 5693 | #define CTIMER_TC_TCVAL_SHIFT (0U) | ||
| 5694 | /*! TCVAL - Timer counter value. | ||
| 5695 | */ | ||
| 5696 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) | ||
| 5697 | /*! @} */ | ||
| 5698 | |||
| 5699 | /*! @name PR - Prescale Register */ | ||
| 5700 | /*! @{ */ | ||
| 5701 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) | ||
| 5702 | #define CTIMER_PR_PRVAL_SHIFT (0U) | ||
| 5703 | /*! PRVAL - Prescale counter value. | ||
| 5704 | */ | ||
| 5705 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) | ||
| 5706 | /*! @} */ | ||
| 5707 | |||
| 5708 | /*! @name PC - Prescale Counter */ | ||
| 5709 | /*! @{ */ | ||
| 5710 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) | ||
| 5711 | #define CTIMER_PC_PCVAL_SHIFT (0U) | ||
| 5712 | /*! PCVAL - Prescale counter value. | ||
| 5713 | */ | ||
| 5714 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) | ||
| 5715 | /*! @} */ | ||
| 5716 | |||
| 5717 | /*! @name MCR - Match Control Register */ | ||
| 5718 | /*! @{ */ | ||
| 5719 | #define CTIMER_MCR_MR0I_MASK (0x1U) | ||
| 5720 | #define CTIMER_MCR_MR0I_SHIFT (0U) | ||
| 5721 | /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. | ||
| 5722 | */ | ||
| 5723 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) | ||
| 5724 | #define CTIMER_MCR_MR0R_MASK (0x2U) | ||
| 5725 | #define CTIMER_MCR_MR0R_SHIFT (1U) | ||
| 5726 | /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. | ||
| 5727 | */ | ||
| 5728 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) | ||
| 5729 | #define CTIMER_MCR_MR0S_MASK (0x4U) | ||
| 5730 | #define CTIMER_MCR_MR0S_SHIFT (2U) | ||
| 5731 | /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. | ||
| 5732 | */ | ||
| 5733 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) | ||
| 5734 | #define CTIMER_MCR_MR1I_MASK (0x8U) | ||
| 5735 | #define CTIMER_MCR_MR1I_SHIFT (3U) | ||
| 5736 | /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. | ||
| 5737 | */ | ||
| 5738 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) | ||
| 5739 | #define CTIMER_MCR_MR1R_MASK (0x10U) | ||
| 5740 | #define CTIMER_MCR_MR1R_SHIFT (4U) | ||
| 5741 | /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. | ||
| 5742 | */ | ||
| 5743 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) | ||
| 5744 | #define CTIMER_MCR_MR1S_MASK (0x20U) | ||
| 5745 | #define CTIMER_MCR_MR1S_SHIFT (5U) | ||
| 5746 | /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. | ||
| 5747 | */ | ||
| 5748 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) | ||
| 5749 | #define CTIMER_MCR_MR2I_MASK (0x40U) | ||
| 5750 | #define CTIMER_MCR_MR2I_SHIFT (6U) | ||
| 5751 | /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. | ||
| 5752 | */ | ||
| 5753 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) | ||
| 5754 | #define CTIMER_MCR_MR2R_MASK (0x80U) | ||
| 5755 | #define CTIMER_MCR_MR2R_SHIFT (7U) | ||
| 5756 | /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. | ||
| 5757 | */ | ||
| 5758 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) | ||
| 5759 | #define CTIMER_MCR_MR2S_MASK (0x100U) | ||
| 5760 | #define CTIMER_MCR_MR2S_SHIFT (8U) | ||
| 5761 | /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. | ||
| 5762 | */ | ||
| 5763 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK | ||