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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/drivers/fsl_reset.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/drivers/fsl_reset.h
new file mode 100644
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5516/drivers/fsl_reset.h
@@ -0,0 +1,255 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_RESET_H_
10#define _FSL_RESET_H_
11
12#include <assert.h>
13#include <stdbool.h>
14#include <stdint.h>
15#include <string.h>
16#include "fsl_device_registers.h"
17
18/*!
19 * @addtogroup reset
20 * @{
21 */
22
23/*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27/*! @name Driver version */
28/*@{*/
29/*! @brief reset driver version 2.0.0. */
30#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
31/*@}*/
32
33/*!
34 * @brief Enumeration for peripheral reset control bits
35 *
36 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
37 */
38typedef enum _SYSCON_RSTn
39{
40 kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */
41 kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */
42 kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */
43 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
44 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
45 kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */
46 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
47 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
48 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
49 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
50 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
51 kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
52 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
53 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
54 kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */
55 kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */
56 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
57
58 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
59 kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */
60 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
61 kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */
62 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
63 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
64 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
65 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
66 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
67 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
68 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
69 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
70 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
71 kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
72 kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */
73 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
74 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
75 kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */
76 kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */
77
78 kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
79 kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */
80 kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */
81 kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */
82 kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */
83 kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */
84 kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
85 kCWT_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */
86 kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
87 kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */
88 kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */
89 kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */
90 kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */
91 kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */
92 kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
93 kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
94 kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
95 kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */
96 kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */
97 kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */
98 kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */
99 kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */
100} SYSCON_RSTn_t;
101
102/** Array initializers with peripheral reset bits **/
103#define ADC_RSTS \
104 { \
105 kADC0_RST_SHIFT_RSTn \
106 } /* Reset bits for ADC peripheral */
107#define MCAN_RSTS \
108 { \
109 kMCAN_RST_SHIFT_RSTn \
110 } /* Reset bits for CAN peripheral */
111#define CRC_RSTS \
112 { \
113 kCRC_RST_SHIFT_RSTn \
114 } /* Reset bits for CRC peripheral */
115#define CTIMER_RSTS \
116 { \
117 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
118 kCTIMER4_RST_SHIFT_RSTn \
119 } /* Reset bits for CTIMER peripheral */
120#define DMA_RSTS_N \
121 { \
122 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
123 } /* Reset bits for DMA peripheral */
124
125#define FLEXCOMM_RSTS \
126 { \
127 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
128 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \
129 } /* Reset bits for FLEXCOMM peripheral */
130#define GINT_RSTS \
131 { \
132 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
133 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
134#define GPIO_RSTS_N \
135 { \
136 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
137 } /* Reset bits for GPIO peripheral */
138#define INPUTMUX_RSTS \
139 { \
140 kMUX0_RST_SHIFT_RSTn \
141 } /* Reset bits for INPUTMUX peripheral */
142#define IOCON_RSTS \
143 { \
144 kIOCON_RST_SHIFT_RSTn \
145 } /* Reset bits for IOCON peripheral */
146#define FLASH_RSTS \
147 { \
148 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
149 } /* Reset bits for Flash peripheral */
150#define MRT_RSTS \
151 { \
152 kMRT_RST_SHIFT_RSTn \
153 } /* Reset bits for MRT peripheral */
154#define PINT_RSTS \
155 { \
156 kPINT_RST_SHIFT_RSTn \
157 } /* Reset bits for PINT peripheral */
158#define CWT_RSTS \
159 { \
160 kCWT_RST_SHIFT_RSTn \
161 } /* Reset bits for CWT peripheral */
162#define RNG_RSTS \
163 { \
164 kRNG_RST_SHIFT_RSTn \
165 } /* Reset bits for RNG peripheral */
166#define SCT_RSTS \
167 { \
168 kSCT0_RST_SHIFT_RSTn \
169 } /* Reset bits for SCT peripheral */
170#define USB0D_RST \
171 { \
172 kUSB0D_RST_SHIFT_RSTn \
173 } /* Reset bits for USB0D peripheral */
174#define USB0HMR_RST \
175 { \
176 kUSB0HMR_RST_SHIFT_RSTn \
177 } /* Reset bits for USB0HMR peripheral */
178#define USB0HSL_RST \
179 { \
180 kUSB0HSL_RST_SHIFT_RSTn \
181 } /* Reset bits for USB0HSL peripheral */
182#define USB1H_RST \
183 { \
184 kUSB1H_RST_SHIFT_RSTn \
185 } /* Reset bits for USB1H peripheral */
186#define USB1D_RST \
187 { \
188 kUSB1D_RST_SHIFT_RSTn \
189 } /* Reset bits for USB1D peripheral */
190#define USB1RAM_RST \
191 { \
192 kUSB1RAM_RST_SHIFT_RSTn \
193 } /* Reset bits for USB1RAM peripheral */
194#define UTICK_RSTS \
195 { \
196 kUTICK_RST_SHIFT_RSTn \
197 } /* Reset bits for UTICK peripheral */
198#define WWDT_RSTS \
199 { \
200 kWWDT_RST_SHIFT_RSTn \
201 } /* Reset bits for WWDT peripheral */
202#define PLU_RSTS_N \
203 { \
204 kPLULUT_RST_SHIFT_RSTn \
205 } /* Reset bits for PLU peripheral */
206#define OSTIMER_RSTS \
207 { \
208 kOSTIMER0_RST_SHIFT_RSTn \
209 } /* Reset bits for OSTIMER peripheral */
210typedef SYSCON_RSTn_t reset_ip_name_t;
211
212/*******************************************************************************
213 * API
214 ******************************************************************************/
215#if defined(__cplusplus)
216extern "C" {
217#endif
218
219/*!
220 * @brief Assert reset to peripheral.
221 *
222 * Asserts reset signal to specified peripheral module.
223 *
224 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
225 * and reset bit position in the reset register.
226 */
227void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
228
229/*!
230 * @brief Clear reset to peripheral.
231 *
232 * Clears reset signal to specified peripheral module, allows it to operate.
233 *
234 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
235 * and reset bit position in the reset register.
236 */
237void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
238
239/*!
240 * @brief Reset peripheral module.
241 *
242 * Reset peripheral module.
243 *
244 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
245 * and reset bit position in the reset register.
246 */
247void RESET_PeripheralReset(reset_ip_name_t peripheral);
248
249#if defined(__cplusplus)
250}
251#endif
252
253/*! @} */
254
255#endif /* _FSL_RESET_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:28 +0100