diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC5528')
37 files changed, 36856 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5528/LPC5528.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5528/LPC5528.h new file mode 100644 index 000000000..8d917cf34 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC5528/LPC5528.h | |||
| @@ -0,0 +1,25455 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: LPC5528JBD100 | ||
| 4 | ** LPC5528JBD64 | ||
| 5 | ** LPC5528JEV98 | ||
| 6 | ** | ||
| 7 | ** Compilers: GNU C Compiler | ||
| 8 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 9 | ** Keil ARM C/C++ Compiler | ||
| 10 | ** MCUXpresso Compiler | ||
| 11 | ** | ||
| 12 | ** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 | ||
| 13 | ** Version: rev. 1.1, 2019-05-16 | ||
| 14 | ** Build: b200928 | ||
| 15 | ** | ||
| 16 | ** Abstract: | ||
| 17 | ** CMSIS Peripheral Access Layer for LPC5528 | ||
| 18 | ** | ||
| 19 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 20 | ** Copyright 2016-2020 NXP | ||
| 21 | ** All rights reserved. | ||
| 22 | ** | ||
| 23 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 24 | ** | ||
| 25 | ** http: www.nxp.com | ||
| 26 | ** mail: [email protected] | ||
| 27 | ** | ||
| 28 | ** Revisions: | ||
| 29 | ** - rev. 1.0 (2018-08-22) | ||
| 30 | ** Initial version based on v0.2UM | ||
| 31 | ** - rev. 1.1 (2019-05-16) | ||
| 32 | ** Initial A1 version based on v1.3UM | ||
| 33 | ** | ||
| 34 | ** ################################################################### | ||
| 35 | */ | ||
| 36 | |||
| 37 | /*! | ||
| 38 | * @file LPC5528.h | ||
| 39 | * @version 1.1 | ||
| 40 | * @date 2019-05-16 | ||
| 41 | * @brief CMSIS Peripheral Access Layer for LPC5528 | ||
| 42 | * | ||
| 43 | * CMSIS Peripheral Access Layer for LPC5528 | ||
| 44 | */ | ||
| 45 | |||
| 46 | #ifndef _LPC5528_H_ | ||
| 47 | #define _LPC5528_H_ /**< Symbol preventing repeated inclusion */ | ||
| 48 | |||
| 49 | /** Memory map major version (memory maps with equal major version number are | ||
| 50 | * compatible) */ | ||
| 51 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 52 | /** Memory map minor version */ | ||
| 53 | #define MCU_MEM_MAP_VERSION_MINOR 0x0001U | ||
| 54 | |||
| 55 | |||
| 56 | /* ---------------------------------------------------------------------------- | ||
| 57 | -- Interrupt vector numbers | ||
| 58 | ---------------------------------------------------------------------------- */ | ||
| 59 | |||
| 60 | /*! | ||
| 61 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 62 | * @{ | ||
| 63 | */ | ||
| 64 | |||
| 65 | /** Interrupt Number Definitions */ | ||
| 66 | #define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ | ||
| 67 | |||
| 68 | typedef enum IRQn { | ||
| 69 | /* Auxiliary constants */ | ||
| 70 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 71 | |||
| 72 | /* Core interrupts */ | ||
| 73 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 74 | HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ | ||
| 75 | MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ | ||
| 76 | BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ | ||
| 77 | UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ | ||
| 78 | SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ | ||
| 79 | SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ | ||
| 80 | DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ | ||
| 81 | PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ | ||
| 82 | SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ | ||
| 83 | |||
| 84 | /* Device specific interrupts */ | ||
| 85 | WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ | ||
| 86 | DMA0_IRQn = 1, /**< DMA0 controller */ | ||
| 87 | GINT0_IRQn = 2, /**< GPIO group 0 */ | ||
| 88 | GINT1_IRQn = 3, /**< GPIO group 1 */ | ||
| 89 | PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ | ||
| 90 | PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ | ||
| 91 | PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ | ||
| 92 | PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ | ||
| 93 | UTICK0_IRQn = 8, /**< Micro-tick Timer */ | ||
| 94 | MRT0_IRQn = 9, /**< Multi-rate timer */ | ||
| 95 | CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ | ||
| 96 | CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ | ||
| 97 | SCT0_IRQn = 12, /**< SCTimer/PWM */ | ||
| 98 | CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ | ||
| 99 | FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 100 | FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 101 | FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 102 | FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 103 | FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 104 | FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 105 | FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 106 | FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 107 | ADC0_IRQn = 22, /**< ADC0 */ | ||
| 108 | Reserved39_IRQn = 23, /**< Reserved interrupt */ | ||
| 109 | ACMP_IRQn = 24, /**< ACMP interrupts */ | ||
| 110 | Reserved41_IRQn = 25, /**< Reserved interrupt */ | ||
| 111 | Reserved42_IRQn = 26, /**< Reserved interrupt */ | ||
| 112 | USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ | ||
| 113 | USB0_IRQn = 28, /**< USB device */ | ||
| 114 | RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ | ||
| 115 | Reserved46_IRQn = 30, /**< Reserved interrupt */ | ||
| 116 | Reserved47_IRQn = 31, /**< Reserved interrupt */ | ||
| 117 | PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ | ||
| 118 | PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ | ||
| 119 | PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ | ||
| 120 | PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ | ||
| 121 | CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ | ||
| 122 | CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ | ||
| 123 | OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ | ||
| 124 | Reserved55_IRQn = 39, /**< Reserved interrupt */ | ||
| 125 | Reserved56_IRQn = 40, /**< Reserved interrupt */ | ||
| 126 | Reserved57_IRQn = 41, /**< Reserved interrupt */ | ||
| 127 | SDIO_IRQn = 42, /**< SD/MMC */ | ||
| 128 | Reserved59_IRQn = 43, /**< Reserved interrupt */ | ||
| 129 | Reserved60_IRQn = 44, /**< Reserved interrupt */ | ||
| 130 | Reserved61_IRQn = 45, /**< Reserved interrupt */ | ||
| 131 | USB1_PHY_IRQn = 46, /**< USB1_PHY */ | ||
| 132 | USB1_IRQn = 47, /**< USB1 interrupt */ | ||
| 133 | USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ | ||
| 134 | SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ | ||
| 135 | SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ | ||
| 136 | SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ | ||
| 137 | PLU_IRQn = 52, /**< PLU interrupt */ | ||
| 138 | SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ | ||
| 139 | Reserved70_IRQn = 54, /**< Reserved interrupt */ | ||
| 140 | CASER_IRQn = 55, /**< CASPER interrupt */ | ||
| 141 | Reserved72_IRQn = 56, /**< Reserved interrupt */ | ||
| 142 | PQ_IRQn = 57, /**< PQ interrupt */ | ||
| 143 | DMA1_IRQn = 58, /**< DMA1 interrupt */ | ||
| 144 | FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ | ||
| 145 | } IRQn_Type; | ||
| 146 | |||
| 147 | /*! | ||
| 148 | * @} | ||
| 149 | */ /* end of group Interrupt_vector_numbers */ | ||
| 150 | |||
| 151 | |||
| 152 | /* ---------------------------------------------------------------------------- | ||
| 153 | -- Cortex M33 Core Configuration | ||
| 154 | ---------------------------------------------------------------------------- */ | ||
| 155 | |||
| 156 | /*! | ||
| 157 | * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration | ||
| 158 | * @{ | ||
| 159 | */ | ||
| 160 | |||
| 161 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 162 | #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ | ||
| 163 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 164 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 165 | #define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ | ||
| 166 | #define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ | ||
| 167 | |||
| 168 | #include "core_cm33.h" /* Core Peripheral Access Layer */ | ||
| 169 | #include "system_LPC5528.h" /* Device specific configuration file */ | ||
| 170 | |||
| 171 | /*! | ||
| 172 | * @} | ||
| 173 | */ /* end of group Cortex_Core_Configuration */ | ||
| 174 | |||
| 175 | |||
| 176 | /* ---------------------------------------------------------------------------- | ||
| 177 | -- Mapping Information | ||
| 178 | ---------------------------------------------------------------------------- */ | ||
| 179 | |||
| 180 | /*! | ||
| 181 | * @addtogroup Mapping_Information Mapping Information | ||
| 182 | * @{ | ||
| 183 | */ | ||
| 184 | |||
| 185 | /** Mapping Information */ | ||
| 186 | /*! | ||
| 187 | * @addtogroup dma_request | ||
| 188 | * @{ | ||
| 189 | */ | ||
| 190 | |||
| 191 | /******************************************************************************* | ||
| 192 | * Definitions | ||
| 193 | ******************************************************************************/ | ||
| 194 | |||
| 195 | /*! | ||
| 196 | * @brief Structure for the DMA hardware request | ||
| 197 | * | ||
| 198 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 199 | * hardware request to trigger the DMA transfer accordingly. The index | ||
| 200 | * of the hardware request varies according to the to SoC. | ||
| 201 | */ | ||
| 202 | typedef enum _dma_request_source | ||
| 203 | { | ||
| 204 | kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 205 | kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 206 | kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 207 | kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 208 | kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 209 | kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 210 | kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 211 | kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 212 | kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 213 | kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 214 | kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 215 | kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 216 | kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 217 | kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 218 | kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 219 | kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 220 | kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 221 | kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 222 | kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ | ||
| 223 | kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ | ||
| 224 | kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ | ||
| 225 | kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ | ||
| 226 | kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ | ||
| 227 | kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ | ||
| 228 | kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ | ||
| 229 | kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ | ||
| 230 | kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ | ||
| 231 | kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ | ||
| 232 | kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ | ||
| 233 | kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ | ||
| 234 | kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ | ||
| 235 | } dma_request_source_t; | ||
| 236 | |||
| 237 | /* @} */ | ||
| 238 | |||
| 239 | |||
| 240 | /*! | ||
| 241 | * @} | ||
| 242 | */ /* end of group Mapping_Information */ | ||
| 243 | |||
| 244 | |||
| 245 | /* ---------------------------------------------------------------------------- | ||
| 246 | -- Device Peripheral Access Layer | ||
| 247 | ---------------------------------------------------------------------------- */ | ||
| 248 | |||
| 249 | /*! | ||
| 250 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 251 | * @{ | ||
| 252 | */ | ||
| 253 | |||
| 254 | |||
| 255 | /* | ||
| 256 | ** Start of section using anonymous unions | ||
| 257 | */ | ||
| 258 | |||
| 259 | #if defined(__ARMCC_VERSION) | ||
| 260 | #if (__ARMCC_VERSION >= 6010050) | ||
| 261 | #pragma clang diagnostic push | ||
| 262 | #else | ||
| 263 | #pragma push | ||
| 264 | #pragma anon_unions | ||
| 265 | #endif | ||
| 266 | #elif defined(__GNUC__) | ||
| 267 | /* anonymous unions are enabled by default */ | ||
| 268 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 269 | #pragma language=extended | ||
| 270 | #else | ||
| 271 | #error Not supported compiler type | ||
| 272 | #endif | ||
| 273 | |||
| 274 | /* ---------------------------------------------------------------------------- | ||
| 275 | -- ADC Peripheral Access Layer | ||
| 276 | ---------------------------------------------------------------------------- */ | ||
| 277 | |||
| 278 | /*! | ||
| 279 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 280 | * @{ | ||
| 281 | */ | ||
| 282 | |||
| 283 | /** ADC - Register Layout Typedef */ | ||
| 284 | typedef struct { | ||
| 285 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ | ||
| 286 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ | ||
| 287 | uint8_t RESERVED_0[8]; | ||
| 288 | __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ | ||
| 289 | __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ | ||
| 290 | __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ | ||
| 291 | __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ | ||
| 292 | __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ | ||
| 293 | __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ | ||
| 294 | uint8_t RESERVED_1[12]; | ||
| 295 | __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ | ||
| 296 | __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ | ||
| 297 | uint8_t RESERVED_2[4]; | ||
| 298 | __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ | ||
| 299 | uint8_t RESERVED_3[92]; | ||
| 300 | __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ | ||
| 301 | __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ | ||
| 302 | uint8_t RESERVED_4[8]; | ||
| 303 | __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ | ||
| 304 | __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ | ||
| 305 | struct { /* offset: 0x100, array step: 0x8 */ | ||
| 306 | __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ | ||
| 307 | __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ | ||
| 308 | } CMD[15]; | ||
| 309 | uint8_t RESERVED_5[136]; | ||
| 310 | __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ | ||
| 311 | uint8_t RESERVED_6[240]; | ||
| 312 | __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ | ||
| 313 | uint8_t RESERVED_7[248]; | ||
| 314 | __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ | ||
| 315 | uint8_t RESERVED_8[124]; | ||
| 316 | __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ | ||
| 317 | uint8_t RESERVED_9[2680]; | ||
| 318 | __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ | ||
| 319 | } ADC_Type; | ||
| 320 | |||
| 321 | /* ---------------------------------------------------------------------------- | ||
| 322 | -- ADC Register Masks | ||
| 323 | ---------------------------------------------------------------------------- */ | ||
| 324 | |||
| 325 | /*! | ||
| 326 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 327 | * @{ | ||
| 328 | */ | ||
| 329 | |||
| 330 | /*! @name VERID - Version ID Register */ | ||
| 331 | /*! @{ */ | ||
| 332 | #define ADC_VERID_RES_MASK (0x1U) | ||
| 333 | #define ADC_VERID_RES_SHIFT (0U) | ||
| 334 | /*! RES - Resolution | ||
| 335 | * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. | ||
| 336 | * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. | ||
| 337 | */ | ||
| 338 | #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) | ||
| 339 | #define ADC_VERID_DIFFEN_MASK (0x2U) | ||
| 340 | #define ADC_VERID_DIFFEN_SHIFT (1U) | ||
| 341 | /*! DIFFEN - Differential Supported | ||
| 342 | * 0b0..Differential operation not supported. | ||
| 343 | * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. | ||
| 344 | */ | ||
| 345 | #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) | ||
| 346 | #define ADC_VERID_MVI_MASK (0x8U) | ||
| 347 | #define ADC_VERID_MVI_SHIFT (3U) | ||
| 348 | /*! MVI - Multi Vref Implemented | ||
| 349 | * 0b0..Single voltage reference high (VREFH) input supported. | ||
| 350 | * 0b1..Multiple voltage reference high (VREFH) inputs supported. | ||
| 351 | */ | ||
| 352 | #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) | ||
| 353 | #define ADC_VERID_CSW_MASK (0x70U) | ||
| 354 | #define ADC_VERID_CSW_SHIFT (4U) | ||
| 355 | /*! CSW - Channel Scale Width | ||
| 356 | * 0b000..Channel scaling not supported. | ||
| 357 | * 0b001..Channel scaling supported. 1-bit CSCALE control field. | ||
| 358 | * 0b110..Channel scaling supported. 6-bit CSCALE control field. | ||
| 359 | */ | ||
| 360 | #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) | ||
| 361 | #define ADC_VERID_VR1RNGI_MASK (0x100U) | ||
| 362 | #define ADC_VERID_VR1RNGI_SHIFT (8U) | ||
| 363 | /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented | ||
| 364 | * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. | ||
| 365 | * 0b1..Range control required. CFG[VREF1RNG] is implemented. | ||
| 366 | */ | ||
| 367 | #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) | ||
| 368 | #define ADC_VERID_IADCKI_MASK (0x200U) | ||
| 369 | #define ADC_VERID_IADCKI_SHIFT (9U) | ||
| 370 | /*! IADCKI - Internal ADC Clock implemented | ||
| 371 | * 0b0..Internal clock source not implemented. | ||
| 372 | * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. | ||
| 373 | */ | ||
| 374 | #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) | ||
| 375 | #define ADC_VERID_CALOFSI_MASK (0x400U) | ||
| 376 | #define ADC_VERID_CALOFSI_SHIFT (10U) | ||
| 377 | /*! CALOFSI - Calibration Function Implemented | ||
| 378 | * 0b0..Calibration Not Implemented. | ||
| 379 | * 0b1..Calibration Implemented. | ||
| 380 | */ | ||
| 381 | #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) | ||
| 382 | #define ADC_VERID_NUM_SEC_MASK (0x800U) | ||
| 383 | #define ADC_VERID_NUM_SEC_SHIFT (11U) | ||
| 384 | /*! NUM_SEC - Number of Single Ended Outputs Supported | ||
| 385 | * 0b0..This design supports one single ended conversion at a time. | ||
| 386 | * 0b1..This design supports two simultanious single ended conversions. | ||
| 387 | */ | ||
| 388 | #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) | ||
| 389 | #define ADC_VERID_NUM_FIFO_MASK (0x7000U) | ||
| 390 | #define ADC_VERID_NUM_FIFO_SHIFT (12U) | ||
| 391 | /*! NUM_FIFO - Number of FIFOs | ||
| 392 | * 0b000..N/A | ||
| 393 | * 0b001..This design supports one result FIFO. | ||
| 394 | * 0b010..This design supports two result FIFOs. | ||
| 395 | * 0b011..This design supports three result FIFOs. | ||
| 396 | * 0b100..This design supports four result FIFOs. | ||
| 397 | */ | ||
| 398 | #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) | ||
| 399 | #define ADC_VERID_MINOR_MASK (0xFF0000U) | ||
| 400 | #define ADC_VERID_MINOR_SHIFT (16U) | ||
| 401 | /*! MINOR - Minor Version Number | ||
| 402 | */ | ||
| 403 | #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) | ||
| 404 | #define ADC_VERID_MAJOR_MASK (0xFF000000U) | ||
| 405 | #define ADC_VERID_MAJOR_SHIFT (24U) | ||
| 406 | /*! MAJOR - Major Version Number | ||
| 407 | */ | ||
| 408 | #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) | ||
| 409 | /*! @} */ | ||
| 410 | |||
| 411 | /*! @name PARAM - Parameter Register */ | ||
| 412 | /*! @{ */ | ||
| 413 | #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) | ||
| 414 | #define ADC_PARAM_TRIG_NUM_SHIFT (0U) | ||
| 415 | /*! TRIG_NUM - Trigger Number | ||
| 416 | */ | ||
| 417 | #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) | ||
| 418 | #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) | ||
| 419 | #define ADC_PARAM_FIFOSIZE_SHIFT (8U) | ||
| 420 | /*! FIFOSIZE - Result FIFO Depth | ||
| 421 | * 0b00000001..Result FIFO depth = 1 dataword. | ||
| 422 | * 0b00000100..Result FIFO depth = 4 datawords. | ||
| 423 | * 0b00001000..Result FIFO depth = 8 datawords. | ||
| 424 | * 0b00010000..Result FIFO depth = 16 datawords. | ||
| 425 | * 0b00100000..Result FIFO depth = 32 datawords. | ||
| 426 | * 0b01000000..Result FIFO depth = 64 datawords. | ||
| 427 | */ | ||
| 428 | #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) | ||
| 429 | #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) | ||
| 430 | #define ADC_PARAM_CV_NUM_SHIFT (16U) | ||
| 431 | /*! CV_NUM - Compare Value Number | ||
| 432 | */ | ||
| 433 | #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) | ||
| 434 | #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) | ||
| 435 | #define ADC_PARAM_CMD_NUM_SHIFT (24U) | ||
| 436 | /*! CMD_NUM - Command Buffer Number | ||
| 437 | */ | ||
| 438 | #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) | ||
| 439 | /*! @} */ | ||
| 440 | |||
| 441 | /*! @name CTRL - ADC Control Register */ | ||
| 442 | /*! @{ */ | ||
| 443 | #define ADC_CTRL_ADCEN_MASK (0x1U) | ||
| 444 | #define ADC_CTRL_ADCEN_SHIFT (0U) | ||
| 445 | /*! ADCEN - ADC Enable | ||
| 446 | * 0b0..ADC is disabled. | ||
| 447 | * 0b1..ADC is enabled. | ||
| 448 | */ | ||
| 449 | #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) | ||
| 450 | #define ADC_CTRL_RST_MASK (0x2U) | ||
| 451 | #define ADC_CTRL_RST_SHIFT (1U) | ||
| 452 | /*! RST - Software Reset | ||
| 453 | * 0b0..ADC logic is not reset. | ||
| 454 | * 0b1..ADC logic is reset. | ||
| 455 | */ | ||
| 456 | #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) | ||
| 457 | #define ADC_CTRL_DOZEN_MASK (0x4U) | ||
| 458 | #define ADC_CTRL_DOZEN_SHIFT (2U) | ||
| 459 | /*! DOZEN - Doze Enable | ||
| 460 | * 0b0..ADC is enabled in Doze mode. | ||
| 461 | * 0b1..ADC is disabled in Doze mode. | ||
| 462 | */ | ||
| 463 | #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) | ||
| 464 | #define ADC_CTRL_CAL_REQ_MASK (0x8U) | ||
| 465 | #define ADC_CTRL_CAL_REQ_SHIFT (3U) | ||
| 466 | /*! CAL_REQ - Auto-Calibration Request | ||
| 467 | * 0b0..No request for auto-calibration has been made. | ||
| 468 | * 0b1..A request for auto-calibration has been made | ||
| 469 | */ | ||
| 470 | #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) | ||
| 471 | #define ADC_CTRL_CALOFS_MASK (0x10U) | ||
| 472 | #define ADC_CTRL_CALOFS_SHIFT (4U) | ||
| 473 | /*! CALOFS - Configure for offset calibration function | ||
| 474 | * 0b0..Calibration function disabled | ||
| 475 | * 0b1..Request for offset calibration function | ||
| 476 | */ | ||
| 477 | #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) | ||
| 478 | #define ADC_CTRL_RSTFIFO0_MASK (0x100U) | ||
| 479 | #define ADC_CTRL_RSTFIFO0_SHIFT (8U) | ||
| 480 | /*! RSTFIFO0 - Reset FIFO 0 | ||
| 481 | * 0b0..No effect. | ||
| 482 | * 0b1..FIFO 0 is reset. | ||
| 483 | */ | ||
| 484 | #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) | ||
| 485 | #define ADC_CTRL_RSTFIFO1_MASK (0x200U) | ||
| 486 | #define ADC_CTRL_RSTFIFO1_SHIFT (9U) | ||
| 487 | /*! RSTFIFO1 - Reset FIFO 1 | ||
| 488 | * 0b0..No effect. | ||
| 489 | * 0b1..FIFO 1 is reset. | ||
| 490 | */ | ||
| 491 | #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) | ||
| 492 | #define ADC_CTRL_CAL_AVGS_MASK (0x70000U) | ||
| 493 | #define ADC_CTRL_CAL_AVGS_SHIFT (16U) | ||
| 494 | /*! CAL_AVGS - Auto-Calibration Averages | ||
| 495 | * 0b000..Single conversion. | ||
| 496 | * 0b001..2 conversions averaged. | ||
| 497 | * 0b010..4 conversions averaged. | ||
| 498 | * 0b011..8 conversions averaged. | ||
| 499 | * 0b100..16 conversions averaged. | ||
| 500 | * 0b101..32 conversions averaged. | ||
| 501 | * 0b110..64 conversions averaged. | ||
| 502 | * 0b111..128 conversions averaged. | ||
| 503 | */ | ||
| 504 | #define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) | ||
| 505 | /*! @} */ | ||
| 506 | |||
| 507 | /*! @name STAT - ADC Status Register */ | ||
| 508 | /*! @{ */ | ||
| 509 | #define ADC_STAT_RDY0_MASK (0x1U) | ||
| 510 | #define ADC_STAT_RDY0_SHIFT (0U) | ||
| 511 | /*! RDY0 - Result FIFO 0 Ready Flag | ||
| 512 | * 0b0..Result FIFO 0 data level not above watermark level. | ||
| 513 | * 0b1..Result FIFO 0 holding data above watermark level. | ||
| 514 | */ | ||
| 515 | #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) | ||
| 516 | #define ADC_STAT_FOF0_MASK (0x2U) | ||
| 517 | #define ADC_STAT_FOF0_SHIFT (1U) | ||
| 518 | /*! FOF0 - Result FIFO 0 Overflow Flag | ||
| 519 | * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 520 | * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 521 | */ | ||
| 522 | #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) | ||
| 523 | #define ADC_STAT_RDY1_MASK (0x4U) | ||
| 524 | #define ADC_STAT_RDY1_SHIFT (2U) | ||
| 525 | /*! RDY1 - Result FIFO1 Ready Flag | ||
| 526 | * 0b0..Result FIFO1 data level not above watermark level. | ||
| 527 | * 0b1..Result FIFO1 holding data above watermark level. | ||
| 528 | */ | ||
| 529 | #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) | ||
| 530 | #define ADC_STAT_FOF1_MASK (0x8U) | ||
| 531 | #define ADC_STAT_FOF1_SHIFT (3U) | ||
| 532 | /*! FOF1 - Result FIFO1 Overflow Flag | ||
| 533 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 534 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 535 | */ | ||
| 536 | #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) | ||
| 537 | #define ADC_STAT_TEXC_INT_MASK (0x100U) | ||
| 538 | #define ADC_STAT_TEXC_INT_SHIFT (8U) | ||
| 539 | /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception | ||
| 540 | * 0b0..No trigger exceptions have occurred. | ||
| 541 | * 0b1..A trigger exception has occurred and is pending acknowledgement. | ||
| 542 | */ | ||
| 543 | #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) | ||
| 544 | #define ADC_STAT_TCOMP_INT_MASK (0x200U) | ||
| 545 | #define ADC_STAT_TCOMP_INT_SHIFT (9U) | ||
| 546 | /*! TCOMP_INT - Interrupt Flag For Trigger Completion | ||
| 547 | * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. | ||
| 548 | * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. | ||
| 549 | */ | ||
| 550 | #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) | ||
| 551 | #define ADC_STAT_CAL_RDY_MASK (0x400U) | ||
| 552 | #define ADC_STAT_CAL_RDY_SHIFT (10U) | ||
| 553 | /*! CAL_RDY - Calibration Ready | ||
| 554 | * 0b0..Calibration is incomplete or hasn't been ran. | ||
| 555 | * 0b1..The ADC is calibrated. | ||
| 556 | */ | ||
| 557 | #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) | ||
| 558 | #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) | ||
| 559 | #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) | ||
| 560 | /*! ADC_ACTIVE - ADC Active | ||
| 561 | * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. | ||
| 562 | * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. | ||
| 563 | */ | ||
| 564 | #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) | ||
| 565 | #define ADC_STAT_TRGACT_MASK (0xF0000U) | ||
| 566 | #define ADC_STAT_TRGACT_SHIFT (16U) | ||
| 567 | /*! TRGACT - Trigger Active | ||
| 568 | * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. | ||
| 569 | * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. | ||
| 570 | * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. | ||
| 571 | * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. | ||
| 572 | */ | ||
| 573 | #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) | ||
| 574 | #define ADC_STAT_CMDACT_MASK (0xF000000U) | ||
| 575 | #define ADC_STAT_CMDACT_SHIFT (24U) | ||
| 576 | /*! CMDACT - Command Active | ||
| 577 | * 0b0000..No command is currently in progress. | ||
| 578 | * 0b0001..Command 1 currently being executed. | ||
| 579 | * 0b0010..Command 2 currently being executed. | ||
| 580 | * 0b0011-0b1111..Associated command number is currently being executed. | ||
| 581 | */ | ||
| 582 | #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) | ||
| 583 | /*! @} */ | ||
| 584 | |||
| 585 | /*! @name IE - Interrupt Enable Register */ | ||
| 586 | /*! @{ */ | ||
| 587 | #define ADC_IE_FWMIE0_MASK (0x1U) | ||
| 588 | #define ADC_IE_FWMIE0_SHIFT (0U) | ||
| 589 | /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable | ||
| 590 | * 0b0..FIFO 0 watermark interrupts are not enabled. | ||
| 591 | * 0b1..FIFO 0 watermark interrupts are enabled. | ||
| 592 | */ | ||
| 593 | #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) | ||
| 594 | #define ADC_IE_FOFIE0_MASK (0x2U) | ||
| 595 | #define ADC_IE_FOFIE0_SHIFT (1U) | ||
| 596 | /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable | ||
| 597 | * 0b0..FIFO 0 overflow interrupts are not enabled. | ||
| 598 | * 0b1..FIFO 0 overflow interrupts are enabled. | ||
| 599 | */ | ||
| 600 | #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) | ||
| 601 | #define ADC_IE_FWMIE1_MASK (0x4U) | ||
| 602 | #define ADC_IE_FWMIE1_SHIFT (2U) | ||
| 603 | /*! FWMIE1 - FIFO1 Watermark Interrupt Enable | ||
| 604 | * 0b0..FIFO1 watermark interrupts are not enabled. | ||
| 605 | * 0b1..FIFO1 watermark interrupts are enabled. | ||
| 606 | */ | ||
| 607 | #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) | ||
| 608 | #define ADC_IE_FOFIE1_MASK (0x8U) | ||
| 609 | #define ADC_IE_FOFIE1_SHIFT (3U) | ||
| 610 | /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable | ||
| 611 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 612 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 613 | */ | ||
| 614 | #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) | ||
| 615 | #define ADC_IE_TEXC_IE_MASK (0x100U) | ||
| 616 | #define ADC_IE_TEXC_IE_SHIFT (8U) | ||
| 617 | /*! TEXC_IE - Trigger Exception Interrupt Enable | ||
| 618 | * 0b0..Trigger exception interrupts are disabled. | ||
| 619 | * 0b1..Trigger exception interrupts are enabled. | ||
| 620 | */ | ||
| 621 | #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) | ||
| 622 | #define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) | ||
| 623 | #define ADC_IE_TCOMP_IE_SHIFT (16U) | ||
| 624 | /*! TCOMP_IE - Trigger Completion Interrupt Enable | ||
| 625 | * 0b0000000000000000..Trigger completion interrupts are disabled. | ||
| 626 | * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. | ||
| 627 | * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. | ||
| 628 | * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. | ||
| 629 | * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. | ||
| 630 | */ | ||
| 631 | #define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) | ||
| 632 | /*! @} */ | ||
| 633 | |||
| 634 | /*! @name DE - DMA Enable Register */ | ||
| 635 | /*! @{ */ | ||
| 636 | #define ADC_DE_FWMDE0_MASK (0x1U) | ||
| 637 | #define ADC_DE_FWMDE0_SHIFT (0U) | ||
| 638 | /*! FWMDE0 - FIFO 0 Watermark DMA Enable | ||
| 639 | * 0b0..DMA request disabled. | ||
| 640 | * 0b1..DMA request enabled. | ||
| 641 | */ | ||
| 642 | #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) | ||
| 643 | #define ADC_DE_FWMDE1_MASK (0x2U) | ||
| 644 | #define ADC_DE_FWMDE1_SHIFT (1U) | ||
| 645 | /*! FWMDE1 - FIFO1 Watermark DMA Enable | ||
| 646 | * 0b0..DMA request disabled. | ||
| 647 | * 0b1..DMA request enabled. | ||
| 648 | */ | ||
| 649 | #define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) | ||
| 650 | /*! @} */ | ||
| 651 | |||
| 652 | /*! @name CFG - ADC Configuration Register */ | ||
| 653 | /*! @{ */ | ||
| 654 | #define ADC_CFG_TPRICTRL_MASK (0x3U) | ||
| 655 | #define ADC_CFG_TPRICTRL_SHIFT (0U) | ||
| 656 | /*! TPRICTRL - ADC trigger priority control | ||
| 657 | * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted | ||
| 658 | * and the new command specified by the trigger is started. | ||
| 659 | * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after | ||
| 660 | * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. | ||
| 661 | * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. | ||
| 662 | * 0b10..If a higher priority trigger is received during command processing, the current command will be | ||
| 663 | * completed (averaging, looping, compare) before servicing the higher priority trigger. | ||
| 664 | * 0b11..RESERVED | ||
| 665 | */ | ||
| 666 | #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) | ||
| 667 | #define ADC_CFG_PWRSEL_MASK (0x30U) | ||
| 668 | #define ADC_CFG_PWRSEL_SHIFT (4U) | ||
| 669 | /*! PWRSEL - Power Configuration Select | ||
| 670 | * 0b00..Lowest power setting. | ||
| 671 | * 0b01..Higher power setting than 0b0. | ||
| 672 | * 0b10..Higher power setting than 0b1. | ||
| 673 | * 0b11..Highest power setting. | ||
| 674 | */ | ||
| 675 | #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) | ||
| 676 | #define ADC_CFG_REFSEL_MASK (0xC0U) | ||
| 677 | #define ADC_CFG_REFSEL_SHIFT (6U) | ||
| 678 | /*! REFSEL - Voltage Reference Selection | ||
| 679 | * 0b00..(Default) Option 1 setting. | ||
| 680 | * 0b01..Option 2 setting. | ||
| 681 | * 0b10..Option 3 setting. | ||
| 682 | * 0b11..Reserved | ||
| 683 | */ | ||
| 684 | #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) | ||
| 685 | #define ADC_CFG_TRES_MASK (0x100U) | ||
| 686 | #define ADC_CFG_TRES_SHIFT (8U) | ||
| 687 | /*! TRES - Trigger Resume Enable | ||
| 688 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. | ||
| 689 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. | ||
| 690 | */ | ||
| 691 | #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) | ||
| 692 | #define ADC_CFG_TCMDRES_MASK (0x200U) | ||
| 693 | #define ADC_CFG_TCMDRES_SHIFT (9U) | ||
| 694 | /*! TCMDRES - Trigger Command Resume | ||
| 695 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. | ||
| 696 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. | ||
| 697 | */ | ||
| 698 | #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) | ||
| 699 | #define ADC_CFG_HPT_EXDI_MASK (0x400U) | ||
| 700 | #define ADC_CFG_HPT_EXDI_SHIFT (10U) | ||
| 701 | /*! HPT_EXDI - High Priority Trigger Exception Disable | ||
| 702 | * 0b0..High priority trigger exceptions are enabled. | ||
| 703 | * 0b1..High priority trigger exceptions are disabled. | ||
| 704 | */ | ||
| 705 | #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) | ||
| 706 | #define ADC_CFG_PUDLY_MASK (0xFF0000U) | ||
| 707 | #define ADC_CFG_PUDLY_SHIFT (16U) | ||
| 708 | /*! PUDLY - Power Up Delay | ||
| 709 | */ | ||
| 710 | #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) | ||
| 711 | #define ADC_CFG_PWREN_MASK (0x10000000U) | ||
| 712 | #define ADC_CFG_PWREN_SHIFT (28U) | ||
| 713 | /*! PWREN - ADC Analog Pre-Enable | ||
| 714 | * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. | ||
| 715 | * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost | ||
| 716 | * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN | ||
| 717 | * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. | ||
| 718 | * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be | ||
| 719 | * executed. | ||
| 720 | */ | ||
| 721 | #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) | ||
| 722 | /*! @} */ | ||
| 723 | |||
| 724 | /*! @name PAUSE - ADC Pause Register */ | ||
| 725 | /*! @{ */ | ||
| 726 | #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) | ||
| 727 | #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) | ||
| 728 | /*! PAUSEDLY - Pause Delay | ||
| 729 | */ | ||
| 730 | #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) | ||
| 731 | #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) | ||
| 732 | #define ADC_PAUSE_PAUSEEN_SHIFT (31U) | ||
| 733 | /*! PAUSEEN - PAUSE Option Enable | ||
| 734 | * 0b0..Pause operation disabled | ||
| 735 | * 0b1..Pause operation enabled | ||
| 736 | */ | ||
| 737 | #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) | ||
| 738 | /*! @} */ | ||
| 739 | |||
| 740 | /*! @name SWTRIG - Software Trigger Register */ | ||
| 741 | /*! @{ */ | ||
| 742 | #define ADC_SWTRIG_SWT0_MASK (0x1U) | ||
| 743 | #define ADC_SWTRIG_SWT0_SHIFT (0U) | ||
| 744 | /*! SWT0 - Software trigger 0 event | ||
| 745 | * 0b0..No trigger 0 event generated. | ||
| 746 | * 0b1..Trigger 0 event generated. | ||
| 747 | */ | ||
| 748 | #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) | ||
| 749 | #define ADC_SWTRIG_SWT1_MASK (0x2U) | ||
| 750 | #define ADC_SWTRIG_SWT1_SHIFT (1U) | ||
| 751 | /*! SWT1 - Software trigger 1 event | ||
| 752 | * 0b0..No trigger 1 event generated. | ||
| 753 | * 0b1..Trigger 1 event generated. | ||
| 754 | */ | ||
| 755 | #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) | ||
| 756 | #define ADC_SWTRIG_SWT2_MASK (0x4U) | ||
| 757 | #define ADC_SWTRIG_SWT2_SHIFT (2U) | ||
| 758 | /*! SWT2 - Software trigger 2 event | ||
| 759 | * 0b0..No trigger 2 event generated. | ||
| 760 | * 0b1..Trigger 2 event generated. | ||
| 761 | */ | ||
| 762 | #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) | ||
| 763 | #define ADC_SWTRIG_SWT3_MASK (0x8U) | ||
| 764 | #define ADC_SWTRIG_SWT3_SHIFT (3U) | ||
| 765 | /*! SWT3 - Software trigger 3 event | ||
| 766 | * 0b0..No trigger 3 event generated. | ||
| 767 | * 0b1..Trigger 3 event generated. | ||
| 768 | */ | ||
| 769 | #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) | ||
| 770 | #define ADC_SWTRIG_SWT4_MASK (0x10U) | ||
| 771 | #define ADC_SWTRIG_SWT4_SHIFT (4U) | ||
| 772 | /*! SWT4 - Software trigger 4 event | ||
| 773 | * 0b0..No trigger 4 event generated. | ||
| 774 | * 0b1..Trigger 4 event generated. | ||
| 775 | */ | ||
| 776 | #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) | ||
| 777 | #define ADC_SWTRIG_SWT5_MASK (0x20U) | ||
| 778 | #define ADC_SWTRIG_SWT5_SHIFT (5U) | ||
| 779 | /*! SWT5 - Software trigger 5 event | ||
| 780 | * 0b0..No trigger 5 event generated. | ||
| 781 | * 0b1..Trigger 5 event generated. | ||
| 782 | */ | ||
| 783 | #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) | ||
| 784 | #define ADC_SWTRIG_SWT6_MASK (0x40U) | ||
| 785 | #define ADC_SWTRIG_SWT6_SHIFT (6U) | ||
| 786 | /*! SWT6 - Software trigger 6 event | ||
| 787 | * 0b0..No trigger 6 event generated. | ||
| 788 | * 0b1..Trigger 6 event generated. | ||
| 789 | */ | ||
| 790 | #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) | ||
| 791 | #define ADC_SWTRIG_SWT7_MASK (0x80U) | ||
| 792 | #define ADC_SWTRIG_SWT7_SHIFT (7U) | ||
| 793 | /*! SWT7 - Software trigger 7 event | ||
| 794 | * 0b0..No trigger 7 event generated. | ||
| 795 | * 0b1..Trigger 7 event generated. | ||
| 796 | */ | ||
| 797 | #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) | ||
| 798 | #define ADC_SWTRIG_SWT8_MASK (0x100U) | ||
| 799 | #define ADC_SWTRIG_SWT8_SHIFT (8U) | ||
| 800 | /*! SWT8 - Software trigger 8 event | ||
| 801 | * 0b0..No trigger 8 event generated. | ||
| 802 | * 0b1..Trigger 8 event generated. | ||
| 803 | */ | ||
| 804 | #define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) | ||
| 805 | #define ADC_SWTRIG_SWT9_MASK (0x200U) | ||
| 806 | #define ADC_SWTRIG_SWT9_SHIFT (9U) | ||
| 807 | /*! SWT9 - Software trigger 9 event | ||
| 808 | * 0b0..No trigger 9 event generated. | ||
| 809 | * 0b1..Trigger 9 event generated. | ||
| 810 | */ | ||
| 811 | #define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) | ||
| 812 | #define ADC_SWTRIG_SWT10_MASK (0x400U) | ||
| 813 | #define ADC_SWTRIG_SWT10_SHIFT (10U) | ||
| 814 | /*! SWT10 - Software trigger 10 event | ||
| 815 | * 0b0..No trigger 10 event generated. | ||
| 816 | * 0b1..Trigger 10 event generated. | ||
| 817 | */ | ||
| 818 | #define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) | ||
| 819 | #define ADC_SWTRIG_SWT11_MASK (0x800U) | ||
| 820 | #define ADC_SWTRIG_SWT11_SHIFT (11U) | ||
| 821 | /*! SWT11 - Software trigger 11 event | ||
| 822 | * 0b0..No trigger 11 event generated. | ||
| 823 | * 0b1..Trigger 11 event generated. | ||
| 824 | */ | ||
| 825 | #define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) | ||
| 826 | #define ADC_SWTRIG_SWT12_MASK (0x1000U) | ||
| 827 | #define ADC_SWTRIG_SWT12_SHIFT (12U) | ||
| 828 | /*! SWT12 - Software trigger 12 event | ||
| 829 | * 0b0..No trigger 12 event generated. | ||
| 830 | * 0b1..Trigger 12 event generated. | ||
| 831 | */ | ||
| 832 | #define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) | ||
| 833 | #define ADC_SWTRIG_SWT13_MASK (0x2000U) | ||
| 834 | #define ADC_SWTRIG_SWT13_SHIFT (13U) | ||
| 835 | /*! SWT13 - Software trigger 13 event | ||
| 836 | * 0b0..No trigger 13 event generated. | ||
| 837 | * 0b1..Trigger 13 event generated. | ||
| 838 | */ | ||
| 839 | #define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) | ||
| 840 | #define ADC_SWTRIG_SWT14_MASK (0x4000U) | ||
| 841 | #define ADC_SWTRIG_SWT14_SHIFT (14U) | ||
| 842 | /*! SWT14 - Software trigger 14 event | ||
| 843 | * 0b0..No trigger 14 event generated. | ||
| 844 | * 0b1..Trigger 14 event generated. | ||
| 845 | */ | ||
| 846 | #define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) | ||
| 847 | #define ADC_SWTRIG_SWT15_MASK (0x8000U) | ||
| 848 | #define ADC_SWTRIG_SWT15_SHIFT (15U) | ||
| 849 | /*! SWT15 - Software trigger 15 event | ||
| 850 | * 0b0..No trigger 15 event generated. | ||
| 851 | * 0b1..Trigger 15 event generated. | ||
| 852 | */ | ||
| 853 | #define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) | ||
| 854 | /*! @} */ | ||
| 855 | |||
| 856 | /*! @name TSTAT - Trigger Status Register */ | ||
| 857 | /*! @{ */ | ||
| 858 | #define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) | ||
| 859 | #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) | ||
| 860 | /*! TEXC_NUM - Trigger Exception Number | ||
| 861 | * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. | ||
| 862 | * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. | ||
| 863 | * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. | ||
| 864 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. | ||
| 865 | * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. | ||
| 866 | */ | ||
| 867 | #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) | ||
| 868 | #define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) | ||
| 869 | #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) | ||
| 870 | /*! TCOMP_FLAG - Trigger Completion Flag | ||
| 871 | * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. | ||
| 872 | * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. | ||
| 873 | * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. | ||
| 874 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. | ||
| 875 | * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. | ||
| 876 | */ | ||
| 877 | #define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) | ||
| 878 | /*! @} */ | ||
| 879 | |||
| 880 | /*! @name OFSTRIM - ADC Offset Trim Register */ | ||
| 881 | /*! @{ */ | ||
| 882 | #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) | ||
| 883 | #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) | ||
| 884 | /*! OFSTRIM_A - Trim for offset | ||
| 885 | */ | ||
| 886 | #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) | ||
| 887 | #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) | ||
| 888 | #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) | ||
| 889 | /*! OFSTRIM_B - Trim for offset | ||
| 890 | */ | ||
| 891 | #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) | ||
| 892 | /*! @} */ | ||
| 893 | |||
| 894 | /*! @name TCTRL - Trigger Control Register */ | ||
| 895 | /*! @{ */ | ||
| 896 | #define ADC_TCTRL_HTEN_MASK (0x1U) | ||
| 897 | #define ADC_TCTRL_HTEN_SHIFT (0U) | ||
| 898 | /*! HTEN - Trigger enable | ||
| 899 | * 0b0..Hardware trigger source disabled | ||
| 900 | * 0b1..Hardware trigger source enabled | ||
| 901 | */ | ||
| 902 | #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) | ||
| 903 | #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) | ||
| 904 | #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) | ||
| 905 | /*! FIFO_SEL_A - SAR Result Destination For Channel A | ||
| 906 | * 0b0..Result written to FIFO 0 | ||
| 907 | * 0b1..Result written to FIFO 1 | ||
| 908 | */ | ||
| 909 | #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) | ||
| 910 | #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) | ||
| 911 | #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) | ||
| 912 | /*! FIFO_SEL_B - SAR Result Destination For Channel B | ||
| 913 | * 0b0..Result written to FIFO 0 | ||
| 914 | * 0b1..Result written to FIFO 1 | ||
| 915 | */ | ||
| 916 | #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) | ||
| 917 | #define ADC_TCTRL_TPRI_MASK (0xF00U) | ||
| 918 | #define ADC_TCTRL_TPRI_SHIFT (8U) | ||
| 919 | /*! TPRI - Trigger priority setting | ||
| 920 | * 0b0000..Set to highest priority, Level 1 | ||
| 921 | * 0b0001-0b1110..Set to corresponding priority level | ||
| 922 | * 0b1111..Set to lowest priority, Level 16 | ||
| 923 | */ | ||
| 924 | #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) | ||
| 925 | #define ADC_TCTRL_RSYNC_MASK (0x8000U) | ||
| 926 | #define ADC_TCTRL_RSYNC_SHIFT (15U) | ||
| 927 | /*! RSYNC - Trigger Resync | ||
| 928 | */ | ||
| 929 | #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) | ||
| 930 | #define ADC_TCTRL_TDLY_MASK (0xF0000U) | ||
| 931 | #define ADC_TCTRL_TDLY_SHIFT (16U) | ||
| 932 | /*! TDLY - Trigger delay select | ||
| 933 | */ | ||
| 934 | #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) | ||
| 935 | #define ADC_TCTRL_TCMD_MASK (0xF000000U) | ||
| 936 | #define ADC_TCTRL_TCMD_SHIFT (24U) | ||
| 937 | /*! TCMD - Trigger command select | ||
| 938 | * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. | ||
| 939 | * 0b0001..CMD1 is executed | ||
| 940 | * 0b0010-0b1110..Corresponding CMD is executed | ||
| 941 | * 0b1111..CMD15 is executed | ||
| 942 | */ | ||
| 943 | #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) | ||
| 944 | /*! @} */ | ||
| 945 | |||
| 946 | /* The count of ADC_TCTRL */ | ||
| 947 | #define ADC_TCTRL_COUNT (16U) | ||
| 948 | |||
| 949 | /*! @name FCTRL - FIFO Control Register */ | ||
| 950 | /*! @{ */ | ||
| 951 | #define ADC_FCTRL_FCOUNT_MASK (0x1FU) | ||
| 952 | #define ADC_FCTRL_FCOUNT_SHIFT (0U) | ||
| 953 | /*! FCOUNT - Result FIFO counter | ||
| 954 | */ | ||
| 955 | #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) | ||
| 956 | #define ADC_FCTRL_FWMARK_MASK (0xF0000U) | ||
| 957 | #define ADC_FCTRL_FWMARK_SHIFT (16U) | ||
| 958 | /*! FWMARK - Watermark level selection | ||
| 959 | */ | ||
| 960 | #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) | ||
| 961 | /*! @} */ | ||
| 962 | |||
| 963 | /* The count of ADC_FCTRL */ | ||
| 964 | #define ADC_FCTRL_COUNT (2U) | ||
| 965 | |||
| 966 | /*! @name GCC - Gain Calibration Control */ | ||
| 967 | /*! @{ */ | ||
| 968 | #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) | ||
| 969 | #define ADC_GCC_GAIN_CAL_SHIFT (0U) | ||
| 970 | /*! GAIN_CAL - Gain Calibration Value | ||
| 971 | */ | ||
| 972 | #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) | ||
| 973 | #define ADC_GCC_RDY_MASK (0x1000000U) | ||
| 974 | #define ADC_GCC_RDY_SHIFT (24U) | ||
| 975 | /*! RDY - Gain Calibration Value Valid | ||
| 976 | * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. | ||
| 977 | * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. | ||
| 978 | */ | ||
| 979 | #define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) | ||
| 980 | /*! @} */ | ||
| 981 | |||
| 982 | /* The count of ADC_GCC */ | ||
| 983 | #define ADC_GCC_COUNT (2U) | ||
| 984 | |||
| 985 | /*! @name GCR - Gain Calculation Result */ | ||
| 986 | /*! @{ */ | ||
| 987 | #define ADC_GCR_GCALR_MASK (0xFFFFU) | ||
| 988 | #define ADC_GCR_GCALR_SHIFT (0U) | ||
| 989 | /*! GCALR - Gain Calculation Result | ||
| 990 | */ | ||
| 991 | #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) | ||
| 992 | #define ADC_GCR_RDY_MASK (0x1000000U) | ||
| 993 | #define ADC_GCR_RDY_SHIFT (24U) | ||
| 994 | /*! RDY - Gain Calculation Ready | ||
| 995 | * 0b0..The gain offset calculation value is invalid. | ||
| 996 | * 0b1..The gain calibration value is valid. | ||
| 997 | */ | ||
| 998 | #define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) | ||
| 999 | /*! @} */ | ||
| 1000 | |||
| 1001 | /* The count of ADC_GCR */ | ||
| 1002 | #define ADC_GCR_COUNT (2U) | ||
| 1003 | |||
| 1004 | /*! @name CMDL - ADC Command Low Buffer Register */ | ||
| 1005 | /*! @{ */ | ||
| 1006 | #define ADC_CMDL_ADCH_MASK (0x1FU) | ||
| 1007 | #define ADC_CMDL_ADCH_SHIFT (0U) | ||
| 1008 | /*! ADCH - Input channel select | ||
| 1009 | * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. | ||
| 1010 | * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. | ||
| 1011 | * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. | ||
| 1012 | * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. | ||
| 1013 | * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. | ||
| 1014 | * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. | ||
| 1015 | * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. | ||
| 1016 | */ | ||
| 1017 | #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) | ||
| 1018 | #define ADC_CMDL_CTYPE_MASK (0x60U) | ||
| 1019 | #define ADC_CMDL_CTYPE_SHIFT (5U) | ||
| 1020 | /*! CTYPE - Conversion Type | ||
| 1021 | * 0b00..Single-Ended Mode. Only A side channel is converted. | ||
| 1022 | * 0b01..Single-Ended Mode. Only B side channel is converted. | ||
| 1023 | * 0b10..Differential Mode. A-B. | ||
| 1024 | * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. | ||
| 1025 | */ | ||
| 1026 | #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) | ||
| 1027 | #define ADC_CMDL_MODE_MASK (0x80U) | ||
| 1028 | #define ADC_CMDL_MODE_SHIFT (7U) | ||
| 1029 | /*! MODE - Select resolution of conversions | ||
| 1030 | * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. | ||
| 1031 | * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. | ||
| 1032 | */ | ||
| 1033 | #define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) | ||
| 1034 | /*! @} */ | ||
| 1035 | |||
| 1036 | /* The count of ADC_CMDL */ | ||
| 1037 | #define ADC_CMDL_COUNT (15U) | ||
| 1038 | |||
| 1039 | /*! @name CMDH - ADC Command High Buffer Register */ | ||
| 1040 | /*! @{ */ | ||
| 1041 | #define ADC_CMDH_CMPEN_MASK (0x3U) | ||
| 1042 | #define ADC_CMDH_CMPEN_SHIFT (0U) | ||
| 1043 | /*! CMPEN - Compare Function Enable | ||
| 1044 | * 0b00..Compare disabled. | ||
| 1045 | * 0b01..Reserved | ||
| 1046 | * 0b10..Compare enabled. Store on true. | ||
| 1047 | * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. | ||
| 1048 | */ | ||
| 1049 | #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) | ||
| 1050 | #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) | ||
| 1051 | #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) | ||
| 1052 | /*! WAIT_TRIG - Wait for trigger assertion before execution. | ||
| 1053 | * 0b0..This command will be automatically executed. | ||
| 1054 | * 0b1..The active trigger must be asserted again before executing this command. | ||
| 1055 | */ | ||
| 1056 | #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) | ||
| 1057 | #define ADC_CMDH_LWI_MASK (0x80U) | ||
| 1058 | #define ADC_CMDH_LWI_SHIFT (7U) | ||
| 1059 | /*! LWI - Loop with Increment | ||
| 1060 | * 0b0..Auto channel increment disabled | ||
| 1061 | * 0b1..Auto channel increment enabled | ||
| 1062 | */ | ||
| 1063 | #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) | ||
| 1064 | #define ADC_CMDH_STS_MASK (0x700U) | ||
| 1065 | #define ADC_CMDH_STS_SHIFT (8U) | ||
| 1066 | /*! STS - Sample Time Select | ||
| 1067 | * 0b000..Minimum sample time of 3 ADCK cycles. | ||
| 1068 | * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. | ||
| 1069 | * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. | ||
| 1070 | * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. | ||
| 1071 | * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. | ||
| 1072 | * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. | ||
| 1073 | * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. | ||
| 1074 | * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. | ||
| 1075 | */ | ||
| 1076 | #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) | ||
| 1077 | #define ADC_CMDH_AVGS_MASK (0x7000U) | ||
| 1078 | #define ADC_CMDH_AVGS_SHIFT (12U) | ||
| 1079 | /*! AVGS - Hardware Average Select | ||
| 1080 | * 0b000..Single conversion. | ||
| 1081 | * 0b001..2 conversions averaged. | ||
| 1082 | * 0b010..4 conversions averaged. | ||
| 1083 | * 0b011..8 conversions averaged. | ||
| 1084 | * 0b100..16 conversions averaged. | ||
| 1085 | * 0b101..32 conversions averaged. | ||
| 1086 | * 0b110..64 conversions averaged. | ||
| 1087 | * 0b111..128 conversions averaged. | ||
| 1088 | */ | ||
| 1089 | #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) | ||
| 1090 | #define ADC_CMDH_LOOP_MASK (0xF0000U) | ||
| 1091 | #define ADC_CMDH_LOOP_SHIFT (16U) | ||
| 1092 | /*! LOOP - Loop Count Select | ||
| 1093 | * 0b0000..Looping not enabled. Command executes 1 time. | ||
| 1094 | * 0b0001..Loop 1 time. Command executes 2 times. | ||
| 1095 | * 0b0010..Loop 2 times. Command executes 3 times. | ||
| 1096 | * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. | ||
| 1097 | * 0b1111..Loop 15 times. Command executes 16 times. | ||
| 1098 | */ | ||
| 1099 | #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) | ||
| 1100 | #define ADC_CMDH_NEXT_MASK (0xF000000U) | ||
| 1101 | #define ADC_CMDH_NEXT_SHIFT (24U) | ||
| 1102 | /*! NEXT - Next Command Select | ||
| 1103 | * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority | ||
| 1104 | * trigger pending, begin command associated with lower priority trigger. | ||
| 1105 | * 0b0001..Select CMD1 command buffer register as next command. | ||
| 1106 | * 0b0010-0b1110..Select corresponding CMD command buffer register as next command | ||
| 1107 | * 0b1111..Select CMD15 command buffer register as next command. | ||
| 1108 | */ | ||
| 1109 | #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) | ||
| 1110 | /*! @} */ | ||
| 1111 | |||
| 1112 | /* The count of ADC_CMDH */ | ||
| 1113 | #define ADC_CMDH_COUNT (15U) | ||
| 1114 | |||
| 1115 | /*! @name CV - Compare Value Register */ | ||
| 1116 | /*! @{ */ | ||
| 1117 | #define ADC_CV_CVL_MASK (0xFFFFU) | ||
| 1118 | #define ADC_CV_CVL_SHIFT (0U) | ||
| 1119 | /*! CVL - Compare Value Low. | ||
| 1120 | */ | ||
| 1121 | #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) | ||
| 1122 | #define ADC_CV_CVH_MASK (0xFFFF0000U) | ||
| 1123 | #define ADC_CV_CVH_SHIFT (16U) | ||
| 1124 | /*! CVH - Compare Value High. | ||
| 1125 | */ | ||
| 1126 | #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) | ||
| 1127 | /*! @} */ | ||
| 1128 | |||
| 1129 | /* The count of ADC_CV */ | ||
| 1130 | #define ADC_CV_COUNT (4U) | ||
| 1131 | |||
| 1132 | /*! @name RESFIFO - ADC Data Result FIFO Register */ | ||
| 1133 | /*! @{ */ | ||
| 1134 | #define ADC_RESFIFO_D_MASK (0xFFFFU) | ||
| 1135 | #define ADC_RESFIFO_D_SHIFT (0U) | ||
| 1136 | /*! D - Data result | ||
| 1137 | */ | ||
| 1138 | #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) | ||
| 1139 | #define ADC_RESFIFO_TSRC_MASK (0xF0000U) | ||
| 1140 | #define ADC_RESFIFO_TSRC_SHIFT (16U) | ||
| 1141 | /*! TSRC - Trigger Source | ||
| 1142 | * 0b0000..Trigger source 0 initiated this conversion. | ||
| 1143 | * 0b0001..Trigger source 1 initiated this conversion. | ||
| 1144 | * 0b0010-0b1110..Corresponding trigger source initiated this conversion. | ||
| 1145 | * 0b1111..Trigger source 15 initiated this conversion. | ||
| 1146 | */ | ||
| 1147 | #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) | ||
| 1148 | #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) | ||
| 1149 | #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) | ||
| 1150 | /*! LOOPCNT - Loop count value | ||
| 1151 | * 0b0000..Result is from initial conversion in command. | ||
| 1152 | * 0b0001..Result is from second conversion in command. | ||
| 1153 | * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. | ||
| 1154 | * 0b1111..Result is from 16th conversion in command. | ||
| 1155 | */ | ||
| 1156 | #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) | ||
| 1157 | #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) | ||
| 1158 | #define ADC_RESFIFO_CMDSRC_SHIFT (24U) | ||
| 1159 | /*! CMDSRC - Command Buffer Source | ||
| 1160 | * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state | ||
| 1161 | * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. | ||
| 1162 | * 0b0001..CMD1 buffer used as control settings for this conversion. | ||
| 1163 | * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. | ||
| 1164 | * 0b1111..CMD15 buffer used as control settings for this conversion. | ||
| 1165 | */ | ||
| 1166 | #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) | ||
| 1167 | #define ADC_RESFIFO_VALID_MASK (0x80000000U) | ||
| 1168 | #define ADC_RESFIFO_VALID_SHIFT (31U) | ||
| 1169 | /*! VALID - FIFO entry is valid | ||
| 1170 | * 0b0..FIFO is empty. Discard any read from RESFIFO. | ||
| 1171 | * 0b1..FIFO record read from RESFIFO is valid. | ||
| 1172 | */ | ||
| 1173 | #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) | ||
| 1174 | /*! @} */ | ||
| 1175 | |||
| 1176 | /* The count of ADC_RESFIFO */ | ||
| 1177 | #define ADC_RESFIFO_COUNT (2U) | ||
| 1178 | |||
| 1179 | /*! @name CAL_GAR - Calibration General A-Side Registers */ | ||
| 1180 | /*! @{ */ | ||
| 1181 | #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) | ||
| 1182 | #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) | ||
| 1183 | /*! CAL_GAR_VAL - Calibration General A Side Register Element | ||
| 1184 | */ | ||
| 1185 | #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) | ||
| 1186 | /*! @} */ | ||
| 1187 | |||
| 1188 | /* The count of ADC_CAL_GAR */ | ||
| 1189 | #define ADC_CAL_GAR_COUNT (33U) | ||
| 1190 | |||
| 1191 | /*! @name CAL_GBR - Calibration General B-Side Registers */ | ||
| 1192 | /*! @{ */ | ||
| 1193 | #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) | ||
| 1194 | #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) | ||
| 1195 | /*! CAL_GBR_VAL - Calibration General B Side Register Element | ||
| 1196 | */ | ||
| 1197 | #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) | ||
| 1198 | /*! @} */ | ||
| 1199 | |||
| 1200 | /* The count of ADC_CAL_GBR */ | ||
| 1201 | #define ADC_CAL_GBR_COUNT (33U) | ||
| 1202 | |||
| 1203 | /*! @name TST - ADC Test Register */ | ||
| 1204 | /*! @{ */ | ||
| 1205 | #define ADC_TST_CST_LONG_MASK (0x1U) | ||
| 1206 | #define ADC_TST_CST_LONG_SHIFT (0U) | ||
| 1207 | /*! CST_LONG - Calibration Sample Time Long | ||
| 1208 | * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. | ||
| 1209 | * 0b1..Increased sample time. 67 ADCK cycles total sample time. | ||
| 1210 | */ | ||
| 1211 | #define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) | ||
| 1212 | #define ADC_TST_FOFFM_MASK (0x100U) | ||
| 1213 | #define ADC_TST_FOFFM_SHIFT (8U) | ||
| 1214 | /*! FOFFM - Force M-side positive offset | ||
| 1215 | * 0b0..Normal operation. No forced offset. | ||
| 1216 | * 0b1..Test configuration. Forced positive offset on MDAC. | ||
| 1217 | */ | ||
| 1218 | #define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) | ||
| 1219 | #define ADC_TST_FOFFP_MASK (0x200U) | ||
| 1220 | #define ADC_TST_FOFFP_SHIFT (9U) | ||
| 1221 | /*! FOFFP - Force P-side positive offset | ||
| 1222 | * 0b0..Normal operation. No forced offset. | ||
| 1223 | * 0b1..Test configuration. Forced positive offset on PDAC. | ||
| 1224 | */ | ||
| 1225 | #define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) | ||
| 1226 | #define ADC_TST_FOFFM2_MASK (0x400U) | ||
| 1227 | #define ADC_TST_FOFFM2_SHIFT (10U) | ||
| 1228 | /*! FOFFM2 - Force M-side negative offset | ||
| 1229 | * 0b0..Normal operation. No forced offset. | ||
| 1230 | * 0b1..Test configuration. Forced negative offset on MDAC. | ||
| 1231 | */ | ||
| 1232 | #define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) | ||
| 1233 | #define ADC_TST_FOFFP2_MASK (0x800U) | ||
| 1234 | #define ADC_TST_FOFFP2_SHIFT (11U) | ||
| 1235 | /*! FOFFP2 - Force P-side negative offset | ||
| 1236 | * 0b0..Normal operation. No forced offset. | ||
| 1237 | * 0b1..Test configuration. Forced negative offset on PDAC. | ||
| 1238 | */ | ||
| 1239 | #define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) | ||
| 1240 | #define ADC_TST_TESTEN_MASK (0x800000U) | ||
| 1241 | #define ADC_TST_TESTEN_SHIFT (23U) | ||
| 1242 | /*! TESTEN - Enable test configuration | ||
| 1243 | * 0b0..Normal operation. Test configuration not enabled. | ||
| 1244 | * 0b1..Hardware BIST Test in progress. | ||
| 1245 | */ | ||
| 1246 | #define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) | ||
| 1247 | /*! @} */ | ||
| 1248 | |||
| 1249 | |||
| 1250 | /*! | ||
| 1251 | * @} | ||
| 1252 | */ /* end of group ADC_Register_Masks */ | ||
| 1253 | |||
| 1254 | |||
| 1255 | /* ADC - Peripheral instance base addresses */ | ||
| 1256 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 1257 | /** Peripheral ADC0 base address */ | ||
| 1258 | #define ADC0_BASE (0x500A0000u) | ||
| 1259 | /** Peripheral ADC0 base address */ | ||
| 1260 | #define ADC0_BASE_NS (0x400A0000u) | ||
| 1261 | /** Peripheral ADC0 base pointer */ | ||
| 1262 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1263 | /** Peripheral ADC0 base pointer */ | ||
| 1264 | #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) | ||
| 1265 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1266 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1267 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1268 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1269 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1270 | #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } | ||
| 1271 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1272 | #define ADC_BASE_PTRS_NS { ADC0_NS } | ||
| 1273 | #else | ||
| 1274 | /** Peripheral ADC0 base address */ | ||
| 1275 | #define ADC0_BASE (0x400A0000u) | ||
| 1276 | /** Peripheral ADC0 base pointer */ | ||
| 1277 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1278 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1279 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1280 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1281 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1282 | #endif | ||
| 1283 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1284 | #define ADC_IRQS { ADC0_IRQn } | ||
| 1285 | |||
| 1286 | /*! | ||
| 1287 | * @} | ||
| 1288 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1289 | |||
| 1290 | |||
| 1291 | /* ---------------------------------------------------------------------------- | ||
| 1292 | -- AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1293 | ---------------------------------------------------------------------------- */ | ||
| 1294 | |||
| 1295 | /*! | ||
| 1296 | * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1297 | * @{ | ||
| 1298 | */ | ||
| 1299 | |||
| 1300 | /** AHB_SECURE_CTRL - Register Layout Typedef */ | ||
| 1301 | typedef struct { | ||
| 1302 | struct { /* offset: 0x0, array step: 0x30 */ | ||
| 1303 | __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ | ||
| 1304 | uint8_t RESERVED_0[12]; | ||
| 1305 | __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ | ||
| 1306 | uint8_t RESERVED_1[4]; | ||
| 1307 | __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ | ||
| 1308 | } SEC_CTRL_FLASH_ROM[1]; | ||
| 1309 | struct { /* offset: 0x30, array step: 0x14 */ | ||
| 1310 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ | ||
| 1311 | uint8_t RESERVED_0[12]; | ||
| 1312 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ | ||
| 1313 | } SEC_CTRL_RAMX[1]; | ||
| 1314 | uint8_t RESERVED_0[12]; | ||
| 1315 | struct { /* offset: 0x50, array step: 0x18 */ | ||
| 1316 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ | ||
| 1317 | uint8_t RESERVED_0[12]; | ||
| 1318 | __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ | ||
| 1319 | } SEC_CTRL_RAM0[1]; | ||
| 1320 | uint8_t RESERVED_1[8]; | ||
| 1321 | struct { /* offset: 0x70, array step: 0x18 */ | ||
| 1322 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ | ||
| 1323 | uint8_t RESERVED_0[12]; | ||
| 1324 | __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ | ||
| 1325 | } SEC_CTRL_RAM1[1]; | ||
| 1326 | uint8_t RESERVED_2[8]; | ||
| 1327 | struct { /* offset: 0x90, array step: 0x18 */ | ||
| 1328 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ | ||
| 1329 | uint8_t RESERVED_0[12]; | ||
| 1330 | __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ | ||
| 1331 | } SEC_CTRL_RAM2[1]; | ||
| 1332 | uint8_t RESERVED_3[8]; | ||
| 1333 | struct { /* offset: 0xB0, array step: 0x18 */ | ||
| 1334 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ | ||
| 1335 | uint8_t RESERVED_0[12]; | ||
| 1336 | __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ | ||
| 1337 | } SEC_CTRL_RAM3[1]; | ||
| 1338 | uint8_t RESERVED_4[8]; | ||
| 1339 | struct { /* offset: 0xD0, array step: 0x14 */ | ||
| 1340 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ | ||
| 1341 | uint8_t RESERVED_0[12]; | ||
| 1342 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ | ||
| 1343 | } SEC_CTRL_RAM4[1]; | ||
| 1344 | uint8_t RESERVED_5[12]; | ||
| 1345 | struct { /* offset: 0xF0, array step: 0x30 */ | ||
| 1346 | __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ | ||
| 1347 | uint8_t RESERVED_0[12]; | ||
| 1348 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ | ||
| 1349 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ | ||
| 1350 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ | ||
| 1351 | uint8_t RESERVED_1[4]; | ||
| 1352 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ | ||
| 1353 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ | ||
| 1354 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ | ||
| 1355 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ | ||
| 1356 | } SEC_CTRL_APB_BRIDGE[1]; | ||
| 1357 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ | ||
| 1358 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ | ||
| 1359 | uint8_t RESERVED_6[8]; | ||
| 1360 | __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ | ||
| 1361 | __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ | ||
| 1362 | uint8_t RESERVED_7[8]; | ||
| 1363 | struct { /* offset: 0x140, array step: 0x14 */ | ||
| 1364 | __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ | ||
| 1365 | __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ | ||
| 1366 | uint8_t RESERVED_0[8]; | ||
| 1367 | __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ | ||
| 1368 | } SEC_CTRL_AHB_PORT10[1]; | ||
| 1369 | uint8_t RESERVED_8[12]; | ||
| 1370 | struct { /* offset: 0x160, array step: 0x14 */ | ||
| 1371 | __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ | ||
| 1372 | uint8_t RESERVED_0[12]; | ||
| 1373 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ | ||
| 1374 | } SEC_CTRL_USB_HS[1]; | ||
| 1375 | uint8_t RESERVED_9[3212]; | ||
| 1376 | __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ | ||
| 1377 | uint8_t RESERVED_10[80]; | ||
| 1378 | __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ | ||
| 1379 | uint8_t RESERVED_11[80]; | ||
| 1380 | __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ | ||
| 1381 | uint8_t RESERVED_12[124]; | ||
| 1382 | __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ | ||
| 1383 | __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ | ||
| 1384 | uint8_t RESERVED_13[8]; | ||
| 1385 | __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ | ||
| 1386 | __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ | ||
| 1387 | uint8_t RESERVED_14[36]; | ||
| 1388 | __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ | ||
| 1389 | uint8_t RESERVED_15[16]; | ||
| 1390 | __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ | ||
| 1391 | __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ | ||
| 1392 | uint8_t RESERVED_16[20]; | ||
| 1393 | __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ | ||
| 1394 | __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ | ||
| 1395 | uint8_t RESERVED_17[4]; | ||
| 1396 | __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ | ||
| 1397 | __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ | ||
| 1398 | } AHB_SECURE_CTRL_Type; | ||
| 1399 | |||
| 1400 | /* ---------------------------------------------------------------------------- | ||
| 1401 | -- AHB_SECURE_CTRL Register Masks | ||
| 1402 | ---------------------------------------------------------------------------- */ | ||
| 1403 | |||
| 1404 | /*! | ||
| 1405 | * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks | ||
| 1406 | * @{ | ||
| 1407 | */ | ||
| 1408 | |||
| 1409 | /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ | ||
| 1410 | /*! @{ */ | ||
| 1411 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) | ||
| 1412 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) | ||
| 1413 | /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF | ||
| 1414 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1415 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1416 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1417 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1418 | */ | ||
| 1419 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) | ||
| 1420 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) | ||
| 1421 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) | ||
| 1422 | /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF | ||
| 1423 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1424 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1425 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1426 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1427 | */ | ||
| 1428 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) | ||
| 1429 | /*! @} */ | ||
| 1430 | |||
| 1431 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ | ||
| 1432 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) | ||
| 1433 | |||
| 1434 | /*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ | ||
| 1435 | /*! @{ */ | ||
| 1436 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1437 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1438 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1439 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1440 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1441 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1442 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1443 | */ | ||
| 1444 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) | ||
| 1445 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1446 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1447 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1448 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1449 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1450 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1451 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1452 | */ | ||
| 1453 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) | ||
| 1454 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1455 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1456 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1457 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1458 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1459 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1460 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1461 | */ | ||
| 1462 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) | ||
| 1463 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1464 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1465 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1466 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1467 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1468 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1469 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1470 | */ | ||
| 1471 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) | ||
| 1472 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1473 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1474 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1475 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1476 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1477 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1478 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1479 | */ | ||
| 1480 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) | ||
| 1481 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1482 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1483 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1484 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1485 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1486 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1487 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1488 | */ | ||
| 1489 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) | ||
| 1490 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1491 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1492 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1493 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1494 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1495 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1496 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1497 | */ | ||
| 1498 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) | ||
| 1499 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1500 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1501 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1502 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1503 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1504 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1505 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1506 | */ | ||
| 1507 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) | ||
| 1508 | /*! @} */ | ||
| 1509 | |||
| 1510 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1511 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) | ||
| 1512 | |||
| 1513 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1514 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) | ||
| 1515 | |||
| 1516 | /*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ | ||
| 1517 | /*! @{ */ | ||
| 1518 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1519 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1520 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1521 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1522 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1523 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1524 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1525 | */ | ||
| 1526 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) | ||
| 1527 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1528 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1529 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1530 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1531 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1532 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1533 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1534 | */ | ||
| 1535 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) | ||
| 1536 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1537 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1538 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1539 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1540 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1541 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1542 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1543 | */ | ||
| 1544 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) | ||
| 1545 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1546 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1547 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1548 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1549 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1550 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1551 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1552 | */ | ||
| 1553 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) | ||
| 1554 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1555 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1556 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1557 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1558 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1559 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1560 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1561 | */ | ||
| 1562 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) | ||
| 1563 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1564 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1565 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1566 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1567 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1568 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1569 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1570 | */ | ||
| 1571 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) | ||
| 1572 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1573 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1574 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1575 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1576 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1577 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1578 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1579 | */ | ||
| 1580 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) | ||
| 1581 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1582 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1583 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1584 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1585 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1586 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1587 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1588 | */ | ||
| 1589 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) | ||
| 1590 | /*! @} */ | ||
| 1591 | |||
| 1592 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1593 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) | ||
| 1594 | |||
| 1595 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1596 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) | ||
| 1597 | |||
| 1598 | /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ | ||
| 1599 | /*! @{ */ | ||
| 1600 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) | ||
| 1601 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) | ||
| 1602 | /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF | ||
| 1603 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1604 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1605 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1606 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1607 | */ | ||
| 1608 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) | ||
| 1609 | /*! @} */ | ||
| 1610 | |||
| 1611 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ | ||
| 1612 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) | ||
| 1613 | |||
| 1614 | /*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ | ||
| 1615 | /*! @{ */ | ||
| 1616 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1617 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1618 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1619 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1620 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1621 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1622 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1623 | */ | ||
| 1624 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) | ||
| 1625 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1626 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1627 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1628 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1629 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1630 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1631 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1632 | */ | ||
| 1633 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) | ||
| 1634 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1635 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1636 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1637 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1638 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1639 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1640 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1641 | */ | ||
| 1642 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) | ||
| 1643 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1644 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1645 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1646 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1647 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1648 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1649 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1650 | */ | ||
| 1651 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) | ||
| 1652 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1653 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1654 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1655 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1656 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1657 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1658 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1659 | */ | ||
| 1660 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) | ||
| 1661 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1662 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1663 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1664 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1665 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1666 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1667 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1668 | */ | ||
| 1669 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) | ||
| 1670 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1671 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1672 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1673 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1674 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1675 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1676 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1677 | */ | ||
| 1678 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) | ||
| 1679 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1680 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1681 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1682 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1683 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1684 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1685 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1686 | */ | ||
| 1687 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) | ||
| 1688 | /*! @} */ | ||
| 1689 | |||
| 1690 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1691 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) | ||
| 1692 | |||
| 1693 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1694 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) | ||
| 1695 | |||
| 1696 | /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ | ||
| 1697 | /*! @{ */ | ||
| 1698 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) | ||
| 1699 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) | ||
| 1700 | /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF | ||
| 1701 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1702 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1703 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1704 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1705 | */ | ||
| 1706 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) | ||
| 1707 | /*! @} */ | ||
| 1708 | |||
| 1709 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ | ||
| 1710 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) | ||
| 1711 | |||
| 1712 | /*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ | ||
| 1713 | /*! @{ */ | ||
| 1714 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1715 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1716 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1717 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1718 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1719 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1720 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1721 | */ | ||
| 1722 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) | ||
| 1723 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1724 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1725 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1726 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1727 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1728 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1729 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1730 | */ | ||
| 1731 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) | ||
| 1732 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1733 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1734 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1735 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1736 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1737 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1738 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1739 | */ | ||
| 1740 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) | ||
| 1741 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1742 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1743 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1744 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1745 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1746 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1747 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1748 | */ | ||
| 1749 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) | ||
| 1750 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1751 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1752 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1753 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1754 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1755 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1756 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1757 | */ | ||
| 1758 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) | ||
| 1759 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1760 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1761 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1762 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1763 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1764 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1765 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1766 | */ | ||
| 1767 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) | ||
| 1768 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1769 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1770 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1771 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1772 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1773 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1774 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1775 | */ | ||
| 1776 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) | ||
| 1777 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1778 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1779 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1780 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1781 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1782 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1783 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1784 | */ | ||
| 1785 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) | ||
| 1786 | /*! @} */ | ||
| 1787 | |||
| 1788 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1789 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) | ||
| 1790 | |||
| 1791 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1792 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) | ||
| 1793 | |||
| 1794 | /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ | ||
| 1795 | /*! @{ */ | ||
| 1796 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) | ||
| 1797 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) | ||
| 1798 | /*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 | ||
| 1799 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1800 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1801 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1802 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1803 | */ | ||
| 1804 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) | ||
| 1805 | /*! @} */ | ||
| 1806 | |||
| 1807 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ | ||
| 1808 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) | ||
| 1809 | |||
| 1810 | /*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ | ||
| 1811 | /*! @{ */ | ||
| 1812 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1813 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1814 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1815 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1816 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1817 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1818 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1819 | */ | ||
| 1820 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) | ||
| 1821 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1822 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1823 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1824 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1825 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1826 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1827 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1828 | */ | ||
| 1829 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) | ||
| 1830 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1831 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1832 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1833 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1834 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1835 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1836 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1837 | */ | ||
| 1838 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) | ||
| 1839 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1840 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1841 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1842 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1843 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1844 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1845 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1846 | */ | ||
| 1847 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) | ||
| 1848 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1849 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1850 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1851 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1852 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1853 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1854 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1855 | */ | ||
| 1856 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) | ||
| 1857 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1858 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1859 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1860 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1861 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1862 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1863 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1864 | */ | ||
| 1865 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) | ||
| 1866 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1867 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1868 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1869 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1870 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1871 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1872 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1873 | */ | ||
| 1874 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) | ||
| 1875 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1876 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1877 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1878 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1879 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1880 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1881 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1882 | */ | ||
| 1883 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) | ||
| 1884 | /*! @} */ | ||
| 1885 | |||
| 1886 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1887 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) | ||
| 1888 | |||
| 1889 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1890 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) | ||
| 1891 | |||
| 1892 | /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ | ||
| 1893 | /*! @{ */ | ||
| 1894 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) | ||
| 1895 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) | ||
| 1896 | /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF | ||
| 1897 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1898 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1899 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1900 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1901 | */ | ||
| 1902 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) | ||
| 1903 | /*! @} */ | ||
| 1904 | |||
| 1905 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ | ||
| 1906 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) | ||
| 1907 | |||
| 1908 | /*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ | ||
| 1909 | /*! @{ */ | ||
| 1910 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1911 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1912 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1913 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1914 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1915 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1916 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1917 | */ | ||
| 1918 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) | ||
| 1919 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1920 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1921 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1922 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1923 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1924 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1925 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1926 | */ | ||
| 1927 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) | ||
| 1928 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1929 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1930 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1931 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1932 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1933 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1934 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1935 | */ | ||
| 1936 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) | ||
| 1937 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1938 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1939 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1940 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1941 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1942 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1943 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1944 | */ | ||
| 1945 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) | ||
| 1946 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1947 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1948 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1949 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1950 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1951 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1952 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1953 | */ | ||
| 1954 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) | ||
| 1955 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1956 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1957 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1958 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1959 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1960 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1961 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1962 | */ | ||
| 1963 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) | ||
| 1964 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1965 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1966 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1967 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1968 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1969 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1970 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1971 | */ | ||
| 1972 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) | ||
| 1973 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1974 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1975 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1976 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1977 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1978 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1979 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1980 | */ | ||
| 1981 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) | ||
| 1982 | /*! @} */ | ||
| 1983 | |||
| 1984 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1985 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) | ||
| 1986 | |||
| 1987 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1988 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) | ||
| 1989 | |||
| 1990 | /*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ | ||
| 1991 | /*! @{ */ | ||
| 1992 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) | ||
| 1993 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) | ||
| 1994 | /*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF | ||
| 1995 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1996 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1997 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1998 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1999 | */ | ||
| 2000 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) | ||
| 2001 | /*! @} */ | ||
| 2002 | |||
| 2003 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ | ||
| 2004 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) | ||
| 2005 | |||
| 2006 | /*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ | ||
| 2007 | /*! @{ */ | ||
| 2008 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) | ||
| 2009 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) | ||
| 2010 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 2011 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2012 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2013 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2014 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2015 | */ | ||
| 2016 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) | ||
| 2017 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) | ||
| 2018 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) | ||
| 2019 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 2020 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2021 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2022 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2023 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2024 | */ | ||
| 2025 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) | ||
| 2026 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) | ||
| 2027 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) | ||
| 2028 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 2029 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2030 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2031 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2032 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2033 | */ | ||
| 2034 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) | ||
| 2035 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 2036 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) | ||
| 2037 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 2038 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2039 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2040 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2041 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2042 | */ | ||
| 2043 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) | ||
| 2044 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 2045 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) | ||
| 2046 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 2047 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2048 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2049 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2050 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2051 | */ | ||
| 2052 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) | ||
| 2053 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 2054 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) | ||
| 2055 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 2056 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2057 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2058 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2059 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2060 | */ | ||
| 2061 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) | ||
| 2062 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 2063 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) | ||
| 2064 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 2065 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2066 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2067 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2068 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2069 | */ | ||
| 2070 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) | ||
| 2071 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 2072 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) | ||
| 2073 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 2074 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2075 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2076 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2077 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2078 | */ | ||
| 2079 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) | ||
| 2080 | /*! @} */ | ||
| 2081 | |||
| 2082 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ | ||
| 2083 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) | ||
| 2084 | |||
| 2085 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ | ||
| 2086 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) | ||
| 2087 | |||
| 2088 | /*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ | ||
| 2089 | /*! @{ */ | ||
| 2090 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) | ||
| 2091 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) | ||
| 2092 | /*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF | ||
| 2093 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2094 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2095 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2096 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2097 | */ | ||
| 2098 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) | ||
| 2099 | /*! @} */ | ||
| 2100 | |||
| 2101 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ | ||
| 2102 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) | ||
| 2103 | |||
| 2104 | /*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ | ||
| 2105 | /*! @{ */ | ||
| 2106 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) | ||
| 2107 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) | ||
| 2108 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 2109 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2110 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2111 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2112 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2113 | */ | ||
| 2114 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) | ||
| 2115 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) | ||
| 2116 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) | ||
| 2117 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 2118 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2119 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2120 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2121 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2122 | */ | ||
| 2123 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) | ||
| 2124 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) | ||
| 2125 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) | ||
| 2126 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 2127 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2128 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2129 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2130 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2131 | */ | ||
| 2132 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) | ||
| 2133 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 2134 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) | ||
| 2135 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 2136 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2137 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2138 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2139 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2140 | */ | ||
| 2141 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) | ||
| 2142 | /*! @} */ | ||
| 2143 | |||
| 2144 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ | ||
| 2145 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) | ||
| 2146 | |||
| 2147 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ | ||
| 2148 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) | ||
| 2149 | |||
| 2150 | /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ | ||
| 2151 | /*! @{ */ | ||
| 2152 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) | ||
| 2153 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) | ||
| 2154 | /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 | ||
| 2155 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2156 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2157 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2158 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2159 | */ | ||
| 2160 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) | ||
| 2161 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) | ||
| 2162 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) | ||
| 2163 | /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 | ||
| 2164 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2165 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2166 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2167 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2168 | */ | ||
| 2169 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) | ||
| 2170 | /*! @} */ | ||
| 2171 | |||
| 2172 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ | ||
| 2173 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) | ||
| 2174 | |||
| 2175 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 2176 | /*! @{ */ | ||
| 2177 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) | ||
| 2178 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) | ||
| 2179 | /*! SYSCON_RULE - System Configuration | ||
| 2180 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2181 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2182 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2183 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2184 | */ | ||
| 2185 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) | ||
| 2186 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) | ||
| 2187 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) | ||
| 2188 | /*! IOCON_RULE - I/O Configuration | ||
| 2189 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2190 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2191 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2192 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2193 | */ | ||
| 2194 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) | ||
| 2195 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) | ||
| 2196 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) | ||
| 2197 | /*! GINT0_RULE - GPIO input Interrupt 0 | ||
| 2198 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2199 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2200 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2201 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2202 | */ | ||
| 2203 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) | ||
| 2204 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) | ||
| 2205 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) | ||
| 2206 | /*! GINT1_RULE - GPIO input Interrupt 1 | ||
| 2207 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2208 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2209 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2210 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2211 | */ | ||
| 2212 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) | ||
| 2213 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) | ||
| 2214 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) | ||
| 2215 | /*! PINT_RULE - Pin Interrupt and Pattern match | ||
| 2216 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2217 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2218 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2219 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2220 | */ | ||
| 2221 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) | ||
| 2222 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) | ||
| 2223 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) | ||
| 2224 | /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match | ||
| 2225 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2226 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2227 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2228 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2229 | */ | ||
| 2230 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) | ||
| 2231 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) | ||
| 2232 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) | ||
| 2233 | /*! INPUTMUX_RULE - Peripheral input multiplexing | ||
| 2234 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2235 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2236 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2237 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2238 | */ | ||
| 2239 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) | ||
| 2240 | /*! @} */ | ||
| 2241 | |||
| 2242 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ | ||
| 2243 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) | ||
| 2244 | |||
| 2245 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 2246 | /*! @{ */ | ||
| 2247 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) | ||
| 2248 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) | ||
| 2249 | /*! CTIMER0_RULE - Standard counter/Timer 0 | ||
| 2250 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2251 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2252 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2253 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2254 | */ | ||
| 2255 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) | ||
| 2256 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) | ||
| 2257 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) | ||
| 2258 | /*! CTIMER1_RULE - Standard counter/Timer 1 | ||
| 2259 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2260 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2261 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2262 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2263 | */ | ||
| 2264 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) | ||
| 2265 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) | ||
| 2266 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) | ||
| 2267 | /*! WWDT_RULE - Windiwed wtachdog Timer | ||
| 2268 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2269 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2270 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2271 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2272 | */ | ||
| 2273 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) | ||
| 2274 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) | ||
| 2275 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) | ||
| 2276 | /*! MRT_RULE - Multi-rate Timer | ||
| 2277 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2278 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2279 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2280 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2281 | */ | ||
| 2282 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) | ||
| 2283 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) | ||
| 2284 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) | ||
| 2285 | /*! UTICK_RULE - Micro-Timer | ||
| 2286 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2287 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2288 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2289 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2290 | */ | ||
| 2291 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) | ||
| 2292 | /*! @} */ | ||
| 2293 | |||
| 2294 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ | ||
| 2295 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) | ||
| 2296 | |||
| 2297 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 2298 | /*! @{ */ | ||
| 2299 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) | ||
| 2300 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) | ||
| 2301 | /*! ANACTRL_RULE - Analog Modules controller | ||
| 2302 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2303 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2304 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2305 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2306 | */ | ||
| 2307 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) | ||
| 2308 | /*! @} */ | ||
| 2309 | |||
| 2310 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ | ||
| 2311 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) | ||
| 2312 | |||
| 2313 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2314 | /*! @{ */ | ||
| 2315 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) | ||
| 2316 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) | ||
| 2317 | /*! PMC_RULE - Power Management Controller | ||
| 2318 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2319 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2320 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2321 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2322 | */ | ||
| 2323 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) | ||
| 2324 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) | ||
| 2325 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) | ||
| 2326 | /*! SYSCTRL_RULE - System Controller | ||
| 2327 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2328 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2329 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2330 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2331 | */ | ||
| 2332 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) | ||
| 2333 | /*! @} */ | ||
| 2334 | |||
| 2335 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ | ||
| 2336 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) | ||
| 2337 | |||
| 2338 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2339 | /*! @{ */ | ||
| 2340 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) | ||
| 2341 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) | ||
| 2342 | /*! CTIMER2_RULE - Standard counter/Timer 2 | ||
| 2343 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2344 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2345 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2346 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2347 | */ | ||
| 2348 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) | ||
| 2349 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) | ||
| 2350 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) | ||
| 2351 | /*! CTIMER3_RULE - Standard counter/Timer 3 | ||
| 2352 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2353 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2354 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2355 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2356 | */ | ||
| 2357 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) | ||
| 2358 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) | ||
| 2359 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) | ||
| 2360 | /*! CTIMER4_RULE - Standard counter/Timer 4 | ||
| 2361 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2362 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2363 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2364 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2365 | */ | ||
| 2366 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) | ||
| 2367 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) | ||
| 2368 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) | ||
| 2369 | /*! RTC_RULE - Real Time Counter | ||
| 2370 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2371 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2372 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2373 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2374 | */ | ||
| 2375 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) | ||
| 2376 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) | ||
| 2377 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) | ||
| 2378 | /*! OSEVENT_RULE - OS Event Timer | ||
| 2379 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2380 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2381 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2382 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2383 | */ | ||
| 2384 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) | ||
| 2385 | /*! @} */ | ||
| 2386 | |||
| 2387 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ | ||
| 2388 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) | ||
| 2389 | |||
| 2390 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2391 | /*! @{ */ | ||
| 2392 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) | ||
| 2393 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) | ||
| 2394 | /*! FLASH_CTRL_RULE - Flash Controller | ||
| 2395 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2396 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2397 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2398 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2399 | */ | ||
| 2400 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) | ||
| 2401 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) | ||
| 2402 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) | ||
| 2403 | /*! PRINCE_RULE - Prince | ||
| 2404 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2405 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2406 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2407 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2408 | */ | ||
| 2409 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) | ||
| 2410 | /*! @} */ | ||
| 2411 | |||
| 2412 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ | ||
| 2413 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) | ||
| 2414 | |||
| 2415 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2416 | /*! @{ */ | ||
| 2417 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) | ||
| 2418 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) | ||
| 2419 | /*! USBHPHY_RULE - USB High Speed Phy controller | ||
| 2420 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2421 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2422 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2423 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2424 | */ | ||
| 2425 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) | ||
| 2426 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) | ||
| 2427 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) | ||
| 2428 | /*! RNG_RULE - True Random Number Generator | ||
| 2429 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2430 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2431 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2432 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2433 | */ | ||
| 2434 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) | ||
| 2435 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) | ||
| 2436 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) | ||
| 2437 | /*! PUF_RULE - PUF | ||
| 2438 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2439 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2440 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2441 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2442 | */ | ||
| 2443 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) | ||
| 2444 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) | ||
| 2445 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) | ||
| 2446 | /*! PLU_RULE - Programmable Look-Up logic | ||
| 2447 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2448 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2449 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2450 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2451 | */ | ||
| 2452 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) | ||
| 2453 | /*! @} */ | ||
| 2454 | |||
| 2455 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ | ||
| 2456 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) | ||
| 2457 | |||
| 2458 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2459 | /*! @{ */ | ||
| 2460 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) | ||
| 2461 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) | ||
| 2462 | /*! DMA0_RULE - DMA Controller | ||
| 2463 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2464 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2465 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2466 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2467 | */ | ||
| 2468 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) | ||
| 2469 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) | ||
| 2470 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) | ||
| 2471 | /*! FS_USB_DEV_RULE - USB Full-speed device | ||
| 2472 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2473 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2474 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2475 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2476 | */ | ||
| 2477 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) | ||
| 2478 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) | ||
| 2479 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) | ||
| 2480 | /*! SCT_RULE - SCTimer | ||
| 2481 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2482 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2483 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2484 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2485 | */ | ||
| 2486 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) | ||
| 2487 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) | ||
| 2488 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) | ||
| 2489 | /*! FLEXCOMM0_RULE - Flexcomm interface 0 | ||
| 2490 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2491 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2492 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2493 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2494 | */ | ||
| 2495 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) | ||
| 2496 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) | ||
| 2497 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) | ||
| 2498 | /*! FLEXCOMM1_RULE - Flexcomm interface 1 | ||
| 2499 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2500 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2501 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2502 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2503 | */ | ||
| 2504 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) | ||
| 2505 | /*! @} */ | ||
| 2506 | |||
| 2507 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2508 | /*! @{ */ | ||
| 2509 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) | ||
| 2510 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) | ||
| 2511 | /*! FLEXCOMM2_RULE - Flexcomm interface 2 | ||
| 2512 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2513 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2514 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2515 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2516 | */ | ||
| 2517 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) | ||
| 2518 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) | ||
| 2519 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) | ||
| 2520 | /*! FLEXCOMM3_RULE - Flexcomm interface 3 | ||
| 2521 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2522 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2523 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2524 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2525 | */ | ||
| 2526 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) | ||
| 2527 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) | ||
| 2528 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) | ||
| 2529 | /*! FLEXCOMM4_RULE - Flexcomm interface 4 | ||
| 2530 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2531 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2532 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2533 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2534 | */ | ||
| 2535 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) | ||
| 2536 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) | ||
| 2537 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) | ||
| 2538 | /*! MAILBOX_RULE - Inter CPU communication Mailbox | ||
| 2539 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2540 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2541 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2542 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2543 | */ | ||
| 2544 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) | ||
| 2545 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) | ||
| 2546 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) | ||
| 2547 | /*! GPIO0_RULE - High Speed GPIO | ||
| 2548 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2549 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2550 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2551 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2552 | */ | ||
| 2553 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) | ||
| 2554 | /*! @} */ | ||
| 2555 | |||
| 2556 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2557 | /*! @{ */ | ||
| 2558 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) | ||
| 2559 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) | ||
| 2560 | /*! USB_HS_DEV_RULE - USB high Speed device registers | ||
| 2561 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2562 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2563 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2564 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2565 | */ | ||
| 2566 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) | ||
| 2567 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) | ||
| 2568 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) | ||
| 2569 | /*! CRC_RULE - CRC engine | ||
| 2570 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2571 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2572 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2573 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2574 | */ | ||
| 2575 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) | ||
| 2576 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) | ||
| 2577 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) | ||
| 2578 | /*! FLEXCOMM5_RULE - Flexcomm interface 5 | ||
| 2579 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2580 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2581 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2582 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2583 | */ | ||
| 2584 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) | ||
| 2585 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) | ||
| 2586 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) | ||
| 2587 | /*! FLEXCOMM6_RULE - Flexcomm interface 6 | ||
| 2588 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2589 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2590 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2591 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2592 | */ | ||
| 2593 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) | ||
| 2594 | /*! @} */ | ||
| 2595 | |||
| 2596 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2597 | /*! @{ */ | ||
| 2598 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) | ||
| 2599 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) | ||
| 2600 | /*! FLEXCOMM7_RULE - Flexcomm interface 7 | ||
| 2601 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2602 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2603 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2604 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2605 | */ | ||
| 2606 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) | ||
| 2607 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) | ||
| 2608 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) | ||
| 2609 | /*! SDIO_RULE - SDMMC card interface | ||
| 2610 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2611 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2612 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2613 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2614 | */ | ||
| 2615 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) | ||
| 2616 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) | ||
| 2617 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) | ||
| 2618 | /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) | ||
| 2619 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2620 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2621 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2622 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2623 | */ | ||
| 2624 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) | ||
| 2625 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) | ||
| 2626 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) | ||
| 2627 | /*! HS_LSPI_RULE - High Speed SPI | ||
| 2628 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2629 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2630 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2631 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2632 | */ | ||
| 2633 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) | ||
| 2634 | /*! @} */ | ||
| 2635 | |||
| 2636 | /*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2637 | /*! @{ */ | ||
| 2638 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) | ||
| 2639 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) | ||
| 2640 | /*! ADC_RULE - ADC | ||
| 2641 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2642 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2643 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2644 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2645 | */ | ||
| 2646 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) | ||
| 2647 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) | ||
| 2648 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) | ||
| 2649 | /*! USB_FS_HOST_RULE - USB Full Speed Host registers. | ||
| 2650 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2651 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2652 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2653 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2654 | */ | ||
| 2655 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) | ||
| 2656 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) | ||
| 2657 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) | ||
| 2658 | /*! USB_HS_HOST_RULE - USB High speed host registers | ||
| 2659 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2660 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2661 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2662 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2663 | */ | ||
| 2664 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) | ||
| 2665 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) | ||
| 2666 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) | ||
| 2667 | /*! HASH_RULE - SHA-2 crypto registers | ||
| 2668 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2669 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2670 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2671 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2672 | */ | ||
| 2673 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) | ||
| 2674 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) | ||
| 2675 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) | ||
| 2676 | /*! CASPER_RULE - RSA/ECC crypto accelerator | ||
| 2677 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2678 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2679 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2680 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2681 | */ | ||
| 2682 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) | ||
| 2683 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) | ||
| 2684 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) | ||
| 2685 | /*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) | ||
| 2686 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2687 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2688 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2689 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2690 | */ | ||
| 2691 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) | ||
| 2692 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) | ||
| 2693 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) | ||
| 2694 | /*! DMA1_RULE - DMA Controller (Secure) | ||
| 2695 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2696 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2697 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2698 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2699 | */ | ||
| 2700 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) | ||
| 2701 | /*! @} */ | ||
| 2702 | |||
| 2703 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ | ||
| 2704 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) | ||
| 2705 | |||
| 2706 | /*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2707 | /*! @{ */ | ||
| 2708 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) | ||
| 2709 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) | ||
| 2710 | /*! GPIO1_RULE - Secure High Speed GPIO | ||
| 2711 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2712 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2713 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2714 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2715 | */ | ||
| 2716 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) | ||
| 2717 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) | ||
| 2718 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) | ||
| 2719 | /*! AHB_SEC_CTRL_RULE - AHB Secure Controller | ||
| 2720 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2721 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2722 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2723 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2724 | */ | ||
| 2725 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) | ||
| 2726 | /*! @} */ | ||
| 2727 | |||
| 2728 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ | ||
| 2729 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) | ||
| 2730 | |||
| 2731 | /*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ | ||
| 2732 | /*! @{ */ | ||
| 2733 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) | ||
| 2734 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) | ||
| 2735 | /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF | ||
| 2736 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2737 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2738 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2739 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2740 | */ | ||
| 2741 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) | ||
| 2742 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) | ||
| 2743 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) | ||
| 2744 | /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF | ||
| 2745 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2746 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2747 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2748 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2749 | */ | ||
| 2750 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) | ||
| 2751 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) | ||
| 2752 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) | ||
| 2753 | /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF | ||
| 2754 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2755 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2756 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2757 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2758 | */ | ||
| 2759 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) | ||
| 2760 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) | ||
| 2761 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) | ||
| 2762 | /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF | ||
| 2763 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2764 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2765 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2766 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2767 | */ | ||
| 2768 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) | ||
| 2769 | /*! @} */ | ||
| 2770 | |||
| 2771 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2772 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) | ||
| 2773 | |||
| 2774 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2775 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) | ||
| 2776 | |||
| 2777 | /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ | ||
| 2778 | /*! @{ */ | ||
| 2779 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) | ||
| 2780 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) | ||
| 2781 | /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF | ||
| 2782 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2783 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2784 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2785 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2786 | */ | ||
| 2787 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) | ||
| 2788 | /*! @} */ | ||
| 2789 | |||
| 2790 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ | ||
| 2791 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) | ||
| 2792 | |||
| 2793 | /*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ | ||
| 2794 | /*! @{ */ | ||
| 2795 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) | ||
| 2796 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) | ||
| 2797 | /*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF | ||
| 2798 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2799 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2800 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2801 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2802 | */ | ||
| 2803 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) | ||
| 2804 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) | ||
| 2805 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) | ||
| 2806 | /*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF | ||
| 2807 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2808 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2809 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2810 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2811 | */ | ||
| 2812 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) | ||
| 2813 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) | ||
| 2814 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) | ||
| 2815 | /*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF | ||
| 2816 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2817 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2818 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2819 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2820 | */ | ||
| 2821 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) | ||
| 2822 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) | ||
| 2823 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) | ||
| 2824 | /*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF | ||
| 2825 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2826 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2827 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2828 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2829 | */ | ||
| 2830 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) | ||
| 2831 | /*! @} */ | ||
| 2832 | |||
| 2833 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 2834 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) | ||
| 2835 | |||
| 2836 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 2837 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) | ||
| 2838 | |||
| 2839 | /*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ | ||
| 2840 | /*! @{ */ | ||
| 2841 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) | ||
| 2842 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) | ||
| 2843 | /*! SEC_VIO_ADDR - security violation address for AHB port | ||
| 2844 | */ | ||
| 2845 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) | ||
| 2846 | /*! @} */ | ||
| 2847 | |||
| 2848 | /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ | ||
| 2849 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) | ||
| 2850 | |||
| 2851 | /*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ | ||
| 2852 | /*! @{ */ | ||
| 2853 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) | ||
| 2854 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) | ||
| 2855 | /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. | ||
| 2856 | * 0b0..Read access. | ||
| 2857 | * 0b1..Write access. | ||
| 2858 | */ | ||
| 2859 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) | ||
| 2860 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) | ||
| 2861 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) | ||
| 2862 | /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. | ||
| 2863 | * 0b0..Code access. | ||
| 2864 | * 0b1..Data access. | ||
| 2865 | */ | ||
| 2866 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) | ||
| 2867 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) | ||
| 2868 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) | ||
| 2869 | /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level | ||
| 2870 | */ | ||
| 2871 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) | ||
| 2872 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) | ||
| 2873 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) | ||
| 2874 | /*! SEC_VIO_INFO_MASTER - security violation master number | ||
| 2875 | * 0b0000..CPU0 Code. | ||
| 2876 | * 0b0001..CPU0 System. | ||
| 2877 | * 0b0010..CPU1 Data. | ||
| 2878 | * 0b0011..CPU1 System. | ||
| 2879 | * 0b0100..USB-HS Device. | ||
| 2880 | * 0b0101..SDMA0. | ||
| 2881 | * 0b1000..SDIO. | ||
| 2882 | * 0b1001..PowerQuad. | ||
| 2883 | * 0b1010..HASH. | ||
| 2884 | * 0b1011..USB-FS Host. | ||
| 2885 | * 0b1100..SDMA1. | ||
| 2886 | */ | ||
| 2887 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) | ||
| 2888 | /*! @} */ | ||
| 2889 | |||
| 2890 | /* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ | ||
| 2891 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) | ||
| 2892 | |||
| 2893 | /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ | ||
| 2894 | /*! @{ */ | ||
| 2895 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) | ||
| 2896 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) | ||
| 2897 | /*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. | ||
| 2898 | * 0b0..Not valid. | ||
| 2899 | * 0b1..Valid (violation occurred). | ||
| 2900 | */ | ||
| 2901 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) | ||
| 2902 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) | ||
| 2903 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) | ||
| 2904 | /*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. | ||
| 2905 | * 0b0..Not valid. | ||
| 2906 | * 0b1..Valid (violation occurred). | ||
| 2907 | */ | ||
| 2908 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) | ||
| 2909 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) | ||
| 2910 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) | ||
| 2911 | /*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. | ||
| 2912 | * 0b0..Not valid. | ||
| 2913 | * 0b1..Valid (violation occurred). | ||
| 2914 | */ | ||
| 2915 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) | ||
| 2916 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) | ||
| 2917 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) | ||
| 2918 | /*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. | ||
| 2919 | * 0b0..Not valid. | ||
| 2920 | * 0b1..Valid (violation occurred). | ||
| 2921 | */ | ||
| 2922 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) | ||
| 2923 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) | ||
| 2924 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) | ||
| 2925 | /*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. | ||
| 2926 | * 0b0..Not valid. | ||
| 2927 | * 0b1..Valid (violation occurred). | ||
| 2928 | */ | ||
| 2929 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) | ||
| 2930 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) | ||
| 2931 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) | ||
| 2932 | /*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. | ||
| 2933 | * 0b0..Not valid. | ||
| 2934 | * 0b1..Valid (violation occurred). | ||
| 2935 | */ | ||
| 2936 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) | ||
| 2937 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) | ||
| 2938 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) | ||
| 2939 | /*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. | ||
| 2940 | * 0b0..Not valid. | ||
| 2941 | * 0b1..Valid (violation occurred). | ||
| 2942 | */ | ||
| 2943 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) | ||
| 2944 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) | ||
| 2945 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) | ||
| 2946 | /*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. | ||
| 2947 | * 0b0..Not valid. | ||
| 2948 | * 0b1..Valid (violation occurred). | ||
| 2949 | */ | ||
| 2950 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) | ||
| 2951 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) | ||
| 2952 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) | ||
| 2953 | /*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. | ||
| 2954 | * 0b0..Not valid. | ||
| 2955 | * 0b1..Valid (violation occurred). | ||
| 2956 | */ | ||
| 2957 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) | ||
| 2958 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) | ||
| 2959 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) | ||
| 2960 | /*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. | ||
| 2961 | * 0b0..Not valid. | ||
| 2962 | * 0b1..Valid (violation occurred). | ||
| 2963 | */ | ||
| 2964 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) | ||
| 2965 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) | ||
| 2966 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) | ||
| 2967 | /*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. | ||
| 2968 | * 0b0..Not valid. | ||
| 2969 | * 0b1..Valid (violation occurred). | ||
| 2970 | */ | ||
| 2971 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) | ||
| 2972 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) | ||
| 2973 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) | ||
| 2974 | /*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. | ||
| 2975 | * 0b0..Not valid. | ||
| 2976 | * 0b1..Valid (violation occurred). | ||
| 2977 | */ | ||
| 2978 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) | ||
| 2979 | /*! @} */ | ||
| 2980 | |||
| 2981 | /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ | ||
| 2982 | /*! @{ */ | ||
| 2983 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) | ||
| 2984 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) | ||
| 2985 | /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 | ||
| 2986 | * 0b1..Pin state is readable by non-secure world. | ||
| 2987 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2988 | */ | ||
| 2989 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) | ||
| 2990 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) | ||
| 2991 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) | ||
| 2992 | /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 | ||
| 2993 | * 0b1..Pin state is readable by non-secure world. | ||
| 2994 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2995 | */ | ||
| 2996 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) | ||
| 2997 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) | ||
| 2998 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) | ||
| 2999 | /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 | ||
| 3000 | * 0b1..Pin state is readable by non-secure world. | ||
| 3001 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3002 | */ | ||
| 3003 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) | ||
| 3004 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) | ||
| 3005 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) | ||
| 3006 | /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 | ||
| 3007 | * 0b1..Pin state is readable by non-secure world. | ||
| 3008 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3009 | */ | ||
| 3010 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) | ||
| 3011 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) | ||
| 3012 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) | ||
| 3013 | /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 | ||
| 3014 | * 0b1..Pin state is readable by non-secure world. | ||
| 3015 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3016 | */ | ||
| 3017 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) | ||
| 3018 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) | ||
| 3019 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) | ||
| 3020 | /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 | ||
| 3021 | * 0b1..Pin state is readable by non-secure world. | ||
| 3022 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3023 | */ | ||
| 3024 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) | ||
| 3025 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) | ||
| 3026 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) | ||
| 3027 | /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 | ||
| 3028 | * 0b1..Pin state is readable by non-secure world. | ||
| 3029 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3030 | */ | ||
| 3031 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) | ||
| 3032 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) | ||
| 3033 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) | ||
| 3034 | /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 | ||
| 3035 | * 0b1..Pin state is readable by non-secure world. | ||
| 3036 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3037 | */ | ||
| 3038 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) | ||
| 3039 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) | ||
| 3040 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) | ||
| 3041 | /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 | ||
| 3042 | * 0b1..Pin state is readable by non-secure world. | ||
| 3043 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3044 | */ | ||
| 3045 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) | ||
| 3046 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) | ||
| 3047 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) | ||
| 3048 | /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 | ||
| 3049 | * 0b1..Pin state is readable by non-secure world. | ||
| 3050 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3051 | */ | ||
| 3052 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) | ||
| 3053 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) | ||
| 3054 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) | ||
| 3055 | /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 | ||
| 3056 | * 0b1..Pin state is readable by non-secure world. | ||
| 3057 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3058 | */ | ||
| 3059 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) | ||
| 3060 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) | ||
| 3061 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) | ||
| 3062 | /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 | ||
| 3063 | * 0b1..Pin state is readable by non-secure world. | ||
| 3064 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3065 | */ | ||
| 3066 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) | ||
| 3067 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 3068 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) | ||
| 3069 | /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 | ||
| 3070 | * 0b1..Pin state is readable by non-secure world. | ||
| 3071 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3072 | */ | ||
| 3073 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) | ||
| 3074 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 3075 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) | ||
| 3076 | /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 | ||
| 3077 | * 0b1..Pin state is readable by non-secure world. | ||
| 3078 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3079 | */ | ||
| 3080 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) | ||
| 3081 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 3082 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) | ||
| 3083 | /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 | ||
| 3084 | * 0b1..Pin state is readable by non-secure world. | ||
| 3085 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3086 | */ | ||
| 3087 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) | ||
| 3088 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 3089 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) | ||
| 3090 | /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 | ||
| 3091 | * 0b1..Pin state is readable by non-secure world. | ||
| 3092 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3093 | */ | ||
| 3094 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) | ||
| 3095 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 3096 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) | ||
| 3097 | /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 | ||
| 3098 | * 0b1..Pin state is readable by non-secure world. | ||
| 3099 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3100 | */ | ||
| 3101 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) | ||
| 3102 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 3103 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) | ||
| 3104 | /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 | ||
| 3105 | * 0b1..Pin state is readable by non-secure world. | ||
| 3106 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3107 | */ | ||
| 3108 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) | ||
| 3109 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 3110 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) | ||
| 3111 | /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 | ||
| 3112 | * 0b1..Pin state is readable by non-secure world. | ||
| 3113 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3114 | */ | ||
| 3115 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) | ||
| 3116 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 3117 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) | ||
| 3118 | /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 | ||
| 3119 | * 0b1..Pin state is readable by non-secure world. | ||
| 3120 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3121 | */ | ||
| 3122 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) | ||
| 3123 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 3124 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) | ||
| 3125 | /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 | ||
| 3126 | * 0b1..Pin state is readable by non-secure world. | ||
| 3127 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3128 | */ | ||
| 3129 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) | ||
| 3130 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 3131 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) | ||
| 3132 | /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 | ||
| 3133 | * 0b1..Pin state is readable by non-secure world. | ||
| 3134 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3135 | */ | ||
| 3136 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) | ||
| 3137 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 3138 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) | ||
| 3139 | /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 | ||
| 3140 | * 0b1..Pin state is readable by non-secure world. | ||
| 3141 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3142 | */ | ||
| 3143 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) | ||
| 3144 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 3145 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) | ||
| 3146 | /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 | ||
| 3147 | * 0b1..Pin state is readable by non-secure world. | ||
| 3148 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3149 | */ | ||
| 3150 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) | ||
| 3151 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 3152 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) | ||
| 3153 | /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 | ||
| 3154 | * 0b1..Pin state is readable by non-secure world. | ||
| 3155 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3156 | */ | ||
| 3157 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) | ||
| 3158 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 3159 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) | ||
| 3160 | /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 | ||
| 3161 | * 0b1..Pin state is readable by non-secure world. | ||
| 3162 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3163 | */ | ||
| 3164 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) | ||
| 3165 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 3166 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) | ||
| 3167 | /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 | ||
| 3168 | * 0b1..Pin state is readable by non-secure world. | ||
| 3169 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3170 | */ | ||
| 3171 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) | ||
| 3172 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 3173 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) | ||
| 3174 | /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 | ||
| 3175 | * 0b1..Pin state is readable by non-secure world. | ||
| 3176 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3177 | */ | ||
| 3178 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) | ||
| 3179 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 3180 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) | ||
| 3181 | /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 | ||
| 3182 | * 0b1..Pin state is readable by non-secure world. | ||
| 3183 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3184 | */ | ||
| 3185 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) | ||
| 3186 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 3187 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) | ||
| 3188 | /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 | ||
| 3189 | * 0b1..Pin state is readable by non-secure world. | ||
| 3190 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3191 | */ | ||
| 3192 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) | ||
| 3193 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 3194 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) | ||
| 3195 | /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 | ||
| 3196 | * 0b1..Pin state is readable by non-secure world. | ||
| 3197 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3198 | */ | ||
| 3199 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) | ||
| 3200 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 3201 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) | ||
| 3202 | /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 | ||
| 3203 | * 0b1..Pin state is readable by non-secure world. | ||
| 3204 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3205 | */ | ||
| 3206 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) | ||
| 3207 | /*! @} */ | ||
| 3208 | |||
| 3209 | /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ | ||
| 3210 | /*! @{ */ | ||
| 3211 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) | ||
| 3212 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) | ||
| 3213 | /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 | ||
| 3214 | * 0b1..Pin state is readable by non-secure world. | ||
| 3215 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3216 | */ | ||
| 3217 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) | ||
| 3218 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) | ||
| 3219 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) | ||
| 3220 | /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 | ||
| 3221 | * 0b1..Pin state is readable by non-secure world. | ||
| 3222 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3223 | */ | ||
| 3224 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) | ||
| 3225 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) | ||
| 3226 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) | ||
| 3227 | /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 | ||
| 3228 | * 0b1..Pin state is readable by non-secure world. | ||
| 3229 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3230 | */ | ||
| 3231 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) | ||
| 3232 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) | ||
| 3233 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) | ||
| 3234 | /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 | ||
| 3235 | * 0b1..Pin state is readable by non-secure world. | ||
| 3236 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3237 | */ | ||
| 3238 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) | ||
| 3239 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) | ||
| 3240 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) | ||
| 3241 | /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 | ||
| 3242 | * 0b1..Pin state is readable by non-secure world. | ||
| 3243 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3244 | */ | ||
| 3245 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) | ||
| 3246 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) | ||
| 3247 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) | ||
| 3248 | /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 | ||
| 3249 | * 0b1..Pin state is readable by non-secure world. | ||
| 3250 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3251 | */ | ||
| 3252 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) | ||
| 3253 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) | ||
| 3254 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) | ||
| 3255 | /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 | ||
| 3256 | * 0b1..Pin state is readable by non-secure world. | ||
| 3257 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3258 | */ | ||
| 3259 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) | ||
| 3260 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) | ||
| 3261 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) | ||
| 3262 | /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 | ||
| 3263 | * 0b1..Pin state is readable by non-secure world. | ||
| 3264 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3265 | */ | ||
| 3266 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) | ||
| 3267 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) | ||
| 3268 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) | ||
| 3269 | /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 | ||
| 3270 | * 0b1..Pin state is readable by non-secure world. | ||
| 3271 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3272 | */ | ||
| 3273 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) | ||
| 3274 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) | ||
| 3275 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) | ||
| 3276 | /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 | ||
| 3277 | * 0b1..Pin state is readable by non-secure world. | ||
| 3278 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3279 | */ | ||
| 3280 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) | ||
| 3281 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) | ||
| 3282 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) | ||
| 3283 | /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 | ||
| 3284 | * 0b1..Pin state is readable by non-secure world. | ||
| 3285 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3286 | */ | ||
| 3287 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) | ||
| 3288 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) | ||
| 3289 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) | ||
| 3290 | /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 | ||
| 3291 | * 0b1..Pin state is readable by non-secure world. | ||
| 3292 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3293 | */ | ||
| 3294 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) | ||
| 3295 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 3296 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) | ||
| 3297 | /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 | ||
| 3298 | * 0b1..Pin state is readable by non-secure world. | ||
| 3299 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3300 | */ | ||
| 3301 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) | ||
| 3302 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 3303 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) | ||
| 3304 | /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 | ||
| 3305 | * 0b1..Pin state is readable by non-secure world. | ||
| 3306 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3307 | */ | ||
| 3308 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) | ||
| 3309 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 3310 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) | ||
| 3311 | /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 | ||
| 3312 | * 0b1..Pin state is readable by non-secure world. | ||
| 3313 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3314 | */ | ||
| 3315 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) | ||
| 3316 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 3317 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) | ||
| 3318 | /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 | ||
| 3319 | * 0b1..Pin state is readable by non-secure world. | ||
| 3320 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3321 | */ | ||
| 3322 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) | ||
| 3323 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 3324 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) | ||
| 3325 | /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 | ||
| 3326 | * 0b1..Pin state is readable by non-secure world. | ||
| 3327 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3328 | */ | ||
| 3329 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) | ||
| 3330 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 3331 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) | ||
| 3332 | /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 | ||
| 3333 | * 0b1..Pin state is readable by non-secure world. | ||
| 3334 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3335 | */ | ||
| 3336 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) | ||
| 3337 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 3338 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) | ||
| 3339 | /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 | ||
| 3340 | * 0b1..Pin state is readable by non-secure world. | ||
| 3341 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3342 | */ | ||
| 3343 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) | ||
| 3344 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 3345 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) | ||
| 3346 | /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 | ||
| 3347 | * 0b1..Pin state is readable by non-secure world. | ||
| 3348 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3349 | */ | ||
| 3350 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) | ||
| 3351 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 3352 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) | ||
| 3353 | /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 | ||
| 3354 | * 0b1..Pin state is readable by non-secure world. | ||
| 3355 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3356 | */ | ||
| 3357 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) | ||
| 3358 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 3359 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) | ||
| 3360 | /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 | ||
| 3361 | * 0b1..Pin state is readable by non-secure world. | ||
| 3362 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3363 | */ | ||
| 3364 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) | ||
| 3365 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 3366 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) | ||
| 3367 | /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 | ||
| 3368 | * 0b1..Pin state is readable by non-secure world. | ||
| 3369 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3370 | */ | ||
| 3371 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) | ||
| 3372 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 3373 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) | ||
| 3374 | /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 | ||
| 3375 | * 0b1..Pin state is readable by non-secure world. | ||
| 3376 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3377 | */ | ||
| 3378 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) | ||
| 3379 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 3380 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) | ||
| 3381 | /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 | ||
| 3382 | * 0b1..Pin state is readable by non-secure world. | ||
| 3383 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3384 | */ | ||
| 3385 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) | ||
| 3386 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 3387 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) | ||
| 3388 | /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 | ||
| 3389 | * 0b1..Pin state is readable by non-secure world. | ||
| 3390 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3391 | */ | ||
| 3392 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) | ||
| 3393 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 3394 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) | ||
| 3395 | /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 | ||
| 3396 | * 0b1..Pin state is readable by non-secure world. | ||
| 3397 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3398 | */ | ||
| 3399 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) | ||
| 3400 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 3401 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) | ||
| 3402 | /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 | ||
| 3403 | * 0b1..Pin state is readable by non-secure world. | ||
| 3404 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3405 | */ | ||
| 3406 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) | ||
| 3407 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 3408 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) | ||
| 3409 | /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 | ||
| 3410 | * 0b1..Pin state is readable by non-secure world. | ||
| 3411 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3412 | */ | ||
| 3413 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) | ||
| 3414 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 3415 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) | ||
| 3416 | /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 | ||
| 3417 | * 0b1..Pin state is readable by non-secure world. | ||
| 3418 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3419 | */ | ||
| 3420 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) | ||
| 3421 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 3422 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) | ||
| 3423 | /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 | ||
| 3424 | * 0b1..Pin state is readable by non-secure world. | ||
| 3425 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3426 | */ | ||
| 3427 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) | ||
| 3428 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 3429 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) | ||
| 3430 | /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 | ||
| 3431 | * 0b1..Pin state is readable by non-secure world. | ||
| 3432 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3433 | */ | ||
| 3434 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) | ||
| 3435 | /*! @} */ | ||
| 3436 | |||
| 3437 | /*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ | ||
| 3438 | /*! @{ */ | ||
| 3439 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) | ||
| 3440 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) | ||
| 3441 | /*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts | ||
| 3442 | * 0b0.. | ||
| 3443 | * 0b1.. | ||
| 3444 | */ | ||
| 3445 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) | ||
| 3446 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) | ||
| 3447 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) | ||
| 3448 | /*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. | ||
| 3449 | * 0b0.. | ||
| 3450 | * 0b1.. | ||
| 3451 | */ | ||
| 3452 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) | ||
| 3453 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) | ||
| 3454 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) | ||
| 3455 | /*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. | ||
| 3456 | * 0b0.. | ||
| 3457 | * 0b1.. | ||
| 3458 | */ | ||
| 3459 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) | ||
| 3460 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) | ||
| 3461 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) | ||
| 3462 | /*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. | ||
| 3463 | * 0b0.. | ||
| 3464 | * 0b1.. | ||
| 3465 | */ | ||
| 3466 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) | ||
| 3467 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) | ||
| 3468 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) | ||
| 3469 | /*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. | ||
| 3470 | * 0b0.. | ||
| 3471 | * 0b1.. | ||
| 3472 | */ | ||
| 3473 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) | ||
| 3474 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) | ||
| 3475 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) | ||
| 3476 | /*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. | ||
| 3477 | * 0b0.. | ||
| 3478 | * 0b1.. | ||
| 3479 | */ | ||
| 3480 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) | ||
| 3481 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) | ||
| 3482 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) | ||
| 3483 | /*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. | ||
| 3484 | * 0b0.. | ||
| 3485 | * 0b1.. | ||
| 3486 | */ | ||
| 3487 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) | ||
| 3488 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) | ||
| 3489 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) | ||
| 3490 | /*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. | ||
| 3491 | * 0b0.. | ||
| 3492 | * 0b1.. | ||
| 3493 | */ | ||
| 3494 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) | ||
| 3495 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) | ||
| 3496 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) | ||
| 3497 | /*! UTICK_IRQ - Micro Tick Timer interrupt. | ||
| 3498 | * 0b0.. | ||
| 3499 | * 0b1.. | ||
| 3500 | */ | ||
| 3501 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) | ||
| 3502 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) | ||
| 3503 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) | ||
| 3504 | /*! MRT_IRQ - Multi-Rate Timer interrupt. | ||
| 3505 | * 0b0.. | ||
| 3506 | * 0b1.. | ||
| 3507 | */ | ||
| 3508 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) | ||
| 3509 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) | ||
| 3510 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) | ||
| 3511 | /*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. | ||
| 3512 | * 0b0.. | ||
| 3513 | * 0b1.. | ||
| 3514 | */ | ||
| 3515 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) | ||
| 3516 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) | ||
| 3517 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) | ||
| 3518 | /*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. | ||
| 3519 | * 0b0.. | ||
| 3520 | * 0b1.. | ||
| 3521 | */ | ||
| 3522 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) | ||
| 3523 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) | ||
| 3524 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) | ||
| 3525 | /*! SCT_IRQ - SCTimer/PWM interrupt. | ||
| 3526 | * 0b0.. | ||
| 3527 | * 0b1.. | ||
| 3528 | */ | ||
| 3529 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) | ||
| 3530 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) | ||
| 3531 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) | ||
| 3532 | /*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. | ||
| 3533 | * 0b0.. | ||
| 3534 | * 0b1.. | ||
| 3535 | */ | ||
| 3536 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) | ||
| 3537 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) | ||
| 3538 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) | ||
| 3539 | /*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). | ||
| 3540 | * 0b0.. | ||
| 3541 | * 0b1.. | ||
| 3542 | */ | ||
| 3543 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) | ||
| 3544 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) | ||
| 3545 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) | ||
| 3546 | /*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). | ||
| 3547 | * 0b0.. | ||
| 3548 | * 0b1.. | ||
| 3549 | */ | ||
| 3550 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) | ||
| 3551 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) | ||
| 3552 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) | ||
| 3553 | /*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). | ||
| 3554 | * 0b0.. | ||
| 3555 | * 0b1.. | ||
| 3556 | */ | ||
| 3557 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) | ||
| 3558 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) | ||
| 3559 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) | ||
| 3560 | /*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). | ||
| 3561 | * 0b0.. | ||
| 3562 | * 0b1.. | ||
| 3563 | */ | ||
| 3564 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) | ||
| 3565 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) | ||
| 3566 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) | ||
| 3567 | /*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). | ||
| 3568 | * 0b0.. | ||
| 3569 | * 0b1.. | ||
| 3570 | */ | ||
| 3571 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) | ||
| 3572 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) | ||
| 3573 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) | ||
| 3574 | /*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). | ||
| 3575 | * 0b0.. | ||
| 3576 | * 0b1.. | ||
| 3577 | */ | ||
| 3578 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) | ||
| 3579 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) | ||
| 3580 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) | ||
| 3581 | /*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). | ||
| 3582 | * 0b0.. | ||
| 3583 | * 0b1.. | ||
| 3584 | */ | ||
| 3585 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) | ||
| 3586 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) | ||
| 3587 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) | ||
| 3588 | /*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). | ||
| 3589 | * 0b0.. | ||
| 3590 | * 0b1.. | ||
| 3591 | */ | ||
| 3592 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) | ||
| 3593 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) | ||
| 3594 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) | ||
| 3595 | /*! ADC_IRQ - General Purpose ADC interrupt. | ||
| 3596 | * 0b0.. | ||
| 3597 | * 0b1.. | ||
| 3598 | */ | ||
| 3599 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) | ||
| 3600 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) | ||
| 3601 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) | ||
| 3602 | /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. | ||
| 3603 | * 0b0.. | ||
| 3604 | * 0b1.. | ||
| 3605 | */ | ||
| 3606 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) | ||
| 3607 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) | ||
| 3608 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) | ||
| 3609 | /*! ACMP_IRQ - Analog Comparator interrupt. | ||
| 3610 | * 0b0.. | ||
| 3611 | * 0b1.. | ||
| 3612 | */ | ||
| 3613 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) | ||
| 3614 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) | ||
| 3615 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) | ||
| 3616 | /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. | ||
| 3617 | * 0b0.. | ||
| 3618 | * 0b1.. | ||
| 3619 | */ | ||
| 3620 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) | ||
| 3621 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) | ||
| 3622 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) | ||
| 3623 | /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. | ||
| 3624 | * 0b0.. | ||
| 3625 | * 0b1.. | ||
| 3626 | */ | ||
| 3627 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) | ||
| 3628 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) | ||
| 3629 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) | ||
| 3630 | /*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. | ||
| 3631 | * 0b0.. | ||
| 3632 | * 0b1.. | ||
| 3633 | */ | ||
| 3634 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) | ||
| 3635 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) | ||
| 3636 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) | ||
| 3637 | /*! USB0_IRQ - USB Full Speed Controller interrupt. | ||
| 3638 | * 0b0.. | ||
| 3639 | * 0b1.. | ||
| 3640 | */ | ||
| 3641 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) | ||
| 3642 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) | ||
| 3643 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) | ||
| 3644 | /*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ | ||
| 3645 | * 0b0.. | ||
| 3646 | * 0b1.. | ||
| 3647 | */ | ||
| 3648 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) | ||
| 3649 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) | ||
| 3650 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) | ||
| 3651 | /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. | ||
| 3652 | * 0b0.. | ||
| 3653 | * 0b1.. | ||
| 3654 | */ | ||
| 3655 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) | ||
| 3656 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) | ||
| 3657 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) | ||
| 3658 | /*! MAILBOX_IRQ - Mailbox interrupt. | ||
| 3659 | * 0b0.. | ||
| 3660 | * 0b1.. | ||
| 3661 | */ | ||
| 3662 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) | ||
| 3663 | /*! @} */ | ||
| 3664 | |||
| 3665 | /*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ | ||
| 3666 | /*! @{ */ | ||
| 3667 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) | ||
| 3668 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) | ||
| 3669 | /*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. | ||
| 3670 | * 0b0.. | ||
| 3671 | * 0b1.. | ||
| 3672 | */ | ||
| 3673 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) | ||
| 3674 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) | ||
| 3675 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) | ||
| 3676 | /*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. | ||
| 3677 | * 0b0.. | ||
| 3678 | * 0b1.. | ||
| 3679 | */ | ||
| 3680 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) | ||
| 3681 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) | ||
| 3682 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) | ||
| 3683 | /*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. | ||
| 3684 | * 0b0.. | ||
| 3685 | * 0b1.. | ||
| 3686 | */ | ||
| 3687 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) | ||
| 3688 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) | ||
| 3689 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) | ||
| 3690 | /*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. | ||
| 3691 | * 0b0.. | ||
| 3692 | * 0b1.. | ||
| 3693 | */ | ||
| 3694 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) | ||
| 3695 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) | ||
| 3696 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) | ||
| 3697 | /*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. | ||
| 3698 | * 0b0.. | ||
| 3699 | * 0b1.. | ||
| 3700 | */ | ||
| 3701 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) | ||
| 3702 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) | ||
| 3703 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) | ||
| 3704 | /*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. | ||
| 3705 | * 0b0.. | ||
| 3706 | * 0b1.. | ||
| 3707 | */ | ||
| 3708 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) | ||
| 3709 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) | ||
| 3710 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) | ||
| 3711 | /*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts | ||
| 3712 | * 0b0.. | ||
| 3713 | * 0b1.. | ||
| 3714 | */ | ||
| 3715 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) | ||
| 3716 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) | ||
| 3717 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) | ||
| 3718 | /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. | ||
| 3719 | * 0b0.. | ||
| 3720 | * 0b1.. | ||
| 3721 | */ | ||
| 3722 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) | ||
| 3723 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) | ||
| 3724 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) | ||
| 3725 | /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. | ||
| 3726 | * 0b0.. | ||
| 3727 | * 0b1.. | ||
| 3728 | */ | ||
| 3729 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) | ||
| 3730 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) | ||
| 3731 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) | ||
| 3732 | /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. | ||
| 3733 | * 0b0.. | ||
| 3734 | * 0b1.. | ||
| 3735 | */ | ||
| 3736 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) | ||
| 3737 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) | ||
| 3738 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) | ||
| 3739 | /*! SDIO_IRQ - SDIO Controller interrupt. | ||
| 3740 | * 0b0.. | ||
| 3741 | * 0b1.. | ||
| 3742 | */ | ||
| 3743 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) | ||
| 3744 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) | ||
| 3745 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) | ||
| 3746 | /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. | ||
| 3747 | * 0b0.. | ||
| 3748 | * 0b1.. | ||
| 3749 | */ | ||
| 3750 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) | ||
| 3751 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) | ||
| 3752 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) | ||
| 3753 | /*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. | ||
| 3754 | * 0b0.. | ||
| 3755 | * 0b1.. | ||
| 3756 | */ | ||
| 3757 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) | ||
| 3758 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) | ||
| 3759 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) | ||
| 3760 | /*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. | ||
| 3761 | * 0b0.. | ||
| 3762 | * 0b1.. | ||
| 3763 | */ | ||
| 3764 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) | ||
| 3765 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) | ||
| 3766 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) | ||
| 3767 | /*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. | ||
| 3768 | * 0b0.. | ||
| 3769 | * 0b1.. | ||
| 3770 | */ | ||
| 3771 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) | ||
| 3772 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) | ||
| 3773 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) | ||
| 3774 | /*! USB1_IRQ - USB High Speed Controller interrupt. | ||
| 3775 | * 0b0.. | ||
| 3776 | * 0b1.. | ||
| 3777 | */ | ||
| 3778 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) | ||
| 3779 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) | ||
| 3780 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) | ||
| 3781 | /*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. | ||
| 3782 | * 0b0.. | ||
| 3783 | * 0b1.. | ||
| 3784 | */ | ||
| 3785 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) | ||
| 3786 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) | ||
| 3787 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) | ||
| 3788 | /*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. | ||
| 3789 | * 0b0.. | ||
| 3790 | * 0b1.. | ||
| 3791 | */ | ||
| 3792 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) | ||
| 3793 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) | ||
| 3794 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) | ||
| 3795 | /*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. | ||
| 3796 | * 0b0.. | ||
| 3797 | * 0b1.. | ||
| 3798 | */ | ||
| 3799 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) | ||
| 3800 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) | ||
| 3801 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) | ||
| 3802 | /*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. | ||
| 3803 | * 0b0.. | ||
| 3804 | * 0b1.. | ||
| 3805 | */ | ||
| 3806 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) | ||
| 3807 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) | ||
| 3808 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) | ||
| 3809 | /*! PLU_IRQ - Programmable Look-Up Controller interrupt. | ||
| 3810 | * 0b0.. | ||
| 3811 | * 0b1.. | ||
| 3812 | */ | ||
| 3813 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) | ||
| 3814 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) | ||
| 3815 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) | ||
| 3816 | /*! SEC_VIO_IRQ - Security Violation interrupt. | ||
| 3817 | * 0b0.. | ||
| 3818 | * 0b1.. | ||
| 3819 | */ | ||
| 3820 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) | ||
| 3821 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) | ||
| 3822 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) | ||
| 3823 | /*! SHA_IRQ - HASH-AES interrupt. | ||
| 3824 | * 0b0.. | ||
| 3825 | * 0b1.. | ||
| 3826 | */ | ||
| 3827 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) | ||
| 3828 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) | ||
| 3829 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) | ||
| 3830 | /*! CASPER_IRQ - CASPER interrupt. | ||
| 3831 | * 0b0.. | ||
| 3832 | * 0b1.. | ||
| 3833 | */ | ||
| 3834 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) | ||
| 3835 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) | ||
| 3836 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) | ||
| 3837 | /*! PUFKEY_IRQ - PUF interrupt. | ||
| 3838 | * 0b0.. | ||
| 3839 | * 0b1.. | ||
| 3840 | */ | ||
| 3841 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) | ||
| 3842 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) | ||
| 3843 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) | ||
| 3844 | /*! PQ_IRQ - Power Quad interrupt. | ||
| 3845 | * 0b0.. | ||
| 3846 | * 0b1.. | ||
| 3847 | */ | ||
| 3848 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) | ||
| 3849 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) | ||
| 3850 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) | ||
| 3851 | /*! SDMA1_IRQ - System DMA 1 (Secure) interrupt | ||
| 3852 | * 0b0.. | ||
| 3853 | * 0b1.. | ||
| 3854 | */ | ||
| 3855 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) | ||
| 3856 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) | ||
| 3857 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) | ||
| 3858 | /*! LSPI_HS_IRQ - High Speed SPI interrupt | ||
| 3859 | * 0b0.. | ||
| 3860 | * 0b1.. | ||
| 3861 | */ | ||
| 3862 | #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) | ||
| 3863 | /*! @} */ | ||
| 3864 | |||
| 3865 | /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ | ||
| 3866 | /*! @{ */ | ||
| 3867 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) | ||
| 3868 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) | ||
| 3869 | /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. | ||
| 3870 | * 0b10..Writable. | ||
| 3871 | * 0b01..Restricted mode. | ||
| 3872 | */ | ||
| 3873 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) | ||
| 3874 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) | ||
| 3875 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) | ||
| 3876 | /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. | ||
| 3877 | * 0b10..Writable. | ||
| 3878 | * 0b01..Restricted mode. | ||
| 3879 | */ | ||
| 3880 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) | ||
| 3881 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) | ||
| 3882 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) | ||
| 3883 | /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. | ||
| 3884 | * 0b10..Writable. | ||
| 3885 | * 0b01..Restricted mode. | ||
| 3886 | */ | ||
| 3887 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) | ||
| 3888 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) | ||
| 3889 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) | ||
| 3890 | /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. | ||
| 3891 | * 0b10..Writable. | ||
| 3892 | * 0b01..Restricted mode. | ||
| 3893 | */ | ||
| 3894 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) | ||
| 3895 | /*! @} */ | ||
| 3896 | |||
| 3897 | /*! @name MASTER_SEC_LEVEL - master secure level register */ | ||
| 3898 | /*! @{ */ | ||
| 3899 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) | ||
| 3900 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) | ||
| 3901 | /*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. | ||
| 3902 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3903 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3904 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3905 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3906 | */ | ||
| 3907 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) | ||
| 3908 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) | ||
| 3909 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) | ||
| 3910 | /*! CPU1S - Micro-Cortex M33 (CPU1) System bus. | ||
| 3911 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3912 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3913 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3914 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3915 | */ | ||
| 3916 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) | ||
| 3917 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) | ||
| 3918 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) | ||
| 3919 | /*! USBFSD - USB Full Speed Device. | ||
| 3920 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3921 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3922 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3923 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3924 | */ | ||
| 3925 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) | ||
| 3926 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) | ||
| 3927 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) | ||
| 3928 | /*! SDMA0 - System DMA 0. | ||
| 3929 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3930 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3931 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3932 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3933 | */ | ||
| 3934 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) | ||
| 3935 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) | ||
| 3936 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) | ||
| 3937 | /*! SDIO - SDIO. | ||
| 3938 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3939 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3940 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3941 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3942 | */ | ||
| 3943 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) | ||
| 3944 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) | ||
| 3945 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) | ||
| 3946 | /*! PQ - Power Quad. | ||
| 3947 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3948 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3949 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3950 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3951 | */ | ||
| 3952 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) | ||
| 3953 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) | ||
| 3954 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) | ||
| 3955 | /*! HASH - Hash. | ||
| 3956 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3957 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3958 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3959 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3960 | */ | ||
| 3961 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) | ||
| 3962 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) | ||
| 3963 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) | ||
| 3964 | /*! USBFSH - USB Full speed Host. | ||
| 3965 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3966 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3967 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3968 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3969 | */ | ||
| 3970 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) | ||
| 3971 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) | ||
| 3972 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) | ||
| 3973 | /*! SDMA1 - System DMA 1 security level. | ||
| 3974 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3975 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3976 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3977 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3978 | */ | ||
| 3979 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) | ||
| 3980 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) | ||
| 3981 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) | ||
| 3982 | /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. | ||
| 3983 | * 0b10..Writable. | ||
| 3984 | * 0b01..Restricted mode. | ||
| 3985 | */ | ||
| 3986 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) | ||
| 3987 | /*! @} */ | ||
| 3988 | |||
| 3989 | /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ | ||
| 3990 | /*! @{ */ | ||
| 3991 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) | ||
| 3992 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) | ||
| 3993 | /*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) | ||
| 3994 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3995 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3996 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3997 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3998 | */ | ||
| 3999 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) | ||
| 4000 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) | ||
| 4001 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) | ||
| 4002 | /*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) | ||
| 4003 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4004 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4005 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4006 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4007 | */ | ||
| 4008 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) | ||
| 4009 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) | ||
| 4010 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) | ||
| 4011 | /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) | ||
| 4012 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4013 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4014 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4015 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4016 | */ | ||
| 4017 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) | ||
| 4018 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) | ||
| 4019 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) | ||
| 4020 | /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) | ||
| 4021 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4022 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4023 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4024 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4025 | */ | ||
| 4026 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) | ||
| 4027 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) | ||
| 4028 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) | ||
| 4029 | /*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) | ||
| 4030 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4031 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4032 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4033 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4034 | */ | ||
| 4035 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) | ||
| 4036 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) | ||
| 4037 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) | ||
| 4038 | /*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) | ||
| 4039 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4040 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4041 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4042 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4043 | */ | ||
| 4044 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) | ||
| 4045 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) | ||
| 4046 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) | ||
| 4047 | /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) | ||
| 4048 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4049 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4050 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4051 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4052 | */ | ||
| 4053 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) | ||
| 4054 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) | ||
| 4055 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) | ||
| 4056 | /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) | ||
| 4057 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4058 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4059 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4060 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4061 | */ | ||
| 4062 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) | ||
| 4063 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) | ||
| 4064 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) | ||
| 4065 | /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) | ||
| 4066 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 4067 | * 0b10..Non-secure and Privilege access allowed. | ||
| 4068 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 4069 | * 0b00..Secure and Priviledge user access allowed. | ||
| 4070 | */ | ||
| 4071 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) | ||
| 4072 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) | ||
| 4073 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) | ||
| 4074 | /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. | ||
| 4075 | * 0b10..Writable. | ||
| 4076 | * 0b01..Restricted mode. | ||
| 4077 | */ | ||
| 4078 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) | ||
| 4079 | /*! @} */ | ||
| 4080 | |||
| 4081 | /*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ | ||
| 4082 | /*! @{ */ | ||
| 4083 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) | ||
| 4084 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) | ||
| 4085 | /*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. | ||
| 4086 | * 0b10..Writable. | ||
| 4087 | * 0b01..Restricted mode. | ||
| 4088 | */ | ||
| 4089 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) | ||
| 4090 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) | ||
| 4091 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) | ||
| 4092 | /*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. | ||
| 4093 | * 0b10..Writable. | ||
| 4094 | * 0b01..Restricted mode. | ||
| 4095 | */ | ||
| 4096 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) | ||
| 4097 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) | ||
| 4098 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) | ||
| 4099 | /*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. | ||
| 4100 | * 0b10..Writable. | ||
| 4101 | * 0b01..Restricted mode. | ||
| 4102 | */ | ||
| 4103 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) | ||
| 4104 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) | ||
| 4105 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) | ||
| 4106 | /*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. | ||
| 4107 | * 0b10..Writable. | ||
| 4108 | * 0b01..Restricted mode. | ||
| 4109 | */ | ||
| 4110 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) | ||
| 4111 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) | ||
| 4112 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) | ||
| 4113 | /*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. | ||
| 4114 | * 0b10..Writable. | ||
| 4115 | * 0b01..Restricted mode. | ||
| 4116 | */ | ||
| 4117 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) | ||
| 4118 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) | ||
| 4119 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) | ||
| 4120 | /*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. | ||
| 4121 | * 0b10..Writable. | ||
| 4122 | * 0b01..Restricted mode. | ||
| 4123 | */ | ||
| 4124 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) | ||
| 4125 | /*! @} */ | ||
| 4126 | |||
| 4127 | /*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ | ||
| 4128 | /*! @{ */ | ||
| 4129 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) | ||
| 4130 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) | ||
| 4131 | /*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. | ||
| 4132 | * 0b10..Writable. | ||
| 4133 | * 0b01..Restricted mode. | ||
| 4134 | */ | ||
| 4135 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) | ||
| 4136 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) | ||
| 4137 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) | ||
| 4138 | /*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. | ||
| 4139 | * 0b10..Writable. | ||
| 4140 | * 0b01..Restricted mode. | ||
| 4141 | */ | ||
| 4142 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) | ||
| 4143 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) | ||
| 4144 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) | ||
| 4145 | /*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. | ||
| 4146 | * 0b10..Writable. | ||
| 4147 | * 0b01..Restricted mode. | ||
| 4148 | */ | ||
| 4149 | #define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) | ||
| 4150 | /*! @} */ | ||
| 4151 | |||
| 4152 | /*! @name MISC_CTRL_DP_REG - secure control duplicate register */ | ||
| 4153 | /*! @{ */ | ||
| 4154 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) | ||
| 4155 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) | ||
| 4156 | /*! WRITE_LOCK - Write lock. | ||
| 4157 | * 0b10..Secure control registers can be written. | ||
| 4158 | * 0b01..Restricted mode. | ||
| 4159 | */ | ||
| 4160 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) | ||
| 4161 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 4162 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 4163 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 4164 | * 0b10..Disable check. | ||
| 4165 | * 0b01..Restricted mode. | ||
| 4166 | */ | ||
| 4167 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 4168 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 4169 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 4170 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 4171 | * 0b10..Disable check. | ||
| 4172 | * 0b01..Restricted mode. | ||
| 4173 | */ | ||
| 4174 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 4175 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 4176 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 4177 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 4178 | * 0b10..Disable check. | ||
| 4179 | * 0b01..Restricted mode. | ||
| 4180 | */ | ||
| 4181 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 4182 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 4183 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 4184 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 4185 | * 0b10..Enable abort fort secure checker. | ||
| 4186 | * 0b01..Disable abort fort secure checker. | ||
| 4187 | */ | ||
| 4188 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 4189 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 4190 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 4191 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 4192 | * 0b10..Simple master in strict mode. | ||
| 4193 | * 0b01..Simple master in tier mode. | ||
| 4194 | */ | ||
| 4195 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 4196 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 4197 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 4198 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 4199 | * 0b10..Smart master in strict mode. | ||
| 4200 | * 0b01..Smart master in tier mode. | ||
| 4201 | */ | ||
| 4202 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 4203 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 4204 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 4205 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 4206 | * 0b10..IDAU is enabled. | ||
| 4207 | * 0b01..IDAU is disable. | ||
| 4208 | */ | ||
| 4209 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) | ||
| 4210 | /*! @} */ | ||
| 4211 | |||
| 4212 | /*! @name MISC_CTRL_REG - secure control register */ | ||
| 4213 | /*! @{ */ | ||
| 4214 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) | ||
| 4215 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) | ||
| 4216 | /*! WRITE_LOCK - Write lock. | ||
| 4217 | * 0b10..Secure control registers can be written. | ||
| 4218 | * 0b01..Restricted mode. | ||
| 4219 | */ | ||
| 4220 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) | ||
| 4221 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 4222 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 4223 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 4224 | * 0b10..Disable check. | ||
| 4225 | * 0b01..Restricted mode. | ||
| 4226 | */ | ||
| 4227 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 4228 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 4229 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 4230 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 4231 | * 0b10..Disable check. | ||
| 4232 | * 0b01..Restricted mode. | ||
| 4233 | */ | ||
| 4234 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 4235 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 4236 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 4237 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 4238 | * 0b10..Disable check. | ||
| 4239 | * 0b01..Restricted mode. | ||
| 4240 | */ | ||
| 4241 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 4242 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 4243 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 4244 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 4245 | * 0b10..Enable abort fort secure checker. | ||
| 4246 | * 0b01..Disable abort fort secure checker. | ||
| 4247 | */ | ||
| 4248 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 4249 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 4250 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 4251 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 4252 | * 0b10..Simple master in strict mode. | ||
| 4253 | * 0b01..Simple master in tier mode. | ||
| 4254 | */ | ||
| 4255 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 4256 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 4257 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 4258 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 4259 | * 0b10..Smart master in strict mode. | ||
| 4260 | * 0b01..Smart master in tier mode. | ||
| 4261 | */ | ||
| 4262 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 4263 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 4264 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 4265 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 4266 | * 0b10..IDAU is enabled. | ||
| 4267 | * 0b01..IDAU is disable. | ||
| 4268 | */ | ||
| 4269 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) | ||
| 4270 | /*! @} */ | ||
| 4271 | |||
| 4272 | |||
| 4273 | /*! | ||
| 4274 | * @} | ||
| 4275 | */ /* end of group AHB_SECURE_CTRL_Register_Masks */ | ||
| 4276 | |||
| 4277 | |||
| 4278 | /* AHB_SECURE_CTRL - Peripheral instance base addresses */ | ||
| 4279 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 4280 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 4281 | #define AHB_SECURE_CTRL_BASE (0x500AC000u) | ||
| 4282 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 4283 | #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) | ||
| 4284 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 4285 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 4286 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 4287 | #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) | ||
| 4288 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 4289 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 4290 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 4291 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 4292 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 4293 | #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } | ||
| 4294 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 4295 | #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } | ||
| 4296 | #else | ||
| 4297 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 4298 | #define AHB_SECURE_CTRL_BASE (0x400AC000u) | ||
| 4299 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 4300 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 4301 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 4302 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 4303 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 4304 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 4305 | #endif | ||
| 4306 | |||
| 4307 | /*! | ||
| 4308 | * @} | ||
| 4309 | */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ | ||
| 4310 | |||
| 4311 | |||
| 4312 | /* ---------------------------------------------------------------------------- | ||
| 4313 | -- ANACTRL Peripheral Access Layer | ||
| 4314 | ---------------------------------------------------------------------------- */ | ||
| 4315 | |||
| 4316 | /*! | ||
| 4317 | * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer | ||
| 4318 | * @{ | ||
| 4319 | */ | ||
| 4320 | |||
| 4321 | /** ANACTRL - Register Layout Typedef */ | ||
| 4322 | typedef struct { | ||
| 4323 | uint8_t RESERVED_0[4]; | ||
| 4324 | __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ | ||
| 4325 | uint8_t RESERVED_1[4]; | ||
| 4326 | __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ | ||
| 4327 | __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ | ||
| 4328 | __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ | ||
| 4329 | uint8_t RESERVED_2[8]; | ||
| 4330 | __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ | ||
| 4331 | __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ | ||
| 4332 | uint8_t RESERVED_3[8]; | ||
| 4333 | __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ | ||
| 4334 | __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ | ||
| 4335 | uint8_t RESERVED_4[8]; | ||
| 4336 | __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ | ||
| 4337 | __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ | ||
| 4338 | __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ | ||
| 4339 | uint8_t RESERVED_5[180]; | ||
| 4340 | __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ | ||
| 4341 | } ANACTRL_Type; | ||
| 4342 | |||
| 4343 | /* ---------------------------------------------------------------------------- | ||
| 4344 | -- ANACTRL Register Masks | ||
| 4345 | ---------------------------------------------------------------------------- */ | ||
| 4346 | |||
| 4347 | /*! | ||
| 4348 | * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks | ||
| 4349 | * @{ | ||
| 4350 | */ | ||
| 4351 | |||
| 4352 | /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ | ||
| 4353 | /*! @{ */ | ||
| 4354 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) | ||
| 4355 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) | ||
| 4356 | /*! FLASH_PWRDWN - Flash Power Down status. | ||
| 4357 | * 0b0..Flash is not in power down mode. | ||
| 4358 | * 0b1..Flash is in power down mode. | ||
| 4359 | */ | ||
| 4360 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) | ||
| 4361 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) | ||
| 4362 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) | ||
| 4363 | /*! FLASH_INIT_ERROR - Flash initialization error status. | ||
| 4364 | * 0b0..No error. | ||
| 4365 | * 0b1..At least one error occured during flash initialization.. | ||
| 4366 | */ | ||
| 4367 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) | ||
| 4368 | /*! @} */ | ||
| 4369 | |||
| 4370 | /*! @name FREQ_ME_CTRL - Frequency Measure function control register */ | ||
| 4371 | /*! @{ */ | ||
| 4372 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) | ||
| 4373 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) | ||
| 4374 | /*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale | ||
| 4375 | */ | ||
| 4376 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) | ||
| 4377 | #define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) | ||
| 4378 | #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) | ||
| 4379 | /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit | ||
| 4380 | * when the measurement cycle has completed and there is valid capture data in the CAPVAL field | ||
| 4381 | * (bits 30:0). | ||
| 4382 | */ | ||
| 4383 | #define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) | ||
| 4384 | /*! @} */ | ||
| 4385 | |||
| 4386 | /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ | ||
| 4387 | /*! @{ */ | ||
| 4388 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) | ||
| 4389 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) | ||
| 4390 | /*! ENA_12MHZCLK - 12 MHz clock control. | ||
| 4391 | * 0b0..12 MHz clock is disabled. | ||
| 4392 | * 0b1..12 MHz clock is enabled. | ||
| 4393 | */ | ||
| 4394 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) | ||
| 4395 | #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) | ||
| 4396 | #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) | ||
| 4397 | /*! ENA_48MHZCLK - 48 MHz clock control. | ||
| 4398 | * 0b0..Reserved. | ||
| 4399 | * 0b1..48 MHz clock is enabled. | ||
| 4400 | */ | ||
| 4401 | #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) | ||
| 4402 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) | ||
| 4403 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) | ||
| 4404 | /*! DAC_TRIM - Frequency trim. | ||
| 4405 | */ | ||
| 4406 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) | ||
| 4407 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) | ||
| 4408 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) | ||
| 4409 | /*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, | ||
| 4410 | * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF | ||
| 4411 | * packets. | ||
| 4412 | */ | ||
| 4413 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) | ||
| 4414 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) | ||
| 4415 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) | ||
| 4416 | /*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. | ||
| 4417 | */ | ||
| 4418 | #define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) | ||
| 4419 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) | ||
| 4420 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) | ||
| 4421 | /*! ENA_96MHZCLK - 96 MHz clock control. | ||
| 4422 | * 0b0..96 MHz clock is disabled. | ||
| 4423 | * 0b1..96 MHz clock is enabled. | ||
| 4424 | */ | ||
| 4425 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) | ||
| 4426 | /*! @} */ | ||
| 4427 | |||
| 4428 | /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ | ||
| 4429 | /*! @{ */ | ||
| 4430 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) | ||
| 4431 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) | ||
| 4432 | /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. | ||
| 4433 | * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). | ||
| 4434 | * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by | ||
| 4435 | * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). | ||
| 4436 | */ | ||
| 4437 | #define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) | ||
| 4438 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) | ||
| 4439 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) | ||
| 4440 | /*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses | ||
| 4441 | * the threshold voltage of a SLVT transistor, this output signal will go high. It is also | ||
| 4442 | * possible to observe the clk_valid signal. | ||
| 4443 | */ | ||
| 4444 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) | ||
| 4445 | /*! @} */ | ||
| 4446 | |||
| 4447 | /*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ | ||
| 4448 | /*! @{ */ | ||
| 4449 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) | ||
| 4450 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) | ||
| 4451 | /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. | ||
| 4452 | * 0b0..XO AC buffer bypass is disabled. | ||
| 4453 | * 0b1..XO AC buffer bypass is enabled. | ||
| 4454 | */ | ||
| 4455 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) | ||
| 4456 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) | ||
| 4457 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) | ||
| 4458 | /*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. | ||
| 4459 | * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. | ||
| 4460 | * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. | ||
| 4461 | */ | ||
| 4462 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) | ||
| 4463 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) | ||
| 4464 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) | ||
| 4465 | /*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. | ||
| 4466 | * 0b0..High speed Crystal oscillator output to CPU system is disabled. | ||
| 4467 | * 0b1..High speed Crystal oscillator output to CPU system is enabled. | ||
| 4468 | */ | ||
| 4469 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) | ||
| 4470 | /*! @} */ | ||
| 4471 | |||
| 4472 | /*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ | ||
| 4473 | /*! @{ */ | ||
| 4474 | #define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) | ||
| 4475 | #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) | ||
| 4476 | /*! XO_READY - Indicates XO out frequency statibilty. | ||
| 4477 | * 0b0..XO output frequency is not yet stable. | ||
| 4478 | * 0b1..XO output frequency is stable. | ||
| 4479 | */ | ||
| 4480 | #define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) | ||
| 4481 | /*! @} */ | ||
| 4482 | |||
| 4483 | /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ | ||
| 4484 | /*! @{ */ | ||
| 4485 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) | ||
| 4486 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) | ||
| 4487 | /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. | ||
| 4488 | * 0b0..BOD VBAT interrupt is disabled. | ||
| 4489 | * 0b1..BOD VBAT interrupt is enabled. | ||
| 4490 | */ | ||
| 4491 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) | ||
| 4492 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) | ||
| 4493 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) | ||
| 4494 | /*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 4495 | */ | ||
| 4496 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) | ||
| 4497 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) | ||
| 4498 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) | ||
| 4499 | /*! BODCORE_INT_ENABLE - BOD CORE interrupt control. | ||
| 4500 | * 0b0..BOD CORE interrupt is disabled. | ||
| 4501 | * 0b1..BOD CORE interrupt is enabled. | ||
| 4502 | */ | ||
| 4503 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) | ||
| 4504 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) | ||
| 4505 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) | ||
| 4506 | /*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 4507 | */ | ||
| 4508 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) | ||
| 4509 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) | ||
| 4510 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) | ||
| 4511 | /*! DCDC_INT_ENABLE - DCDC interrupt control. | ||
| 4512 | * 0b0..DCDC interrupt is disabled. | ||
| 4513 | * 0b1..DCDC interrupt is enabled. | ||
| 4514 | */ | ||
| 4515 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) | ||
| 4516 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) | ||
| 4517 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) | ||
| 4518 | /*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 4519 | */ | ||
| 4520 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) | ||
| 4521 | /*! @} */ | ||
| 4522 | |||
| 4523 | /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ | ||
| 4524 | /*! @{ */ | ||
| 4525 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) | ||
| 4526 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) | ||
| 4527 | /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. | ||
| 4528 | * 0b0..No interrupt pending.. | ||
| 4529 | * 0b1..Interrupt pending.. | ||
| 4530 | */ | ||
| 4531 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) | ||
| 4532 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) | ||
| 4533 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) | ||
| 4534 | /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. | ||
| 4535 | * 0b0..No interrupt pending.. | ||
| 4536 | * 0b1..Interrupt pending.. | ||
| 4537 | */ | ||
| 4538 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) | ||
| 4539 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) | ||
| 4540 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) | ||
| 4541 | /*! BODVBAT_VAL - Current value of BOD VBAT power status output. | ||
| 4542 | * 0b0..VBAT voltage level is below the threshold. | ||
| 4543 | * 0b1..VBAT voltage level is above the threshold. | ||
| 4544 | */ | ||
| 4545 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) | ||
| 4546 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) | ||
| 4547 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) | ||
| 4548 | /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. | ||
| 4549 | * 0b0..No interrupt pending.. | ||
| 4550 | * 0b1..Interrupt pending.. | ||
| 4551 | */ | ||
| 4552 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) | ||
| 4553 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) | ||
| 4554 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) | ||
| 4555 | /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. | ||
| 4556 | * 0b0..No interrupt pending.. | ||
| 4557 | * 0b1..Interrupt pending.. | ||
| 4558 | */ | ||
| 4559 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) | ||
| 4560 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) | ||
| 4561 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) | ||
| 4562 | /*! BODCORE_VAL - Current value of BOD CORE power status output. | ||
| 4563 | * 0b0..CORE voltage level is below the threshold. | ||
| 4564 | * 0b1..CORE voltage level is above the threshold. | ||
| 4565 | */ | ||
| 4566 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) | ||
| 4567 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) | ||
| 4568 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) | ||
| 4569 | /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. | ||
| 4570 | * 0b0..No interrupt pending.. | ||
| 4571 | * 0b1..Interrupt pending.. | ||
| 4572 | */ | ||
| 4573 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) | ||
| 4574 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) | ||
| 4575 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) | ||
| 4576 | /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. | ||
| 4577 | * 0b0..No interrupt pending.. | ||
| 4578 | * 0b1..Interrupt pending.. | ||
| 4579 | */ | ||
| 4580 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) | ||
| 4581 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) | ||
| 4582 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) | ||
| 4583 | /*! DCDC_VAL - Current value of DCDC power status output. | ||
| 4584 | * 0b0..DCDC output Voltage is below the targeted regulation level. | ||
| 4585 | * 0b1..DCDC output Voltage is above the targeted regulation level. | ||
| 4586 | */ | ||
| 4587 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) | ||
| 4588 | /*! @} */ | ||
| 4589 | |||
| 4590 | /*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ | ||
| 4591 | /*! @{ */ | ||
| 4592 | #define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) | ||
| 4593 | #define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) | ||
| 4594 | /*! SL - Select short or long ringo (for all ringos types). | ||
| 4595 | * 0b0..Select short ringo (few elements). | ||
| 4596 | * 0b1..Select long ringo (many elements). | ||
| 4597 | */ | ||
| 4598 | #define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) | ||
| 4599 | #define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) | ||
| 4600 | #define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) | ||
| 4601 | /*! FS - Ringo frequency output divider. | ||
| 4602 | * 0b0..High frequency output (frequency lower than 100 MHz). | ||
| 4603 | * 0b1..Low frequency output (frequency lower than 10 MHz). | ||
| 4604 | */ | ||
| 4605 | #define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) | ||
| 4606 | #define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) | ||
| 4607 | #define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) | ||
| 4608 | /*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. | ||
| 4609 | * 0b00..Normal mode. | ||
| 4610 | * 0b01..P-Monitor mode. Measure with weak P transistor. | ||
| 4611 | * 0b10..P-Monitor mode. Measure with weak N transistor. | ||
| 4612 | * 0b11..Don't use. | ||
| 4613 | */ | ||
| 4614 | #define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) | ||
| 4615 | #define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) | ||
| 4616 | #define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) | ||
| 4617 | /*! PD - Ringo module Power control. | ||
| 4618 | * 0b0..The Ringo module is enabled. | ||
| 4619 | * 0b1..The Ringo module is disabled. | ||
| 4620 | */ | ||
| 4621 | #define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) | ||
| 4622 | #define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) | ||
| 4623 | #define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) | ||
| 4624 | /*! E_ND0 - First NAND2-based ringo control. | ||
| 4625 | * 0b0..First NAND2-based ringo is disabled. | ||
| 4626 | * 0b1..First NAND2-based ringo is enabled. | ||
| 4627 | */ | ||
| 4628 | #define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) | ||
| 4629 | #define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) | ||
| 4630 | #define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) | ||
| 4631 | /*! E_ND1 - Second NAND2-based ringo control. | ||
| 4632 | * 0b0..Second NAND2-based ringo is disabled. | ||
| 4633 | * 0b1..Second NAND2-based ringo is enabled. | ||
| 4634 | */ | ||
| 4635 | #define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) | ||
| 4636 | #define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) | ||
| 4637 | #define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) | ||
| 4638 | /*! E_NR0 - First NOR2-based ringo control. | ||
| 4639 | * 0b0..First NOR2-based ringo is disabled. | ||
| 4640 | * 0b1..First NOR2-based ringo is enabled. | ||
| 4641 | */ | ||
| 4642 | #define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) | ||
| 4643 | #define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) | ||
| 4644 | #define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) | ||
| 4645 | /*! E_NR1 - Second NOR2-based ringo control. | ||
| 4646 | * 0b0..Second NORD2-based ringo is disabled. | ||
| 4647 | * 0b1..Second NORD2-based ringo is enabled. | ||
| 4648 | */ | ||
| 4649 | #define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) | ||
| 4650 | #define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) | ||
| 4651 | #define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) | ||
| 4652 | /*! E_IV0 - First Inverter-based ringo control. | ||
| 4653 | * 0b0..First INV-based ringo is disabled. | ||
| 4654 | * 0b1..First INV-based ringo is enabled. | ||
| 4655 | */ | ||
| 4656 | #define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) | ||
| 4657 | #define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) | ||
| 4658 | #define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) | ||
| 4659 | /*! E_IV1 - Second Inverter-based ringo control. | ||
| 4660 | * 0b0..Second INV-based ringo is disabled. | ||
| 4661 | * 0b1..Second INV-based ringo is enabled. | ||
| 4662 | */ | ||
| 4663 | #define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) | ||
| 4664 | #define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) | ||
| 4665 | #define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) | ||
| 4666 | /*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. | ||
| 4667 | * 0b0..First PN-based ringo is disabled. | ||
| 4668 | * 0b1..First PN-based ringo is enabled. | ||
| 4669 | */ | ||
| 4670 | #define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) | ||
| 4671 | #define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) | ||
| 4672 | #define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) | ||
| 4673 | /*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. | ||
| 4674 | * 0b0..Second PN-based ringo is disabled. | ||
| 4675 | * 0b1..Second PN-based ringo is enabled. | ||
| 4676 | */ | ||
| 4677 | #define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) | ||
| 4678 | #define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) | ||
| 4679 | #define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) | ||
| 4680 | /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) | ||
| 4681 | */ | ||
| 4682 | #define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) | ||
| 4683 | #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) | ||
| 4684 | #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) | ||
| 4685 | /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider | ||
| 4686 | * value, cleared when the change is complete. | ||
| 4687 | */ | ||
| 4688 | #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) | ||
| 4689 | /*! @} */ | ||
| 4690 | |||
| 4691 | /*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ | ||
| 4692 | /*! @{ */ | ||
| 4693 | #define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) | ||
| 4694 | #define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) | ||
| 4695 | /*! S - Select short or long ringo (for all ringos types). | ||
| 4696 | * 0b0..Select short ringo (few elements). | ||
| 4697 | * 0b1..Select long ringo (many elements). | ||
| 4698 | */ | ||
| 4699 | #define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) | ||
| 4700 | #define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) | ||
| 4701 | #define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) | ||
| 4702 | /*! FS - Ringo frequency output divider. | ||
| 4703 | * 0b0..High frequency output (frequency lower than 100 MHz). | ||
| 4704 | * 0b1..Low frequency output (frequency lower than 10 MHz). | ||
| 4705 | */ | ||
| 4706 | #define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) | ||
| 4707 | #define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) | ||
| 4708 | #define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) | ||
| 4709 | /*! PD - Ringo module Power control. | ||
| 4710 | * 0b0..The Ringo module is enabled. | ||
| 4711 | * 0b1..The Ringo module is disabled. | ||
| 4712 | */ | ||
| 4713 | #define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) | ||
| 4714 | #define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) | ||
| 4715 | #define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) | ||
| 4716 | /*! E_R24 - . | ||
| 4717 | * 0b0..Ringo is disabled. | ||
| 4718 | * 0b1..Ringo is enabled. | ||
| 4719 | */ | ||
| 4720 | #define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) | ||
| 4721 | #define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) | ||
| 4722 | #define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) | ||
| 4723 | /*! E_R35 - . | ||
| 4724 | * 0b0..Ringo is disabled. | ||
| 4725 | * 0b1..Ringo is enabled. | ||
| 4726 | */ | ||
| 4727 | #define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) | ||
| 4728 | #define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) | ||
| 4729 | #define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) | ||
| 4730 | /*! E_M2 - Metal 2 (M2) monitor control. | ||
| 4731 | * 0b0..Ringo is disabled. | ||
| 4732 | * 0b1..Ringo is enabled. | ||
| 4733 | */ | ||
| 4734 | #define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) | ||
| 4735 | #define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) | ||
| 4736 | #define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) | ||
| 4737 | /*! E_M3 - Metal 3 (M3) monitor control. | ||
| 4738 | * 0b0..Ringo is disabled. | ||
| 4739 | * 0b1..Ringo is enabled. | ||
| 4740 | */ | ||
| 4741 | #define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) | ||
| 4742 | #define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) | ||
| 4743 | #define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) | ||
| 4744 | /*! E_M4 - Metal 4 (M4) monitor control. | ||
| 4745 | * 0b0..Ringo is disabled. | ||
| 4746 | * 0b1..Ringo is enabled. | ||
| 4747 | */ | ||
| 4748 | #define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) | ||
| 4749 | #define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) | ||
| 4750 | #define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) | ||
| 4751 | /*! E_M5 - Metal 5 (M5) monitor control. | ||
| 4752 | * 0b0..Ringo is disabled. | ||
| 4753 | * 0b1..Ringo is enabled. | ||
| 4754 | */ | ||
| 4755 | #define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) | ||
| 4756 | #define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) | ||
| 4757 | #define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) | ||
| 4758 | /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) | ||
| 4759 | */ | ||
| 4760 | #define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) | ||
| 4761 | #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) | ||
| 4762 | #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) | ||
| 4763 | /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider | ||
| 4764 | * value, cleared when the change is complete. | ||
| 4765 | */ | ||
| 4766 | #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) | ||
| 4767 | /*! @} */ | ||
| 4768 | |||
| 4769 | /*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ | ||
| 4770 | /*! @{ */ | ||
| 4771 | #define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) | ||
| 4772 | #define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) | ||
| 4773 | /*! S - Select short or long ringo (for all ringos types). | ||
| 4774 | * 0b0..Select short ringo (few elements). | ||
| 4775 | * 0b1..Select long ringo (many elements). | ||
| 4776 | */ | ||
| 4777 | #define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) | ||
| 4778 | #define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) | ||
| 4779 | #define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) | ||
| 4780 | /*! FS - Ringo frequency output divider. | ||
| 4781 | * 0b0..High frequency output (frequency lower than 100 MHz). | ||
| 4782 | * 0b1..Low frequency output (frequency lower than 10 MHz). | ||
| 4783 | */ | ||
| 4784 | #define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) | ||
| 4785 | #define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) | ||
| 4786 | #define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) | ||
| 4787 | /*! PD - Ringo module Power control. | ||
| 4788 | * 0b0..The Ringo module is enabled. | ||
| 4789 | * 0b1..The Ringo module is disabled. | ||
| 4790 | */ | ||
| 4791 | #define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) | ||
| 4792 | #define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) | ||
| 4793 | #define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) | ||
| 4794 | /*! E_R24 - . | ||
| 4795 | * 0b0..Ringo is disabled. | ||
| 4796 | * 0b1..Ringo is enabled. | ||
| 4797 | */ | ||
| 4798 | #define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) | ||
| 4799 | #define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) | ||
| 4800 | #define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) | ||
| 4801 | /*! E_R35 - . | ||
| 4802 | * 0b0..Ringo is disabled. | ||
| 4803 | * 0b1..Ringo is enabled. | ||
| 4804 | */ | ||
| 4805 | #define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) | ||
| 4806 | #define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) | ||
| 4807 | #define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) | ||
| 4808 | /*! E_M2 - Metal 2 (M2) monitor control. | ||
| 4809 | * 0b0..Ringo is disabled. | ||
| 4810 | * 0b1..Ringo is enabled. | ||
| 4811 | */ | ||
| 4812 | #define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) | ||
| 4813 | #define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) | ||
| 4814 | #define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) | ||
| 4815 | /*! E_M3 - Metal 3 (M3) monitor control. | ||
| 4816 | * 0b0..Ringo is disabled. | ||
| 4817 | * 0b1..Ringo is enabled. | ||
| 4818 | */ | ||
| 4819 | #define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) | ||
| 4820 | #define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) | ||
| 4821 | #define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) | ||
| 4822 | /*! E_M4 - Metal 4 (M4) monitor control. | ||
| 4823 | * 0b0..Ringo is disabled. | ||
| 4824 | * 0b1..Ringo is enabled. | ||
| 4825 | */ | ||
| 4826 | #define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) | ||
| 4827 | #define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) | ||
| 4828 | #define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) | ||
| 4829 | /*! E_M5 - Metal 5 (M5) monitor control. | ||
| 4830 | * 0b0..Ringo is disabled. | ||
| 4831 | * 0b1..Ringo is enabled. | ||
| 4832 | */ | ||
| 4833 | #define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) | ||
| 4834 | #define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) | ||
| 4835 | #define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) | ||
| 4836 | /*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) | ||
| 4837 | */ | ||
| 4838 | #define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) | ||
| 4839 | #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) | ||
| 4840 | #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) | ||
| 4841 | /*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider | ||
| 4842 | * value, cleared when the change is complete. | ||
| 4843 | */ | ||
| 4844 | #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) | ||
| 4845 | /*! @} */ | ||
| 4846 | |||
| 4847 | /*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ | ||
| 4848 | /*! @{ */ | ||
| 4849 | #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) | ||
| 4850 | #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) | ||
| 4851 | /*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. | ||
| 4852 | */ | ||
| 4853 | #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) | ||
| 4854 | #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) | ||
| 4855 | #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) | ||
| 4856 | /*! usb_id_ext - Override value for ID if using external detectors. | ||
| 4857 | */ | ||
| 4858 | #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) | ||
| 4859 | /*! @} */ | ||
| 4860 | |||
| 4861 | |||
| 4862 | /*! | ||
| 4863 | * @} | ||
| 4864 | */ /* end of group ANACTRL_Register_Masks */ | ||
| 4865 | |||
| 4866 | |||
| 4867 | /* ANACTRL - Peripheral instance base addresses */ | ||
| 4868 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 4869 | /** Peripheral ANACTRL base address */ | ||
| 4870 | #define ANACTRL_BASE (0x50013000u) | ||
| 4871 | /** Peripheral ANACTRL base address */ | ||
| 4872 | #define ANACTRL_BASE_NS (0x40013000u) | ||
| 4873 | /** Peripheral ANACTRL base pointer */ | ||
| 4874 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 4875 | /** Peripheral ANACTRL base pointer */ | ||
| 4876 | #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) | ||
| 4877 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 4878 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 4879 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 4880 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 4881 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 4882 | #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } | ||
| 4883 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 4884 | #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } | ||
| 4885 | #else | ||
| 4886 | /** Peripheral ANACTRL base address */ | ||
| 4887 | #define ANACTRL_BASE (0x40013000u) | ||
| 4888 | /** Peripheral ANACTRL base pointer */ | ||
| 4889 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 4890 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 4891 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 4892 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 4893 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 4894 | #endif | ||
| 4895 | |||
| 4896 | /*! | ||
| 4897 | * @} | ||
| 4898 | */ /* end of group ANACTRL_Peripheral_Access_Layer */ | ||
| 4899 | |||
| 4900 | |||
| 4901 | /* ---------------------------------------------------------------------------- | ||
| 4902 | -- CRC Peripheral Access Layer | ||
| 4903 | ---------------------------------------------------------------------------- */ | ||
| 4904 | |||
| 4905 | /*! | ||
| 4906 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 4907 | * @{ | ||
| 4908 | */ | ||
| 4909 | |||
| 4910 | /** CRC - Register Layout Typedef */ | ||
| 4911 | typedef struct { | ||
| 4912 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ | ||
| 4913 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ | ||
| 4914 | union { /* offset: 0x8 */ | ||
| 4915 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ | ||
| 4916 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ | ||
| 4917 | }; | ||
| 4918 | } CRC_Type; | ||
| 4919 | |||
| 4920 | /* ---------------------------------------------------------------------------- | ||
| 4921 | -- CRC Register Masks | ||
| 4922 | ---------------------------------------------------------------------------- */ | ||
| 4923 | |||
| 4924 | /*! | ||
| 4925 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 4926 | * @{ | ||
| 4927 | */ | ||
| 4928 | |||
| 4929 | /*! @name MODE - CRC mode register */ | ||
| 4930 | /*! @{ */ | ||
| 4931 | #define CRC_MODE_CRC_POLY_MASK (0x3U) | ||
| 4932 | #define CRC_MODE_CRC_POLY_SHIFT (0U) | ||
| 4933 | /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial | ||
| 4934 | */ | ||
| 4935 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) | ||
| 4936 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) | ||
| 4937 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) | ||
| 4938 | /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) | ||
| 4939 | */ | ||
| 4940 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) | ||
| 4941 | #define CRC_MODE_CMPL_WR_MASK (0x8U) | ||
| 4942 | #define CRC_MODE_CMPL_WR_SHIFT (3U) | ||
| 4943 | /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA | ||
| 4944 | */ | ||
| 4945 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) | ||
| 4946 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) | ||
| 4947 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) | ||
| 4948 | /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM | ||
| 4949 | */ | ||
| 4950 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) | ||
| 4951 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) | ||
| 4952 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) | ||
| 4953 | /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM | ||
| 4954 | */ | ||
| 4955 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) | ||
| 4956 | /*! @} */ | ||
| 4957 | |||
| 4958 | /*! @name SEED - CRC seed register */ | ||
| 4959 | /*! @{ */ | ||
| 4960 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) | ||
| 4961 | #define CRC_SEED_CRC_SEED_SHIFT (0U) | ||
| 4962 | /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with | ||
| 4963 | * selected bit order and 1's complement pre-processes. A write access to this register will | ||
| 4964 | * overrule the CRC calculation in progresses. | ||
| 4965 | */ | ||
| 4966 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) | ||
| 4967 | /*! @} */ | ||
| 4968 | |||
| 4969 | /*! @name SUM - CRC checksum register */ | ||
| 4970 | /*! @{ */ | ||
| 4971 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) | ||
| 4972 | #define CRC_SUM_CRC_SUM_SHIFT (0U) | ||
| 4973 | /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. | ||
| 4974 | */ | ||
| 4975 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) | ||
| 4976 | /*! @} */ | ||
| 4977 | |||
| 4978 | /*! @name WR_DATA - CRC data register */ | ||
| 4979 | /*! @{ */ | ||
| 4980 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) | ||
| 4981 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) | ||
| 4982 | /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with | ||
| 4983 | * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and | ||
| 4984 | * accept back-to-back transactions. | ||
| 4985 | */ | ||
| 4986 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) | ||
| 4987 | /*! @} */ | ||
| 4988 | |||
| 4989 | |||
| 4990 | /*! | ||
| 4991 | * @} | ||
| 4992 | */ /* end of group CRC_Register_Masks */ | ||
| 4993 | |||
| 4994 | |||
| 4995 | /* CRC - Peripheral instance base addresses */ | ||
| 4996 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 4997 | /** Peripheral CRC_ENGINE base address */ | ||
| 4998 | #define CRC_ENGINE_BASE (0x50095000u) | ||
| 4999 | /** Peripheral CRC_ENGINE base address */ | ||
| 5000 | #define CRC_ENGINE_BASE_NS (0x40095000u) | ||
| 5001 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5002 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5003 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5004 | #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) | ||
| 5005 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5006 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5007 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5008 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5009 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5010 | #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } | ||
| 5011 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5012 | #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } | ||
| 5013 | #else | ||
| 5014 | /** Peripheral CRC_ENGINE base address */ | ||
| 5015 | #define CRC_ENGINE_BASE (0x40095000u) | ||
| 5016 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5017 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5018 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5019 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5020 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5021 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5022 | #endif | ||
| 5023 | |||
| 5024 | /*! | ||
| 5025 | * @} | ||
| 5026 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 5027 | |||
| 5028 | |||
| 5029 | /* ---------------------------------------------------------------------------- | ||
| 5030 | -- CTIMER Peripheral Access Layer | ||
| 5031 | ---------------------------------------------------------------------------- */ | ||
| 5032 | |||
| 5033 | /*! | ||
| 5034 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer | ||
| 5035 | * @{ | ||
| 5036 | */ | ||
| 5037 | |||
| 5038 | /** CTIMER - Register Layout Typedef */ | ||
| 5039 | typedef struct { | ||
| 5040 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ | ||
| 5041 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ | ||
| 5042 | __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ | ||
| 5043 | __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ | ||
| 5044 | __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ | ||
| 5045 | __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ | ||
| 5046 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ | ||
| 5047 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ | ||
| 5048 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ | ||
| 5049 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ | ||
| 5050 | uint8_t RESERVED_0[48]; | ||
| 5051 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ | ||
| 5052 | __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ | ||
| 5053 | __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ | ||
| 5054 | } CTIMER_Type; | ||
| 5055 | |||
| 5056 | /* ---------------------------------------------------------------------------- | ||
| 5057 | -- CTIMER Register Masks | ||
| 5058 | ---------------------------------------------------------------------------- */ | ||
| 5059 | |||
| 5060 | /*! | ||
| 5061 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks | ||
| 5062 | * @{ | ||
| 5063 | */ | ||
| 5064 | |||
| 5065 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ | ||
| 5066 | /*! @{ */ | ||
| 5067 | #define CTIMER_IR_MR0INT_MASK (0x1U) | ||
| 5068 | #define CTIMER_IR_MR0INT_SHIFT (0U) | ||
| 5069 | /*! MR0INT - Interrupt flag for match channel 0. | ||
| 5070 | */ | ||
| 5071 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) | ||
| 5072 | #define CTIMER_IR_MR1INT_MASK (0x2U) | ||
| 5073 | #define CTIMER_IR_MR1INT_SHIFT (1U) | ||
| 5074 | /*! MR1INT - Interrupt flag for match channel 1. | ||
| 5075 | */ | ||
| 5076 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) | ||
| 5077 | #define CTIMER_IR_MR2INT_MASK (0x4U) | ||
| 5078 | #define CTIMER_IR_MR2INT_SHIFT (2U) | ||
| 5079 | /*! MR2INT - Interrupt flag for match channel 2. | ||
| 5080 | */ | ||
| 5081 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) | ||
| 5082 | #define CTIMER_IR_MR3INT_MASK (0x8U) | ||
| 5083 | #define CTIMER_IR_MR3INT_SHIFT (3U) | ||
| 5084 | /*! MR3INT - Interrupt flag for match channel 3. | ||
| 5085 | */ | ||
| 5086 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) | ||
| 5087 | #define CTIMER_IR_CR0INT_MASK (0x10U) | ||
| 5088 | #define CTIMER_IR_CR0INT_SHIFT (4U) | ||
| 5089 | /*! CR0INT - Interrupt flag for capture channel 0 event. | ||
| 5090 | */ | ||
| 5091 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) | ||
| 5092 | #define CTIMER_IR_CR1INT_MASK (0x20U) | ||
| 5093 | #define CTIMER_IR_CR1INT_SHIFT (5U) | ||
| 5094 | /*! CR1INT - Interrupt flag for capture channel 1 event. | ||
| 5095 | */ | ||
| 5096 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) | ||
| 5097 | #define CTIMER_IR_CR2INT_MASK (0x40U) | ||
| 5098 | #define CTIMER_IR_CR2INT_SHIFT (6U) | ||
| 5099 | /*! CR2INT - Interrupt flag for capture channel 2 event. | ||
| 5100 | */ | ||
| 5101 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) | ||
| 5102 | #define CTIMER_IR_CR3INT_MASK (0x80U) | ||
| 5103 | #define CTIMER_IR_CR3INT_SHIFT (7U) | ||
| 5104 | /*! CR3INT - Interrupt flag for capture channel 3 event. | ||
| 5105 | */ | ||
| 5106 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) | ||
| 5107 | /*! @} */ | ||
| 5108 | |||
| 5109 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ | ||
| 5110 | /*! @{ */ | ||
| 5111 | #define CTIMER_TCR_CEN_MASK (0x1U) | ||
| 5112 | #define CTIMER_TCR_CEN_SHIFT (0U) | ||
| 5113 | /*! CEN - Counter enable. | ||
| 5114 | * 0b0..Disabled.The counters are disabled. | ||
| 5115 | * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. | ||
| 5116 | */ | ||
| 5117 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) | ||
| 5118 | #define CTIMER_TCR_CRST_MASK (0x2U) | ||
| 5119 | #define CTIMER_TCR_CRST_SHIFT (1U) | ||
| 5120 | /*! CRST - Counter reset. | ||
| 5121 | * 0b0..Disabled. Do nothing. | ||
| 5122 | * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of | ||
| 5123 | * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. | ||
| 5124 | */ | ||
| 5125 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) | ||
| 5126 | /*! @} */ | ||
| 5127 | |||
| 5128 | /*! @name TC - Timer Counter */ | ||
| 5129 | /*! @{ */ | ||
| 5130 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) | ||
| 5131 | #define CTIMER_TC_TCVAL_SHIFT (0U) | ||
| 5132 | /*! TCVAL - Timer counter value. | ||
| 5133 | */ | ||
| 5134 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) | ||
| 5135 | /*! @} */ | ||
| 5136 | |||
| 5137 | /*! @name PR - Prescale Register */ | ||
| 5138 | /*! @{ */ | ||
| 5139 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) | ||
| 5140 | #define CTIMER_PR_PRVAL_SHIFT (0U) | ||
| 5141 | /*! PRVAL - Prescale counter value. | ||
| 5142 | */ | ||
| 5143 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) | ||
| 5144 | /*! @} */ | ||
| 5145 | |||
| 5146 | /*! @name PC - Prescale Counter */ | ||
| 5147 | /*! @{ */ | ||
| 5148 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) | ||
| 5149 | #define CTIMER_PC_PCVAL_SHIFT (0U) | ||
| 5150 | /*! PCVAL - Prescale counter value. | ||
| 5151 | */ | ||
| 5152 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) | ||
| 5153 | /*! @} */ | ||
| 5154 | |||
| 5155 | /*! @name MCR - Match Control Register */ | ||
| 5156 | /*! @{ */ | ||
| 5157 | #define CTIMER_MCR_MR0I_MASK (0x1U) | ||
| 5158 | #define CTIMER_MCR_MR0I_SHIFT (0U) | ||
| 5159 | /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. | ||
| 5160 | */ | ||
| 5161 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) | ||
| 5162 | #define CTIMER_MCR_MR0R_MASK (0x2U) | ||
| 5163 | #define CTIMER_MCR_MR0R_SHIFT (1U) | ||
| 5164 | /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. | ||
| 5165 | */ | ||
| 5166 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) | ||
| 5167 | #define CTIMER_MCR_MR0S_MASK (0x4U) | ||
| 5168 | #define CTIMER_MCR_MR0S_SHIFT (2U) | ||
| 5169 | /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. | ||
| 5170 | */ | ||
| 5171 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) | ||
| 5172 | #define CTIMER_MCR_MR1I_MASK (0x8U) | ||
| 5173 | #define CTIMER_MCR_MR1I_SHIFT (3U) | ||
| 5174 | /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. | ||
| 5175 | */ | ||
| 5176 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) | ||
| 5177 | #define CTIMER_MCR_MR1R_MASK (0x10U) | ||
| 5178 | #define CTIMER_MCR_MR1R_SHIFT (4U) | ||
| 5179 | /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. | ||
| 5180 | */ | ||
| 5181 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) | ||
| 5182 | #define CTIMER_MCR_MR1S_MASK (0x20U) | ||
| 5183 | #define CTIMER_MCR_MR1S_SHIFT (5U) | ||
| 5184 | /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. | ||
| 5185 | */ | ||
| 5186 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) | ||
| 5187 | #define CTIMER_MCR_MR2I_MASK (0x40U) | ||
| 5188 | #define CTIMER_MCR_MR2I_SHIFT (6U) | ||
| 5189 | /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. | ||
| 5190 | */ | ||
| 5191 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) | ||
| 5192 | #define CTIMER_MCR_MR2R_MASK (0x80U) | ||
| 5193 | #define CTIMER_MCR_MR2R_SHIFT (7U) | ||
| 5194 | /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. | ||
| 5195 | */ | ||
| 5196 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) | ||
| 5197 | #define CTIMER_MCR_MR2S_MASK (0x100U) | ||
| 5198 | #define CTIMER_MCR_MR2S_SHIFT (8U) | ||
| 5199 | /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. | ||
| 5200 | */ | ||
| 5201 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) | ||
| 5202 | #define CTIMER_MCR_MR3I_MASK (0x200U) | ||
| 5203 | #define CTIMER_MCR_MR3I_SHIFT (9U) | ||
| 5204 | /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. | ||
| 5205 | */ | ||
| 5206 | #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) | ||
| 5207 | #define CTIMER_MCR_MR3R_MASK (0x400U) | ||
| 5208 | #define CTIMER_MCR_MR3R_SHIFT (10U) | ||
| 5209 | /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. | ||
| 5210 | */ | ||
| 5211 | #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) | ||
| 5212 | #define CTIMER_MCR_MR3S_MASK (0x800U) | ||
| 5213 | #define CTIMER_MCR_MR3S_SHIFT (11U) | ||
| 5214 | /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. | ||
| 5215 | */ | ||
| 5216 | #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) | ||
| 5217 | #define CTIMER_MCR_MR0RL_MASK (0x1000000U) | ||
| 5218 | #define CTIMER_MCR_MR0RL_SHIFT (24U) | ||
| 5219 | /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero | ||
| 5220 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 5221 | */ | ||
| 5222 | #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) | ||
| 5223 | #define CTIMER_MCR_MR1RL_MASK (0x2000000U) | ||
| 5224 | #define CTIMER_MCR_MR1RL_SHIFT (25U) | ||
| 5225 | /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero | ||
| 5226 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 5227 | */ | ||
| 5228 | #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) | ||
| 5229 | #define CTIMER_MCR_MR2RL_MASK (0x4000000U) | ||
| 5230 | #define CTIMER_MCR_MR2RL_SHIFT (26U) | ||
| 5231 | /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero | ||
| 5232 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 5233 | */ | ||
| 5234 | #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) | ||
| 5235 | #define CTIMER_MCR_MR3RL_MASK (0x8000000U) | ||
| 5236 | #define CTIMER_MCR_MR3RL_SHIFT (27U) | ||
| 5237 | /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero | ||
| 5238 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 5239 | */ | ||
| 5240 | #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) | ||
| 5241 | /*! @} */ | ||
| 5242 | |||
| 5243 | /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ | ||
| 5244 | /*! @{ */ | ||
| 5245 | #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) | ||
| 5246 | #define CTIMER_MR_MATCH_SHIFT (0U) | ||
| 5247 | /*! MATCH - Timer counter match value. | ||
| 5248 | */ | ||
| 5249 | #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) | ||
| 5250 | /*! @} */ | ||
| 5251 | |||
| 5252 | /* The count of CTIMER_MR */ | ||
| 5253 | #define CTIMER_MR_COUNT (4U) | ||
| 5254 | |||
| 5255 | /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ | ||
| 5256 | /*! @{ */ | ||
| 5257 | #define CTIMER_CCR_CAP0RE_MASK (0x1U) | ||
| 5258 | #define CTIMER_CCR_CAP0RE_SHIFT (0U) | ||
| 5259 | /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with | ||
| 5260 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5261 | */ | ||
| 5262 | #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) | ||
| 5263 | #define CTIMER_CCR_CAP0FE_MASK (0x2U) | ||
| 5264 | #define CTIMER_CCR_CAP0FE_SHIFT (1U) | ||
| 5265 | /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with | ||
| 5266 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5267 | */ | ||
| 5268 | #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) | ||
| 5269 | #define CTIMER_CCR_CAP0I_MASK (0x4U) | ||
| 5270 | #define CTIMER_CCR_CAP0I_SHIFT (2U) | ||
| 5271 | /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. | ||
| 5272 | */ | ||
| 5273 | #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) | ||
| 5274 | #define CTIMER_CCR_CAP1RE_MASK (0x8U) | ||
| 5275 | #define CTIMER_CCR_CAP1RE_SHIFT (3U) | ||
| 5276 | /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with | ||
| 5277 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5278 | */ | ||
| 5279 | #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) | ||
| 5280 | #define CTIMER_CCR_CAP1FE_MASK (0x10U) | ||
| 5281 | #define CTIMER_CCR_CAP1FE_SHIFT (4U) | ||
| 5282 | /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with | ||
| 5283 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5284 | */ | ||
| 5285 | #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) | ||
| 5286 | #define CTIMER_CCR_CAP1I_MASK (0x20U) | ||
| 5287 | #define CTIMER_CCR_CAP1I_SHIFT (5U) | ||
| 5288 | /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. | ||
| 5289 | */ | ||
| 5290 | #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) | ||
| 5291 | #define CTIMER_CCR_CAP2RE_MASK (0x40U) | ||
| 5292 | #define CTIMER_CCR_CAP2RE_SHIFT (6U) | ||
| 5293 | /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with | ||
| 5294 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5295 | */ | ||
| 5296 | #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) | ||
| 5297 | #define CTIMER_CCR_CAP2FE_MASK (0x80U) | ||
| 5298 | #define CTIMER_CCR_CAP2FE_SHIFT (7U) | ||
| 5299 | /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with | ||
| 5300 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5301 | */ | ||
| 5302 | #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) | ||
| 5303 | #define CTIMER_CCR_CAP2I_MASK (0x100U) | ||
| 5304 | #define CTIMER_CCR_CAP2I_SHIFT (8U) | ||
| 5305 | /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. | ||
| 5306 | */ | ||
| 5307 | #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) | ||
| 5308 | #define CTIMER_CCR_CAP3RE_MASK (0x200U) | ||
| 5309 | #define CTIMER_CCR_CAP3RE_SHIFT (9U) | ||
| 5310 | /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with | ||
| 5311 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5312 | */ | ||
| 5313 | #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) | ||
| 5314 | #define CTIMER_CCR_CAP3FE_MASK (0x400U) | ||
| 5315 | #define CTIMER_CCR_CAP3FE_SHIFT (10U) | ||
| 5316 | /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with | ||
| 5317 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 5318 | */ | ||
| 5319 | #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) | ||
| 5320 | #define CTIMER_CCR_CAP3I_MASK (0x800U) | ||
| 5321 | #define CTIMER_CCR_CAP3I_SHIFT (11U) | ||
| 5322 | /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. | ||
| 5323 | */ | ||
| 5324 | #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) | ||
| 5325 | /*! @} */ | ||
| 5326 | |||
| 5327 | /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ | ||
| 5328 | /*! @{ */ | ||
| 5329 | #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) | ||
| 5330 | #define CTIMER_CR_CAP_SHIFT (0U) | ||
| 5331 | /*! CAP - Timer counter capture value. | ||
| 5332 | */ | ||
| 5333 | #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) | ||
| 5334 | /*! @} */ | ||
| 5335 | |||
| 5336 | /* The count of CTIMER_CR */ | ||
| 5337 | #define CTIMER_CR_COUNT (4U) | ||
| 5338 | |||
| 5339 | /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ | ||
| 5340 | /*! @{ */ | ||
| 5341 | #define CTIMER_EMR_EM0_MASK (0x1U) | ||
| 5342 | #define CTIMER_EMR_EM0_SHIFT (0U) | ||
| 5343 | /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output | ||
| 5344 | * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, | ||
| 5345 | * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if | ||
| 5346 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 5347 | */ | ||
| 5348 | #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) | ||
| 5349 | #define CTIMER_EMR_EM1_MASK (0x2U) | ||
| 5350 | #define CTIMER_EMR_EM1_SHIFT (1U) | ||
| 5351 | /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output | ||
| 5352 | * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, | ||
| 5353 | * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if | ||
| 5354 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 5355 | */ | ||
| 5356 | #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) | ||
| 5357 | #define CTIMER_EMR_EM2_MASK (0x4U) | ||
| 5358 | #define CTIMER_EMR_EM2_SHIFT (2U) | ||
| 5359 | /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output | ||
| 5360 | * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, | ||
| 5361 | * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if | ||
| 5362 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 5363 | */ | ||
| 5364 | #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) | ||
| 5365 | #define CTIMER_EMR_EM3_MASK (0x8U) | ||
| 5366 | #define CTIMER_EMR_EM3_SHIFT (3U) | ||
| 5367 | /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output | ||
| 5368 | * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, | ||
| 5369 | * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins | ||
| 5370 | * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 5371 | */ | ||
| 5372 | #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) | ||
| 5373 | #define CTIMER_EMR_EMC0_MASK (0x30U) | ||
| 5374 | #define CTIMER_EMR_EMC0_SHIFT (4U) | ||
| 5375 | /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. | ||
| 5376 | * 0b00..Do Nothing. | ||
| 5377 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). | ||
| 5378 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). | ||
| 5379 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 5380 | */ | ||
| 5381 | #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) | ||
| 5382 | #define CTIMER_EMR_EMC1_MASK (0xC0U) | ||
| 5383 | #define CTIMER_EMR_EMC1_SHIFT (6U) | ||
| 5384 | /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. | ||
| 5385 | * 0b00..Do Nothing. | ||
| 5386 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). | ||
| 5387 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). | ||
| 5388 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 5389 | */ | ||
| 5390 | #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) | ||
| 5391 | #define CTIMER_EMR_EMC2_MASK (0x300U) | ||
| 5392 | #define CTIMER_EMR_EMC2_SHIFT (8U) | ||
| 5393 | /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. | ||
| 5394 | * 0b00..Do Nothing. | ||
| 5395 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). | ||
| 5396 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). | ||
| 5397 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 5398 | */ | ||
| 5399 | #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) | ||
| 5400 | #define CTIMER_EMR_EMC3_MASK (0xC00U) | ||
| 5401 | #define CTIMER_EMR_EMC3_SHIFT (10U) | ||
| 5402 | /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. | ||
| 5403 | * 0b00..Do Nothing. | ||
| 5404 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). | ||
| 5405 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). | ||
| 5406 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 5407 | */ | ||
| 5408 | #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) | ||
| 5409 | /*! @} */ | ||
| 5410 | |||
| 5411 | /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ | ||
| 5412 | /*! @{ */ | ||
| 5413 | #define CTIMER_CTCR_CTMODE_MASK (0x3U) | ||
| 5414 | #define CTIMER_CTCR_CTMODE_SHIFT (0U) | ||
| 5415 | /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment | ||
| 5416 | * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC | ||
| 5417 | * is incremented when the Prescale Counter matches the Prescale Register. | ||
| 5418 | * 0b00..Timer Mode. Incremented every rising APB bus clock edge. | ||
| 5419 | * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. | ||
| 5420 | * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. | ||
| 5421 | * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. | ||
| 5422 | */ | ||
| 5423 | #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) | ||
| 5424 | #define CTIMER_CTCR_CINSEL_MASK (0xCU) | ||
| 5425 | #define CTIMER_CTCR_CINSEL_SHIFT (2U) | ||
| 5426 | /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which | ||
| 5427 | * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input | ||
| 5428 | * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be | ||
| 5429 | * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the | ||
| 5430 | * same timer. | ||
| 5431 | * 0b00..Channel 0. CAPn.0 for CTIMERn | ||
| 5432 | * 0b01..Channel 1. CAPn.1 for CTIMERn | ||
| 5433 | * 0b10..Channel 2. CAPn.2 for CTIMERn | ||
| 5434 | * 0b11..Channel 3. CAPn.3 for CTIMERn | ||
| 5435 | */ | ||
| 5436 | #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) | ||
| 5437 | #define CTIMER_CTCR_ENCC_MASK (0x10U) | ||
| 5438 | #define CTIMER_CTCR_ENCC_SHIFT (4U) | ||
| 5439 | /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the | ||
| 5440 | * capture-edge event specified in bits 7:5 occurs. | ||
| 5441 | */ | ||
| 5442 | #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) | ||
| 5443 | #define CTIMER_CTCR_SELCC_MASK (0xE0U) | ||
| 5444 | #define CTIMER_CTCR_SELCC_SHIFT (5U) | ||
| 5445 | /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the | ||
| 5446 | * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to | ||
| 5447 | * 0x3 and 0x6 to 0x7 are reserved. | ||
| 5448 | * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 5449 | * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 5450 | * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 5451 | * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 5452 | * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 5453 | * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 5454 | */ | ||
| 5455 | #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) | ||
| 5456 | /*! @} */ | ||
| 5457 | |||
| 5458 | /*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ | ||
| 5459 | /*! @{ */ | ||
| 5460 | #define CTIMER_PWMC_PWMEN0_MASK (0x1U) | ||
| 5461 | #define CTIMER_PWMC_PWMEN0_SHIFT (0U) | ||
| 5462 | /*! PWMEN0 - PWM mode enable for channel0. | ||
| 5463 | * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. | ||
| 5464 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. | ||
| 5465 | */ | ||
| 5466 | #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) | ||
| 5467 | #define CTIMER_PWMC_PWMEN1_MASK (0x2U) | ||
| 5468 | #define CTIMER_PWMC_PWMEN1_SHIFT (1U) | ||
| 5469 | /*! PWMEN1 - PWM mode enable for channel1. | ||
| 5470 | * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. | ||
| 5471 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. | ||
| 5472 | */ | ||
| 5473 | #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) | ||
| 5474 | #define CTIMER_PWMC_PWMEN2_MASK (0x4U) | ||
| 5475 | #define CTIMER_PWMC_PWMEN2_SHIFT (2U) | ||
| 5476 | /*! PWMEN2 - PWM mode enable for channel2. | ||
| 5477 | * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. | ||
| 5478 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. | ||
| 5479 | */ | ||
| 5480 | #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) | ||
| 5481 | #define CTIMER_PWMC_PWMEN3_MASK (0x8U) | ||
| 5482 | #define CTIMER_PWMC_PWMEN3_SHIFT (3U) | ||
| 5483 | /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. | ||
| 5484 | * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. | ||
| 5485 | * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. | ||
| 5486 | */ | ||
| 5487 | #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) | ||
| 5488 | /*! @} */ | ||
| 5489 | |||
| 5490 | /*! @name MSR - Match Shadow Register */ | ||
| 5491 | /*! @{ */ | ||
| 5492 | #define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) | ||
| 5493 | #define CTIMER_MSR_SHADOW_SHIFT (0U) | ||
| 5494 | /*! SHADOW - Timer counter match shadow value. | ||
| 5495 | */ | ||
| 5496 | #define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) | ||
| 5497 | /*! @} */ | ||
| 5498 | |||
| 5499 | /* The count of CTIMER_MSR */ | ||
| 5500 | #define CTIMER_MSR_COUNT (4U) | ||
| 5501 | |||
| 5502 | |||
| 5503 | /*! | ||
| 5504 | * @} | ||
| 5505 | */ /* end of group CTIMER_Register_Masks */ | ||
| 5506 | |||
| 5507 | |||
| 5508 | /* CTIMER - Peripheral instance base addresses */ | ||
| 5509 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5510 | /** Peripheral CTIMER0 base address */ | ||
| 5511 | #define CTIMER0_BASE (0x50008000u) | ||
| 5512 | /** Peripheral CTIMER0 base address */ | ||
| 5513 | #define CTIMER0_BASE_NS (0x40008000u) | ||
| 5514 | /** Peripheral CTIMER0 base pointer */ | ||
| 5515 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 5516 | /** Peripheral CTIMER0 base pointer */ | ||
| 5517 | #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) | ||
| 5518 | /** Peripheral CTIMER1 base address */ | ||
| 5519 | #define CTIMER1_BASE (0x50009000u) | ||
| 5520 | /** Peripheral CTIMER1 base address */ | ||
| 5521 | #define CTIMER1_BASE_NS (0x40009000u) | ||
| 5522 | /** Peripheral CTIMER1 base pointer */ | ||
| 5523 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) | ||
| 5524 | /** Peripheral CTIMER1 base pointer */ | ||
| 5525 | #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) | ||
| 5526 | /** Peripheral CTIMER2 base address */ | ||
| 5527 | #define CTIMER2_BASE (0x50028000u) | ||
| 5528 | /** Peripheral CTIMER2 base address */ | ||
| 5529 | #define CTIMER2_BASE_NS (0x40028000u) | ||
| 5530 | /** Peripheral CTIMER2 base pointer */ | ||
| 5531 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) | ||
| 5532 | /** Peripheral CTIMER2 base pointer */ | ||
| 5533 | #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) | ||
| 5534 | /** Peripheral CTIMER3 base address */ | ||
| 5535 | #define CTIMER3_BASE (0x50029000u) | ||
| 5536 | /** Peripheral CTIMER3 base address */ | ||
| 5537 | #define CTIMER3_BASE_NS (0x40029000u) | ||
| 5538 | /** Peripheral CTIMER3 base pointer */ | ||
| 5539 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) | ||
| 5540 | /** Peripheral CTIMER3 base pointer */ | ||
| 5541 | #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) | ||
| 5542 | /** Peripheral CTIMER4 base address */ | ||
| 5543 | #define CTIMER4_BASE (0x5002A000u) | ||
| 5544 | /** Peripheral CTIMER4 base address */ | ||
| 5545 | #define CTIMER4_BASE_NS (0x4002A000u) | ||
| 5546 | /** Peripheral CTIMER4 base pointer */ | ||
| 5547 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) | ||
| 5548 | /** Peripheral CTIMER4 base pointer */ | ||
| 5549 | #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) | ||
| 5550 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 5551 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } | ||
| 5552 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 5553 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } | ||
| 5554 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 5555 | #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } | ||
| 5556 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 5557 | #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } | ||
| 5558 | #else | ||
| 5559 | /** Peripheral CTIMER0 base address */ | ||
| 5560 | #define CTIMER0_BASE (0x40008000u) | ||
| 5561 | /** Peripheral CTIMER0 base pointer */ | ||
| 5562 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 5563 | /** Peripheral CTIMER1 base address */ | ||
| 5564 | #define CTIMER1_BASE (0x40009000u) | ||
| 5565 | /** Peripheral CTIMER1 base pointer */ | ||
| 5566 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) | ||
| 5567 | /** Peripheral CTIMER2 base address */ | ||
| 5568 | #define CTIMER2_BASE (0x40028000u) | ||
| 5569 | /** Peripheral CTIMER2 base pointer */ | ||
| 5570 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) | ||
| 5571 | /** Peripheral CTIMER3 base address */ | ||
| 5572 | #define CTIMER3_BASE (0x40029000u) | ||
| 5573 | /** Peripheral CTIMER3 base pointer */ | ||
| 5574 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) | ||
| 5575 | /** Peripheral CTIMER4 base address */ | ||
| 5576 | #define CTIMER4_BASE (0x4002A000u) | ||
| 5577 | /** Peripheral CTIMER4 base pointer */ | ||
| 5578 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) | ||
| 5579 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 5580 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } | ||
| 5581 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 5582 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } | ||
| 5583 | #endif | ||
| 5584 | /** Interrupt vectors for the CTIMER peripheral type */ | ||
| 5585 | #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } | ||
| 5586 | |||
| 5587 | /*! | ||
| 5588 | * @} | ||
| 5589 | */ /* end of group CTIMER_Peripheral_Access_Layer */ | ||
| 5590 | |||
| 5591 | |||
| 5592 | /* ---------------------------------------------------------------------------- | ||
| 5593 | -- DBGMAILBOX Peripheral Access Layer | ||
| 5594 | ---------------------------------------------------------------------------- */ | ||
| 5595 | |||
| 5596 | /*! | ||
| 5597 | * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer | ||
| 5598 | * @{ | ||
| 5599 | */ | ||
| 5600 | |||
| 5601 | /** DBGMAILBOX - Register Layout Typedef */ | ||
| 5602 | typedef struct { | ||
| 5603 | __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ | ||
| 5604 | __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ | ||
| 5605 | __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ | ||
| 5606 | uint8_t RESERVED_0[240]; | ||
| 5607 | __I uint32_t ID; /**< Identification register, offset: 0xFC */ | ||
| 5608 | } DBGMAILBOX_Type; | ||
| 5609 | |||
| 5610 | /* ---------------------------------------------------------------------------- | ||
| 5611 | -- DBGMAILBOX Register Masks | ||
| 5612 | ---------------------------------------------------------------------------- */ | ||
| 5613 | |||
| 5614 | /*! | ||
| 5615 | * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks | ||
| 5616 | * @{ | ||
| 5617 | */ | ||
| 5618 | |||
| 5619 | /*! @name CSW - CRC mode register */ | ||
| 5620 | /*! @{ */ | ||
| 5621 | #define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) | ||
| 5622 | #define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) | ||
| 5623 | /*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation | ||
| 5624 | */ | ||
| 5625 | #define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) | ||
| 5626 | #define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) | ||
| 5627 | #define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) | ||
| 5628 | /*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) | ||
| 5629 | */ | ||
| 5630 | #define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) | ||
| 5631 | #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) | ||
| 5632 | #define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) | ||
| 5633 | /*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) | ||
| 5634 | */ | ||
| 5635 | #define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) | ||
| 5636 | #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) | ||
| 5637 | #define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) | ||
| 5638 | /*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) | ||
| 5639 | */ | ||
| 5640 | #define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) | ||
| 5641 | #define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) | ||
| 5642 | #define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) | ||
| 5643 | /*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to | ||
| 5644 | * this bit will cause a soft reset for DM. | ||
| 5645 | */ | ||
| 5646 | #define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) | ||
| 5647 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) | ||
| 5648 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) | ||
| 5649 | /*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is | ||
| 5650 | * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) | ||
| 5651 | */ | ||
| 5652 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) | ||
| 5653 | /*! @} */ | ||
| 5654 | |||
| 5655 | /*! @name REQUEST - CRC seed register */ | ||
| 5656 | /*! @{ */ | ||
| 5657 | #define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) | ||
| 5658 | #define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) | ||
| 5659 | /*! REQ - Request Value | ||
| 5660 | */ | ||
| 5661 | #define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) | ||
| 5662 | /*! @} */ | ||
| 5663 | |||
| 5664 | /*! @name RETURN - Return value from ROM. */ | ||
| 5665 | /*! @{ */ | ||
| 5666 | #define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) | ||
| 5667 | #define DBGMAILBOX_RETURN_RET_SHIFT (0U) | ||
| 5668 | /*! RET - The Return value from ROM. | ||
| 5669 | */ | ||
| 5670 | #define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) | ||
| 5671 | /*! @} */ | ||
| 5672 | |||
| 5673 | /*! @name ID - Identification register */ | ||
| 5674 | /*! @{ */ | ||
| 5675 | #define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) | ||
| 5676 | #define DBGMAILBOX_ID_ID_SHIFT (0U) | ||
| 5677 | /*! ID - Identification value. | ||
| 5678 | */ | ||
| 5679 | #define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) | ||
| 5680 | /*! @} */ | ||
| 5681 | |||
| 5682 | |||
| 5683 | /*! | ||
| 5684 | * @} | ||
| 5685 | */ /* end of group DBGMAILBOX_Register_Masks */ | ||
| 5686 | |||
| 5687 | |||
| 5688 | /* DBGMAILBOX - Peripheral instance base addresses */ | ||
| 5689 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5690 | /** Peripheral DBGMAILBOX base address */ | ||
| 5691 | #define DBGMAILBOX_BASE (0x5009C000u) | ||
| 5692 | /** Peripheral DBGMAILBOX base address */ | ||
| 5693 | #define DBGMAILBOX_BASE_NS (0x4009C000u) | ||
| 5694 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 5695 | #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) | ||
| 5696 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 5697 | #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) | ||
| 5698 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 5699 | #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } | ||
| 5700 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 5701 | #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } | ||
| 5702 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 5703 | #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } | ||
| 5704 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 5705 | #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } | ||
| 5706 | #else | ||
| 5707 | /** Peripheral DBGMAILBOX base address */ | ||
| 5708 | #define DBGMAILBOX_BASE (0x4009C000u) | ||
| 5709 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 5710 | #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) | ||
| 5711 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 5712 | #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } | ||
| 5713 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 5714 | #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } | ||
| 5715 | #endif | ||
| 5716 | |||
| 5717 | /*! | ||
| 5718 | * @} | ||
| 5719 | */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ | ||
| 5720 | |||
| 5721 | |||
| 5722 | /* ---------------------------------------------------------------------------- | ||
| 5723 | -- DMA Peripheral Access Layer | ||
| 5724 | ---------------------------------------------------------------------------- */ | ||
| 5725 | |||
| 5726 | /*! | ||
| 5727 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 5728 | * @{ | ||
| 5729 | */ | ||
| 5730 | |||
| 5731 | /** DMA - Register Layout Typedef */ | ||
| 5732 | typedef struct { | ||
| 5733 | __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ | ||
| 5734 | __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ | ||
| 5735 | __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ | ||
| 5736 | uint8_t RESERVED_0[20]; | ||
| 5737 | struct { /* offset: 0x20, array step: 0x5C */ | ||
| 5738 | __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ | ||
| 5739 | uint8_t RESERVED_0[4]; | ||
| 5740 | __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ | ||
| 5741 | uint8_t RESERVED_1[4]; | ||
| 5742 | __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ | ||
| 5743 | uint8_t RESERVED_2[4]; | ||
| 5744 | __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ | ||
| 5745 | uint8_t RESERVED_3[4]; | ||
| 5746 | __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ | ||
| 5747 | uint8_t RESERVED_4[4]; | ||
| 5748 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ | ||
| 5749 | uint8_t RESERVED_5[4]; | ||
| 5750 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ | ||
| 5751 | uint8_t RESERVED_6[4]; | ||
| 5752 | __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ | ||
| 5753 | uint8_t RESERVED_7[4]; | ||
| 5754 | __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ | ||
| 5755 | uint8_t RESERVED_8[4]; | ||
| 5756 | __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ | ||
| 5757 | uint8_t RESERVED_9[4]; | ||
| 5758 | __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ | ||
| 5759 | uint8_t RESERVED_10[4]; | ||
| 5760 | __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ | ||
| 5761 | } COMMON[1]; | ||
| 5762 | uint8_t RESERVED_1[900]; | ||
| 5763 | struct { /* offset: 0x400, array step: 0x10 */ | ||
| 5764 | __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ | ||
| 5765 | __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ | ||
| 5766 | __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ | ||
| 5767 | uint8_t RESERVED_0[4]; | ||
| 5768 | } CHANNEL[23]; | ||
| 5769 | } DMA_Type; | ||
| 5770 | |||
| 5771 | /* ---------------------------------------------------------------------------- | ||
| 5772 | -- DMA Register Masks | ||
| 5773 | ---------------------------------------------------------------------------- */ | ||
| 5774 | |||
| 5775 | /*! | ||
| 5776 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 5777 | * @{ | ||
| 5778 | */ | ||
| 5779 | |||
| 5780 | /*! @name CTRL - DMA control. */ | ||
| 5781 | /*! @{ */ | ||
| 5782 | #define DMA_CTRL_ENABLE_MASK (0x1U) | ||
| 5783 | #define DMA_CTRL_ENABLE_SHIFT (0U) | ||
| 5784 | /*! ENABLE - DMA controller master enable. | ||
| 5785 | * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when | ||
| 5786 | * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. | ||
| 5787 | * 0b1..Enabled. The DMA controller is enabled. | ||
| 5788 | */ | ||
| 5789 | #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) | ||
| 5790 | /*! @} */ | ||
| 5791 | |||
| 5792 | /*! @name INTSTAT - Interrupt status. */ | ||
| 5793 | /*! @{ */ | ||
| 5794 | #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) | ||
| 5795 | #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) | ||
| 5796 | /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. | ||
| 5797 | * 0b0..Not pending. No enabled interrupts are pending. | ||
| 5798 | * 0b1..Pending. At least one enabled interrupt is pending. | ||
| 5799 | */ | ||
| 5800 | #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) | ||
| 5801 | #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) | ||
| 5802 | #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) | ||
| 5803 | /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. | ||
| 5804 | * 0b0..Not pending. No error interrupts are pending. | ||
| 5805 | * 0b1..Pending. At least one error interrupt is pending. | ||
| 5806 | */ | ||
| 5807 | #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) | ||
| 5808 | /*! @} */ | ||
| 5809 | |||
| 5810 | /*! @name SRAMBASE - SRAM address of the channel configuration table. */ | ||
| 5811 | /*! @{ */ | ||
| 5812 | #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) | ||
| 5813 | #define DMA_SRAMBASE_OFFSET_SHIFT (9U) | ||
| 5814 | /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the | ||
| 5815 | * table must begin on a 512 byte boundary. | ||
| 5816 | */ | ||
| 5817 | #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) | ||
| 5818 | /*! @} */ | ||
| 5819 | |||
| 5820 | /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ | ||
| 5821 | /*! @{ */ | ||
| 5822 | #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) | ||
| 5823 | #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) | ||
| 5824 | /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = | ||
| 5825 | * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. | ||
| 5826 | */ | ||
| 5827 | #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) | ||
| 5828 | /*! @} */ | ||
| 5829 | |||
| 5830 | /* The count of DMA_COMMON_ENABLESET */ | ||
| 5831 | #define DMA_COMMON_ENABLESET_COUNT (1U) | ||
| 5832 | |||
| 5833 | /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ | ||
| 5834 | /*! @{ */ | ||
| 5835 | #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) | ||
| 5836 | #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) | ||
| 5837 | /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears | ||
| 5838 | * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits | ||
| 5839 | * are reserved. | ||
| 5840 | */ | ||
| 5841 | #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) | ||
| 5842 | /*! @} */ | ||
| 5843 | |||
| 5844 | /* The count of DMA_COMMON_ENABLECLR */ | ||
| 5845 | #define DMA_COMMON_ENABLECLR_COUNT (1U) | ||
| 5846 | |||
| 5847 | /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ | ||
| 5848 | /*! @{ */ | ||
| 5849 | #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) | ||
| 5850 | #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) | ||
| 5851 | /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 5852 | * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. | ||
| 5853 | */ | ||
| 5854 | #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) | ||
| 5855 | /*! @} */ | ||
| 5856 | |||
| 5857 | /* The count of DMA_COMMON_ACTIVE */ | ||
| 5858 | #define DMA_COMMON_ACTIVE_COUNT (1U) | ||
| 5859 | |||
| 5860 | /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ | ||
| 5861 | /*! @{ */ | ||
| 5862 | #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) | ||
| 5863 | #define DMA_COMMON_BUSY_BSY_SHIFT (0U) | ||
| 5864 | /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 5865 | * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. | ||
| 5866 | */ | ||
| 5867 | #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) | ||
| 5868 | /*! @} */ | ||
| 5869 | |||
| 5870 | /* The count of DMA_COMMON_BUSY */ | ||
| 5871 | #define DMA_COMMON_BUSY_COUNT (1U) | ||
| 5872 | |||
| 5873 | /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ | ||
| 5874 | /*! @{ */ | ||
| 5875 | #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) | ||
| 5876 | #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) | ||
| 5877 | /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 5878 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is | ||
| 5879 | * not active. 1 = error interrupt is active. | ||
| 5880 | */ | ||
| 5881 | #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) | ||
| 5882 | /*! @} */ | ||
| 5883 | |||
| 5884 | /* The count of DMA_COMMON_ERRINT */ | ||
| 5885 | #define DMA_COMMON_ERRINT_COUNT (1U) | ||
| 5886 | |||
| 5887 | /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ | ||
| 5888 | /*! @{ */ | ||
| 5889 | #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) | ||
| 5890 | #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) | ||
| 5891 | /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The | ||
| 5892 | * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = | ||
| 5893 | * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. | ||
| 5894 | */ | ||
| 5895 | #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) | ||
| 5896 | /*! @} */ | ||
| 5897 | |||
| 5898 | /* The count of DMA_COMMON_INTENSET */ | ||
| 5899 | #define DMA_COMMON_INTENSET_COUNT (1U) | ||
| 5900 | |||
| 5901 | /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ | ||
| 5902 | /*! @{ */ | ||
| 5903 | #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) | ||
| 5904 | #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) | ||
| 5905 | /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n | ||
| 5906 | * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are | ||
| 5907 | * reserved. | ||
| 5908 | */ | ||
| 5909 | #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) | ||
| 5910 | /*! @} */ | ||
| 5911 | |||
| 5912 | /* The count of DMA_COMMON_INTENCLR */ | ||
| 5913 | #define DMA_COMMON_INTENCLR_COUNT (1U) | ||
| 5914 | |||
| 5915 | /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ | ||
| 5916 | /*! @{ */ | ||
| 5917 | #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) | ||
| 5918 | #define DMA_COMMON_INTA_IA_SHIFT (0U) | ||
| 5919 | /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 5920 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 5921 | * interrupt A is not active. 1 = the DMA channel interrupt A is active. | ||
| 5922 | */ | ||
| 5923 | #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) | ||
| 5924 | /*! @} */ | ||
| 5925 | |||
| 5926 | /* The count of DMA_COMMON_INTA */ | ||
| 5927 | #define DMA_COMMON_INTA_COUNT (1U) | ||
| 5928 | |||
| 5929 | /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ | ||
| 5930 | /*! @{ */ | ||
| 5931 | #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) | ||
| 5932 | #define DMA_COMMON_INTB_IB_SHIFT (0U) | ||
| 5933 | /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 5934 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 5935 | * interrupt B is not active. 1 = the DMA channel interrupt B is active. | ||
| 5936 | */ | ||
| 5937 | #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) | ||
| 5938 | /*! @} */ | ||
| 5939 | |||
| 5940 | /* The count of DMA_COMMON_INTB */ | ||
| 5941 | #define DMA_COMMON_INTB_COUNT (1U) | ||
| 5942 | |||
| 5943 | /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ | ||
| 5944 | /*! @{ */ | ||
| 5945 | #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) | ||
| 5946 | #define DMA_COMMON_SETVALID_SV_SHIFT (0U) | ||
| 5947 | /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits | ||
| 5948 | * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the | ||
| 5949 | * VALIDPENDING control bit for DMA channel n | ||
| 5950 | */ | ||
| 5951 | #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) | ||
| 5952 | /*! @} */ | ||
| 5953 | |||
| 5954 | /* The count of DMA_COMMON_SETVALID */ | ||
| 5955 | #define DMA_COMMON_SETVALID_COUNT (1U) | ||
| 5956 | |||
| 5957 | /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ | ||
| 5958 | /*! @{ */ | ||
| 5959 | #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) | ||
| 5960 | #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) | ||
| 5961 | /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number | ||
| 5962 | * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = | ||
| 5963 | * sets the TRIG bit for DMA channel n. | ||
| 5964 | */ | ||
| 5965 | #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) | ||
| 5966 | /*! @} */ | ||
| 5967 | |||
| 5968 | /* The count of DMA_COMMON_SETTRIG */ | ||
| 5969 | #define DMA_COMMON_SETTRIG_COUNT (1U) | ||
| 5970 | |||
| 5971 | /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ | ||
| 5972 | /*! @{ */ | ||
| 5973 | #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) | ||
| 5974 | #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) | ||
| 5975 | /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. | ||
| 5976 | * 1 = aborts DMA operations on channel n. | ||
| 5977 | */ | ||
| 5978 | #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) | ||
| 5979 | /*! @} */ | ||
| 5980 | |||
| 5981 | /* The count of DMA_COMMON_ABORT */ | ||
| 5982 | #define DMA_COMMON_ABORT_COUNT (1U) | ||
| 5983 | |||
| 5984 | /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ | ||
| 5985 | /*! @{ */ | ||
| 5986 | #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) | ||
| 5987 | #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) | ||
| 5988 | /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory | ||
| 5989 | * move, any peripheral DMA request associated with that channel can be disabled to prevent any | ||
| 5990 | * interaction between the peripheral and the DMA controller. | ||
| 5991 | * 0b0..Disabled. Peripheral DMA requests are disabled. | ||
| 5992 | * 0b1..Enabled. Peripheral DMA requests are enabled. | ||
| 5993 | */ | ||
| 5994 | #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) | ||
| 5995 | #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) | ||
| 5996 | #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) | ||
| 5997 | /*! HWTRIGEN - Hardware Triggering Enable for this channel. | ||
| 5998 | * 0b0..Disabled. Hardware triggering is not used. | ||
| 5999 | * 0b1..Enabled. Use hardware triggering. | ||
| 6000 | */ | ||
| 6001 | #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) | ||
| 6002 | #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) | ||
| 6003 | #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) | ||
| 6004 | /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. | ||
| 6005 | * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. | ||
| 6006 | * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. | ||
| 6007 | */ | ||
| 6008 | #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) | ||
| 6009 | #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) | ||
| 6010 | #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) | ||
| 6011 | /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. | ||
| 6012 | * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. | ||
| 6013 | * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = | ||
| 6014 | * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the | ||
| 6015 | * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger | ||
| 6016 | * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the | ||
| 6017 | * current BURSTPOWER length are completed. | ||
| 6018 | */ | ||
| 6019 | #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) | ||
| 6020 | #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) | ||
| 6021 | #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) | ||
| 6022 | /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. | ||
| 6023 | * 0b0..Single transfer. Hardware trigger causes a single transfer. | ||
| 6024 | * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a | ||
| 6025 | * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a | ||
| 6026 | * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is | ||
| 6027 | * complete. | ||
| 6028 | */ | ||
| 6029 | #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) | ||
| 6030 | #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) | ||
| 6031 | #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) | ||
| 6032 | /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when | ||
| 6033 | * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). | ||
| 6034 | * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many | ||
| 6035 | * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that | ||
| 6036 | * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: | ||
| 6037 | * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = | ||
| 6038 | * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The | ||
| 6039 | * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even | ||
| 6040 | * multiple of the burst size. | ||
| 6041 | */ | ||
| 6042 | #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) | ||
| 6043 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) | ||
| 6044 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) | ||
| 6045 | /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is | ||
| 6046 | * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this | ||
| 6047 | * could be used to read several sequential registers from a peripheral for each DMA burst, | ||
| 6048 | * reading the same registers again for each burst. | ||
| 6049 | * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. | ||
| 6050 | * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. | ||
| 6051 | */ | ||
| 6052 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) | ||
| 6053 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) | ||
| 6054 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) | ||
| 6055 | /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is | ||
| 6056 | * 'wrapped', meaning that the destination address range for each burst will be the same. As an | ||
| 6057 | * example, this could be used to write several sequential registers to a peripheral for each DMA | ||
| 6058 | * burst, writing the same registers again for each burst. | ||
| 6059 | * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. | ||
| 6060 | * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. | ||
| 6061 | */ | ||
| 6062 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) | ||
| 6063 | #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) | ||
| 6064 | #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) | ||
| 6065 | /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority | ||
| 6066 | * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. | ||
| 6067 | */ | ||
| 6068 | #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) | ||
| 6069 | /*! @} */ | ||
| 6070 | |||
| 6071 | /* The count of DMA_CHANNEL_CFG */ | ||
| 6072 | #define DMA_CHANNEL_CFG_COUNT (23U) | ||
| 6073 | |||
| 6074 | /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ | ||
| 6075 | /*! @{ */ | ||
| 6076 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) | ||
| 6077 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) | ||
| 6078 | /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the | ||
| 6079 | * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. | ||
| 6080 | * 0b0..No effect. No effect on DMA operation. | ||
| 6081 | * 0b1..Valid pending. | ||
| 6082 | */ | ||
| 6083 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) | ||
| 6084 | #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) | ||
| 6085 | #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) | ||
| 6086 | /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is | ||
| 6087 | * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. | ||
| 6088 | * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. | ||
| 6089 | * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. | ||
| 6090 | */ | ||
| 6091 | #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) | ||
| 6092 | /*! @} */ | ||
| 6093 | |||
| 6094 | /* The count of DMA_CHANNEL_CTLSTAT */ | ||
| 6095 | #define DMA_CHANNEL_CTLSTAT_COUNT (23U) | ||
| 6096 | |||
| 6097 | /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ | ||
| 6098 | /*! @{ */ | ||
| 6099 | #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) | ||
| 6100 | #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) | ||
| 6101 | /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor | ||
| 6102 | * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. | ||
| 6103 | * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. | ||
| 6104 | * 0b1..Valid. The current channel descriptor is considered valid. | ||
| 6105 | */ | ||
| 6106 | #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) | ||
| 6107 | #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) | ||
| 6108 | #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) | ||
| 6109 | /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current | ||
| 6110 | * descriptor is exhausted. Reloading allows ping-pong and linked transfers. | ||
| 6111 | * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. | ||
| 6112 | * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. | ||
| 6113 | */ | ||
| 6114 | #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) | ||
| 6115 | #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) | ||
| 6116 | #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) | ||
| 6117 | /*! SWTRIG - Software Trigger. | ||
| 6118 | * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by | ||
| 6119 | * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. | ||
| 6120 | * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not | ||
| 6121 | * be used with level triggering when TRIGBURST = 0. | ||
| 6122 | */ | ||
| 6123 | #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) | ||
| 6124 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) | ||
| 6125 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) | ||
| 6126 | /*! CLRTRIG - Clear Trigger. | ||
| 6127 | * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. | ||
| 6128 | * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted | ||
| 6129 | */ | ||
| 6130 | #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) | ||
| 6131 | #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) | ||
| 6132 | #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) | ||
| 6133 | /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between | ||
| 6134 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 6135 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 6136 | * 0b0..No effect. | ||
| 6137 | * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. | ||
| 6138 | */ | ||
| 6139 | #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) | ||
| 6140 | #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) | ||
| 6141 | #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) | ||
| 6142 | /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between | ||
| 6143 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 6144 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 6145 | * 0b0..No effect. | ||
| 6146 | * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. | ||
| 6147 | */ | ||
| 6148 | #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) | ||
| 6149 | #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) | ||
| 6150 | #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) | ||
| 6151 | /*! WIDTH - Transfer width used for this DMA channel. | ||
| 6152 | * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). | ||
| 6153 | * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). | ||
| 6154 | * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). | ||
| 6155 | * 0b11..Reserved. Reserved setting, do not use. | ||
| 6156 | */ | ||
| 6157 | #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) | ||
| 6158 | #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) | ||
| 6159 | #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) | ||
| 6160 | /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. | ||
| 6161 | * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. | ||
| 6162 | * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is | ||
| 6163 | * the usual case when the source is memory. | ||
| 6164 | * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 6165 | * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 6166 | */ | ||
| 6167 | #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) | ||
| 6168 | #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) | ||
| 6169 | #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) | ||
| 6170 | /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. | ||
| 6171 | * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when | ||
| 6172 | * the destination is a peripheral device. | ||
| 6173 | * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. | ||
| 6174 | * This is the usual case when the destination is memory. | ||
| 6175 | * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 6176 | * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 6177 | */ | ||
| 6178 | #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) | ||
| 6179 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) | ||
| 6180 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) | ||
| 6181 | /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes | ||
| 6182 | * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller | ||
| 6183 | * uses this bit field during transfer to count down. Hence, it cannot be used by software to read | ||
| 6184 | * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 | ||
| 6185 | * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of | ||
| 6186 | * 1,024 transfers will be performed. | ||
| 6187 | */ | ||
| 6188 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) | ||
| 6189 | /*! @} */ | ||
| 6190 | |||
| 6191 | /* The count of DMA_CHANNEL_XFERCFG */ | ||
| 6192 | #define DMA_CHANNEL_XFERCFG_COUNT (23U) | ||
| 6193 | |||
| 6194 | |||
| 6195 | /*! | ||
| 6196 | * @} | ||
| 6197 | */ /* end of group DMA_Register_Masks */ | ||
| 6198 | |||
| 6199 | |||
| 6200 | /* DMA - Peripheral instance base addresses */ | ||
| 6201 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 6202 | /** Peripheral DMA0 base address */ | ||
| 6203 | #define DMA0_BASE (0x50082000u) | ||
| 6204 | /** Peripheral DMA0 base address */ | ||
| 6205 | #define DMA0_BASE_NS (0x40082000u) | ||
| 6206 | /** Peripheral DMA0 base pointer */ | ||
| 6207 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 6208 | /** Peripheral DMA0 base pointer */ | ||
| 6209 | #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) | ||
| 6210 | /** Peripheral DMA1 base address */ | ||
| 6211 | #define DMA1_BASE (0x500A7000u) | ||
| 6212 | /** Peripheral DMA1 base address */ | ||
| 6213 | #define DMA1_BASE_NS (0x400A7000u) | ||
| 6214 | /** Peripheral DMA1 base pointer */ | ||
| 6215 | #define DMA1 ((DMA_Type *)DMA1_BASE) | ||
| 6216 | /** Peripheral DMA1 base pointer */ | ||
| 6217 | #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) | ||
| 6218 | /** Array initializer of DMA peripheral base addresses */ | ||
| 6219 | #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } | ||
| 6220 | /** Array initializer of DMA peripheral base pointers */ | ||
| 6221 | #define DMA_BASE_PTRS { DMA0, DMA1 } | ||
| 6222 | /** Array initializer of DMA peripheral base addresses */ | ||
| 6223 | #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } | ||
| 6224 | /** Array initializer of DMA peripheral base pointers */ | ||
| 6225 | #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } | ||
| 6226 | #else | ||
| 6227 | /** Peripheral DMA0 base address */ | ||
| 6228 | #define DMA0_BASE (0x40082000u) | ||
| 6229 | /** Peripheral DMA0 base pointer */ | ||
| 6230 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 6231 | /** Peripheral DMA1 base address */ | ||
| 6232 | #define DMA1_BASE (0x400A7000u) | ||
| 6233 | /** Peripheral DMA1 base pointer */ | ||
| 6234 | #define DMA1 ((DMA_Type *)DMA1_BASE) | ||
| 6235 | /** Array initializer of DMA peripheral base addresses */ | ||
| 6236 | #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } | ||
| 6237 | /** Array initializer of DMA peripheral base pointers */ | ||
| 6238 | #define DMA_BASE_PTRS { DMA0, DMA1 } | ||
| 6239 | #endif | ||
| 6240 | /** Interrupt vectors for the DMA peripheral type */ | ||
| 6241 | #define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } | ||
| 6242 | |||
| 6243 | /*! | ||
| 6244 | * @} | ||
| 6245 | */ /* end of group DMA_Peripheral_Access_Layer */ | ||
| 6246 | |||
| 6247 | |||
| 6248 | /* ---------------------------------------------------------------------------- | ||
| 6249 | -- FLASH Peripheral Access Layer | ||
| 6250 | ---------------------------------------------------------------------------- */ | ||
| 6251 | |||
| 6252 | /*! | ||
| 6253 | * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer | ||
| 6254 | * @{ | ||
| 6255 | */ | ||
| 6256 | |||
| 6257 | /** FLASH - Register Layout Typedef */ | ||
| 6258 | typedef struct { | ||
| 6259 | __O uint32_t CMD; /**< command register, offset: 0x0 */ | ||
| 6260 | __O uint32_t EVENT; /**< event register, offset: 0x4 */ | ||
| 6261 | uint8_t RESERVED_0[8]; | ||
| 6262 | __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ | ||
| 6263 | __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ | ||
| 6264 | uint8_t RESERVED_1[104]; | ||
| 6265 | __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ | ||
| 6266 | uint8_t RESERVED_2[3912]; | ||
| 6267 | __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ | ||
| 6268 | __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ | ||
| 6269 | __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ | ||
| 6270 | __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ | ||
| 6271 | __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ | ||
| 6272 | __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ | ||
| 6273 | uint8_t RESERVED_3[12]; | ||
| 6274 | __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ | ||
| 6275 | } FLASH_Type; | ||
| 6276 | |||
| 6277 | /* ---------------------------------------------------------------------------- | ||
| 6278 | -- FLASH Register Masks | ||
| 6279 | ---------------------------------------------------------------------------- */ | ||
| 6280 | |||
| 6281 | /*! | ||
| 6282 | * @addtogroup FLASH_Register_Masks FLASH Register Masks | ||
| 6283 | * @{ | ||
| 6284 | */ | ||
| 6285 | |||
| 6286 | /*! @name CMD - command register */ | ||
| 6287 | /*! @{ */ | ||
| 6288 | #define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) | ||
| 6289 | #define FLASH_CMD_CMD_SHIFT (0U) | ||
| 6290 | /*! CMD - command register. | ||
| 6291 | */ | ||
| 6292 | #define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) | ||
| 6293 | /*! @} */ | ||
| 6294 | |||
| 6295 | /*! @name EVENT - event register */ | ||
| 6296 | /*! @{ */ | ||
| 6297 | #define FLASH_EVENT_RST_MASK (0x1U) | ||
| 6298 | #define FLASH_EVENT_RST_SHIFT (0U) | ||
| 6299 | /*! RST - When bit is set, the controller and flash are reset. | ||
| 6300 | */ | ||
| 6301 | #define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) | ||
| 6302 | #define FLASH_EVENT_WAKEUP_MASK (0x2U) | ||
| 6303 | #define FLASH_EVENT_WAKEUP_SHIFT (1U) | ||
| 6304 | /*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. | ||
| 6305 | */ | ||
| 6306 | #define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) | ||
| 6307 | #define FLASH_EVENT_ABORT_MASK (0x4U) | ||
| 6308 | #define FLASH_EVENT_ABORT_SHIFT (2U) | ||
| 6309 | /*! ABORT - When bit is set, a running program/erase command is aborted. | ||
| 6310 | */ | ||
| 6311 | #define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) | ||
| 6312 | /*! @} */ | ||
| 6313 | |||
| 6314 | /*! @name STARTA - start (or only) address for next flash command */ | ||
| 6315 | /*! @{ */ | ||
| 6316 | #define FLASH_STARTA_STARTA_MASK (0x3FFFFU) | ||
| 6317 | #define FLASH_STARTA_STARTA_SHIFT (0U) | ||
| 6318 | /*! STARTA - Address / Start address for commands that take an address (range) as a parameter. | ||
| 6319 | */ | ||
| 6320 | #define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) | ||
| 6321 | /*! @} */ | ||
| 6322 | |||
| 6323 | /*! @name STOPA - end address for next flash command, if command operates on address ranges */ | ||
| 6324 | /*! @{ */ | ||
| 6325 | #define FLASH_STOPA_STOPA_MASK (0x3FFFFU) | ||
| 6326 | #define FLASH_STOPA_STOPA_SHIFT (0U) | ||
| 6327 | /*! STOPA - Stop address for commands that take an address range as a parameter (the word specified | ||
| 6328 | * by STOPA is included in the address range). | ||
| 6329 | */ | ||
| 6330 | #define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) | ||
| 6331 | /*! @} */ | ||
| 6332 | |||
| 6333 | /*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ | ||
| 6334 | /*! @{ */ | ||
| 6335 | #define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) | ||
| 6336 | #define FLASH_DATAW_DATAW_SHIFT (0U) | ||
| 6337 | #define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) | ||
| 6338 | /*! @} */ | ||
| 6339 | |||
| 6340 | /* The count of FLASH_DATAW */ | ||
| 6341 | #define FLASH_DATAW_COUNT (4U) | ||
| 6342 | |||
| 6343 | /*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ | ||
| 6344 | /*! @{ */ | ||
| 6345 | #define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) | ||
| 6346 | #define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) | ||
| 6347 | /*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 6348 | */ | ||
| 6349 | #define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) | ||
| 6350 | #define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) | ||
| 6351 | #define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) | ||
| 6352 | /*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 6353 | */ | ||
| 6354 | #define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) | ||
| 6355 | #define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) | ||
| 6356 | #define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) | ||
| 6357 | /*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 6358 | */ | ||
| 6359 | #define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) | ||
| 6360 | #define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 6361 | #define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 6362 | /*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 6363 | */ | ||
| 6364 | #define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) | ||
| 6365 | /*! @} */ | ||
| 6366 | |||
| 6367 | /*! @name INT_SET_ENABLE - Set interrupt enable bits */ | ||
| 6368 | /*! @{ */ | ||
| 6369 | #define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) | ||
| 6370 | #define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) | ||
| 6371 | /*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 6372 | */ | ||
| 6373 | #define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) | ||
| 6374 | #define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) | ||
| 6375 | #define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) | ||
| 6376 | /*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 6377 | */ | ||
| 6378 | #define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) | ||
| 6379 | #define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) | ||
| 6380 | #define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) | ||
| 6381 | /*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 6382 | */ | ||
| 6383 | #define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) | ||
| 6384 | #define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 6385 | #define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 6386 | /*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 6387 | */ | ||
| 6388 | #define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) | ||
| 6389 | /*! @} */ | ||
| 6390 | |||
| 6391 | /*! @name INT_STATUS - Interrupt status bits */ | ||
| 6392 | /*! @{ */ | ||
| 6393 | #define FLASH_INT_STATUS_FAIL_MASK (0x1U) | ||
| 6394 | #define FLASH_INT_STATUS_FAIL_SHIFT (0U) | ||
| 6395 | /*! FAIL - This status bit is set if execution of a (legal) command failed. | ||
| 6396 | */ | ||
| 6397 | #define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) | ||
| 6398 | #define FLASH_INT_STATUS_ERR_MASK (0x2U) | ||
| 6399 | #define FLASH_INT_STATUS_ERR_SHIFT (1U) | ||
| 6400 | /*! ERR - This status bit is set if execution of an illegal command is detected. | ||
| 6401 | */ | ||
| 6402 | #define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) | ||
| 6403 | #define FLASH_INT_STATUS_DONE_MASK (0x4U) | ||
| 6404 | #define FLASH_INT_STATUS_DONE_SHIFT (2U) | ||
| 6405 | /*! DONE - This status bit is set at the end of command execution. | ||
| 6406 | */ | ||
| 6407 | #define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) | ||
| 6408 | #define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) | ||
| 6409 | #define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) | ||
| 6410 | /*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested | ||
| 6411 | * read, or a speculative read, or reads performed by a controller command), a correctable or | ||
| 6412 | * uncorrectable error is detected by ECC decoding logic. | ||
| 6413 | */ | ||
| 6414 | #define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) | ||
| 6415 | /*! @} */ | ||
| 6416 | |||
| 6417 | /*! @name INT_ENABLE - Interrupt enable bits */ | ||
| 6418 | /*! @{ */ | ||
| 6419 | #define FLASH_INT_ENABLE_FAIL_MASK (0x1U) | ||
| 6420 | #define FLASH_INT_ENABLE_FAIL_SHIFT (0U) | ||
| 6421 | /*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 6422 | */ | ||
| 6423 | #define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) | ||
| 6424 | #define FLASH_INT_ENABLE_ERR_MASK (0x2U) | ||
| 6425 | #define FLASH_INT_ENABLE_ERR_SHIFT (1U) | ||
| 6426 | /*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 6427 | */ | ||
| 6428 | #define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) | ||
| 6429 | #define FLASH_INT_ENABLE_DONE_MASK (0x4U) | ||
| 6430 | #define FLASH_INT_ENABLE_DONE_SHIFT (2U) | ||
| 6431 | /*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 6432 | */ | ||
| 6433 | #define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) | ||
| 6434 | #define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 6435 | #define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 6436 | /*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 6437 | */ | ||
| 6438 | #define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) | ||
| 6439 | /*! @} */ | ||
| 6440 | |||
| 6441 | /*! @name INT_CLR_STATUS - Clear interrupt status bits */ | ||
| 6442 | /*! @{ */ | ||
| 6443 | #define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) | ||
| 6444 | #define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) | ||
| 6445 | /*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 6446 | */ | ||
| 6447 | #define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) | ||
| 6448 | #define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) | ||
| 6449 | #define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) | ||
| 6450 | /*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 6451 | */ | ||
| 6452 | #define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) | ||
| 6453 | #define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) | ||
| 6454 | #define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) | ||
| 6455 | /*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 6456 | */ | ||
| 6457 | #define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) | ||
| 6458 | #define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) | ||
| 6459 | #define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) | ||
| 6460 | /*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 6461 | */ | ||
| 6462 | #define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) | ||
| 6463 | /*! @} */ | ||
| 6464 | |||
| 6465 | /*! @name INT_SET_STATUS - Set interrupt status bits */ | ||
| 6466 | /*! @{ */ | ||
| 6467 | #define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) | ||
| 6468 | #define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) | ||
| 6469 | /*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 6470 | */ | ||
| 6471 | #define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) | ||
| 6472 | #define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) | ||
| 6473 | #define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) | ||
| 6474 | /*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 6475 | */ | ||
| 6476 | #define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) | ||
| 6477 | #define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) | ||
| 6478 | #define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) | ||
| 6479 | /*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 6480 | */ | ||
| 6481 | #define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) | ||
| 6482 | #define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) | ||
| 6483 | #define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) | ||
| 6484 | /*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 6485 | */ | ||
| 6486 | #define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) | ||
| 6487 | /*! @} */ | ||
| 6488 | |||
| 6489 | /*! @name MODULE_ID - Controller+Memory module identification */ | ||
| 6490 | /*! @{ */ | ||
| 6491 | #define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) | ||
| 6492 | #define FLASH_MODULE_ID_APERTURE_SHIFT (0U) | ||
| 6493 | /*! APERTURE - Aperture i. | ||
| 6494 | */ | ||
| 6495 | #define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) | ||
| 6496 | #define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) | ||
| 6497 | #define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) | ||
| 6498 | /*! MINOR_REV - Minor revision i. | ||
| 6499 | */ | ||
| 6500 | #define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) | ||
| 6501 | #define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) | ||
| 6502 | #define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) | ||
| 6503 | /*! MAJOR_REV - Major revision i. | ||
| 6504 | */ | ||
| 6505 | #define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) | ||
| 6506 | #define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) | ||
| 6507 | #define FLASH_MODULE_ID_ID_SHIFT (16U) | ||
| 6508 | /*! ID - Identifier. | ||
| 6509 | */ | ||
| 6510 | #define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) | ||
| 6511 | /*! @} */ | ||
| 6512 | |||
| 6513 | |||
| 6514 | /*! | ||
| 6515 | * @} | ||
| 6516 | */ /* end of group FLASH_Register_Masks */ | ||
| 6517 | |||
| 6518 | |||
| 6519 | /* FLASH - Peripheral instance base addresses */ | ||
| 6520 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 6521 | /** Peripheral FLASH base address */ | ||
| 6522 | #define FLASH_BASE (0x50034000u) | ||
| 6523 | /** Peripheral FLASH base address */ | ||
| 6524 | #define FLASH_BASE_NS (0x40034000u) | ||
| 6525 | /** Peripheral FLASH base pointer */ | ||
| 6526 | #define FLASH ((FLASH_Type *)FLASH_BASE) | ||
| 6527 | /** Peripheral FLASH base pointer */ | ||
| 6528 | #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) | ||
| 6529 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 6530 | #define FLASH_BASE_ADDRS { FLASH_BASE } | ||
| 6531 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 6532 | #define FLASH_BASE_PTRS { FLASH } | ||
| 6533 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 6534 | #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } | ||
| 6535 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 6536 | #define FLASH_BASE_PTRS_NS { FLASH_NS } | ||
| 6537 | #else | ||
| 6538 | /** Peripheral FLASH base address */ | ||
| 6539 | #define FLASH_BASE (0x40034000u) | ||
| 6540 | /** Peripheral FLASH base pointer */ | ||
| 6541 | #define FLASH ((FLASH_Type *)FLASH_BASE) | ||
| 6542 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 6543 | #define FLASH_BASE_ADDRS { FLASH_BASE } | ||
| 6544 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 6545 | #define FLASH_BASE_PTRS { FLASH } | ||
| 6546 | #endif | ||
| 6547 | |||
| 6548 | /*! | ||
| 6549 | * @} | ||
| 6550 | */ /* end of group FLASH_Peripheral_Access_Layer */ | ||
| 6551 | |||
| 6552 | |||
| 6553 | /* ---------------------------------------------------------------------------- | ||
| 6554 | -- FLASH_CFPA Peripheral Access Layer | ||
| 6555 | ---------------------------------------------------------------------------- */ | ||
| 6556 | |||
| 6557 | /*! | ||
| 6558 | * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer | ||
| 6559 | * @{ | ||
| 6560 | */ | ||
| 6561 | |||
| 6562 | /** FLASH_CFPA - Register Layout Typedef */ | ||
| 6563 | typedef struct { | ||
| 6564 | __IO uint32_t HEADER; /**< ., offset: 0x0 */ | ||
| 6565 | __IO uint32_t VERSION; /**< ., offset: 0x4 */ | ||
| 6566 | __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ | ||
| 6567 | __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ | ||
| 6568 | __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ | ||
| 6569 | uint8_t RESERVED_0[4]; | ||
| 6570 | __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ | ||
| 6571 | __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ | ||
| 6572 | __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ | ||
| 6573 | __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ | ||
| 6574 | __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ | ||
| 6575 | __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ | ||
| 6576 | union { /* offset: 0x30 */ | ||
| 6577 | __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ | ||
| 6578 | struct { /* offset: 0x30 */ | ||
| 6579 | __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ | ||
| 6580 | __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ | ||
| 6581 | __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ | ||
| 6582 | } PRINCE_REGION0_IV_CODE_CORE; | ||
| 6583 | }; | ||
| 6584 | union { /* offset: 0x68 */ | ||
| 6585 | __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ | ||
| 6586 | struct { /* offset: 0x68 */ | ||
| 6587 | __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ | ||
| 6588 | __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ | ||
| 6589 | __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ | ||
| 6590 | } PRINCE_REGION1_IV_CODE_CORE; | ||
| 6591 | }; | ||
| 6592 | union { /* offset: 0xA0 */ | ||
| 6593 | __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ | ||
| 6594 | struct { /* offset: 0xA0 */ | ||
| 6595 | __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ | ||
| 6596 | __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ | ||
| 6597 | __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ | ||
| 6598 | } PRINCE_REGION2_IV_CODE_CORE; | ||
| 6599 | }; | ||
| 6600 | uint8_t RESERVED_1[40]; | ||
| 6601 | __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ | ||
| 6602 | __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ | ||
| 6603 | } FLASH_CFPA_Type; | ||
| 6604 | |||
| 6605 | /* ---------------------------------------------------------------------------- | ||
| 6606 | -- FLASH_CFPA Register Masks | ||
| 6607 | ---------------------------------------------------------------------------- */ | ||
| 6608 | |||
| 6609 | /*! | ||
| 6610 | * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks | ||
| 6611 | * @{ | ||
| 6612 | */ | ||
| 6613 | |||
| 6614 | /*! @name HEADER - . */ | ||
| 6615 | /*! @{ */ | ||
| 6616 | #define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) | ||
| 6617 | #define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) | ||
| 6618 | /*! FIELD - . | ||
| 6619 | */ | ||
| 6620 | #define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) | ||
| 6621 | /*! @} */ | ||
| 6622 | |||
| 6623 | /*! @name VERSION - . */ | ||
| 6624 | /*! @{ */ | ||
| 6625 | #define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 6626 | #define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) | ||
| 6627 | /*! FIELD - . | ||
| 6628 | */ | ||
| 6629 | #define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) | ||
| 6630 | /*! @} */ | ||
| 6631 | |||
| 6632 | /*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ | ||
| 6633 | /*! @{ */ | ||
| 6634 | #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 6635 | #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) | ||
| 6636 | /*! FIELD - . | ||
| 6637 | */ | ||
| 6638 | #define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) | ||
| 6639 | /*! @} */ | ||
| 6640 | |||
| 6641 | /*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ | ||
| 6642 | /*! @{ */ | ||
| 6643 | #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 6644 | #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) | ||
| 6645 | /*! FIELD - . | ||
| 6646 | */ | ||
| 6647 | #define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) | ||
| 6648 | /*! @} */ | ||
| 6649 | |||
| 6650 | /*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ | ||
| 6651 | /*! @{ */ | ||
| 6652 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) | ||
| 6653 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) | ||
| 6654 | /*! FIELD - . | ||
| 6655 | */ | ||
| 6656 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) | ||
| 6657 | /*! @} */ | ||
| 6658 | |||
| 6659 | /*! @name ROTKH_REVOKE - . */ | ||
| 6660 | /*! @{ */ | ||
| 6661 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) | ||
| 6662 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) | ||
| 6663 | /*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 6664 | */ | ||
| 6665 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) | ||
| 6666 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) | ||
| 6667 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) | ||
| 6668 | /*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 6669 | */ | ||
| 6670 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) | ||
| 6671 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) | ||
| 6672 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) | ||
| 6673 | /*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 6674 | */ | ||
| 6675 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) | ||
| 6676 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) | ||
| 6677 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) | ||
| 6678 | /*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 6679 | */ | ||
| 6680 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) | ||
| 6681 | /*! @} */ | ||
| 6682 | |||
| 6683 | /*! @name VENDOR_USAGE - . */ | ||
| 6684 | /*! @{ */ | ||
| 6685 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) | ||
| 6686 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) | ||
| 6687 | /*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. | ||
| 6688 | */ | ||
| 6689 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) | ||
| 6690 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 6691 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) | ||
| 6692 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 6693 | */ | ||
| 6694 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) | ||
| 6695 | /*! @} */ | ||
| 6696 | |||
| 6697 | /*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ | ||
| 6698 | /*! @{ */ | ||
| 6699 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) | ||
| 6700 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) | ||
| 6701 | /*! NIDEN - Non Secure non-invasive debug enable | ||
| 6702 | * 0b0..Use DAP to enable | ||
| 6703 | * 0b1..Fixed state | ||
| 6704 | */ | ||
| 6705 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) | ||
| 6706 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) | ||
| 6707 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) | ||
| 6708 | /*! DBGEN - Non Secure debug enable | ||
| 6709 | * 0b0..Use DAP to enable | ||
| 6710 | * 0b1..Fixed state | ||
| 6711 | */ | ||
| 6712 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) | ||
| 6713 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) | ||
| 6714 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) | ||
| 6715 | /*! SPNIDEN - Secure non-invasive debug enable | ||
| 6716 | * 0b0..Use DAP to enable | ||
| 6717 | * 0b1..Fixed state | ||
| 6718 | */ | ||
| 6719 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) | ||
| 6720 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) | ||
| 6721 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) | ||
| 6722 | /*! SPIDEN - Secure invasive debug enable | ||
| 6723 | * 0b0..Use DAP to enable | ||
| 6724 | * 0b1..Fixed state | ||
| 6725 | */ | ||
| 6726 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) | ||
| 6727 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) | ||
| 6728 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) | ||
| 6729 | /*! TAPEN - JTAG TAP enable | ||
| 6730 | * 0b0..Use DAP to enable | ||
| 6731 | * 0b1..Fixed state | ||
| 6732 | */ | ||
| 6733 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) | ||
| 6734 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) | ||
| 6735 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) | ||
| 6736 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable | ||
| 6737 | * 0b0..Use DAP to enable | ||
| 6738 | * 0b1..Fixed state | ||
| 6739 | */ | ||
| 6740 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) | ||
| 6741 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) | ||
| 6742 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) | ||
| 6743 | /*! ISP_CMD_EN - ISP Boot Command enable | ||
| 6744 | * 0b0..Use DAP to enable | ||
| 6745 | * 0b1..Fixed state | ||
| 6746 | */ | ||
| 6747 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) | ||
| 6748 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) | ||
| 6749 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) | ||
| 6750 | /*! FA_CMD_EN - FA Command enable | ||
| 6751 | * 0b0..Use DAP to enable | ||
| 6752 | * 0b1..Fixed state | ||
| 6753 | */ | ||
| 6754 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) | ||
| 6755 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) | ||
| 6756 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) | ||
| 6757 | /*! ME_CMD_EN - Flash Mass Erase Command enable | ||
| 6758 | * 0b0..Use DAP to enable | ||
| 6759 | * 0b1..Fixed state | ||
| 6760 | */ | ||
| 6761 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) | ||
| 6762 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) | ||
| 6763 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) | ||
| 6764 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable | ||
| 6765 | * 0b0..Use DAP to enable | ||
| 6766 | * 0b1..Fixed state | ||
| 6767 | */ | ||
| 6768 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) | ||
| 6769 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) | ||
| 6770 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) | ||
| 6771 | /*! UUID_CHECK - Enforce UUID match during Debug authentication. | ||
| 6772 | */ | ||
| 6773 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) | ||
| 6774 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 6775 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) | ||
| 6776 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 6777 | */ | ||
| 6778 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) | ||
| 6779 | /*! @} */ | ||
| 6780 | |||
| 6781 | /*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ | ||
| 6782 | /*! @{ */ | ||
| 6783 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) | ||
| 6784 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) | ||
| 6785 | /*! NIDEN - Non Secure non-invasive debug fixed state | ||
| 6786 | * 0b0..Disable | ||
| 6787 | * 0b1..Enable | ||
| 6788 | */ | ||
| 6789 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) | ||
| 6790 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) | ||
| 6791 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) | ||
| 6792 | /*! DBGEN - Non Secure debug fixed state | ||
| 6793 | * 0b0..Disable | ||
| 6794 | * 0b1..Enable | ||
| 6795 | */ | ||
| 6796 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) | ||
| 6797 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) | ||
| 6798 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) | ||
| 6799 | /*! SPNIDEN - Secure non-invasive debug fixed state | ||
| 6800 | * 0b0..Disable | ||
| 6801 | * 0b1..Enable | ||
| 6802 | */ | ||
| 6803 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) | ||
| 6804 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) | ||
| 6805 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) | ||
| 6806 | /*! SPIDEN - Secure invasive debug fixed state | ||
| 6807 | * 0b0..Disable | ||
| 6808 | * 0b1..Enable | ||
| 6809 | */ | ||
| 6810 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) | ||
| 6811 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) | ||
| 6812 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) | ||
| 6813 | /*! TAPEN - JTAG TAP fixed state | ||
| 6814 | * 0b0..Disable | ||
| 6815 | * 0b1..Enable | ||
| 6816 | */ | ||
| 6817 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) | ||
| 6818 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) | ||
| 6819 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) | ||
| 6820 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state | ||
| 6821 | * 0b0..Disable | ||
| 6822 | * 0b1..Enable | ||
| 6823 | */ | ||
| 6824 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) | ||
| 6825 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) | ||
| 6826 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) | ||
| 6827 | /*! ISP_CMD_EN - ISP Boot Command fixed state | ||
| 6828 | * 0b0..Disable | ||
| 6829 | * 0b1..Enable | ||
| 6830 | */ | ||
| 6831 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) | ||
| 6832 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) | ||
| 6833 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) | ||
| 6834 | /*! FA_CMD_EN - FA Command fixed state | ||
| 6835 | * 0b0..Disable | ||
| 6836 | * 0b1..Enable | ||
| 6837 | */ | ||
| 6838 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) | ||
| 6839 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) | ||
| 6840 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) | ||
| 6841 | /*! ME_CMD_EN - Flash Mass Erase Command fixed state | ||
| 6842 | * 0b0..Disable | ||
| 6843 | * 0b1..Enable | ||
| 6844 | */ | ||
| 6845 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) | ||
| 6846 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) | ||
| 6847 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) | ||
| 6848 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state | ||
| 6849 | * 0b0..Disable | ||
| 6850 | * 0b1..Enable | ||
| 6851 | */ | ||
| 6852 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) | ||
| 6853 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 6854 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) | ||
| 6855 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 6856 | */ | ||
| 6857 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) | ||
| 6858 | /*! @} */ | ||
| 6859 | |||
| 6860 | /*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ | ||
| 6861 | /*! @{ */ | ||
| 6862 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 6863 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) | ||
| 6864 | /*! FIELD - . | ||
| 6865 | */ | ||
| 6866 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) | ||
| 6867 | /*! @} */ | ||
| 6868 | |||
| 6869 | /*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ | ||
| 6870 | /*! @{ */ | ||
| 6871 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) | ||
| 6872 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) | ||
| 6873 | /*! FIELD - . | ||
| 6874 | */ | ||
| 6875 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) | ||
| 6876 | /*! @} */ | ||
| 6877 | |||
| 6878 | /*! @name PRINCE_REGION0_IV_CODE - . */ | ||
| 6879 | /*! @{ */ | ||
| 6880 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 6881 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) | ||
| 6882 | /*! FIELD - . | ||
| 6883 | */ | ||
| 6884 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) | ||
| 6885 | /*! @} */ | ||
| 6886 | |||
| 6887 | /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ | ||
| 6888 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) | ||
| 6889 | |||
| 6890 | /*! @name PRINCE_REGION0_IV_HEADER0 - . */ | ||
| 6891 | /*! @{ */ | ||
| 6892 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 6893 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 6894 | /*! FIELD - . | ||
| 6895 | */ | ||
| 6896 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) | ||
| 6897 | /*! @} */ | ||
| 6898 | |||
| 6899 | /*! @name PRINCE_REGION0_IV_HEADER1 - . */ | ||
| 6900 | /*! @{ */ | ||
| 6901 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 6902 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 6903 | /*! TYPE - . | ||
| 6904 | */ | ||
| 6905 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) | ||
| 6906 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 6907 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 6908 | /*! INDEX - . | ||
| 6909 | */ | ||
| 6910 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) | ||
| 6911 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 6912 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 6913 | /*! SIZE - . | ||
| 6914 | */ | ||
| 6915 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) | ||
| 6916 | /*! @} */ | ||
| 6917 | |||
| 6918 | /*! @name PRINCE_REGION0_IV_BODY - . */ | ||
| 6919 | /*! @{ */ | ||
| 6920 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 6921 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) | ||
| 6922 | /*! FIELD - . | ||
| 6923 | */ | ||
| 6924 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) | ||
| 6925 | /*! @} */ | ||
| 6926 | |||
| 6927 | /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ | ||
| 6928 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) | ||
| 6929 | |||
| 6930 | /*! @name PRINCE_REGION1_IV_CODE - . */ | ||
| 6931 | /*! @{ */ | ||
| 6932 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 6933 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) | ||
| 6934 | /*! FIELD - . | ||
| 6935 | */ | ||
| 6936 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) | ||
| 6937 | /*! @} */ | ||
| 6938 | |||
| 6939 | /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ | ||
| 6940 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) | ||
| 6941 | |||
| 6942 | /*! @name PRINCE_REGION1_IV_HEADER0 - . */ | ||
| 6943 | /*! @{ */ | ||
| 6944 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 6945 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 6946 | /*! FIELD - . | ||
| 6947 | */ | ||
| 6948 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) | ||
| 6949 | /*! @} */ | ||
| 6950 | |||
| 6951 | /*! @name PRINCE_REGION1_IV_HEADER1 - . */ | ||
| 6952 | /*! @{ */ | ||
| 6953 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 6954 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 6955 | /*! TYPE - . | ||
| 6956 | */ | ||
| 6957 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) | ||
| 6958 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 6959 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 6960 | /*! INDEX - . | ||
| 6961 | */ | ||
| 6962 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) | ||
| 6963 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 6964 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 6965 | /*! SIZE - . | ||
| 6966 | */ | ||
| 6967 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) | ||
| 6968 | /*! @} */ | ||
| 6969 | |||
| 6970 | /*! @name PRINCE_REGION1_IV_BODY - . */ | ||
| 6971 | /*! @{ */ | ||
| 6972 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 6973 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) | ||
| 6974 | /*! FIELD - . | ||
| 6975 | */ | ||
| 6976 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) | ||
| 6977 | /*! @} */ | ||
| 6978 | |||
| 6979 | /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ | ||
| 6980 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) | ||
| 6981 | |||
| 6982 | /*! @name PRINCE_REGION2_IV_CODE - . */ | ||
| 6983 | /*! @{ */ | ||
| 6984 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 6985 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) | ||
| 6986 | /*! FIELD - . | ||
| 6987 | */ | ||
| 6988 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) | ||
| 6989 | /*! @} */ | ||
| 6990 | |||
| 6991 | /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ | ||
| 6992 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) | ||
| 6993 | |||
| 6994 | /*! @name PRINCE_REGION2_IV_HEADER0 - . */ | ||
| 6995 | /*! @{ */ | ||
| 6996 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 6997 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 6998 | /*! FIELD - . | ||
| 6999 | */ | ||
| 7000 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) | ||
| 7001 | /*! @} */ | ||
| 7002 | |||
| 7003 | /*! @name PRINCE_REGION2_IV_HEADER1 - . */ | ||
| 7004 | /*! @{ */ | ||
| 7005 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 7006 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 7007 | /*! TYPE - . | ||
| 7008 | */ | ||
| 7009 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) | ||
| 7010 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 7011 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 7012 | /*! INDEX - . | ||
| 7013 | */ | ||
| 7014 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) | ||
| 7015 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7016 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 7017 | /*! SIZE - . | ||
| 7018 | */ | ||
| 7019 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) | ||
| 7020 | /*! @} */ | ||
| 7021 | |||
| 7022 | /*! @name PRINCE_REGION2_IV_BODY - . */ | ||
| 7023 | /*! @{ */ | ||
| 7024 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7025 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) | ||
| 7026 | /*! FIELD - . | ||
| 7027 | */ | ||
| 7028 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) | ||
| 7029 | /*! @} */ | ||
| 7030 | |||
| 7031 | /* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ | ||
| 7032 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) | ||
| 7033 | |||
| 7034 | /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ | ||
| 7035 | /*! @{ */ | ||
| 7036 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) | ||
| 7037 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) | ||
| 7038 | /*! FIELD - . | ||
| 7039 | */ | ||
| 7040 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) | ||
| 7041 | /*! @} */ | ||
| 7042 | |||
| 7043 | /* The count of FLASH_CFPA_CUSTOMER_DEFINED */ | ||
| 7044 | #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) | ||
| 7045 | |||
| 7046 | /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ | ||
| 7047 | /*! @{ */ | ||
| 7048 | #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) | ||
| 7049 | #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) | ||
| 7050 | /*! FIELD - . | ||
| 7051 | */ | ||
| 7052 | #define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) | ||
| 7053 | /*! @} */ | ||
| 7054 | |||
| 7055 | /* The count of FLASH_CFPA_SHA256_DIGEST */ | ||
| 7056 | #define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) | ||
| 7057 | |||
| 7058 | |||
| 7059 | /*! | ||
| 7060 | * @} | ||
| 7061 | */ /* end of group FLASH_CFPA_Register_Masks */ | ||
| 7062 | |||
| 7063 | |||
| 7064 | /* FLASH_CFPA - Peripheral instance base addresses */ | ||
| 7065 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 7066 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 7067 | #define FLASH_CFPA0_BASE (0x1009E000u) | ||
| 7068 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 7069 | #define FLASH_CFPA0_BASE_NS (0x9E000u) | ||
| 7070 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 7071 | #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) | ||
| 7072 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 7073 | #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) | ||
| 7074 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 7075 | #define FLASH_CFPA1_BASE (0x1009E200u) | ||
| 7076 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 7077 | #define FLASH_CFPA1_BASE_NS (0x9E200u) | ||
| 7078 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 7079 | #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) | ||
| 7080 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 7081 | #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) | ||
| 7082 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 7083 | #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) | ||
| 7084 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 7085 | #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) | ||
| 7086 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 7087 | #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) | ||
| 7088 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 7089 | #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) | ||
| 7090 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 7091 | #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } | ||
| 7092 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 7093 | #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } | ||
| 7094 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 7095 | #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } | ||
| 7096 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 7097 | #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } | ||
| 7098 | #else | ||
| 7099 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 7100 | #define FLASH_CFPA0_BASE (0x9E000u) | ||
| 7101 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 7102 | #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) | ||
| 7103 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 7104 | #define FLASH_CFPA1_BASE (0x9E200u) | ||
| 7105 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 7106 | #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) | ||
| 7107 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 7108 | #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) | ||
| 7109 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 7110 | #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) | ||
| 7111 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 7112 | #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } | ||
| 7113 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 7114 | #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } | ||
| 7115 | #endif | ||
| 7116 | |||
| 7117 | /*! | ||
| 7118 | * @} | ||
| 7119 | */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ | ||
| 7120 | |||
| 7121 | |||
| 7122 | /* ---------------------------------------------------------------------------- | ||
| 7123 | -- FLASH_CMPA Peripheral Access Layer | ||
| 7124 | ---------------------------------------------------------------------------- */ | ||
| 7125 | |||
| 7126 | /*! | ||
| 7127 | * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer | ||
| 7128 | * @{ | ||
| 7129 | */ | ||
| 7130 | |||
| 7131 | /** FLASH_CMPA - Register Layout Typedef */ | ||
| 7132 | typedef struct { | ||
| 7133 | __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ | ||
| 7134 | __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ | ||
| 7135 | __IO uint32_t USB_ID; /**< ., offset: 0x8 */ | ||
| 7136 | __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ | ||
| 7137 | __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */ | ||
| 7138 | __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */ | ||
| 7139 | __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */ | ||
| 7140 | __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ | ||
| 7141 | __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ | ||
| 7142 | __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ | ||
| 7143 | __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ | ||
| 7144 | __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ | ||
| 7145 | __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ | ||
| 7146 | __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ | ||
| 7147 | uint8_t RESERVED_0[24]; | ||
| 7148 | __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ | ||
| 7149 | uint8_t RESERVED_1[144]; | ||
| 7150 | __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ | ||
| 7151 | __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ | ||
| 7152 | } FLASH_CMPA_Type; | ||
| 7153 | |||
| 7154 | /* ---------------------------------------------------------------------------- | ||
| 7155 | -- FLASH_CMPA Register Masks | ||
| 7156 | ---------------------------------------------------------------------------- */ | ||
| 7157 | |||
| 7158 | /*! | ||
| 7159 | * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks | ||
| 7160 | * @{ | ||
| 7161 | */ | ||
| 7162 | |||
| 7163 | /*! @name BOOT_CFG - . */ | ||
| 7164 | /*! @{ */ | ||
| 7165 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) | ||
| 7166 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) | ||
| 7167 | /*! DEFAULT_ISP_MODE - Default ISP mode: | ||
| 7168 | * 0b000..Auto ISP | ||
| 7169 | * 0b001..USB_HID_MSC | ||
| 7170 | * 0b010..SPI Slave ISP | ||
| 7171 | * 0b011..I2C Slave ISP | ||
| 7172 | * 0b111..Disable ISP fall through | ||
| 7173 | */ | ||
| 7174 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) | ||
| 7175 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) | ||
| 7176 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) | ||
| 7177 | /*! BOOT_SPEED - Core clock: | ||
| 7178 | * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE | ||
| 7179 | * 0b01..96MHz FRO | ||
| 7180 | * 0b10..48MHz FRO | ||
| 7181 | */ | ||
| 7182 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) | ||
| 7183 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) | ||
| 7184 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) | ||
| 7185 | /*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle | ||
| 7186 | * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO | ||
| 7187 | * pin | ||
| 7188 | */ | ||
| 7189 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) | ||
| 7190 | /*! @} */ | ||
| 7191 | |||
| 7192 | /*! @name SPI_FLASH_CFG - . */ | ||
| 7193 | /*! @{ */ | ||
| 7194 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) | ||
| 7195 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) | ||
| 7196 | /*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. | ||
| 7197 | */ | ||
| 7198 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) | ||
| 7199 | /*! @} */ | ||
| 7200 | |||
| 7201 | /*! @name USB_ID - . */ | ||
| 7202 | /*! @{ */ | ||
| 7203 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) | ||
| 7204 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) | ||
| 7205 | /*! USB_VENDOR_ID - . | ||
| 7206 | */ | ||
| 7207 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) | ||
| 7208 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) | ||
| 7209 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) | ||
| 7210 | /*! USB_PRODUCT_ID - . | ||
| 7211 | */ | ||
| 7212 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) | ||
| 7213 | /*! @} */ | ||
| 7214 | |||
| 7215 | /*! @name SDIO_CFG - . */ | ||
| 7216 | /*! @{ */ | ||
| 7217 | #define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) | ||
| 7218 | #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) | ||
| 7219 | /*! FIELD - . | ||
| 7220 | */ | ||
| 7221 | #define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) | ||
| 7222 | /*! @} */ | ||
| 7223 | |||
| 7224 | /*! @name CC_SOCU_PIN - . */ | ||
| 7225 | /*! @{ */ | ||
| 7226 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) | ||
| 7227 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) | ||
| 7228 | /*! NIDEN - Non Secure non-invasive debug enable | ||
| 7229 | * 0b0..Use DAP to enable | ||
| 7230 | * 0b1..Fixed state | ||
| 7231 | */ | ||
| 7232 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) | ||
| 7233 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) | ||
| 7234 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) | ||
| 7235 | /*! DBGEN - Non Secure debug enable | ||
| 7236 | * 0b0..Use DAP to enable | ||
| 7237 | * 0b1..Fixed state | ||
| 7238 | */ | ||
| 7239 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) | ||
| 7240 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) | ||
| 7241 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) | ||
| 7242 | /*! SPNIDEN - Secure non-invasive debug enable | ||
| 7243 | * 0b0..Use DAP to enable | ||
| 7244 | * 0b1..Fixed state | ||
| 7245 | */ | ||
| 7246 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) | ||
| 7247 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) | ||
| 7248 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) | ||
| 7249 | /*! SPIDEN - Secure invasive debug enable | ||
| 7250 | * 0b0..Use DAP to enable | ||
| 7251 | * 0b1..Fixed state | ||
| 7252 | */ | ||
| 7253 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) | ||
| 7254 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) | ||
| 7255 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) | ||
| 7256 | /*! TAPEN - JTAG TAP enable | ||
| 7257 | * 0b0..Use DAP to enable | ||
| 7258 | * 0b1..Fixed state | ||
| 7259 | */ | ||
| 7260 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) | ||
| 7261 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) | ||
| 7262 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) | ||
| 7263 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable | ||
| 7264 | * 0b0..Use DAP to enable | ||
| 7265 | * 0b1..Fixed state | ||
| 7266 | */ | ||
| 7267 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) | ||
| 7268 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) | ||
| 7269 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) | ||
| 7270 | /*! ISP_CMD_EN - ISP Boot Command enable | ||
| 7271 | * 0b0..Use DAP to enable | ||
| 7272 | * 0b1..Fixed state | ||
| 7273 | */ | ||
| 7274 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) | ||
| 7275 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) | ||
| 7276 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) | ||
| 7277 | /*! FA_CMD_EN - FA Command enable | ||
| 7278 | * 0b0..Use DAP to enable | ||
| 7279 | * 0b1..Fixed state | ||
| 7280 | */ | ||
| 7281 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) | ||
| 7282 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) | ||
| 7283 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) | ||
| 7284 | /*! ME_CMD_EN - Flash Mass Erase Command enable | ||
| 7285 | * 0b0..Use DAP to enable | ||
| 7286 | * 0b1..Fixed state | ||
| 7287 | */ | ||
| 7288 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) | ||
| 7289 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) | ||
| 7290 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) | ||
| 7291 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable | ||
| 7292 | * 0b0..Use DAP to enable | ||
| 7293 | * 0b1..Fixed state | ||
| 7294 | */ | ||
| 7295 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) | ||
| 7296 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) | ||
| 7297 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) | ||
| 7298 | /*! UUID_CHECK - Enforce UUID match during Debug authentication. | ||
| 7299 | */ | ||
| 7300 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) | ||
| 7301 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 7302 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) | ||
| 7303 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 7304 | */ | ||
| 7305 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) | ||
| 7306 | /*! @} */ | ||
| 7307 | |||
| 7308 | /*! @name CC_SOCU_DFLT - . */ | ||
| 7309 | /*! @{ */ | ||
| 7310 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) | ||
| 7311 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) | ||
| 7312 | /*! NIDEN - Non Secure non-invasive debug fixed state | ||
| 7313 | * 0b0..Disable | ||
| 7314 | * 0b1..Enable | ||
| 7315 | */ | ||
| 7316 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) | ||
| 7317 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) | ||
| 7318 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) | ||
| 7319 | /*! DBGEN - Non Secure debug fixed state | ||
| 7320 | * 0b0..Disable | ||
| 7321 | * 0b1..Enable | ||
| 7322 | */ | ||
| 7323 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) | ||
| 7324 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) | ||
| 7325 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) | ||
| 7326 | /*! SPNIDEN - Secure non-invasive debug fixed state | ||
| 7327 | * 0b0..Disable | ||
| 7328 | * 0b1..Enable | ||
| 7329 | */ | ||
| 7330 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) | ||
| 7331 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) | ||
| 7332 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) | ||
| 7333 | /*! SPIDEN - Secure invasive debug fixed state | ||
| 7334 | * 0b0..Disable | ||
| 7335 | * 0b1..Enable | ||
| 7336 | */ | ||
| 7337 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) | ||
| 7338 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) | ||
| 7339 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) | ||
| 7340 | /*! TAPEN - JTAG TAP fixed state | ||
| 7341 | * 0b0..Disable | ||
| 7342 | * 0b1..Enable | ||
| 7343 | */ | ||
| 7344 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) | ||
| 7345 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) | ||
| 7346 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) | ||
| 7347 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state | ||
| 7348 | * 0b0..Disable | ||
| 7349 | * 0b1..Enable | ||
| 7350 | */ | ||
| 7351 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) | ||
| 7352 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) | ||
| 7353 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) | ||
| 7354 | /*! ISP_CMD_EN - ISP Boot Command fixed state | ||
| 7355 | * 0b0..Disable | ||
| 7356 | * 0b1..Enable | ||
| 7357 | */ | ||
| 7358 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) | ||
| 7359 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) | ||
| 7360 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) | ||
| 7361 | /*! FA_CMD_EN - FA Command fixed state | ||
| 7362 | * 0b0..Disable | ||
| 7363 | * 0b1..Enable | ||
| 7364 | */ | ||
| 7365 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) | ||
| 7366 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) | ||
| 7367 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) | ||
| 7368 | /*! ME_CMD_EN - Flash Mass Erase Command fixed state | ||
| 7369 | * 0b0..Disable | ||
| 7370 | * 0b1..Enable | ||
| 7371 | */ | ||
| 7372 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) | ||
| 7373 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) | ||
| 7374 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) | ||
| 7375 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state | ||
| 7376 | * 0b0..Disable | ||
| 7377 | * 0b1..Enable | ||
| 7378 | */ | ||
| 7379 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) | ||
| 7380 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 7381 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) | ||
| 7382 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 7383 | */ | ||
| 7384 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) | ||
| 7385 | /*! @} */ | ||
| 7386 | |||
| 7387 | /*! @name VENDOR_USAGE - . */ | ||
| 7388 | /*! @{ */ | ||
| 7389 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) | ||
| 7390 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) | ||
| 7391 | /*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. | ||
| 7392 | */ | ||
| 7393 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) | ||
| 7394 | /*! @} */ | ||
| 7395 | |||
| 7396 | /*! @name SECURE_BOOT_CFG - . */ | ||
| 7397 | /*! @{ */ | ||
| 7398 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) | ||
| 7399 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) | ||
| 7400 | /*! RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys | ||
| 7401 | */ | ||
| 7402 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) | ||
| 7403 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) | ||
| 7404 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) | ||
| 7405 | /*! DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included | ||
| 7406 | */ | ||
| 7407 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) | ||
| 7408 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) | ||
| 7409 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) | ||
| 7410 | /*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included | ||
| 7411 | */ | ||
| 7412 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) | ||
| 7413 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) | ||
| 7414 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) | ||
| 7415 | /*! SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE | ||
| 7416 | */ | ||
| 7417 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) | ||
| 7418 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) | ||
| 7419 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) | ||
| 7420 | /*! TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to | ||
| 7421 | * NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. | ||
| 7422 | */ | ||
| 7423 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) | ||
| 7424 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) | ||
| 7425 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) | ||
| 7426 | /*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation | ||
| 7427 | */ | ||
| 7428 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) | ||
| 7429 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) | ||
| 7430 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) | ||
| 7431 | /*! BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet | ||
| 7432 | */ | ||
| 7433 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) | ||
| 7434 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) | ||
| 7435 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) | ||
| 7436 | /*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE | ||
| 7437 | */ | ||
| 7438 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) | ||
| 7439 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) | ||
| 7440 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) | ||
| 7441 | /*! SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, | ||
| 7442 | * 11 - Boot signed images. (internal flash, RSA signed) | ||
| 7443 | */ | ||
| 7444 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) | ||
| 7445 | /*! @} */ | ||
| 7446 | |||
| 7447 | /*! @name PRINCE_BASE_ADDR - . */ | ||
| 7448 | /*! @{ */ | ||
| 7449 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) | ||
| 7450 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) | ||
| 7451 | /*! ADDR0_PRG - Programmable portion of the base address of region 0. | ||
| 7452 | */ | ||
| 7453 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) | ||
| 7454 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) | ||
| 7455 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) | ||
| 7456 | /*! ADDR1_PRG - Programmable portion of the base address of region 1. | ||
| 7457 | */ | ||
| 7458 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) | ||
| 7459 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) | ||
| 7460 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) | ||
| 7461 | /*! ADDR2_PRG - Programmable portion of the base address of region 2. | ||
| 7462 | */ | ||
| 7463 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) | ||
| 7464 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) | ||
| 7465 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) | ||
| 7466 | /*! LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 7467 | */ | ||
| 7468 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) | ||
| 7469 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) | ||
| 7470 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) | ||
| 7471 | /*! LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 7472 | */ | ||
| 7473 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) | ||
| 7474 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) | ||
| 7475 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) | ||
| 7476 | /*! LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 7477 | */ | ||
| 7478 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) | ||
| 7479 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) | ||
| 7480 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) | ||
| 7481 | /*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased | ||
| 7482 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 7483 | */ | ||
| 7484 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) | ||
| 7485 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) | ||
| 7486 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) | ||
| 7487 | /*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased | ||
| 7488 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 7489 | */ | ||
| 7490 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) | ||
| 7491 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) | ||
| 7492 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) | ||
| 7493 | /*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased | ||
| 7494 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 7495 | */ | ||
| 7496 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) | ||
| 7497 | /*! @} */ | ||
| 7498 | |||
| 7499 | /*! @name PRINCE_SR_0 - Region 0, sub-region enable */ | ||
| 7500 | /*! @{ */ | ||
| 7501 | #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7502 | #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) | ||
| 7503 | /*! FIELD - . | ||
| 7504 | */ | ||
| 7505 | #define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) | ||
| 7506 | /*! @} */ | ||
| 7507 | |||
| 7508 | /*! @name PRINCE_SR_1 - Region 1, sub-region enable */ | ||
| 7509 | /*! @{ */ | ||
| 7510 | #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) | ||
| 7511 | #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) | ||
| 7512 | /*! FIELD - . | ||
| 7513 | */ | ||
| 7514 | #define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) | ||
| 7515 | /*! @} */ | ||
| 7516 | |||
| 7517 | /*! @name PRINCE_SR_2 - Region 2, sub-region enable */ | ||
| 7518 | /*! @{ */ | ||
| 7519 | #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) | ||
| 7520 | #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) | ||
| 7521 | /*! FIELD - . | ||
| 7522 | */ | ||
| 7523 | #define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) | ||
| 7524 | /*! @} */ | ||
| 7525 | |||
| 7526 | /*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ | ||
| 7527 | /*! @{ */ | ||
| 7528 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) | ||
| 7529 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) | ||
| 7530 | /*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. | ||
| 7531 | */ | ||
| 7532 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) | ||
| 7533 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) | ||
| 7534 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) | ||
| 7535 | /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7536 | */ | ||
| 7537 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) | ||
| 7538 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) | ||
| 7539 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) | ||
| 7540 | /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7541 | */ | ||
| 7542 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) | ||
| 7543 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) | ||
| 7544 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) | ||
| 7545 | /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7546 | */ | ||
| 7547 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) | ||
| 7548 | /*! @} */ | ||
| 7549 | |||
| 7550 | /*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ | ||
| 7551 | /*! @{ */ | ||
| 7552 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) | ||
| 7553 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) | ||
| 7554 | /*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. | ||
| 7555 | */ | ||
| 7556 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) | ||
| 7557 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) | ||
| 7558 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) | ||
| 7559 | /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7560 | */ | ||
| 7561 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) | ||
| 7562 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) | ||
| 7563 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) | ||
| 7564 | /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7565 | */ | ||
| 7566 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) | ||
| 7567 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) | ||
| 7568 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) | ||
| 7569 | /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 7570 | */ | ||
| 7571 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) | ||
| 7572 | /*! @} */ | ||
| 7573 | |||
| 7574 | /*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ | ||
| 7575 | /*! @{ */ | ||
| 7576 | #define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) | ||
| 7577 | #define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) | ||
| 7578 | /*! FIELD - . | ||
| 7579 | */ | ||
| 7580 | #define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) | ||
| 7581 | /*! @} */ | ||
| 7582 | |||
| 7583 | /* The count of FLASH_CMPA_ROTKH */ | ||
| 7584 | #define FLASH_CMPA_ROTKH_COUNT (8U) | ||
| 7585 | |||
| 7586 | /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ | ||
| 7587 | /*! @{ */ | ||
| 7588 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) | ||
| 7589 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) | ||
| 7590 | /*! FIELD - . | ||
| 7591 | */ | ||
| 7592 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) | ||
| 7593 | /*! @} */ | ||
| 7594 | |||
| 7595 | /* The count of FLASH_CMPA_CUSTOMER_DEFINED */ | ||
| 7596 | #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) | ||
| 7597 | |||
| 7598 | /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ | ||
| 7599 | /*! @{ */ | ||
| 7600 | #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) | ||
| 7601 | #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) | ||
| 7602 | /*! FIELD - . | ||
| 7603 | */ | ||
| 7604 | #define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) | ||
| 7605 | /*! @} */ | ||
| 7606 | |||
| 7607 | /* The count of FLASH_CMPA_SHA256_DIGEST */ | ||
| 7608 | #define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) | ||
| 7609 | |||
| 7610 | |||
| 7611 | /*! | ||
| 7612 | * @} | ||
| 7613 | */ /* end of group FLASH_CMPA_Register_Masks */ | ||
| 7614 | |||
| 7615 | |||
| 7616 | /* FLASH_CMPA - Peripheral instance base addresses */ | ||
| 7617 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 7618 | /** Peripheral FLASH_CMPA base address */ | ||
| 7619 | #define FLASH_CMPA_BASE (0x1009E400u) | ||
| 7620 | /** Peripheral FLASH_CMPA base address */ | ||
| 7621 | #define FLASH_CMPA_BASE_NS (0x9E400u) | ||
| 7622 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 7623 | #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) | ||
| 7624 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 7625 | #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) | ||
| 7626 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 7627 | #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } | ||
| 7628 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 7629 | #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } | ||
| 7630 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 7631 | #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } | ||
| 7632 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 7633 | #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } | ||
| 7634 | #else | ||
| 7635 | /** Peripheral FLASH_CMPA base address */ | ||
| 7636 | #define FLASH_CMPA_BASE (0x9E400u) | ||
| 7637 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 7638 | #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) | ||
| 7639 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 7640 | #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } | ||
| 7641 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 7642 | #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } | ||
| 7643 | #endif | ||
| 7644 | |||
| 7645 | /*! | ||
| 7646 | * @} | ||
| 7647 | */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ | ||
| 7648 | |||
| 7649 | |||
| 7650 | /* ---------------------------------------------------------------------------- | ||
| 7651 | -- FLASH_KEY_STORE Peripheral Access Layer | ||
| 7652 | ---------------------------------------------------------------------------- */ | ||
| 7653 | |||
| 7654 | /*! | ||
| 7655 | * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer | ||
| 7656 | * @{ | ||
| 7657 | */ | ||
| 7658 | |||
| 7659 | /** FLASH_KEY_STORE - Register Layout Typedef */ | ||
| 7660 | typedef struct { | ||
| 7661 | struct { /* offset: 0x0 */ | ||
| 7662 | __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ | ||
| 7663 | __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ | ||
| 7664 | } KEY_STORE_HEADER; | ||
| 7665 | __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ | ||
| 7666 | union { /* offset: 0x4B0 */ | ||
| 7667 | __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ | ||
| 7668 | struct { /* offset: 0x4B0 */ | ||
| 7669 | __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ | ||
| 7670 | __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ | ||
| 7671 | __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ | ||
| 7672 | } SBKEY_KEY_CODE_CORE; | ||
| 7673 | }; | ||
| 7674 | union { /* offset: 0x4E8 */ | ||
| 7675 | __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ | ||
| 7676 | struct { /* offset: 0x4E8 */ | ||
| 7677 | __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ | ||
| 7678 | __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ | ||
| 7679 | __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ | ||
| 7680 | } USER_KEK_KEY_CODE_CORE; | ||
| 7681 | }; | ||
| 7682 | union { /* offset: 0x520 */ | ||
| 7683 | __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ | ||
| 7684 | struct { /* offset: 0x520 */ | ||
| 7685 | __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ | ||
| 7686 | __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ | ||
| 7687 | __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ | ||
| 7688 | } UDS_KEY_CODE_CORE; | ||
| 7689 | }; | ||
| 7690 | union { /* offset: 0x558 */ | ||
| 7691 | __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ | ||
| 7692 | struct { /* offset: 0x558 */ | ||
| 7693 | __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ | ||
| 7694 | __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ | ||
| 7695 | __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ | ||
| 7696 | } PRINCE_REGION0_KEY_CODE_CORE; | ||
| 7697 | }; | ||
| 7698 | union { /* offset: 0x590 */ | ||
| 7699 | __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ | ||
| 7700 | struct { /* offset: 0x590 */ | ||
| 7701 | __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ | ||
| 7702 | __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ | ||
| 7703 | __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ | ||
| 7704 | } PRINCE_REGION1_KEY_CODE_CORE; | ||
| 7705 | }; | ||
| 7706 | union { /* offset: 0x5C8 */ | ||
| 7707 | __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ | ||
| 7708 | struct { /* offset: 0x5C8 */ | ||
| 7709 | __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ | ||
| 7710 | __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ | ||
| 7711 | __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ | ||
| 7712 | } PRINCE_REGION2_KEY_CODE_CORE; | ||
| 7713 | }; | ||
| 7714 | } FLASH_KEY_STORE_Type; | ||
| 7715 | |||
| 7716 | /* ---------------------------------------------------------------------------- | ||
| 7717 | -- FLASH_KEY_STORE Register Masks | ||
| 7718 | ---------------------------------------------------------------------------- */ | ||
| 7719 | |||
| 7720 | /*! | ||
| 7721 | * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks | ||
| 7722 | * @{ | ||
| 7723 | */ | ||
| 7724 | |||
| 7725 | /*! @name HEADER - Valid Key Sore Header : 0x95959595 */ | ||
| 7726 | /*! @{ */ | ||
| 7727 | #define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) | ||
| 7728 | #define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) | ||
| 7729 | /*! FIELD - . | ||
| 7730 | */ | ||
| 7731 | #define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) | ||
| 7732 | /*! @} */ | ||
| 7733 | |||
| 7734 | /*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ | ||
| 7735 | /*! @{ */ | ||
| 7736 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) | ||
| 7737 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) | ||
| 7738 | /*! FIELD - . | ||
| 7739 | */ | ||
| 7740 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) | ||
| 7741 | /*! @} */ | ||
| 7742 | |||
| 7743 | /*! @name ACTIVATION_CODE - . */ | ||
| 7744 | /*! @{ */ | ||
| 7745 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7746 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) | ||
| 7747 | /*! FIELD - . | ||
| 7748 | */ | ||
| 7749 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) | ||
| 7750 | /*! @} */ | ||
| 7751 | |||
| 7752 | /* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ | ||
| 7753 | #define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) | ||
| 7754 | |||
| 7755 | /*! @name SBKEY_KEY_CODE - . */ | ||
| 7756 | /*! @{ */ | ||
| 7757 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7758 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) | ||
| 7759 | /*! FIELD - . | ||
| 7760 | */ | ||
| 7761 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) | ||
| 7762 | /*! @} */ | ||
| 7763 | |||
| 7764 | /* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ | ||
| 7765 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) | ||
| 7766 | |||
| 7767 | /*! @name SBKEY_HEADER0 - . */ | ||
| 7768 | /*! @{ */ | ||
| 7769 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7770 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) | ||
| 7771 | /*! FIELD - . | ||
| 7772 | */ | ||
| 7773 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) | ||
| 7774 | /*! @} */ | ||
| 7775 | |||
| 7776 | /*! @name SBKEY_HEADER1 - . */ | ||
| 7777 | /*! @{ */ | ||
| 7778 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) | ||
| 7779 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) | ||
| 7780 | /*! TYPE - . | ||
| 7781 | */ | ||
| 7782 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) | ||
| 7783 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) | ||
| 7784 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) | ||
| 7785 | /*! INDEX - . | ||
| 7786 | */ | ||
| 7787 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) | ||
| 7788 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7789 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) | ||
| 7790 | /*! SIZE - . | ||
| 7791 | */ | ||
| 7792 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) | ||
| 7793 | /*! @} */ | ||
| 7794 | |||
| 7795 | /*! @name SBKEY_BODY - . */ | ||
| 7796 | /*! @{ */ | ||
| 7797 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7798 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) | ||
| 7799 | /*! FIELD - . | ||
| 7800 | */ | ||
| 7801 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) | ||
| 7802 | /*! @} */ | ||
| 7803 | |||
| 7804 | /* The count of FLASH_KEY_STORE_SBKEY_BODY */ | ||
| 7805 | #define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) | ||
| 7806 | |||
| 7807 | /*! @name USER_KEK_KEY_CODE - . */ | ||
| 7808 | /*! @{ */ | ||
| 7809 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7810 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) | ||
| 7811 | /*! FIELD - . | ||
| 7812 | */ | ||
| 7813 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) | ||
| 7814 | /*! @} */ | ||
| 7815 | |||
| 7816 | /* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ | ||
| 7817 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) | ||
| 7818 | |||
| 7819 | /*! @name USER_KEK_HEADER0 - . */ | ||
| 7820 | /*! @{ */ | ||
| 7821 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7822 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) | ||
| 7823 | /*! FIELD - . | ||
| 7824 | */ | ||
| 7825 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) | ||
| 7826 | /*! @} */ | ||
| 7827 | |||
| 7828 | /*! @name USER_KEK_HEADER1 - . */ | ||
| 7829 | /*! @{ */ | ||
| 7830 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) | ||
| 7831 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) | ||
| 7832 | /*! TYPE - . | ||
| 7833 | */ | ||
| 7834 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) | ||
| 7835 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) | ||
| 7836 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) | ||
| 7837 | /*! INDEX - . | ||
| 7838 | */ | ||
| 7839 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) | ||
| 7840 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7841 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) | ||
| 7842 | /*! SIZE - . | ||
| 7843 | */ | ||
| 7844 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) | ||
| 7845 | /*! @} */ | ||
| 7846 | |||
| 7847 | /*! @name USER_KEK_BODY - . */ | ||
| 7848 | /*! @{ */ | ||
| 7849 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7850 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) | ||
| 7851 | /*! FIELD - . | ||
| 7852 | */ | ||
| 7853 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) | ||
| 7854 | /*! @} */ | ||
| 7855 | |||
| 7856 | /* The count of FLASH_KEY_STORE_USER_KEK_BODY */ | ||
| 7857 | #define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) | ||
| 7858 | |||
| 7859 | /*! @name UDS_KEY_CODE - . */ | ||
| 7860 | /*! @{ */ | ||
| 7861 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7862 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) | ||
| 7863 | /*! FIELD - . | ||
| 7864 | */ | ||
| 7865 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) | ||
| 7866 | /*! @} */ | ||
| 7867 | |||
| 7868 | /* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ | ||
| 7869 | #define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) | ||
| 7870 | |||
| 7871 | /*! @name UDS_HEADER0 - . */ | ||
| 7872 | /*! @{ */ | ||
| 7873 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7874 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) | ||
| 7875 | /*! FIELD - . | ||
| 7876 | */ | ||
| 7877 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) | ||
| 7878 | /*! @} */ | ||
| 7879 | |||
| 7880 | /*! @name UDS_HEADER1 - . */ | ||
| 7881 | /*! @{ */ | ||
| 7882 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) | ||
| 7883 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) | ||
| 7884 | /*! TYPE - . | ||
| 7885 | */ | ||
| 7886 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) | ||
| 7887 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) | ||
| 7888 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) | ||
| 7889 | /*! INDEX - . | ||
| 7890 | */ | ||
| 7891 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) | ||
| 7892 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7893 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) | ||
| 7894 | /*! SIZE - . | ||
| 7895 | */ | ||
| 7896 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) | ||
| 7897 | /*! @} */ | ||
| 7898 | |||
| 7899 | /*! @name UDS_BODY - . */ | ||
| 7900 | /*! @{ */ | ||
| 7901 | #define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7902 | #define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) | ||
| 7903 | /*! FIELD - . | ||
| 7904 | */ | ||
| 7905 | #define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) | ||
| 7906 | /*! @} */ | ||
| 7907 | |||
| 7908 | /* The count of FLASH_KEY_STORE_UDS_BODY */ | ||
| 7909 | #define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) | ||
| 7910 | |||
| 7911 | /*! @name PRINCE_REGION0_KEY_CODE - . */ | ||
| 7912 | /*! @{ */ | ||
| 7913 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7914 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) | ||
| 7915 | /*! FIELD - . | ||
| 7916 | */ | ||
| 7917 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) | ||
| 7918 | /*! @} */ | ||
| 7919 | |||
| 7920 | /* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ | ||
| 7921 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) | ||
| 7922 | |||
| 7923 | /*! @name PRINCE_REGION0_HEADER0 - . */ | ||
| 7924 | /*! @{ */ | ||
| 7925 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7926 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) | ||
| 7927 | /*! FIELD - . | ||
| 7928 | */ | ||
| 7929 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) | ||
| 7930 | /*! @} */ | ||
| 7931 | |||
| 7932 | /*! @name PRINCE_REGION0_HEADER1 - . */ | ||
| 7933 | /*! @{ */ | ||
| 7934 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) | ||
| 7935 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) | ||
| 7936 | /*! TYPE - . | ||
| 7937 | */ | ||
| 7938 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) | ||
| 7939 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) | ||
| 7940 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) | ||
| 7941 | /*! INDEX - . | ||
| 7942 | */ | ||
| 7943 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) | ||
| 7944 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7945 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) | ||
| 7946 | /*! SIZE - . | ||
| 7947 | */ | ||
| 7948 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) | ||
| 7949 | /*! @} */ | ||
| 7950 | |||
| 7951 | /*! @name PRINCE_REGION0_BODY - . */ | ||
| 7952 | /*! @{ */ | ||
| 7953 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7954 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) | ||
| 7955 | /*! FIELD - . | ||
| 7956 | */ | ||
| 7957 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) | ||
| 7958 | /*! @} */ | ||
| 7959 | |||
| 7960 | /* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ | ||
| 7961 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) | ||
| 7962 | |||
| 7963 | /*! @name PRINCE_REGION1_KEY_CODE - . */ | ||
| 7964 | /*! @{ */ | ||
| 7965 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7966 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) | ||
| 7967 | /*! FIELD - . | ||
| 7968 | */ | ||
| 7969 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) | ||
| 7970 | /*! @} */ | ||
| 7971 | |||
| 7972 | /* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ | ||
| 7973 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) | ||
| 7974 | |||
| 7975 | /*! @name PRINCE_REGION1_HEADER0 - . */ | ||
| 7976 | /*! @{ */ | ||
| 7977 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7978 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) | ||
| 7979 | /*! FIELD - . | ||
| 7980 | */ | ||
| 7981 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) | ||
| 7982 | /*! @} */ | ||
| 7983 | |||
| 7984 | /*! @name PRINCE_REGION1_HEADER1 - . */ | ||
| 7985 | /*! @{ */ | ||
| 7986 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) | ||
| 7987 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) | ||
| 7988 | /*! TYPE - . | ||
| 7989 | */ | ||
| 7990 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) | ||
| 7991 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) | ||
| 7992 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) | ||
| 7993 | /*! INDEX - . | ||
| 7994 | */ | ||
| 7995 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) | ||
| 7996 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7997 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) | ||
| 7998 | /*! SIZE - . | ||
| 7999 | */ | ||
| 8000 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) | ||
| 8001 | /*! @} */ | ||
| 8002 | |||
| 8003 | /*! @name PRINCE_REGION1_BODY - . */ | ||
| 8004 | /*! @{ */ | ||
| 8005 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8006 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) | ||
| 8007 | /*! FIELD - . | ||
| 8008 | */ | ||
| 8009 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) | ||
| 8010 | /*! @} */ | ||
| 8011 | |||
| 8012 | /* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ | ||
| 8013 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) | ||
| 8014 | |||
| 8015 | /*! @name PRINCE_REGION2_KEY_CODE - . */ | ||
| 8016 | /*! @{ */ | ||
| 8017 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8018 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8019 | /*! FIELD - . | ||
| 8020 | */ | ||
| 8021 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) | ||
| 8022 | /*! @} */ | ||
| 8023 | |||
| 8024 | /* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ | ||
| 8025 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) | ||
| 8026 | |||
| 8027 | /*! @name PRINCE_REGION2_HEADER0 - . */ | ||
| 8028 | /*! @{ */ | ||
| 8029 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8030 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) | ||
| 8031 | /*! FIELD - . | ||
| 8032 | */ | ||
| 8033 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) | ||
| 8034 | /*! @} */ | ||
| 8035 | |||
| 8036 | /*! @name PRINCE_REGION2_HEADER1 - . */ | ||
| 8037 | /*! @{ */ | ||
| 8038 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) | ||
| 8039 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) | ||
| 8040 | /*! TYPE - . | ||
| 8041 | */ | ||
| 8042 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) | ||
| 8043 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) | ||
| 8044 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) | ||
| 8045 | /*! INDEX - . | ||
| 8046 | */ | ||
| 8047 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) | ||
| 8048 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8049 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) | ||
| 8050 | /*! SIZE - . | ||
| 8051 | */ | ||
| 8052 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) | ||
| 8053 | /*! @} */ | ||
| 8054 | |||
| 8055 | /*! @name PRINCE_REGION2_BODY - . */ | ||
| 8056 | /*! @{ */ | ||
| 8057 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8058 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) | ||
| 8059 | /*! FIELD - . | ||
| 8060 | */ | ||
| 8061 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) | ||
| 8062 | /*! @} */ | ||
| 8063 | |||
| 8064 | /* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ | ||
| 8065 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) | ||
| 8066 | |||
| 8067 | |||
| 8068 | /*! | ||
| 8069 | * @} | ||
| 8070 | */ /* end of group FLASH_KEY_STORE_Register_Masks */ | ||
| 8071 | |||
| 8072 | |||
| 8073 | /* FLASH_KEY_STORE - Peripheral instance base addresses */ | ||
| 8074 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 8075 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 8076 | #define FLASH_KEY_STORE_BASE (0x1009E600u) | ||
| 8077 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 8078 | #define FLASH_KEY_STORE_BASE_NS (0x9E600u) | ||
| 8079 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 8080 | #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) | ||
| 8081 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 8082 | #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) | ||
| 8083 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 8084 | #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } | ||
| 8085 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 8086 | #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } | ||
| 8087 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 8088 | #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } | ||
| 8089 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 8090 | #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } | ||
| 8091 | #else | ||
| 8092 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 8093 | #define FLASH_KEY_STORE_BASE (0x9E600u) | ||
| 8094 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 8095 | #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) | ||
| 8096 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 8097 | #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } | ||
| 8098 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 8099 | #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } | ||
| 8100 | #endif | ||
| 8101 | |||
| 8102 | /*! | ||
| 8103 | * @} | ||
| 8104 | */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ | ||
| 8105 | |||
| 8106 | |||
| 8107 | /* ---------------------------------------------------------------------------- | ||
| 8108 | -- FLEXCOMM Peripheral Access Layer | ||
| 8109 | ---------------------------------------------------------------------------- */ | ||
| 8110 | |||
| 8111 | /*! | ||
| 8112 | * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer | ||
| 8113 | * @{ | ||
| 8114 | */ | ||
| 8115 | |||
| 8116 | /** FLEXCOMM - Register Layout Typedef */ | ||
| 8117 | typedef struct { | ||
| 8118 | uint8_t RESERVED_0[4088]; | ||
| 8119 | __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ | ||
| 8120 | __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ | ||
| 8121 | } FLEXCOMM_Type; | ||
| 8122 | |||
| 8123 | /* ---------------------------------------------------------------------------- | ||
| 8124 | -- FLEXCOMM Register Masks | ||
| 8125 | ---------------------------------------------------------------------------- */ | ||
| 8126 | |||
| 8127 | /*! | ||
| 8128 | * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks | ||
| 8129 | * @{ | ||
| 8130 | */ | ||
| 8131 | |||
| 8132 | /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ | ||
| 8133 | /*! @{ */ | ||
| 8134 | #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) | ||
| 8135 | #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) | ||
| 8136 | /*! PERSEL - Peripheral Select. This field is writable by software. | ||
| 8137 | * 0b000..No peripheral selected. | ||
| 8138 | * 0b001..USART function selected. | ||
| 8139 | * 0b010..SPI function selected. | ||
| 8140 | * 0b011..I2C function selected. | ||
| 8141 | * 0b100..I2S transmit function selected. | ||
| 8142 | * 0b101..I2S receive function selected. | ||
| 8143 | * 0b110..Reserved | ||
| 8144 | * 0b111..Reserved | ||
| 8145 | */ | ||
| 8146 | #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) | ||
| 8147 | #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) | ||
| 8148 | #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) | ||
| 8149 | /*! LOCK - Lock the peripheral select. This field is writable by software. | ||
| 8150 | * 0b0..Peripheral select can be changed by software. | ||
| 8151 | * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. | ||
| 8152 | */ | ||
| 8153 | #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) | ||
| 8154 | #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) | ||
| 8155 | #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) | ||
| 8156 | /*! USARTPRESENT - USART present indicator. This field is Read-only. | ||
| 8157 | * 0b0..This Flexcomm does not include the USART function. | ||
| 8158 | * 0b1..This Flexcomm includes the USART function. | ||
| 8159 | */ | ||
| 8160 | #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) | ||
| 8161 | #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) | ||
| 8162 | #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) | ||
| 8163 | /*! SPIPRESENT - SPI present indicator. This field is Read-only. | ||
| 8164 | * 0b0..This Flexcomm does not include the SPI function. | ||
| 8165 | * 0b1..This Flexcomm includes the SPI function. | ||
| 8166 | */ | ||
| 8167 | #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) | ||
| 8168 | #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) | ||
| 8169 | #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) | ||
| 8170 | /*! I2CPRESENT - I2C present indicator. This field is Read-only. | ||
| 8171 | * 0b0..This Flexcomm does not include the I2C function. | ||
| 8172 | * 0b1..This Flexcomm includes the I2C function. | ||
| 8173 | */ | ||
| 8174 | #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) | ||
| 8175 | #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) | ||
| 8176 | #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) | ||
| 8177 | /*! I2SPRESENT - I 2S present indicator. This field is Read-only. | ||
| 8178 | * 0b0..This Flexcomm does not include the I2S function. | ||
| 8179 | * 0b1..This Flexcomm includes the I2S function. | ||
| 8180 | */ | ||
| 8181 | #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) | ||
| 8182 | #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) | ||
| 8183 | #define FLEXCOMM_PSELID_ID_SHIFT (12U) | ||
| 8184 | /*! ID - Flexcomm ID. | ||
| 8185 | */ | ||
| 8186 | #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) | ||
| 8187 | /*! @} */ | ||
| 8188 | |||
| 8189 | /*! @name PID - Peripheral identification register. */ | ||
| 8190 | /*! @{ */ | ||
| 8191 | #define FLEXCOMM_PID_APERTURE_MASK (0xFFU) | ||
| 8192 | #define FLEXCOMM_PID_APERTURE_SHIFT (0U) | ||
| 8193 | /*! APERTURE - size aperture for the register port on the bus (APB or AHB). | ||
| 8194 | */ | ||
| 8195 | #define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) | ||
| 8196 | #define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) | ||
| 8197 | #define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) | ||
| 8198 | /*! MINOR_REV - Minor revision of module implementation. | ||
| 8199 | */ | ||
| 8200 | #define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) | ||
| 8201 | #define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) | ||
| 8202 | #define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) | ||
| 8203 | /*! MAJOR_REV - Major revision of module implementation. | ||
| 8204 | */ | ||
| 8205 | #define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) | ||
| 8206 | #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) | ||
| 8207 | #define FLEXCOMM_PID_ID_SHIFT (16U) | ||
| 8208 | /*! ID - Module identifier for the selected function. | ||
| 8209 | */ | ||
| 8210 | #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) | ||
| 8211 | /*! @} */ | ||
| 8212 | |||
| 8213 | |||
| 8214 | /*! | ||
| 8215 | * @} | ||
| 8216 | */ /* end of group FLEXCOMM_Register_Masks */ | ||
| 8217 | |||
| 8218 | |||
| 8219 | /* FLEXCOMM - Peripheral instance base addresses */ | ||
| 8220 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 8221 | /** Peripheral FLEXCOMM0 base address */ | ||
| 8222 | #define FLEXCOMM0_BASE (0x50086000u) | ||
| 8223 | /** Peripheral FLEXCOMM0 base address */ | ||
| 8224 | #define FLEXCOMM0_BASE_NS (0x40086000u) | ||
| 8225 | /** Peripheral FLEXCOMM0 base pointer */ | ||
| 8226 | #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) | ||
| 8227 | /** Peripheral FLEXCOMM0 base pointer */ | ||
| 8228 | #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) | ||
| 8229 | /** Peripheral FLEXCOMM1 base address */ | ||
| 8230 | #define FLEXCOMM1_BASE (0x50087000u) | ||
| 8231 | /** Peripheral FLEXCOMM1 base address */ | ||
| 8232 | #define FLEXCOMM1_BASE_NS (0x40087000u) | ||
| 8233 | /** Peripheral FLEXCOMM1 base pointer */ | ||
| 8234 | #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) | ||
| 8235 | /** Peripheral FLEXCOMM1 base pointer */ | ||
| 8236 | #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) | ||
| 8237 | /** Peripheral FLEXCOMM2 base address */ | ||
| 8238 | #define FLEXCOMM2_BASE (0x50088000u) | ||
| 8239 | /** Peripheral FLEXCOMM2 base address */ | ||
| 8240 | #define FLEXCOMM2_BASE_NS (0x40088000u) | ||
| 8241 | /** Peripheral FLEXCOMM2 base pointer */ | ||
| 8242 | #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) | ||
| 8243 | /** Peripheral FLEXCOMM2 base pointer */ | ||
| 8244 | #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) | ||
| 8245 | /** Peripheral FLEXCOMM3 base address */ | ||
| 8246 | #define FLEXCOMM3_BASE (0x50089000u) | ||
| 8247 | /** Peripheral FLEXCOMM3 base address */ | ||
| 8248 | #define FLEXCOMM3_BASE_NS (0x40089000u) | ||
| 8249 | /** Peripheral FLEXCOMM3 base pointer */ | ||
| 8250 | #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) | ||
| 8251 | /** Peripheral FLEXCOMM3 base pointer */ | ||
| 8252 | #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) | ||
| 8253 | /** Peripheral FLEXCOMM4 base address */ | ||
| 8254 | #define FLEXCOMM4_BASE (0x5008A000u) | ||
| 8255 | /** Peripheral FLEXCOMM4 base address */ | ||
| 8256 | #define FLEXCOMM4_BASE_NS (0x4008A000u) | ||
| 8257 | /** Peripheral FLEXCOMM4 base pointer */ | ||
| 8258 | #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) | ||
| 8259 | /** Peripheral FLEXCOMM4 base pointer */ | ||
| 8260 | #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) | ||
| 8261 | /** Peripheral FLEXCOMM5 base address */ | ||
| 8262 | #define FLEXCOMM5_BASE (0x50096000u) | ||
| 8263 | /** Peripheral FLEXCOMM5 base address */ | ||
| 8264 | #define FLEXCOMM5_BASE_NS (0x40096000u) | ||
| 8265 | /** Peripheral FLEXCOMM5 base pointer */ | ||
| 8266 | #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) | ||
| 8267 | /** Peripheral FLEXCOMM5 base pointer */ | ||
| 8268 | #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) | ||
| 8269 | /** Peripheral FLEXCOMM6 base address */ | ||
| 8270 | #define FLEXCOMM6_BASE (0x50097000u) | ||
| 8271 | /** Peripheral FLEXCOMM6 base address */ | ||
| 8272 | #define FLEXCOMM6_BASE_NS (0x40097000u) | ||
| 8273 | /** Peripheral FLEXCOMM6 base pointer */ | ||
| 8274 | #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) | ||
| 8275 | /** Peripheral FLEXCOMM6 base pointer */ | ||
| 8276 | #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) | ||
| 8277 | /** Peripheral FLEXCOMM7 base address */ | ||
| 8278 | #define FLEXCOMM7_BASE (0x50098000u) | ||
| 8279 | /** Peripheral FLEXCOMM7 base address */ | ||
| 8280 | #define FLEXCOMM7_BASE_NS (0x40098000u) | ||
| 8281 | /** Peripheral FLEXCOMM7 base pointer */ | ||
| 8282 | #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) | ||
| 8283 | /** Peripheral FLEXCOMM7 base pointer */ | ||
| 8284 | #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) | ||
| 8285 | /** Peripheral FLEXCOMM8 base address */ | ||
| 8286 | #define FLEXCOMM8_BASE (0x5009F000u) | ||
| 8287 | /** Peripheral FLEXCOMM8 base address */ | ||
| 8288 | #define FLEXCOMM8_BASE_NS (0x4009F000u) | ||
| 8289 | /** Peripheral FLEXCOMM8 base pointer */ | ||
| 8290 | #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) | ||
| 8291 | /** Peripheral FLEXCOMM8 base pointer */ | ||
| 8292 | #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) | ||
| 8293 | /** Array initializer of FLEXCOMM peripheral base addresses */ | ||
| 8294 | #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } | ||
| 8295 | /** Array initializer of FLEXCOMM peripheral base pointers */ | ||
| 8296 | #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } | ||
| 8297 | /** Array initializer of FLEXCOMM peripheral base addresses */ | ||
| 8298 | #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } | ||
| 8299 | /** Array initializer of FLEXCOMM peripheral base pointers */ | ||
| 8300 | #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } | ||
| 8301 | #else | ||
| 8302 | /** Peripheral FLEXCOMM0 base address */ | ||
| 8303 | #define FLEXCOMM0_BASE (0x40086000u) | ||
| 8304 | /** Peripheral FLEXCOMM0 base pointer */ | ||
| 8305 | #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) | ||
| 8306 | /** Peripheral FLEXCOMM1 base address */ | ||
| 8307 | #define FLEXCOMM1_BASE (0x40087000u) | ||
| 8308 | /** Peripheral FLEXCOMM1 base pointer */ | ||
| 8309 | #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) | ||
| 8310 | /** Peripheral FLEXCOMM2 base address */ | ||
| 8311 | #define FLEXCOMM2_BASE (0x40088000u) | ||
| 8312 | /** Peripheral FLEXCOMM2 base pointer */ | ||
| 8313 | #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) | ||
| 8314 | /** Peripheral FLEXCOMM3 base address */ | ||
| 8315 | #define FLEXCOMM3_BASE (0x40089000u) | ||
| 8316 | /** Peripheral FLEXCOMM3 base pointer */ | ||
| 8317 | #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) | ||
| 8318 | /** Peripheral FLEXCOMM4 base address */ | ||
| 8319 | #define FLEXCOMM4_BASE (0x4008A000u) | ||
| 8320 | /** Peripheral FLEXCOMM4 base pointer */ | ||
| 8321 | #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) | ||
| 8322 | /** Peripheral FLEXCOMM5 base address */ | ||
| 8323 | #define FLEXCOMM5_BASE (0x40096000u) | ||
| 8324 | /** Peripheral FLEXCOMM5 base pointer */ | ||
| 8325 | #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) | ||
| 8326 | /** Peripheral FLEXCOMM6 base address */ | ||
| 8327 | #define FLEXCOMM6_BASE (0x40097000u) | ||
| 8328 | /** Peripheral FLEXCOMM6 base pointer */ | ||
| 8329 | #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) | ||
| 8330 | /** Peripheral FLEXCOMM7 base address */ | ||
| 8331 | #define FLEXCOMM7_BASE (0x40098000u) | ||
| 8332 | /** Peripheral FLEXCOMM7 base pointer */ | ||
| 8333 | #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) | ||
| 8334 | /** Peripheral FLEXCOMM8 base address */ | ||
| 8335 | #define FLEXCOMM8_BASE (0x4009F000u) | ||
| 8336 | /** Peripheral FLEXCOMM8 base pointer */ | ||
| 8337 | #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) | ||
| 8338 | /** Array initializer of FLEXCOMM peripheral base addresses */ | ||
| 8339 | #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } | ||
| 8340 | /** Array initializer of FLEXCOMM peripheral base pointers */ | ||
| 8341 | #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } | ||
| 8342 | #endif | ||
| 8343 | /** Interrupt vectors for the FLEXCOMM peripheral type */ | ||
| 8344 | #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } | ||
| 8345 | |||
| 8346 | /*! | ||
| 8347 | * @} | ||
| 8348 | */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ | ||
| 8349 | |||
| 8350 | |||
| 8351 | /* ---------------------------------------------------------------------------- | ||
| 8352 | -- GINT Peripheral Access Layer | ||
| 8353 | ---------------------------------------------------------------------------- */ | ||
| 8354 | |||
| 8355 | /*! | ||
| 8356 | * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer | ||
| 8357 | * @{ | ||
| 8358 | */ | ||
| 8359 | |||
| 8360 | /** GINT - Register Layout Typedef */ | ||
| 8361 | typedef struct { | ||
| 8362 | __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ | ||
| 8363 | uint8_t RESERVED_0[28]; | ||
| 8364 | __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ | ||
| 8365 | uint8_t RESERVED_1[24]; | ||
| 8366 | __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ | ||
| 8367 | } GINT_Type; | ||
| 8368 | |||
| 8369 | /* ---------------------------------------------------------------------------- | ||
| 8370 | -- GINT Register Masks | ||
| 8371 | ---------------------------------------------------------------------------- */ | ||
| 8372 | |||
| 8373 | /*! | ||
| 8374 | * @addtogroup GINT_Register_Masks GINT Register Masks | ||
| 8375 | * @{ | ||
| 8376 | */ | ||
| 8377 | |||
| 8378 | /*! @name CTRL - GPIO grouped interrupt control register */ | ||
| 8379 | /*! @{ */ | ||
| 8380 | #define GINT_CTRL_INT_MASK (0x1U) | ||
| 8381 | #define GINT_CTRL_INT_SHIFT (0U) | ||
| 8382 | /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. | ||
| 8383 | * 0b0..No request. No interrupt request is pending. | ||
| 8384 | * 0b1..Request active. Interrupt request is active. | ||
| 8385 | */ | ||
| 8386 | #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) | ||
| 8387 | #define GINT_CTRL_COMB_MASK (0x2U) | ||
| 8388 | #define GINT_CTRL_COMB_SHIFT (1U) | ||
| 8389 | /*! COMB - Combine enabled inputs for group interrupt | ||
| 8390 | * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). | ||
| 8391 | * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). | ||
| 8392 | */ | ||
| 8393 | #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) | ||
| 8394 | #define GINT_CTRL_TRIG_MASK (0x4U) | ||
| 8395 | #define GINT_CTRL_TRIG_SHIFT (2U) | ||
| 8396 | /*! TRIG - Group interrupt trigger | ||
| 8397 | * 0b0..Edge-triggered. | ||
| 8398 | * 0b1..Level-triggered. | ||
| 8399 | */ | ||
| 8400 | #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) | ||
| 8401 | /*! @} */ | ||
| 8402 | |||
| 8403 | /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ | ||
| 8404 | /*! @{ */ | ||
| 8405 | #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) | ||
| 8406 | #define GINT_PORT_POL_POL_SHIFT (0U) | ||
| 8407 | /*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n | ||
| 8408 | * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to | ||
| 8409 | * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin | ||
| 8410 | * contributes to the group interrupt. | ||
| 8411 | */ | ||
| 8412 | #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) | ||
| 8413 | /*! @} */ | ||
| 8414 | |||
| 8415 | /* The count of GINT_PORT_POL */ | ||
| 8416 | #define GINT_PORT_POL_COUNT (2U) | ||
| 8417 | |||
| 8418 | /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ | ||
| 8419 | /*! @{ */ | ||
| 8420 | #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) | ||
| 8421 | #define GINT_PORT_ENA_ENA_SHIFT (0U) | ||
| 8422 | /*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the | ||
| 8423 | * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is | ||
| 8424 | * enabled and contributes to the grouped interrupt. | ||
| 8425 | */ | ||
| 8426 | #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) | ||
| 8427 | /*! @} */ | ||
| 8428 | |||
| 8429 | /* The count of GINT_PORT_ENA */ | ||
| 8430 | #define GINT_PORT_ENA_COUNT (2U) | ||
| 8431 | |||
| 8432 | |||
| 8433 | /*! | ||
| 8434 | * @} | ||
| 8435 | */ /* end of group GINT_Register_Masks */ | ||
| 8436 | |||
| 8437 | |||
| 8438 | /* GINT - Peripheral instance base addresses */ | ||
| 8439 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 8440 | /** Peripheral GINT0 base address */ | ||
| 8441 | #define GINT0_BASE (0x50002000u) | ||
| 8442 | /** Peripheral GINT0 base address */ | ||
| 8443 | #define GINT0_BASE_NS (0x40002000u) | ||
| 8444 | /** Peripheral GINT0 base pointer */ | ||
| 8445 | #define GINT0 ((GINT_Type *)GINT0_BASE) | ||
| 8446 | /** Peripheral GINT0 base pointer */ | ||
| 8447 | #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) | ||
| 8448 | /** Peripheral GINT1 base address */ | ||
| 8449 | #define GINT1_BASE (0x50003000u) | ||
| 8450 | /** Peripheral GINT1 base address */ | ||
| 8451 | #define GINT1_BASE_NS (0x40003000u) | ||
| 8452 | /** Peripheral GINT1 base pointer */ | ||
| 8453 | #define GINT1 ((GINT_Type *)GINT1_BASE) | ||
| 8454 | /** Peripheral GINT1 base pointer */ | ||
| 8455 | #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) | ||
| 8456 | /** Array initializer of GINT peripheral base addresses */ | ||
| 8457 | #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } | ||
| 8458 | /** Array initializer of GINT peripheral base pointers */ | ||
| 8459 | #define GINT_BASE_PTRS { GINT0, GINT1 } | ||
| 8460 | /** Array initializer of GINT peripheral base addresses */ | ||
| 8461 | #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } | ||
| 8462 | /** Array initializer of GINT peripheral base pointers */ | ||
| 8463 | #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } | ||
| 8464 | #else | ||
| 8465 | /** Peripheral GINT0 base address */ | ||
| 8466 | #define GINT0_BASE (0x40002000u) | ||
| 8467 | /** Peripheral GINT0 base pointer */ | ||
| 8468 | #define GINT0 ((GINT_Type *)GINT0_BASE) | ||
| 8469 | /** Peripheral GINT1 base address */ | ||
| 8470 | #define GINT1_BASE (0x40003000u) | ||
| 8471 | /** Peripheral GINT1 base pointer */ | ||
| 8472 | #define GINT1 ((GINT_Type *)GINT1_BASE) | ||
| 8473 | /** Array initializer of GINT peripheral base addresses */ | ||
| 8474 | #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } | ||
| 8475 | /** Array initializer of GINT peripheral base pointers */ | ||
| 8476 | #define GINT_BASE_PTRS { GINT0, GINT1 } | ||
| 8477 | #endif | ||
| 8478 | /** Interrupt vectors for the GINT peripheral type */ | ||
| 8479 | #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } | ||
| 8480 | |||
| 8481 | /*! | ||
| 8482 | * @} | ||
| 8483 | */ /* end of group GINT_Peripheral_Access_Layer */ | ||
| 8484 | |||
| 8485 | |||
| 8486 | /* ---------------------------------------------------------------------------- | ||
| 8487 | -- GPIO Peripheral Access Layer | ||
| 8488 | ---------------------------------------------------------------------------- */ | ||
| 8489 | |||
| 8490 | /*! | ||
| 8491 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer | ||
| 8492 | * @{ | ||
| 8493 | */ | ||
| 8494 | |||
| 8495 | /** GPIO - Register Layout Typedef */ | ||
| 8496 | typedef struct { | ||
| 8497 | __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ | ||
| 8498 | uint8_t RESERVED_0[4032]; | ||
| 8499 | __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ | ||
| 8500 | uint8_t RESERVED_1[3840]; | ||
| 8501 | __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ | ||
| 8502 | uint8_t RESERVED_2[120]; | ||
| 8503 | __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ | ||
| 8504 | uint8_t RESERVED_3[120]; | ||
| 8505 | __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ | ||
| 8506 | uint8_t RESERVED_4[120]; | ||
| 8507 | __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ | ||
| 8508 | uint8_t RESERVED_5[120]; | ||
| 8509 | __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ | ||
| 8510 | uint8_t RESERVED_6[120]; | ||
| 8511 | __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ | ||
| 8512 | uint8_t RESERVED_7[120]; | ||
| 8513 | __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ | ||
| 8514 | uint8_t RESERVED_8[120]; | ||
| 8515 | __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ | ||
| 8516 | uint8_t RESERVED_9[120]; | ||
| 8517 | __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ | ||
| 8518 | uint8_t RESERVED_10[120]; | ||
| 8519 | __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ | ||
| 8520 | } GPIO_Type; | ||
| 8521 | |||
| 8522 | /* ---------------------------------------------------------------------------- | ||
| 8523 | -- GPIO Register Masks | ||
| 8524 | ---------------------------------------------------------------------------- */ | ||
| 8525 | |||
| 8526 | /*! | ||
| 8527 | * @addtogroup GPIO_Register_Masks GPIO Register Masks | ||
| 8528 | * @{ | ||
| 8529 | */ | ||
| 8530 | |||
| 8531 | /*! @name B - Byte pin registers for all port GPIO pins */ | ||
| 8532 | /*! @{ */ | ||
| 8533 | #define GPIO_B_PBYTE_MASK (0x1U) | ||
| 8534 | #define GPIO_B_PBYTE_SHIFT (0U) | ||
| 8535 | /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, | ||
| 8536 | * except that pins configured as analog I/O always read as 0. One register for each port pin. | ||
| 8537 | * Supported pins depends on the specific device and package. Write: loads the pin's output bit. | ||
| 8538 | * One register for each port pin. Supported pins depends on the specific device and package. | ||
| 8539 | */ | ||
| 8540 | #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) | ||
| 8541 | /*! @} */ | ||
| 8542 | |||
| 8543 | /* The count of GPIO_B */ | ||
| 8544 | #define GPIO_B_COUNT (2U) | ||
| 8545 | |||
| 8546 | /* The count of GPIO_B */ | ||
| 8547 | #define GPIO_B_COUNT2 (32U) | ||
| 8548 | |||
| 8549 | /*! @name W - Word pin registers for all port GPIO pins */ | ||
| 8550 | /*! @{ */ | ||
| 8551 | #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) | ||
| 8552 | #define GPIO_W_PWORD_SHIFT (0U) | ||
| 8553 | /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is | ||
| 8554 | * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be | ||
| 8555 | * read. Writing any value other than 0 will set the output bit. One register for each port pin. | ||
| 8556 | * Supported pins depends on the specific device and package. | ||
| 8557 | */ | ||
| 8558 | #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) | ||
| 8559 | /*! @} */ | ||
| 8560 | |||
| 8561 | /* The count of GPIO_W */ | ||
| 8562 | #define GPIO_W_COUNT (2U) | ||
| 8563 | |||
| 8564 | /* The count of GPIO_W */ | ||
| 8565 | #define GPIO_W_COUNT2 (32U) | ||
| 8566 | |||
| 8567 | /*! @name DIR - Direction registers for all port GPIO pins */ | ||
| 8568 | /*! @{ */ | ||
| 8569 | #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) | ||
| 8570 | #define GPIO_DIR_DIRP_SHIFT (0U) | ||
| 8571 | /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported | ||
| 8572 | * pins depends on the specific device and package. 0 = input. 1 = output. | ||
| 8573 | */ | ||
| 8574 | #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) | ||
| 8575 | /*! @} */ | ||
| 8576 | |||
| 8577 | /* The count of GPIO_DIR */ | ||
| 8578 | #define GPIO_DIR_COUNT (2U) | ||
| 8579 | |||
| 8580 | /*! @name MASK - Mask register for all port GPIO pins */ | ||
| 8581 | /*! @{ */ | ||
| 8582 | #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) | ||
| 8583 | #define GPIO_MASK_MASKP_SHIFT (0U) | ||
| 8584 | /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = | ||
| 8585 | * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = | ||
| 8586 | * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit | ||
| 8587 | * not affected. | ||
| 8588 | */ | ||
| 8589 | #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) | ||
| 8590 | /*! @} */ | ||
| 8591 | |||
| 8592 | /* The count of GPIO_MASK */ | ||
| 8593 | #define GPIO_MASK_COUNT (2U) | ||
| 8594 | |||
| 8595 | /*! @name PIN - Port pin register for all port GPIO pins */ | ||
| 8596 | /*! @{ */ | ||
| 8597 | #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) | ||
| 8598 | #define GPIO_PIN_PORT_SHIFT (0U) | ||
| 8599 | /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported | ||
| 8600 | * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. | ||
| 8601 | * 1 = Read: pin is high; write: set output bit. | ||
| 8602 | */ | ||
| 8603 | #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) | ||
| 8604 | /*! @} */ | ||
| 8605 | |||
| 8606 | /* The count of GPIO_PIN */ | ||
| 8607 | #define GPIO_PIN_COUNT (2U) | ||
| 8608 | |||
| 8609 | /*! @name MPIN - Masked port register for all port GPIO pins */ | ||
| 8610 | /*! @{ */ | ||
| 8611 | #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) | ||
| 8612 | #define GPIO_MPIN_MPORTP_SHIFT (0U) | ||
| 8613 | /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 8614 | * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK | ||
| 8615 | * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 | ||
| 8616 | * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit | ||
| 8617 | * if the corresponding bit in the MASK register is 0. | ||
| 8618 | */ | ||
| 8619 | #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) | ||
| 8620 | /*! @} */ | ||
| 8621 | |||
| 8622 | /* The count of GPIO_MPIN */ | ||
| 8623 | #define GPIO_MPIN_COUNT (2U) | ||
| 8624 | |||
| 8625 | /*! @name SET - Write: Set register for port. Read: output bits for port */ | ||
| 8626 | /*! @{ */ | ||
| 8627 | #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) | ||
| 8628 | #define GPIO_SET_SETP_SHIFT (0U) | ||
| 8629 | /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 8630 | * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output | ||
| 8631 | * bit; write: set output bit. | ||
| 8632 | */ | ||
| 8633 | #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) | ||
| 8634 | /*! @} */ | ||
| 8635 | |||
| 8636 | /* The count of GPIO_SET */ | ||
| 8637 | #define GPIO_SET_COUNT (2U) | ||
| 8638 | |||
| 8639 | /*! @name CLR - Clear port for all port GPIO pins */ | ||
| 8640 | /*! @{ */ | ||
| 8641 | #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) | ||
| 8642 | #define GPIO_CLR_CLRP_SHIFT (0U) | ||
| 8643 | /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the | ||
| 8644 | * specific device and package. 0 = No operation. 1 = Clear output bit. | ||
| 8645 | */ | ||
| 8646 | #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) | ||
| 8647 | /*! @} */ | ||
| 8648 | |||
| 8649 | /* The count of GPIO_CLR */ | ||
| 8650 | #define GPIO_CLR_COUNT (2U) | ||
| 8651 | |||
| 8652 | /*! @name NOT - Toggle port for all port GPIO pins */ | ||
| 8653 | /*! @{ */ | ||
| 8654 | #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) | ||
| 8655 | #define GPIO_NOT_NOTP_SHIFT (0U) | ||
| 8656 | /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the | ||
| 8657 | * specific device and package. 0 = no operation. 1 = Toggle output bit. | ||
| 8658 | */ | ||
| 8659 | #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) | ||
| 8660 | /*! @} */ | ||
| 8661 | |||
| 8662 | /* The count of GPIO_NOT */ | ||
| 8663 | #define GPIO_NOT_COUNT (2U) | ||
| 8664 | |||
| 8665 | /*! @name DIRSET - Set pin direction bits for port */ | ||
| 8666 | /*! @{ */ | ||
| 8667 | #define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) | ||
| 8668 | #define GPIO_DIRSET_DIRSETP_SHIFT (0U) | ||
| 8669 | /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 8670 | * the specific device and package. 0 = No operation. 1 = Set direction bit. | ||
| 8671 | */ | ||
| 8672 | #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) | ||
| 8673 | /*! @} */ | ||
| 8674 | |||
| 8675 | /* The count of GPIO_DIRSET */ | ||
| 8676 | #define GPIO_DIRSET_COUNT (2U) | ||
| 8677 | |||
| 8678 | /*! @name DIRCLR - Clear pin direction bits for port */ | ||
| 8679 | /*! @{ */ | ||
| 8680 | #define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) | ||
| 8681 | #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) | ||
| 8682 | /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 8683 | * the specific device and package. 0 = No operation. 1 = Clear direction bit. | ||
| 8684 | */ | ||
| 8685 | #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) | ||
| 8686 | /*! @} */ | ||
| 8687 | |||
| 8688 | /* The count of GPIO_DIRCLR */ | ||
| 8689 | #define GPIO_DIRCLR_COUNT (2U) | ||
| 8690 | |||
| 8691 | /*! @name DIRNOT - Toggle pin direction bits for port */ | ||
| 8692 | /*! @{ */ | ||
| 8693 | #define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) | ||
| 8694 | #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) | ||
| 8695 | /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends | ||
| 8696 | * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. | ||
| 8697 | */ | ||
| 8698 | #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) | ||
| 8699 | /*! @} */ | ||
| 8700 | |||
| 8701 | /* The count of GPIO_DIRNOT */ | ||
| 8702 | #define GPIO_DIRNOT_COUNT (2U) | ||
| 8703 | |||
| 8704 | |||
| 8705 | /*! | ||
| 8706 | * @} | ||
| 8707 | */ /* end of group GPIO_Register_Masks */ | ||
| 8708 | |||
| 8709 | |||
| 8710 | /* GPIO - Peripheral instance base addresses */ | ||
| 8711 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 8712 | /** Peripheral GPIO base address */ | ||
| 8713 | #define GPIO_BASE (0x5008C000u) | ||
| 8714 | /** Peripheral GPIO base address */ | ||
| 8715 | #define GPIO_BASE_NS (0x4008C000u) | ||
| 8716 | /** Peripheral GPIO base pointer */ | ||
| 8717 | #define GPIO ((GPIO_Type *)GPIO_BASE) | ||
| 8718 | /** Peripheral GPIO base pointer */ | ||
| 8719 | #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) | ||
| 8720 | /** Peripheral SECGPIO base address */ | ||
| 8721 | #define SECGPIO_BASE (0x500A8000u) | ||
| 8722 | /** Peripheral SECGPIO base address */ | ||
| 8723 | #define SECGPIO_BASE_NS (0x400A8000u) | ||
| 8724 | /** Peripheral SECGPIO base pointer */ | ||
| 8725 | #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) | ||
| 8726 | /** Peripheral SECGPIO base pointer */ | ||
| 8727 | #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) | ||
| 8728 | /** Array initializer of GPIO peripheral base addresses */ | ||
| 8729 | #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } | ||
| 8730 | /** Array initializer of GPIO peripheral base pointers */ | ||
| 8731 | #define GPIO_BASE_PTRS { GPIO, SECGPIO } | ||
| 8732 | /** Array initializer of GPIO peripheral base addresses */ | ||
| 8733 | #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } | ||
| 8734 | /** Array initializer of GPIO peripheral base pointers */ | ||
| 8735 | #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } | ||
| 8736 | #else | ||
| 8737 | /** Peripheral GPIO base address */ | ||
| 8738 | #define GPIO_BASE (0x4008C000u) | ||
| 8739 | /** Peripheral GPIO base pointer */ | ||
| 8740 | #define GPIO ((GPIO_Type *)GPIO_BASE) | ||
| 8741 | /** Peripheral SECGPIO base address */ | ||
| 8742 | #define SECGPIO_BASE (0x400A8000u) | ||
| 8743 | /** Peripheral SECGPIO base pointer */ | ||
| 8744 | #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) | ||
| 8745 | /** Array initializer of GPIO peripheral base addresses */ | ||
| 8746 | #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } | ||
| 8747 | /** Array initializer of GPIO peripheral base pointers */ | ||
| 8748 | #define GPIO_BASE_PTRS { GPIO, SECGPIO } | ||
| 8749 | #endif | ||
| 8750 | |||
| 8751 | /*! | ||
| 8752 | * @} | ||
| 8753 | */ /* end of group GPIO_Peripheral_Access_Layer */ | ||
| 8754 | |||
| 8755 | |||
| 8756 | /* ---------------------------------------------------------------------------- | ||
| 8757 | -- I2C Peripheral Access Layer | ||
| 8758 | ---------------------------------------------------------------------------- */ | ||
| 8759 | |||
| 8760 | /*! | ||
| 8761 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer | ||
| 8762 | * @{ | ||
| 8763 | */ | ||
| 8764 | |||
| 8765 | /** I2C - Register Layout Typedef */ | ||
| 8766 | typedef struct { | ||
| 8767 | uint8_t RESERVED_0[2048]; | ||
| 8768 | __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ | ||
| 8769 | __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ | ||
| 8770 | __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ | ||
| 8771 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ | ||
| 8772 | __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ | ||
| 8773 | __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ | ||
| 8774 | __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ | ||
| 8775 | uint8_t RESERVED_1[4]; | ||
| 8776 | __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ | ||
| 8777 | __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ | ||
| 8778 | __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ | ||
| 8779 | uint8_t RESERVED_2[20]; | ||
| 8780 | __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ | ||
| 8781 | __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ | ||
| 8782 | __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ | ||
| 8783 | __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ | ||
| 8784 | uint8_t RESERVED_3[36]; | ||
| 8785 | __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ | ||
| 8786 | uint8_t RESERVED_4[1912]; | ||
| 8787 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ | ||
| 8788 | } I2C_Type; | ||
| 8789 | |||
| 8790 | /* ---------------------------------------------------------------------------- | ||
| 8791 | -- I2C Register Masks | ||
| 8792 | ---------------------------------------------------------------------------- */ | ||
| 8793 | |||
| 8794 | /*! | ||
| 8795 | * @addtogroup I2C_Register_Masks I2C Register Masks | ||
| 8796 | * @{ | ||
| 8797 | */ | ||
| 8798 | |||
| 8799 | /*! @name CFG - Configuration for shared functions. */ | ||
| 8800 | /*! @{ */ | ||
| 8801 | #define I2C_CFG_MSTEN_MASK (0x1U) | ||
| 8802 | #define I2C_CFG_MSTEN_SHIFT (0U) | ||
| 8803 | /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not | ||
| 8804 | * changed, but the Master function is internally reset. | ||
| 8805 | * 0b0..Disabled. The I2C Master function is disabled. | ||
| 8806 | * 0b1..Enabled. The I2C Master function is enabled. | ||
| 8807 | */ | ||
| 8808 | #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) | ||
| 8809 | #define I2C_CFG_SLVEN_MASK (0x2U) | ||
| 8810 | #define I2C_CFG_SLVEN_SHIFT (1U) | ||
| 8811 | /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not | ||
| 8812 | * changed, but the Slave function is internally reset. | ||
| 8813 | * 0b0..Disabled. The I2C slave function is disabled. | ||
| 8814 | * 0b1..Enabled. The I2C slave function is enabled. | ||
| 8815 | */ | ||
| 8816 | #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) | ||
| 8817 | #define I2C_CFG_MONEN_MASK (0x4U) | ||
| 8818 | #define I2C_CFG_MONEN_SHIFT (2U) | ||
| 8819 | /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not | ||
| 8820 | * changed, but the Monitor function is internally reset. | ||
| 8821 | * 0b0..Disabled. The I2C Monitor function is disabled. | ||
| 8822 | * 0b1..Enabled. The I2C Monitor function is enabled. | ||
| 8823 | */ | ||
| 8824 | #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) | ||
| 8825 | #define I2C_CFG_TIMEOUTEN_MASK (0x8U) | ||
| 8826 | #define I2C_CFG_TIMEOUTEN_SHIFT (3U) | ||
| 8827 | /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. | ||
| 8828 | * 0b0..Disabled. Time-out function is disabled. | ||
| 8829 | * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause | ||
| 8830 | * interrupts if they are enabled. Typically, only one time-out will be used in a system. | ||
| 8831 | */ | ||
| 8832 | #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) | ||
| 8833 | #define I2C_CFG_MONCLKSTR_MASK (0x10U) | ||
| 8834 | #define I2C_CFG_MONCLKSTR_SHIFT (4U) | ||
| 8835 | /*! MONCLKSTR - Monitor function Clock Stretching. | ||
| 8836 | * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able | ||
| 8837 | * to read data provided by the Monitor function before it is overwritten. This mode may be used when | ||
| 8838 | * non-invasive monitoring is critical. | ||
| 8839 | * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can | ||
| 8840 | * read all incoming data supplied by the Monitor function. | ||
| 8841 | */ | ||
| 8842 | #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) | ||
| 8843 | #define I2C_CFG_HSCAPABLE_MASK (0x20U) | ||
| 8844 | #define I2C_CFG_HSCAPABLE_SHIFT (5U) | ||
| 8845 | /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive | ||
| 8846 | * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies | ||
| 8847 | * to all functions: Master, Slave, and Monitor. | ||
| 8848 | * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the | ||
| 8849 | * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, | ||
| 8850 | * such as changing the drive strength or filtering, must be made by software via the IOCON register associated | ||
| 8851 | * with each I2C pin, | ||
| 8852 | * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support | ||
| 8853 | * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more | ||
| 8854 | * information. | ||
| 8855 | */ | ||
| 8856 | #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) | ||
| 8857 | /*! @} */ | ||
| 8858 | |||
| 8859 | /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ | ||
| 8860 | /*! @{ */ | ||
| 8861 | #define I2C_STAT_MSTPENDING_MASK (0x1U) | ||
| 8862 | #define I2C_STAT_MSTPENDING_SHIFT (0U) | ||
| 8863 | /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on | ||
| 8864 | * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what | ||
| 8865 | * type of software service if any the master expects. This flag will cause an interrupt when set | ||
| 8866 | * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling | ||
| 8867 | * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle | ||
| 8868 | * state, and no communication is needed, mask this interrupt. | ||
| 8869 | * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. | ||
| 8870 | * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the | ||
| 8871 | * idle state, it is waiting to receive or transmit data or the NACK bit. | ||
| 8872 | */ | ||
| 8873 | #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) | ||
| 8874 | #define I2C_STAT_MSTSTATE_MASK (0xEU) | ||
| 8875 | #define I2C_STAT_MSTSTATE_SHIFT (1U) | ||
| 8876 | /*! MSTSTATE - Master State code. The master state code reflects the master state when the | ||
| 8877 | * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field | ||
| 8878 | * indicates a specific required service for the Master function. All other values are reserved. See | ||
| 8879 | * Table 400 for details of state values and appropriate responses. | ||
| 8880 | * 0b000..Idle. The Master function is available to be used for a new transaction. | ||
| 8881 | * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. | ||
| 8882 | * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. | ||
| 8883 | * 0b011..NACK Address. Slave NACKed address. | ||
| 8884 | * 0b100..NACK Data. Slave NACKed transmitted data. | ||
| 8885 | */ | ||
| 8886 | #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) | ||
| 8887 | #define I2C_STAT_MSTARBLOSS_MASK (0x10U) | ||
| 8888 | #define I2C_STAT_MSTARBLOSS_SHIFT (4U) | ||
| 8889 | /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to | ||
| 8890 | * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. | ||
| 8891 | * 0b0..No Arbitration Loss has occurred. | ||
| 8892 | * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master | ||
| 8893 | * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, | ||
| 8894 | * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. | ||
| 8895 | */ | ||
| 8896 | #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) | ||
| 8897 | #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) | ||
| 8898 | #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) | ||
| 8899 | /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to | ||
| 8900 | * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. | ||
| 8901 | * 0b0..No Start/Stop Error has occurred. | ||
| 8902 | * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is | ||
| 8903 | * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an | ||
| 8904 | * idle state, no action is required. A request for a Start could be made, or software could attempt to insure | ||
| 8905 | * that the bus has not stalled. | ||
| 8906 | */ | ||
| 8907 | #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) | ||
| 8908 | #define I2C_STAT_SLVPENDING_MASK (0x100U) | ||
| 8909 | #define I2C_STAT_SLVPENDING_SHIFT (8U) | ||
| 8910 | /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue | ||
| 8911 | * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if | ||
| 8912 | * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the | ||
| 8913 | * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is | ||
| 8914 | * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time | ||
| 8915 | * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section | ||
| 8916 | * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are | ||
| 8917 | * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must | ||
| 8918 | * also be detected automatically, since the address must be acknowledged before the clock can be | ||
| 8919 | * stretched. | ||
| 8920 | * 0b0..In progress. The Slave function does not currently need service. | ||
| 8921 | * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. | ||
| 8922 | */ | ||
| 8923 | #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) | ||
| 8924 | #define I2C_STAT_SLVSTATE_MASK (0x600U) | ||
| 8925 | #define I2C_STAT_SLVSTATE_SHIFT (9U) | ||
| 8926 | /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for | ||
| 8927 | * the Slave function. All other values are reserved. See Table 401 for state values and actions. | ||
| 8928 | * note that the occurrence of some states and how they are handled are affected by DMA mode and | ||
| 8929 | * Automatic Operation modes. | ||
| 8930 | * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. | ||
| 8931 | * 0b01..Slave receive. Received data is available (Slave Receiver mode). | ||
| 8932 | * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). | ||
| 8933 | */ | ||
| 8934 | #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) | ||
| 8935 | #define I2C_STAT_SLVNOTSTR_MASK (0x800U) | ||
| 8936 | #define I2C_STAT_SLVNOTSTR_SHIFT (11U) | ||
| 8937 | /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. | ||
| 8938 | * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave | ||
| 8939 | * operation. This read-only flag reflects the slave function status in real time. | ||
| 8940 | * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. | ||
| 8941 | * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or | ||
| 8942 | * Power-down mode could be entered at this time. | ||
| 8943 | */ | ||
| 8944 | #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) | ||
| 8945 | #define I2C_STAT_SLVIDX_MASK (0x3000U) | ||
| 8946 | #define I2C_STAT_SLVIDX_SHIFT (12U) | ||
| 8947 | /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been | ||
| 8948 | * selected by receiving an address that matches one of the slave addresses defined by any enabled | ||
| 8949 | * slave address registers, and provides an identification of the address that was matched. It is | ||
| 8950 | * possible that more than one address could be matched, but only one match can be reported here. | ||
| 8951 | * 0b00..Address 0. Slave address 0 was matched. | ||
| 8952 | * 0b01..Address 1. Slave address 1 was matched. | ||
| 8953 | * 0b10..Address 2. Slave address 2 was matched. | ||
| 8954 | * 0b11..Address 3. Slave address 3 was matched. | ||
| 8955 | */ | ||
| 8956 | #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) | ||
| 8957 | #define I2C_STAT_SLVSEL_MASK (0x4000U) | ||
| 8958 | #define I2C_STAT_SLVSEL_SHIFT (14U) | ||
| 8959 | /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave | ||
| 8960 | * function to acknowledge the address, or when the address has been automatically acknowledged. | ||
| 8961 | * It is cleared when another address cycle presents an address that does not match an enabled | ||
| 8962 | * address on the Slave function, when slave software decides to NACK a matched address, when | ||
| 8963 | * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of | ||
| 8964 | * Automatic Operation. SLVSEL is not cleared if software NACKs data. | ||
| 8965 | * 0b0..Not selected. The Slave function is not currently selected. | ||
| 8966 | * 0b1..Selected. The Slave function is currently selected. | ||
| 8967 | */ | ||
| 8968 | #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) | ||
| 8969 | #define I2C_STAT_SLVDESEL_MASK (0x8000U) | ||
| 8970 | #define I2C_STAT_SLVDESEL_SHIFT (15U) | ||
| 8971 | /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via | ||
| 8972 | * INTENSET. This flag can be cleared by writing a 1 to this bit. | ||
| 8973 | * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently | ||
| 8974 | * selected. That information can be found in the SLVSEL flag. | ||
| 8975 | * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag | ||
| 8976 | * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. | ||
| 8977 | */ | ||
| 8978 | #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) | ||
| 8979 | #define I2C_STAT_MONRDY_MASK (0x10000U) | ||
| 8980 | #define I2C_STAT_MONRDY_SHIFT (16U) | ||
| 8981 | /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. | ||
| 8982 | * 0b0..No data. The Monitor function does not currently have data available. | ||
| 8983 | * 0b1..Data waiting. The Monitor function has data waiting to be read. | ||
| 8984 | */ | ||
| 8985 | #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) | ||
| 8986 | #define I2C_STAT_MONOV_MASK (0x20000U) | ||
| 8987 | #define I2C_STAT_MONOV_SHIFT (17U) | ||
| 8988 | /*! MONOV - Monitor Overflow flag. | ||
| 8989 | * 0b0..No overrun. Monitor data has not overrun. | ||
| 8990 | * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not | ||
| 8991 | * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. | ||
| 8992 | */ | ||
| 8993 | #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) | ||
| 8994 | #define I2C_STAT_MONACTIVE_MASK (0x40000U) | ||
| 8995 | #define I2C_STAT_MONACTIVE_SHIFT (18U) | ||
| 8996 | /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to | ||
| 8997 | * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred | ||
| 8998 | * more recently than a bus Stop. | ||
| 8999 | * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. | ||
| 9000 | * 0b1..Active. The Monitor function considers the I2C bus to be active. | ||
| 9001 | */ | ||
| 9002 | #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) | ||
| 9003 | #define I2C_STAT_MONIDLE_MASK (0x80000U) | ||
| 9004 | #define I2C_STAT_MONIDLE_SHIFT (19U) | ||
| 9005 | /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change | ||
| 9006 | * from active to inactive. This can be used by software to decide when to process data | ||
| 9007 | * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the | ||
| 9008 | * INTENSET register. The flag can be cleared by writing a 1 to this bit. | ||
| 9009 | * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. | ||
| 9010 | * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. | ||
| 9011 | */ | ||
| 9012 | #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) | ||
| 9013 | #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) | ||
| 9014 | #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) | ||
| 9015 | /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been | ||
| 9016 | * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock | ||
| 9017 | * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus | ||
| 9018 | * is idle. | ||
| 9019 | * 0b0..No time-out. I2C bus events have not caused a time-out. | ||
| 9020 | * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. | ||
| 9021 | */ | ||
| 9022 | #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) | ||
| 9023 | #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) | ||
| 9024 | #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) | ||
| 9025 | /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the | ||
| 9026 | * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. | ||
| 9027 | * 0b0..No time-out. SCL low time has not caused a time-out. | ||
| 9028 | * 0b1..Time-out. SCL low time has caused a time-out. | ||
| 9029 | */ | ||
| 9030 | #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) | ||
| 9031 | /*! @} */ | ||
| 9032 | |||
| 9033 | /*! @name INTENSET - Interrupt Enable Set and read register. */ | ||
| 9034 | /*! @{ */ | ||
| 9035 | #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) | ||
| 9036 | #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) | ||
| 9037 | /*! MSTPENDINGEN - Master Pending interrupt Enable. | ||
| 9038 | * 0b0..Disabled. The MstPending interrupt is disabled. | ||
| 9039 | * 0b1..Enabled. The MstPending interrupt is enabled. | ||
| 9040 | */ | ||
| 9041 | #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) | ||
| 9042 | #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) | ||
| 9043 | #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) | ||
| 9044 | /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. | ||
| 9045 | * 0b0..Disabled. The MstArbLoss interrupt is disabled. | ||
| 9046 | * 0b1..Enabled. The MstArbLoss interrupt is enabled. | ||
| 9047 | */ | ||
| 9048 | #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) | ||
| 9049 | #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) | ||
| 9050 | #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) | ||
| 9051 | /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. | ||
| 9052 | * 0b0..Disabled. The MstStStpErr interrupt is disabled. | ||
| 9053 | * 0b1..Enabled. The MstStStpErr interrupt is enabled. | ||
| 9054 | */ | ||
| 9055 | #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) | ||
| 9056 | #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) | ||
| 9057 | #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) | ||
| 9058 | /*! SLVPENDINGEN - Slave Pending interrupt Enable. | ||
| 9059 | * 0b0..Disabled. The SlvPending interrupt is disabled. | ||
| 9060 | * 0b1..Enabled. The SlvPending interrupt is enabled. | ||
| 9061 | */ | ||
| 9062 | #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) | ||
| 9063 | #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) | ||
| 9064 | #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) | ||
| 9065 | /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. | ||
| 9066 | * 0b0..Disabled. The SlvNotStr interrupt is disabled. | ||
| 9067 | * 0b1..Enabled. The SlvNotStr interrupt is enabled. | ||
| 9068 | */ | ||
| 9069 | #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) | ||
| 9070 | #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) | ||
| 9071 | #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) | ||
| 9072 | /*! SLVDESELEN - Slave Deselect interrupt Enable. | ||
| 9073 | * 0b0..Disabled. The SlvDeSel interrupt is disabled. | ||
| 9074 | * 0b1..Enabled. The SlvDeSel interrupt is enabled. | ||
| 9075 | */ | ||
| 9076 | #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) | ||
| 9077 | #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) | ||
| 9078 | #define I2C_INTENSET_MONRDYEN_SHIFT (16U) | ||
| 9079 | /*! MONRDYEN - Monitor data Ready interrupt Enable. | ||
| 9080 | * 0b0..Disabled. The MonRdy interrupt is disabled. | ||
| 9081 | * 0b1..Enabled. The MonRdy interrupt is enabled. | ||
| 9082 | */ | ||
| 9083 | #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) | ||
| 9084 | #define I2C_INTENSET_MONOVEN_MASK (0x20000U) | ||
| 9085 | #define I2C_INTENSET_MONOVEN_SHIFT (17U) | ||
| 9086 | /*! MONOVEN - Monitor Overrun interrupt Enable. | ||
| 9087 | * 0b0..Disabled. The MonOv interrupt is disabled. | ||
| 9088 | * 0b1..Enabled. The MonOv interrupt is enabled. | ||
| 9089 | */ | ||
| 9090 | #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) | ||
| 9091 | #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) | ||
| 9092 | #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) | ||
| 9093 | /*! MONIDLEEN - Monitor Idle interrupt Enable. | ||
| 9094 | * 0b0..Disabled. The MonIdle interrupt is disabled. | ||
| 9095 | * 0b1..Enabled. The MonIdle interrupt is enabled. | ||
| 9096 | */ | ||
| 9097 | #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) | ||
| 9098 | #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) | ||
| 9099 | #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) | ||
| 9100 | /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. | ||
| 9101 | * 0b0..Disabled. The Event time-out interrupt is disabled. | ||
| 9102 | * 0b1..Enabled. The Event time-out interrupt is enabled. | ||
| 9103 | */ | ||
| 9104 | #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) | ||
| 9105 | #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) | ||
| 9106 | #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) | ||
| 9107 | /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. | ||
| 9108 | * 0b0..Disabled. The SCL time-out interrupt is disabled. | ||
| 9109 | * 0b1..Enabled. The SCL time-out interrupt is enabled. | ||
| 9110 | */ | ||
| 9111 | #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) | ||
| 9112 | /*! @} */ | ||
| 9113 | |||
| 9114 | /*! @name INTENCLR - Interrupt Enable Clear register. */ | ||
| 9115 | /*! @{ */ | ||
| 9116 | #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) | ||
| 9117 | #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) | ||
| 9118 | /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding | ||
| 9119 | * bit in the INTENSET register if implemented. | ||
| 9120 | */ | ||
| 9121 | #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) | ||
| 9122 | #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) | ||
| 9123 | #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) | ||
| 9124 | /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. | ||
| 9125 | */ | ||
| 9126 | #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) | ||
| 9127 | #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) | ||
| 9128 | #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) | ||
| 9129 | /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. | ||
| 9130 | */ | ||
| 9131 | #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) | ||
| 9132 | #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) | ||
| 9133 | #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) | ||
| 9134 | /*! SLVPENDINGCLR - Slave Pending interrupt clear. | ||
| 9135 | */ | ||
| 9136 | #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) | ||
| 9137 | #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) | ||
| 9138 | #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) | ||
| 9139 | /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. | ||
| 9140 | */ | ||
| 9141 | #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) | ||
| 9142 | #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) | ||
| 9143 | #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) | ||
| 9144 | /*! SLVDESELCLR - Slave Deselect interrupt clear. | ||
| 9145 | */ | ||
| 9146 | #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) | ||
| 9147 | #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) | ||
| 9148 | #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) | ||
| 9149 | /*! MONRDYCLR - Monitor data Ready interrupt clear. | ||
| 9150 | */ | ||
| 9151 | #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) | ||
| 9152 | #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) | ||
| 9153 | #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) | ||
| 9154 | /*! MONOVCLR - Monitor Overrun interrupt clear. | ||
| 9155 | */ | ||
| 9156 | #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) | ||
| 9157 | #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) | ||
| 9158 | #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) | ||
| 9159 | /*! MONIDLECLR - Monitor Idle interrupt clear. | ||
| 9160 | */ | ||
| 9161 | #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) | ||
| 9162 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) | ||
| 9163 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) | ||
| 9164 | /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. | ||
| 9165 | */ | ||
| 9166 | #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) | ||
| 9167 | #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) | ||
| 9168 | #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) | ||
| 9169 | /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. | ||
| 9170 | */ | ||
| 9171 | #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) | ||
| 9172 | /*! @} */ | ||
| 9173 | |||
| 9174 | /*! @name TIMEOUT - Time-out value register. */ | ||
| 9175 | /*! @{ */ | ||
| 9176 | #define I2C_TIMEOUT_TOMIN_MASK (0xFU) | ||
| 9177 | #define I2C_TIMEOUT_TOMIN_SHIFT (0U) | ||
| 9178 | /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum | ||
| 9179 | * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. | ||
| 9180 | */ | ||
| 9181 | #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) | ||
| 9182 | #define I2C_TIMEOUT_TO_MASK (0xFFF0U) | ||
| 9183 | #define I2C_TIMEOUT_TO_SHIFT (4U) | ||
| 9184 | /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C | ||
| 9185 | * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, | ||
| 9186 | * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A | ||
| 9187 | * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after | ||
| 9188 | * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the | ||
| 9189 | * I2C function clock. | ||
| 9190 | */ | ||
| 9191 | #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) | ||
| 9192 | /*! @} */ | ||
| 9193 | |||
| 9194 | /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ | ||
| 9195 | /*! @{ */ | ||
| 9196 | #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) | ||
| 9197 | #define I2C_CLKDIV_DIVVAL_SHIFT (0U) | ||
| 9198 | /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that | ||
| 9199 | * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = | ||
| 9200 | * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is | ||
| 9201 | * divided by 65,536 before use. | ||
| 9202 | */ | ||
| 9203 | #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) | ||
| 9204 | /*! @} */ | ||
| 9205 | |||
| 9206 | /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ | ||
| 9207 | /*! @{ */ | ||
| 9208 | #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) | ||
| 9209 | #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) | ||
| 9210 | /*! MSTPENDING - Master Pending. | ||
| 9211 | */ | ||
| 9212 | #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) | ||
| 9213 | #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) | ||
| 9214 | #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) | ||
| 9215 | /*! MSTARBLOSS - Master Arbitration Loss flag. | ||
| 9216 | */ | ||
| 9217 | #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) | ||
| 9218 | #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) | ||
| 9219 | #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) | ||
| 9220 | /*! MSTSTSTPERR - Master Start/Stop Error flag. | ||
| 9221 | */ | ||
| 9222 | #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) | ||
| 9223 | #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) | ||
| 9224 | #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) | ||
| 9225 | /*! SLVPENDING - Slave Pending. | ||
| 9226 | */ | ||
| 9227 | #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) | ||
| 9228 | #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) | ||
| 9229 | #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) | ||
| 9230 | /*! SLVNOTSTR - Slave Not Stretching status. | ||
| 9231 | */ | ||
| 9232 | #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) | ||
| 9233 | #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) | ||
| 9234 | #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) | ||
| 9235 | /*! SLVDESEL - Slave Deselected flag. | ||
| 9236 | */ | ||
| 9237 | #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) | ||
| 9238 | #define I2C_INTSTAT_MONRDY_MASK (0x10000U) | ||
| 9239 | #define I2C_INTSTAT_MONRDY_SHIFT (16U) | ||
| 9240 | /*! MONRDY - Monitor Ready. | ||
| 9241 | */ | ||
| 9242 | #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) | ||
| 9243 | #define I2C_INTSTAT_MONOV_MASK (0x20000U) | ||
| 9244 | #define I2C_INTSTAT_MONOV_SHIFT (17U) | ||
| 9245 | /*! MONOV - Monitor Overflow flag. | ||
| 9246 | */ | ||
| 9247 | #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) | ||
| 9248 | #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) | ||
| 9249 | #define I2C_INTSTAT_MONIDLE_SHIFT (19U) | ||
| 9250 | /*! MONIDLE - Monitor Idle flag. | ||
| 9251 | */ | ||
| 9252 | #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) | ||
| 9253 | #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) | ||
| 9254 | #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) | ||
| 9255 | /*! EVENTTIMEOUT - Event time-out Interrupt flag. | ||
| 9256 | */ | ||
| 9257 | #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) | ||
| 9258 | #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) | ||
| 9259 | #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) | ||
| 9260 | /*! SCLTIMEOUT - SCL time-out Interrupt flag. | ||
| 9261 | */ | ||
| 9262 | #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) | ||
| 9263 | /*! @} */ | ||
| 9264 | |||
| 9265 | /*! @name MSTCTL - Master control register. */ | ||
| 9266 | /*! @{ */ | ||
| 9267 | #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) | ||
| 9268 | #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) | ||
| 9269 | /*! MSTCONTINUE - Master Continue. This bit is write-only. | ||
| 9270 | * 0b0..No effect. | ||
| 9271 | * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing | ||
| 9272 | * transmit data, reading received data, or any other housekeeping related to the next bus operation. | ||
| 9273 | */ | ||
| 9274 | #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) | ||
| 9275 | #define I2C_MSTCTL_MSTSTART_MASK (0x2U) | ||
| 9276 | #define I2C_MSTCTL_MSTSTART_SHIFT (1U) | ||
| 9277 | /*! MSTSTART - Master Start control. This bit is write-only. | ||
| 9278 | * 0b0..No effect. | ||
| 9279 | * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. | ||
| 9280 | */ | ||
| 9281 | #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) | ||
| 9282 | #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) | ||
| 9283 | #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) | ||
| 9284 | /*! MSTSTOP - Master Stop control. This bit is write-only. | ||
| 9285 | * 0b0..No effect. | ||
| 9286 | * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave | ||
| 9287 | * if the master is receiving data from the slave (Master Receiver mode). | ||
| 9288 | */ | ||
| 9289 | #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) | ||
| 9290 | #define I2C_MSTCTL_MSTDMA_MASK (0x8U) | ||
| 9291 | #define I2C_MSTCTL_MSTDMA_SHIFT (3U) | ||
| 9292 | /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type | ||
| 9293 | * operations such as Start, address, Stop, and address match must always be done with software, | ||
| 9294 | * typically via an interrupt. Address acknowledgement must also be done by software except when | ||
| 9295 | * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by | ||
| 9296 | * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA | ||
| 9297 | * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is | ||
| 9298 | * read/write. | ||
| 9299 | * 0b0..Disable. No DMA requests are generated for master operation. | ||
| 9300 | * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating | ||
| 9301 | * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. | ||
| 9302 | */ | ||
| 9303 | #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) | ||
| 9304 | /*! @} */ | ||
| 9305 | |||
| 9306 | /*! @name MSTTIME - Master timing configuration. */ | ||
| 9307 | /*! @{ */ | ||
| 9308 | #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) | ||
| 9309 | #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) | ||
| 9310 | /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this | ||
| 9311 | * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This | ||
| 9312 | * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters | ||
| 9313 | * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. | ||
| 9314 | * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. | ||
| 9315 | * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. | ||
| 9316 | * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. | ||
| 9317 | * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. | ||
| 9318 | * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. | ||
| 9319 | * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. | ||
| 9320 | * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. | ||
| 9321 | * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. | ||
| 9322 | */ | ||
| 9323 | #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) | ||
| 9324 | #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) | ||
| 9325 | #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) | ||
| 9326 | /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this | ||
| 9327 | * master on SCL. Other masters in a multi-master system could shorten this time. This | ||
| 9328 | * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters | ||
| 9329 | * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. | ||
| 9330 | * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. | ||
| 9331 | * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . | ||
| 9332 | * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. | ||
| 9333 | * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. | ||
| 9334 | * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. | ||
| 9335 | * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. | ||
| 9336 | * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. | ||
| 9337 | * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. | ||
| 9338 | */ | ||
| 9339 | #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) | ||
| 9340 | /*! @} */ | ||
| 9341 | |||
| 9342 | /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ | ||
| 9343 | /*! @{ */ | ||
| 9344 | #define I2C_MSTDAT_DATA_MASK (0xFFU) | ||
| 9345 | #define I2C_MSTDAT_DATA_SHIFT (0U) | ||
| 9346 | /*! DATA - Master function data register. Read: read the most recently received data for the Master | ||
| 9347 | * function. Write: transmit data using the Master function. | ||
| 9348 | */ | ||
| 9349 | #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) | ||
| 9350 | /*! @} */ | ||
| 9351 | |||
| 9352 | /*! @name SLVCTL - Slave control register. */ | ||
| 9353 | /*! @{ */ | ||
| 9354 | #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) | ||
| 9355 | #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) | ||
| 9356 | /*! SLVCONTINUE - Slave Continue. | ||
| 9357 | * 0b0..No effect. | ||
| 9358 | * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag | ||
| 9359 | * in the STAT register. This must be done after writing transmit data, reading received data, or any other | ||
| 9360 | * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE | ||
| 9361 | * should not be set unless SLVPENDING = 1. | ||
| 9362 | */ | ||
| 9363 | #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) | ||
| 9364 | #define I2C_SLVCTL_SLVNACK_MASK (0x2U) | ||
| 9365 | #define I2C_SLVCTL_SLVNACK_SHIFT (1U) | ||
| 9366 | /*! SLVNACK - Slave NACK. | ||
| 9367 | * 0b0..No effect. | ||
| 9368 | * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). | ||
| 9369 | */ | ||
| 9370 | #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) | ||
| 9371 | #define I2C_SLVCTL_SLVDMA_MASK (0x8U) | ||
| 9372 | #define I2C_SLVCTL_SLVDMA_SHIFT (3U) | ||
| 9373 | /*! SLVDMA - Slave DMA enable. | ||
| 9374 | * 0b0..Disabled. No DMA requests are issued for Slave mode operation. | ||
| 9375 | * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. | ||
| 9376 | */ | ||
| 9377 | #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) | ||
| 9378 | #define I2C_SLVCTL_AUTOACK_MASK (0x100U) | ||
| 9379 | #define I2C_SLVCTL_AUTOACK_SHIFT (8U) | ||
| 9380 | /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches | ||
| 9381 | * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA | ||
| 9382 | * to allow processing of the data without intervention. If this bit is clear and a header | ||
| 9383 | * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or | ||
| 9384 | * interrupt. | ||
| 9385 | * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching | ||
| 9386 | * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). | ||
| 9387 | * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, | ||
| 9388 | * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does | ||
| 9389 | * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK | ||
| 9390 | * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. | ||
| 9391 | */ | ||
| 9392 | #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) | ||
| 9393 | #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) | ||
| 9394 | #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) | ||
| 9395 | /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write | ||
| 9396 | * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to | ||
| 9397 | * match the transfer direction, the direction needs to be specified. This bit allows a direction to | ||
| 9398 | * be chosen for the next operation. | ||
| 9399 | * 0b0..The expected next operation in Automatic Mode is an I2C write. | ||
| 9400 | * 0b1..The expected next operation in Automatic Mode is an I2C read. | ||
| 9401 | */ | ||
| 9402 | #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) | ||
| 9403 | /*! @} */ | ||
| 9404 | |||
| 9405 | /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ | ||
| 9406 | /*! @{ */ | ||
| 9407 | #define I2C_SLVDAT_DATA_MASK (0xFFU) | ||
| 9408 | #define I2C_SLVDAT_DATA_SHIFT (0U) | ||
| 9409 | /*! DATA - Slave function data register. Read: read the most recently received data for the Slave | ||
| 9410 | * function. Write: transmit data using the Slave function. | ||
| 9411 | */ | ||
| 9412 | #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) | ||
| 9413 | /*! @} */ | ||
| 9414 | |||
| 9415 | /*! @name SLVADR - Slave address register. */ | ||
| 9416 | /*! @{ */ | ||
| 9417 | #define I2C_SLVADR_SADISABLE_MASK (0x1U) | ||
| 9418 | #define I2C_SLVADR_SADISABLE_SHIFT (0U) | ||
| 9419 | /*! SADISABLE - Slave Address n Disable. | ||
| 9420 | * 0b0..Enabled. Slave Address n is enabled. | ||
| 9421 | * 0b1..Ignored Slave Address n is ignored. | ||
| 9422 | */ | ||
| 9423 | #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) | ||
| 9424 | #define I2C_SLVADR_SLVADR_MASK (0xFEU) | ||
| 9425 | #define I2C_SLVADR_SLVADR_SHIFT (1U) | ||
| 9426 | /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. | ||
| 9427 | */ | ||
| 9428 | #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) | ||
| 9429 | #define I2C_SLVADR_AUTONACK_MASK (0x8000U) | ||
| 9430 | #define I2C_SLVADR_AUTONACK_SHIFT (15U) | ||
| 9431 | /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows | ||
| 9432 | * software to ignore I2C traffic while handling previous I2C data or other operations. | ||
| 9433 | * 0b0..Normal operation, matching I2C addresses are not ignored. | ||
| 9434 | * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches | ||
| 9435 | * SLVADRn, and AUTOMATCHREAD matches the direction. | ||
| 9436 | */ | ||
| 9437 | #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) | ||
| 9438 | /*! @} */ | ||
| 9439 | |||
| 9440 | /* The count of I2C_SLVADR */ | ||
| 9441 | #define I2C_SLVADR_COUNT (4U) | ||
| 9442 | |||
| 9443 | /*! @name SLVQUAL0 - Slave Qualification for address 0. */ | ||
| 9444 | /*! @{ */ | ||
| 9445 | #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) | ||
| 9446 | #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) | ||
| 9447 | /*! QUALMODE0 - Qualify mode for slave address 0. | ||
| 9448 | * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. | ||
| 9449 | * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. | ||
| 9450 | */ | ||
| 9451 | #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) | ||
| 9452 | #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) | ||
| 9453 | #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) | ||
| 9454 | /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to | ||
| 9455 | * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is | ||
| 9456 | * set to 1 will cause an automatic match of the corresponding bit of the received address when it | ||
| 9457 | * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for | ||
| 9458 | * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 | ||
| 9459 | * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). | ||
| 9460 | */ | ||
| 9461 | #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) | ||
| 9462 | /*! @} */ | ||
| 9463 | |||
| 9464 | /*! @name MONRXDAT - Monitor receiver data register. */ | ||
| 9465 | /*! @{ */ | ||
| 9466 | #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) | ||
| 9467 | #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) | ||
| 9468 | /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. | ||
| 9469 | */ | ||
| 9470 | #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) | ||
| 9471 | #define I2C_MONRXDAT_MONSTART_MASK (0x100U) | ||
| 9472 | #define I2C_MONRXDAT_MONSTART_SHIFT (8U) | ||
| 9473 | /*! MONSTART - Monitor Received Start. | ||
| 9474 | * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. | ||
| 9475 | * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. | ||
| 9476 | */ | ||
| 9477 | #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) | ||
| 9478 | #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) | ||
| 9479 | #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) | ||
| 9480 | /*! MONRESTART - Monitor Received Repeated Start. | ||
| 9481 | * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. | ||
| 9482 | * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. | ||
| 9483 | */ | ||
| 9484 | #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) | ||
| 9485 | #define I2C_MONRXDAT_MONNACK_MASK (0x400U) | ||
| 9486 | #define I2C_MONRXDAT_MONNACK_SHIFT (10U) | ||
| 9487 | /*! MONNACK - Monitor Received NACK. | ||
| 9488 | * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. | ||
| 9489 | * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. | ||
| 9490 | */ | ||
| 9491 | #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) | ||
| 9492 | /*! @} */ | ||
| 9493 | |||
| 9494 | /*! @name ID - Peripheral identification register. */ | ||
| 9495 | /*! @{ */ | ||
| 9496 | #define I2C_ID_APERTURE_MASK (0xFFU) | ||
| 9497 | #define I2C_ID_APERTURE_SHIFT (0U) | ||
| 9498 | /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. | ||
| 9499 | */ | ||
| 9500 | #define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) | ||
| 9501 | #define I2C_ID_MINOR_REV_MASK (0xF00U) | ||
| 9502 | #define I2C_ID_MINOR_REV_SHIFT (8U) | ||
| 9503 | /*! MINOR_REV - Minor revision of module implementation. | ||
| 9504 | */ | ||
| 9505 | #define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) | ||
| 9506 | #define I2C_ID_MAJOR_REV_MASK (0xF000U) | ||
| 9507 | #define I2C_ID_MAJOR_REV_SHIFT (12U) | ||
| 9508 | /*! MAJOR_REV - Major revision of module implementation. | ||
| 9509 | */ | ||
| 9510 | #define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) | ||
| 9511 | #define I2C_ID_ID_MASK (0xFFFF0000U) | ||
| 9512 | #define I2C_ID_ID_SHIFT (16U) | ||
| 9513 | /*! ID - Module identifier for the selected function. | ||
| 9514 | */ | ||
| 9515 | #define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) | ||
| 9516 | /*! @} */ | ||
| 9517 | |||
| 9518 | |||
| 9519 | /*! | ||
| 9520 | * @} | ||
| 9521 | */ /* end of group I2C_Register_Masks */ | ||
| 9522 | |||
| 9523 | |||
| 9524 | /* I2C - Peripheral instance base addresses */ | ||
| 9525 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 9526 | /** Peripheral I2C0 base address */ | ||
| 9527 | #define I2C0_BASE (0x50086000u) | ||
| 9528 | /** Peripheral I2C0 base address */ | ||
| 9529 | #define I2C0_BASE_NS (0x40086000u) | ||
| 9530 | /** Peripheral I2C0 base pointer */ | ||
| 9531 | #define I2C0 ((I2C_Type *)I2C0_BASE) | ||
| 9532 | /** Peripheral I2C0 base pointer */ | ||
| 9533 | #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) | ||
| 9534 | /** Peripheral I2C1 base address */ | ||
| 9535 | #define I2C1_BASE (0x50087000u) | ||
| 9536 | /** Peripheral I2C1 base address */ | ||
| 9537 | #define I2C1_BASE_NS (0x40087000u) | ||
| 9538 | /** Peripheral I2C1 base pointer */ | ||
| 9539 | #define I2C1 ((I2C_Type *)I2C1_BASE) | ||
| 9540 | /** Peripheral I2C1 base pointer */ | ||
| 9541 | #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) | ||
| 9542 | /** Peripheral I2C2 base address */ | ||
| 9543 | #define I2C2_BASE (0x50088000u) | ||
| 9544 | /** Peripheral I2C2 base address */ | ||
| 9545 | #define I2C2_BASE_NS (0x40088000u) | ||
| 9546 | /** Peripheral I2C2 base pointer */ | ||
| 9547 | #define I2C2 ((I2C_Type *)I2C2_BASE) | ||
| 9548 | /** Peripheral I2C2 base pointer */ | ||
| 9549 | #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) | ||
| 9550 | /** Peripheral I2C3 base address */ | ||
| 9551 | #define I2C3_BASE (0x50089000u) | ||
| 9552 | /** Peripheral I2C3 base address */ | ||
| 9553 | #define I2C3_BASE_NS (0x40089000u) | ||
| 9554 | /** Peripheral I2C3 base pointer */ | ||
| 9555 | #define I2C3 ((I2C_Type *)I2C3_BASE) | ||
| 9556 | /** Peripheral I2C3 base pointer */ | ||
| 9557 | #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) | ||
| 9558 | /** Peripheral I2C4 base address */ | ||
| 9559 | #define I2C4_BASE (0x5008A000u) | ||
| 9560 | /** Peripheral I2C4 base address */ | ||
| 9561 | #define I2C4_BASE_NS (0x4008A000u) | ||
| 9562 | /** Peripheral I2C4 base pointer */ | ||
| 9563 | #define I2C4 ((I2C_Type *)I2C4_BASE) | ||
| 9564 | /** Peripheral I2C4 base pointer */ | ||
| 9565 | #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) | ||
| 9566 | /** Peripheral I2C5 base address */ | ||
| 9567 | #define I2C5_BASE (0x50096000u) | ||
| 9568 | /** Peripheral I2C5 base address */ | ||
| 9569 | #define I2C5_BASE_NS (0x40096000u) | ||
| 9570 | /** Peripheral I2C5 base pointer */ | ||
| 9571 | #define I2C5 ((I2C_Type *)I2C5_BASE) | ||
| 9572 | /** Peripheral I2C5 base pointer */ | ||
| 9573 | #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) | ||
| 9574 | /** Peripheral I2C6 base address */ | ||
| 9575 | #define I2C6_BASE (0x50097000u) | ||
| 9576 | /** Peripheral I2C6 base address */ | ||
| 9577 | #define I2C6_BASE_NS (0x40097000u) | ||
| 9578 | /** Peripheral I2C6 base pointer */ | ||
| 9579 | #define I2C6 ((I2C_Type *)I2C6_BASE) | ||
| 9580 | /** Peripheral I2C6 base pointer */ | ||
| 9581 | #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) | ||
| 9582 | /** Peripheral I2C7 base address */ | ||
| 9583 | #define I2C7_BASE (0x50098000u) | ||
| 9584 | /** Peripheral I2C7 base address */ | ||
| 9585 | #define I2C7_BASE_NS (0x40098000u) | ||
| 9586 | /** Peripheral I2C7 base pointer */ | ||
| 9587 | #define I2C7 ((I2C_Type *)I2C7_BASE) | ||
| 9588 | /** Peripheral I2C7 base pointer */ | ||
| 9589 | #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) | ||
| 9590 | /** Array initializer of I2C peripheral base addresses */ | ||
| 9591 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } | ||
| 9592 | /** Array initializer of I2C peripheral base pointers */ | ||
| 9593 | #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } | ||
| 9594 | /** Array initializer of I2C peripheral base addresses */ | ||
| 9595 | #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } | ||
| 9596 | /** Array initializer of I2C peripheral base pointers */ | ||
| 9597 | #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } | ||
| 9598 | #else | ||
| 9599 | /** Peripheral I2C0 base address */ | ||
| 9600 | #define I2C0_BASE (0x40086000u) | ||
| 9601 | /** Peripheral I2C0 base pointer */ | ||
| 9602 | #define I2C0 ((I2C_Type *)I2C0_BASE) | ||
| 9603 | /** Peripheral I2C1 base address */ | ||
| 9604 | #define I2C1_BASE (0x40087000u) | ||
| 9605 | /** Peripheral I2C1 base pointer */ | ||
| 9606 | #define I2C1 ((I2C_Type *)I2C1_BASE) | ||
| 9607 | /** Peripheral I2C2 base address */ | ||
| 9608 | #define I2C2_BASE (0x40088000u) | ||
| 9609 | /** Peripheral I2C2 base pointer */ | ||
| 9610 | #define I2C2 ((I2C_Type *)I2C2_BASE) | ||
| 9611 | /** Peripheral I2C3 base address */ | ||
| 9612 | #define I2C3_BASE (0x40089000u) | ||
| 9613 | /** Peripheral I2C3 base pointer */ | ||
| 9614 | #define I2C3 ((I2C_Type *)I2C3_BASE) | ||
| 9615 | /** Peripheral I2C4 base address */ | ||
| 9616 | #define I2C4_BASE (0x4008A000u) | ||
| 9617 | /** Peripheral I2C4 base pointer */ | ||
| 9618 | #define I2C4 ((I2C_Type *)I2C4_BASE) | ||
| 9619 | /** Peripheral I2C5 base address */ | ||
| 9620 | #define I2C5_BASE (0x40096000u) | ||
| 9621 | /** Peripheral I2C5 base pointer */ | ||
| 9622 | #define I2C5 ((I2C_Type *)I2C5_BASE) | ||
| 9623 | /** Peripheral I2C6 base address */ | ||
| 9624 | #define I2C6_BASE (0x40097000u) | ||
| 9625 | /** Peripheral I2C6 base pointer */ | ||
| 9626 | #define I2C6 ((I2C_Type *)I2C6_BASE) | ||
| 9627 | /** Peripheral I2C7 base address */ | ||
| 9628 | #define I2C7_BASE (0x40098000u) | ||
| 9629 | /** Peripheral I2C7 base pointer */ | ||
| 9630 | #define I2C7 ((I2C_Type *)I2C7_BASE) | ||
| 9631 | /** Array initializer of I2C peripheral base addresses */ | ||
| 9632 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } | ||
| 9633 | /** Array initializer of I2C peripheral base pointers */ | ||
| 9634 | #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } | ||
| 9635 | #endif | ||
| 9636 | /** Interrupt vectors for the I2C peripheral type */ | ||
| 9637 | #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } | ||
| 9638 | |||
| 9639 | /*! | ||
| 9640 | * @} | ||
| 9641 | */ /* end of group I2C_Peripheral_Access_Layer */ | ||
| 9642 | |||
| 9643 | |||
| 9644 | /* ---------------------------------------------------------------------------- | ||
| 9645 | -- I2S Peripheral Access Layer | ||
| 9646 | ---------------------------------------------------------------------------- */ | ||
| 9647 | |||
| 9648 | /*! | ||
| 9649 | * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer | ||
| 9650 | * @{ | ||
| 9651 | */ | ||
| 9652 | |||
| 9653 | /** I2S - Register Layout Typedef */ | ||
| 9654 | typedef struct { | ||
| 9655 | uint8_t RESERVED_0[3072]; | ||
| 9656 | __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ | ||
| 9657 | __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ | ||
| 9658 | __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ | ||
| 9659 | uint8_t RESERVED_1[16]; | ||
| 9660 | __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ | ||
| 9661 | uint8_t RESERVED_2[480]; | ||
| 9662 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ | ||
| 9663 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ | ||
| 9664 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ | ||
| 9665 | uint8_t RESERVED_3[4]; | ||
| 9666 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ | ||
| 9667 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ | ||
| 9668 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ | ||
| 9669 | uint8_t RESERVED_4[4]; | ||
| 9670 | __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ | ||
| 9671 | __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ | ||
| 9672 | uint8_t RESERVED_5[8]; | ||
| 9673 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ | ||
| 9674 | __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ | ||
| 9675 | uint8_t RESERVED_6[8]; | ||
| 9676 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ | ||
| 9677 | __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ | ||
| 9678 | uint8_t RESERVED_7[436]; | ||
| 9679 | __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ | ||
| 9680 | } I2S_Type; | ||
| 9681 | |||
| 9682 | /* ---------------------------------------------------------------------------- | ||
| 9683 | -- I2S Register Masks | ||
| 9684 | ---------------------------------------------------------------------------- */ | ||
| 9685 | |||
| 9686 | /*! | ||
| 9687 | * @addtogroup I2S_Register_Masks I2S Register Masks | ||
| 9688 | * @{ | ||
| 9689 | */ | ||
| 9690 | |||
| 9691 | /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ | ||
| 9692 | /*! @{ */ | ||
| 9693 | #define I2S_CFG1_MAINENABLE_MASK (0x1U) | ||
| 9694 | #define I2S_CFG1_MAINENABLE_SHIFT (0U) | ||
| 9695 | /*! MAINENABLE - Main enable for I 2S function in this Flexcomm | ||
| 9696 | * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags | ||
| 9697 | * are reset. No other channel pairs can be enabled. | ||
| 9698 | * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. | ||
| 9699 | */ | ||
| 9700 | #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) | ||
| 9701 | #define I2S_CFG1_DATAPAUSE_MASK (0x2U) | ||
| 9702 | #define I2S_CFG1_DATAPAUSE_SHIFT (1U) | ||
| 9703 | /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer | ||
| 9704 | * and the FIFO. This could be done in order to change streams, or while restarting after a data | ||
| 9705 | * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is | ||
| 9706 | * in the process of being sent or received. Once a data pause has been requested, the interface | ||
| 9707 | * may need to complete sending data that was in progress before interrupting the flow of data. | ||
| 9708 | * Software must check that the pause is actually in effect before taking action. This is done by | ||
| 9709 | * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer | ||
| 9710 | * will resume at the beginning of the next frame. | ||
| 9711 | * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. | ||
| 9712 | * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. | ||
| 9713 | */ | ||
| 9714 | #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) | ||
| 9715 | #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) | ||
| 9716 | #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) | ||
| 9717 | /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field | ||
| 9718 | * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this | ||
| 9719 | * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs | ||
| 9720 | * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. | ||
| 9721 | * 0b00..1 I2S channel pairs in this flexcomm | ||
| 9722 | * 0b01..2 I2S channel pairs in this flexcomm | ||
| 9723 | * 0b10..3 I2S channel pairs in this flexcomm | ||
| 9724 | * 0b11..4 I2S channel pairs in this flexcomm | ||
| 9725 | */ | ||
| 9726 | #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) | ||
| 9727 | #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) | ||
| 9728 | #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) | ||
| 9729 | /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. | ||
| 9730 | * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. | ||
| 9731 | * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of | ||
| 9732 | * SCK, when divided from the Flexcomm function clock. | ||
| 9733 | * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. | ||
| 9734 | * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. | ||
| 9735 | */ | ||
| 9736 | #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) | ||
| 9737 | #define I2S_CFG1_MODE_MASK (0xC0U) | ||
| 9738 | #define I2S_CFG1_MODE_SHIFT (6U) | ||
| 9739 | /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all | ||
| 9740 | * supported cases. See Formats and modes for examples. | ||
| 9741 | * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece | ||
| 9742 | * of left channel data occurring during the first phase, and one pieces of right channel data occurring | ||
| 9743 | * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the | ||
| 9744 | * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If | ||
| 9745 | * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. | ||
| 9746 | * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. | ||
| 9747 | * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. | ||
| 9748 | * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. | ||
| 9749 | */ | ||
| 9750 | #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) | ||
| 9751 | #define I2S_CFG1_RIGHTLOW_MASK (0x100U) | ||
| 9752 | #define I2S_CFG1_RIGHTLOW_SHIFT (8U) | ||
| 9753 | /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left | ||
| 9754 | * and right channel data as it is transferred to or from the FIFO. This bit is not used if the | ||
| 9755 | * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 | ||
| 9756 | * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION | ||
| 9757 | * can still place that data in the frame where right channel data is normally located. if all | ||
| 9758 | * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. | ||
| 9759 | * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO | ||
| 9760 | * bits 31:16 are used for the right channel. | ||
| 9761 | * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO | ||
| 9762 | * bits 15:0 are used for the right channel. | ||
| 9763 | */ | ||
| 9764 | #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) | ||
| 9765 | #define I2S_CFG1_LEFTJUST_MASK (0x200U) | ||
| 9766 | #define I2S_CFG1_LEFTJUST_SHIFT (9U) | ||
| 9767 | /*! LEFTJUST - Left Justify data. | ||
| 9768 | * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting | ||
| 9769 | * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data | ||
| 9770 | * in the stream on the data bus. | ||
| 9771 | * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting | ||
| 9772 | * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would | ||
| 9773 | * correspond to left justified data in the stream on the data bus. | ||
| 9774 | */ | ||
| 9775 | #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) | ||
| 9776 | #define I2S_CFG1_ONECHANNEL_MASK (0x400U) | ||
| 9777 | #define I2S_CFG1_ONECHANNEL_SHIFT (10U) | ||
| 9778 | /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit | ||
| 9779 | * applies only to the first I2S channel pair. Other channel pairs may select this mode | ||
| 9780 | * independently in their separate CFG1 registers. | ||
| 9781 | * 0b0..I2S data for this channel pair is treated as left and right channels. | ||
| 9782 | * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this | ||
| 9783 | * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a | ||
| 9784 | * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel | ||
| 9785 | * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side | ||
| 9786 | * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data | ||
| 9787 | * for the single channel of data is placed at the clock defined by POSITION. | ||
| 9788 | */ | ||
| 9789 | #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) | ||
| 9790 | #define I2S_CFG1_SCK_POL_MASK (0x1000U) | ||
| 9791 | #define I2S_CFG1_SCK_POL_SHIFT (12U) | ||
| 9792 | /*! SCK_POL - SCK polarity. | ||
| 9793 | * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). | ||
| 9794 | * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. | ||
| 9795 | */ | ||
| 9796 | #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) | ||
| 9797 | #define I2S_CFG1_WS_POL_MASK (0x2000U) | ||
| 9798 | #define I2S_CFG1_WS_POL_SHIFT (13U) | ||
| 9799 | /*! WS_POL - WS polarity. | ||
| 9800 | * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). | ||
| 9801 | * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). | ||
| 9802 | */ | ||
| 9803 | #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) | ||
| 9804 | #define I2S_CFG1_DATALEN_MASK (0x1F0000U) | ||
| 9805 | #define I2S_CFG1_DATALEN_SHIFT (16U) | ||
| 9806 | /*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or | ||
| 9807 | * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received | ||
| 9808 | * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the | ||
| 9809 | * I2S: Determines the size of data transfers between the FIFO and the I2S | ||
| 9810 | * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of | ||
| 9811 | * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse | ||
| 9812 | * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to | ||
| 9813 | * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = | ||
| 9814 | * data is 32 bits in length | ||
| 9815 | */ | ||
| 9816 | #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) | ||
| 9817 | /*! @} */ | ||
| 9818 | |||
| 9819 | /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ | ||
| 9820 | /*! @{ */ | ||
| 9821 | #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) | ||
| 9822 | #define I2S_CFG2_FRAMELEN_SHIFT (0U) | ||
| 9823 | /*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the | ||
| 9824 | * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported | ||
| 9825 | * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is | ||
| 9826 | * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in | ||
| 9827 | * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger | ||
| 9828 | * than DATALEN in order for the WS pulse to be generated correctly. | ||
| 9829 | */ | ||
| 9830 | #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) | ||
| 9831 | #define I2S_CFG2_POSITION_MASK (0x1FF0000U) | ||
| 9832 | #define I2S_CFG2_POSITION_SHIFT (16U) | ||
| 9833 | /*! POSITION - Data Position. Defines the location within the frame of the data for this channel | ||
| 9834 | * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION | ||
| 9835 | * defines the location of data in both the left phase and right phase, starting one clock after | ||
| 9836 | * the WS edge. In other modes, POSITION defines the location of data within the entire frame. | ||
| 9837 | * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The | ||
| 9838 | * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels | ||
| 9839 | * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit | ||
| 9840 | * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS | ||
| 9841 | * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. | ||
| 9842 | */ | ||
| 9843 | #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) | ||
| 9844 | /*! @} */ | ||
| 9845 | |||
| 9846 | /*! @name STAT - Status register for the primary channel pair. */ | ||
| 9847 | /*! @{ */ | ||
| 9848 | #define I2S_STAT_BUSY_MASK (0x1U) | ||
| 9849 | #define I2S_STAT_BUSY_SHIFT (0U) | ||
| 9850 | /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. | ||
| 9851 | * 0b0..The transmitter/receiver for channel pair is currently idle. | ||
| 9852 | * 0b1..The transmitter/receiver for channel pair is currently processing data. | ||
| 9853 | */ | ||
| 9854 | #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) | ||
| 9855 | #define I2S_STAT_SLVFRMERR_MASK (0x2U) | ||
| 9856 | #define I2S_STAT_SLVFRMERR_SHIFT (1U) | ||
| 9857 | /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as | ||
| 9858 | * a slave. An error indicates that the incoming WS signal did not transition as expected due to | ||
| 9859 | * a mismatch between FRAMELEN and the actual incoming I2S stream. | ||
| 9860 | * 0b0..No error has been recorded. | ||
| 9861 | * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. | ||
| 9862 | */ | ||
| 9863 | #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) | ||
| 9864 | #define I2S_STAT_LR_MASK (0x4U) | ||
| 9865 | #define I2S_STAT_LR_SHIFT (2U) | ||
| 9866 | /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to | ||
| 9867 | * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data | ||
| 9868 | * being processed for the currently busy channel pair. | ||
| 9869 | * 0b0..Left channel. | ||
| 9870 | * 0b1..Right channel. | ||
| 9871 | */ | ||
| 9872 | #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) | ||
| 9873 | #define I2S_STAT_DATAPAUSED_MASK (0x8U) | ||
| 9874 | #define I2S_STAT_DATAPAUSED_SHIFT (3U) | ||
| 9875 | /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels | ||
| 9876 | * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for | ||
| 9877 | * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. | ||
| 9878 | * 0b1..A data pause has been requested and is now in force. | ||
| 9879 | */ | ||
| 9880 | #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) | ||
| 9881 | /*! @} */ | ||
| 9882 | |||
| 9883 | /*! @name DIV - Clock divider, used by all channel pairs. */ | ||
| 9884 | /*! @{ */ | ||
| 9885 | #define I2S_DIV_DIV_MASK (0xFFFU) | ||
| 9886 | #define I2S_DIV_DIV_SHIFT (0U) | ||
| 9887 | /*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The | ||
| 9888 | * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. | ||
| 9889 | * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is | ||
| 9890 | * divided by 4,096. | ||
| 9891 | */ | ||
| 9892 | #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) | ||
| 9893 | /*! @} */ | ||
| 9894 | |||
| 9895 | /*! @name FIFOCFG - FIFO configuration and enable register. */ | ||
| 9896 | /*! @{ */ | ||
| 9897 | #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) | ||
| 9898 | #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) | ||
| 9899 | /*! ENABLETX - Enable the transmit FIFO. | ||
| 9900 | * 0b0..The transmit FIFO is not enabled. | ||
| 9901 | * 0b1..The transmit FIFO is enabled. | ||
| 9902 | */ | ||
| 9903 | #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) | ||
| 9904 | #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) | ||
| 9905 | #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) | ||
| 9906 | /*! ENABLERX - Enable the receive FIFO. | ||
| 9907 | * 0b0..The receive FIFO is not enabled. | ||
| 9908 | * 0b1..The receive FIFO is enabled. | ||
| 9909 | */ | ||
| 9910 | #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) | ||
| 9911 | #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) | ||
| 9912 | #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) | ||
| 9913 | /*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX | ||
| 9914 | * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is | ||
| 9915 | * cleared, new data is provided, and the I2S is un-paused. | ||
| 9916 | * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 | ||
| 9917 | * bits or less, or when MONO = 1 for this channel pair. | ||
| 9918 | * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. | ||
| 9919 | */ | ||
| 9920 | #define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) | ||
| 9921 | #define I2S_FIFOCFG_PACK48_MASK (0x8U) | ||
| 9922 | #define I2S_FIFOCFG_PACK48_SHIFT (3U) | ||
| 9923 | /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. | ||
| 9924 | * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. | ||
| 9925 | * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. | ||
| 9926 | */ | ||
| 9927 | #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) | ||
| 9928 | #define I2S_FIFOCFG_SIZE_MASK (0x30U) | ||
| 9929 | #define I2S_FIFOCFG_SIZE_SHIFT (4U) | ||
| 9930 | /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 | ||
| 9931 | * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. | ||
| 9932 | */ | ||
| 9933 | #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) | ||
| 9934 | #define I2S_FIFOCFG_DMATX_MASK (0x1000U) | ||
| 9935 | #define I2S_FIFOCFG_DMATX_SHIFT (12U) | ||
| 9936 | /*! DMATX - DMA configuration for transmit. | ||
| 9937 | * 0b0..DMA is not used for the transmit function. | ||
| 9938 | * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 9939 | */ | ||
| 9940 | #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) | ||
| 9941 | #define I2S_FIFOCFG_DMARX_MASK (0x2000U) | ||
| 9942 | #define I2S_FIFOCFG_DMARX_SHIFT (13U) | ||
| 9943 | /*! DMARX - DMA configuration for receive. | ||
| 9944 | * 0b0..DMA is not used for the receive function. | ||
| 9945 | * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 9946 | */ | ||
| 9947 | #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) | ||
| 9948 | #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) | ||
| 9949 | #define I2S_FIFOCFG_WAKETX_SHIFT (14U) | ||
| 9950 | /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power | ||
| 9951 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 9952 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 9953 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 9954 | * Wake-up control register. | ||
| 9955 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 9956 | * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in | ||
| 9957 | * FIFOTRIG, even when the TXLVL interrupt is not enabled. | ||
| 9958 | */ | ||
| 9959 | #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) | ||
| 9960 | #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) | ||
| 9961 | #define I2S_FIFOCFG_WAKERX_SHIFT (15U) | ||
| 9962 | /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power | ||
| 9963 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 9964 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 9965 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 9966 | * Wake-up control register. | ||
| 9967 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 9968 | * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in | ||
| 9969 | * FIFOTRIG, even when the RXLVL interrupt is not enabled. | ||
| 9970 | */ | ||
| 9971 | #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) | ||
| 9972 | #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) | ||
| 9973 | #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) | ||
| 9974 | /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. | ||
| 9975 | */ | ||
| 9976 | #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) | ||
| 9977 | #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) | ||
| 9978 | #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) | ||
| 9979 | /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. | ||
| 9980 | */ | ||
| 9981 | #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) | ||
| 9982 | /*! @} */ | ||
| 9983 | |||
| 9984 | /*! @name FIFOSTAT - FIFO status register. */ | ||
| 9985 | /*! @{ */ | ||
| 9986 | #define I2S_FIFOSTAT_TXERR_MASK (0x1U) | ||
| 9987 | #define I2S_FIFOSTAT_TXERR_SHIFT (0U) | ||
| 9988 | /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow | ||
| 9989 | * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is | ||
| 9990 | * needed. Cleared by writing a 1 to this bit. | ||
| 9991 | */ | ||
| 9992 | #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) | ||
| 9993 | #define I2S_FIFOSTAT_RXERR_MASK (0x2U) | ||
| 9994 | #define I2S_FIFOSTAT_RXERR_SHIFT (1U) | ||
| 9995 | /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA | ||
| 9996 | * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. | ||
| 9997 | */ | ||
| 9998 | #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) | ||
| 9999 | #define I2S_FIFOSTAT_PERINT_MASK (0x8U) | ||
| 10000 | #define I2S_FIFOSTAT_PERINT_SHIFT (3U) | ||
| 10001 | /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted | ||
| 10002 | * an interrupt. The details can be found by reading the peripheral's STAT register. | ||
| 10003 | */ | ||
| 10004 | #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) | ||
| 10005 | #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) | ||
| 10006 | #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) | ||
| 10007 | /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. | ||
| 10008 | */ | ||
| 10009 | #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) | ||
| 10010 | #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) | ||
| 10011 | #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) | ||
| 10012 | /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be | ||
| 10013 | * written. When 0, the transmit FIFO is full and another write would cause it to overflow. | ||
| 10014 | */ | ||
| 10015 | #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) | ||
| 10016 | #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) | ||
| 10017 | #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) | ||
| 10018 | /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. | ||
| 10019 | */ | ||
| 10020 | #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) | ||
| 10021 | #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) | ||
| 10022 | #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) | ||
| 10023 | /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to | ||
| 10024 | * prevent the peripheral from causing an overflow. | ||
| 10025 | */ | ||
| 10026 | #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) | ||
| 10027 | #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) | ||
| 10028 | #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) | ||
| 10029 | /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY | ||
| 10030 | * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at | ||
| 10031 | * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be | ||
| 10032 | * 0. | ||
| 10033 | */ | ||
| 10034 | #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) | ||
| 10035 | #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) | ||
| 10036 | #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) | ||
| 10037 | /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and | ||
| 10038 | * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the | ||
| 10039 | * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be | ||
| 10040 | * 1. | ||
| 10041 | */ | ||
| 10042 | #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) | ||
| 10043 | /*! @} */ | ||
| 10044 | |||
| 10045 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ | ||
| 10046 | /*! @{ */ | ||
| 10047 | #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) | ||
| 10048 | #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) | ||
| 10049 | /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 10050 | * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. | ||
| 10051 | * 0b0..Transmit FIFO level does not generate a FIFO level trigger. | ||
| 10052 | * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. | ||
| 10053 | */ | ||
| 10054 | #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) | ||
| 10055 | #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) | ||
| 10056 | #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) | ||
| 10057 | /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 10058 | * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. | ||
| 10059 | * 0b0..Receive FIFO level does not generate a FIFO level trigger. | ||
| 10060 | * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. | ||
| 10061 | */ | ||
| 10062 | #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) | ||
| 10063 | #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) | ||
| 10064 | #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) | ||
| 10065 | /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled | ||
| 10066 | * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to | ||
| 10067 | * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO | ||
| 10068 | * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX | ||
| 10069 | * FIFO level decreases to 15 entries (is no longer full). | ||
| 10070 | */ | ||
| 10071 | #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) | ||
| 10072 | #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) | ||
| 10073 | #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) | ||
| 10074 | /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data | ||
| 10075 | * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level | ||
| 10076 | * can wake up the device just enough to perform DMA, then return to the reduced power mode. See | ||
| 10077 | * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no | ||
| 10078 | * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX | ||
| 10079 | * FIFO has received 16 entries (has become full). | ||
| 10080 | */ | ||
| 10081 | #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) | ||
| 10082 | /*! @} */ | ||
| 10083 | |||
| 10084 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ | ||
| 10085 | /*! @{ */ | ||
| 10086 | #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) | ||
| 10087 | #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) | ||
| 10088 | /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. | ||
| 10089 | * 0b0..No interrupt will be generated for a transmit error. | ||
| 10090 | * 0b1..An interrupt will be generated when a transmit error occurs. | ||
| 10091 | */ | ||
| 10092 | #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) | ||
| 10093 | #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) | ||
| 10094 | #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) | ||
| 10095 | /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. | ||
| 10096 | * 0b0..No interrupt will be generated for a receive error. | ||
| 10097 | * 0b1..An interrupt will be generated when a receive error occurs. | ||
| 10098 | */ | ||
| 10099 | #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) | ||
| 10100 | #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) | ||
| 10101 | #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) | ||
| 10102 | /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level | ||
| 10103 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 10104 | * 0b0..No interrupt will be generated based on the TX FIFO level. | ||
| 10105 | * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases | ||
| 10106 | * to the level specified by TXLVL in the FIFOTRIG register. | ||
| 10107 | */ | ||
| 10108 | #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) | ||
| 10109 | #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) | ||
| 10110 | #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) | ||
| 10111 | /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level | ||
| 10112 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 10113 | * 0b0..No interrupt will be generated based on the RX FIFO level. | ||
| 10114 | * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level | ||
| 10115 | * increases to the level specified by RXLVL in the FIFOTRIG register. | ||
| 10116 | */ | ||
| 10117 | #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) | ||
| 10118 | /*! @} */ | ||
| 10119 | |||
| 10120 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ | ||
| 10121 | /*! @{ */ | ||
| 10122 | #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) | ||
| 10123 | #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) | ||
| 10124 | /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 10125 | */ | ||
| 10126 | #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) | ||
| 10127 | #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) | ||
| 10128 | #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) | ||
| 10129 | /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 10130 | */ | ||
| 10131 | #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) | ||
| 10132 | #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) | ||
| 10133 | #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) | ||
| 10134 | /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 10135 | */ | ||
| 10136 | #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) | ||
| 10137 | #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) | ||
| 10138 | #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) | ||
| 10139 | /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 10140 | */ | ||
| 10141 | #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) | ||
| 10142 | /*! @} */ | ||
| 10143 | |||
| 10144 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ | ||
| 10145 | /*! @{ */ | ||
| 10146 | #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) | ||
| 10147 | #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) | ||
| 10148 | /*! TXERR - TX FIFO error. | ||
| 10149 | */ | ||
| 10150 | #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) | ||
| 10151 | #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) | ||
| 10152 | #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) | ||
| 10153 | /*! RXERR - RX FIFO error. | ||
| 10154 | */ | ||
| 10155 | #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) | ||
| 10156 | #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) | ||
| 10157 | #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) | ||
| 10158 | /*! TXLVL - Transmit FIFO level interrupt. | ||
| 10159 | */ | ||
| 10160 | #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) | ||
| 10161 | #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) | ||
| 10162 | #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) | ||
| 10163 | /*! RXLVL - Receive FIFO level interrupt. | ||
| 10164 | */ | ||
| 10165 | #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) | ||
| 10166 | #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) | ||
| 10167 | #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) | ||
| 10168 | /*! PERINT - Peripheral interrupt. | ||
| 10169 | */ | ||
| 10170 | #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) | ||
| 10171 | /*! @} */ | ||
| 10172 | |||
| 10173 | /*! @name FIFOWR - FIFO write data. */ | ||
| 10174 | /*! @{ */ | ||
| 10175 | #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) | ||
| 10176 | #define I2S_FIFOWR_TXDATA_SHIFT (0U) | ||
| 10177 | /*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. | ||
| 10178 | */ | ||
| 10179 | #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) | ||
| 10180 | /*! @} */ | ||
| 10181 | |||
| 10182 | /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ | ||
| 10183 | /*! @{ */ | ||
| 10184 | #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) | ||
| 10185 | #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) | ||
| 10186 | /*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. | ||
| 10187 | */ | ||
| 10188 | #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) | ||
| 10189 | /*! @} */ | ||
| 10190 | |||
| 10191 | /*! @name FIFORD - FIFO read data. */ | ||
| 10192 | /*! @{ */ | ||
| 10193 | #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) | ||
| 10194 | #define I2S_FIFORD_RXDATA_SHIFT (0U) | ||
| 10195 | /*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. | ||
| 10196 | */ | ||
| 10197 | #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) | ||
| 10198 | /*! @} */ | ||
| 10199 | |||
| 10200 | /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ | ||
| 10201 | /*! @{ */ | ||
| 10202 | #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) | ||
| 10203 | #define I2S_FIFORD48H_RXDATA_SHIFT (0U) | ||
| 10204 | /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. | ||
| 10205 | */ | ||
| 10206 | #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) | ||
| 10207 | /*! @} */ | ||
| 10208 | |||
| 10209 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ | ||
| 10210 | /*! @{ */ | ||
| 10211 | #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) | ||
| 10212 | #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) | ||
| 10213 | /*! RXDATA - Received data from the FIFO. | ||
| 10214 | */ | ||
| 10215 | #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) | ||
| 10216 | /*! @} */ | ||
| 10217 | |||
| 10218 | /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ | ||
| 10219 | /*! @{ */ | ||
| 10220 | #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) | ||
| 10221 | #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) | ||
| 10222 | /*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. | ||
| 10223 | */ | ||
| 10224 | #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) | ||
| 10225 | /*! @} */ | ||
| 10226 | |||
| 10227 | /*! @name ID - I2S Module identification */ | ||
| 10228 | /*! @{ */ | ||
| 10229 | #define I2S_ID_APERTURE_MASK (0xFFU) | ||
| 10230 | #define I2S_ID_APERTURE_SHIFT (0U) | ||
| 10231 | /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. | ||
| 10232 | */ | ||
| 10233 | #define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) | ||
| 10234 | #define I2S_ID_MINOR_REV_MASK (0xF00U) | ||
| 10235 | #define I2S_ID_MINOR_REV_SHIFT (8U) | ||
| 10236 | /*! MINOR_REV - Minor revision of module implementation, starting at 0. | ||
| 10237 | */ | ||
| 10238 | #define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) | ||
| 10239 | #define I2S_ID_MAJOR_REV_MASK (0xF000U) | ||
| 10240 | #define I2S_ID_MAJOR_REV_SHIFT (12U) | ||
| 10241 | /*! MAJOR_REV - Major revision of module implementation, starting at 0. | ||
| 10242 | */ | ||
| 10243 | #define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) | ||
| 10244 | #define I2S_ID_ID_MASK (0xFFFF0000U) | ||
| 10245 | #define I2S_ID_ID_SHIFT (16U) | ||
| 10246 | /*! ID - Unique module identifier for this IP block. | ||
| 10247 | */ | ||
| 10248 | #define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) | ||
| 10249 | /*! @} */ | ||
| 10250 | |||
| 10251 | |||
| 10252 | /*! | ||
| 10253 | * @} | ||
| 10254 | */ /* end of group I2S_Register_Masks */ | ||
| 10255 | |||
| 10256 | |||
| 10257 | /* I2S - Peripheral instance base addresses */ | ||
| 10258 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 10259 | /** Peripheral I2S0 base address */ | ||
| 10260 | #define I2S0_BASE (0x50086000u) | ||
| 10261 | /** Peripheral I2S0 base address */ | ||
| 10262 | #define I2S0_BASE_NS (0x40086000u) | ||
| 10263 | /** Peripheral I2S0 base pointer */ | ||
| 10264 | #define I2S0 ((I2S_Type *)I2S0_BASE) | ||
| 10265 | /** Peripheral I2S0 base pointer */ | ||
| 10266 | #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) | ||
| 10267 | /** Peripheral I2S1 base address */ | ||
| 10268 | #define I2S1_BASE (0x50087000u) | ||
| 10269 | /** Peripheral I2S1 base address */ | ||
| 10270 | #define I2S1_BASE_NS (0x40087000u) | ||
| 10271 | /** Peripheral I2S1 base pointer */ | ||
| 10272 | #define I2S1 ((I2S_Type *)I2S1_BASE) | ||
| 10273 | /** Peripheral I2S1 base pointer */ | ||
| 10274 | #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) | ||
| 10275 | /** Peripheral I2S2 base address */ | ||
| 10276 | #define I2S2_BASE (0x50088000u) | ||
| 10277 | /** Peripheral I2S2 base address */ | ||
| 10278 | #define I2S2_BASE_NS (0x40088000u) | ||
| 10279 | /** Peripheral I2S2 base pointer */ | ||
| 10280 | #define I2S2 ((I2S_Type *)I2S2_BASE) | ||
| 10281 | /** Peripheral I2S2 base pointer */ | ||
| 10282 | #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) | ||
| 10283 | /** Peripheral I2S3 base address */ | ||
| 10284 | #define I2S3_BASE (0x50089000u) | ||
| 10285 | /** Peripheral I2S3 base address */ | ||
| 10286 | #define I2S3_BASE_NS (0x40089000u) | ||
| 10287 | /** Peripheral I2S3 base pointer */ | ||
| 10288 | #define I2S3 ((I2S_Type *)I2S3_BASE) | ||
| 10289 | /** Peripheral I2S3 base pointer */ | ||
| 10290 | #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) | ||
| 10291 | /** Peripheral I2S4 base address */ | ||
| 10292 | #define I2S4_BASE (0x5008A000u) | ||
| 10293 | /** Peripheral I2S4 base address */ | ||
| 10294 | #define I2S4_BASE_NS (0x4008A000u) | ||
| 10295 | /** Peripheral I2S4 base pointer */ | ||
| 10296 | #define I2S4 ((I2S_Type *)I2S4_BASE) | ||
| 10297 | /** Peripheral I2S4 base pointer */ | ||
| 10298 | #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) | ||
| 10299 | /** Peripheral I2S5 base address */ | ||
| 10300 | #define I2S5_BASE (0x50096000u) | ||
| 10301 | /** Peripheral I2S5 base address */ | ||
| 10302 | #define I2S5_BASE_NS (0x40096000u) | ||
| 10303 | /** Peripheral I2S5 base pointer */ | ||
| 10304 | #define I2S5 ((I2S_Type *)I2S5_BASE) | ||
| 10305 | /** Peripheral I2S5 base pointer */ | ||
| 10306 | #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) | ||
| 10307 | /** Peripheral I2S6 base address */ | ||
| 10308 | #define I2S6_BASE (0x50097000u) | ||
| 10309 | /** Peripheral I2S6 base address */ | ||
| 10310 | #define I2S6_BASE_NS (0x40097000u) | ||
| 10311 | /** Peripheral I2S6 base pointer */ | ||
| 10312 | #define I2S6 ((I2S_Type *)I2S6_BASE) | ||
| 10313 | /** Peripheral I2S6 base pointer */ | ||
| 10314 | #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) | ||
| 10315 | /** Peripheral I2S7 base address */ | ||
| 10316 | #define I2S7_BASE (0x50098000u) | ||
| 10317 | /** Peripheral I2S7 base address */ | ||
| 10318 | #define I2S7_BASE_NS (0x40098000u) | ||
| 10319 | /** Peripheral I2S7 base pointer */ | ||
| 10320 | #define I2S7 ((I2S_Type *)I2S7_BASE) | ||
| 10321 | /** Peripheral I2S7 base pointer */ | ||
| 10322 | #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) | ||
| 10323 | /** Array initializer of I2S peripheral base addresses */ | ||
| 10324 | #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } | ||
| 10325 | /** Array initializer of I2S peripheral base pointers */ | ||
| 10326 | #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } | ||
| 10327 | /** Array initializer of I2S peripheral base addresses */ | ||
| 10328 | #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } | ||
| 10329 | /** Array initializer of I2S peripheral base pointers */ | ||
| 10330 | #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } | ||
| 10331 | #else | ||
| 10332 | /** Peripheral I2S0 base address */ | ||
| 10333 | #define I2S0_BASE (0x40086000u) | ||
| 10334 | /** Peripheral I2S0 base pointer */ | ||
| 10335 | #define I2S0 ((I2S_Type *)I2S0_BASE) | ||
| 10336 | /** Peripheral I2S1 base address */ | ||
| 10337 | #define I2S1_BASE (0x40087000u) | ||
| 10338 | /** Peripheral I2S1 base pointer */ | ||
| 10339 | #define I2S1 ((I2S_Type *)I2S1_BASE) | ||
| 10340 | /** Peripheral I2S2 base address */ | ||
| 10341 | #define I2S2_BASE (0x40088000u) | ||
| 10342 | /** Peripheral I2S2 base pointer */ | ||
| 10343 | #define I2S2 ((I2S_Type *)I2S2_BASE) | ||
| 10344 | /** Peripheral I2S3 base address */ | ||
| 10345 | #define I2S3_BASE (0x40089000u) | ||
| 10346 | /** Peripheral I2S3 base pointer */ | ||
| 10347 | #define I2S3 ((I2S_Type *)I2S3_BASE) | ||
| 10348 | /** Peripheral I2S4 base address */ | ||
| 10349 | #define I2S4_BASE (0x4008A000u) | ||
| 10350 | /** Peripheral I2S4 base pointer */ | ||
| 10351 | #define I2S4 ((I2S_Type *)I2S4_BASE) | ||
| 10352 | /** Peripheral I2S5 base address */ | ||
| 10353 | #define I2S5_BASE (0x40096000u) | ||
| 10354 | /** Peripheral I2S5 base pointer */ | ||
| 10355 | #define I2S5 ((I2S_Type *)I2S5_BASE) | ||
| 10356 | /** Peripheral I2S6 base address */ | ||
| 10357 | #define I2S6_BASE (0x40097000u) | ||
| 10358 | /** Peripheral I2S6 base pointer */ | ||
| 10359 | #define I2S6 ((I2S_Type *)I2S6_BASE) | ||
| 10360 | /** Peripheral I2S7 base address */ | ||
| 10361 | #define I2S7_BASE (0x40098000u) | ||
| 10362 | /** Peripheral I2S7 base pointer */ | ||
| 10363 | #define I2S7 ((I2S_Type *)I2S7_BASE) | ||
| 10364 | /** Array initializer of I2S peripheral base addresses */ | ||
| 10365 | #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } | ||
| 10366 | /** Array initializer of I2S peripheral base pointers */ | ||
| 10367 | #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } | ||
| 10368 | #endif | ||
| 10369 | /** Interrupt vectors for the I2S peripheral type */ | ||
| 10370 | #define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } | ||
| 10371 | |||
| 10372 | /*! | ||
| 10373 | * @} | ||
| 10374 | */ /* end of group I2S_Peripheral_Access_Layer */ | ||
| 10375 | |||
| 10376 | |||
| 10377 | /* ---------------------------------------------------------------------------- | ||
| 10378 | -- INPUTMUX Peripheral Access Layer | ||
| 10379 | ---------------------------------------------------------------------------- */ | ||
| 10380 | |||
| 10381 | /*! | ||
| 10382 | * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer | ||
| 10383 | * @{ | ||
| 10384 | */ | ||
| 10385 | |||
| 10386 | /** INPUTMUX - Register Layout Typedef */ | ||
| 10387 | typedef struct { | ||
| 10388 | __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ | ||
| 10389 | uint8_t RESERVED_0[4]; | ||
| 10390 | __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ | ||
| 10391 | uint8_t RESERVED_1[16]; | ||
| 10392 | __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ | ||
| 10393 | uint8_t RESERVED_2[16]; | ||
| 10394 | __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ | ||
| 10395 | uint8_t RESERVED_3[80]; | ||
| 10396 | __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ | ||
| 10397 | __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ | ||
| 10398 | uint8_t RESERVED_4[36]; | ||
| 10399 | __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ | ||
| 10400 | uint8_t RESERVED_5[16]; | ||
| 10401 | __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ | ||
| 10402 | __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ | ||
| 10403 | uint8_t RESERVED_6[24]; | ||
| 10404 | __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ | ||
| 10405 | uint8_t RESERVED_7[16]; | ||
| 10406 | __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ | ||
| 10407 | uint8_t RESERVED_8[16]; | ||
| 10408 | __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ | ||
| 10409 | uint8_t RESERVED_9[24]; | ||
| 10410 | __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ | ||
| 10411 | uint8_t RESERVED_10[24]; | ||
| 10412 | __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ | ||
| 10413 | uint8_t RESERVED_11[1264]; | ||
| 10414 | __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ | ||
| 10415 | uint8_t RESERVED_12[4]; | ||
| 10416 | __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ | ||
| 10417 | uint8_t RESERVED_13[4]; | ||
| 10418 | __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ | ||
| 10419 | uint8_t RESERVED_14[12]; | ||
| 10420 | __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ | ||
| 10421 | uint8_t RESERVED_15[4]; | ||
| 10422 | __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ | ||
| 10423 | uint8_t RESERVED_16[4]; | ||
| 10424 | __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ | ||
| 10425 | uint8_t RESERVED_17[12]; | ||
| 10426 | __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ | ||
| 10427 | uint8_t RESERVED_18[4]; | ||
| 10428 | __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ | ||
| 10429 | uint8_t RESERVED_19[4]; | ||
| 10430 | __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ | ||
| 10431 | uint8_t RESERVED_20[12]; | ||
| 10432 | __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ | ||
| 10433 | uint8_t RESERVED_21[4]; | ||
| 10434 | __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ | ||
| 10435 | uint8_t RESERVED_22[4]; | ||
| 10436 | __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ | ||
| 10437 | } INPUTMUX_Type; | ||
| 10438 | |||
| 10439 | /* ---------------------------------------------------------------------------- | ||
| 10440 | -- INPUTMUX Register Masks | ||
| 10441 | ---------------------------------------------------------------------------- */ | ||
| 10442 | |||
| 10443 | /*! | ||
| 10444 | * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks | ||
| 10445 | * @{ | ||
| 10446 | */ | ||
| 10447 | |||
| 10448 | /*! @name SCT0_INMUX - Input mux register for SCT0 input */ | ||
| 10449 | /*! @{ */ | ||
| 10450 | #define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) | ||
| 10451 | #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) | ||
| 10452 | /*! INP_N - Input number to SCT0 inputs 0 to 6.. | ||
| 10453 | * 0b00000..SCT_GPI0 function selected from IOCON register | ||
| 10454 | * 0b00001..SCT_GPI1 function selected from IOCON register | ||
| 10455 | * 0b00010..SCT_GPI2 function selected from IOCON register | ||
| 10456 | * 0b00011..SCT_GPI3 function selected from IOCON register | ||
| 10457 | * 0b00100..SCT_GPI4 function selected from IOCON register | ||
| 10458 | * 0b00101..SCT_GPI5 function selected from IOCON register | ||
| 10459 | * 0b00110..SCT_GPI6 function selected from IOCON register | ||
| 10460 | * 0b00111..SCT_GPI7 function selected from IOCON register | ||
| 10461 | * 0b01000..T0_OUT0 ctimer 0 match[0] output | ||
| 10462 | * 0b01001..T1_OUT0 ctimer 1 match[0] output | ||
| 10463 | * 0b01010..T2_OUT0 ctimer 2 match[0] output | ||
| 10464 | * 0b01011..T3_OUT0 ctimer 3 match[0] output | ||
| 10465 | * 0b01100..T4_OUT0 ctimer 4 match[0] output | ||
| 10466 | * 0b01101..ADC_IRQ interrupt request from ADC | ||
| 10467 | * 0b01110..GPIOINT_BMATCH | ||
| 10468 | * 0b01111..USB0_FRAME_TOGGLE | ||
| 10469 | * 0b10000..USB1_FRAME_TOGGLE | ||
| 10470 | * 0b10001..COMP_OUTPUT output from analog comparator | ||
| 10471 | * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing | ||
| 10472 | * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing | ||
| 10473 | * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10474 | * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10475 | * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 | ||
| 10476 | * 0b10111..DEBUG_HALTED from cpu0 or cpu1 | ||
| 10477 | * 0b11000-0b11111..None | ||
| 10478 | */ | ||
| 10479 | #define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) | ||
| 10480 | /*! @} */ | ||
| 10481 | |||
| 10482 | /* The count of INPUTMUX_SCT0_INMUX */ | ||
| 10483 | #define INPUTMUX_SCT0_INMUX_COUNT (7U) | ||
| 10484 | |||
| 10485 | /*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ | ||
| 10486 | /*! @{ */ | ||
| 10487 | #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) | ||
| 10488 | #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) | ||
| 10489 | /*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 | ||
| 10490 | * 0b00000..CT_INP0 function selected from IOCON register | ||
| 10491 | * 0b00001..CT_INP1 function selected from IOCON register | ||
| 10492 | * 0b00010..CT_INP2 function selected from IOCON register | ||
| 10493 | * 0b00011..CT_INP3 function selected from IOCON register | ||
| 10494 | * 0b00100..CT_INP4 function selected from IOCON register | ||
| 10495 | * 0b00101..CT_INP5 function selected from IOCON register | ||
| 10496 | * 0b00110..CT_INP6 function selected from IOCON register | ||
| 10497 | * 0b00111..CT_INP7 function selected from IOCON register | ||
| 10498 | * 0b01000..CT_INP8 function selected from IOCON register | ||
| 10499 | * 0b01001..CT_INP9 function selected from IOCON register | ||
| 10500 | * 0b01010..CT_INP10 function selected from IOCON register | ||
| 10501 | * 0b01011..CT_INP11 function selected from IOCON register | ||
| 10502 | * 0b01100..CT_INP12 function selected from IOCON register | ||
| 10503 | * 0b01101..CT_INP13 function selected from IOCON register | ||
| 10504 | * 0b01110..CT_INP14 function selected from IOCON register | ||
| 10505 | * 0b01111..CT_INP15 function selected from IOCON register | ||
| 10506 | * 0b10000..CT_INP16 function selected from IOCON register | ||
| 10507 | * 0b10001..None | ||
| 10508 | * 0b10010..None | ||
| 10509 | * 0b10011..None | ||
| 10510 | * 0b10100..USB0_FRAME_TOGGLE | ||
| 10511 | * 0b10101..USB1_FRAME_TOGGLE | ||
| 10512 | * 0b10110..COMP_OUTPUT output from analog comparator | ||
| 10513 | * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10514 | * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10515 | * 0b11001-0b11111..None | ||
| 10516 | */ | ||
| 10517 | #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) | ||
| 10518 | /*! @} */ | ||
| 10519 | |||
| 10520 | /* The count of INPUTMUX_TIMER0CAPTSEL */ | ||
| 10521 | #define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) | ||
| 10522 | |||
| 10523 | /*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ | ||
| 10524 | /*! @{ */ | ||
| 10525 | #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) | ||
| 10526 | #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) | ||
| 10527 | /*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 | ||
| 10528 | * 0b00000..CT_INP0 function selected from IOCON register | ||
| 10529 | * 0b00001..CT_INP1 function selected from IOCON register | ||
| 10530 | * 0b00010..CT_INP2 function selected from IOCON register | ||
| 10531 | * 0b00011..CT_INP3 function selected from IOCON register | ||
| 10532 | * 0b00100..CT_INP4 function selected from IOCON register | ||
| 10533 | * 0b00101..CT_INP5 function selected from IOCON register | ||
| 10534 | * 0b00110..CT_INP6 function selected from IOCON register | ||
| 10535 | * 0b00111..CT_INP7 function selected from IOCON register | ||
| 10536 | * 0b01000..CT_INP8 function selected from IOCON register | ||
| 10537 | * 0b01001..CT_INP9 function selected from IOCON register | ||
| 10538 | * 0b01010..CT_INP10 function selected from IOCON register | ||
| 10539 | * 0b01011..CT_INP11 function selected from IOCON register | ||
| 10540 | * 0b01100..CT_INP12 function selected from IOCON register | ||
| 10541 | * 0b01101..CT_INP13 function selected from IOCON register | ||
| 10542 | * 0b01110..CT_INP14 function selected from IOCON register | ||
| 10543 | * 0b01111..CT_INP15 function selected from IOCON register | ||
| 10544 | * 0b10000..CT_INP16 function selected from IOCON register | ||
| 10545 | * 0b10001..None | ||
| 10546 | * 0b10010..None | ||
| 10547 | * 0b10011..None | ||
| 10548 | * 0b10100..USB0_FRAME_TOGGLE | ||
| 10549 | * 0b10101..USB1_FRAME_TOGGLE | ||
| 10550 | * 0b10110..COMP_OUTPUT output from analog comparator | ||
| 10551 | * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10552 | * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10553 | * 0b11001-0b11111..None | ||
| 10554 | */ | ||
| 10555 | #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) | ||
| 10556 | /*! @} */ | ||
| 10557 | |||
| 10558 | /* The count of INPUTMUX_TIMER1CAPTSEL */ | ||
| 10559 | #define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) | ||
| 10560 | |||
| 10561 | /*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ | ||
| 10562 | /*! @{ */ | ||
| 10563 | #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) | ||
| 10564 | #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) | ||
| 10565 | /*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 | ||
| 10566 | * 0b00000..CT_INP0 function selected from IOCON register | ||
| 10567 | * 0b00001..CT_INP1 function selected from IOCON register | ||
| 10568 | * 0b00010..CT_INP2 function selected from IOCON register | ||
| 10569 | * 0b00011..CT_INP3 function selected from IOCON register | ||
| 10570 | * 0b00100..CT_INP4 function selected from IOCON register | ||
| 10571 | * 0b00101..CT_INP5 function selected from IOCON register | ||
| 10572 | * 0b00110..CT_INP6 function selected from IOCON register | ||
| 10573 | * 0b00111..CT_INP7 function selected from IOCON register | ||
| 10574 | * 0b01000..CT_INP8 function selected from IOCON register | ||
| 10575 | * 0b01001..CT_INP9 function selected from IOCON register | ||
| 10576 | * 0b01010..CT_INP10 function selected from IOCON register | ||
| 10577 | * 0b01011..CT_INP11 function selected from IOCON register | ||
| 10578 | * 0b01100..CT_INP12 function selected from IOCON register | ||
| 10579 | * 0b01101..CT_INP13 function selected from IOCON register | ||
| 10580 | * 0b01110..CT_INP14 function selected from IOCON register | ||
| 10581 | * 0b01111..CT_INP15 function selected from IOCON register | ||
| 10582 | * 0b10000..CT_INP16 function selected from IOCON register | ||
| 10583 | * 0b10001..None | ||
| 10584 | * 0b10010..None | ||
| 10585 | * 0b10011..None | ||
| 10586 | * 0b10100..USB0_FRAME_TOGGLE | ||
| 10587 | * 0b10101..USB1_FRAME_TOGGLE | ||
| 10588 | * 0b10110..COMP_OUTPUT output from analog comparator | ||
| 10589 | * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10590 | * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10591 | * 0b11001-0b11111..None | ||
| 10592 | */ | ||
| 10593 | #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) | ||
| 10594 | /*! @} */ | ||
| 10595 | |||
| 10596 | /* The count of INPUTMUX_TIMER2CAPTSEL */ | ||
| 10597 | #define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) | ||
| 10598 | |||
| 10599 | /*! @name PINTSEL - Pin interrupt select register */ | ||
| 10600 | /*! @{ */ | ||
| 10601 | #define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) | ||
| 10602 | #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) | ||
| 10603 | /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = | ||
| 10604 | * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. | ||
| 10605 | */ | ||
| 10606 | #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) | ||
| 10607 | /*! @} */ | ||
| 10608 | |||
| 10609 | /* The count of INPUTMUX_PINTSEL */ | ||
| 10610 | #define INPUTMUX_PINTSEL_COUNT (8U) | ||
| 10611 | |||
| 10612 | /*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ | ||
| 10613 | /*! @{ */ | ||
| 10614 | #define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) | ||
| 10615 | #define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) | ||
| 10616 | /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). | ||
| 10617 | * 0b00000..Pin interrupt 0 | ||
| 10618 | * 0b00001..Pin interrupt 1 | ||
| 10619 | * 0b00010..Pin interrupt 2 | ||
| 10620 | * 0b00011..Pin interrupt 3 | ||
| 10621 | * 0b00100..Timer CTIMER0 Match 0 | ||
| 10622 | * 0b00101..Timer CTIMER0 Match 1 | ||
| 10623 | * 0b00110..Timer CTIMER1 Match 0 | ||
| 10624 | * 0b00111..Timer CTIMER1 Match 1 | ||
| 10625 | * 0b01000..Timer CTIMER2 Match 0 | ||
| 10626 | * 0b01001..Timer CTIMER2 Match 1 | ||
| 10627 | * 0b01010..Timer CTIMER3 Match 0 | ||
| 10628 | * 0b01011..Timer CTIMER3 Match 1 | ||
| 10629 | * 0b01100..Timer CTIMER4 Match 0 | ||
| 10630 | * 0b01101..Timer CTIMER4 Match 1 | ||
| 10631 | * 0b01110..COMP_OUTPUT | ||
| 10632 | * 0b01111..DMA0 output trigger mux 0 | ||
| 10633 | * 0b10000..DMA0 output trigger mux 1 | ||
| 10634 | * 0b10001..DMA0 output trigger mux 1 | ||
| 10635 | * 0b10010..DMA0 output trigger mux 3 | ||
| 10636 | * 0b10011..SCT0 DMA request 0 | ||
| 10637 | * 0b10100..SCT0 DMA request 1 | ||
| 10638 | * 0b10101..HASH DMA RX trigger | ||
| 10639 | * 0b10110-0b11111..None | ||
| 10640 | */ | ||
| 10641 | #define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) | ||
| 10642 | /*! @} */ | ||
| 10643 | |||
| 10644 | /* The count of INPUTMUX_DMA0_ITRIG_INMUX */ | ||
| 10645 | #define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) | ||
| 10646 | |||
| 10647 | /*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ | ||
| 10648 | /*! @{ */ | ||
| 10649 | #define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) | ||
| 10650 | #define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) | ||
| 10651 | /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). | ||
| 10652 | */ | ||
| 10653 | #define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) | ||
| 10654 | /*! @} */ | ||
| 10655 | |||
| 10656 | /* The count of INPUTMUX_DMA0_OTRIG_INMUX */ | ||
| 10657 | #define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) | ||
| 10658 | |||
| 10659 | /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ | ||
| 10660 | /*! @{ */ | ||
| 10661 | #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) | ||
| 10662 | #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) | ||
| 10663 | /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = | ||
| 10664 | * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock | ||
| 10665 | * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 | ||
| 10666 | */ | ||
| 10667 | #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) | ||
| 10668 | /*! @} */ | ||
| 10669 | |||
| 10670 | /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ | ||
| 10671 | /*! @{ */ | ||
| 10672 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) | ||
| 10673 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) | ||
| 10674 | /*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = | ||
| 10675 | * CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock | ||
| 10676 | * (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 | ||
| 10677 | */ | ||
| 10678 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) | ||
| 10679 | /*! @} */ | ||
| 10680 | |||
| 10681 | /*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ | ||
| 10682 | /*! @{ */ | ||
| 10683 | #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) | ||
| 10684 | #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) | ||
| 10685 | /*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 | ||
| 10686 | * 0b00000..CT_INP0 function selected from IOCON register | ||
| 10687 | * 0b00001..CT_INP1 function selected from IOCON register | ||
| 10688 | * 0b00010..CT_INP2 function selected from IOCON register | ||
| 10689 | * 0b00011..CT_INP3 function selected from IOCON register | ||
| 10690 | * 0b00100..CT_INP4 function selected from IOCON register | ||
| 10691 | * 0b00101..CT_INP5 function selected from IOCON register | ||
| 10692 | * 0b00110..CT_INP6 function selected from IOCON register | ||
| 10693 | * 0b00111..CT_INP7 function selected from IOCON register | ||
| 10694 | * 0b01000..CT_INP8 function selected from IOCON register | ||
| 10695 | * 0b01001..CT_INP9 function selected from IOCON register | ||
| 10696 | * 0b01010..CT_INP10 function selected from IOCON register | ||
| 10697 | * 0b01011..CT_INP11 function selected from IOCON register | ||
| 10698 | * 0b01100..CT_INP12 function selected from IOCON register | ||
| 10699 | * 0b01101..CT_INP13 function selected from IOCON register | ||
| 10700 | * 0b01110..CT_INP14 function selected from IOCON register | ||
| 10701 | * 0b01111..CT_INP15 function selected from IOCON register | ||
| 10702 | * 0b10000..CT_INP16 function selected from IOCON register | ||
| 10703 | * 0b10001..CT_INP17 function selected from IOCON register | ||
| 10704 | * 0b10010..CT_INP18 function selected from IOCON register | ||
| 10705 | * 0b10011..CT_INP19 function selected from IOCON register | ||
| 10706 | * 0b10100..USB0_FRAME_TOGGLE | ||
| 10707 | * 0b10101..USB1_FRAME_TOGGLE | ||
| 10708 | * 0b10110..COMP_OUTPUT output from analog comparator | ||
| 10709 | * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10710 | * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10711 | * 0b11001-0b11111..None | ||
| 10712 | */ | ||
| 10713 | #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) | ||
| 10714 | /*! @} */ | ||
| 10715 | |||
| 10716 | /* The count of INPUTMUX_TIMER3CAPTSEL */ | ||
| 10717 | #define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) | ||
| 10718 | |||
| 10719 | /*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ | ||
| 10720 | /*! @{ */ | ||
| 10721 | #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) | ||
| 10722 | #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) | ||
| 10723 | /*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 | ||
| 10724 | * 0b00000..CT_INP0 function selected from IOCON register | ||
| 10725 | * 0b00001..CT_INP1 function selected from IOCON register | ||
| 10726 | * 0b00010..CT_INP2 function selected from IOCON register | ||
| 10727 | * 0b00011..CT_INP3 function selected from IOCON register | ||
| 10728 | * 0b00100..CT_INP4 function selected from IOCON register | ||
| 10729 | * 0b00101..CT_INP5 function selected from IOCON register | ||
| 10730 | * 0b00110..CT_INP6 function selected from IOCON register | ||
| 10731 | * 0b00111..CT_INP7 function selected from IOCON register | ||
| 10732 | * 0b01000..CT_INP8 function selected from IOCON register | ||
| 10733 | * 0b01001..CT_INP9 function selected from IOCON register | ||
| 10734 | * 0b01010..CT_INP10 function selected from IOCON register | ||
| 10735 | * 0b01011..CT_INP11 function selected from IOCON register | ||
| 10736 | * 0b01100..CT_INP12 function selected from IOCON register | ||
| 10737 | * 0b01101..CT_INP13 function selected from IOCON register | ||
| 10738 | * 0b01110..CT_INP14 function selected from IOCON register | ||
| 10739 | * 0b01111..CT_INP15 function selected from IOCON register | ||
| 10740 | * 0b10000..CT_INP16 function selected from IOCON register | ||
| 10741 | * 0b10001..CT_INP17 function selected from IOCON register | ||
| 10742 | * 0b10010..CT_INP18 function selected from IOCON register | ||
| 10743 | * 0b10011..CT_INP19 function selected from IOCON register | ||
| 10744 | * 0b10100..USB0_FRAME_TOGGLE | ||
| 10745 | * 0b10101..USB1_FRAME_TOGGLE | ||
| 10746 | * 0b10110..COMP_OUTPUT output from analog comparator | ||
| 10747 | * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing | ||
| 10748 | * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing | ||
| 10749 | * 0b11001-0b11111..None | ||
| 10750 | */ | ||
| 10751 | #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) | ||
| 10752 | /*! @} */ | ||
| 10753 | |||
| 10754 | /* The count of INPUTMUX_TIMER4CAPTSEL */ | ||
| 10755 | #define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) | ||
| 10756 | |||
| 10757 | /*! @name PINTSECSEL - Pin interrupt secure select register */ | ||
| 10758 | /*! @{ */ | ||
| 10759 | #define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) | ||
| 10760 | #define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) | ||
| 10761 | /*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: | ||
| 10762 | * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. | ||
| 10763 | */ | ||
| 10764 | #define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) | ||
| 10765 | /*! @} */ | ||
| 10766 | |||
| 10767 | /* The count of INPUTMUX_PINTSECSEL */ | ||
| 10768 | #define INPUTMUX_PINTSECSEL_COUNT (2U) | ||
| 10769 | |||
| 10770 | /*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ | ||
| 10771 | /*! @{ */ | ||
| 10772 | #define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) | ||
| 10773 | #define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) | ||
| 10774 | /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). | ||
| 10775 | * 0b0000..Pin interrupt 0 | ||
| 10776 | * 0b0001..Pin interrupt 1 | ||
| 10777 | * 0b0010..Pin interrupt 2 | ||
| 10778 | * 0b0011..Pin interrupt 3 | ||
| 10779 | * 0b0100..Timer CTIMER0 Match 0 | ||
| 10780 | * 0b0101..Timer CTIMER0 Match 1 | ||
| 10781 | * 0b0110..Timer CTIMER2 Match 0 | ||
| 10782 | * 0b0111..Timer CTIMER4 Match 0 | ||
| 10783 | * 0b1000..DMA1 output trigger mux 0 | ||
| 10784 | * 0b1001..DMA1 output trigger mux 1 | ||
| 10785 | * 0b1010..DMA1 output trigger mux 2 | ||
| 10786 | * 0b1011..DMA1 output trigger mux 3 | ||
| 10787 | * 0b1100..SCT0 DMA request 0 | ||
| 10788 | * 0b1101..SCT0 DMA request 1 | ||
| 10789 | * 0b1110..HASH DMA RX trigger | ||
| 10790 | * 0b1111..None | ||
| 10791 | */ | ||
| 10792 | #define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) | ||
| 10793 | /*! @} */ | ||
| 10794 | |||
| 10795 | /* The count of INPUTMUX_DMA1_ITRIG_INMUX */ | ||
| 10796 | #define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) | ||
| 10797 | |||
| 10798 | /*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ | ||
| 10799 | /*! @{ */ | ||
| 10800 | #define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) | ||
| 10801 | #define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) | ||
| 10802 | /*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). | ||
| 10803 | */ | ||
| 10804 | #define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) | ||
| 10805 | /*! @} */ | ||
| 10806 | |||
| 10807 | /* The count of INPUTMUX_DMA1_OTRIG_INMUX */ | ||
| 10808 | #define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) | ||
| 10809 | |||
| 10810 | /*! @name DMA0_REQ_ENA - Enable DMA0 requests */ | ||
| 10811 | /*! @{ */ | ||
| 10812 | #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) | ||
| 10813 | #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) | ||
| 10814 | /*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. | ||
| 10815 | */ | ||
| 10816 | #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) | ||
| 10817 | /*! @} */ | ||
| 10818 | |||
| 10819 | /*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ | ||
| 10820 | /*! @{ */ | ||
| 10821 | #define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) | ||
| 10822 | #define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) | ||
| 10823 | /*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register | ||
| 10824 | */ | ||
| 10825 | #define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) | ||
| 10826 | /*! @} */ | ||
| 10827 | |||
| 10828 | /*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ | ||
| 10829 | /*! @{ */ | ||
| 10830 | #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) | ||
| 10831 | #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) | ||
| 10832 | /*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register | ||
| 10833 | */ | ||
| 10834 | #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) | ||
| 10835 | /*! @} */ | ||
| 10836 | |||
| 10837 | /*! @name DMA1_REQ_ENA - Enable DMA1 requests */ | ||
| 10838 | /*! @{ */ | ||
| 10839 | #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) | ||
| 10840 | #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) | ||
| 10841 | /*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. | ||
| 10842 | */ | ||
| 10843 | #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) | ||
| 10844 | /*! @} */ | ||
| 10845 | |||
| 10846 | /*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ | ||
| 10847 | /*! @{ */ | ||
| 10848 | #define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) | ||
| 10849 | #define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) | ||
| 10850 | /*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register | ||
| 10851 | */ | ||
| 10852 | #define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) | ||
| 10853 | /*! @} */ | ||
| 10854 | |||
| 10855 | /*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ | ||
| 10856 | /*! @{ */ | ||
| 10857 | #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) | ||
| 10858 | #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) | ||
| 10859 | /*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register | ||
| 10860 | */ | ||
| 10861 | #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) | ||
| 10862 | /*! @} */ | ||
| 10863 | |||
| 10864 | /*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ | ||
| 10865 | /*! @{ */ | ||
| 10866 | #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) | ||
| 10867 | #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) | ||
| 10868 | /*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. | ||
| 10869 | */ | ||
| 10870 | #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) | ||
| 10871 | /*! @} */ | ||
| 10872 | |||
| 10873 | /*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ | ||
| 10874 | /*! @{ */ | ||
| 10875 | #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) | ||
| 10876 | #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) | ||
| 10877 | /*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no | ||
| 10878 | * change in DMA0_ITRIG_ENA register | ||
| 10879 | */ | ||
| 10880 | #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) | ||
| 10881 | /*! @} */ | ||
| 10882 | |||
| 10883 | /*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ | ||
| 10884 | /*! @{ */ | ||
| 10885 | #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) | ||
| 10886 | #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) | ||
| 10887 | /*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no | ||
| 10888 | * change in DMA0_ITRIG_ENA register | ||
| 10889 | */ | ||
| 10890 | #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) | ||
| 10891 | /*! @} */ | ||
| 10892 | |||
| 10893 | /*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ | ||
| 10894 | /*! @{ */ | ||
| 10895 | #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) | ||
| 10896 | #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) | ||
| 10897 | /*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. | ||
| 10898 | */ | ||
| 10899 | #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) | ||
| 10900 | /*! @} */ | ||
| 10901 | |||
| 10902 | /*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ | ||
| 10903 | /*! @{ */ | ||
| 10904 | #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) | ||
| 10905 | #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) | ||
| 10906 | /*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no | ||
| 10907 | * change in DMA1_ITRIG_ENA register | ||
| 10908 | */ | ||
| 10909 | #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) | ||
| 10910 | /*! @} */ | ||
| 10911 | |||
| 10912 | /*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ | ||
| 10913 | /*! @{ */ | ||
| 10914 | #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) | ||
| 10915 | #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) | ||
| 10916 | /*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no | ||
| 10917 | * change in DMA1_ITRIG_ENA register | ||
| 10918 | */ | ||
| 10919 | #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) | ||
| 10920 | /*! @} */ | ||
| 10921 | |||
| 10922 | |||
| 10923 | /*! | ||
| 10924 | * @} | ||
| 10925 | */ /* end of group INPUTMUX_Register_Masks */ | ||
| 10926 | |||
| 10927 | |||
| 10928 | /* INPUTMUX - Peripheral instance base addresses */ | ||
| 10929 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 10930 | /** Peripheral INPUTMUX base address */ | ||
| 10931 | #define INPUTMUX_BASE (0x50006000u) | ||
| 10932 | /** Peripheral INPUTMUX base address */ | ||
| 10933 | #define INPUTMUX_BASE_NS (0x40006000u) | ||
| 10934 | /** Peripheral INPUTMUX base pointer */ | ||
| 10935 | #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) | ||
| 10936 | /** Peripheral INPUTMUX base pointer */ | ||
| 10937 | #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) | ||
| 10938 | /** Array initializer of INPUTMUX peripheral base addresses */ | ||
| 10939 | #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } | ||
| 10940 | /** Array initializer of INPUTMUX peripheral base pointers */ | ||
| 10941 | #define INPUTMUX_BASE_PTRS { INPUTMUX } | ||
| 10942 | /** Array initializer of INPUTMUX peripheral base addresses */ | ||
| 10943 | #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } | ||
| 10944 | /** Array initializer of INPUTMUX peripheral base pointers */ | ||
| 10945 | #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } | ||
| 10946 | #else | ||
| 10947 | /** Peripheral INPUTMUX base address */ | ||
| 10948 | #define INPUTMUX_BASE (0x40006000u) | ||
| 10949 | /** Peripheral INPUTMUX base pointer */ | ||
| 10950 | #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) | ||
| 10951 | /** Array initializer of INPUTMUX peripheral base addresses */ | ||
| 10952 | #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } | ||
| 10953 | /** Array initializer of INPUTMUX peripheral base pointers */ | ||
| 10954 | #define INPUTMUX_BASE_PTRS { INPUTMUX } | ||
| 10955 | #endif | ||
| 10956 | |||
| 10957 | /*! | ||
| 10958 | * @} | ||
| 10959 | */ /* end of group INPUTMUX_Peripheral_Access_Layer */ | ||
| 10960 | |||
| 10961 | |||
| 10962 | /* ---------------------------------------------------------------------------- | ||
| 10963 | -- IOCON Peripheral Access Layer | ||
| 10964 | ---------------------------------------------------------------------------- */ | ||
| 10965 | |||
| 10966 | /*! | ||
| 10967 | * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer | ||
| 10968 | * @{ | ||
| 10969 | */ | ||
| 10970 | |||
| 10971 | /** IOCON - Register Layout Typedef */ | ||
| 10972 | typedef struct { | ||
| 10973 | __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ | ||
| 10974 | } IOCON_Type; | ||
| 10975 | |||
| 10976 | /* ---------------------------------------------------------------------------- | ||
| 10977 | -- IOCON Register Masks | ||
| 10978 | ---------------------------------------------------------------------------- */ | ||
| 10979 | |||
| 10980 | /*! | ||
| 10981 | * @addtogroup IOCON_Register_Masks IOCON Register Masks | ||
| 10982 | * @{ | ||
| 10983 | */ | ||
| 10984 | |||
| 10985 | /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ | ||
| 10986 | /*! @{ */ | ||
| 10987 | #define IOCON_PIO_FUNC_MASK (0xFU) | ||
| 10988 | #define IOCON_PIO_FUNC_SHIFT (0U) | ||
| 10989 | /*! FUNC - Selects pin function. | ||
| 10990 | * 0b0000..Alternative connection 0. | ||
| 10991 | * 0b0001..Alternative connection 1. | ||
| 10992 | * 0b0010..Alternative connection 2. | ||
| 10993 | * 0b0011..Alternative connection 3. | ||
| 10994 | * 0b0100..Alternative connection 4. | ||
| 10995 | * 0b0101..Alternative connection 5. | ||
| 10996 | * 0b0110..Alternative connection 6. | ||
| 10997 | * 0b0111..Alternative connection 7. | ||
| 10998 | */ | ||
| 10999 | #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) | ||
| 11000 | #define IOCON_PIO_MODE_MASK (0x30U) | ||
| 11001 | #define IOCON_PIO_MODE_SHIFT (4U) | ||
| 11002 | /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). | ||
| 11003 | * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). | ||
| 11004 | * 0b01..Pull-down. Pull-down resistor enabled. | ||
| 11005 | * 0b10..Pull-up. Pull-up resistor enabled. | ||
| 11006 | * 0b11..Repeater. Repeater mode. | ||
| 11007 | */ | ||
| 11008 | #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) | ||
| 11009 | #define IOCON_PIO_SLEW_MASK (0x40U) | ||
| 11010 | #define IOCON_PIO_SLEW_SHIFT (6U) | ||
| 11011 | /*! SLEW - Driver slew rate. | ||
| 11012 | * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. | ||
| 11013 | * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. | ||
| 11014 | */ | ||
| 11015 | #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) | ||
| 11016 | #define IOCON_PIO_INVERT_MASK (0x80U) | ||
| 11017 | #define IOCON_PIO_INVERT_SHIFT (7U) | ||
| 11018 | /*! INVERT - Input polarity. | ||
| 11019 | * 0b0..Disabled. Input function is not inverted. | ||
| 11020 | * 0b1..Enabled. Input is function inverted. | ||
| 11021 | */ | ||
| 11022 | #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) | ||
| 11023 | #define IOCON_PIO_DIGIMODE_MASK (0x100U) | ||
| 11024 | #define IOCON_PIO_DIGIMODE_SHIFT (8U) | ||
| 11025 | /*! DIGIMODE - Select Digital mode. | ||
| 11026 | * 0b0..Disable digital mode. Digital input set to 0. | ||
| 11027 | * 0b1..Enable Digital mode. Digital input is enabled. | ||
| 11028 | */ | ||
| 11029 | #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) | ||
| 11030 | #define IOCON_PIO_OD_MASK (0x200U) | ||
| 11031 | #define IOCON_PIO_OD_SHIFT (9U) | ||
| 11032 | /*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). | ||
| 11033 | * 0b0..Normal. Normal push-pull output | ||
| 11034 | * 0b1..Open-drain. Simulated open-drain output (high drive disabled). | ||
| 11035 | */ | ||
| 11036 | #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) | ||
| 11037 | #define IOCON_PIO_ASW_MASK (0x400U) | ||
| 11038 | #define IOCON_PIO_ASW_SHIFT (10U) | ||
| 11039 | /*! ASW - Analog switch input control. | ||
| 11040 | * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed | ||
| 11041 | * (enabled). For the other pins, analog switch is open (disabled). | ||
| 11042 | * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) | ||
| 11043 | */ | ||
| 11044 | #define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) | ||
| 11045 | #define IOCON_PIO_SSEL_MASK (0x800U) | ||
| 11046 | #define IOCON_PIO_SSEL_SHIFT (11U) | ||
| 11047 | /*! SSEL - Supply Selection bit. | ||
| 11048 | * 0b0..3V3 Signaling in I2C Mode. | ||
| 11049 | * 0b1..1V8 Signaling in I2C Mode. | ||
| 11050 | */ | ||
| 11051 | #define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) | ||
| 11052 | #define IOCON_PIO_FILTEROFF_MASK (0x1000U) | ||
| 11053 | #define IOCON_PIO_FILTEROFF_SHIFT (12U) | ||
| 11054 | /*! FILTEROFF - Controls input glitch filter. | ||
| 11055 | * 0b0..Filter enabled. | ||
| 11056 | * 0b1..Filter disabled. | ||
| 11057 | */ | ||
| 11058 | #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) | ||
| 11059 | #define IOCON_PIO_ECS_MASK (0x2000U) | ||
| 11060 | #define IOCON_PIO_ECS_SHIFT (13U) | ||
| 11061 | /*! ECS - Pull-up current source enable in I2C mode. | ||
| 11062 | * 0b1..Enabled. Pull resistor is conencted. | ||
| 11063 | * 0b0..Disabled. IO is in open drain cell. | ||
| 11064 | */ | ||
| 11065 | #define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) | ||
| 11066 | #define IOCON_PIO_EGP_MASK (0x4000U) | ||
| 11067 | #define IOCON_PIO_EGP_SHIFT (14U) | ||
| 11068 | /*! EGP - Switch between GPIO mode and I2C mode. | ||
| 11069 | * 0b0..I2C mode. | ||
| 11070 | * 0b1..GPIO mode. | ||
| 11071 | */ | ||
| 11072 | #define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) | ||
| 11073 | #define IOCON_PIO_I2CFILTER_MASK (0x8000U) | ||
| 11074 | #define IOCON_PIO_I2CFILTER_SHIFT (15U) | ||
| 11075 | /*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. | ||
| 11076 | * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. | ||
| 11077 | * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. | ||
| 11078 | */ | ||
| 11079 | #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) | ||
| 11080 | /*! @} */ | ||
| 11081 | |||
| 11082 | /* The count of IOCON_PIO */ | ||
| 11083 | #define IOCON_PIO_COUNT (2U) | ||
| 11084 | |||
| 11085 | /* The count of IOCON_PIO */ | ||
| 11086 | #define IOCON_PIO_COUNT2 (32U) | ||
| 11087 | |||
| 11088 | |||
| 11089 | /*! | ||
| 11090 | * @} | ||
| 11091 | */ /* end of group IOCON_Register_Masks */ | ||
| 11092 | |||
| 11093 | |||
| 11094 | /* IOCON - Peripheral instance base addresses */ | ||
| 11095 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 11096 | /** Peripheral IOCON base address */ | ||
| 11097 | #define IOCON_BASE (0x50001000u) | ||
| 11098 | /** Peripheral IOCON base address */ | ||
| 11099 | #define IOCON_BASE_NS (0x40001000u) | ||
| 11100 | /** Peripheral IOCON base pointer */ | ||
| 11101 | #define IOCON ((IOCON_Type *)IOCON_BASE) | ||
| 11102 | /** Peripheral IOCON base pointer */ | ||
| 11103 | #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) | ||
| 11104 | /** Array initializer of IOCON peripheral base addresses */ | ||
| 11105 | #define IOCON_BASE_ADDRS { IOCON_BASE } | ||
| 11106 | /** Array initializer of IOCON peripheral base pointers */ | ||
| 11107 | #define IOCON_BASE_PTRS { IOCON } | ||
| 11108 | /** Array initializer of IOCON peripheral base addresses */ | ||
| 11109 | #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } | ||
| 11110 | /** Array initializer of IOCON peripheral base pointers */ | ||
| 11111 | #define IOCON_BASE_PTRS_NS { IOCON_NS } | ||
| 11112 | #else | ||
| 11113 | /** Peripheral IOCON base address */ | ||
| 11114 | #define IOCON_BASE (0x40001000u) | ||
| 11115 | /** Peripheral IOCON base pointer */ | ||
| 11116 | #define IOCON ((IOCON_Type *)IOCON_BASE) | ||
| 11117 | /** Array initializer of IOCON peripheral base addresses */ | ||
| 11118 | #define IOCON_BASE_ADDRS { IOCON_BASE } | ||
| 11119 | /** Array initializer of IOCON peripheral base pointers */ | ||
| 11120 | #define IOCON_BASE_PTRS { IOCON } | ||
| 11121 | #endif | ||
| 11122 | |||
| 11123 | /*! | ||
| 11124 | * @} | ||
| 11125 | */ /* end of group IOCON_Peripheral_Access_Layer */ | ||
| 11126 | |||
| 11127 | |||
| 11128 | /* ---------------------------------------------------------------------------- | ||
| 11129 | -- MRT Peripheral Access Layer | ||
| 11130 | ---------------------------------------------------------------------------- */ | ||
| 11131 | |||
| 11132 | /*! | ||
| 11133 | * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer | ||
| 11134 | * @{ | ||
| 11135 | */ | ||
| 11136 | |||
| 11137 | /** MRT - Register Layout Typedef */ | ||
| 11138 | typedef struct { | ||
| 11139 | struct { /* offset: 0x0, array step: 0x10 */ | ||
| 11140 | __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ | ||
| 11141 | __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ | ||
| 11142 | __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ | ||
| 11143 | __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ | ||
| 11144 | } CHANNEL[4]; | ||
| 11145 | uint8_t RESERVED_0[176]; | ||
| 11146 | __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ | ||
| 11147 | __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ | ||
| 11148 | __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ | ||
| 11149 | } MRT_Type; | ||
| 11150 | |||
| 11151 | /* ---------------------------------------------------------------------------- | ||
| 11152 | -- MRT Register Masks | ||
| 11153 | ---------------------------------------------------------------------------- */ | ||
| 11154 | |||
| 11155 | /*! | ||
| 11156 | * @addtogroup MRT_Register_Masks MRT Register Masks | ||
| 11157 | * @{ | ||
| 11158 | */ | ||
| 11159 | |||
| 11160 | /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ | ||
| 11161 | /*! @{ */ | ||
| 11162 | #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) | ||
| 11163 | #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) | ||
| 11164 | /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT | ||
| 11165 | * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to | ||
| 11166 | * this bit field starts the timer immediately. If the timer is running, writing a zero to this | ||
| 11167 | * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer | ||
| 11168 | * stops at the end of the time interval. | ||
| 11169 | */ | ||
| 11170 | #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) | ||
| 11171 | #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) | ||
| 11172 | #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) | ||
| 11173 | /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. | ||
| 11174 | * This bit is write-only. Reading this bit always returns 0. | ||
| 11175 | * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the | ||
| 11176 | * time interval if the repeat mode is selected. | ||
| 11177 | * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. | ||
| 11178 | */ | ||
| 11179 | #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) | ||
| 11180 | /*! @} */ | ||
| 11181 | |||
| 11182 | /* The count of MRT_CHANNEL_INTVAL */ | ||
| 11183 | #define MRT_CHANNEL_INTVAL_COUNT (4U) | ||
| 11184 | |||
| 11185 | /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ | ||
| 11186 | /*! @{ */ | ||
| 11187 | #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) | ||
| 11188 | #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) | ||
| 11189 | /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn | ||
| 11190 | * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval | ||
| 11191 | * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn | ||
| 11192 | * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields | ||
| 11193 | * returns -1 (0x00FF FFFF). | ||
| 11194 | */ | ||
| 11195 | #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) | ||
| 11196 | /*! @} */ | ||
| 11197 | |||
| 11198 | /* The count of MRT_CHANNEL_TIMER */ | ||
| 11199 | #define MRT_CHANNEL_TIMER_COUNT (4U) | ||
| 11200 | |||
| 11201 | /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ | ||
| 11202 | /*! @{ */ | ||
| 11203 | #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) | ||
| 11204 | #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) | ||
| 11205 | /*! INTEN - Enable the TIMERn interrupt. | ||
| 11206 | * 0b0..Disabled. TIMERn interrupt is disabled. | ||
| 11207 | * 0b1..Enabled. TIMERn interrupt is enabled. | ||
| 11208 | */ | ||
| 11209 | #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) | ||
| 11210 | #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) | ||
| 11211 | #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) | ||
| 11212 | /*! MODE - Selects timer mode. | ||
| 11213 | * 0b00..Repeat interrupt mode. | ||
| 11214 | * 0b01..One-shot interrupt mode. | ||
| 11215 | * 0b10..One-shot stall mode. | ||
| 11216 | * 0b11..Reserved. | ||
| 11217 | */ | ||
| 11218 | #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) | ||
| 11219 | /*! @} */ | ||
| 11220 | |||
| 11221 | /* The count of MRT_CHANNEL_CTRL */ | ||
| 11222 | #define MRT_CHANNEL_CTRL_COUNT (4U) | ||
| 11223 | |||
| 11224 | /*! @name CHANNEL_STAT - MRT Status register. */ | ||
| 11225 | /*! @{ */ | ||
| 11226 | #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) | ||
| 11227 | #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) | ||
| 11228 | /*! INTFLAG - Monitors the interrupt flag. | ||
| 11229 | * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. | ||
| 11230 | * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If | ||
| 11231 | * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt | ||
| 11232 | * are raised. Writing a 1 to this bit clears the interrupt request. | ||
| 11233 | */ | ||
| 11234 | #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) | ||
| 11235 | #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) | ||
| 11236 | #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) | ||
| 11237 | /*! RUN - Indicates the state of TIMERn. This bit is read-only. | ||
| 11238 | * 0b0..Idle state. TIMERn is stopped. | ||
| 11239 | * 0b1..Running. TIMERn is running. | ||
| 11240 | */ | ||
| 11241 | #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) | ||
| 11242 | #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) | ||
| 11243 | #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) | ||
| 11244 | /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG | ||
| 11245 | * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating | ||
| 11246 | * modes. | ||
| 11247 | * 0b0..This channel is not in use. | ||
| 11248 | * 0b1..This channel is in use. | ||
| 11249 | */ | ||
| 11250 | #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) | ||
| 11251 | /*! @} */ | ||
| 11252 | |||
| 11253 | /* The count of MRT_CHANNEL_STAT */ | ||
| 11254 | #define MRT_CHANNEL_STAT_COUNT (4U) | ||
| 11255 | |||
| 11256 | /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ | ||
| 11257 | /*! @{ */ | ||
| 11258 | #define MRT_MODCFG_NOC_MASK (0xFU) | ||
| 11259 | #define MRT_MODCFG_NOC_SHIFT (0U) | ||
| 11260 | /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) | ||
| 11261 | */ | ||
| 11262 | #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) | ||
| 11263 | #define MRT_MODCFG_NOB_MASK (0x1F0U) | ||
| 11264 | #define MRT_MODCFG_NOB_SHIFT (4U) | ||
| 11265 | /*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) | ||
| 11266 | */ | ||
| 11267 | #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) | ||
| 11268 | #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) | ||
| 11269 | #define MRT_MODCFG_MULTITASK_SHIFT (31U) | ||
| 11270 | /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. | ||
| 11271 | * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. | ||
| 11272 | * 0b1..Multi-task mode. | ||
| 11273 | */ | ||
| 11274 | #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) | ||
| 11275 | /*! @} */ | ||
| 11276 | |||
| 11277 | /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ | ||
| 11278 | /*! @{ */ | ||
| 11279 | #define MRT_IDLE_CH_CHAN_MASK (0xF0U) | ||
| 11280 | #define MRT_IDLE_CH_CHAN_SHIFT (4U) | ||
| 11281 | /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is | ||
| 11282 | * positioned such that it can be used as an offset from the MRT base address in order to access | ||
| 11283 | * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See | ||
| 11284 | * text above for more details. | ||
| 11285 | */ | ||
| 11286 | #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) | ||
| 11287 | /*! @} */ | ||
| 11288 | |||
| 11289 | /*! @name IRQ_FLAG - Global interrupt flag register */ | ||
| 11290 | /*! @{ */ | ||
| 11291 | #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) | ||
| 11292 | #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) | ||
| 11293 | /*! GFLAG0 - Monitors the interrupt flag of TIMER0. | ||
| 11294 | * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. | ||
| 11295 | * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If | ||
| 11296 | * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global | ||
| 11297 | * interrupt are raised. Writing a 1 to this bit clears the interrupt request. | ||
| 11298 | */ | ||
| 11299 | #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) | ||
| 11300 | #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) | ||
| 11301 | #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) | ||
| 11302 | /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. | ||
| 11303 | */ | ||
| 11304 | #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) | ||
| 11305 | #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) | ||
| 11306 | #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) | ||
| 11307 | /*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. | ||
| 11308 | */ | ||
| 11309 | #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) | ||
| 11310 | #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) | ||
| 11311 | #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) | ||
| 11312 | /*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. | ||
| 11313 | */ | ||
| 11314 | #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) | ||
| 11315 | /*! @} */ | ||
| 11316 | |||
| 11317 | |||
| 11318 | /*! | ||
| 11319 | * @} | ||
| 11320 | */ /* end of group MRT_Register_Masks */ | ||
| 11321 | |||
| 11322 | |||
| 11323 | /* MRT - Peripheral instance base addresses */ | ||
| 11324 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 11325 | /** Peripheral MRT0 base address */ | ||
| 11326 | #define MRT0_BASE (0x5000D000u) | ||
| 11327 | /** Peripheral MRT0 base address */ | ||
| 11328 | #define MRT0_BASE_NS (0x4000D000u) | ||
| 11329 | /** Peripheral MRT0 base pointer */ | ||
| 11330 | #define MRT0 ((MRT_Type *)MRT0_BASE) | ||
| 11331 | /** Peripheral MRT0 base pointer */ | ||
| 11332 | #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) | ||
| 11333 | /** Array initializer of MRT peripheral base addresses */ | ||
| 11334 | #define MRT_BASE_ADDRS { MRT0_BASE } | ||
| 11335 | /** Array initializer of MRT peripheral base pointers */ | ||
| 11336 | #define MRT_BASE_PTRS { MRT0 } | ||
| 11337 | /** Array initializer of MRT peripheral base addresses */ | ||
| 11338 | #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } | ||
| 11339 | /** Array initializer of MRT peripheral base pointers */ | ||
| 11340 | #define MRT_BASE_PTRS_NS { MRT0_NS } | ||
| 11341 | #else | ||
| 11342 | /** Peripheral MRT0 base address */ | ||
| 11343 | #define MRT0_BASE (0x4000D000u) | ||
| 11344 | /** Peripheral MRT0 base pointer */ | ||
| 11345 | #define MRT0 ((MRT_Type *)MRT0_BASE) | ||
| 11346 | /** Array initializer of MRT peripheral base addresses */ | ||
| 11347 | #define MRT_BASE_ADDRS { MRT0_BASE } | ||
| 11348 | /** Array initializer of MRT peripheral base pointers */ | ||
| 11349 | #define MRT_BASE_PTRS { MRT0 } | ||
| 11350 | #endif | ||
| 11351 | /** Interrupt vectors for the MRT peripheral type */ | ||
| 11352 | #define MRT_IRQS { MRT0_IRQn } | ||
| 11353 | |||
| 11354 | /*! | ||
| 11355 | * @} | ||
| 11356 | */ /* end of group MRT_Peripheral_Access_Layer */ | ||
| 11357 | |||
| 11358 | |||
| 11359 | /* ---------------------------------------------------------------------------- | ||
| 11360 | -- OSTIMER Peripheral Access Layer | ||
| 11361 | ---------------------------------------------------------------------------- */ | ||
| 11362 | |||
| 11363 | /*! | ||
| 11364 | * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer | ||
| 11365 | * @{ | ||
| 11366 | */ | ||
| 11367 | |||
| 11368 | /** OSTIMER - Register Layout Typedef */ | ||
| 11369 | typedef struct { | ||
| 11370 | __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ | ||
| 11371 | __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ | ||
| 11372 | __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ | ||
| 11373 | __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ | ||
| 11374 | __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ | ||
| 11375 | __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ | ||
| 11376 | uint8_t RESERVED_0[4]; | ||
| 11377 | __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ | ||
| 11378 | } OSTIMER_Type; | ||
| 11379 | |||
| 11380 | /* ---------------------------------------------------------------------------- | ||
| 11381 | -- OSTIMER Register Masks | ||
| 11382 | ---------------------------------------------------------------------------- */ | ||
| 11383 | |||
| 11384 | /*! | ||
| 11385 | * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks | ||
| 11386 | * @{ | ||
| 11387 | */ | ||
| 11388 | |||
| 11389 | /*! @name EVTIMERL - EVTIMER Low Register */ | ||
| 11390 | /*! @{ */ | ||
| 11391 | #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) | ||
| 11392 | #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) | ||
| 11393 | /*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits | ||
| 11394 | * EVTIMER. Note: There is only one EVTIMER, readable from all domains. | ||
| 11395 | */ | ||
| 11396 | #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) | ||
| 11397 | /*! @} */ | ||
| 11398 | |||
| 11399 | /*! @name EVTIMERH - EVTIMER High Register */ | ||
| 11400 | /*! @{ */ | ||
| 11401 | #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) | ||
| 11402 | #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) | ||
| 11403 | /*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits | ||
| 11404 | * EVTIMER. Note there is only one EVTIMER, readable from all domains. | ||
| 11405 | */ | ||
| 11406 | #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) | ||
| 11407 | /*! @} */ | ||
| 11408 | |||
| 11409 | /*! @name CAPTURE_L - Capture Low Register */ | ||
| 11410 | /*! @{ */ | ||
| 11411 | #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) | ||
| 11412 | #define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) | ||
| 11413 | /*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at | ||
| 11414 | * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). | ||
| 11415 | */ | ||
| 11416 | #define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) | ||
| 11417 | /*! @} */ | ||
| 11418 | |||
| 11419 | /*! @name CAPTURE_H - Capture High Register */ | ||
| 11420 | /*! @{ */ | ||
| 11421 | #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) | ||
| 11422 | #define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) | ||
| 11423 | /*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at | ||
| 11424 | * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). | ||
| 11425 | */ | ||
| 11426 | #define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) | ||
| 11427 | /*! @} */ | ||
| 11428 | |||
| 11429 | /*! @name MATCH_L - Match Low Register */ | ||
| 11430 | /*! @{ */ | ||
| 11431 | #define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) | ||
| 11432 | #define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) | ||
| 11433 | /*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central | ||
| 11434 | * EVTIMER. When a match occurs, an interrupt request is generated if enabled. | ||
| 11435 | */ | ||
| 11436 | #define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) | ||
| 11437 | /*! @} */ | ||
| 11438 | |||
| 11439 | /*! @name MATCH_H - Match High Register */ | ||
| 11440 | /*! @{ */ | ||
| 11441 | #define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) | ||
| 11442 | #define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) | ||
| 11443 | /*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared | ||
| 11444 | * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. | ||
| 11445 | */ | ||
| 11446 | #define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) | ||
| 11447 | /*! @} */ | ||
| 11448 | |||
| 11449 | /*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ | ||
| 11450 | /*! @{ */ | ||
| 11451 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) | ||
| 11452 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) | ||
| 11453 | /*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and | ||
| 11454 | * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes | ||
| 11455 | * to clear this bit are asynchronous. It should be done before a new match value is written into | ||
| 11456 | * the MATCH_L/H registers. | ||
| 11457 | */ | ||
| 11458 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) | ||
| 11459 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) | ||
| 11460 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) | ||
| 11461 | /*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will | ||
| 11462 | * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests | ||
| 11463 | * due to the OSTIMER_INTR flag are blocked. | ||
| 11464 | */ | ||
| 11465 | #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) | ||
| 11466 | #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) | ||
| 11467 | #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) | ||
| 11468 | /*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In | ||
| 11469 | * typical applications it should not be necessary to test this bit. [1] | ||
| 11470 | */ | ||
| 11471 | #define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) | ||
| 11472 | /*! @} */ | ||
| 11473 | |||
| 11474 | |||
| 11475 | /*! | ||
| 11476 | * @} | ||
| 11477 | */ /* end of group OSTIMER_Register_Masks */ | ||
| 11478 | |||
| 11479 | |||
| 11480 | /* OSTIMER - Peripheral instance base addresses */ | ||
| 11481 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 11482 | /** Peripheral OSTIMER base address */ | ||
| 11483 | #define OSTIMER_BASE (0x5002D000u) | ||
| 11484 | /** Peripheral OSTIMER base address */ | ||
| 11485 | #define OSTIMER_BASE_NS (0x4002D000u) | ||
| 11486 | /** Peripheral OSTIMER base pointer */ | ||
| 11487 | #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) | ||
| 11488 | /** Peripheral OSTIMER base pointer */ | ||
| 11489 | #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) | ||
| 11490 | /** Array initializer of OSTIMER peripheral base addresses */ | ||
| 11491 | #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } | ||
| 11492 | /** Array initializer of OSTIMER peripheral base pointers */ | ||
| 11493 | #define OSTIMER_BASE_PTRS { OSTIMER } | ||
| 11494 | /** Array initializer of OSTIMER peripheral base addresses */ | ||
| 11495 | #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } | ||
| 11496 | /** Array initializer of OSTIMER peripheral base pointers */ | ||
| 11497 | #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } | ||
| 11498 | #else | ||
| 11499 | /** Peripheral OSTIMER base address */ | ||
| 11500 | #define OSTIMER_BASE (0x4002D000u) | ||
| 11501 | /** Peripheral OSTIMER base pointer */ | ||
| 11502 | #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) | ||
| 11503 | /** Array initializer of OSTIMER peripheral base addresses */ | ||
| 11504 | #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } | ||
| 11505 | /** Array initializer of OSTIMER peripheral base pointers */ | ||
| 11506 | #define OSTIMER_BASE_PTRS { OSTIMER } | ||
| 11507 | #endif | ||
| 11508 | /** Interrupt vectors for the OSTIMER peripheral type */ | ||
| 11509 | #define OSTIMER_IRQS { OS_EVENT_IRQn } | ||
| 11510 | |||
| 11511 | /*! | ||
| 11512 | * @} | ||
| 11513 | */ /* end of group OSTIMER_Peripheral_Access_Layer */ | ||
| 11514 | |||
| 11515 | |||
| 11516 | /* ---------------------------------------------------------------------------- | ||
| 11517 | -- PINT Peripheral Access Layer | ||
| 11518 | ---------------------------------------------------------------------------- */ | ||
| 11519 | |||
| 11520 | /*! | ||
| 11521 | * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer | ||
| 11522 | * @{ | ||
| 11523 | */ | ||
| 11524 | |||
| 11525 | /** PINT - Register Layout Typedef */ | ||
| 11526 | typedef struct { | ||
| 11527 | __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ | ||
| 11528 | __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ | ||
| 11529 | __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ | ||
| 11530 | __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ | ||
| 11531 | __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ | ||
| 11532 | __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ | ||
| 11533 | __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ | ||
| 11534 | __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ | ||
| 11535 | __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ | ||
| 11536 | __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ | ||
| 11537 | __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ | ||
| 11538 | __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ | ||
| 11539 | __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ | ||
| 11540 | } PINT_Type; | ||
| 11541 | |||
| 11542 | /* ---------------------------------------------------------------------------- | ||
| 11543 | -- PINT Register Masks | ||
| 11544 | ---------------------------------------------------------------------------- */ | ||
| 11545 | |||
| 11546 | /*! | ||
| 11547 | * @addtogroup PINT_Register_Masks PINT Register Masks | ||
| 11548 | * @{ | ||
| 11549 | */ | ||
| 11550 | |||
| 11551 | /*! @name ISEL - Pin Interrupt Mode register */ | ||
| 11552 | /*! @{ */ | ||
| 11553 | #define PINT_ISEL_PMODE_MASK (0xFFU) | ||
| 11554 | #define PINT_ISEL_PMODE_SHIFT (0U) | ||
| 11555 | /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt | ||
| 11556 | * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive | ||
| 11557 | */ | ||
| 11558 | #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) | ||
| 11559 | /*! @} */ | ||
| 11560 | |||
| 11561 | /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ | ||
| 11562 | /*! @{ */ | ||
| 11563 | #define PINT_IENR_ENRL_MASK (0xFFU) | ||
| 11564 | #define PINT_IENR_ENRL_SHIFT (0U) | ||
| 11565 | /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the | ||
| 11566 | * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable | ||
| 11567 | * rising edge or level interrupt. | ||
| 11568 | */ | ||
| 11569 | #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) | ||
| 11570 | /*! @} */ | ||
| 11571 | |||
| 11572 | /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ | ||
| 11573 | /*! @{ */ | ||
| 11574 | #define PINT_SIENR_SETENRL_MASK (0xFFU) | ||
| 11575 | #define PINT_SIENR_SETENRL_SHIFT (0U) | ||
| 11576 | /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n | ||
| 11577 | * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. | ||
| 11578 | */ | ||
| 11579 | #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) | ||
| 11580 | /*! @} */ | ||
| 11581 | |||
| 11582 | /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ | ||
| 11583 | /*! @{ */ | ||
| 11584 | #define PINT_CIENR_CENRL_MASK (0xFFU) | ||
| 11585 | #define PINT_CIENR_CENRL_SHIFT (0U) | ||
| 11586 | /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit | ||
| 11587 | * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level | ||
| 11588 | * interrupt. | ||
| 11589 | */ | ||
| 11590 | #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) | ||
| 11591 | /*! @} */ | ||
| 11592 | |||
| 11593 | /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ | ||
| 11594 | /*! @{ */ | ||
| 11595 | #define PINT_IENF_ENAF_MASK (0xFFU) | ||
| 11596 | #define PINT_IENF_ENAF_SHIFT (0U) | ||
| 11597 | /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. | ||
| 11598 | * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt | ||
| 11599 | * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active | ||
| 11600 | * interrupt level HIGH. | ||
| 11601 | */ | ||
| 11602 | #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) | ||
| 11603 | /*! @} */ | ||
| 11604 | |||
| 11605 | /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ | ||
| 11606 | /*! @{ */ | ||
| 11607 | #define PINT_SIENF_SETENAF_MASK (0xFFU) | ||
| 11608 | #define PINT_SIENF_SETENAF_SHIFT (0U) | ||
| 11609 | /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n | ||
| 11610 | * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable | ||
| 11611 | * falling edge interrupt. | ||
| 11612 | */ | ||
| 11613 | #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) | ||
| 11614 | /*! @} */ | ||
| 11615 | |||
| 11616 | /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ | ||
| 11617 | /*! @{ */ | ||
| 11618 | #define PINT_CIENF_CENAF_MASK (0xFFU) | ||
| 11619 | #define PINT_CIENF_CENAF_SHIFT (0U) | ||
| 11620 | /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n | ||
| 11621 | * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or | ||
| 11622 | * falling edge interrupt disabled. | ||
| 11623 | */ | ||
| 11624 | #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) | ||
| 11625 | /*! @} */ | ||
| 11626 | |||
| 11627 | /*! @name RISE - Pin interrupt rising edge register */ | ||
| 11628 | /*! @{ */ | ||
| 11629 | #define PINT_RISE_RDET_MASK (0xFFU) | ||
| 11630 | #define PINT_RISE_RDET_SHIFT (0U) | ||
| 11631 | /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read | ||
| 11632 | * 0: No rising edge has been detected on this pin since Reset or the last time a one was written | ||
| 11633 | * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the | ||
| 11634 | * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. | ||
| 11635 | */ | ||
| 11636 | #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) | ||
| 11637 | /*! @} */ | ||
| 11638 | |||
| 11639 | /*! @name FALL - Pin interrupt falling edge register */ | ||
| 11640 | /*! @{ */ | ||
| 11641 | #define PINT_FALL_FDET_MASK (0xFFU) | ||
| 11642 | #define PINT_FALL_FDET_SHIFT (0U) | ||
| 11643 | /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read | ||
| 11644 | * 0: No falling edge has been detected on this pin since Reset or the last time a one was | ||
| 11645 | * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or | ||
| 11646 | * the last time a one was written to this bit. Write 1: clear falling edge detection for this | ||
| 11647 | * pin. | ||
| 11648 | */ | ||
| 11649 | #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) | ||
| 11650 | /*! @} */ | ||
| 11651 | |||
| 11652 | /*! @name IST - Pin interrupt status register */ | ||
| 11653 | /*! @{ */ | ||
| 11654 | #define PINT_IST_PSTAT_MASK (0xFFU) | ||
| 11655 | #define PINT_IST_PSTAT_SHIFT (0U) | ||
| 11656 | /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts | ||
| 11657 | * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for | ||
| 11658 | * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this | ||
| 11659 | * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. | ||
| 11660 | * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). | ||
| 11661 | */ | ||
| 11662 | #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) | ||
| 11663 | /*! @} */ | ||
| 11664 | |||
| 11665 | /*! @name PMCTRL - Pattern match interrupt control register */ | ||
| 11666 | /*! @{ */ | ||
| 11667 | #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) | ||
| 11668 | #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) | ||
| 11669 | /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. | ||
| 11670 | * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. | ||
| 11671 | * 0b1..Pattern match. Interrupts are driven in response to pattern matches. | ||
| 11672 | */ | ||
| 11673 | #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) | ||
| 11674 | #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) | ||
| 11675 | #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) | ||
| 11676 | /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. | ||
| 11677 | * 0b0..Disabled. RXEV output to the CPU is disabled. | ||
| 11678 | * 0b1..Enabled. RXEV output to the CPU is enabled. | ||
| 11679 | */ | ||
| 11680 | #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) | ||
| 11681 | #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) | ||
| 11682 | #define PINT_PMCTRL_PMAT_SHIFT (24U) | ||
| 11683 | /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field | ||
| 11684 | * indicates that the corresponding product term is matched by the current state of the appropriate | ||
| 11685 | * inputs. | ||
| 11686 | */ | ||
| 11687 | #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) | ||
| 11688 | /*! @} */ | ||
| 11689 | |||
| 11690 | /*! @name PMSRC - Pattern match interrupt bit-slice source register */ | ||
| 11691 | /*! @{ */ | ||
| 11692 | #define PINT_PMSRC_SRC0_MASK (0x700U) | ||
| 11693 | #define PINT_PMSRC_SRC0_SHIFT (8U) | ||
| 11694 | /*! SRC0 - Selects the input source for bit slice 0 | ||
| 11695 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. | ||
| 11696 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. | ||
| 11697 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. | ||
| 11698 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. | ||
| 11699 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. | ||
| 11700 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. | ||
| 11701 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. | ||
| 11702 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. | ||
| 11703 | */ | ||
| 11704 | #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) | ||
| 11705 | #define PINT_PMSRC_SRC1_MASK (0x3800U) | ||
| 11706 | #define PINT_PMSRC_SRC1_SHIFT (11U) | ||
| 11707 | /*! SRC1 - Selects the input source for bit slice 1 | ||
| 11708 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. | ||
| 11709 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. | ||
| 11710 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. | ||
| 11711 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. | ||
| 11712 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. | ||
| 11713 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. | ||
| 11714 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. | ||
| 11715 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. | ||
| 11716 | */ | ||
| 11717 | #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) | ||
| 11718 | #define PINT_PMSRC_SRC2_MASK (0x1C000U) | ||
| 11719 | #define PINT_PMSRC_SRC2_SHIFT (14U) | ||
| 11720 | /*! SRC2 - Selects the input source for bit slice 2 | ||
| 11721 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. | ||
| 11722 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. | ||
| 11723 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. | ||
| 11724 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. | ||
| 11725 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. | ||
| 11726 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. | ||
| 11727 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. | ||
| 11728 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. | ||
| 11729 | */ | ||
| 11730 | #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) | ||
| 11731 | #define PINT_PMSRC_SRC3_MASK (0xE0000U) | ||
| 11732 | #define PINT_PMSRC_SRC3_SHIFT (17U) | ||
| 11733 | /*! SRC3 - Selects the input source for bit slice 3 | ||
| 11734 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. | ||
| 11735 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. | ||
| 11736 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. | ||
| 11737 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. | ||
| 11738 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. | ||
| 11739 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. | ||
| 11740 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. | ||
| 11741 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. | ||
| 11742 | */ | ||
| 11743 | #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) | ||
| 11744 | #define PINT_PMSRC_SRC4_MASK (0x700000U) | ||
| 11745 | #define PINT_PMSRC_SRC4_SHIFT (20U) | ||
| 11746 | /*! SRC4 - Selects the input source for bit slice 4 | ||
| 11747 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. | ||
| 11748 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. | ||
| 11749 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. | ||
| 11750 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. | ||
| 11751 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. | ||
| 11752 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. | ||
| 11753 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. | ||
| 11754 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. | ||
| 11755 | */ | ||
| 11756 | #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) | ||
| 11757 | #define PINT_PMSRC_SRC5_MASK (0x3800000U) | ||
| 11758 | #define PINT_PMSRC_SRC5_SHIFT (23U) | ||
| 11759 | /*! SRC5 - Selects the input source for bit slice 5 | ||
| 11760 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. | ||
| 11761 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. | ||
| 11762 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. | ||
| 11763 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. | ||
| 11764 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. | ||
| 11765 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. | ||
| 11766 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. | ||
| 11767 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. | ||
| 11768 | */ | ||
| 11769 | #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) | ||
| 11770 | #define PINT_PMSRC_SRC6_MASK (0x1C000000U) | ||
| 11771 | #define PINT_PMSRC_SRC6_SHIFT (26U) | ||
| 11772 | /*! SRC6 - Selects the input source for bit slice 6 | ||
| 11773 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. | ||
| 11774 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. | ||
| 11775 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. | ||
| 11776 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. | ||
| 11777 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. | ||
| 11778 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. | ||
| 11779 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. | ||
| 11780 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. | ||
| 11781 | */ | ||
| 11782 | #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) | ||
| 11783 | #define PINT_PMSRC_SRC7_MASK (0xE0000000U) | ||
| 11784 | #define PINT_PMSRC_SRC7_SHIFT (29U) | ||
| 11785 | /*! SRC7 - Selects the input source for bit slice 7 | ||
| 11786 | * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. | ||
| 11787 | * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. | ||
| 11788 | * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. | ||
| 11789 | * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. | ||
| 11790 | * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. | ||
| 11791 | * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. | ||
| 11792 | * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. | ||
| 11793 | * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. | ||
| 11794 | */ | ||
| 11795 | #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) | ||
| 11796 | /*! @} */ | ||
| 11797 | |||
| 11798 | /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ | ||
| 11799 | /*! @{ */ | ||
| 11800 | #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) | ||
| 11801 | #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) | ||
| 11802 | /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. | ||
| 11803 | * 0b0..No effect. Slice 0 is not an endpoint. | ||
| 11804 | * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. | ||
| 11805 | */ | ||
| 11806 | #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) | ||
| 11807 | #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) | ||
| 11808 | #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) | ||
| 11809 | /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. | ||
| 11810 | * 0b0..No effect. Slice 1 is not an endpoint. | ||
| 11811 | * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. | ||
| 11812 | */ | ||
| 11813 | #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) | ||
| 11814 | #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) | ||
| 11815 | #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) | ||
| 11816 | /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. | ||
| 11817 | * 0b0..No effect. Slice 2 is not an endpoint. | ||
| 11818 | * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. | ||
| 11819 | */ | ||
| 11820 | #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) | ||
| 11821 | #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) | ||
| 11822 | #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) | ||
| 11823 | /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. | ||
| 11824 | * 0b0..No effect. Slice 3 is not an endpoint. | ||
| 11825 | * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. | ||
| 11826 | */ | ||
| 11827 | #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) | ||
| 11828 | #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) | ||
| 11829 | #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) | ||
| 11830 | /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. | ||
| 11831 | * 0b0..No effect. Slice 4 is not an endpoint. | ||
| 11832 | * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. | ||
| 11833 | */ | ||
| 11834 | #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) | ||
| 11835 | #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) | ||
| 11836 | #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) | ||
| 11837 | /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. | ||
| 11838 | * 0b0..No effect. Slice 5 is not an endpoint. | ||
| 11839 | * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. | ||
| 11840 | */ | ||
| 11841 | #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) | ||
| 11842 | #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) | ||
| 11843 | #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) | ||
| 11844 | /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. | ||
| 11845 | * 0b0..No effect. Slice 6 is not an endpoint. | ||
| 11846 | * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. | ||
| 11847 | */ | ||
| 11848 | #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) | ||
| 11849 | #define PINT_PMCFG_CFG0_MASK (0x700U) | ||
| 11850 | #define PINT_PMCFG_CFG0_SHIFT (8U) | ||
| 11851 | /*! CFG0 - Specifies the match contribution condition for bit slice 0. | ||
| 11852 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11853 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11854 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11855 | * PMSRC registers are written to. | ||
| 11856 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11857 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11858 | * PMSRC registers are written to. | ||
| 11859 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11860 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11861 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11862 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11863 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11864 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11865 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11866 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11867 | * is cleared after one clock cycle. | ||
| 11868 | */ | ||
| 11869 | #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) | ||
| 11870 | #define PINT_PMCFG_CFG1_MASK (0x3800U) | ||
| 11871 | #define PINT_PMCFG_CFG1_SHIFT (11U) | ||
| 11872 | /*! CFG1 - Specifies the match contribution condition for bit slice 1. | ||
| 11873 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11874 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11875 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11876 | * PMSRC registers are written to. | ||
| 11877 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11878 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11879 | * PMSRC registers are written to. | ||
| 11880 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11881 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11882 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11883 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11884 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11885 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11886 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11887 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11888 | * is cleared after one clock cycle. | ||
| 11889 | */ | ||
| 11890 | #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) | ||
| 11891 | #define PINT_PMCFG_CFG2_MASK (0x1C000U) | ||
| 11892 | #define PINT_PMCFG_CFG2_SHIFT (14U) | ||
| 11893 | /*! CFG2 - Specifies the match contribution condition for bit slice 2. | ||
| 11894 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11895 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11896 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11897 | * PMSRC registers are written to. | ||
| 11898 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11899 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11900 | * PMSRC registers are written to. | ||
| 11901 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11902 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11903 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11904 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11905 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11906 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11907 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11908 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11909 | * is cleared after one clock cycle. | ||
| 11910 | */ | ||
| 11911 | #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) | ||
| 11912 | #define PINT_PMCFG_CFG3_MASK (0xE0000U) | ||
| 11913 | #define PINT_PMCFG_CFG3_SHIFT (17U) | ||
| 11914 | /*! CFG3 - Specifies the match contribution condition for bit slice 3. | ||
| 11915 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11916 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11917 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11918 | * PMSRC registers are written to. | ||
| 11919 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11920 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11921 | * PMSRC registers are written to. | ||
| 11922 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11923 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11924 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11925 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11926 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11927 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11928 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11929 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11930 | * is cleared after one clock cycle. | ||
| 11931 | */ | ||
| 11932 | #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) | ||
| 11933 | #define PINT_PMCFG_CFG4_MASK (0x700000U) | ||
| 11934 | #define PINT_PMCFG_CFG4_SHIFT (20U) | ||
| 11935 | /*! CFG4 - Specifies the match contribution condition for bit slice 4. | ||
| 11936 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11937 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11938 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11939 | * PMSRC registers are written to. | ||
| 11940 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11941 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11942 | * PMSRC registers are written to. | ||
| 11943 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11944 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11945 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11946 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11947 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11948 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11949 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11950 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11951 | * is cleared after one clock cycle. | ||
| 11952 | */ | ||
| 11953 | #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) | ||
| 11954 | #define PINT_PMCFG_CFG5_MASK (0x3800000U) | ||
| 11955 | #define PINT_PMCFG_CFG5_SHIFT (23U) | ||
| 11956 | /*! CFG5 - Specifies the match contribution condition for bit slice 5. | ||
| 11957 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11958 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11959 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11960 | * PMSRC registers are written to. | ||
| 11961 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11962 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11963 | * PMSRC registers are written to. | ||
| 11964 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11965 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11966 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11967 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11968 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11969 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11970 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11971 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11972 | * is cleared after one clock cycle. | ||
| 11973 | */ | ||
| 11974 | #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) | ||
| 11975 | #define PINT_PMCFG_CFG6_MASK (0x1C000000U) | ||
| 11976 | #define PINT_PMCFG_CFG6_SHIFT (26U) | ||
| 11977 | /*! CFG6 - Specifies the match contribution condition for bit slice 6. | ||
| 11978 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 11979 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 11980 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11981 | * PMSRC registers are written to. | ||
| 11982 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 11983 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 11984 | * PMSRC registers are written to. | ||
| 11985 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 11986 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 11987 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 11988 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 11989 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 11990 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 11991 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 11992 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 11993 | * is cleared after one clock cycle. | ||
| 11994 | */ | ||
| 11995 | #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) | ||
| 11996 | #define PINT_PMCFG_CFG7_MASK (0xE0000000U) | ||
| 11997 | #define PINT_PMCFG_CFG7_SHIFT (29U) | ||
| 11998 | /*! CFG7 - Specifies the match contribution condition for bit slice 7. | ||
| 11999 | * 0b000..Constant HIGH. This bit slice always contributes to a product term match. | ||
| 12000 | * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last | ||
| 12001 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 12002 | * PMSRC registers are written to. | ||
| 12003 | * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last | ||
| 12004 | * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the | ||
| 12005 | * PMSRC registers are written to. | ||
| 12006 | * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input | ||
| 12007 | * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only | ||
| 12008 | * cleared when the PMCFG or the PMSRC registers are written to. | ||
| 12009 | * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. | ||
| 12010 | * 0b101..Low level. Match occurs when there is a low level on the specified input. | ||
| 12011 | * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). | ||
| 12012 | * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or | ||
| 12013 | * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit | ||
| 12014 | * is cleared after one clock cycle. | ||
| 12015 | */ | ||
| 12016 | #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) | ||
| 12017 | /*! @} */ | ||
| 12018 | |||
| 12019 | |||
| 12020 | /*! | ||
| 12021 | * @} | ||
| 12022 | */ /* end of group PINT_Register_Masks */ | ||
| 12023 | |||
| 12024 | |||
| 12025 | /* PINT - Peripheral instance base addresses */ | ||
| 12026 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 12027 | /** Peripheral PINT base address */ | ||
| 12028 | #define PINT_BASE (0x50004000u) | ||
| 12029 | /** Peripheral PINT base address */ | ||
| 12030 | #define PINT_BASE_NS (0x40004000u) | ||
| 12031 | /** Peripheral PINT base pointer */ | ||
| 12032 | #define PINT ((PINT_Type *)PINT_BASE) | ||
| 12033 | /** Peripheral PINT base pointer */ | ||
| 12034 | #define PINT_NS ((PINT_Type *)PINT_BASE_NS) | ||
| 12035 | /** Peripheral SECPINT base address */ | ||
| 12036 | #define SECPINT_BASE (0x50005000u) | ||
| 12037 | /** Peripheral SECPINT base address */ | ||
| 12038 | #define SECPINT_BASE_NS (0x40005000u) | ||
| 12039 | /** Peripheral SECPINT base pointer */ | ||
| 12040 | #define SECPINT ((PINT_Type *)SECPINT_BASE) | ||
| 12041 | /** Peripheral SECPINT base pointer */ | ||
| 12042 | #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) | ||
| 12043 | /** Array initializer of PINT peripheral base addresses */ | ||
| 12044 | #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } | ||
| 12045 | /** Array initializer of PINT peripheral base pointers */ | ||
| 12046 | #define PINT_BASE_PTRS { PINT, SECPINT } | ||
| 12047 | /** Array initializer of PINT peripheral base addresses */ | ||
| 12048 | #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } | ||
| 12049 | /** Array initializer of PINT peripheral base pointers */ | ||
| 12050 | #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } | ||
| 12051 | #else | ||
| 12052 | /** Peripheral PINT base address */ | ||
| 12053 | #define PINT_BASE (0x40004000u) | ||
| 12054 | /** Peripheral PINT base pointer */ | ||
| 12055 | #define PINT ((PINT_Type *)PINT_BASE) | ||
| 12056 | /** Peripheral SECPINT base address */ | ||
| 12057 | #define SECPINT_BASE (0x40005000u) | ||
| 12058 | /** Peripheral SECPINT base pointer */ | ||
| 12059 | #define SECPINT ((PINT_Type *)SECPINT_BASE) | ||
| 12060 | /** Array initializer of PINT peripheral base addresses */ | ||
| 12061 | #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } | ||
| 12062 | /** Array initializer of PINT peripheral base pointers */ | ||
| 12063 | #define PINT_BASE_PTRS { PINT, SECPINT } | ||
| 12064 | #endif | ||
| 12065 | /** Interrupt vectors for the PINT peripheral type */ | ||
| 12066 | #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } | ||
| 12067 | |||
| 12068 | /*! | ||
| 12069 | * @} | ||
| 12070 | */ /* end of group PINT_Peripheral_Access_Layer */ | ||
| 12071 | |||
| 12072 | |||
| 12073 | /* ---------------------------------------------------------------------------- | ||
| 12074 | -- PLU Peripheral Access Layer | ||
| 12075 | ---------------------------------------------------------------------------- */ | ||
| 12076 | |||
| 12077 | /*! | ||
| 12078 | * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer | ||
| 12079 | * @{ | ||
| 12080 | */ | ||
| 12081 | |||
| 12082 | /** PLU - Register Layout Typedef */ | ||
| 12083 | typedef struct { | ||
| 12084 | struct { /* offset: 0x0, array step: 0x20 */ | ||
| 12085 | __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ | ||
| 12086 | uint8_t RESERVED_0[12]; | ||
| 12087 | } LUT[26]; | ||
| 12088 | uint8_t RESERVED_0[1216]; | ||
| 12089 | __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ | ||
| 12090 | uint8_t RESERVED_1[152]; | ||
| 12091 | __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ | ||
| 12092 | __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ | ||
| 12093 | uint8_t RESERVED_2[760]; | ||
| 12094 | __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ | ||
| 12095 | } PLU_Type; | ||
| 12096 | |||
| 12097 | /* ---------------------------------------------------------------------------- | ||
| 12098 | -- PLU Register Masks | ||
| 12099 | ---------------------------------------------------------------------------- */ | ||
| 12100 | |||
| 12101 | /*! | ||
| 12102 | * @addtogroup PLU_Register_Masks PLU Register Masks | ||
| 12103 | * @{ | ||
| 12104 | */ | ||
| 12105 | |||
| 12106 | /*! @name LUT_INP_MUX - LUTn input x MUX */ | ||
| 12107 | /*! @{ */ | ||
| 12108 | #define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) | ||
| 12109 | #define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) | ||
| 12110 | /*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot | ||
| 12111 | * associated with the output from LUTn itself is tied low. | ||
| 12112 | * 0b000000..The PLU primary inputs 0. | ||
| 12113 | * 0b000001..The PLU primary inputs 1. | ||
| 12114 | * 0b000010..The PLU primary inputs 2. | ||
| 12115 | * 0b000011..The PLU primary inputs 3. | ||
| 12116 | * 0b000100..The PLU primary inputs 4. | ||
| 12117 | * 0b000101..The PLU primary inputs 5. | ||
| 12118 | * 0b000110..The output of LUT0. | ||
| 12119 | * 0b000111..The output of LUT1. | ||
| 12120 | * 0b001000..The output of LUT2. | ||
| 12121 | * 0b001001..The output of LUT3. | ||
| 12122 | * 0b001010..The output of LUT4. | ||
| 12123 | * 0b001011..The output of LUT5. | ||
| 12124 | * 0b001100..The output of LUT6. | ||
| 12125 | * 0b001101..The output of LUT7. | ||
| 12126 | * 0b001110..The output of LUT8. | ||
| 12127 | * 0b001111..The output of LUT9. | ||
| 12128 | * 0b010000..The output of LUT10. | ||
| 12129 | * 0b010001..The output of LUT11. | ||
| 12130 | * 0b010010..The output of LUT12. | ||
| 12131 | * 0b010011..The output of LUT13. | ||
| 12132 | * 0b010100..The output of LUT14. | ||
| 12133 | * 0b010101..The output of LUT15. | ||
| 12134 | * 0b010110..The output of LUT16. | ||
| 12135 | * 0b010111..The output of LUT17. | ||
| 12136 | * 0b011000..The output of LUT18. | ||
| 12137 | * 0b011001..The output of LUT19. | ||
| 12138 | * 0b011010..The output of LUT20. | ||
| 12139 | * 0b011011..The output of LUT21. | ||
| 12140 | * 0b011100..The output of LUT22. | ||
| 12141 | * 0b011101..The output of LUT23. | ||
| 12142 | * 0b011110..The output of LUT24. | ||
| 12143 | * 0b011111..The output of LUT25. | ||
| 12144 | * 0b100000..state(0). | ||
| 12145 | * 0b100001..state(1). | ||
| 12146 | * 0b100010..state(2). | ||
| 12147 | * 0b100011..state(3). | ||
| 12148 | */ | ||
| 12149 | #define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) | ||
| 12150 | /*! @} */ | ||
| 12151 | |||
| 12152 | /* The count of PLU_LUT_INP_MUX */ | ||
| 12153 | #define PLU_LUT_INP_MUX_COUNT (26U) | ||
| 12154 | |||
| 12155 | /* The count of PLU_LUT_INP_MUX */ | ||
| 12156 | #define PLU_LUT_INP_MUX_COUNT2 (5U) | ||
| 12157 | |||
| 12158 | /*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ | ||
| 12159 | /*! @{ */ | ||
| 12160 | #define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) | ||
| 12161 | #define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) | ||
| 12162 | /*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. | ||
| 12163 | */ | ||
| 12164 | #define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) | ||
| 12165 | /*! @} */ | ||
| 12166 | |||
| 12167 | /* The count of PLU_LUT_TRUTH */ | ||
| 12168 | #define PLU_LUT_TRUTH_COUNT (26U) | ||
| 12169 | |||
| 12170 | /*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ | ||
| 12171 | /*! @{ */ | ||
| 12172 | #define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) | ||
| 12173 | #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) | ||
| 12174 | /*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. | ||
| 12175 | */ | ||
| 12176 | #define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) | ||
| 12177 | /*! @} */ | ||
| 12178 | |||
| 12179 | /*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ | ||
| 12180 | /*! @{ */ | ||
| 12181 | #define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) | ||
| 12182 | #define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) | ||
| 12183 | /*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) | ||
| 12184 | */ | ||
| 12185 | #define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) | ||
| 12186 | #define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) | ||
| 12187 | #define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) | ||
| 12188 | /*! FILTER_MODE - control input of the PLU, add filtering for glitch. | ||
| 12189 | * 0b00..Bypass mode. | ||
| 12190 | * 0b01..Filter 1 clock period. | ||
| 12191 | * 0b10..Filter 2 clock period. | ||
| 12192 | * 0b11..Filter 3 clock period. | ||
| 12193 | */ | ||
| 12194 | #define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) | ||
| 12195 | #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) | ||
| 12196 | #define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) | ||
| 12197 | /*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. | ||
| 12198 | * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. | ||
| 12199 | * 0b01..Selects the 12 Mhz FRO as the filter clock. | ||
| 12200 | * 0b10..Selects a third filter clock source, if provided. | ||
| 12201 | * 0b11..Reserved. | ||
| 12202 | */ | ||
| 12203 | #define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) | ||
| 12204 | #define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) | ||
| 12205 | #define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) | ||
| 12206 | /*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR | ||
| 12207 | */ | ||
| 12208 | #define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) | ||
| 12209 | #define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) | ||
| 12210 | #define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) | ||
| 12211 | /*! INTR_CLEAR - Write to clear wakeint_latched | ||
| 12212 | */ | ||
| 12213 | #define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) | ||
| 12214 | /*! @} */ | ||
| 12215 | |||
| 12216 | /*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ | ||
| 12217 | /*! @{ */ | ||
| 12218 | #define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) | ||
| 12219 | #define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) | ||
| 12220 | /*! OUTPUTn - Selects the source to be connected to PLU Output 7. | ||
| 12221 | * 0b00000..The PLU output 0. | ||
| 12222 | * 0b00001..The PLU output 1. | ||
| 12223 | * 0b00010..The PLU output 2. | ||
| 12224 | * 0b00011..The PLU output 3. | ||
| 12225 | * 0b00100..The PLU output 4. | ||
| 12226 | * 0b00101..The PLU output 5. | ||
| 12227 | * 0b00110..The PLU output 6. | ||
| 12228 | * 0b00111..The PLU output 7. | ||
| 12229 | * 0b01000..The PLU output 8. | ||
| 12230 | * 0b01001..The PLU output 9. | ||
| 12231 | * 0b01010..The PLU output 10. | ||
| 12232 | * 0b01011..The PLU output 11. | ||
| 12233 | * 0b01100..The PLU output 12. | ||
| 12234 | * 0b01101..The PLU output 13. | ||
| 12235 | * 0b01110..The PLU output 14. | ||
| 12236 | * 0b01111..The PLU output 15. | ||
| 12237 | * 0b10000..The PLU output 16. | ||
| 12238 | * 0b10001..The PLU output 17. | ||
| 12239 | * 0b10010..The PLU output 18. | ||
| 12240 | * 0b10011..The PLU output 19. | ||
| 12241 | * 0b10100..The PLU output 20. | ||
| 12242 | * 0b10101..The PLU output 21. | ||
| 12243 | * 0b10110..The PLU output 22. | ||
| 12244 | * 0b10111..The PLU output 23. | ||
| 12245 | * 0b11000..The PLU output 24. | ||
| 12246 | * 0b11001..The PLU output 25. | ||
| 12247 | * 0b11010..state(0). | ||
| 12248 | * 0b11011..state(1). | ||
| 12249 | * 0b11100..state(2). | ||
| 12250 | * 0b11101..state(3). | ||
| 12251 | */ | ||
| 12252 | #define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) | ||
| 12253 | /*! @} */ | ||
| 12254 | |||
| 12255 | /* The count of PLU_OUTPUT_MUX */ | ||
| 12256 | #define PLU_OUTPUT_MUX_COUNT (8U) | ||
| 12257 | |||
| 12258 | |||
| 12259 | /*! | ||
| 12260 | * @} | ||
| 12261 | */ /* end of group PLU_Register_Masks */ | ||
| 12262 | |||
| 12263 | |||
| 12264 | /* PLU - Peripheral instance base addresses */ | ||
| 12265 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 12266 | /** Peripheral PLU base address */ | ||
| 12267 | #define PLU_BASE (0x5003D000u) | ||
| 12268 | /** Peripheral PLU base address */ | ||
| 12269 | #define PLU_BASE_NS (0x4003D000u) | ||
| 12270 | /** Peripheral PLU base pointer */ | ||
| 12271 | #define PLU ((PLU_Type *)PLU_BASE) | ||
| 12272 | /** Peripheral PLU base pointer */ | ||
| 12273 | #define PLU_NS ((PLU_Type *)PLU_BASE_NS) | ||
| 12274 | /** Array initializer of PLU peripheral base addresses */ | ||
| 12275 | #define PLU_BASE_ADDRS { PLU_BASE } | ||
| 12276 | /** Array initializer of PLU peripheral base pointers */ | ||
| 12277 | #define PLU_BASE_PTRS { PLU } | ||
| 12278 | /** Array initializer of PLU peripheral base addresses */ | ||
| 12279 | #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } | ||
| 12280 | /** Array initializer of PLU peripheral base pointers */ | ||
| 12281 | #define PLU_BASE_PTRS_NS { PLU_NS } | ||
| 12282 | #else | ||
| 12283 | /** Peripheral PLU base address */ | ||
| 12284 | #define PLU_BASE (0x4003D000u) | ||
| 12285 | /** Peripheral PLU base pointer */ | ||
| 12286 | #define PLU ((PLU_Type *)PLU_BASE) | ||
| 12287 | /** Array initializer of PLU peripheral base addresses */ | ||
| 12288 | #define PLU_BASE_ADDRS { PLU_BASE } | ||
| 12289 | /** Array initializer of PLU peripheral base pointers */ | ||
| 12290 | #define PLU_BASE_PTRS { PLU } | ||
| 12291 | #endif | ||
| 12292 | |||
| 12293 | /*! | ||
| 12294 | * @} | ||
| 12295 | */ /* end of group PLU_Peripheral_Access_Layer */ | ||
| 12296 | |||
| 12297 | |||
| 12298 | /* ---------------------------------------------------------------------------- | ||
| 12299 | -- PMC Peripheral Access Layer | ||
| 12300 | ---------------------------------------------------------------------------- */ | ||
| 12301 | |||
| 12302 | /*! | ||
| 12303 | * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer | ||
| 12304 | * @{ | ||
| 12305 | */ | ||
| 12306 | |||
| 12307 | /** PMC - Register Layout Typedef */ | ||
| 12308 | typedef struct { | ||
| 12309 | uint8_t RESERVED_0[8]; | ||
| 12310 | __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ | ||
| 12311 | uint8_t RESERVED_1[36]; | ||
| 12312 | __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ | ||
| 12313 | uint8_t RESERVED_2[28]; | ||
| 12314 | __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ | ||
| 12315 | uint8_t RESERVED_3[20]; | ||
| 12316 | __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ | ||
| 12317 | uint8_t RESERVED_4[8]; | ||
| 12318 | __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ | ||
| 12319 | uint8_t RESERVED_5[12]; | ||
| 12320 | __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ | ||
| 12321 | uint8_t RESERVED_6[16]; | ||
| 12322 | __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ | ||
| 12323 | __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ | ||
| 12324 | uint8_t RESERVED_7[24]; | ||
| 12325 | __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ | ||
| 12326 | uint8_t RESERVED_8[4]; | ||
| 12327 | __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ | ||
| 12328 | uint8_t RESERVED_9[4]; | ||
| 12329 | __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ | ||
| 12330 | } PMC_Type; | ||
| 12331 | |||
| 12332 | /* ---------------------------------------------------------------------------- | ||
| 12333 | -- PMC Register Masks | ||
| 12334 | ---------------------------------------------------------------------------- */ | ||
| 12335 | |||
| 12336 | /*! | ||
| 12337 | * @addtogroup PMC_Register_Masks PMC Register Masks | ||
| 12338 | * @{ | ||
| 12339 | */ | ||
| 12340 | |||
| 12341 | /*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ | ||
| 12342 | /*! @{ */ | ||
| 12343 | #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) | ||
| 12344 | #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) | ||
| 12345 | /*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). | ||
| 12346 | * 0b0..Reset event from DEEP POWER DOWN mode is disable. | ||
| 12347 | * 0b1..Reset event from DEEP POWER DOWN mode is enable. | ||
| 12348 | */ | ||
| 12349 | #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) | ||
| 12350 | #define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) | ||
| 12351 | #define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) | ||
| 12352 | /*! BODVBATRESETENABLE - BOD VBAT reset enable. | ||
| 12353 | * 0b0..BOD VBAT reset is disable. | ||
| 12354 | * 0b1..BOD VBAT reset is enable. | ||
| 12355 | */ | ||
| 12356 | #define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) | ||
| 12357 | #define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) | ||
| 12358 | #define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) | ||
| 12359 | /*! SWRRESETENABLE - Software reset enable. | ||
| 12360 | * 0b0..Software reset is disable. | ||
| 12361 | * 0b1..Software reset is enable. | ||
| 12362 | */ | ||
| 12363 | #define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) | ||
| 12364 | /*! @} */ | ||
| 12365 | |||
| 12366 | /*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ | ||
| 12367 | /*! @{ */ | ||
| 12368 | #define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) | ||
| 12369 | #define PMC_BODVBAT_TRIGLVL_SHIFT (0U) | ||
| 12370 | /*! TRIGLVL - BoD trigger level. | ||
| 12371 | * 0b00000..1.00 V. | ||
| 12372 | * 0b00001..1.10 V. | ||
| 12373 | * 0b00010..1.20 V. | ||
| 12374 | * 0b00011..1.30 V. | ||
| 12375 | * 0b00100..1.40 V. | ||
| 12376 | * 0b00101..1.50 V. | ||
| 12377 | * 0b00110..1.60 V. | ||
| 12378 | * 0b00111..1.65 V. | ||
| 12379 | * 0b01000..1.70 V. | ||
| 12380 | * 0b01001..1.75 V. | ||
| 12381 | * 0b01010..1.80 V. | ||
| 12382 | * 0b01011..1.90 V. | ||
| 12383 | * 0b01100..2.00 V. | ||
| 12384 | * 0b01101..2.10 V. | ||
| 12385 | * 0b01110..2.20 V. | ||
| 12386 | * 0b01111..2.30 V. | ||
| 12387 | * 0b10000..2.40 V. | ||
| 12388 | * 0b10001..2.50 V. | ||
| 12389 | * 0b10010..2.60 V. | ||
| 12390 | * 0b10011..2.70 V. | ||
| 12391 | * 0b10100..2.806 V. | ||
| 12392 | * 0b10101..2.90 V. | ||
| 12393 | * 0b10110..3.00 V. | ||
| 12394 | * 0b10111..3.10 V. | ||
| 12395 | * 0b11000..3.20 V. | ||
| 12396 | * 0b11001..3.30 V. | ||
| 12397 | * 0b11010..3.30 V. | ||
| 12398 | * 0b11011..3.30 V. | ||
| 12399 | * 0b11100..3.30 V. | ||
| 12400 | * 0b11101..3.30 V. | ||
| 12401 | * 0b11110..3.30 V. | ||
| 12402 | * 0b11111..3.30 V. | ||
| 12403 | */ | ||
| 12404 | #define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) | ||
| 12405 | #define PMC_BODVBAT_HYST_MASK (0x60U) | ||
| 12406 | #define PMC_BODVBAT_HYST_SHIFT (5U) | ||
| 12407 | /*! HYST - BoD Hysteresis control. | ||
| 12408 | * 0b00..25 mV. | ||
| 12409 | * 0b01..50 mV. | ||
| 12410 | * 0b10..75 mV. | ||
| 12411 | * 0b11..100 mV. | ||
| 12412 | */ | ||
| 12413 | #define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) | ||
| 12414 | /*! @} */ | ||
| 12415 | |||
| 12416 | /*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ | ||
| 12417 | /*! @{ */ | ||
| 12418 | #define PMC_COMP_HYST_MASK (0x2U) | ||
| 12419 | #define PMC_COMP_HYST_SHIFT (1U) | ||
| 12420 | /*! HYST - Hysteris when hyst = '1'. | ||
| 12421 | * 0b0..Hysteresis is disable. | ||
| 12422 | * 0b1..Hysteresis is enable. | ||
| 12423 | */ | ||
| 12424 | #define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) | ||
| 12425 | #define PMC_COMP_VREFINPUT_MASK (0x4U) | ||
| 12426 | #define PMC_COMP_VREFINPUT_SHIFT (2U) | ||
| 12427 | /*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). | ||
| 12428 | * 0b0..Select internal VREF. | ||
| 12429 | * 0b1..Select VDDA. | ||
| 12430 | */ | ||
| 12431 | #define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) | ||
| 12432 | #define PMC_COMP_LOWPOWER_MASK (0x8U) | ||
| 12433 | #define PMC_COMP_LOWPOWER_SHIFT (3U) | ||
| 12434 | /*! LOWPOWER - Low power mode. | ||
| 12435 | * 0b0..High speed mode. | ||
| 12436 | * 0b1..Low power mode (Low speed). | ||
| 12437 | */ | ||
| 12438 | #define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) | ||
| 12439 | #define PMC_COMP_PMUX_MASK (0x70U) | ||
| 12440 | #define PMC_COMP_PMUX_SHIFT (4U) | ||
| 12441 | /*! PMUX - Control word for P multiplexer:. | ||
| 12442 | * 0b000..VREF (See fiedl VREFINPUT). | ||
| 12443 | * 0b001..Pin P0_0. | ||
| 12444 | * 0b010..Pin P0_9. | ||
| 12445 | * 0b011..Pin P0_18. | ||
| 12446 | * 0b100..Pin P1_14. | ||
| 12447 | * 0b101..Pin P2_23. | ||
| 12448 | */ | ||
| 12449 | #define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) | ||
| 12450 | #define PMC_COMP_NMUX_MASK (0x380U) | ||
| 12451 | #define PMC_COMP_NMUX_SHIFT (7U) | ||
| 12452 | /*! NMUX - Control word for N multiplexer:. | ||
| 12453 | * 0b000..VREF (See field VREFINPUT). | ||
| 12454 | * 0b001..Pin P0_0. | ||
| 12455 | * 0b010..Pin P0_9. | ||
| 12456 | * 0b011..Pin P0_18. | ||
| 12457 | * 0b100..Pin P1_14. | ||
| 12458 | * 0b101..Pin P2_23. | ||
| 12459 | */ | ||
| 12460 | #define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) | ||
| 12461 | #define PMC_COMP_VREF_MASK (0x7C00U) | ||
| 12462 | #define PMC_COMP_VREF_SHIFT (10U) | ||
| 12463 | /*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). | ||
| 12464 | */ | ||
| 12465 | #define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) | ||
| 12466 | #define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) | ||
| 12467 | #define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) | ||
| 12468 | /*! FILTERCGF_SAMPLEMODE - Filter Sample mode. | ||
| 12469 | */ | ||
| 12470 | #define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) | ||
| 12471 | #define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) | ||
| 12472 | #define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) | ||
| 12473 | /*! FILTERCGF_CLKDIV - Filter Clock div . | ||
| 12474 | */ | ||
| 12475 | #define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) | ||
| 12476 | /*! @} */ | ||
| 12477 | |||
| 12478 | /*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ | ||
| 12479 | /*! @{ */ | ||
| 12480 | #define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) | ||
| 12481 | #define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) | ||
| 12482 | /*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. | ||
| 12483 | * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. | ||
| 12484 | * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. | ||
| 12485 | */ | ||
| 12486 | #define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) | ||
| 12487 | #define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) | ||
| 12488 | #define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) | ||
| 12489 | /*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. | ||
| 12490 | * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. | ||
| 12491 | * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. | ||
| 12492 | */ | ||
| 12493 | #define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) | ||
| 12494 | #define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) | ||
| 12495 | #define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) | ||
| 12496 | /*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. | ||
| 12497 | * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. | ||
| 12498 | * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. | ||
| 12499 | */ | ||
| 12500 | #define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) | ||
| 12501 | #define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) | ||
| 12502 | #define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) | ||
| 12503 | /*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. | ||
| 12504 | * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. | ||
| 12505 | * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. | ||
| 12506 | */ | ||
| 12507 | #define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) | ||
| 12508 | /*! @} */ | ||
| 12509 | |||
| 12510 | /*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ | ||
| 12511 | /*! @{ */ | ||
| 12512 | #define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) | ||
| 12513 | #define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) | ||
| 12514 | /*! XTAL32KOK - XTAL oscillator 32 K OK signal. | ||
| 12515 | */ | ||
| 12516 | #define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) | ||
| 12517 | #define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) | ||
| 12518 | #define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) | ||
| 12519 | /*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. | ||
| 12520 | * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. | ||
| 12521 | * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. | ||
| 12522 | */ | ||
| 12523 | #define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) | ||
| 12524 | /*! @} */ | ||
| 12525 | |||
| 12526 | /*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ | ||
| 12527 | /*! @{ */ | ||
| 12528 | #define PMC_AOREG1_POR_MASK (0x10U) | ||
| 12529 | #define PMC_AOREG1_POR_SHIFT (4U) | ||
| 12530 | /*! POR - The last chip reset was caused by a Power On Reset. | ||
| 12531 | */ | ||
| 12532 | #define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) | ||
| 12533 | #define PMC_AOREG1_PADRESET_MASK (0x20U) | ||
| 12534 | #define PMC_AOREG1_PADRESET_SHIFT (5U) | ||
| 12535 | /*! PADRESET - The last chip reset was caused by a Pin Reset. | ||
| 12536 | */ | ||
| 12537 | #define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) | ||
| 12538 | #define PMC_AOREG1_BODRESET_MASK (0x40U) | ||
| 12539 | #define PMC_AOREG1_BODRESET_SHIFT (6U) | ||
| 12540 | /*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. | ||
| 12541 | */ | ||
| 12542 | #define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) | ||
| 12543 | #define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) | ||
| 12544 | #define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) | ||
| 12545 | /*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. | ||
| 12546 | */ | ||
| 12547 | #define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) | ||
| 12548 | #define PMC_AOREG1_WDTRESET_MASK (0x100U) | ||
| 12549 | #define PMC_AOREG1_WDTRESET_SHIFT (8U) | ||
| 12550 | /*! WDTRESET - The last chip reset was caused by the Watchdog Timer. | ||
| 12551 | */ | ||
| 12552 | #define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) | ||
| 12553 | #define PMC_AOREG1_SWRRESET_MASK (0x200U) | ||
| 12554 | #define PMC_AOREG1_SWRRESET_SHIFT (9U) | ||
| 12555 | /*! SWRRESET - The last chip reset was caused by a Software event. | ||
| 12556 | */ | ||
| 12557 | #define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) | ||
| 12558 | #define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) | ||
| 12559 | #define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) | ||
| 12560 | /*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. | ||
| 12561 | */ | ||
| 12562 | #define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) | ||
| 12563 | #define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) | ||
| 12564 | #define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) | ||
| 12565 | /*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. | ||
| 12566 | */ | ||
| 12567 | #define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) | ||
| 12568 | #define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) | ||
| 12569 | #define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) | ||
| 12570 | /*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. | ||
| 12571 | */ | ||
| 12572 | #define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) | ||
| 12573 | #define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) | ||
| 12574 | #define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) | ||
| 12575 | /*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. | ||
| 12576 | */ | ||
| 12577 | #define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) | ||
| 12578 | /*! @} */ | ||
| 12579 | |||
| 12580 | /*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ | ||
| 12581 | /*! @{ */ | ||
| 12582 | #define PMC_RTCOSC32K_SEL_MASK (0x1U) | ||
| 12583 | #define PMC_RTCOSC32K_SEL_SHIFT (0U) | ||
| 12584 | /*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . | ||
| 12585 | * 0b0..FRO 32 KHz. | ||
| 12586 | * 0b1..XTAL 32KHz. | ||
| 12587 | */ | ||
| 12588 | #define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) | ||
| 12589 | #define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) | ||
| 12590 | #define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) | ||
| 12591 | /*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. | ||
| 12592 | */ | ||
| 12593 | #define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) | ||
| 12594 | #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) | ||
| 12595 | #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) | ||
| 12596 | /*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. | ||
| 12597 | */ | ||
| 12598 | #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) | ||
| 12599 | #define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) | ||
| 12600 | #define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) | ||
| 12601 | /*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. | ||
| 12602 | */ | ||
| 12603 | #define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) | ||
| 12604 | #define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) | ||
| 12605 | #define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) | ||
| 12606 | /*! CLK1HZDIVHALT - Halts the divider counter. | ||
| 12607 | */ | ||
| 12608 | #define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) | ||
| 12609 | #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) | ||
| 12610 | #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) | ||
| 12611 | /*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. | ||
| 12612 | */ | ||
| 12613 | #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) | ||
| 12614 | /*! @} */ | ||
| 12615 | |||
| 12616 | /*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ | ||
| 12617 | /*! @{ */ | ||
| 12618 | #define PMC_OSTIMER_SOFTRESET_MASK (0x1U) | ||
| 12619 | #define PMC_OSTIMER_SOFTRESET_SHIFT (0U) | ||
| 12620 | /*! SOFTRESET - Active high reset. | ||
| 12621 | */ | ||
| 12622 | #define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) | ||
| 12623 | #define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) | ||
| 12624 | #define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) | ||
| 12625 | /*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. | ||
| 12626 | */ | ||
| 12627 | #define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) | ||
| 12628 | #define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) | ||
| 12629 | #define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) | ||
| 12630 | /*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). | ||
| 12631 | */ | ||
| 12632 | #define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) | ||
| 12633 | #define PMC_OSTIMER_OSC32KPD_MASK (0x8U) | ||
| 12634 | #define PMC_OSTIMER_OSC32KPD_SHIFT (3U) | ||
| 12635 | /*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. | ||
| 12636 | */ | ||
| 12637 | #define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) | ||
| 12638 | /*! @} */ | ||
| 12639 | |||
| 12640 | /*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ | ||
| 12641 | /*! @{ */ | ||
| 12642 | #define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) | ||
| 12643 | #define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) | ||
| 12644 | /*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). | ||
| 12645 | * 0b0..BOD VBAT is powered. | ||
| 12646 | * 0b1..BOD VBAT is powered down. | ||
| 12647 | */ | ||
| 12648 | #define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) | ||
| 12649 | #define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) | ||
| 12650 | #define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) | ||
| 12651 | /*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. | ||
| 12652 | * 0b0..FRO32KHz is powered. | ||
| 12653 | * 0b1..FRO32KHz is powered down. | ||
| 12654 | */ | ||
| 12655 | #define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) | ||
| 12656 | #define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) | ||
| 12657 | #define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) | ||
| 12658 | /*! PDEN_XTAL32K - Controls power to crystal 32 KHz. | ||
| 12659 | * 0b0..Crystal 32KHz is powered. | ||
| 12660 | * 0b1..Crystal 32KHz is powered down. | ||
| 12661 | */ | ||
| 12662 | #define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) | ||
| 12663 | #define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) | ||
| 12664 | #define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) | ||
| 12665 | /*! PDEN_XTAL32M - Controls power to crystal 32 MHz. | ||
| 12666 | * 0b0..Crystal 32MHz is powered. | ||
| 12667 | * 0b1..Crystal 32MHz is powered down. | ||
| 12668 | */ | ||
| 12669 | #define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) | ||
| 12670 | #define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) | ||
| 12671 | #define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) | ||
| 12672 | /*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). | ||
| 12673 | * 0b0..PLL0 is powered. | ||
| 12674 | * 0b1..PLL0 is powered down. | ||
| 12675 | */ | ||
| 12676 | #define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) | ||
| 12677 | #define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) | ||
| 12678 | #define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) | ||
| 12679 | /*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). | ||
| 12680 | * 0b0..PLL1 is powered. | ||
| 12681 | * 0b1..PLL1 is powered down. | ||
| 12682 | */ | ||
| 12683 | #define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) | ||
| 12684 | #define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) | ||
| 12685 | #define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) | ||
| 12686 | /*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. | ||
| 12687 | * 0b0..USB Full Speed phy is powered. | ||
| 12688 | * 0b1..USB Full Speed phy is powered down. | ||
| 12689 | */ | ||
| 12690 | #define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) | ||
| 12691 | #define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) | ||
| 12692 | #define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) | ||
| 12693 | /*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. | ||
| 12694 | * 0b0..USB HS phy is powered. | ||
| 12695 | * 0b1..USB HS phy is powered down. | ||
| 12696 | */ | ||
| 12697 | #define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) | ||
| 12698 | #define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) | ||
| 12699 | #define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) | ||
| 12700 | /*! PDEN_COMP - Controls power to Analog Comparator. | ||
| 12701 | * 0b0..Analog Comparator is powered. | ||
| 12702 | * 0b1..Analog Comparator is powered down. | ||
| 12703 | */ | ||
| 12704 | #define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) | ||
| 12705 | #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) | ||
| 12706 | #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) | ||
| 12707 | /*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. | ||
| 12708 | * 0b0..USB high speed LDO is powered. | ||
| 12709 | * 0b1..USB high speed LDO is powered down. | ||
| 12710 | */ | ||
| 12711 | #define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) | ||
| 12712 | #define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) | ||
| 12713 | #define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) | ||
| 12714 | /*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) | ||
| 12715 | * 0b0..auxiliary biasing is powered. | ||
| 12716 | * 0b1..auxiliary biasing is powered down. | ||
| 12717 | */ | ||
| 12718 | #define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) | ||
| 12719 | #define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) | ||
| 12720 | #define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) | ||
| 12721 | /*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. | ||
| 12722 | * 0b0..crystal 32 MHz LDO is powered. | ||
| 12723 | * 0b1..crystal 32 MHz LDO is powered down. | ||
| 12724 | */ | ||
| 12725 | #define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) | ||
| 12726 | #define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) | ||
| 12727 | #define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) | ||
| 12728 | /*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. | ||
| 12729 | * 0b0..TRNG clocks are powered. | ||
| 12730 | * 0b1..TRNG clocks are powered down. | ||
| 12731 | */ | ||
| 12732 | #define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) | ||
| 12733 | #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) | ||
| 12734 | #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) | ||
| 12735 | /*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. | ||
| 12736 | * 0b0..PLL0 Sread spectrum module is powered. | ||
| 12737 | * 0b1..PLL0 Sread spectrum module is powered down. | ||
| 12738 | */ | ||
| 12739 | #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) | ||
| 12740 | /*! @} */ | ||
| 12741 | |||
| 12742 | /*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ | ||
| 12743 | /*! @{ */ | ||
| 12744 | #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) | ||
| 12745 | #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) | ||
| 12746 | /*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. | ||
| 12747 | */ | ||
| 12748 | #define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) | ||
| 12749 | /*! @} */ | ||
| 12750 | |||
| 12751 | /*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ | ||
| 12752 | /*! @{ */ | ||
| 12753 | #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) | ||
| 12754 | #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) | ||
| 12755 | /*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. | ||
| 12756 | */ | ||
| 12757 | #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) | ||
| 12758 | /*! @} */ | ||
| 12759 | |||
| 12760 | |||
| 12761 | /*! | ||
| 12762 | * @} | ||
| 12763 | */ /* end of group PMC_Register_Masks */ | ||
| 12764 | |||
| 12765 | |||
| 12766 | /* PMC - Peripheral instance base addresses */ | ||
| 12767 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 12768 | /** Peripheral PMC base address */ | ||
| 12769 | #define PMC_BASE (0x50020000u) | ||
| 12770 | /** Peripheral PMC base address */ | ||
| 12771 | #define PMC_BASE_NS (0x40020000u) | ||
| 12772 | /** Peripheral PMC base pointer */ | ||
| 12773 | #define PMC ((PMC_Type *)PMC_BASE) | ||
| 12774 | /** Peripheral PMC base pointer */ | ||
| 12775 | #define PMC_NS ((PMC_Type *)PMC_BASE_NS) | ||
| 12776 | /** Array initializer of PMC peripheral base addresses */ | ||
| 12777 | #define PMC_BASE_ADDRS { PMC_BASE } | ||
| 12778 | /** Array initializer of PMC peripheral base pointers */ | ||
| 12779 | #define PMC_BASE_PTRS { PMC } | ||
| 12780 | /** Array initializer of PMC peripheral base addresses */ | ||
| 12781 | #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } | ||
| 12782 | /** Array initializer of PMC peripheral base pointers */ | ||
| 12783 | #define PMC_BASE_PTRS_NS { PMC_NS } | ||
| 12784 | #else | ||
| 12785 | /** Peripheral PMC base address */ | ||
| 12786 | #define PMC_BASE (0x40020000u) | ||
| 12787 | /** Peripheral PMC base pointer */ | ||
| 12788 | #define PMC ((PMC_Type *)PMC_BASE) | ||
| 12789 | /** Array initializer of PMC peripheral base addresses */ | ||
| 12790 | #define PMC_BASE_ADDRS { PMC_BASE } | ||
| 12791 | /** Array initializer of PMC peripheral base pointers */ | ||
| 12792 | #define PMC_BASE_PTRS { PMC } | ||
| 12793 | #endif | ||
| 12794 | |||
| 12795 | /*! | ||
| 12796 | * @} | ||
| 12797 | */ /* end of group PMC_Peripheral_Access_Layer */ | ||
| 12798 | |||
| 12799 | |||
| 12800 | /* ---------------------------------------------------------------------------- | ||
| 12801 | -- PRINCE Peripheral Access Layer | ||
| 12802 | ---------------------------------------------------------------------------- */ | ||
| 12803 | |||
| 12804 | /*! | ||
| 12805 | * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer | ||
| 12806 | * @{ | ||
| 12807 | */ | ||
| 12808 | |||
| 12809 | /** PRINCE - Register Layout Typedef */ | ||
| 12810 | typedef struct { | ||
| 12811 | __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ | ||
| 12812 | __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ | ||
| 12813 | __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ | ||
| 12814 | __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ | ||
| 12815 | __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ | ||
| 12816 | __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ | ||
| 12817 | __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ | ||
| 12818 | __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ | ||
| 12819 | __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ | ||
| 12820 | __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ | ||
| 12821 | __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ | ||
| 12822 | __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ | ||
| 12823 | __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ | ||
| 12824 | __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ | ||
| 12825 | __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ | ||
| 12826 | __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ | ||
| 12827 | } PRINCE_Type; | ||
| 12828 | |||
| 12829 | /* ---------------------------------------------------------------------------- | ||
| 12830 | -- PRINCE Register Masks | ||
| 12831 | ---------------------------------------------------------------------------- */ | ||
| 12832 | |||
| 12833 | /*! | ||
| 12834 | * @addtogroup PRINCE_Register_Masks PRINCE Register Masks | ||
| 12835 | * @{ | ||
| 12836 | */ | ||
| 12837 | |||
| 12838 | /*! @name ENC_ENABLE - Encryption Enable register */ | ||
| 12839 | /*! @{ */ | ||
| 12840 | #define PRINCE_ENC_ENABLE_EN_MASK (0x1U) | ||
| 12841 | #define PRINCE_ENC_ENABLE_EN_SHIFT (0U) | ||
| 12842 | /*! EN - Encryption Enable. | ||
| 12843 | * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. | ||
| 12844 | * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. | ||
| 12845 | */ | ||
| 12846 | #define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) | ||
| 12847 | /*! @} */ | ||
| 12848 | |||
| 12849 | /*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ | ||
| 12850 | /*! @{ */ | ||
| 12851 | #define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) | ||
| 12852 | #define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) | ||
| 12853 | /*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. | ||
| 12854 | */ | ||
| 12855 | #define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) | ||
| 12856 | /*! @} */ | ||
| 12857 | |||
| 12858 | /*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ | ||
| 12859 | /*! @{ */ | ||
| 12860 | #define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) | ||
| 12861 | #define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) | ||
| 12862 | /*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. | ||
| 12863 | */ | ||
| 12864 | #define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) | ||
| 12865 | /*! @} */ | ||
| 12866 | |||
| 12867 | /*! @name LOCK - Lock register */ | ||
| 12868 | /*! @{ */ | ||
| 12869 | #define PRINCE_LOCK_LOCKREG0_MASK (0x1U) | ||
| 12870 | #define PRINCE_LOCK_LOCKREG0_SHIFT (0U) | ||
| 12871 | /*! LOCKREG0 - Lock Region 0 registers. | ||
| 12872 | * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. | ||
| 12873 | * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. | ||
| 12874 | */ | ||
| 12875 | #define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) | ||
| 12876 | #define PRINCE_LOCK_LOCKREG1_MASK (0x2U) | ||
| 12877 | #define PRINCE_LOCK_LOCKREG1_SHIFT (1U) | ||
| 12878 | /*! LOCKREG1 - Lock Region 1 registers. | ||
| 12879 | * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. | ||
| 12880 | * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. | ||
| 12881 | */ | ||
| 12882 | #define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) | ||
| 12883 | #define PRINCE_LOCK_LOCKREG2_MASK (0x4U) | ||
| 12884 | #define PRINCE_LOCK_LOCKREG2_SHIFT (2U) | ||
| 12885 | /*! LOCKREG2 - Lock Region 2 registers. | ||
| 12886 | * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. | ||
| 12887 | * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. | ||
| 12888 | */ | ||
| 12889 | #define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) | ||
| 12890 | #define PRINCE_LOCK_LOCKMASK_MASK (0x100U) | ||
| 12891 | #define PRINCE_LOCK_LOCKMASK_SHIFT (8U) | ||
| 12892 | /*! LOCKMASK - Lock the Mask registers. | ||
| 12893 | * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. | ||
| 12894 | * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. | ||
| 12895 | */ | ||
| 12896 | #define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) | ||
| 12897 | /*! @} */ | ||
| 12898 | |||
| 12899 | /*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ | ||
| 12900 | /*! @{ */ | ||
| 12901 | #define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12902 | #define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) | ||
| 12903 | /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. | ||
| 12904 | */ | ||
| 12905 | #define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) | ||
| 12906 | /*! @} */ | ||
| 12907 | |||
| 12908 | /*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ | ||
| 12909 | /*! @{ */ | ||
| 12910 | #define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12911 | #define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) | ||
| 12912 | /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. | ||
| 12913 | */ | ||
| 12914 | #define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) | ||
| 12915 | /*! @} */ | ||
| 12916 | |||
| 12917 | /*! @name BASE_ADDR0 - Base Address for region 0 register */ | ||
| 12918 | /*! @{ */ | ||
| 12919 | #define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) | ||
| 12920 | #define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) | ||
| 12921 | /*! ADDR_FIXED - Fixed portion of the base address of region 0. | ||
| 12922 | */ | ||
| 12923 | #define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) | ||
| 12924 | #define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) | ||
| 12925 | #define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) | ||
| 12926 | /*! ADDR_PRG - Programmable portion of the base address of region 0. | ||
| 12927 | */ | ||
| 12928 | #define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) | ||
| 12929 | /*! @} */ | ||
| 12930 | |||
| 12931 | /*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ | ||
| 12932 | /*! @{ */ | ||
| 12933 | #define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) | ||
| 12934 | #define PRINCE_SR_ENABLE0_EN_SHIFT (0U) | ||
| 12935 | /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. | ||
| 12936 | */ | ||
| 12937 | #define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) | ||
| 12938 | /*! @} */ | ||
| 12939 | |||
| 12940 | /*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ | ||
| 12941 | /*! @{ */ | ||
| 12942 | #define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12943 | #define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) | ||
| 12944 | /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. | ||
| 12945 | */ | ||
| 12946 | #define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) | ||
| 12947 | /*! @} */ | ||
| 12948 | |||
| 12949 | /*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ | ||
| 12950 | /*! @{ */ | ||
| 12951 | #define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12952 | #define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) | ||
| 12953 | /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. | ||
| 12954 | */ | ||
| 12955 | #define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) | ||
| 12956 | /*! @} */ | ||
| 12957 | |||
| 12958 | /*! @name BASE_ADDR1 - Base Address for region 1 register */ | ||
| 12959 | /*! @{ */ | ||
| 12960 | #define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) | ||
| 12961 | #define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) | ||
| 12962 | /*! ADDR_FIXED - Fixed portion of the base address of region 1. | ||
| 12963 | */ | ||
| 12964 | #define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) | ||
| 12965 | #define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) | ||
| 12966 | #define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) | ||
| 12967 | /*! ADDR_PRG - Programmable portion of the base address of region 1. | ||
| 12968 | */ | ||
| 12969 | #define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) | ||
| 12970 | /*! @} */ | ||
| 12971 | |||
| 12972 | /*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ | ||
| 12973 | /*! @{ */ | ||
| 12974 | #define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) | ||
| 12975 | #define PRINCE_SR_ENABLE1_EN_SHIFT (0U) | ||
| 12976 | /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. | ||
| 12977 | */ | ||
| 12978 | #define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) | ||
| 12979 | /*! @} */ | ||
| 12980 | |||
| 12981 | /*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ | ||
| 12982 | /*! @{ */ | ||
| 12983 | #define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12984 | #define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) | ||
| 12985 | /*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. | ||
| 12986 | */ | ||
| 12987 | #define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) | ||
| 12988 | /*! @} */ | ||
| 12989 | |||
| 12990 | /*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ | ||
| 12991 | /*! @{ */ | ||
| 12992 | #define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) | ||
| 12993 | #define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) | ||
| 12994 | /*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. | ||
| 12995 | */ | ||
| 12996 | #define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) | ||
| 12997 | /*! @} */ | ||
| 12998 | |||
| 12999 | /*! @name BASE_ADDR2 - Base Address for region 2 register */ | ||
| 13000 | /*! @{ */ | ||
| 13001 | #define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) | ||
| 13002 | #define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) | ||
| 13003 | /*! ADDR_FIXED - Fixed portion of the base address of region 2. | ||
| 13004 | */ | ||
| 13005 | #define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) | ||
| 13006 | #define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) | ||
| 13007 | #define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) | ||
| 13008 | /*! ADDR_PRG - Programmable portion of the base address of region 2. | ||
| 13009 | */ | ||
| 13010 | #define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) | ||
| 13011 | /*! @} */ | ||
| 13012 | |||
| 13013 | /*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ | ||
| 13014 | /*! @{ */ | ||
| 13015 | #define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) | ||
| 13016 | #define PRINCE_SR_ENABLE2_EN_SHIFT (0U) | ||
| 13017 | /*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. | ||
| 13018 | */ | ||
| 13019 | #define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) | ||
| 13020 | /*! @} */ | ||
| 13021 | |||
| 13022 | |||
| 13023 | /*! | ||
| 13024 | * @} | ||
| 13025 | */ /* end of group PRINCE_Register_Masks */ | ||
| 13026 | |||
| 13027 | |||
| 13028 | /* PRINCE - Peripheral instance base addresses */ | ||
| 13029 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 13030 | /** Peripheral PRINCE base address */ | ||
| 13031 | #define PRINCE_BASE (0x50035000u) | ||
| 13032 | /** Peripheral PRINCE base address */ | ||
| 13033 | #define PRINCE_BASE_NS (0x40035000u) | ||
| 13034 | /** Peripheral PRINCE base pointer */ | ||
| 13035 | #define PRINCE ((PRINCE_Type *)PRINCE_BASE) | ||
| 13036 | /** Peripheral PRINCE base pointer */ | ||
| 13037 | #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) | ||
| 13038 | /** Array initializer of PRINCE peripheral base addresses */ | ||
| 13039 | #define PRINCE_BASE_ADDRS { PRINCE_BASE } | ||
| 13040 | /** Array initializer of PRINCE peripheral base pointers */ | ||
| 13041 | #define PRINCE_BASE_PTRS { PRINCE } | ||
| 13042 | /** Array initializer of PRINCE peripheral base addresses */ | ||
| 13043 | #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } | ||
| 13044 | /** Array initializer of PRINCE peripheral base pointers */ | ||
| 13045 | #define PRINCE_BASE_PTRS_NS { PRINCE_NS } | ||
| 13046 | #else | ||
| 13047 | /** Peripheral PRINCE base address */ | ||
| 13048 | #define PRINCE_BASE (0x40035000u) | ||
| 13049 | /** Peripheral PRINCE base pointer */ | ||
| 13050 | #define PRINCE ((PRINCE_Type *)PRINCE_BASE) | ||
| 13051 | /** Array initializer of PRINCE peripheral base addresses */ | ||
| 13052 | #define PRINCE_BASE_ADDRS { PRINCE_BASE } | ||
| 13053 | /** Array initializer of PRINCE peripheral base pointers */ | ||
| 13054 | #define PRINCE_BASE_PTRS { PRINCE } | ||
| 13055 | #endif | ||
| 13056 | |||
| 13057 | /*! | ||
| 13058 | * @} | ||
| 13059 | */ /* end of group PRINCE_Peripheral_Access_Layer */ | ||
| 13060 | |||
| 13061 | |||
| 13062 | /* ---------------------------------------------------------------------------- | ||
| 13063 | -- RNG Peripheral Access Layer | ||
| 13064 | ---------------------------------------------------------------------------- */ | ||
| 13065 | |||
| 13066 | /*! | ||
| 13067 | * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer | ||
| 13068 | * @{ | ||
| 13069 | */ | ||
| 13070 | |||
| 13071 | /** RNG - Register Layout Typedef */ | ||
| 13072 | typedef struct { | ||
| 13073 | __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ | ||
| 13074 | uint8_t RESERVED_0[4]; | ||
| 13075 | __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ | ||
| 13076 | __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ | ||
| 13077 | __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ | ||
| 13078 | __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ | ||
| 13079 | uint8_t RESERVED_1[4068]; | ||
| 13080 | __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ | ||
| 13081 | } RNG_Type; | ||
| 13082 | |||
| 13083 | /* ---------------------------------------------------------------------------- | ||
| 13084 | -- RNG Register Masks | ||
| 13085 | ---------------------------------------------------------------------------- */ | ||
| 13086 | |||
| 13087 | /*! | ||
| 13088 | * @addtogroup RNG_Register_Masks RNG Register Masks | ||
| 13089 | * @{ | ||
| 13090 | */ | ||
| 13091 | |||
| 13092 | /*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ | ||
| 13093 | /*! @{ */ | ||
| 13094 | #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) | ||
| 13095 | #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) | ||
| 13096 | /*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. | ||
| 13097 | */ | ||
| 13098 | #define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) | ||
| 13099 | /*! @} */ | ||
| 13100 | |||
| 13101 | /*! @name COUNTER_VAL - */ | ||
| 13102 | /*! @{ */ | ||
| 13103 | #define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) | ||
| 13104 | #define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) | ||
| 13105 | /*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock | ||
| 13106 | * frequency for evaluation and certification purposes. | ||
| 13107 | */ | ||
| 13108 | #define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) | ||
| 13109 | #define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) | ||
| 13110 | #define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) | ||
| 13111 | /*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. | ||
| 13112 | */ | ||
| 13113 | #define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) | ||
| 13114 | /*! @} */ | ||
| 13115 | |||
| 13116 | /*! @name COUNTER_CFG - */ | ||
| 13117 | /*! @{ */ | ||
| 13118 | #define RNG_COUNTER_CFG_MODE_MASK (0x3U) | ||
| 13119 | #define RNG_COUNTER_CFG_MODE_SHIFT (0U) | ||
| 13120 | /*! MODE - 00: disabled 01: update once. | ||
| 13121 | */ | ||
| 13122 | #define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) | ||
| 13123 | #define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) | ||
| 13124 | #define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) | ||
| 13125 | /*! CLOCK_SEL - Selects the internal clock on which to compute statistics. | ||
| 13126 | */ | ||
| 13127 | #define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) | ||
| 13128 | #define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) | ||
| 13129 | #define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) | ||
| 13130 | /*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. | ||
| 13131 | */ | ||
| 13132 | #define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) | ||
| 13133 | /*! @} */ | ||
| 13134 | |||
| 13135 | /*! @name ONLINE_TEST_CFG - */ | ||
| 13136 | /*! @{ */ | ||
| 13137 | #define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) | ||
| 13138 | #define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) | ||
| 13139 | /*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. | ||
| 13140 | */ | ||
| 13141 | #define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) | ||
| 13142 | #define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) | ||
| 13143 | #define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) | ||
| 13144 | /*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one | ||
| 13145 | * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: | ||
| 13146 | * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this | ||
| 13147 | * field. | ||
| 13148 | */ | ||
| 13149 | #define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) | ||
| 13150 | /*! @} */ | ||
| 13151 | |||
| 13152 | /*! @name ONLINE_TEST_VAL - */ | ||
| 13153 | /*! @{ */ | ||
| 13154 | #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) | ||
| 13155 | #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) | ||
| 13156 | /*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. | ||
| 13157 | */ | ||
| 13158 | #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) | ||
| 13159 | #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) | ||
| 13160 | #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) | ||
| 13161 | /*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. | ||
| 13162 | */ | ||
| 13163 | #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) | ||
| 13164 | #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) | ||
| 13165 | #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) | ||
| 13166 | /*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. | ||
| 13167 | */ | ||
| 13168 | #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) | ||
| 13169 | /*! @} */ | ||
| 13170 | |||
| 13171 | /*! @name MODULEID - IP identifier */ | ||
| 13172 | /*! @{ */ | ||
| 13173 | #define RNG_MODULEID_APERTURE_MASK (0xFFU) | ||
| 13174 | #define RNG_MODULEID_APERTURE_SHIFT (0U) | ||
| 13175 | /*! APERTURE - Aperture i. | ||
| 13176 | */ | ||
| 13177 | #define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) | ||
| 13178 | #define RNG_MODULEID_MIN_REV_MASK (0xF00U) | ||
| 13179 | #define RNG_MODULEID_MIN_REV_SHIFT (8U) | ||
| 13180 | /*! MIN_REV - Minor revision i. | ||
| 13181 | */ | ||
| 13182 | #define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) | ||
| 13183 | #define RNG_MODULEID_MAJ_REV_MASK (0xF000U) | ||
| 13184 | #define RNG_MODULEID_MAJ_REV_SHIFT (12U) | ||
| 13185 | /*! MAJ_REV - Major revision i. | ||
| 13186 | */ | ||
| 13187 | #define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) | ||
| 13188 | #define RNG_MODULEID_ID_MASK (0xFFFF0000U) | ||
| 13189 | #define RNG_MODULEID_ID_SHIFT (16U) | ||
| 13190 | /*! ID - Identifier. | ||
| 13191 | */ | ||
| 13192 | #define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) | ||
| 13193 | /*! @} */ | ||
| 13194 | |||
| 13195 | |||
| 13196 | /*! | ||
| 13197 | * @} | ||
| 13198 | */ /* end of group RNG_Register_Masks */ | ||
| 13199 | |||
| 13200 | |||
| 13201 | /* RNG - Peripheral instance base addresses */ | ||
| 13202 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 13203 | /** Peripheral RNG base address */ | ||
| 13204 | #define RNG_BASE (0x5003A000u) | ||
| 13205 | /** Peripheral RNG base address */ | ||
| 13206 | #define RNG_BASE_NS (0x4003A000u) | ||
| 13207 | /** Peripheral RNG base pointer */ | ||
| 13208 | #define RNG ((RNG_Type *)RNG_BASE) | ||
| 13209 | /** Peripheral RNG base pointer */ | ||
| 13210 | #define RNG_NS ((RNG_Type *)RNG_BASE_NS) | ||
| 13211 | /** Array initializer of RNG peripheral base addresses */ | ||
| 13212 | #define RNG_BASE_ADDRS { RNG_BASE } | ||
| 13213 | /** Array initializer of RNG peripheral base pointers */ | ||
| 13214 | #define RNG_BASE_PTRS { RNG } | ||
| 13215 | /** Array initializer of RNG peripheral base addresses */ | ||
| 13216 | #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } | ||
| 13217 | /** Array initializer of RNG peripheral base pointers */ | ||
| 13218 | #define RNG_BASE_PTRS_NS { RNG_NS } | ||
| 13219 | #else | ||
| 13220 | /** Peripheral RNG base address */ | ||
| 13221 | #define RNG_BASE (0x4003A000u) | ||
| 13222 | /** Peripheral RNG base pointer */ | ||
| 13223 | #define RNG ((RNG_Type *)RNG_BASE) | ||
| 13224 | /** Array initializer of RNG peripheral base addresses */ | ||
| 13225 | #define RNG_BASE_ADDRS { RNG_BASE } | ||
| 13226 | /** Array initializer of RNG peripheral base pointers */ | ||
| 13227 | #define RNG_BASE_PTRS { RNG } | ||
| 13228 | #endif | ||
| 13229 | |||
| 13230 | /*! | ||
| 13231 | * @} | ||
| 13232 | */ /* end of group RNG_Peripheral_Access_Layer */ | ||
| 13233 | |||
| 13234 | |||
| 13235 | /* ---------------------------------------------------------------------------- | ||
| 13236 | -- RTC Peripheral Access Layer | ||
| 13237 | ---------------------------------------------------------------------------- */ | ||
| 13238 | |||
| 13239 | /*! | ||
| 13240 | * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer | ||
| 13241 | * @{ | ||
| 13242 | */ | ||
| 13243 | |||
| 13244 | /** RTC - Register Layout Typedef */ | ||
| 13245 | typedef struct { | ||
| 13246 | __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ | ||
| 13247 | __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ | ||
| 13248 | __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ | ||
| 13249 | __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ | ||
| 13250 | __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ | ||
| 13251 | uint8_t RESERVED_0[44]; | ||
| 13252 | __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ | ||
| 13253 | } RTC_Type; | ||
| 13254 | |||
| 13255 | /* ---------------------------------------------------------------------------- | ||
| 13256 | -- RTC Register Masks | ||
| 13257 | ---------------------------------------------------------------------------- */ | ||
| 13258 | |||
| 13259 | /*! | ||
| 13260 | * @addtogroup RTC_Register_Masks RTC Register Masks | ||
| 13261 | * @{ | ||
| 13262 | */ | ||
| 13263 | |||
| 13264 | /*! @name CTRL - RTC control register */ | ||
| 13265 | /*! @{ */ | ||
| 13266 | #define RTC_CTRL_SWRESET_MASK (0x1U) | ||
| 13267 | #define RTC_CTRL_SWRESET_SHIFT (0U) | ||
| 13268 | /*! SWRESET - Software reset control | ||
| 13269 | * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. | ||
| 13270 | * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value | ||
| 13271 | * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes | ||
| 13272 | * to set any of the other bits within this register. Do not attempt to write to any bits of this register at | ||
| 13273 | * the same time that the reset bit is being cleared. | ||
| 13274 | */ | ||
| 13275 | #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) | ||
| 13276 | #define RTC_CTRL_ALARM1HZ_MASK (0x4U) | ||
| 13277 | #define RTC_CTRL_ALARM1HZ_SHIFT (2U) | ||
| 13278 | /*! ALARM1HZ - RTC 1 Hz timer alarm flag status. | ||
| 13279 | * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. | ||
| 13280 | * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt | ||
| 13281 | * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. | ||
| 13282 | */ | ||
| 13283 | #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) | ||
| 13284 | #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) | ||
| 13285 | #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) | ||
| 13286 | /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. | ||
| 13287 | * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. | ||
| 13288 | * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up | ||
| 13289 | * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. | ||
| 13290 | */ | ||
| 13291 | #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) | ||
| 13292 | #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) | ||
| 13293 | #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) | ||
| 13294 | /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. | ||
| 13295 | * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. | ||
| 13296 | * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. | ||
| 13297 | */ | ||
| 13298 | #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) | ||
| 13299 | #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) | ||
| 13300 | #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) | ||
| 13301 | /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. | ||
| 13302 | * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. | ||
| 13303 | * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. | ||
| 13304 | */ | ||
| 13305 | #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) | ||
| 13306 | #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) | ||
| 13307 | #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) | ||
| 13308 | /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz | ||
| 13309 | * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). | ||
| 13310 | * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. | ||
| 13311 | * 0b1..Enable. The 1 kHz RTC timer is enabled. | ||
| 13312 | */ | ||
| 13313 | #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) | ||
| 13314 | #define RTC_CTRL_RTC_EN_MASK (0x80U) | ||
| 13315 | #define RTC_CTRL_RTC_EN_SHIFT (7U) | ||
| 13316 | /*! RTC_EN - RTC enable. | ||
| 13317 | * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should | ||
| 13318 | * be 0 when writing to load a value in the RTC counter register. | ||
| 13319 | * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate | ||
| 13320 | * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the | ||
| 13321 | * high-resolution, 1 kHz clock, set bit 6 in this register. | ||
| 13322 | */ | ||
| 13323 | #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) | ||
| 13324 | #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) | ||
| 13325 | #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) | ||
| 13326 | /*! RTC_OSC_PD - RTC oscillator power-down control. | ||
| 13327 | * 0b0..See RTC_OSC_BYPASS | ||
| 13328 | * 0b1..RTC oscillator is powered-down. | ||
| 13329 | */ | ||
| 13330 | #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) | ||
| 13331 | #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) | ||
| 13332 | #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) | ||
| 13333 | /*! RTC_OSC_BYPASS - RTC oscillator bypass control. | ||
| 13334 | * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. | ||
| 13335 | * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. | ||
| 13336 | */ | ||
| 13337 | #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) | ||
| 13338 | #define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) | ||
| 13339 | #define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) | ||
| 13340 | /*! RTC_SUBSEC_ENA - RTC Sub-second counter control. | ||
| 13341 | * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD | ||
| 13342 | * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second | ||
| 13343 | * counter, this bit will always read-back as a '0'. | ||
| 13344 | * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first | ||
| 13345 | * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is | ||
| 13346 | * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip | ||
| 13347 | * exits deep power-down mode. | ||
| 13348 | */ | ||
| 13349 | #define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) | ||
| 13350 | /*! @} */ | ||
| 13351 | |||
| 13352 | /*! @name MATCH - RTC match register */ | ||
| 13353 | /*! @{ */ | ||
| 13354 | #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) | ||
| 13355 | #define RTC_MATCH_MATVAL_SHIFT (0U) | ||
| 13356 | /*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the | ||
| 13357 | * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. | ||
| 13358 | */ | ||
| 13359 | #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) | ||
| 13360 | /*! @} */ | ||
| 13361 | |||
| 13362 | /*! @name COUNT - RTC counter register */ | ||
| 13363 | /*! @{ */ | ||
| 13364 | #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) | ||
| 13365 | #define RTC_COUNT_VAL_SHIFT (0U) | ||
| 13366 | /*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial | ||
| 13367 | * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC | ||
| 13368 | * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this | ||
| 13369 | * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after | ||
| 13370 | * the RTC_EN bit is set. | ||
| 13371 | */ | ||
| 13372 | #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) | ||
| 13373 | /*! @} */ | ||
| 13374 | |||
| 13375 | /*! @name WAKE - High-resolution/wake-up timer control register */ | ||
| 13376 | /*! @{ */ | ||
| 13377 | #define RTC_WAKE_VAL_MASK (0xFFFFU) | ||
| 13378 | #define RTC_WAKE_VAL_SHIFT (0U) | ||
| 13379 | /*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads | ||
| 13380 | * a start count value into the wake-up timer and initializes a count-down sequence. Do not write | ||
| 13381 | * to this register while counting is in progress. | ||
| 13382 | */ | ||
| 13383 | #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) | ||
| 13384 | /*! @} */ | ||
| 13385 | |||
| 13386 | /*! @name SUBSEC - Sub-second counter register */ | ||
| 13387 | /*! @{ */ | ||
| 13388 | #define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) | ||
| 13389 | #define RTC_SUBSEC_SUBSEC_SHIFT (0U) | ||
| 13390 | /*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is | ||
| 13391 | * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz | ||
| 13392 | * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This | ||
| 13393 | * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is | ||
| 13394 | * disabled and re-enabled. On modules not equipped with a sub-second counter, this register | ||
| 13395 | * will read-back as all zeroes. | ||
| 13396 | */ | ||
| 13397 | #define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) | ||
| 13398 | /*! @} */ | ||
| 13399 | |||
| 13400 | /*! @name GPREG - General Purpose register */ | ||
| 13401 | /*! @{ */ | ||
| 13402 | #define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) | ||
| 13403 | #define RTC_GPREG_GPDATA_SHIFT (0U) | ||
| 13404 | /*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. | ||
| 13405 | */ | ||
| 13406 | #define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) | ||
| 13407 | /*! @} */ | ||
| 13408 | |||
| 13409 | /* The count of RTC_GPREG */ | ||
| 13410 | #define RTC_GPREG_COUNT (8U) | ||
| 13411 | |||
| 13412 | |||
| 13413 | /*! | ||
| 13414 | * @} | ||
| 13415 | */ /* end of group RTC_Register_Masks */ | ||
| 13416 | |||
| 13417 | |||
| 13418 | /* RTC - Peripheral instance base addresses */ | ||
| 13419 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 13420 | /** Peripheral RTC base address */ | ||
| 13421 | #define RTC_BASE (0x5002C000u) | ||
| 13422 | /** Peripheral RTC base address */ | ||
| 13423 | #define RTC_BASE_NS (0x4002C000u) | ||
| 13424 | /** Peripheral RTC base pointer */ | ||
| 13425 | #define RTC ((RTC_Type *)RTC_BASE) | ||
| 13426 | /** Peripheral RTC base pointer */ | ||
| 13427 | #define RTC_NS ((RTC_Type *)RTC_BASE_NS) | ||
| 13428 | /** Array initializer of RTC peripheral base addresses */ | ||
| 13429 | #define RTC_BASE_ADDRS { RTC_BASE } | ||
| 13430 | /** Array initializer of RTC peripheral base pointers */ | ||
| 13431 | #define RTC_BASE_PTRS { RTC } | ||
| 13432 | /** Array initializer of RTC peripheral base addresses */ | ||
| 13433 | #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } | ||
| 13434 | /** Array initializer of RTC peripheral base pointers */ | ||
| 13435 | #define RTC_BASE_PTRS_NS { RTC_NS } | ||
| 13436 | #else | ||
| 13437 | /** Peripheral RTC base address */ | ||
| 13438 | #define RTC_BASE (0x4002C000u) | ||
| 13439 | /** Peripheral RTC base pointer */ | ||
| 13440 | #define RTC ((RTC_Type *)RTC_BASE) | ||
| 13441 | /** Array initializer of RTC peripheral base addresses */ | ||
| 13442 | #define RTC_BASE_ADDRS { RTC_BASE } | ||
| 13443 | /** Array initializer of RTC peripheral base pointers */ | ||
| 13444 | #define RTC_BASE_PTRS { RTC } | ||
| 13445 | #endif | ||
| 13446 | /** Interrupt vectors for the RTC peripheral type */ | ||
| 13447 | #define RTC_IRQS { RTC_IRQn } | ||
| 13448 | |||
| 13449 | /*! | ||
| 13450 | * @} | ||
| 13451 | */ /* end of group RTC_Peripheral_Access_Layer */ | ||
| 13452 | |||
| 13453 | |||
| 13454 | /* ---------------------------------------------------------------------------- | ||
| 13455 | -- SCT Peripheral Access Layer | ||
| 13456 | ---------------------------------------------------------------------------- */ | ||
| 13457 | |||
| 13458 | /*! | ||
| 13459 | * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer | ||
| 13460 | * @{ | ||
| 13461 | */ | ||
| 13462 | |||
| 13463 | /** SCT - Register Layout Typedef */ | ||
| 13464 | typedef struct { | ||
| 13465 | __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ | ||
| 13466 | union { /* offset: 0x4 */ | ||
| 13467 | struct { /* offset: 0x4 */ | ||
| 13468 | __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ | ||
| 13469 | __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ | ||
| 13470 | } CTRL_ACCESS16BIT; | ||
| 13471 | __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ | ||
| 13472 | }; | ||
| 13473 | union { /* offset: 0x8 */ | ||
| 13474 | struct { /* offset: 0x8 */ | ||
| 13475 | __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ | ||
| 13476 | __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ | ||
| 13477 | } LIMIT_ACCESS16BIT; | ||
| 13478 | __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ | ||
| 13479 | }; | ||
| 13480 | union { /* offset: 0xC */ | ||
| 13481 | struct { /* offset: 0xC */ | ||
| 13482 | __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ | ||
| 13483 | __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ | ||
| 13484 | } HALT_ACCESS16BIT; | ||
| 13485 | __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ | ||
| 13486 | }; | ||
| 13487 | union { /* offset: 0x10 */ | ||
| 13488 | struct { /* offset: 0x10 */ | ||
| 13489 | __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ | ||
| 13490 | __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ | ||
| 13491 | } STOP_ACCESS16BIT; | ||
| 13492 | __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ | ||
| 13493 | }; | ||
| 13494 | union { /* offset: 0x14 */ | ||
| 13495 | struct { /* offset: 0x14 */ | ||
| 13496 | __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ | ||
| 13497 | __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ | ||
| 13498 | } START_ACCESS16BIT; | ||
| 13499 | __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ | ||
| 13500 | }; | ||
| 13501 | uint8_t RESERVED_0[40]; | ||
| 13502 | union { /* offset: 0x40 */ | ||
| 13503 | struct { /* offset: 0x40 */ | ||
| 13504 | __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ | ||
| 13505 | __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ | ||
| 13506 | } COUNT_ACCESS16BIT; | ||
| 13507 | __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ | ||
| 13508 | }; | ||
| 13509 | union { /* offset: 0x44 */ | ||
| 13510 | struct { /* offset: 0x44 */ | ||
| 13511 | __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ | ||
| 13512 | __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ | ||
| 13513 | } STATE_ACCESS16BIT; | ||
| 13514 | __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ | ||
| 13515 | }; | ||
| 13516 | __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ | ||
| 13517 | union { /* offset: 0x4C */ | ||
| 13518 | struct { /* offset: 0x4C */ | ||
| 13519 | __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ | ||
| 13520 | __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ | ||
| 13521 | } REGMODE_ACCESS16BIT; | ||
| 13522 | __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ | ||
| 13523 | }; | ||
| 13524 | __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ | ||
| 13525 | __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ | ||
| 13526 | __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ | ||
| 13527 | __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ | ||
| 13528 | __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ | ||
| 13529 | uint8_t RESERVED_1[140]; | ||
| 13530 | __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ | ||
| 13531 | __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ | ||
| 13532 | __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ | ||
| 13533 | __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ | ||
| 13534 | union { /* offset: 0x100 */ | ||
| 13535 | union { /* offset: 0x100, array step: 0x4 */ | ||
| 13536 | struct { /* offset: 0x100, array step: 0x4 */ | ||
| 13537 | __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ | ||
| 13538 | __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ | ||
| 13539 | } CAP_ACCESS16BIT[16]; | ||
| 13540 | __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ | ||
| 13541 | }; | ||
| 13542 | union { /* offset: 0x100, array step: 0x4 */ | ||
| 13543 | struct { /* offset: 0x100, array step: 0x4 */ | ||
| 13544 | __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ | ||
| 13545 | __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ | ||
| 13546 | } MATCH_ACCESS16BIT[16]; | ||
| 13547 | __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ | ||
| 13548 | }; | ||
| 13549 | }; | ||
| 13550 | uint8_t RESERVED_2[192]; | ||
| 13551 | union { /* offset: 0x200 */ | ||
| 13552 | union { /* offset: 0x200, array step: 0x4 */ | ||
| 13553 | struct { /* offset: 0x200, array step: 0x4 */ | ||
| 13554 | __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ | ||
| 13555 | __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ | ||
| 13556 | } CAPCTRL_ACCESS16BIT[16]; | ||
| 13557 | __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ | ||
| 13558 | }; | ||
| 13559 | union { /* offset: 0x200, array step: 0x4 */ | ||
| 13560 | struct { /* offset: 0x200, array step: 0x4 */ | ||
| 13561 | __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ | ||
| 13562 | __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ | ||
| 13563 | } MATCHREL_ACCESS16BIT[16]; | ||
| 13564 | __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ | ||
| 13565 | }; | ||
| 13566 | }; | ||
| 13567 | uint8_t RESERVED_3[192]; | ||
| 13568 | struct { /* offset: 0x300, array step: 0x8 */ | ||
| 13569 | __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ | ||
| 13570 | __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ | ||
| 13571 | } EV[16]; | ||
| 13572 | uint8_t RESERVED_4[384]; | ||
| 13573 | struct { /* offset: 0x500, array step: 0x8 */ | ||
| 13574 | __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ | ||
| 13575 | __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ | ||
| 13576 | } OUT[10]; | ||
| 13577 | } SCT_Type; | ||
| 13578 | |||
| 13579 | /* ---------------------------------------------------------------------------- | ||
| 13580 | -- SCT Register Masks | ||
| 13581 | ---------------------------------------------------------------------------- */ | ||
| 13582 | |||
| 13583 | /*! | ||
| 13584 | * @addtogroup SCT_Register_Masks SCT Register Masks | ||
| 13585 | * @{ | ||
| 13586 | */ | ||
| 13587 | |||
| 13588 | /*! @name CONFIG - SCT configuration register */ | ||
| 13589 | /*! @{ */ | ||
| 13590 | #define SCT_CONFIG_UNIFY_MASK (0x1U) | ||
| 13591 | #define SCT_CONFIG_UNIFY_SHIFT (0U) | ||
| 13592 | /*! UNIFY - SCT operation | ||
| 13593 | * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. | ||
| 13594 | * 0b1..The SCT operates as a unified 32-bit counter. | ||
| 13595 | */ | ||
| 13596 | #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) | ||
| 13597 | #define SCT_CONFIG_CLKMODE_MASK (0x6U) | ||
| 13598 | #define SCT_CONFIG_CLKMODE_SHIFT (1U) | ||
| 13599 | /*! CLKMODE - SCT clock mode | ||
| 13600 | * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. | ||
| 13601 | * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are | ||
| 13602 | * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The | ||
| 13603 | * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the | ||
| 13604 | * high-performance, sampled-clock mode. | ||
| 13605 | * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the | ||
| 13606 | * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the | ||
| 13607 | * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. | ||
| 13608 | * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL | ||
| 13609 | * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system | ||
| 13610 | * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than | ||
| 13611 | * the system clock. | ||
| 13612 | */ | ||
| 13613 | #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) | ||
| 13614 | #define SCT_CONFIG_CKSEL_MASK (0x78U) | ||
| 13615 | #define SCT_CONFIG_CKSEL_SHIFT (3U) | ||
| 13616 | /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent | ||
| 13617 | * on the CLKMODE bit selection in this register. | ||
| 13618 | * 0b0000..Rising edges on input 0. | ||
| 13619 | * 0b0001..Falling edges on input 0. | ||
| 13620 | * 0b0010..Rising edges on input 1. | ||
| 13621 | * 0b0011..Falling edges on input 1. | ||
| 13622 | * 0b0100..Rising edges on input 2. | ||
| 13623 | * 0b0101..Falling edges on input 2. | ||
| 13624 | * 0b0110..Rising edges on input 3. | ||
| 13625 | * 0b0111..Falling edges on input 3. | ||
| 13626 | * 0b1000..Rising edges on input 4. | ||
| 13627 | * 0b1001..Falling edges on input 4. | ||
| 13628 | * 0b1010..Rising edges on input 5. | ||
| 13629 | * 0b1011..Falling edges on input 5. | ||
| 13630 | * 0b1100..Rising edges on input 6. | ||
| 13631 | * 0b1101..Falling edges on input 6. | ||
| 13632 | * 0b1110..Rising edges on input 7. | ||
| 13633 | * 0b1111..Falling edges on input 7. | ||
| 13634 | */ | ||
| 13635 | #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) | ||
| 13636 | #define SCT_CONFIG_NORELOAD_L_MASK (0x80U) | ||
| 13637 | #define SCT_CONFIG_NORELOAD_L_SHIFT (7U) | ||
| 13638 | /*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their | ||
| 13639 | * respective reload registers. Setting this bit eliminates the need to write to the reload | ||
| 13640 | * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any | ||
| 13641 | * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. | ||
| 13642 | */ | ||
| 13643 | #define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) | ||
| 13644 | #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) | ||
| 13645 | #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) | ||
| 13646 | /*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their | ||
| 13647 | * respective reload registers. Setting this bit eliminates the need to write to the reload | ||
| 13648 | * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at | ||
| 13649 | * any time. This bit is not used when the UNIFY bit is set. | ||
| 13650 | */ | ||
| 13651 | #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) | ||
| 13652 | #define SCT_CONFIG_INSYNC_MASK (0x1E00U) | ||
| 13653 | #define SCT_CONFIG_INSYNC_SHIFT (9U) | ||
| 13654 | /*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all | ||
| 13655 | * other bits are reserved. A 1 in one of these bits subjects the corresponding input to | ||
| 13656 | * synchronization to the SCT clock, before it is used to create an event. If an input is known to | ||
| 13657 | * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: | ||
| 13658 | * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input | ||
| 13659 | * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. | ||
| 13660 | * It does not apply to the clock input specified in the CKSEL field. | ||
| 13661 | */ | ||
| 13662 | #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) | ||
| 13663 | #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) | ||
| 13664 | #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) | ||
| 13665 | /*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto | ||
| 13666 | * LIMIT condition without the need to define an associated event. As with any LIMIT event, this | ||
| 13667 | * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change | ||
| 13668 | * the direction of count in bi-directional mode. Software can write to set or clear this bit at | ||
| 13669 | * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. | ||
| 13670 | */ | ||
| 13671 | #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) | ||
| 13672 | #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) | ||
| 13673 | #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) | ||
| 13674 | /*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a | ||
| 13675 | * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, | ||
| 13676 | * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to | ||
| 13677 | * change the direction of count in bi-directional mode. Software can write to set or clear this bit | ||
| 13678 | * at any time. This bit is not used when the UNIFY bit is set. | ||
| 13679 | */ | ||
| 13680 | #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) | ||
| 13681 | /*! @} */ | ||
| 13682 | |||
| 13683 | /*! @name CTRLL - SCT_CTRLL register */ | ||
| 13684 | /*! @{ */ | ||
| 13685 | #define SCT_CTRLL_DOWN_L_MASK (0x1U) | ||
| 13686 | #define SCT_CTRLL_DOWN_L_SHIFT (0U) | ||
| 13687 | /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit | ||
| 13688 | * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit | ||
| 13689 | * when the counter is counting down and a limit condition occurs or when the counter reaches 0. | ||
| 13690 | */ | ||
| 13691 | #define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) | ||
| 13692 | #define SCT_CTRLL_STOP_L_MASK (0x2U) | ||
| 13693 | #define SCT_CTRLL_STOP_L_SHIFT (1U) | ||
| 13694 | /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events | ||
| 13695 | * related to the counter can occur. If a designated start event occurs, this bit is cleared and | ||
| 13696 | * counting resumes. | ||
| 13697 | */ | ||
| 13698 | #define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) | ||
| 13699 | #define SCT_CTRLL_HALT_L_MASK (0x4U) | ||
| 13700 | #define SCT_CTRLL_HALT_L_SHIFT (2U) | ||
| 13701 | /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A | ||
| 13702 | * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to | ||
| 13703 | * remove the halt condition while keeping the SCT in the stop condition (not running) with a | ||
| 13704 | * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, | ||
| 13705 | * only software can clear this bit to restore counter operation. This bit is set on reset. | ||
| 13706 | */ | ||
| 13707 | #define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) | ||
| 13708 | #define SCT_CTRLL_CLRCTR_L_MASK (0x8U) | ||
| 13709 | #define SCT_CTRLL_CLRCTR_L_SHIFT (3U) | ||
| 13710 | /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. | ||
| 13711 | */ | ||
| 13712 | #define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) | ||
| 13713 | #define SCT_CTRLL_BIDIR_L_MASK (0x10U) | ||
| 13714 | #define SCT_CTRLL_BIDIR_L_SHIFT (4U) | ||
| 13715 | /*! BIDIR_L - L or unified counter direction select | ||
| 13716 | * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. | ||
| 13717 | * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. | ||
| 13718 | */ | ||
| 13719 | #define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) | ||
| 13720 | #define SCT_CTRLL_PRE_L_MASK (0x1FE0U) | ||
| 13721 | #define SCT_CTRLL_PRE_L_SHIFT (5U) | ||
| 13722 | /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified | ||
| 13723 | * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. | ||
| 13724 | * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. | ||
| 13725 | */ | ||
| 13726 | #define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) | ||
| 13727 | /*! @} */ | ||
| 13728 | |||
| 13729 | /*! @name CTRLH - SCT_CTRLH register */ | ||
| 13730 | /*! @{ */ | ||
| 13731 | #define SCT_CTRLH_DOWN_H_MASK (0x1U) | ||
| 13732 | #define SCT_CTRLH_DOWN_H_SHIFT (0U) | ||
| 13733 | /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the | ||
| 13734 | * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit | ||
| 13735 | * when the counter is counting down and a limit condition occurs or when the counter reaches 0. | ||
| 13736 | */ | ||
| 13737 | #define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) | ||
| 13738 | #define SCT_CTRLH_STOP_H_MASK (0x2U) | ||
| 13739 | #define SCT_CTRLH_STOP_H_SHIFT (1U) | ||
| 13740 | /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to | ||
| 13741 | * the counter can occur. If such an event matches the mask in the Start register, this bit is | ||
| 13742 | * cleared and counting resumes. | ||
| 13743 | */ | ||
| 13744 | #define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) | ||
| 13745 | #define SCT_CTRLH_HALT_H_MASK (0x4U) | ||
| 13746 | #define SCT_CTRLH_HALT_H_SHIFT (2U) | ||
| 13747 | /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets | ||
| 13748 | * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the | ||
| 13749 | * halt condition while keeping the SCT in the stop condition (not running) with a single write to | ||
| 13750 | * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit | ||
| 13751 | * can only be cleared by software to restore counter operation. This bit is set on reset. | ||
| 13752 | */ | ||
| 13753 | #define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) | ||
| 13754 | #define SCT_CTRLH_CLRCTR_H_MASK (0x8U) | ||
| 13755 | #define SCT_CTRLH_CLRCTR_H_SHIFT (3U) | ||
| 13756 | /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. | ||
| 13757 | */ | ||
| 13758 | #define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) | ||
| 13759 | #define SCT_CTRLH_BIDIR_H_MASK (0x10U) | ||
| 13760 | #define SCT_CTRLH_BIDIR_H_SHIFT (4U) | ||
| 13761 | /*! BIDIR_H - Direction select | ||
| 13762 | * 0b0..The H counter counts up to its limit condition, then is cleared to zero. | ||
| 13763 | * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. | ||
| 13764 | */ | ||
| 13765 | #define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) | ||
| 13766 | #define SCT_CTRLH_PRE_H_MASK (0x1FE0U) | ||
| 13767 | #define SCT_CTRLH_PRE_H_SHIFT (5U) | ||
| 13768 | /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. | ||
| 13769 | * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the | ||
| 13770 | * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. | ||
| 13771 | */ | ||
| 13772 | #define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) | ||
| 13773 | /*! @} */ | ||
| 13774 | |||
| 13775 | /*! @name CTRL - SCT control register */ | ||
| 13776 | /*! @{ */ | ||
| 13777 | #define SCT_CTRL_DOWN_L_MASK (0x1U) | ||
| 13778 | #define SCT_CTRL_DOWN_L_SHIFT (0U) | ||
| 13779 | /*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit | ||
| 13780 | * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit | ||
| 13781 | * when the counter is counting down and a limit condition occurs or when the counter reaches 0. | ||
| 13782 | */ | ||
| 13783 | #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) | ||
| 13784 | #define SCT_CTRL_STOP_L_MASK (0x2U) | ||
| 13785 | #define SCT_CTRL_STOP_L_SHIFT (1U) | ||
| 13786 | /*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events | ||
| 13787 | * related to the counter can occur. If a designated start event occurs, this bit is cleared and | ||
| 13788 | * counting resumes. | ||
| 13789 | */ | ||
| 13790 | #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) | ||
| 13791 | #define SCT_CTRL_HALT_L_MASK (0x4U) | ||
| 13792 | #define SCT_CTRL_HALT_L_SHIFT (2U) | ||
| 13793 | /*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A | ||
| 13794 | * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to | ||
| 13795 | * remove the halt condition while keeping the SCT in the stop condition (not running) with a | ||
| 13796 | * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, | ||
| 13797 | * only software can clear this bit to restore counter operation. This bit is set on reset. | ||
| 13798 | */ | ||
| 13799 | #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) | ||
| 13800 | #define SCT_CTRL_CLRCTR_L_MASK (0x8U) | ||
| 13801 | #define SCT_CTRL_CLRCTR_L_SHIFT (3U) | ||
| 13802 | /*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. | ||
| 13803 | */ | ||
| 13804 | #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) | ||
| 13805 | #define SCT_CTRL_BIDIR_L_MASK (0x10U) | ||
| 13806 | #define SCT_CTRL_BIDIR_L_SHIFT (4U) | ||
| 13807 | /*! BIDIR_L - L or unified counter direction select | ||
| 13808 | * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. | ||
| 13809 | * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. | ||
| 13810 | */ | ||
| 13811 | #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) | ||
| 13812 | #define SCT_CTRL_PRE_L_MASK (0x1FE0U) | ||
| 13813 | #define SCT_CTRL_PRE_L_SHIFT (5U) | ||
| 13814 | /*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified | ||
| 13815 | * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. | ||
| 13816 | * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. | ||
| 13817 | */ | ||
| 13818 | #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) | ||
| 13819 | #define SCT_CTRL_DOWN_H_MASK (0x10000U) | ||
| 13820 | #define SCT_CTRL_DOWN_H_SHIFT (16U) | ||
| 13821 | /*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the | ||
| 13822 | * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit | ||
| 13823 | * when the counter is counting down and a limit condition occurs or when the counter reaches 0. | ||
| 13824 | */ | ||
| 13825 | #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) | ||
| 13826 | #define SCT_CTRL_STOP_H_MASK (0x20000U) | ||
| 13827 | #define SCT_CTRL_STOP_H_SHIFT (17U) | ||
| 13828 | /*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to | ||
| 13829 | * the counter can occur. If such an event matches the mask in the Start register, this bit is | ||
| 13830 | * cleared and counting resumes. | ||
| 13831 | */ | ||
| 13832 | #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) | ||
| 13833 | #define SCT_CTRL_HALT_H_MASK (0x40000U) | ||
| 13834 | #define SCT_CTRL_HALT_H_SHIFT (18U) | ||
| 13835 | /*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets | ||
| 13836 | * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the | ||
| 13837 | * halt condition while keeping the SCT in the stop condition (not running) with a single write to | ||
| 13838 | * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit | ||
| 13839 | * can only be cleared by software to restore counter operation. This bit is set on reset. | ||
| 13840 | */ | ||
| 13841 | #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) | ||
| 13842 | #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) | ||
| 13843 | #define SCT_CTRL_CLRCTR_H_SHIFT (19U) | ||
| 13844 | /*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. | ||
| 13845 | */ | ||
| 13846 | #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) | ||
| 13847 | #define SCT_CTRL_BIDIR_H_MASK (0x100000U) | ||
| 13848 | #define SCT_CTRL_BIDIR_H_SHIFT (20U) | ||
| 13849 | /*! BIDIR_H - Direction select | ||
| 13850 | * 0b0..The H counter counts up to its limit condition, then is cleared to zero. | ||
| 13851 | * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. | ||
| 13852 | */ | ||
| 13853 | #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) | ||
| 13854 | #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) | ||
| 13855 | #define SCT_CTRL_PRE_H_SHIFT (21U) | ||
| 13856 | /*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. | ||
| 13857 | * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the | ||
| 13858 | * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. | ||
| 13859 | */ | ||
| 13860 | #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) | ||
| 13861 | /*! @} */ | ||
| 13862 | |||
| 13863 | /*! @name LIMITL - SCT_LIMITL register */ | ||
| 13864 | /*! @{ */ | ||
| 13865 | #define SCT_LIMITL_LIMITL_MASK (0xFFFFU) | ||
| 13866 | #define SCT_LIMITL_LIMITL_SHIFT (0U) | ||
| 13867 | #define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) | ||
| 13868 | /*! @} */ | ||
| 13869 | |||
| 13870 | /*! @name LIMITH - SCT_LIMITH register */ | ||
| 13871 | /*! @{ */ | ||
| 13872 | #define SCT_LIMITH_LIMITH_MASK (0xFFFFU) | ||
| 13873 | #define SCT_LIMITH_LIMITH_SHIFT (0U) | ||
| 13874 | #define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) | ||
| 13875 | /*! @} */ | ||
| 13876 | |||
| 13877 | /*! @name LIMIT - SCT limit event select register */ | ||
| 13878 | /*! @{ */ | ||
| 13879 | #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) | ||
| 13880 | #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) | ||
| 13881 | /*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter | ||
| 13882 | * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. | ||
| 13883 | */ | ||
| 13884 | #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) | ||
| 13885 | #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) | ||
| 13886 | #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) | ||
| 13887 | /*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit | ||
| 13888 | * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. | ||
| 13889 | */ | ||
| 13890 | #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) | ||
| 13891 | /*! @} */ | ||
| 13892 | |||
| 13893 | /*! @name HALTL - SCT_HALTL register */ | ||
| 13894 | /*! @{ */ | ||
| 13895 | #define SCT_HALTL_HALTL_MASK (0xFFFFU) | ||
| 13896 | #define SCT_HALTL_HALTL_SHIFT (0U) | ||
| 13897 | #define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) | ||
| 13898 | /*! @} */ | ||
| 13899 | |||
| 13900 | /*! @name HALTH - SCT_HALTH register */ | ||
| 13901 | /*! @{ */ | ||
| 13902 | #define SCT_HALTH_HALTH_MASK (0xFFFFU) | ||
| 13903 | #define SCT_HALTH_HALTH_SHIFT (0U) | ||
| 13904 | #define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) | ||
| 13905 | /*! @} */ | ||
| 13906 | |||
| 13907 | /*! @name HALT - SCT halt event select register */ | ||
| 13908 | /*! @{ */ | ||
| 13909 | #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) | ||
| 13910 | #define SCT_HALT_HALTMSK_L_SHIFT (0U) | ||
| 13911 | /*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, | ||
| 13912 | * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. | ||
| 13913 | */ | ||
| 13914 | #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) | ||
| 13915 | #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) | ||
| 13916 | #define SCT_HALT_HALTMSK_H_SHIFT (16U) | ||
| 13917 | /*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, | ||
| 13918 | * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. | ||
| 13919 | */ | ||
| 13920 | #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) | ||
| 13921 | /*! @} */ | ||
| 13922 | |||
| 13923 | /*! @name STOPL - SCT_STOPL register */ | ||
| 13924 | /*! @{ */ | ||
| 13925 | #define SCT_STOPL_STOPL_MASK (0xFFFFU) | ||
| 13926 | #define SCT_STOPL_STOPL_SHIFT (0U) | ||
| 13927 | #define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) | ||
| 13928 | /*! @} */ | ||
| 13929 | |||
| 13930 | /*! @name STOPH - SCT_STOPH register */ | ||
| 13931 | /*! @{ */ | ||
| 13932 | #define SCT_STOPH_STOPH_MASK (0xFFFFU) | ||
| 13933 | #define SCT_STOPH_STOPH_SHIFT (0U) | ||
| 13934 | #define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) | ||
| 13935 | /*! @} */ | ||
| 13936 | |||
| 13937 | /*! @name STOP - SCT stop event select register */ | ||
| 13938 | /*! @{ */ | ||
| 13939 | #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) | ||
| 13940 | #define SCT_STOP_STOPMSK_L_SHIFT (0U) | ||
| 13941 | /*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, | ||
| 13942 | * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. | ||
| 13943 | */ | ||
| 13944 | #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) | ||
| 13945 | #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) | ||
| 13946 | #define SCT_STOP_STOPMSK_H_SHIFT (16U) | ||
| 13947 | /*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, | ||
| 13948 | * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. | ||
| 13949 | */ | ||
| 13950 | #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) | ||
| 13951 | /*! @} */ | ||
| 13952 | |||
| 13953 | /*! @name STARTL - SCT_STARTL register */ | ||
| 13954 | /*! @{ */ | ||
| 13955 | #define SCT_STARTL_STARTL_MASK (0xFFFFU) | ||
| 13956 | #define SCT_STARTL_STARTL_SHIFT (0U) | ||
| 13957 | #define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) | ||
| 13958 | /*! @} */ | ||
| 13959 | |||
| 13960 | /*! @name STARTH - SCT_STARTH register */ | ||
| 13961 | /*! @{ */ | ||
| 13962 | #define SCT_STARTH_STARTH_MASK (0xFFFFU) | ||
| 13963 | #define SCT_STARTH_STARTH_SHIFT (0U) | ||
| 13964 | #define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) | ||
| 13965 | /*! @} */ | ||
| 13966 | |||
| 13967 | /*! @name START - SCT start event select register */ | ||
| 13968 | /*! @{ */ | ||
| 13969 | #define SCT_START_STARTMSK_L_MASK (0xFFFFU) | ||
| 13970 | #define SCT_START_STARTMSK_L_SHIFT (0U) | ||
| 13971 | /*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit | ||
| 13972 | * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. | ||
| 13973 | */ | ||
| 13974 | #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) | ||
| 13975 | #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) | ||
| 13976 | #define SCT_START_STARTMSK_H_SHIFT (16U) | ||
| 13977 | /*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit | ||
| 13978 | * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. | ||
| 13979 | */ | ||
| 13980 | #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) | ||
| 13981 | /*! @} */ | ||
| 13982 | |||
| 13983 | /*! @name COUNTL - SCT_COUNTL register */ | ||
| 13984 | /*! @{ */ | ||
| 13985 | #define SCT_COUNTL_COUNTL_MASK (0xFFFFU) | ||
| 13986 | #define SCT_COUNTL_COUNTL_SHIFT (0U) | ||
| 13987 | #define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) | ||
| 13988 | /*! @} */ | ||
| 13989 | |||
| 13990 | /*! @name COUNTH - SCT_COUNTH register */ | ||
| 13991 | /*! @{ */ | ||
| 13992 | #define SCT_COUNTH_COUNTH_MASK (0xFFFFU) | ||
| 13993 | #define SCT_COUNTH_COUNTH_SHIFT (0U) | ||
| 13994 | #define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) | ||
| 13995 | /*! @} */ | ||
| 13996 | |||
| 13997 | /*! @name COUNT - SCT counter register */ | ||
| 13998 | /*! @{ */ | ||
| 13999 | #define SCT_COUNT_CTR_L_MASK (0xFFFFU) | ||
| 14000 | #define SCT_COUNT_CTR_L_SHIFT (0U) | ||
| 14001 | /*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write | ||
| 14002 | * the lower 16 bits of the 32-bit unified counter. | ||
| 14003 | */ | ||
| 14004 | #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) | ||
| 14005 | #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) | ||
| 14006 | #define SCT_COUNT_CTR_H_SHIFT (16U) | ||
| 14007 | /*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write | ||
| 14008 | * the upper 16 bits of the 32-bit unified counter. | ||
| 14009 | */ | ||
| 14010 | #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) | ||
| 14011 | /*! @} */ | ||
| 14012 | |||
| 14013 | /*! @name STATEL - SCT_STATEL register */ | ||
| 14014 | /*! @{ */ | ||
| 14015 | #define SCT_STATEL_STATEL_MASK (0xFFFFU) | ||
| 14016 | #define SCT_STATEL_STATEL_SHIFT (0U) | ||
| 14017 | #define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) | ||
| 14018 | /*! @} */ | ||
| 14019 | |||
| 14020 | /*! @name STATEH - SCT_STATEH register */ | ||
| 14021 | /*! @{ */ | ||
| 14022 | #define SCT_STATEH_STATEH_MASK (0xFFFFU) | ||
| 14023 | #define SCT_STATEH_STATEH_SHIFT (0U) | ||
| 14024 | #define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) | ||
| 14025 | /*! @} */ | ||
| 14026 | |||
| 14027 | /*! @name STATE - SCT state register */ | ||
| 14028 | /*! @{ */ | ||
| 14029 | #define SCT_STATE_STATE_L_MASK (0x1FU) | ||
| 14030 | #define SCT_STATE_STATE_L_SHIFT (0U) | ||
| 14031 | /*! STATE_L - State variable. | ||
| 14032 | */ | ||
| 14033 | #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) | ||
| 14034 | #define SCT_STATE_STATE_H_MASK (0x1F0000U) | ||
| 14035 | #define SCT_STATE_STATE_H_SHIFT (16U) | ||
| 14036 | /*! STATE_H - State variable. | ||
| 14037 | */ | ||
| 14038 | #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) | ||
| 14039 | /*! @} */ | ||
| 14040 | |||
| 14041 | /*! @name INPUT - SCT input register */ | ||
| 14042 | /*! @{ */ | ||
| 14043 | #define SCT_INPUT_AIN0_MASK (0x1U) | ||
| 14044 | #define SCT_INPUT_AIN0_SHIFT (0U) | ||
| 14045 | /*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. | ||
| 14046 | */ | ||
| 14047 | #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) | ||
| 14048 | #define SCT_INPUT_AIN1_MASK (0x2U) | ||
| 14049 | #define SCT_INPUT_AIN1_SHIFT (1U) | ||
| 14050 | /*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. | ||
| 14051 | */ | ||
| 14052 | #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) | ||
| 14053 | #define SCT_INPUT_AIN2_MASK (0x4U) | ||
| 14054 | #define SCT_INPUT_AIN2_SHIFT (2U) | ||
| 14055 | /*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. | ||
| 14056 | */ | ||
| 14057 | #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) | ||
| 14058 | #define SCT_INPUT_AIN3_MASK (0x8U) | ||
| 14059 | #define SCT_INPUT_AIN3_SHIFT (3U) | ||
| 14060 | /*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. | ||
| 14061 | */ | ||
| 14062 | #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) | ||
| 14063 | #define SCT_INPUT_AIN4_MASK (0x10U) | ||
| 14064 | #define SCT_INPUT_AIN4_SHIFT (4U) | ||
| 14065 | /*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. | ||
| 14066 | */ | ||
| 14067 | #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) | ||
| 14068 | #define SCT_INPUT_AIN5_MASK (0x20U) | ||
| 14069 | #define SCT_INPUT_AIN5_SHIFT (5U) | ||
| 14070 | /*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. | ||
| 14071 | */ | ||
| 14072 | #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) | ||
| 14073 | #define SCT_INPUT_AIN6_MASK (0x40U) | ||
| 14074 | #define SCT_INPUT_AIN6_SHIFT (6U) | ||
| 14075 | /*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. | ||
| 14076 | */ | ||
| 14077 | #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) | ||
| 14078 | #define SCT_INPUT_AIN7_MASK (0x80U) | ||
| 14079 | #define SCT_INPUT_AIN7_SHIFT (7U) | ||
| 14080 | /*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. | ||
| 14081 | */ | ||
| 14082 | #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) | ||
| 14083 | #define SCT_INPUT_AIN8_MASK (0x100U) | ||
| 14084 | #define SCT_INPUT_AIN8_SHIFT (8U) | ||
| 14085 | /*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. | ||
| 14086 | */ | ||
| 14087 | #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) | ||
| 14088 | #define SCT_INPUT_AIN9_MASK (0x200U) | ||
| 14089 | #define SCT_INPUT_AIN9_SHIFT (9U) | ||
| 14090 | /*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. | ||
| 14091 | */ | ||
| 14092 | #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) | ||
| 14093 | #define SCT_INPUT_AIN10_MASK (0x400U) | ||
| 14094 | #define SCT_INPUT_AIN10_SHIFT (10U) | ||
| 14095 | /*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. | ||
| 14096 | */ | ||
| 14097 | #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) | ||
| 14098 | #define SCT_INPUT_AIN11_MASK (0x800U) | ||
| 14099 | #define SCT_INPUT_AIN11_SHIFT (11U) | ||
| 14100 | /*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. | ||
| 14101 | */ | ||
| 14102 | #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) | ||
| 14103 | #define SCT_INPUT_AIN12_MASK (0x1000U) | ||
| 14104 | #define SCT_INPUT_AIN12_SHIFT (12U) | ||
| 14105 | /*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. | ||
| 14106 | */ | ||
| 14107 | #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) | ||
| 14108 | #define SCT_INPUT_AIN13_MASK (0x2000U) | ||
| 14109 | #define SCT_INPUT_AIN13_SHIFT (13U) | ||
| 14110 | /*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. | ||
| 14111 | */ | ||
| 14112 | #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) | ||
| 14113 | #define SCT_INPUT_AIN14_MASK (0x4000U) | ||
| 14114 | #define SCT_INPUT_AIN14_SHIFT (14U) | ||
| 14115 | /*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. | ||
| 14116 | */ | ||
| 14117 | #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) | ||
| 14118 | #define SCT_INPUT_AIN15_MASK (0x8000U) | ||
| 14119 | #define SCT_INPUT_AIN15_SHIFT (15U) | ||
| 14120 | /*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. | ||
| 14121 | */ | ||
| 14122 | #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) | ||
| 14123 | #define SCT_INPUT_SIN0_MASK (0x10000U) | ||
| 14124 | #define SCT_INPUT_SIN0_SHIFT (16U) | ||
| 14125 | /*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. | ||
| 14126 | */ | ||
| 14127 | #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) | ||
| 14128 | #define SCT_INPUT_SIN1_MASK (0x20000U) | ||
| 14129 | #define SCT_INPUT_SIN1_SHIFT (17U) | ||
| 14130 | /*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. | ||
| 14131 | */ | ||
| 14132 | #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) | ||
| 14133 | #define SCT_INPUT_SIN2_MASK (0x40000U) | ||
| 14134 | #define SCT_INPUT_SIN2_SHIFT (18U) | ||
| 14135 | /*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. | ||
| 14136 | */ | ||
| 14137 | #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) | ||
| 14138 | #define SCT_INPUT_SIN3_MASK (0x80000U) | ||
| 14139 | #define SCT_INPUT_SIN3_SHIFT (19U) | ||
| 14140 | /*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. | ||
| 14141 | */ | ||
| 14142 | #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) | ||
| 14143 | #define SCT_INPUT_SIN4_MASK (0x100000U) | ||
| 14144 | #define SCT_INPUT_SIN4_SHIFT (20U) | ||
| 14145 | /*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. | ||
| 14146 | */ | ||
| 14147 | #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) | ||
| 14148 | #define SCT_INPUT_SIN5_MASK (0x200000U) | ||
| 14149 | #define SCT_INPUT_SIN5_SHIFT (21U) | ||
| 14150 | /*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. | ||
| 14151 | */ | ||
| 14152 | #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) | ||
| 14153 | #define SCT_INPUT_SIN6_MASK (0x400000U) | ||
| 14154 | #define SCT_INPUT_SIN6_SHIFT (22U) | ||
| 14155 | /*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. | ||
| 14156 | */ | ||
| 14157 | #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) | ||
| 14158 | #define SCT_INPUT_SIN7_MASK (0x800000U) | ||
| 14159 | #define SCT_INPUT_SIN7_SHIFT (23U) | ||
| 14160 | /*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. | ||
| 14161 | */ | ||
| 14162 | #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) | ||
| 14163 | #define SCT_INPUT_SIN8_MASK (0x1000000U) | ||
| 14164 | #define SCT_INPUT_SIN8_SHIFT (24U) | ||
| 14165 | /*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. | ||
| 14166 | */ | ||
| 14167 | #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) | ||
| 14168 | #define SCT_INPUT_SIN9_MASK (0x2000000U) | ||
| 14169 | #define SCT_INPUT_SIN9_SHIFT (25U) | ||
| 14170 | /*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. | ||
| 14171 | */ | ||
| 14172 | #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) | ||
| 14173 | #define SCT_INPUT_SIN10_MASK (0x4000000U) | ||
| 14174 | #define SCT_INPUT_SIN10_SHIFT (26U) | ||
| 14175 | /*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. | ||
| 14176 | */ | ||
| 14177 | #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) | ||
| 14178 | #define SCT_INPUT_SIN11_MASK (0x8000000U) | ||
| 14179 | #define SCT_INPUT_SIN11_SHIFT (27U) | ||
| 14180 | /*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. | ||
| 14181 | */ | ||
| 14182 | #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) | ||
| 14183 | #define SCT_INPUT_SIN12_MASK (0x10000000U) | ||
| 14184 | #define SCT_INPUT_SIN12_SHIFT (28U) | ||
| 14185 | /*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. | ||
| 14186 | */ | ||
| 14187 | #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) | ||
| 14188 | #define SCT_INPUT_SIN13_MASK (0x20000000U) | ||
| 14189 | #define SCT_INPUT_SIN13_SHIFT (29U) | ||
| 14190 | /*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. | ||
| 14191 | */ | ||
| 14192 | #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) | ||
| 14193 | #define SCT_INPUT_SIN14_MASK (0x40000000U) | ||
| 14194 | #define SCT_INPUT_SIN14_SHIFT (30U) | ||
| 14195 | /*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. | ||
| 14196 | */ | ||
| 14197 | #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) | ||
| 14198 | #define SCT_INPUT_SIN15_MASK (0x80000000U) | ||
| 14199 | #define SCT_INPUT_SIN15_SHIFT (31U) | ||
| 14200 | /*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. | ||
| 14201 | */ | ||
| 14202 | #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) | ||
| 14203 | /*! @} */ | ||
| 14204 | |||
| 14205 | /*! @name REGMODEL - SCT_REGMODEL register */ | ||
| 14206 | /*! @{ */ | ||
| 14207 | #define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) | ||
| 14208 | #define SCT_REGMODEL_REGMODEL_SHIFT (0U) | ||
| 14209 | #define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) | ||
| 14210 | /*! @} */ | ||
| 14211 | |||
| 14212 | /*! @name REGMODEH - SCT_REGMODEH register */ | ||
| 14213 | /*! @{ */ | ||
| 14214 | #define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) | ||
| 14215 | #define SCT_REGMODEH_REGMODEH_SHIFT (0U) | ||
| 14216 | #define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) | ||
| 14217 | /*! @} */ | ||
| 14218 | |||
| 14219 | /*! @name REGMODE - SCT match/capture mode register */ | ||
| 14220 | /*! @{ */ | ||
| 14221 | #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) | ||
| 14222 | #define SCT_REGMODE_REGMOD_L_SHIFT (0U) | ||
| 14223 | /*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, | ||
| 14224 | * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as | ||
| 14225 | * match register. 1 = register operates as capture register. | ||
| 14226 | */ | ||
| 14227 | #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) | ||
| 14228 | #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) | ||
| 14229 | #define SCT_REGMODE_REGMOD_H_SHIFT (16U) | ||
| 14230 | /*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit | ||
| 14231 | * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as | ||
| 14232 | * match registers. 1 = register operates as capture registers. | ||
| 14233 | */ | ||
| 14234 | #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) | ||
| 14235 | /*! @} */ | ||
| 14236 | |||
| 14237 | /*! @name OUTPUT - SCT output register */ | ||
| 14238 | /*! @{ */ | ||
| 14239 | #define SCT_OUTPUT_OUT_MASK (0xFFFFU) | ||
| 14240 | #define SCT_OUTPUT_OUT_SHIFT (0U) | ||
| 14241 | /*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the | ||
| 14242 | * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of | ||
| 14243 | * outputs in this SCT. | ||
| 14244 | */ | ||
| 14245 | #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) | ||
| 14246 | /*! @} */ | ||
| 14247 | |||
| 14248 | /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ | ||
| 14249 | /*! @{ */ | ||
| 14250 | #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) | ||
| 14251 | #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) | ||
| 14252 | /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. | ||
| 14253 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14254 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14255 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14256 | */ | ||
| 14257 | #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) | ||
| 14258 | #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) | ||
| 14259 | #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) | ||
| 14260 | /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. | ||
| 14261 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14262 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14263 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14264 | */ | ||
| 14265 | #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) | ||
| 14266 | #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) | ||
| 14267 | #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) | ||
| 14268 | /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. | ||
| 14269 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14270 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14271 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14272 | */ | ||
| 14273 | #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) | ||
| 14274 | #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) | ||
| 14275 | #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) | ||
| 14276 | /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. | ||
| 14277 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14278 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14279 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14280 | */ | ||
| 14281 | #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) | ||
| 14282 | #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) | ||
| 14283 | #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) | ||
| 14284 | /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. | ||
| 14285 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14286 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14287 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14288 | */ | ||
| 14289 | #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) | ||
| 14290 | #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) | ||
| 14291 | #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) | ||
| 14292 | /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. | ||
| 14293 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14294 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14295 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14296 | */ | ||
| 14297 | #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) | ||
| 14298 | #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) | ||
| 14299 | #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) | ||
| 14300 | /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. | ||
| 14301 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14302 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14303 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14304 | */ | ||
| 14305 | #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) | ||
| 14306 | #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) | ||
| 14307 | #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) | ||
| 14308 | /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. | ||
| 14309 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14310 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14311 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14312 | */ | ||
| 14313 | #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) | ||
| 14314 | #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) | ||
| 14315 | #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) | ||
| 14316 | /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. | ||
| 14317 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14318 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14319 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14320 | */ | ||
| 14321 | #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) | ||
| 14322 | #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) | ||
| 14323 | #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) | ||
| 14324 | /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. | ||
| 14325 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14326 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14327 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14328 | */ | ||
| 14329 | #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) | ||
| 14330 | #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) | ||
| 14331 | #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) | ||
| 14332 | /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. | ||
| 14333 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14334 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14335 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14336 | */ | ||
| 14337 | #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) | ||
| 14338 | #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) | ||
| 14339 | #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) | ||
| 14340 | /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. | ||
| 14341 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14342 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14343 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14344 | */ | ||
| 14345 | #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) | ||
| 14346 | #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) | ||
| 14347 | #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) | ||
| 14348 | /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. | ||
| 14349 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14350 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14351 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14352 | */ | ||
| 14353 | #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) | ||
| 14354 | #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) | ||
| 14355 | #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) | ||
| 14356 | /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. | ||
| 14357 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14358 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14359 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14360 | */ | ||
| 14361 | #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) | ||
| 14362 | #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) | ||
| 14363 | #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) | ||
| 14364 | /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. | ||
| 14365 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14366 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14367 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14368 | */ | ||
| 14369 | #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) | ||
| 14370 | #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) | ||
| 14371 | #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) | ||
| 14372 | /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. | ||
| 14373 | * 0b00..Set and clear do not depend on the direction of any counter. | ||
| 14374 | * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. | ||
| 14375 | * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. | ||
| 14376 | */ | ||
| 14377 | #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) | ||
| 14378 | /*! @} */ | ||
| 14379 | |||
| 14380 | /*! @name RES - SCT conflict resolution register */ | ||
| 14381 | /*! @{ */ | ||
| 14382 | #define SCT_RES_O0RES_MASK (0x3U) | ||
| 14383 | #define SCT_RES_O0RES_SHIFT (0U) | ||
| 14384 | /*! O0RES - Effect of simultaneous set and clear on output 0. | ||
| 14385 | * 0b00..No change. | ||
| 14386 | * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). | ||
| 14387 | * 0b10..Clear output (or set based on the SETCLR0 field). | ||
| 14388 | * 0b11..Toggle output. | ||
| 14389 | */ | ||
| 14390 | #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) | ||
| 14391 | #define SCT_RES_O1RES_MASK (0xCU) | ||
| 14392 | #define SCT_RES_O1RES_SHIFT (2U) | ||
| 14393 | /*! O1RES - Effect of simultaneous set and clear on output 1. | ||
| 14394 | * 0b00..No change. | ||
| 14395 | * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). | ||
| 14396 | * 0b10..Clear output (or set based on the SETCLR1 field). | ||
| 14397 | * 0b11..Toggle output. | ||
| 14398 | */ | ||
| 14399 | #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) | ||
| 14400 | #define SCT_RES_O2RES_MASK (0x30U) | ||
| 14401 | #define SCT_RES_O2RES_SHIFT (4U) | ||
| 14402 | /*! O2RES - Effect of simultaneous set and clear on output 2. | ||
| 14403 | * 0b00..No change. | ||
| 14404 | * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). | ||
| 14405 | * 0b10..Clear output n (or set based on the SETCLR2 field). | ||
| 14406 | * 0b11..Toggle output. | ||
| 14407 | */ | ||
| 14408 | #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) | ||
| 14409 | #define SCT_RES_O3RES_MASK (0xC0U) | ||
| 14410 | #define SCT_RES_O3RES_SHIFT (6U) | ||
| 14411 | /*! O3RES - Effect of simultaneous set and clear on output 3. | ||
| 14412 | * 0b00..No change. | ||
| 14413 | * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). | ||
| 14414 | * 0b10..Clear output (or set based on the SETCLR3 field). | ||
| 14415 | * 0b11..Toggle output. | ||
| 14416 | */ | ||
| 14417 | #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) | ||
| 14418 | #define SCT_RES_O4RES_MASK (0x300U) | ||
| 14419 | #define SCT_RES_O4RES_SHIFT (8U) | ||
| 14420 | /*! O4RES - Effect of simultaneous set and clear on output 4. | ||
| 14421 | * 0b00..No change. | ||
| 14422 | * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). | ||
| 14423 | * 0b10..Clear output (or set based on the SETCLR4 field). | ||
| 14424 | * 0b11..Toggle output. | ||
| 14425 | */ | ||
| 14426 | #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) | ||
| 14427 | #define SCT_RES_O5RES_MASK (0xC00U) | ||
| 14428 | #define SCT_RES_O5RES_SHIFT (10U) | ||
| 14429 | /*! O5RES - Effect of simultaneous set and clear on output 5. | ||
| 14430 | * 0b00..No change. | ||
| 14431 | * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). | ||
| 14432 | * 0b10..Clear output (or set based on the SETCLR5 field). | ||
| 14433 | * 0b11..Toggle output. | ||
| 14434 | */ | ||
| 14435 | #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) | ||
| 14436 | #define SCT_RES_O6RES_MASK (0x3000U) | ||
| 14437 | #define SCT_RES_O6RES_SHIFT (12U) | ||
| 14438 | /*! O6RES - Effect of simultaneous set and clear on output 6. | ||
| 14439 | * 0b00..No change. | ||
| 14440 | * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). | ||
| 14441 | * 0b10..Clear output (or set based on the SETCLR6 field). | ||
| 14442 | * 0b11..Toggle output. | ||
| 14443 | */ | ||
| 14444 | #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) | ||
| 14445 | #define SCT_RES_O7RES_MASK (0xC000U) | ||
| 14446 | #define SCT_RES_O7RES_SHIFT (14U) | ||
| 14447 | /*! O7RES - Effect of simultaneous set and clear on output 7. | ||
| 14448 | * 0b00..No change. | ||
| 14449 | * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). | ||
| 14450 | * 0b10..Clear output n (or set based on the SETCLR7 field). | ||
| 14451 | * 0b11..Toggle output. | ||
| 14452 | */ | ||
| 14453 | #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) | ||
| 14454 | #define SCT_RES_O8RES_MASK (0x30000U) | ||
| 14455 | #define SCT_RES_O8RES_SHIFT (16U) | ||
| 14456 | /*! O8RES - Effect of simultaneous set and clear on output 8. | ||
| 14457 | * 0b00..No change. | ||
| 14458 | * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). | ||
| 14459 | * 0b10..Clear output (or set based on the SETCLR8 field). | ||
| 14460 | * 0b11..Toggle output. | ||
| 14461 | */ | ||
| 14462 | #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) | ||
| 14463 | #define SCT_RES_O9RES_MASK (0xC0000U) | ||
| 14464 | #define SCT_RES_O9RES_SHIFT (18U) | ||
| 14465 | /*! O9RES - Effect of simultaneous set and clear on output 9. | ||
| 14466 | * 0b00..No change. | ||
| 14467 | * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). | ||
| 14468 | * 0b10..Clear output (or set based on the SETCLR9 field). | ||
| 14469 | * 0b11..Toggle output. | ||
| 14470 | */ | ||
| 14471 | #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) | ||
| 14472 | #define SCT_RES_O10RES_MASK (0x300000U) | ||
| 14473 | #define SCT_RES_O10RES_SHIFT (20U) | ||
| 14474 | /*! O10RES - Effect of simultaneous set and clear on output 10. | ||
| 14475 | * 0b00..No change. | ||
| 14476 | * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). | ||
| 14477 | * 0b10..Clear output (or set based on the SETCLR10 field). | ||
| 14478 | * 0b11..Toggle output. | ||
| 14479 | */ | ||
| 14480 | #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) | ||
| 14481 | #define SCT_RES_O11RES_MASK (0xC00000U) | ||
| 14482 | #define SCT_RES_O11RES_SHIFT (22U) | ||
| 14483 | /*! O11RES - Effect of simultaneous set and clear on output 11. | ||
| 14484 | * 0b00..No change. | ||
| 14485 | * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). | ||
| 14486 | * 0b10..Clear output (or set based on the SETCLR11 field). | ||
| 14487 | * 0b11..Toggle output. | ||
| 14488 | */ | ||
| 14489 | #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) | ||
| 14490 | #define SCT_RES_O12RES_MASK (0x3000000U) | ||
| 14491 | #define SCT_RES_O12RES_SHIFT (24U) | ||
| 14492 | /*! O12RES - Effect of simultaneous set and clear on output 12. | ||
| 14493 | * 0b00..No change. | ||
| 14494 | * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). | ||
| 14495 | * 0b10..Clear output (or set based on the SETCLR12 field). | ||
| 14496 | * 0b11..Toggle output. | ||
| 14497 | */ | ||
| 14498 | #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) | ||
| 14499 | #define SCT_RES_O13RES_MASK (0xC000000U) | ||
| 14500 | #define SCT_RES_O13RES_SHIFT (26U) | ||
| 14501 | /*! O13RES - Effect of simultaneous set and clear on output 13. | ||
| 14502 | * 0b00..No change. | ||
| 14503 | * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). | ||
| 14504 | * 0b10..Clear output (or set based on the SETCLR13 field). | ||
| 14505 | * 0b11..Toggle output. | ||
| 14506 | */ | ||
| 14507 | #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) | ||
| 14508 | #define SCT_RES_O14RES_MASK (0x30000000U) | ||
| 14509 | #define SCT_RES_O14RES_SHIFT (28U) | ||
| 14510 | /*! O14RES - Effect of simultaneous set and clear on output 14. | ||
| 14511 | * 0b00..No change. | ||
| 14512 | * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). | ||
| 14513 | * 0b10..Clear output (or set based on the SETCLR14 field). | ||
| 14514 | * 0b11..Toggle output. | ||
| 14515 | */ | ||
| 14516 | #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) | ||
| 14517 | #define SCT_RES_O15RES_MASK (0xC0000000U) | ||
| 14518 | #define SCT_RES_O15RES_SHIFT (30U) | ||
| 14519 | /*! O15RES - Effect of simultaneous set and clear on output 15. | ||
| 14520 | * 0b00..No change. | ||
| 14521 | * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). | ||
| 14522 | * 0b10..Clear output (or set based on the SETCLR15 field). | ||
| 14523 | * 0b11..Toggle output. | ||
| 14524 | */ | ||
| 14525 | #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) | ||
| 14526 | /*! @} */ | ||
| 14527 | |||
| 14528 | /*! @name DMAREQ0 - SCT DMA request 0 register */ | ||
| 14529 | /*! @{ */ | ||
| 14530 | #define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) | ||
| 14531 | #define SCT_DMAREQ0_DEV_0_SHIFT (0U) | ||
| 14532 | /*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, | ||
| 14533 | * etc.). The number of bits = number of events in this SCT. | ||
| 14534 | */ | ||
| 14535 | #define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) | ||
| 14536 | #define SCT_DMAREQ0_DRL0_MASK (0x40000000U) | ||
| 14537 | #define SCT_DMAREQ0_DRL0_SHIFT (30U) | ||
| 14538 | /*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. | ||
| 14539 | */ | ||
| 14540 | #define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) | ||
| 14541 | #define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) | ||
| 14542 | #define SCT_DMAREQ0_DRQ0_SHIFT (31U) | ||
| 14543 | /*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA | ||
| 14544 | * channel is enabled and properly set up, it is unlikely that software will see this flag, it will | ||
| 14545 | * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA | ||
| 14546 | * setup. | ||
| 14547 | */ | ||
| 14548 | #define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) | ||
| 14549 | /*! @} */ | ||
| 14550 | |||
| 14551 | /*! @name DMAREQ1 - SCT DMA request 1 register */ | ||
| 14552 | /*! @{ */ | ||
| 14553 | #define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) | ||
| 14554 | #define SCT_DMAREQ1_DEV_1_SHIFT (0U) | ||
| 14555 | /*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, | ||
| 14556 | * etc.). The number of bits = number of events in this SCT. | ||
| 14557 | */ | ||
| 14558 | #define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) | ||
| 14559 | #define SCT_DMAREQ1_DRL1_MASK (0x40000000U) | ||
| 14560 | #define SCT_DMAREQ1_DRL1_SHIFT (30U) | ||
| 14561 | /*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. | ||
| 14562 | */ | ||
| 14563 | #define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) | ||
| 14564 | #define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) | ||
| 14565 | #define SCT_DMAREQ1_DRQ1_SHIFT (31U) | ||
| 14566 | /*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA | ||
| 14567 | * channel is enabled and properly set up, it is unlikely that software will see this flag, it will | ||
| 14568 | * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA | ||
| 14569 | * setup. | ||
| 14570 | */ | ||
| 14571 | #define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) | ||
| 14572 | /*! @} */ | ||
| 14573 | |||
| 14574 | /*! @name EVEN - SCT event interrupt enable register */ | ||
| 14575 | /*! @{ */ | ||
| 14576 | #define SCT_EVEN_IEN_MASK (0xFFFFU) | ||
| 14577 | #define SCT_EVEN_IEN_SHIFT (0U) | ||
| 14578 | /*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are | ||
| 14579 | * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in | ||
| 14580 | * this SCT. | ||
| 14581 | */ | ||
| 14582 | #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) | ||
| 14583 | /*! @} */ | ||
| 14584 | |||
| 14585 | /*! @name EVFLAG - SCT event flag register */ | ||
| 14586 | /*! @{ */ | ||
| 14587 | #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) | ||
| 14588 | #define SCT_EVFLAG_FLAG_SHIFT (0U) | ||
| 14589 | /*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit | ||
| 14590 | * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. | ||
| 14591 | */ | ||
| 14592 | #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) | ||
| 14593 | /*! @} */ | ||
| 14594 | |||
| 14595 | /*! @name CONEN - SCT conflict interrupt enable register */ | ||
| 14596 | /*! @{ */ | ||
| 14597 | #define SCT_CONEN_NCEN_MASK (0xFFFFU) | ||
| 14598 | #define SCT_CONEN_NCEN_SHIFT (0U) | ||
| 14599 | /*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag | ||
| 14600 | * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of | ||
| 14601 | * outputs in this SCT. | ||
| 14602 | */ | ||
| 14603 | #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) | ||
| 14604 | /*! @} */ | ||
| 14605 | |||
| 14606 | /*! @name CONFLAG - SCT conflict flag register */ | ||
| 14607 | /*! @{ */ | ||
| 14608 | #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) | ||
| 14609 | #define SCT_CONFLAG_NCFLAG_SHIFT (0U) | ||
| 14610 | /*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was | ||
| 14611 | * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = | ||
| 14612 | * number of outputs in this SCT. | ||
| 14613 | */ | ||
| 14614 | #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) | ||
| 14615 | #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) | ||
| 14616 | #define SCT_CONFLAG_BUSERRL_SHIFT (30U) | ||
| 14617 | /*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE | ||
| 14618 | * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write | ||
| 14619 | * to certain L and H registers can be half successful and half unsuccessful. | ||
| 14620 | */ | ||
| 14621 | #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) | ||
| 14622 | #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) | ||
| 14623 | #define SCT_CONFLAG_BUSERRH_SHIFT (31U) | ||
| 14624 | /*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or | ||
| 14625 | * the Output register when the H counter was not halted. | ||
| 14626 | */ | ||
| 14627 | #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) | ||
| 14628 | /*! @} */ | ||
| 14629 | |||
| 14630 | /*! @name CAPL - SCT_CAPL register */ | ||
| 14631 | /*! @{ */ | ||
| 14632 | #define SCT_CAPL_CAPL_MASK (0xFFFFU) | ||
| 14633 | #define SCT_CAPL_CAPL_SHIFT (0U) | ||
| 14634 | #define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) | ||
| 14635 | /*! @} */ | ||
| 14636 | |||
| 14637 | /* The count of SCT_CAPL */ | ||
| 14638 | #define SCT_CAPL_COUNT (16U) | ||
| 14639 | |||
| 14640 | /*! @name CAPH - SCT_CAPH register */ | ||
| 14641 | /*! @{ */ | ||
| 14642 | #define SCT_CAPH_CAPH_MASK (0xFFFFU) | ||
| 14643 | #define SCT_CAPH_CAPH_SHIFT (0U) | ||
| 14644 | #define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) | ||
| 14645 | /*! @} */ | ||
| 14646 | |||
| 14647 | /* The count of SCT_CAPH */ | ||
| 14648 | #define SCT_CAPH_COUNT (16U) | ||
| 14649 | |||
| 14650 | /*! @name CAP - SCT capture register of capture channel */ | ||
| 14651 | /*! @{ */ | ||
| 14652 | #define SCT_CAP_CAPn_L_MASK (0xFFFFU) | ||
| 14653 | #define SCT_CAP_CAPn_L_SHIFT (0U) | ||
| 14654 | /*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. | ||
| 14655 | * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last | ||
| 14656 | * captured. | ||
| 14657 | */ | ||
| 14658 | #define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) | ||
| 14659 | #define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) | ||
| 14660 | #define SCT_CAP_CAPn_H_SHIFT (16U) | ||
| 14661 | /*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. | ||
| 14662 | * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last | ||
| 14663 | * captured. | ||
| 14664 | */ | ||
| 14665 | #define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) | ||
| 14666 | /*! @} */ | ||
| 14667 | |||
| 14668 | /* The count of SCT_CAP */ | ||
| 14669 | #define SCT_CAP_COUNT (16U) | ||
| 14670 | |||
| 14671 | /*! @name MATCHL - SCT_MATCHL register */ | ||
| 14672 | /*! @{ */ | ||
| 14673 | #define SCT_MATCHL_MATCHL_MASK (0xFFFFU) | ||
| 14674 | #define SCT_MATCHL_MATCHL_SHIFT (0U) | ||
| 14675 | #define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) | ||
| 14676 | /*! @} */ | ||
| 14677 | |||
| 14678 | /* The count of SCT_MATCHL */ | ||
| 14679 | #define SCT_MATCHL_COUNT (16U) | ||
| 14680 | |||
| 14681 | /*! @name MATCHH - SCT_MATCHH register */ | ||
| 14682 | /*! @{ */ | ||
| 14683 | #define SCT_MATCHH_MATCHH_MASK (0xFFFFU) | ||
| 14684 | #define SCT_MATCHH_MATCHH_SHIFT (0U) | ||
| 14685 | #define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) | ||
| 14686 | /*! @} */ | ||
| 14687 | |||
| 14688 | /* The count of SCT_MATCHH */ | ||
| 14689 | #define SCT_MATCHH_COUNT (16U) | ||
| 14690 | |||
| 14691 | /*! @name MATCH - SCT match value register of match channels */ | ||
| 14692 | /*! @{ */ | ||
| 14693 | #define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) | ||
| 14694 | #define SCT_MATCH_MATCHn_L_SHIFT (0U) | ||
| 14695 | /*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When | ||
| 14696 | * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified | ||
| 14697 | * counter. | ||
| 14698 | */ | ||
| 14699 | #define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) | ||
| 14700 | #define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) | ||
| 14701 | #define SCT_MATCH_MATCHn_H_SHIFT (16U) | ||
| 14702 | /*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When | ||
| 14703 | * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified | ||
| 14704 | * counter. | ||
| 14705 | */ | ||
| 14706 | #define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) | ||
| 14707 | /*! @} */ | ||
| 14708 | |||
| 14709 | /* The count of SCT_MATCH */ | ||
| 14710 | #define SCT_MATCH_COUNT (16U) | ||
| 14711 | |||
| 14712 | /*! @name CAPCTRLL - SCT_CAPCTRLL register */ | ||
| 14713 | /*! @{ */ | ||
| 14714 | #define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) | ||
| 14715 | #define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) | ||
| 14716 | #define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) | ||
| 14717 | /*! @} */ | ||
| 14718 | |||
| 14719 | /* The count of SCT_CAPCTRLL */ | ||
| 14720 | #define SCT_CAPCTRLL_COUNT (16U) | ||
| 14721 | |||
| 14722 | /*! @name CAPCTRLH - SCT_CAPCTRLH register */ | ||
| 14723 | /*! @{ */ | ||
| 14724 | #define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) | ||
| 14725 | #define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) | ||
| 14726 | #define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) | ||
| 14727 | /*! @} */ | ||
| 14728 | |||
| 14729 | /* The count of SCT_CAPCTRLH */ | ||
| 14730 | #define SCT_CAPCTRLH_COUNT (16U) | ||
| 14731 | |||
| 14732 | /*! @name CAPCTRL - SCT capture control register */ | ||
| 14733 | /*! @{ */ | ||
| 14734 | #define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) | ||
| 14735 | #define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) | ||
| 14736 | /*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) | ||
| 14737 | * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of | ||
| 14738 | * match/captures in this SCT. | ||
| 14739 | */ | ||
| 14740 | #define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) | ||
| 14741 | #define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) | ||
| 14742 | #define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) | ||
| 14743 | /*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event | ||
| 14744 | * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. | ||
| 14745 | */ | ||
| 14746 | #define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) | ||
| 14747 | /*! @} */ | ||
| 14748 | |||
| 14749 | /* The count of SCT_CAPCTRL */ | ||
| 14750 | #define SCT_CAPCTRL_COUNT (16U) | ||
| 14751 | |||
| 14752 | /*! @name MATCHRELL - SCT_MATCHRELL register */ | ||
| 14753 | /*! @{ */ | ||
| 14754 | #define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) | ||
| 14755 | #define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) | ||
| 14756 | #define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) | ||
| 14757 | /*! @} */ | ||
| 14758 | |||
| 14759 | /* The count of SCT_MATCHRELL */ | ||
| 14760 | #define SCT_MATCHRELL_COUNT (16U) | ||
| 14761 | |||
| 14762 | /*! @name MATCHRELH - SCT_MATCHRELH register */ | ||
| 14763 | /*! @{ */ | ||
| 14764 | #define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) | ||
| 14765 | #define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) | ||
| 14766 | #define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) | ||
| 14767 | /*! @} */ | ||
| 14768 | |||
| 14769 | /* The count of SCT_MATCHRELH */ | ||
| 14770 | #define SCT_MATCHRELH_COUNT (16U) | ||
| 14771 | |||
| 14772 | /*! @name MATCHREL - SCT match reload value register */ | ||
| 14773 | /*! @{ */ | ||
| 14774 | #define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) | ||
| 14775 | #define SCT_MATCHREL_RELOADn_L_SHIFT (0U) | ||
| 14776 | /*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. | ||
| 14777 | * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn | ||
| 14778 | * register. | ||
| 14779 | */ | ||
| 14780 | #define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) | ||
| 14781 | #define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) | ||
| 14782 | #define SCT_MATCHREL_RELOADn_H_SHIFT (16U) | ||
| 14783 | /*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When | ||
| 14784 | * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn | ||
| 14785 | * register. | ||
| 14786 | */ | ||
| 14787 | #define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) | ||
| 14788 | /*! @} */ | ||
| 14789 | |||
| 14790 | /* The count of SCT_MATCHREL */ | ||
| 14791 | #define SCT_MATCHREL_COUNT (16U) | ||
| 14792 | |||
| 14793 | /*! @name EV_STATE - SCT event state register 0 */ | ||
| 14794 | /*! @{ */ | ||
| 14795 | #define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) | ||
| 14796 | #define SCT_EV_STATE_STATEMSKn_SHIFT (0U) | ||
| 14797 | /*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT | ||
| 14798 | * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of | ||
| 14799 | * bits = number of states in this SCT. | ||
| 14800 | */ | ||
| 14801 | #define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) | ||
| 14802 | /*! @} */ | ||
| 14803 | |||
| 14804 | /* The count of SCT_EV_STATE */ | ||
| 14805 | #define SCT_EV_STATE_COUNT (16U) | ||
| 14806 | |||
| 14807 | /*! @name EV_CTRL - SCT event control register 0 */ | ||
| 14808 | /*! @{ */ | ||
| 14809 | #define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) | ||
| 14810 | #define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) | ||
| 14811 | /*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur | ||
| 14812 | * only when the counter selected by the HEVENT bit is running. | ||
| 14813 | */ | ||
| 14814 | #define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) | ||
| 14815 | #define SCT_EV_CTRL_HEVENT_MASK (0x10U) | ||
| 14816 | #define SCT_EV_CTRL_HEVENT_SHIFT (4U) | ||
| 14817 | /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. | ||
| 14818 | * 0b0..Selects the L state and the L match register selected by MATCHSEL. | ||
| 14819 | * 0b1..Selects the H state and the H match register selected by MATCHSEL. | ||
| 14820 | */ | ||
| 14821 | #define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) | ||
| 14822 | #define SCT_EV_CTRL_OUTSEL_MASK (0x20U) | ||
| 14823 | #define SCT_EV_CTRL_OUTSEL_SHIFT (5U) | ||
| 14824 | /*! OUTSEL - Input/output select | ||
| 14825 | * 0b0..Selects the inputs selected by IOSEL. | ||
| 14826 | * 0b1..Selects the outputs selected by IOSEL. | ||
| 14827 | */ | ||
| 14828 | #define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) | ||
| 14829 | #define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) | ||
| 14830 | #define SCT_EV_CTRL_IOSEL_SHIFT (6U) | ||
| 14831 | /*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not | ||
| 14832 | * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit | ||
| 14833 | * ingredient of every event. | ||
| 14834 | */ | ||
| 14835 | #define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) | ||
| 14836 | #define SCT_EV_CTRL_IOCOND_MASK (0xC00U) | ||
| 14837 | #define SCT_EV_CTRL_IOCOND_SHIFT (10U) | ||
| 14838 | /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the | ||
| 14839 | * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state | ||
| 14840 | * detection, an input must have a minimum pulse width of at least one SCT clock period . | ||
| 14841 | * 0b00..LOW | ||
| 14842 | * 0b01..Rise | ||
| 14843 | * 0b10..Fall | ||
| 14844 | * 0b11..HIGH | ||
| 14845 | */ | ||
| 14846 | #define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) | ||
| 14847 | #define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) | ||
| 14848 | #define SCT_EV_CTRL_COMBMODE_SHIFT (12U) | ||
| 14849 | /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. | ||
| 14850 | * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. | ||
| 14851 | * 0b01..MATCH. Uses the specified match only. | ||
| 14852 | * 0b10..IO. Uses the specified I/O condition only. | ||
| 14853 | * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. | ||
| 14854 | */ | ||
| 14855 | #define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) | ||
| 14856 | #define SCT_EV_CTRL_STATELD_MASK (0x4000U) | ||
| 14857 | #define SCT_EV_CTRL_STATELD_SHIFT (14U) | ||
| 14858 | /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this | ||
| 14859 | * event is the highest-numbered event occurring for that state. | ||
| 14860 | * 0b0..STATEV value is added into STATE (the carry-out is ignored). | ||
| 14861 | * 0b1..STATEV value is loaded into STATE. | ||
| 14862 | */ | ||
| 14863 | #define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) | ||
| 14864 | #define SCT_EV_CTRL_STATEV_MASK (0xF8000U) | ||
| 14865 | #define SCT_EV_CTRL_STATEV_SHIFT (15U) | ||
| 14866 | /*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on | ||
| 14867 | * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and | ||
| 14868 | * STATEV are both zero, there is no change to the STATE value. | ||
| 14869 | */ | ||
| 14870 | #define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) | ||
| 14871 | #define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) | ||
| 14872 | #define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) | ||
| 14873 | /*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the | ||
| 14874 | * triggering of this event, then a match is considered to be active whenever the counter value is | ||
| 14875 | * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR | ||
| 14876 | * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active | ||
| 14877 | * during the cycle when the counter is equal to the match value. | ||
| 14878 | */ | ||
| 14879 | #define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) | ||
| 14880 | #define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) | ||
| 14881 | #define SCT_EV_CTRL_DIRECTION_SHIFT (21U) | ||
| 14882 | /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters | ||
| 14883 | * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. | ||
| 14884 | * 0b00..Direction independent. This event is triggered regardless of the count direction. | ||
| 14885 | * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. | ||
| 14886 | * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. | ||
| 14887 | */ | ||
| 14888 | #define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) | ||
| 14889 | /*! @} */ | ||
| 14890 | |||
| 14891 | /* The count of SCT_EV_CTRL */ | ||
| 14892 | #define SCT_EV_CTRL_COUNT (16U) | ||
| 14893 | |||
| 14894 | /*! @name OUT_SET - SCT output 0 set register */ | ||
| 14895 | /*! @{ */ | ||
| 14896 | #define SCT_OUT_SET_SET_MASK (0xFFFFU) | ||
| 14897 | #define SCT_OUT_SET_SET_SHIFT (0U) | ||
| 14898 | /*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output | ||
| 14899 | * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the | ||
| 14900 | * counter is used in bi-directional mode, it is possible to reverse the action specified by the | ||
| 14901 | * output set and clear registers when counting down, See the OUTPUTCTRL register. | ||
| 14902 | */ | ||
| 14903 | #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) | ||
| 14904 | /*! @} */ | ||
| 14905 | |||
| 14906 | /* The count of SCT_OUT_SET */ | ||
| 14907 | #define SCT_OUT_SET_COUNT (10U) | ||
| 14908 | |||
| 14909 | /*! @name OUT_CLR - SCT output 0 clear register */ | ||
| 14910 | /*! @{ */ | ||
| 14911 | #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) | ||
| 14912 | #define SCT_OUT_CLR_CLR_SHIFT (0U) | ||
| 14913 | /*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 | ||
| 14914 | * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the | ||
| 14915 | * counter is used in bi-directional mode, it is possible to reverse the action specified by the | ||
| 14916 | * output set and clear registers when counting down, See the OUTPUTCTRL register. | ||
| 14917 | */ | ||
| 14918 | #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) | ||
| 14919 | /*! @} */ | ||
| 14920 | |||
| 14921 | /* The count of SCT_OUT_CLR */ | ||
| 14922 | #define SCT_OUT_CLR_COUNT (10U) | ||
| 14923 | |||
| 14924 | |||
| 14925 | /*! | ||
| 14926 | * @} | ||
| 14927 | */ /* end of group SCT_Register_Masks */ | ||
| 14928 | |||
| 14929 | |||
| 14930 | /* SCT - Peripheral instance base addresses */ | ||
| 14931 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 14932 | /** Peripheral SCT0 base address */ | ||
| 14933 | #define SCT0_BASE (0x50085000u) | ||
| 14934 | /** Peripheral SCT0 base address */ | ||
| 14935 | #define SCT0_BASE_NS (0x40085000u) | ||
| 14936 | /** Peripheral SCT0 base pointer */ | ||
| 14937 | #define SCT0 ((SCT_Type *)SCT0_BASE) | ||
| 14938 | /** Peripheral SCT0 base pointer */ | ||
| 14939 | #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) | ||
| 14940 | /** Array initializer of SCT peripheral base addresses */ | ||
| 14941 | #define SCT_BASE_ADDRS { SCT0_BASE } | ||
| 14942 | /** Array initializer of SCT peripheral base pointers */ | ||
| 14943 | #define SCT_BASE_PTRS { SCT0 } | ||
| 14944 | /** Array initializer of SCT peripheral base addresses */ | ||
| 14945 | #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } | ||
| 14946 | /** Array initializer of SCT peripheral base pointers */ | ||
| 14947 | #define SCT_BASE_PTRS_NS { SCT0_NS } | ||
| 14948 | #else | ||
| 14949 | /** Peripheral SCT0 base address */ | ||
| 14950 | #define SCT0_BASE (0x40085000u) | ||
| 14951 | /** Peripheral SCT0 base pointer */ | ||
| 14952 | #define SCT0 ((SCT_Type *)SCT0_BASE) | ||
| 14953 | /** Array initializer of SCT peripheral base addresses */ | ||
| 14954 | #define SCT_BASE_ADDRS { SCT0_BASE } | ||
| 14955 | /** Array initializer of SCT peripheral base pointers */ | ||
| 14956 | #define SCT_BASE_PTRS { SCT0 } | ||
| 14957 | #endif | ||
| 14958 | /** Interrupt vectors for the SCT peripheral type */ | ||
| 14959 | #define SCT_IRQS { SCT0_IRQn } | ||
| 14960 | |||
| 14961 | /*! | ||
| 14962 | * @} | ||
| 14963 | */ /* end of group SCT_Peripheral_Access_Layer */ | ||
| 14964 | |||
| 14965 | |||
| 14966 | /* ---------------------------------------------------------------------------- | ||
| 14967 | -- SDIF Peripheral Access Layer | ||
| 14968 | ---------------------------------------------------------------------------- */ | ||
| 14969 | |||
| 14970 | /*! | ||
| 14971 | * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer | ||
| 14972 | * @{ | ||
| 14973 | */ | ||
| 14974 | |||
| 14975 | /** SDIF - Register Layout Typedef */ | ||
| 14976 | typedef struct { | ||
| 14977 | __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ | ||
| 14978 | __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ | ||
| 14979 | __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ | ||
| 14980 | uint8_t RESERVED_0[4]; | ||
| 14981 | __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ | ||
| 14982 | __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ | ||
| 14983 | __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ | ||
| 14984 | __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ | ||
| 14985 | __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ | ||
| 14986 | __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ | ||
| 14987 | __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ | ||
| 14988 | __IO uint32_t CMD; /**< Command register, offset: 0x2C */ | ||
| 14989 | __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ | ||
| 14990 | __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ | ||
| 14991 | __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ | ||
| 14992 | __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ | ||
| 14993 | __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ | ||
| 14994 | __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ | ||
| 14995 | __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ | ||
| 14996 | uint8_t RESERVED_1[4]; | ||
| 14997 | __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ | ||
| 14998 | __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ | ||
| 14999 | __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ | ||
| 15000 | uint8_t RESERVED_2[16]; | ||
| 15001 | __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ | ||
| 15002 | uint8_t RESERVED_3[4]; | ||
| 15003 | __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ | ||
| 15004 | __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ | ||
| 15005 | __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ | ||
| 15006 | __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ | ||
| 15007 | __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ | ||
| 15008 | __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ | ||
| 15009 | __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ | ||
| 15010 | uint8_t RESERVED_4[100]; | ||
| 15011 | __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ | ||
| 15012 | __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ | ||
| 15013 | uint8_t RESERVED_5[248]; | ||
| 15014 | __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ | ||
| 15015 | } SDIF_Type; | ||
| 15016 | |||
| 15017 | /* ---------------------------------------------------------------------------- | ||
| 15018 | -- SDIF Register Masks | ||
| 15019 | ---------------------------------------------------------------------------- */ | ||
| 15020 | |||
| 15021 | /*! | ||
| 15022 | * @addtogroup SDIF_Register_Masks SDIF Register Masks | ||
| 15023 | * @{ | ||
| 15024 | */ | ||
| 15025 | |||
| 15026 | /*! @name CTRL - Control register */ | ||
| 15027 | /*! @{ */ | ||
| 15028 | #define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) | ||
| 15029 | #define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) | ||
| 15030 | /*! CONTROLLER_RESET - Controller reset. | ||
| 15031 | */ | ||
| 15032 | #define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) | ||
| 15033 | #define SDIF_CTRL_FIFO_RESET_MASK (0x2U) | ||
| 15034 | #define SDIF_CTRL_FIFO_RESET_SHIFT (1U) | ||
| 15035 | /*! FIFO_RESET - Fifo reset. | ||
| 15036 | */ | ||
| 15037 | #define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) | ||
| 15038 | #define SDIF_CTRL_DMA_RESET_MASK (0x4U) | ||
| 15039 | #define SDIF_CTRL_DMA_RESET_SHIFT (2U) | ||
| 15040 | /*! DMA_RESET - DMA reset. | ||
| 15041 | */ | ||
| 15042 | #define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) | ||
| 15043 | #define SDIF_CTRL_INT_ENABLE_MASK (0x10U) | ||
| 15044 | #define SDIF_CTRL_INT_ENABLE_SHIFT (4U) | ||
| 15045 | /*! INT_ENABLE - Global interrupt enable/disable bit. | ||
| 15046 | */ | ||
| 15047 | #define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) | ||
| 15048 | #define SDIF_CTRL_READ_WAIT_MASK (0x40U) | ||
| 15049 | #define SDIF_CTRL_READ_WAIT_SHIFT (6U) | ||
| 15050 | /*! READ_WAIT - Read/wait. | ||
| 15051 | */ | ||
| 15052 | #define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) | ||
| 15053 | #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) | ||
| 15054 | #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) | ||
| 15055 | /*! SEND_IRQ_RESPONSE - Send irq response. | ||
| 15056 | */ | ||
| 15057 | #define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) | ||
| 15058 | #define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) | ||
| 15059 | #define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) | ||
| 15060 | /*! ABORT_READ_DATA - Abort read data. | ||
| 15061 | */ | ||
| 15062 | #define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) | ||
| 15063 | #define SDIF_CTRL_SEND_CCSD_MASK (0x200U) | ||
| 15064 | #define SDIF_CTRL_SEND_CCSD_SHIFT (9U) | ||
| 15065 | /*! SEND_CCSD - Send ccsd. | ||
| 15066 | */ | ||
| 15067 | #define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) | ||
| 15068 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) | ||
| 15069 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) | ||
| 15070 | /*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. | ||
| 15071 | */ | ||
| 15072 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) | ||
| 15073 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) | ||
| 15074 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) | ||
| 15075 | /*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. | ||
| 15076 | */ | ||
| 15077 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) | ||
| 15078 | #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) | ||
| 15079 | #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) | ||
| 15080 | /*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. | ||
| 15081 | */ | ||
| 15082 | #define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) | ||
| 15083 | #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) | ||
| 15084 | #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) | ||
| 15085 | /*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. | ||
| 15086 | */ | ||
| 15087 | #define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) | ||
| 15088 | #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) | ||
| 15089 | #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) | ||
| 15090 | /*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. | ||
| 15091 | */ | ||
| 15092 | #define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) | ||
| 15093 | #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) | ||
| 15094 | #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) | ||
| 15095 | /*! USE_INTERNAL_DMAC - SD/MMC DMA use. | ||
| 15096 | */ | ||
| 15097 | #define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) | ||
| 15098 | /*! @} */ | ||
| 15099 | |||
| 15100 | /*! @name PWREN - Power Enable register */ | ||
| 15101 | /*! @{ */ | ||
| 15102 | #define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) | ||
| 15103 | #define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) | ||
| 15104 | /*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait | ||
| 15105 | * for regulator/switch ramp-up time before trying to initialize card 0. | ||
| 15106 | */ | ||
| 15107 | #define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) | ||
| 15108 | #define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) | ||
| 15109 | #define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) | ||
| 15110 | /*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait | ||
| 15111 | * for regulator/switch ramp-up time before trying to initialize card 1. | ||
| 15112 | */ | ||
| 15113 | #define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) | ||
| 15114 | /*! @} */ | ||
| 15115 | |||
| 15116 | /*! @name CLKDIV - Clock Divider register */ | ||
| 15117 | /*! @{ */ | ||
| 15118 | #define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) | ||
| 15119 | #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) | ||
| 15120 | /*! CLK_DIVIDER0 - Clock divider-0 value. | ||
| 15121 | */ | ||
| 15122 | #define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) | ||
| 15123 | /*! @} */ | ||
| 15124 | |||
| 15125 | /*! @name CLKENA - Clock Enable register */ | ||
| 15126 | /*! @{ */ | ||
| 15127 | #define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) | ||
| 15128 | #define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) | ||
| 15129 | /*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. | ||
| 15130 | */ | ||
| 15131 | #define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) | ||
| 15132 | #define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) | ||
| 15133 | #define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) | ||
| 15134 | /*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. | ||
| 15135 | */ | ||
| 15136 | #define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) | ||
| 15137 | #define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) | ||
| 15138 | #define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) | ||
| 15139 | /*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. | ||
| 15140 | */ | ||
| 15141 | #define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) | ||
| 15142 | #define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) | ||
| 15143 | #define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) | ||
| 15144 | /*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. | ||
| 15145 | */ | ||
| 15146 | #define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) | ||
| 15147 | /*! @} */ | ||
| 15148 | |||
| 15149 | /*! @name TMOUT - Time-out register */ | ||
| 15150 | /*! @{ */ | ||
| 15151 | #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) | ||
| 15152 | #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) | ||
| 15153 | /*! RESPONSE_TIMEOUT - Response time-out value. | ||
| 15154 | */ | ||
| 15155 | #define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) | ||
| 15156 | #define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) | ||
| 15157 | #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) | ||
| 15158 | /*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. | ||
| 15159 | */ | ||
| 15160 | #define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) | ||
| 15161 | /*! @} */ | ||
| 15162 | |||
| 15163 | /*! @name CTYPE - Card Type register */ | ||
| 15164 | /*! @{ */ | ||
| 15165 | #define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) | ||
| 15166 | #define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) | ||
| 15167 | /*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit | ||
| 15168 | * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set | ||
| 15169 | * to 0). | ||
| 15170 | */ | ||
| 15171 | #define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) | ||
| 15172 | #define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) | ||
| 15173 | #define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) | ||
| 15174 | /*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit | ||
| 15175 | * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set | ||
| 15176 | * to 0). | ||
| 15177 | */ | ||
| 15178 | #define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) | ||
| 15179 | #define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) | ||
| 15180 | #define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) | ||
| 15181 | /*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. | ||
| 15182 | */ | ||
| 15183 | #define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) | ||
| 15184 | #define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) | ||
| 15185 | #define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) | ||
| 15186 | /*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. | ||
| 15187 | */ | ||
| 15188 | #define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) | ||
| 15189 | /*! @} */ | ||
| 15190 | |||
| 15191 | /*! @name BLKSIZ - Block Size register */ | ||
| 15192 | /*! @{ */ | ||
| 15193 | #define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) | ||
| 15194 | #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) | ||
| 15195 | /*! BLOCK_SIZE - Block size. | ||
| 15196 | */ | ||
| 15197 | #define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) | ||
| 15198 | /*! @} */ | ||
| 15199 | |||
| 15200 | /*! @name BYTCNT - Byte Count register */ | ||
| 15201 | /*! @{ */ | ||
| 15202 | #define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) | ||
| 15203 | #define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) | ||
| 15204 | /*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. | ||
| 15205 | */ | ||
| 15206 | #define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) | ||
| 15207 | /*! @} */ | ||
| 15208 | |||
| 15209 | /*! @name INTMASK - Interrupt Mask register */ | ||
| 15210 | /*! @{ */ | ||
| 15211 | #define SDIF_INTMASK_CDET_MASK (0x1U) | ||
| 15212 | #define SDIF_INTMASK_CDET_SHIFT (0U) | ||
| 15213 | /*! CDET - Card detect. | ||
| 15214 | */ | ||
| 15215 | #define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) | ||
| 15216 | #define SDIF_INTMASK_RE_MASK (0x2U) | ||
| 15217 | #define SDIF_INTMASK_RE_SHIFT (1U) | ||
| 15218 | /*! RE - Response error. | ||
| 15219 | */ | ||
| 15220 | #define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) | ||
| 15221 | #define SDIF_INTMASK_CDONE_MASK (0x4U) | ||
| 15222 | #define SDIF_INTMASK_CDONE_SHIFT (2U) | ||
| 15223 | /*! CDONE - Command done. | ||
| 15224 | */ | ||
| 15225 | #define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) | ||
| 15226 | #define SDIF_INTMASK_DTO_MASK (0x8U) | ||
| 15227 | #define SDIF_INTMASK_DTO_SHIFT (3U) | ||
| 15228 | /*! DTO - Data transfer over. | ||
| 15229 | */ | ||
| 15230 | #define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) | ||
| 15231 | #define SDIF_INTMASK_TXDR_MASK (0x10U) | ||
| 15232 | #define SDIF_INTMASK_TXDR_SHIFT (4U) | ||
| 15233 | /*! TXDR - Transmit FIFO data request. | ||
| 15234 | */ | ||
| 15235 | #define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) | ||
| 15236 | #define SDIF_INTMASK_RXDR_MASK (0x20U) | ||
| 15237 | #define SDIF_INTMASK_RXDR_SHIFT (5U) | ||
| 15238 | /*! RXDR - Receive FIFO data request. | ||
| 15239 | */ | ||
| 15240 | #define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) | ||
| 15241 | #define SDIF_INTMASK_RCRC_MASK (0x40U) | ||
| 15242 | #define SDIF_INTMASK_RCRC_SHIFT (6U) | ||
| 15243 | /*! RCRC - Response CRC error. | ||
| 15244 | */ | ||
| 15245 | #define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) | ||
| 15246 | #define SDIF_INTMASK_DCRC_MASK (0x80U) | ||
| 15247 | #define SDIF_INTMASK_DCRC_SHIFT (7U) | ||
| 15248 | /*! DCRC - Data CRC error. | ||
| 15249 | */ | ||
| 15250 | #define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) | ||
| 15251 | #define SDIF_INTMASK_RTO_MASK (0x100U) | ||
| 15252 | #define SDIF_INTMASK_RTO_SHIFT (8U) | ||
| 15253 | /*! RTO - Response time-out. | ||
| 15254 | */ | ||
| 15255 | #define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) | ||
| 15256 | #define SDIF_INTMASK_DRTO_MASK (0x200U) | ||
| 15257 | #define SDIF_INTMASK_DRTO_SHIFT (9U) | ||
| 15258 | /*! DRTO - Data read time-out. | ||
| 15259 | */ | ||
| 15260 | #define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) | ||
| 15261 | #define SDIF_INTMASK_HTO_MASK (0x400U) | ||
| 15262 | #define SDIF_INTMASK_HTO_SHIFT (10U) | ||
| 15263 | /*! HTO - Data starvation-by-host time-out (HTO). | ||
| 15264 | */ | ||
| 15265 | #define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) | ||
| 15266 | #define SDIF_INTMASK_FRUN_MASK (0x800U) | ||
| 15267 | #define SDIF_INTMASK_FRUN_SHIFT (11U) | ||
| 15268 | /*! FRUN - FIFO underrun/overrun error. | ||
| 15269 | */ | ||
| 15270 | #define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) | ||
| 15271 | #define SDIF_INTMASK_HLE_MASK (0x1000U) | ||
| 15272 | #define SDIF_INTMASK_HLE_SHIFT (12U) | ||
| 15273 | /*! HLE - Hardware locked write error. | ||
| 15274 | */ | ||
| 15275 | #define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) | ||
| 15276 | #define SDIF_INTMASK_SBE_MASK (0x2000U) | ||
| 15277 | #define SDIF_INTMASK_SBE_SHIFT (13U) | ||
| 15278 | /*! SBE - Start-bit error. | ||
| 15279 | */ | ||
| 15280 | #define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) | ||
| 15281 | #define SDIF_INTMASK_ACD_MASK (0x4000U) | ||
| 15282 | #define SDIF_INTMASK_ACD_SHIFT (14U) | ||
| 15283 | /*! ACD - Auto command done. | ||
| 15284 | */ | ||
| 15285 | #define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) | ||
| 15286 | #define SDIF_INTMASK_EBE_MASK (0x8000U) | ||
| 15287 | #define SDIF_INTMASK_EBE_SHIFT (15U) | ||
| 15288 | /*! EBE - End-bit error (read)/Write no CRC. | ||
| 15289 | */ | ||
| 15290 | #define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) | ||
| 15291 | #define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) | ||
| 15292 | #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) | ||
| 15293 | /*! SDIO_INT_MASK - Mask SDIO interrupt. | ||
| 15294 | */ | ||
| 15295 | #define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) | ||
| 15296 | /*! @} */ | ||
| 15297 | |||
| 15298 | /*! @name CMDARG - Command Argument register */ | ||
| 15299 | /*! @{ */ | ||
| 15300 | #define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) | ||
| 15301 | #define SDIF_CMDARG_CMD_ARG_SHIFT (0U) | ||
| 15302 | /*! CMD_ARG - Value indicates command argument to be passed to card. | ||
| 15303 | */ | ||
| 15304 | #define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) | ||
| 15305 | /*! @} */ | ||
| 15306 | |||
| 15307 | /*! @name CMD - Command register */ | ||
| 15308 | /*! @{ */ | ||
| 15309 | #define SDIF_CMD_CMD_INDEX_MASK (0x3FU) | ||
| 15310 | #define SDIF_CMD_CMD_INDEX_SHIFT (0U) | ||
| 15311 | /*! CMD_INDEX - Command index. | ||
| 15312 | */ | ||
| 15313 | #define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) | ||
| 15314 | #define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) | ||
| 15315 | #define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) | ||
| 15316 | /*! RESPONSE_EXPECT - Response expect. | ||
| 15317 | */ | ||
| 15318 | #define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) | ||
| 15319 | #define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) | ||
| 15320 | #define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) | ||
| 15321 | /*! RESPONSE_LENGTH - Response length. | ||
| 15322 | */ | ||
| 15323 | #define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) | ||
| 15324 | #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) | ||
| 15325 | #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) | ||
| 15326 | /*! CHECK_RESPONSE_CRC - Check response CRC. | ||
| 15327 | */ | ||
| 15328 | #define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) | ||
| 15329 | #define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) | ||
| 15330 | #define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) | ||
| 15331 | /*! DATA_EXPECTED - Data expected. | ||
| 15332 | */ | ||
| 15333 | #define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) | ||
| 15334 | #define SDIF_CMD_READ_WRITE_MASK (0x400U) | ||
| 15335 | #define SDIF_CMD_READ_WRITE_SHIFT (10U) | ||
| 15336 | /*! READ_WRITE - read/write. | ||
| 15337 | */ | ||
| 15338 | #define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) | ||
| 15339 | #define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) | ||
| 15340 | #define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) | ||
| 15341 | /*! TRANSFER_MODE - Transfer mode. | ||
| 15342 | */ | ||
| 15343 | #define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) | ||
| 15344 | #define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) | ||
| 15345 | #define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) | ||
| 15346 | /*! SEND_AUTO_STOP - Send auto stop. | ||
| 15347 | */ | ||
| 15348 | #define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) | ||
| 15349 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) | ||
| 15350 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) | ||
| 15351 | /*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. | ||
| 15352 | */ | ||
| 15353 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) | ||
| 15354 | #define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) | ||
| 15355 | #define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) | ||
| 15356 | /*! STOP_ABORT_CMD - Stop abort command. | ||
| 15357 | */ | ||
| 15358 | #define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) | ||
| 15359 | #define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) | ||
| 15360 | #define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) | ||
| 15361 | /*! SEND_INITIALIZATION - Send initialization. | ||
| 15362 | */ | ||
| 15363 | #define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) | ||
| 15364 | #define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) | ||
| 15365 | #define SDIF_CMD_CARD_NUMBER_SHIFT (16U) | ||
| 15366 | /*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed | ||
| 15367 | * 0b00000..Command will be execute on SDCARD 0 | ||
| 15368 | * 0b00001..Command will be execute on SDCARD 1 | ||
| 15369 | */ | ||
| 15370 | #define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) | ||
| 15371 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) | ||
| 15372 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) | ||
| 15373 | /*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. | ||
| 15374 | */ | ||
| 15375 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) | ||
| 15376 | #define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) | ||
| 15377 | #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) | ||
| 15378 | /*! READ_CEATA_DEVICE - Read ceata device. | ||
| 15379 | */ | ||
| 15380 | #define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) | ||
| 15381 | #define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) | ||
| 15382 | #define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) | ||
| 15383 | /*! CCS_EXPECTED - CCS expected. | ||
| 15384 | */ | ||
| 15385 | #define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) | ||
| 15386 | #define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) | ||
| 15387 | #define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) | ||
| 15388 | /*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. | ||
| 15389 | */ | ||
| 15390 | #define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) | ||
| 15391 | #define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) | ||
| 15392 | #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) | ||
| 15393 | /*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. | ||
| 15394 | */ | ||
| 15395 | #define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) | ||
| 15396 | #define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) | ||
| 15397 | #define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) | ||
| 15398 | /*! DISABLE_BOOT - Disable Boot. | ||
| 15399 | */ | ||
| 15400 | #define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) | ||
| 15401 | #define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) | ||
| 15402 | #define SDIF_CMD_BOOT_MODE_SHIFT (27U) | ||
| 15403 | /*! BOOT_MODE - Boot Mode. | ||
| 15404 | */ | ||
| 15405 | #define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) | ||
| 15406 | #define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) | ||
| 15407 | #define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) | ||
| 15408 | /*! VOLT_SWITCH - Voltage switch bit. | ||
| 15409 | */ | ||
| 15410 | #define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) | ||
| 15411 | #define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) | ||
| 15412 | #define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) | ||
| 15413 | /*! USE_HOLD_REG - Use Hold Register. | ||
| 15414 | */ | ||
| 15415 | #define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) | ||
| 15416 | #define SDIF_CMD_START_CMD_MASK (0x80000000U) | ||
| 15417 | #define SDIF_CMD_START_CMD_SHIFT (31U) | ||
| 15418 | /*! START_CMD - Start command. | ||
| 15419 | */ | ||
| 15420 | #define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) | ||
| 15421 | /*! @} */ | ||
| 15422 | |||
| 15423 | /*! @name RESP - Response register */ | ||
| 15424 | /*! @{ */ | ||
| 15425 | #define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) | ||
| 15426 | #define SDIF_RESP_RESPONSE_SHIFT (0U) | ||
| 15427 | /*! RESPONSE - Bits of response. | ||
| 15428 | */ | ||
| 15429 | #define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) | ||
| 15430 | /*! @} */ | ||
| 15431 | |||
| 15432 | /* The count of SDIF_RESP */ | ||
| 15433 | #define SDIF_RESP_COUNT (4U) | ||
| 15434 | |||
| 15435 | /*! @name MINTSTS - Masked Interrupt Status register */ | ||
| 15436 | /*! @{ */ | ||
| 15437 | #define SDIF_MINTSTS_CDET_MASK (0x1U) | ||
| 15438 | #define SDIF_MINTSTS_CDET_SHIFT (0U) | ||
| 15439 | /*! CDET - Card detect. | ||
| 15440 | */ | ||
| 15441 | #define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) | ||
| 15442 | #define SDIF_MINTSTS_RE_MASK (0x2U) | ||
| 15443 | #define SDIF_MINTSTS_RE_SHIFT (1U) | ||
| 15444 | /*! RE - Response error. | ||
| 15445 | */ | ||
| 15446 | #define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) | ||
| 15447 | #define SDIF_MINTSTS_CDONE_MASK (0x4U) | ||
| 15448 | #define SDIF_MINTSTS_CDONE_SHIFT (2U) | ||
| 15449 | /*! CDONE - Command done. | ||
| 15450 | */ | ||
| 15451 | #define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) | ||
| 15452 | #define SDIF_MINTSTS_DTO_MASK (0x8U) | ||
| 15453 | #define SDIF_MINTSTS_DTO_SHIFT (3U) | ||
| 15454 | /*! DTO - Data transfer over. | ||
| 15455 | */ | ||
| 15456 | #define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) | ||
| 15457 | #define SDIF_MINTSTS_TXDR_MASK (0x10U) | ||
| 15458 | #define SDIF_MINTSTS_TXDR_SHIFT (4U) | ||
| 15459 | /*! TXDR - Transmit FIFO data request. | ||
| 15460 | */ | ||
| 15461 | #define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) | ||
| 15462 | #define SDIF_MINTSTS_RXDR_MASK (0x20U) | ||
| 15463 | #define SDIF_MINTSTS_RXDR_SHIFT (5U) | ||
| 15464 | /*! RXDR - Receive FIFO data request. | ||
| 15465 | */ | ||
| 15466 | #define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) | ||
| 15467 | #define SDIF_MINTSTS_RCRC_MASK (0x40U) | ||
| 15468 | #define SDIF_MINTSTS_RCRC_SHIFT (6U) | ||
| 15469 | /*! RCRC - Response CRC error. | ||
| 15470 | */ | ||
| 15471 | #define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) | ||
| 15472 | #define SDIF_MINTSTS_DCRC_MASK (0x80U) | ||
| 15473 | #define SDIF_MINTSTS_DCRC_SHIFT (7U) | ||
| 15474 | /*! DCRC - Data CRC error. | ||
| 15475 | */ | ||
| 15476 | #define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) | ||
| 15477 | #define SDIF_MINTSTS_RTO_MASK (0x100U) | ||
| 15478 | #define SDIF_MINTSTS_RTO_SHIFT (8U) | ||
| 15479 | /*! RTO - Response time-out. | ||
| 15480 | */ | ||
| 15481 | #define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) | ||
| 15482 | #define SDIF_MINTSTS_DRTO_MASK (0x200U) | ||
| 15483 | #define SDIF_MINTSTS_DRTO_SHIFT (9U) | ||
| 15484 | /*! DRTO - Data read time-out. | ||
| 15485 | */ | ||
| 15486 | #define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) | ||
| 15487 | #define SDIF_MINTSTS_HTO_MASK (0x400U) | ||
| 15488 | #define SDIF_MINTSTS_HTO_SHIFT (10U) | ||
| 15489 | /*! HTO - Data starvation-by-host time-out (HTO). | ||
| 15490 | */ | ||
| 15491 | #define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) | ||
| 15492 | #define SDIF_MINTSTS_FRUN_MASK (0x800U) | ||
| 15493 | #define SDIF_MINTSTS_FRUN_SHIFT (11U) | ||
| 15494 | /*! FRUN - FIFO underrun/overrun error. | ||
| 15495 | */ | ||
| 15496 | #define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) | ||
| 15497 | #define SDIF_MINTSTS_HLE_MASK (0x1000U) | ||
| 15498 | #define SDIF_MINTSTS_HLE_SHIFT (12U) | ||
| 15499 | /*! HLE - Hardware locked write error. | ||
| 15500 | */ | ||
| 15501 | #define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) | ||
| 15502 | #define SDIF_MINTSTS_SBE_MASK (0x2000U) | ||
| 15503 | #define SDIF_MINTSTS_SBE_SHIFT (13U) | ||
| 15504 | /*! SBE - Start-bit error. | ||
| 15505 | */ | ||
| 15506 | #define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) | ||
| 15507 | #define SDIF_MINTSTS_ACD_MASK (0x4000U) | ||
| 15508 | #define SDIF_MINTSTS_ACD_SHIFT (14U) | ||
| 15509 | /*! ACD - Auto command done. | ||
| 15510 | */ | ||
| 15511 | #define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) | ||
| 15512 | #define SDIF_MINTSTS_EBE_MASK (0x8000U) | ||
| 15513 | #define SDIF_MINTSTS_EBE_SHIFT (15U) | ||
| 15514 | /*! EBE - End-bit error (read)/write no CRC. | ||
| 15515 | */ | ||
| 15516 | #define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) | ||
| 15517 | #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) | ||
| 15518 | #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) | ||
| 15519 | /*! SDIO_INTERRUPT - Interrupt from SDIO card. | ||
| 15520 | */ | ||
| 15521 | #define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) | ||
| 15522 | /*! @} */ | ||
| 15523 | |||
| 15524 | /*! @name RINTSTS - Raw Interrupt Status register */ | ||
| 15525 | /*! @{ */ | ||
| 15526 | #define SDIF_RINTSTS_CDET_MASK (0x1U) | ||
| 15527 | #define SDIF_RINTSTS_CDET_SHIFT (0U) | ||
| 15528 | /*! CDET - Card detect. | ||
| 15529 | */ | ||
| 15530 | #define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) | ||
| 15531 | #define SDIF_RINTSTS_RE_MASK (0x2U) | ||
| 15532 | #define SDIF_RINTSTS_RE_SHIFT (1U) | ||
| 15533 | /*! RE - Response error. | ||
| 15534 | */ | ||
| 15535 | #define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) | ||
| 15536 | #define SDIF_RINTSTS_CDONE_MASK (0x4U) | ||
| 15537 | #define SDIF_RINTSTS_CDONE_SHIFT (2U) | ||
| 15538 | /*! CDONE - Command done. | ||
| 15539 | */ | ||
| 15540 | #define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) | ||
| 15541 | #define SDIF_RINTSTS_DTO_MASK (0x8U) | ||
| 15542 | #define SDIF_RINTSTS_DTO_SHIFT (3U) | ||
| 15543 | /*! DTO - Data transfer over. | ||
| 15544 | */ | ||
| 15545 | #define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) | ||
| 15546 | #define SDIF_RINTSTS_TXDR_MASK (0x10U) | ||
| 15547 | #define SDIF_RINTSTS_TXDR_SHIFT (4U) | ||
| 15548 | /*! TXDR - Transmit FIFO data request. | ||
| 15549 | */ | ||
| 15550 | #define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) | ||
| 15551 | #define SDIF_RINTSTS_RXDR_MASK (0x20U) | ||
| 15552 | #define SDIF_RINTSTS_RXDR_SHIFT (5U) | ||
| 15553 | /*! RXDR - Receive FIFO data request. | ||
| 15554 | */ | ||
| 15555 | #define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) | ||
| 15556 | #define SDIF_RINTSTS_RCRC_MASK (0x40U) | ||
| 15557 | #define SDIF_RINTSTS_RCRC_SHIFT (6U) | ||
| 15558 | /*! RCRC - Response CRC error. | ||
| 15559 | */ | ||
| 15560 | #define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) | ||
| 15561 | #define SDIF_RINTSTS_DCRC_MASK (0x80U) | ||
| 15562 | #define SDIF_RINTSTS_DCRC_SHIFT (7U) | ||
| 15563 | /*! DCRC - Data CRC error. | ||
| 15564 | */ | ||
| 15565 | #define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) | ||
| 15566 | #define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) | ||
| 15567 | #define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) | ||
| 15568 | /*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). | ||
| 15569 | */ | ||
| 15570 | #define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) | ||
| 15571 | #define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) | ||
| 15572 | #define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) | ||
| 15573 | /*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). | ||
| 15574 | */ | ||
| 15575 | #define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) | ||
| 15576 | #define SDIF_RINTSTS_HTO_MASK (0x400U) | ||
| 15577 | #define SDIF_RINTSTS_HTO_SHIFT (10U) | ||
| 15578 | /*! HTO - Data starvation-by-host time-out (HTO). | ||
| 15579 | */ | ||
| 15580 | #define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) | ||
| 15581 | #define SDIF_RINTSTS_FRUN_MASK (0x800U) | ||
| 15582 | #define SDIF_RINTSTS_FRUN_SHIFT (11U) | ||
| 15583 | /*! FRUN - FIFO underrun/overrun error. | ||
| 15584 | */ | ||
| 15585 | #define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) | ||
| 15586 | #define SDIF_RINTSTS_HLE_MASK (0x1000U) | ||
| 15587 | #define SDIF_RINTSTS_HLE_SHIFT (12U) | ||
| 15588 | /*! HLE - Hardware locked write error. | ||
| 15589 | */ | ||
| 15590 | #define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) | ||
| 15591 | #define SDIF_RINTSTS_SBE_MASK (0x2000U) | ||
| 15592 | #define SDIF_RINTSTS_SBE_SHIFT (13U) | ||
| 15593 | /*! SBE - Start-bit error. | ||
| 15594 | */ | ||
| 15595 | #define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) | ||
| 15596 | #define SDIF_RINTSTS_ACD_MASK (0x4000U) | ||
| 15597 | #define SDIF_RINTSTS_ACD_SHIFT (14U) | ||
| 15598 | /*! ACD - Auto command done. | ||
| 15599 | */ | ||
| 15600 | #define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) | ||
| 15601 | #define SDIF_RINTSTS_EBE_MASK (0x8000U) | ||
| 15602 | #define SDIF_RINTSTS_EBE_SHIFT (15U) | ||
| 15603 | /*! EBE - End-bit error (read)/write no CRC. | ||
| 15604 | */ | ||
| 15605 | #define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) | ||
| 15606 | #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) | ||
| 15607 | #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) | ||
| 15608 | /*! SDIO_INTERRUPT - Interrupt from SDIO card. | ||
| 15609 | */ | ||
| 15610 | #define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) | ||
| 15611 | /*! @} */ | ||
| 15612 | |||
| 15613 | /*! @name STATUS - Status register */ | ||
| 15614 | /*! @{ */ | ||
| 15615 | #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) | ||
| 15616 | #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) | ||
| 15617 | /*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. | ||
| 15618 | */ | ||
| 15619 | #define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) | ||
| 15620 | #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) | ||
| 15621 | #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) | ||
| 15622 | /*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. | ||
| 15623 | */ | ||
| 15624 | #define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) | ||
| 15625 | #define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) | ||
| 15626 | #define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) | ||
| 15627 | /*! FIFO_EMPTY - FIFO is empty status. | ||
| 15628 | */ | ||
| 15629 | #define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) | ||
| 15630 | #define SDIF_STATUS_FIFO_FULL_MASK (0x8U) | ||
| 15631 | #define SDIF_STATUS_FIFO_FULL_SHIFT (3U) | ||
| 15632 | /*! FIFO_FULL - FIFO is full status. | ||
| 15633 | */ | ||
| 15634 | #define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) | ||
| 15635 | #define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) | ||
| 15636 | #define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) | ||
| 15637 | /*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx | ||
| 15638 | * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - | ||
| 15639 | * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp | ||
| 15640 | * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The | ||
| 15641 | * command FSM state is represented using 19 bits. | ||
| 15642 | */ | ||
| 15643 | #define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) | ||
| 15644 | #define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) | ||
| 15645 | #define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) | ||
| 15646 | /*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. | ||
| 15647 | */ | ||
| 15648 | #define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) | ||
| 15649 | #define SDIF_STATUS_DATA_BUSY_MASK (0x200U) | ||
| 15650 | #define SDIF_STATUS_DATA_BUSY_SHIFT (9U) | ||
| 15651 | /*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. | ||
| 15652 | */ | ||
| 15653 | #define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) | ||
| 15654 | #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) | ||
| 15655 | #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) | ||
| 15656 | /*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. | ||
| 15657 | */ | ||
| 15658 | #define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) | ||
| 15659 | #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) | ||
| 15660 | #define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) | ||
| 15661 | /*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. | ||
| 15662 | */ | ||
| 15663 | #define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) | ||
| 15664 | #define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) | ||
| 15665 | #define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) | ||
| 15666 | /*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. | ||
| 15667 | */ | ||
| 15668 | #define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) | ||
| 15669 | #define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) | ||
| 15670 | #define SDIF_STATUS_DMA_ACK_SHIFT (30U) | ||
| 15671 | /*! DMA_ACK - DMA acknowledge signal state. | ||
| 15672 | */ | ||
| 15673 | #define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) | ||
| 15674 | #define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) | ||
| 15675 | #define SDIF_STATUS_DMA_REQ_SHIFT (31U) | ||
| 15676 | /*! DMA_REQ - DMA request signal state. | ||
| 15677 | */ | ||
| 15678 | #define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) | ||
| 15679 | /*! @} */ | ||
| 15680 | |||
| 15681 | /*! @name FIFOTH - FIFO Threshold Watermark register */ | ||
| 15682 | /*! @{ */ | ||
| 15683 | #define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) | ||
| 15684 | #define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) | ||
| 15685 | /*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. | ||
| 15686 | */ | ||
| 15687 | #define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) | ||
| 15688 | #define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) | ||
| 15689 | #define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) | ||
| 15690 | /*! RX_WMARK - FIFO threshold watermark level when receiving data to card. | ||
| 15691 | */ | ||
| 15692 | #define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) | ||
| 15693 | #define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) | ||
| 15694 | #define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) | ||
| 15695 | /*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller | ||
| 15696 | * multiple-transaction-size SRC/DEST_MSIZE. | ||
| 15697 | */ | ||
| 15698 | #define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) | ||
| 15699 | /*! @} */ | ||
| 15700 | |||
| 15701 | /*! @name CDETECT - Card Detect register */ | ||
| 15702 | /*! @{ */ | ||
| 15703 | #define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) | ||
| 15704 | #define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) | ||
| 15705 | /*! CARD0_DETECT - Card 0 detect | ||
| 15706 | */ | ||
| 15707 | #define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) | ||
| 15708 | #define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) | ||
| 15709 | #define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) | ||
| 15710 | /*! CARD1_DETECT - Card 1 detect | ||
| 15711 | */ | ||
| 15712 | #define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) | ||
| 15713 | /*! @} */ | ||
| 15714 | |||
| 15715 | /*! @name WRTPRT - Write Protect register */ | ||
| 15716 | /*! @{ */ | ||
| 15717 | #define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) | ||
| 15718 | #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) | ||
| 15719 | /*! WRITE_PROTECT - Write protect. | ||
| 15720 | */ | ||
| 15721 | #define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) | ||
| 15722 | /*! @} */ | ||
| 15723 | |||
| 15724 | /*! @name TCBCNT - Transferred CIU Card Byte Count register */ | ||
| 15725 | /*! @{ */ | ||
| 15726 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) | ||
| 15727 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) | ||
| 15728 | /*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. | ||
| 15729 | */ | ||
| 15730 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) | ||
| 15731 | /*! @} */ | ||
| 15732 | |||
| 15733 | /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ | ||
| 15734 | /*! @{ */ | ||
| 15735 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) | ||
| 15736 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) | ||
| 15737 | /*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. | ||
| 15738 | */ | ||
| 15739 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) | ||
| 15740 | /*! @} */ | ||
| 15741 | |||
| 15742 | /*! @name DEBNCE - Debounce Count register */ | ||
| 15743 | /*! @{ */ | ||
| 15744 | #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) | ||
| 15745 | #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) | ||
| 15746 | /*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. | ||
| 15747 | */ | ||
| 15748 | #define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) | ||
| 15749 | /*! @} */ | ||
| 15750 | |||
| 15751 | /*! @name RST_N - Hardware Reset */ | ||
| 15752 | /*! @{ */ | ||
| 15753 | #define SDIF_RST_N_CARD_RESET_MASK (0x1U) | ||
| 15754 | #define SDIF_RST_N_CARD_RESET_SHIFT (0U) | ||
| 15755 | /*! CARD_RESET - Hardware reset. | ||
| 15756 | */ | ||
| 15757 | #define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) | ||
| 15758 | /*! @} */ | ||
| 15759 | |||
| 15760 | /*! @name BMOD - Bus Mode register */ | ||
| 15761 | /*! @{ */ | ||
| 15762 | #define SDIF_BMOD_SWR_MASK (0x1U) | ||
| 15763 | #define SDIF_BMOD_SWR_SHIFT (0U) | ||
| 15764 | /*! SWR - Software Reset. | ||
| 15765 | */ | ||
| 15766 | #define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) | ||
| 15767 | #define SDIF_BMOD_FB_MASK (0x2U) | ||
| 15768 | #define SDIF_BMOD_FB_SHIFT (1U) | ||
| 15769 | /*! FB - Fixed Burst. | ||
| 15770 | */ | ||
| 15771 | #define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) | ||
| 15772 | #define SDIF_BMOD_DSL_MASK (0x7CU) | ||
| 15773 | #define SDIF_BMOD_DSL_SHIFT (2U) | ||
| 15774 | /*! DSL - Descriptor Skip Length. | ||
| 15775 | */ | ||
| 15776 | #define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) | ||
| 15777 | #define SDIF_BMOD_DE_MASK (0x80U) | ||
| 15778 | #define SDIF_BMOD_DE_SHIFT (7U) | ||
| 15779 | /*! DE - SD/MMC DMA Enable. | ||
| 15780 | */ | ||
| 15781 | #define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) | ||
| 15782 | #define SDIF_BMOD_PBL_MASK (0x700U) | ||
| 15783 | #define SDIF_BMOD_PBL_SHIFT (8U) | ||
| 15784 | /*! PBL - Programmable Burst Length. | ||
| 15785 | */ | ||
| 15786 | #define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) | ||
| 15787 | /*! @} */ | ||
| 15788 | |||
| 15789 | /*! @name PLDMND - Poll Demand register */ | ||
| 15790 | /*! @{ */ | ||
| 15791 | #define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) | ||
| 15792 | #define SDIF_PLDMND_PD_SHIFT (0U) | ||
| 15793 | /*! PD - Poll Demand. | ||
| 15794 | */ | ||
| 15795 | #define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) | ||
| 15796 | /*! @} */ | ||
| 15797 | |||
| 15798 | /*! @name DBADDR - Descriptor List Base Address register */ | ||
| 15799 | /*! @{ */ | ||
| 15800 | #define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) | ||
| 15801 | #define SDIF_DBADDR_SDL_SHIFT (0U) | ||
| 15802 | /*! SDL - Start of Descriptor List. | ||
| 15803 | */ | ||
| 15804 | #define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) | ||
| 15805 | /*! @} */ | ||
| 15806 | |||
| 15807 | /*! @name IDSTS - Internal DMAC Status register */ | ||
| 15808 | /*! @{ */ | ||
| 15809 | #define SDIF_IDSTS_TI_MASK (0x1U) | ||
| 15810 | #define SDIF_IDSTS_TI_SHIFT (0U) | ||
| 15811 | /*! TI - Transmit Interrupt. | ||
| 15812 | */ | ||
| 15813 | #define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) | ||
| 15814 | #define SDIF_IDSTS_RI_MASK (0x2U) | ||
| 15815 | #define SDIF_IDSTS_RI_SHIFT (1U) | ||
| 15816 | /*! RI - Receive Interrupt. | ||
| 15817 | */ | ||
| 15818 | #define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) | ||
| 15819 | #define SDIF_IDSTS_FBE_MASK (0x4U) | ||
| 15820 | #define SDIF_IDSTS_FBE_SHIFT (2U) | ||
| 15821 | /*! FBE - Fatal Bus Error Interrupt. | ||
| 15822 | */ | ||
| 15823 | #define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) | ||
| 15824 | #define SDIF_IDSTS_DU_MASK (0x10U) | ||
| 15825 | #define SDIF_IDSTS_DU_SHIFT (4U) | ||
| 15826 | /*! DU - Descriptor Unavailable Interrupt. | ||
| 15827 | */ | ||
| 15828 | #define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) | ||
| 15829 | #define SDIF_IDSTS_CES_MASK (0x20U) | ||
| 15830 | #define SDIF_IDSTS_CES_SHIFT (5U) | ||
| 15831 | /*! CES - Card Error Summary. | ||
| 15832 | */ | ||
| 15833 | #define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) | ||
| 15834 | #define SDIF_IDSTS_NIS_MASK (0x100U) | ||
| 15835 | #define SDIF_IDSTS_NIS_SHIFT (8U) | ||
| 15836 | /*! NIS - Normal Interrupt Summary. | ||
| 15837 | */ | ||
| 15838 | #define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) | ||
| 15839 | #define SDIF_IDSTS_AIS_MASK (0x200U) | ||
| 15840 | #define SDIF_IDSTS_AIS_SHIFT (9U) | ||
| 15841 | /*! AIS - Abnormal Interrupt Summary. | ||
| 15842 | */ | ||
| 15843 | #define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) | ||
| 15844 | #define SDIF_IDSTS_EB_MASK (0x1C00U) | ||
| 15845 | #define SDIF_IDSTS_EB_SHIFT (10U) | ||
| 15846 | /*! EB - Error Bits. | ||
| 15847 | */ | ||
| 15848 | #define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) | ||
| 15849 | #define SDIF_IDSTS_FSM_MASK (0x1E000U) | ||
| 15850 | #define SDIF_IDSTS_FSM_SHIFT (13U) | ||
| 15851 | /*! FSM - DMAC state machine present state. | ||
| 15852 | */ | ||
| 15853 | #define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) | ||
| 15854 | /*! @} */ | ||
| 15855 | |||
| 15856 | /*! @name IDINTEN - Internal DMAC Interrupt Enable register */ | ||
| 15857 | /*! @{ */ | ||
| 15858 | #define SDIF_IDINTEN_TI_MASK (0x1U) | ||
| 15859 | #define SDIF_IDINTEN_TI_SHIFT (0U) | ||
| 15860 | /*! TI - Transmit Interrupt Enable. | ||
| 15861 | */ | ||
| 15862 | #define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) | ||
| 15863 | #define SDIF_IDINTEN_RI_MASK (0x2U) | ||
| 15864 | #define SDIF_IDINTEN_RI_SHIFT (1U) | ||
| 15865 | /*! RI - Receive Interrupt Enable. | ||
| 15866 | */ | ||
| 15867 | #define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) | ||
| 15868 | #define SDIF_IDINTEN_FBE_MASK (0x4U) | ||
| 15869 | #define SDIF_IDINTEN_FBE_SHIFT (2U) | ||
| 15870 | /*! FBE - Fatal Bus Error Enable. | ||
| 15871 | */ | ||
| 15872 | #define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) | ||
| 15873 | #define SDIF_IDINTEN_DU_MASK (0x10U) | ||
| 15874 | #define SDIF_IDINTEN_DU_SHIFT (4U) | ||
| 15875 | /*! DU - Descriptor Unavailable Interrupt. | ||
| 15876 | */ | ||
| 15877 | #define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) | ||
| 15878 | #define SDIF_IDINTEN_CES_MASK (0x20U) | ||
| 15879 | #define SDIF_IDINTEN_CES_SHIFT (5U) | ||
| 15880 | /*! CES - Card Error summary Interrupt Enable. | ||
| 15881 | */ | ||
| 15882 | #define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) | ||
| 15883 | #define SDIF_IDINTEN_NIS_MASK (0x100U) | ||
| 15884 | #define SDIF_IDINTEN_NIS_SHIFT (8U) | ||
| 15885 | /*! NIS - Normal Interrupt Summary Enable. | ||
| 15886 | */ | ||
| 15887 | #define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) | ||
| 15888 | #define SDIF_IDINTEN_AIS_MASK (0x200U) | ||
| 15889 | #define SDIF_IDINTEN_AIS_SHIFT (9U) | ||
| 15890 | /*! AIS - Abnormal Interrupt Summary Enable. | ||
| 15891 | */ | ||
| 15892 | #define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) | ||
| 15893 | /*! @} */ | ||
| 15894 | |||
| 15895 | /*! @name DSCADDR - Current Host Descriptor Address register */ | ||
| 15896 | /*! @{ */ | ||
| 15897 | #define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) | ||
| 15898 | #define SDIF_DSCADDR_HDA_SHIFT (0U) | ||
| 15899 | /*! HDA - Host Descriptor Address Pointer. | ||
| 15900 | */ | ||
| 15901 | #define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) | ||
| 15902 | /*! @} */ | ||
| 15903 | |||
| 15904 | /*! @name BUFADDR - Current Buffer Descriptor Address register */ | ||
| 15905 | /*! @{ */ | ||
| 15906 | #define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) | ||
| 15907 | #define SDIF_BUFADDR_HBA_SHIFT (0U) | ||
| 15908 | /*! HBA - Host Buffer Address Pointer. | ||
| 15909 | */ | ||
| 15910 | #define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) | ||
| 15911 | /*! @} */ | ||
| 15912 | |||
| 15913 | /*! @name CARDTHRCTL - Card Threshold Control */ | ||
| 15914 | /*! @{ */ | ||
| 15915 | #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) | ||
| 15916 | #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) | ||
| 15917 | /*! CARDRDTHREN - Card Read Threshold Enable. | ||
| 15918 | */ | ||
| 15919 | #define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) | ||
| 15920 | #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) | ||
| 15921 | #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) | ||
| 15922 | /*! BSYCLRINTEN - Busy Clear Interrupt Enable. | ||
| 15923 | */ | ||
| 15924 | #define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) | ||
| 15925 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) | ||
| 15926 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) | ||
| 15927 | /*! CARDTHRESHOLD - Card Threshold size. | ||
| 15928 | */ | ||
| 15929 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) | ||
| 15930 | /*! @} */ | ||
| 15931 | |||
| 15932 | /*! @name BACKENDPWR - Power control */ | ||
| 15933 | /*! @{ */ | ||
| 15934 | #define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) | ||
| 15935 | #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) | ||
| 15936 | /*! BACKENDPWR - Back-end Power control for card application. | ||
| 15937 | */ | ||
| 15938 | #define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) | ||
| 15939 | /*! @} */ | ||
| 15940 | |||
| 15941 | /*! @name FIFO - SDIF FIFO */ | ||
| 15942 | /*! @{ */ | ||
| 15943 | #define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) | ||
| 15944 | #define SDIF_FIFO_DATA_SHIFT (0U) | ||
| 15945 | /*! DATA - SDIF FIFO. | ||
| 15946 | */ | ||
| 15947 | #define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) | ||
| 15948 | /*! @} */ | ||
| 15949 | |||
| 15950 | /* The count of SDIF_FIFO */ | ||
| 15951 | #define SDIF_FIFO_COUNT (64U) | ||
| 15952 | |||
| 15953 | |||
| 15954 | /*! | ||
| 15955 | * @} | ||
| 15956 | */ /* end of group SDIF_Register_Masks */ | ||
| 15957 | |||
| 15958 | |||
| 15959 | /* SDIF - Peripheral instance base addresses */ | ||
| 15960 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 15961 | /** Peripheral SDIF base address */ | ||
| 15962 | #define SDIF_BASE (0x5009B000u) | ||
| 15963 | /** Peripheral SDIF base address */ | ||
| 15964 | #define SDIF_BASE_NS (0x4009B000u) | ||
| 15965 | /** Peripheral SDIF base pointer */ | ||
| 15966 | #define SDIF ((SDIF_Type *)SDIF_BASE) | ||
| 15967 | /** Peripheral SDIF base pointer */ | ||
| 15968 | #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) | ||
| 15969 | /** Array initializer of SDIF peripheral base addresses */ | ||
| 15970 | #define SDIF_BASE_ADDRS { SDIF_BASE } | ||
| 15971 | /** Array initializer of SDIF peripheral base pointers */ | ||
| 15972 | #define SDIF_BASE_PTRS { SDIF } | ||
| 15973 | /** Array initializer of SDIF peripheral base addresses */ | ||
| 15974 | #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } | ||
| 15975 | /** Array initializer of SDIF peripheral base pointers */ | ||
| 15976 | #define SDIF_BASE_PTRS_NS { SDIF_NS } | ||
| 15977 | #else | ||
| 15978 | /** Peripheral SDIF base address */ | ||
| 15979 | #define SDIF_BASE (0x4009B000u) | ||
| 15980 | /** Peripheral SDIF base pointer */ | ||
| 15981 | #define SDIF ((SDIF_Type *)SDIF_BASE) | ||
| 15982 | /** Array initializer of SDIF peripheral base addresses */ | ||
| 15983 | #define SDIF_BASE_ADDRS { SDIF_BASE } | ||
| 15984 | /** Array initializer of SDIF peripheral base pointers */ | ||
| 15985 | #define SDIF_BASE_PTRS { SDIF } | ||
| 15986 | #endif | ||
| 15987 | /** Interrupt vectors for the SDIF peripheral type */ | ||
| 15988 | #define SDIF_IRQS { SDIO_IRQn } | ||
| 15989 | |||
| 15990 | /*! | ||
| 15991 | * @} | ||
| 15992 | */ /* end of group SDIF_Peripheral_Access_Layer */ | ||
| 15993 | |||
| 15994 | |||
| 15995 | /* ---------------------------------------------------------------------------- | ||
| 15996 | -- SPI Peripheral Access Layer | ||
| 15997 | ---------------------------------------------------------------------------- */ | ||
| 15998 | |||
| 15999 | /*! | ||
| 16000 | * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer | ||
| 16001 | * @{ | ||
| 16002 | */ | ||
| 16003 | |||
| 16004 | /** SPI - Register Layout Typedef */ | ||
| 16005 | typedef struct { | ||
| 16006 | uint8_t RESERVED_0[1024]; | ||
| 16007 | __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ | ||
| 16008 | __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ | ||
| 16009 | __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ | ||
| 16010 | __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ | ||
| 16011 | __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ | ||
| 16012 | uint8_t RESERVED_1[16]; | ||
| 16013 | __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ | ||
| 16014 | __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ | ||
| 16015 | uint8_t RESERVED_2[2516]; | ||
| 16016 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ | ||
| 16017 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ | ||
| 16018 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ | ||
| 16019 | uint8_t RESERVED_3[4]; | ||
| 16020 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ | ||
| 16021 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ | ||
| 16022 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ | ||
| 16023 | uint8_t RESERVED_4[4]; | ||
| 16024 | __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ | ||
| 16025 | uint8_t RESERVED_5[12]; | ||
| 16026 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ | ||
| 16027 | uint8_t RESERVED_6[12]; | ||
| 16028 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ | ||
| 16029 | uint8_t RESERVED_7[440]; | ||
| 16030 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ | ||
| 16031 | } SPI_Type; | ||
| 16032 | |||
| 16033 | /* ---------------------------------------------------------------------------- | ||
| 16034 | -- SPI Register Masks | ||
| 16035 | ---------------------------------------------------------------------------- */ | ||
| 16036 | |||
| 16037 | /*! | ||
| 16038 | * @addtogroup SPI_Register_Masks SPI Register Masks | ||
| 16039 | * @{ | ||
| 16040 | */ | ||
| 16041 | |||
| 16042 | /*! @name CFG - SPI Configuration register */ | ||
| 16043 | /*! @{ */ | ||
| 16044 | #define SPI_CFG_ENABLE_MASK (0x1U) | ||
| 16045 | #define SPI_CFG_ENABLE_SHIFT (0U) | ||
| 16046 | /*! ENABLE - SPI enable. | ||
| 16047 | * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. | ||
| 16048 | * 0b1..Enabled. The SPI is enabled for operation. | ||
| 16049 | */ | ||
| 16050 | #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) | ||
| 16051 | #define SPI_CFG_MASTER_MASK (0x4U) | ||
| 16052 | #define SPI_CFG_MASTER_SHIFT (2U) | ||
| 16053 | /*! MASTER - Master mode select. | ||
| 16054 | * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. | ||
| 16055 | * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. | ||
| 16056 | */ | ||
| 16057 | #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) | ||
| 16058 | #define SPI_CFG_LSBF_MASK (0x8U) | ||
| 16059 | #define SPI_CFG_LSBF_SHIFT (3U) | ||
| 16060 | /*! LSBF - LSB First mode enable. | ||
| 16061 | * 0b0..Standard. Data is transmitted and received in standard MSB first order. | ||
| 16062 | * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). | ||
| 16063 | */ | ||
| 16064 | #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) | ||
| 16065 | #define SPI_CFG_CPHA_MASK (0x10U) | ||
| 16066 | #define SPI_CFG_CPHA_SHIFT (4U) | ||
| 16067 | /*! CPHA - Clock Phase select. | ||
| 16068 | * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock | ||
| 16069 | * changes away from the rest state). Data is changed on the following edge. | ||
| 16070 | * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock | ||
| 16071 | * changes away from the rest state). Data is captured on the following edge. | ||
| 16072 | */ | ||
| 16073 | #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) | ||
| 16074 | #define SPI_CFG_CPOL_MASK (0x20U) | ||
| 16075 | #define SPI_CFG_CPOL_SHIFT (5U) | ||
| 16076 | /*! CPOL - Clock Polarity select. | ||
| 16077 | * 0b0..Low. The rest state of the clock (between transfers) is low. | ||
| 16078 | * 0b1..High. The rest state of the clock (between transfers) is high. | ||
| 16079 | */ | ||
| 16080 | #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) | ||
| 16081 | #define SPI_CFG_LOOP_MASK (0x80U) | ||
| 16082 | #define SPI_CFG_LOOP_SHIFT (7U) | ||
| 16083 | /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit | ||
| 16084 | * and receive data connected together to allow simple software testing. | ||
| 16085 | * 0b0..Disabled. | ||
| 16086 | * 0b1..Enabled. | ||
| 16087 | */ | ||
| 16088 | #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) | ||
| 16089 | #define SPI_CFG_SPOL0_MASK (0x100U) | ||
| 16090 | #define SPI_CFG_SPOL0_SHIFT (8U) | ||
| 16091 | /*! SPOL0 - SSEL0 Polarity select. | ||
| 16092 | * 0b0..Low. The SSEL0 pin is active low. | ||
| 16093 | * 0b1..High. The SSEL0 pin is active high. | ||
| 16094 | */ | ||
| 16095 | #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) | ||
| 16096 | #define SPI_CFG_SPOL1_MASK (0x200U) | ||
| 16097 | #define SPI_CFG_SPOL1_SHIFT (9U) | ||
| 16098 | /*! SPOL1 - SSEL1 Polarity select. | ||
| 16099 | * 0b0..Low. The SSEL1 pin is active low. | ||
| 16100 | * 0b1..High. The SSEL1 pin is active high. | ||
| 16101 | */ | ||
| 16102 | #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) | ||
| 16103 | #define SPI_CFG_SPOL2_MASK (0x400U) | ||
| 16104 | #define SPI_CFG_SPOL2_SHIFT (10U) | ||
| 16105 | /*! SPOL2 - SSEL2 Polarity select. | ||
| 16106 | * 0b0..Low. The SSEL2 pin is active low. | ||
| 16107 | * 0b1..High. The SSEL2 pin is active high. | ||
| 16108 | */ | ||
| 16109 | #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) | ||
| 16110 | #define SPI_CFG_SPOL3_MASK (0x800U) | ||
| 16111 | #define SPI_CFG_SPOL3_SHIFT (11U) | ||
| 16112 | /*! SPOL3 - SSEL3 Polarity select. | ||
| 16113 | * 0b0..Low. The SSEL3 pin is active low. | ||
| 16114 | * 0b1..High. The SSEL3 pin is active high. | ||
| 16115 | */ | ||
| 16116 | #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) | ||
| 16117 | /*! @} */ | ||
| 16118 | |||
| 16119 | /*! @name DLY - SPI Delay register */ | ||
| 16120 | /*! @{ */ | ||
| 16121 | #define SPI_DLY_PRE_DELAY_MASK (0xFU) | ||
| 16122 | #define SPI_DLY_PRE_DELAY_SHIFT (0U) | ||
| 16123 | /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data | ||
| 16124 | * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This | ||
| 16125 | * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI | ||
| 16126 | * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are | ||
| 16127 | * inserted. | ||
| 16128 | */ | ||
| 16129 | #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) | ||
| 16130 | #define SPI_DLY_POST_DELAY_MASK (0xF0U) | ||
| 16131 | #define SPI_DLY_POST_DELAY_SHIFT (4U) | ||
| 16132 | /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL | ||
| 16133 | * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock | ||
| 16134 | * times are inserted. 0xF = 15 SPI clock times are inserted. | ||
| 16135 | */ | ||
| 16136 | #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) | ||
| 16137 | #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) | ||
| 16138 | #define SPI_DLY_FRAME_DELAY_SHIFT (8U) | ||
| 16139 | /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current | ||
| 16140 | * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 | ||
| 16141 | * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock | ||
| 16142 | * times are inserted. | ||
| 16143 | */ | ||
| 16144 | #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) | ||
| 16145 | #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) | ||
| 16146 | #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) | ||
| 16147 | /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between | ||
| 16148 | * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 | ||
| 16149 | * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that | ||
| 16150 | * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 | ||
| 16151 | * SPI clock times. | ||
| 16152 | */ | ||
| 16153 | #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) | ||
| 16154 | /*! @} */ | ||
| 16155 | |||
| 16156 | /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ | ||
| 16157 | /*! @{ */ | ||
| 16158 | #define SPI_STAT_SSA_MASK (0x10U) | ||
| 16159 | #define SPI_STAT_SSA_SHIFT (4U) | ||
| 16160 | /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from | ||
| 16161 | * deasserted to asserted, in both master and slave modes. This allows determining when the SPI | ||
| 16162 | * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a | ||
| 16163 | * slave mode access begins. This flag is cleared by software. | ||
| 16164 | */ | ||
| 16165 | #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) | ||
| 16166 | #define SPI_STAT_SSD_MASK (0x20U) | ||
| 16167 | #define SPI_STAT_SSD_SHIFT (5U) | ||
| 16168 | /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to | ||
| 16169 | * deasserted, in both master and slave modes. This allows determining when the SPI | ||
| 16170 | * transmit/receive functions become idle. This flag is cleared by software. | ||
| 16171 | */ | ||
| 16172 | #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) | ||
| 16173 | #define SPI_STAT_STALLED_MASK (0x40U) | ||
| 16174 | #define SPI_STAT_STALLED_SHIFT (6U) | ||
| 16175 | /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. | ||
| 16176 | */ | ||
| 16177 | #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) | ||
| 16178 | #define SPI_STAT_ENDTRANSFER_MASK (0x80U) | ||
| 16179 | #define SPI_STAT_ENDTRANSFER_SHIFT (7U) | ||
| 16180 | /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current | ||
| 16181 | * transfer when the transmitter finishes any activity already in progress, as if the EOT flag | ||
| 16182 | * had been set prior to the last transmission. This capability is included to support cases where | ||
| 16183 | * it is not known when transmit data is written that it will be the end of a transfer. The bit | ||
| 16184 | * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end | ||
| 16185 | * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. | ||
| 16186 | */ | ||
| 16187 | #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) | ||
| 16188 | #define SPI_STAT_MSTIDLE_MASK (0x100U) | ||
| 16189 | #define SPI_STAT_MSTIDLE_SHIFT (8U) | ||
| 16190 | /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. | ||
| 16191 | * This means that the transmit holding register is empty and the transmitter is not in the | ||
| 16192 | * process of sending data. | ||
| 16193 | */ | ||
| 16194 | #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) | ||
| 16195 | /*! @} */ | ||
| 16196 | |||
| 16197 | /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ | ||
| 16198 | /*! @{ */ | ||
| 16199 | #define SPI_INTENSET_SSAEN_MASK (0x10U) | ||
| 16200 | #define SPI_INTENSET_SSAEN_SHIFT (4U) | ||
| 16201 | /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. | ||
| 16202 | * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. | ||
| 16203 | * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. | ||
| 16204 | */ | ||
| 16205 | #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) | ||
| 16206 | #define SPI_INTENSET_SSDEN_MASK (0x20U) | ||
| 16207 | #define SPI_INTENSET_SSDEN_SHIFT (5U) | ||
| 16208 | /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. | ||
| 16209 | * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. | ||
| 16210 | * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. | ||
| 16211 | */ | ||
| 16212 | #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) | ||
| 16213 | #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) | ||
| 16214 | #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) | ||
| 16215 | /*! MSTIDLEEN - Master idle interrupt enable. | ||
| 16216 | * 0b0..No interrupt will be generated when the SPI master function is idle. | ||
| 16217 | * 0b1..An interrupt will be generated when the SPI master function is fully idle. | ||
| 16218 | */ | ||
| 16219 | #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) | ||
| 16220 | /*! @} */ | ||
| 16221 | |||
| 16222 | /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ | ||
| 16223 | /*! @{ */ | ||
| 16224 | #define SPI_INTENCLR_SSAEN_MASK (0x10U) | ||
| 16225 | #define SPI_INTENCLR_SSAEN_SHIFT (4U) | ||
| 16226 | /*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 16227 | */ | ||
| 16228 | #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) | ||
| 16229 | #define SPI_INTENCLR_SSDEN_MASK (0x20U) | ||
| 16230 | #define SPI_INTENCLR_SSDEN_SHIFT (5U) | ||
| 16231 | /*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 16232 | */ | ||
| 16233 | #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) | ||
| 16234 | #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) | ||
| 16235 | #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) | ||
| 16236 | /*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 16237 | */ | ||
| 16238 | #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) | ||
| 16239 | /*! @} */ | ||
| 16240 | |||
| 16241 | /*! @name DIV - SPI clock Divider */ | ||
| 16242 | /*! @{ */ | ||
| 16243 | #define SPI_DIV_DIVVAL_MASK (0xFFFFU) | ||
| 16244 | #define SPI_DIV_DIVVAL_SHIFT (0U) | ||
| 16245 | /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the | ||
| 16246 | * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, | ||
| 16247 | * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results | ||
| 16248 | * in FCLK/65536. | ||
| 16249 | */ | ||
| 16250 | #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) | ||
| 16251 | /*! @} */ | ||
| 16252 | |||
| 16253 | /*! @name INTSTAT - SPI Interrupt Status */ | ||
| 16254 | /*! @{ */ | ||
| 16255 | #define SPI_INTSTAT_SSA_MASK (0x10U) | ||
| 16256 | #define SPI_INTSTAT_SSA_SHIFT (4U) | ||
| 16257 | /*! SSA - Slave Select Assert. | ||
| 16258 | */ | ||
| 16259 | #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) | ||
| 16260 | #define SPI_INTSTAT_SSD_MASK (0x20U) | ||
| 16261 | #define SPI_INTSTAT_SSD_SHIFT (5U) | ||
| 16262 | /*! SSD - Slave Select Deassert. | ||
| 16263 | */ | ||
| 16264 | #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) | ||
| 16265 | #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) | ||
| 16266 | #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) | ||
| 16267 | /*! MSTIDLE - Master Idle status flag. | ||
| 16268 | */ | ||
| 16269 | #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) | ||
| 16270 | /*! @} */ | ||
| 16271 | |||
| 16272 | /*! @name FIFOCFG - FIFO configuration and enable register. */ | ||
| 16273 | /*! @{ */ | ||
| 16274 | #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) | ||
| 16275 | #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) | ||
| 16276 | /*! ENABLETX - Enable the transmit FIFO. | ||
| 16277 | * 0b0..The transmit FIFO is not enabled. | ||
| 16278 | * 0b1..The transmit FIFO is enabled. | ||
| 16279 | */ | ||
| 16280 | #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) | ||
| 16281 | #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) | ||
| 16282 | #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) | ||
| 16283 | /*! ENABLERX - Enable the receive FIFO. | ||
| 16284 | * 0b0..The receive FIFO is not enabled. | ||
| 16285 | * 0b1..The receive FIFO is enabled. | ||
| 16286 | */ | ||
| 16287 | #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) | ||
| 16288 | #define SPI_FIFOCFG_SIZE_MASK (0x30U) | ||
| 16289 | #define SPI_FIFOCFG_SIZE_SHIFT (4U) | ||
| 16290 | /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 | ||
| 16291 | * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. | ||
| 16292 | */ | ||
| 16293 | #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) | ||
| 16294 | #define SPI_FIFOCFG_DMATX_MASK (0x1000U) | ||
| 16295 | #define SPI_FIFOCFG_DMATX_SHIFT (12U) | ||
| 16296 | /*! DMATX - DMA configuration for transmit. | ||
| 16297 | * 0b0..DMA is not used for the transmit function. | ||
| 16298 | * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 16299 | */ | ||
| 16300 | #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) | ||
| 16301 | #define SPI_FIFOCFG_DMARX_MASK (0x2000U) | ||
| 16302 | #define SPI_FIFOCFG_DMARX_SHIFT (13U) | ||
| 16303 | /*! DMARX - DMA configuration for receive. | ||
| 16304 | * 0b0..DMA is not used for the receive function. | ||
| 16305 | * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 16306 | */ | ||
| 16307 | #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) | ||
| 16308 | #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) | ||
| 16309 | #define SPI_FIFOCFG_WAKETX_SHIFT (14U) | ||
| 16310 | /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power | ||
| 16311 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 16312 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 16313 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 16314 | * Wake-up control register. | ||
| 16315 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 16316 | * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in | ||
| 16317 | * FIFOTRIG, even when the TXLVL interrupt is not enabled. | ||
| 16318 | */ | ||
| 16319 | #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) | ||
| 16320 | #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) | ||
| 16321 | #define SPI_FIFOCFG_WAKERX_SHIFT (15U) | ||
| 16322 | /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power | ||
| 16323 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 16324 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 16325 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 16326 | * Wake-up control register. | ||
| 16327 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 16328 | * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in | ||
| 16329 | * FIFOTRIG, even when the RXLVL interrupt is not enabled. | ||
| 16330 | */ | ||
| 16331 | #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) | ||
| 16332 | #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) | ||
| 16333 | #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) | ||
| 16334 | /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. | ||
| 16335 | */ | ||
| 16336 | #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) | ||
| 16337 | #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) | ||
| 16338 | #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) | ||
| 16339 | /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. | ||
| 16340 | */ | ||
| 16341 | #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) | ||
| 16342 | /*! @} */ | ||
| 16343 | |||
| 16344 | /*! @name FIFOSTAT - FIFO status register. */ | ||
| 16345 | /*! @{ */ | ||
| 16346 | #define SPI_FIFOSTAT_TXERR_MASK (0x1U) | ||
| 16347 | #define SPI_FIFOSTAT_TXERR_SHIFT (0U) | ||
| 16348 | /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow | ||
| 16349 | * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is | ||
| 16350 | * needed. Cleared by writing a 1 to this bit. | ||
| 16351 | */ | ||
| 16352 | #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) | ||
| 16353 | #define SPI_FIFOSTAT_RXERR_MASK (0x2U) | ||
| 16354 | #define SPI_FIFOSTAT_RXERR_SHIFT (1U) | ||
| 16355 | /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA | ||
| 16356 | * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. | ||
| 16357 | */ | ||
| 16358 | #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) | ||
| 16359 | #define SPI_FIFOSTAT_PERINT_MASK (0x8U) | ||
| 16360 | #define SPI_FIFOSTAT_PERINT_SHIFT (3U) | ||
| 16361 | /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted | ||
| 16362 | * an interrupt. The details can be found by reading the peripheral's STAT register. | ||
| 16363 | */ | ||
| 16364 | #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) | ||
| 16365 | #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) | ||
| 16366 | #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) | ||
| 16367 | /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. | ||
| 16368 | */ | ||
| 16369 | #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) | ||
| 16370 | #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) | ||
| 16371 | #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) | ||
| 16372 | /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be | ||
| 16373 | * written. When 0, the transmit FIFO is full and another write would cause it to overflow. | ||
| 16374 | */ | ||
| 16375 | #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) | ||
| 16376 | #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) | ||
| 16377 | #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) | ||
| 16378 | /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. | ||
| 16379 | */ | ||
| 16380 | #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) | ||
| 16381 | #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) | ||
| 16382 | #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) | ||
| 16383 | /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to | ||
| 16384 | * prevent the peripheral from causing an overflow. | ||
| 16385 | */ | ||
| 16386 | #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) | ||
| 16387 | #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) | ||
| 16388 | #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) | ||
| 16389 | /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY | ||
| 16390 | * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at | ||
| 16391 | * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be | ||
| 16392 | * 0. | ||
| 16393 | */ | ||
| 16394 | #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) | ||
| 16395 | #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) | ||
| 16396 | #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) | ||
| 16397 | /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and | ||
| 16398 | * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the | ||
| 16399 | * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be | ||
| 16400 | * 1. | ||
| 16401 | */ | ||
| 16402 | #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) | ||
| 16403 | /*! @} */ | ||
| 16404 | |||
| 16405 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ | ||
| 16406 | /*! @{ */ | ||
| 16407 | #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) | ||
| 16408 | #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) | ||
| 16409 | /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 16410 | * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. | ||
| 16411 | * 0b0..Transmit FIFO level does not generate a FIFO level trigger. | ||
| 16412 | * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. | ||
| 16413 | */ | ||
| 16414 | #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) | ||
| 16415 | #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) | ||
| 16416 | #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) | ||
| 16417 | /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 16418 | * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. | ||
| 16419 | * 0b0..Receive FIFO level does not generate a FIFO level trigger. | ||
| 16420 | * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. | ||
| 16421 | */ | ||
| 16422 | #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) | ||
| 16423 | #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) | ||
| 16424 | #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) | ||
| 16425 | /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled | ||
| 16426 | * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to | ||
| 16427 | * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO | ||
| 16428 | * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX | ||
| 16429 | * FIFO level decreases to 15 entries (is no longer full). | ||
| 16430 | */ | ||
| 16431 | #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) | ||
| 16432 | #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) | ||
| 16433 | #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) | ||
| 16434 | /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data | ||
| 16435 | * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level | ||
| 16436 | * can wake up the device just enough to perform DMA, then return to the reduced power mode. See | ||
| 16437 | * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no | ||
| 16438 | * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX | ||
| 16439 | * FIFO has received 16 entries (has become full). | ||
| 16440 | */ | ||
| 16441 | #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) | ||
| 16442 | /*! @} */ | ||
| 16443 | |||
| 16444 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ | ||
| 16445 | /*! @{ */ | ||
| 16446 | #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) | ||
| 16447 | #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) | ||
| 16448 | /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. | ||
| 16449 | * 0b0..No interrupt will be generated for a transmit error. | ||
| 16450 | * 0b1..An interrupt will be generated when a transmit error occurs. | ||
| 16451 | */ | ||
| 16452 | #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) | ||
| 16453 | #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) | ||
| 16454 | #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) | ||
| 16455 | /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. | ||
| 16456 | * 0b0..No interrupt will be generated for a receive error. | ||
| 16457 | * 0b1..An interrupt will be generated when a receive error occurs. | ||
| 16458 | */ | ||
| 16459 | #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) | ||
| 16460 | #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) | ||
| 16461 | #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) | ||
| 16462 | /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level | ||
| 16463 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 16464 | * 0b0..No interrupt will be generated based on the TX FIFO level. | ||
| 16465 | * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases | ||
| 16466 | * to the level specified by TXLVL in the FIFOTRIG register. | ||
| 16467 | */ | ||
| 16468 | #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) | ||
| 16469 | #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) | ||
| 16470 | #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) | ||
| 16471 | /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level | ||
| 16472 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 16473 | * 0b0..No interrupt will be generated based on the RX FIFO level. | ||
| 16474 | * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level | ||
| 16475 | * increases to the level specified by RXLVL in the FIFOTRIG register. | ||
| 16476 | */ | ||
| 16477 | #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) | ||
| 16478 | /*! @} */ | ||
| 16479 | |||
| 16480 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ | ||
| 16481 | /*! @{ */ | ||
| 16482 | #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) | ||
| 16483 | #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) | ||
| 16484 | /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 16485 | */ | ||
| 16486 | #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) | ||
| 16487 | #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) | ||
| 16488 | #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) | ||
| 16489 | /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 16490 | */ | ||
| 16491 | #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) | ||
| 16492 | #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) | ||
| 16493 | #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) | ||
| 16494 | /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 16495 | */ | ||
| 16496 | #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) | ||
| 16497 | #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) | ||
| 16498 | #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) | ||
| 16499 | /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 16500 | */ | ||
| 16501 | #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) | ||
| 16502 | /*! @} */ | ||
| 16503 | |||
| 16504 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ | ||
| 16505 | /*! @{ */ | ||
| 16506 | #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) | ||
| 16507 | #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) | ||
| 16508 | /*! TXERR - TX FIFO error. | ||
| 16509 | */ | ||
| 16510 | #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) | ||
| 16511 | #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) | ||
| 16512 | #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) | ||
| 16513 | /*! RXERR - RX FIFO error. | ||
| 16514 | */ | ||
| 16515 | #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) | ||
| 16516 | #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) | ||
| 16517 | #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) | ||
| 16518 | /*! TXLVL - Transmit FIFO level interrupt. | ||
| 16519 | */ | ||
| 16520 | #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) | ||
| 16521 | #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) | ||
| 16522 | #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) | ||
| 16523 | /*! RXLVL - Receive FIFO level interrupt. | ||
| 16524 | */ | ||
| 16525 | #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) | ||
| 16526 | #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) | ||
| 16527 | #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) | ||
| 16528 | /*! PERINT - Peripheral interrupt. | ||
| 16529 | */ | ||
| 16530 | #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) | ||
| 16531 | /*! @} */ | ||
| 16532 | |||
| 16533 | /*! @name FIFOWR - FIFO write data. */ | ||
| 16534 | /*! @{ */ | ||
| 16535 | #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) | ||
| 16536 | #define SPI_FIFOWR_TXDATA_SHIFT (0U) | ||
| 16537 | /*! TXDATA - Transmit data to the FIFO. | ||
| 16538 | */ | ||
| 16539 | #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) | ||
| 16540 | #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) | ||
| 16541 | #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) | ||
| 16542 | /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. | ||
| 16543 | * 0b0..SSEL0 asserted. | ||
| 16544 | * 0b1..SSEL0 not asserted. | ||
| 16545 | */ | ||
| 16546 | #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) | ||
| 16547 | #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) | ||
| 16548 | #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) | ||
| 16549 | /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. | ||
| 16550 | * 0b0..SSEL1 asserted. | ||
| 16551 | * 0b1..SSEL1 not asserted. | ||
| 16552 | */ | ||
| 16553 | #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) | ||
| 16554 | #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) | ||
| 16555 | #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) | ||
| 16556 | /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. | ||
| 16557 | * 0b0..SSEL2 asserted. | ||
| 16558 | * 0b1..SSEL2 not asserted. | ||
| 16559 | */ | ||
| 16560 | #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) | ||
| 16561 | #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) | ||
| 16562 | #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) | ||
| 16563 | /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. | ||
| 16564 | * 0b0..SSEL3 asserted. | ||
| 16565 | * 0b1..SSEL3 not asserted. | ||
| 16566 | */ | ||
| 16567 | #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) | ||
| 16568 | #define SPI_FIFOWR_EOT_MASK (0x100000U) | ||
| 16569 | #define SPI_FIFOWR_EOT_SHIFT (20U) | ||
| 16570 | /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain | ||
| 16571 | * so far at least the time specified by the Transfer_delay value in the DLY register. | ||
| 16572 | * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. | ||
| 16573 | * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. | ||
| 16574 | */ | ||
| 16575 | #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) | ||
| 16576 | #define SPI_FIFOWR_EOF_MASK (0x200000U) | ||
| 16577 | #define SPI_FIFOWR_EOF_SHIFT (21U) | ||
| 16578 | /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value | ||
| 16579 | * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay | ||
| 16580 | * value = 0. This control can be used as part of the support for frame lengths greater than 16 | ||
| 16581 | * bits. | ||
| 16582 | * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. | ||
| 16583 | * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be | ||
| 16584 | * inserted before subsequent data is transmitted. | ||
| 16585 | */ | ||
| 16586 | #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) | ||
| 16587 | #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) | ||
| 16588 | #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) | ||
| 16589 | /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to | ||
| 16590 | * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can | ||
| 16591 | * be used with the DMA. | ||
| 16592 | * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit | ||
| 16593 | * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data | ||
| 16594 | * is not read before new data is received. | ||
| 16595 | * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received | ||
| 16596 | * data. No receiver flags are generated. | ||
| 16597 | */ | ||
| 16598 | #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) | ||
| 16599 | #define SPI_FIFOWR_LEN_MASK (0xF000000U) | ||
| 16600 | #define SPI_FIFOWR_LEN_SHIFT (24U) | ||
| 16601 | /*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths | ||
| 16602 | * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. | ||
| 16603 | * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data | ||
| 16604 | * transfer is 16 bits in length. | ||
| 16605 | */ | ||
| 16606 | #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) | ||
| 16607 | /*! @} */ | ||
| 16608 | |||
| 16609 | /*! @name FIFORD - FIFO read data. */ | ||
| 16610 | /*! @{ */ | ||
| 16611 | #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) | ||
| 16612 | #define SPI_FIFORD_RXDATA_SHIFT (0U) | ||
| 16613 | /*! RXDATA - Received data from the FIFO. | ||
| 16614 | */ | ||
| 16615 | #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) | ||
| 16616 | #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) | ||
| 16617 | #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) | ||
| 16618 | /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved | ||
| 16619 | * along with received data. The value will reflect the SSEL0 pin for both master and slave | ||
| 16620 | * operation. A zero indicates that a slave select is active. The actual polarity of each slave select | ||
| 16621 | * pin is configured by the related SPOL bit in CFG. | ||
| 16622 | */ | ||
| 16623 | #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) | ||
| 16624 | #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) | ||
| 16625 | #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) | ||
| 16626 | /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved | ||
| 16627 | * along with received data. The value will reflect the SSEL1 pin for both master and slave | ||
| 16628 | * operation. A zero indicates that a slave select is active. The actual polarity of each slave select | ||
| 16629 | * pin is configured by the related SPOL bit in CFG. | ||
| 16630 | */ | ||
| 16631 | #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) | ||
| 16632 | #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) | ||
| 16633 | #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) | ||
| 16634 | /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved | ||
| 16635 | * along with received data. The value will reflect the SSEL2 pin for both master and slave | ||
| 16636 | * operation. A zero indicates that a slave select is active. The actual polarity of each slave select | ||
| 16637 | * pin is configured by the related SPOL bit in CFG. | ||
| 16638 | */ | ||
| 16639 | #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) | ||
| 16640 | #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) | ||
| 16641 | #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) | ||
| 16642 | /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved | ||
| 16643 | * along with received data. The value will reflect the SSEL3 pin for both master and slave | ||
| 16644 | * operation. A zero indicates that a slave select is active. The actual polarity of each slave select | ||
| 16645 | * pin is configured by the related SPOL bit in CFG. | ||
| 16646 | */ | ||
| 16647 | #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) | ||
| 16648 | #define SPI_FIFORD_SOT_MASK (0x100000U) | ||
| 16649 | #define SPI_FIFORD_SOT_SHIFT (20U) | ||
| 16650 | /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went | ||
| 16651 | * from deasserted to asserted (i.e., any previous transfer has ended). This information can be | ||
| 16652 | * used to identify the first piece of data in cases where the transfer length is greater than 16 | ||
| 16653 | * bits. | ||
| 16654 | */ | ||
| 16655 | #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) | ||
| 16656 | /*! @} */ | ||
| 16657 | |||
| 16658 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ | ||
| 16659 | /*! @{ */ | ||
| 16660 | #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) | ||
| 16661 | #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) | ||
| 16662 | /*! RXDATA - Received data from the FIFO. | ||
| 16663 | */ | ||
| 16664 | #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) | ||
| 16665 | #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) | ||
| 16666 | #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) | ||
| 16667 | /*! RXSSEL0_N - Slave Select for receive. | ||
| 16668 | */ | ||
| 16669 | #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) | ||
| 16670 | #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) | ||
| 16671 | #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) | ||
| 16672 | /*! RXSSEL1_N - Slave Select for receive. | ||
| 16673 | */ | ||
| 16674 | #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) | ||
| 16675 | #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) | ||
| 16676 | #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) | ||
| 16677 | /*! RXSSEL2_N - Slave Select for receive. | ||
| 16678 | */ | ||
| 16679 | #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) | ||
| 16680 | #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) | ||
| 16681 | #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) | ||
| 16682 | /*! RXSSEL3_N - Slave Select for receive. | ||
| 16683 | */ | ||
| 16684 | #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) | ||
| 16685 | #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) | ||
| 16686 | #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) | ||
| 16687 | /*! SOT - Start of transfer flag. | ||
| 16688 | */ | ||
| 16689 | #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) | ||
| 16690 | /*! @} */ | ||
| 16691 | |||
| 16692 | /*! @name ID - Peripheral identification register. */ | ||
| 16693 | /*! @{ */ | ||
| 16694 | #define SPI_ID_APERTURE_MASK (0xFFU) | ||
| 16695 | #define SPI_ID_APERTURE_SHIFT (0U) | ||
| 16696 | /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. | ||
| 16697 | */ | ||
| 16698 | #define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) | ||
| 16699 | #define SPI_ID_MINOR_REV_MASK (0xF00U) | ||
| 16700 | #define SPI_ID_MINOR_REV_SHIFT (8U) | ||
| 16701 | /*! MINOR_REV - Minor revision of module implementation. | ||
| 16702 | */ | ||
| 16703 | #define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) | ||
| 16704 | #define SPI_ID_MAJOR_REV_MASK (0xF000U) | ||
| 16705 | #define SPI_ID_MAJOR_REV_SHIFT (12U) | ||
| 16706 | /*! MAJOR_REV - Major revision of module implementation. | ||
| 16707 | */ | ||
| 16708 | #define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) | ||
| 16709 | #define SPI_ID_ID_MASK (0xFFFF0000U) | ||
| 16710 | #define SPI_ID_ID_SHIFT (16U) | ||
| 16711 | /*! ID - Module identifier for the selected function. | ||
| 16712 | */ | ||
| 16713 | #define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) | ||
| 16714 | /*! @} */ | ||
| 16715 | |||
| 16716 | |||
| 16717 | /*! | ||
| 16718 | * @} | ||
| 16719 | */ /* end of group SPI_Register_Masks */ | ||
| 16720 | |||
| 16721 | |||
| 16722 | /* SPI - Peripheral instance base addresses */ | ||
| 16723 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 16724 | /** Peripheral SPI0 base address */ | ||
| 16725 | #define SPI0_BASE (0x50086000u) | ||
| 16726 | /** Peripheral SPI0 base address */ | ||
| 16727 | #define SPI0_BASE_NS (0x40086000u) | ||
| 16728 | /** Peripheral SPI0 base pointer */ | ||
| 16729 | #define SPI0 ((SPI_Type *)SPI0_BASE) | ||
| 16730 | /** Peripheral SPI0 base pointer */ | ||
| 16731 | #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) | ||
| 16732 | /** Peripheral SPI1 base address */ | ||
| 16733 | #define SPI1_BASE (0x50087000u) | ||
| 16734 | /** Peripheral SPI1 base address */ | ||
| 16735 | #define SPI1_BASE_NS (0x40087000u) | ||
| 16736 | /** Peripheral SPI1 base pointer */ | ||
| 16737 | #define SPI1 ((SPI_Type *)SPI1_BASE) | ||
| 16738 | /** Peripheral SPI1 base pointer */ | ||
| 16739 | #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) | ||
| 16740 | /** Peripheral SPI2 base address */ | ||
| 16741 | #define SPI2_BASE (0x50088000u) | ||
| 16742 | /** Peripheral SPI2 base address */ | ||
| 16743 | #define SPI2_BASE_NS (0x40088000u) | ||
| 16744 | /** Peripheral SPI2 base pointer */ | ||
| 16745 | #define SPI2 ((SPI_Type *)SPI2_BASE) | ||
| 16746 | /** Peripheral SPI2 base pointer */ | ||
| 16747 | #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) | ||
| 16748 | /** Peripheral SPI3 base address */ | ||
| 16749 | #define SPI3_BASE (0x50089000u) | ||
| 16750 | /** Peripheral SPI3 base address */ | ||
| 16751 | #define SPI3_BASE_NS (0x40089000u) | ||
| 16752 | /** Peripheral SPI3 base pointer */ | ||
| 16753 | #define SPI3 ((SPI_Type *)SPI3_BASE) | ||
| 16754 | /** Peripheral SPI3 base pointer */ | ||
| 16755 | #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) | ||
| 16756 | /** Peripheral SPI4 base address */ | ||
| 16757 | #define SPI4_BASE (0x5008A000u) | ||
| 16758 | /** Peripheral SPI4 base address */ | ||
| 16759 | #define SPI4_BASE_NS (0x4008A000u) | ||
| 16760 | /** Peripheral SPI4 base pointer */ | ||
| 16761 | #define SPI4 ((SPI_Type *)SPI4_BASE) | ||
| 16762 | /** Peripheral SPI4 base pointer */ | ||
| 16763 | #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) | ||
| 16764 | /** Peripheral SPI5 base address */ | ||
| 16765 | #define SPI5_BASE (0x50096000u) | ||
| 16766 | /** Peripheral SPI5 base address */ | ||
| 16767 | #define SPI5_BASE_NS (0x40096000u) | ||
| 16768 | /** Peripheral SPI5 base pointer */ | ||
| 16769 | #define SPI5 ((SPI_Type *)SPI5_BASE) | ||
| 16770 | /** Peripheral SPI5 base pointer */ | ||
| 16771 | #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) | ||
| 16772 | /** Peripheral SPI6 base address */ | ||
| 16773 | #define SPI6_BASE (0x50097000u) | ||
| 16774 | /** Peripheral SPI6 base address */ | ||
| 16775 | #define SPI6_BASE_NS (0x40097000u) | ||
| 16776 | /** Peripheral SPI6 base pointer */ | ||
| 16777 | #define SPI6 ((SPI_Type *)SPI6_BASE) | ||
| 16778 | /** Peripheral SPI6 base pointer */ | ||
| 16779 | #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) | ||
| 16780 | /** Peripheral SPI7 base address */ | ||
| 16781 | #define SPI7_BASE (0x50098000u) | ||
| 16782 | /** Peripheral SPI7 base address */ | ||
| 16783 | #define SPI7_BASE_NS (0x40098000u) | ||
| 16784 | /** Peripheral SPI7 base pointer */ | ||
| 16785 | #define SPI7 ((SPI_Type *)SPI7_BASE) | ||
| 16786 | /** Peripheral SPI7 base pointer */ | ||
| 16787 | #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) | ||
| 16788 | /** Peripheral SPI8 base address */ | ||
| 16789 | #define SPI8_BASE (0x5009F000u) | ||
| 16790 | /** Peripheral SPI8 base address */ | ||
| 16791 | #define SPI8_BASE_NS (0x4009F000u) | ||
| 16792 | /** Peripheral SPI8 base pointer */ | ||
| 16793 | #define SPI8 ((SPI_Type *)SPI8_BASE) | ||
| 16794 | /** Peripheral SPI8 base pointer */ | ||
| 16795 | #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) | ||
| 16796 | /** Array initializer of SPI peripheral base addresses */ | ||
| 16797 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } | ||
| 16798 | /** Array initializer of SPI peripheral base pointers */ | ||
| 16799 | #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } | ||
| 16800 | /** Array initializer of SPI peripheral base addresses */ | ||
| 16801 | #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } | ||
| 16802 | /** Array initializer of SPI peripheral base pointers */ | ||
| 16803 | #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } | ||
| 16804 | #else | ||
| 16805 | /** Peripheral SPI0 base address */ | ||
| 16806 | #define SPI0_BASE (0x40086000u) | ||
| 16807 | /** Peripheral SPI0 base pointer */ | ||
| 16808 | #define SPI0 ((SPI_Type *)SPI0_BASE) | ||
| 16809 | /** Peripheral SPI1 base address */ | ||
| 16810 | #define SPI1_BASE (0x40087000u) | ||
| 16811 | /** Peripheral SPI1 base pointer */ | ||
| 16812 | #define SPI1 ((SPI_Type *)SPI1_BASE) | ||
| 16813 | /** Peripheral SPI2 base address */ | ||
| 16814 | #define SPI2_BASE (0x40088000u) | ||
| 16815 | /** Peripheral SPI2 base pointer */ | ||
| 16816 | #define SPI2 ((SPI_Type *)SPI2_BASE) | ||
| 16817 | /** Peripheral SPI3 base address */ | ||
| 16818 | #define SPI3_BASE (0x40089000u) | ||
| 16819 | /** Peripheral SPI3 base pointer */ | ||
| 16820 | #define SPI3 ((SPI_Type *)SPI3_BASE) | ||
| 16821 | /** Peripheral SPI4 base address */ | ||
| 16822 | #define SPI4_BASE (0x4008A000u) | ||
| 16823 | /** Peripheral SPI4 base pointer */ | ||
| 16824 | #define SPI4 ((SPI_Type *)SPI4_BASE) | ||
| 16825 | /** Peripheral SPI5 base address */ | ||
| 16826 | #define SPI5_BASE (0x40096000u) | ||
| 16827 | /** Peripheral SPI5 base pointer */ | ||
| 16828 | #define SPI5 ((SPI_Type *)SPI5_BASE) | ||
| 16829 | /** Peripheral SPI6 base address */ | ||
| 16830 | #define SPI6_BASE (0x40097000u) | ||
| 16831 | /** Peripheral SPI6 base pointer */ | ||
| 16832 | #define SPI6 ((SPI_Type *)SPI6_BASE) | ||
| 16833 | /** Peripheral SPI7 base address */ | ||
| 16834 | #define SPI7_BASE (0x40098000u) | ||
| 16835 | /** Peripheral SPI7 base pointer */ | ||
| 16836 | #define SPI7 ((SPI_Type *)SPI7_BASE) | ||
| 16837 | /** Peripheral SPI8 base address */ | ||
| 16838 | #define SPI8_BASE (0x4009F000u) | ||
| 16839 | /** Peripheral SPI8 base pointer */ | ||
| 16840 | #define SPI8 ((SPI_Type *)SPI8_BASE) | ||
| 16841 | /** Array initializer of SPI peripheral base addresses */ | ||
| 16842 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } | ||
| 16843 | /** Array initializer of SPI peripheral base pointers */ | ||
| 16844 | #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } | ||
| 16845 | #endif | ||
| 16846 | /** Interrupt vectors for the SPI peripheral type */ | ||
| 16847 | #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } | ||
| 16848 | |||
| 16849 | /*! | ||
| 16850 | * @} | ||
| 16851 | */ /* end of group SPI_Peripheral_Access_Layer */ | ||
| 16852 | |||
| 16853 | |||
| 16854 | /* ---------------------------------------------------------------------------- | ||
| 16855 | -- SYSCON Peripheral Access Layer | ||
| 16856 | ---------------------------------------------------------------------------- */ | ||
| 16857 | |||
| 16858 | /*! | ||
| 16859 | * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer | ||
| 16860 | * @{ | ||
| 16861 | */ | ||
| 16862 | |||
| 16863 | /** SYSCON - Register Layout Typedef */ | ||
| 16864 | typedef struct { | ||
| 16865 | __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ | ||
| 16866 | uint8_t RESERVED_0[12]; | ||
| 16867 | __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ | ||
| 16868 | uint8_t RESERVED_1[36]; | ||
| 16869 | __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ | ||
| 16870 | __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ | ||
| 16871 | __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ | ||
| 16872 | uint8_t RESERVED_2[4]; | ||
| 16873 | __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ | ||
| 16874 | uint8_t RESERVED_3[180]; | ||
| 16875 | union { /* offset: 0x100 */ | ||
| 16876 | struct { /* offset: 0x100 */ | ||
| 16877 | __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ | ||
| 16878 | __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ | ||
| 16879 | __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ | ||
| 16880 | } PRESETCTRL; | ||
| 16881 | __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ | ||
| 16882 | }; | ||
| 16883 | uint8_t RESERVED_4[20]; | ||
| 16884 | __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ | ||
| 16885 | uint8_t RESERVED_5[20]; | ||
| 16886 | __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ | ||
| 16887 | uint8_t RESERVED_6[20]; | ||
| 16888 | __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ | ||
| 16889 | uint8_t RESERVED_7[156]; | ||
| 16890 | union { /* offset: 0x200 */ | ||
| 16891 | struct { /* offset: 0x200 */ | ||
| 16892 | __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ | ||
| 16893 | __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ | ||
| 16894 | __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ | ||
| 16895 | } AHBCLKCTRL; | ||
| 16896 | __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ | ||
| 16897 | }; | ||
| 16898 | uint8_t RESERVED_8[20]; | ||
| 16899 | __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ | ||
| 16900 | uint8_t RESERVED_9[20]; | ||
| 16901 | __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ | ||
| 16902 | uint8_t RESERVED_10[20]; | ||
| 16903 | union { /* offset: 0x260 */ | ||
| 16904 | __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ | ||
| 16905 | __IO uint32_t SYSTICKCLKSELX[1]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ | ||
| 16906 | }; | ||
| 16907 | uint8_t RESERVED_11[4]; | ||
| 16908 | __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ | ||
| 16909 | union { /* offset: 0x26C */ | ||
| 16910 | struct { /* offset: 0x26C */ | ||
| 16911 | __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ | ||
| 16912 | __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ | ||
| 16913 | __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ | ||
| 16914 | __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ | ||
| 16915 | __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ | ||
| 16916 | } CTIMERCLKSEL; | ||
| 16917 | __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ | ||
| 16918 | }; | ||
| 16919 | __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ | ||
| 16920 | __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ | ||
| 16921 | __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ | ||
| 16922 | uint8_t RESERVED_12[4]; | ||
| 16923 | __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ | ||
| 16924 | __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ | ||
| 16925 | uint8_t RESERVED_13[12]; | ||
| 16926 | __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ | ||
| 16927 | __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ | ||
| 16928 | uint8_t RESERVED_14[4]; | ||
| 16929 | union { /* offset: 0x2B0 */ | ||
| 16930 | struct { /* offset: 0x2B0 */ | ||
| 16931 | __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ | ||
| 16932 | __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ | ||
| 16933 | __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ | ||
| 16934 | __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ | ||
| 16935 | __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ | ||
| 16936 | __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ | ||
| 16937 | __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ | ||
| 16938 | __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ | ||
| 16939 | } FCCLKSEL; | ||
| 16940 | __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ | ||
| 16941 | }; | ||
| 16942 | __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ | ||
| 16943 | uint8_t RESERVED_15[12]; | ||
| 16944 | __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ | ||
| 16945 | uint8_t RESERVED_16[12]; | ||
| 16946 | __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ | ||
| 16947 | uint8_t RESERVED_17[4]; | ||
| 16948 | __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ | ||
| 16949 | uint8_t RESERVED_18[4]; | ||
| 16950 | __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ | ||
| 16951 | __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ | ||
| 16952 | __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ | ||
| 16953 | uint8_t RESERVED_19[20]; | ||
| 16954 | union { /* offset: 0x320 */ | ||
| 16955 | struct { /* offset: 0x320 */ | ||
| 16956 | __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ | ||
| 16957 | __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ | ||
| 16958 | __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ | ||
| 16959 | __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ | ||
| 16960 | __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ | ||
| 16961 | __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ | ||
| 16962 | __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ | ||
| 16963 | __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ | ||
| 16964 | } FLEXFRGCTRL; | ||
| 16965 | __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ | ||
| 16966 | }; | ||
| 16967 | uint8_t RESERVED_20[64]; | ||
| 16968 | __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ | ||
| 16969 | __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ | ||
| 16970 | __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ | ||
| 16971 | __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ | ||
| 16972 | uint8_t RESERVED_21[4]; | ||
| 16973 | __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ | ||
| 16974 | __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ | ||
| 16975 | uint8_t RESERVED_22[16]; | ||
| 16976 | __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ | ||
| 16977 | uint8_t RESERVED_23[4]; | ||
| 16978 | __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ | ||
| 16979 | uint8_t RESERVED_24[4]; | ||
| 16980 | __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ | ||
| 16981 | uint8_t RESERVED_25[4]; | ||
| 16982 | __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ | ||
| 16983 | uint8_t RESERVED_26[52]; | ||
| 16984 | __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ | ||
| 16985 | __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ | ||
| 16986 | uint8_t RESERVED_27[8]; | ||
| 16987 | __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ | ||
| 16988 | __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ | ||
| 16989 | uint8_t RESERVED_28[8]; | ||
| 16990 | __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ | ||
| 16991 | __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ | ||
| 16992 | __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ | ||
| 16993 | __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ | ||
| 16994 | uint8_t RESERVED_29[52]; | ||
| 16995 | __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ | ||
| 16996 | uint8_t RESERVED_30[252]; | ||
| 16997 | __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ | ||
| 16998 | __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ | ||
| 16999 | __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ | ||
| 17000 | __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ | ||
| 17001 | __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ | ||
| 17002 | uint8_t RESERVED_31[12]; | ||
| 17003 | __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ | ||
| 17004 | __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ | ||
| 17005 | __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ | ||
| 17006 | __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ | ||
| 17007 | __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ | ||
| 17008 | __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ | ||
| 17009 | uint8_t RESERVED_32[616]; | ||
| 17010 | __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ | ||
| 17011 | __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ | ||
| 17012 | uint8_t RESERVED_33[4]; | ||
| 17013 | __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ | ||
| 17014 | uint8_t RESERVED_34[520]; | ||
| 17015 | __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ | ||
| 17016 | uint8_t RESERVED_35[244]; | ||
| 17017 | __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ | ||
| 17018 | __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ | ||
| 17019 | uint8_t RESERVED_36[748]; | ||
| 17020 | __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ | ||
| 17021 | __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ | ||
| 17022 | uint8_t RESERVED_37[404]; | ||
| 17023 | __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ | ||
| 17024 | __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ | ||
| 17025 | __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ | ||
| 17026 | uint8_t RESERVED_38[16]; | ||
| 17027 | __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ | ||
| 17028 | __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ | ||
| 17029 | uint8_t RESERVED_39[52]; | ||
| 17030 | __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ | ||
| 17031 | __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ | ||
| 17032 | } SYSCON_Type; | ||
| 17033 | |||
| 17034 | /* ---------------------------------------------------------------------------- | ||
| 17035 | -- SYSCON Register Masks | ||
| 17036 | ---------------------------------------------------------------------------- */ | ||
| 17037 | |||
| 17038 | /*! | ||
| 17039 | * @addtogroup SYSCON_Register_Masks SYSCON Register Masks | ||
| 17040 | * @{ | ||
| 17041 | */ | ||
| 17042 | |||
| 17043 | /*! @name MEMORYREMAP - Memory Remap control register */ | ||
| 17044 | /*! @{ */ | ||
| 17045 | #define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) | ||
| 17046 | #define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) | ||
| 17047 | /*! MAP - Select the location of the vector table :. | ||
| 17048 | * 0b00..Vector Table in ROM. | ||
| 17049 | * 0b01..Vector Table in RAM. | ||
| 17050 | * 0b10..Vector Table in Flash. | ||
| 17051 | * 0b11..Vector Table in Flash. | ||
| 17052 | */ | ||
| 17053 | #define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) | ||
| 17054 | /*! @} */ | ||
| 17055 | |||
| 17056 | /*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ | ||
| 17057 | /*! @{ */ | ||
| 17058 | #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) | ||
| 17059 | #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) | ||
| 17060 | /*! PRI_CPU0_CBUS - CPU0 C-AHB bus. | ||
| 17061 | */ | ||
| 17062 | #define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) | ||
| 17063 | #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) | ||
| 17064 | #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) | ||
| 17065 | /*! PRI_CPU0_SBUS - CPU0 S-AHB bus. | ||
| 17066 | */ | ||
| 17067 | #define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) | ||
| 17068 | #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) | ||
| 17069 | #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) | ||
| 17070 | /*! PRI_CPU1_CBUS - CPU1 C-AHB bus. | ||
| 17071 | */ | ||
| 17072 | #define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) | ||
| 17073 | #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) | ||
| 17074 | #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) | ||
| 17075 | /*! PRI_CPU1_SBUS - CPU1 S-AHB bus. | ||
| 17076 | */ | ||
| 17077 | #define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) | ||
| 17078 | #define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) | ||
| 17079 | #define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) | ||
| 17080 | /*! PRI_USB_FS - USB-FS.(USB0) | ||
| 17081 | */ | ||
| 17082 | #define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) | ||
| 17083 | #define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) | ||
| 17084 | #define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) | ||
| 17085 | /*! PRI_SDMA0 - DMA0 controller priority. | ||
| 17086 | */ | ||
| 17087 | #define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) | ||
| 17088 | #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) | ||
| 17089 | #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) | ||
| 17090 | /*! PRI_SDIO - SDIO. | ||
| 17091 | */ | ||
| 17092 | #define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) | ||
| 17093 | #define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) | ||
| 17094 | #define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) | ||
| 17095 | /*! PRI_PQ - PQ (HW Accelerator). | ||
| 17096 | */ | ||
| 17097 | #define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) | ||
| 17098 | #define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) | ||
| 17099 | #define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) | ||
| 17100 | /*! PRI_HASH_AES - HASH_AES. | ||
| 17101 | */ | ||
| 17102 | #define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) | ||
| 17103 | #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) | ||
| 17104 | #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) | ||
| 17105 | /*! PRI_USB_HS - USB-HS.(USB1) | ||
| 17106 | */ | ||
| 17107 | #define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) | ||
| 17108 | #define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) | ||
| 17109 | #define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) | ||
| 17110 | /*! PRI_SDMA1 - DMA1 controller priority. | ||
| 17111 | */ | ||
| 17112 | #define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) | ||
| 17113 | /*! @} */ | ||
| 17114 | |||
| 17115 | /*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ | ||
| 17116 | /*! @{ */ | ||
| 17117 | #define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) | ||
| 17118 | #define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) | ||
| 17119 | /*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value | ||
| 17120 | * reads as zero, the calibration value is not known. | ||
| 17121 | */ | ||
| 17122 | #define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) | ||
| 17123 | #define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) | ||
| 17124 | #define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) | ||
| 17125 | /*! SKEW - Initial value for the Systick timer. | ||
| 17126 | */ | ||
| 17127 | #define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) | ||
| 17128 | #define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) | ||
| 17129 | #define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) | ||
| 17130 | /*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference | ||
| 17131 | * clock provided; 1 = no reference clock provided. | ||
| 17132 | */ | ||
| 17133 | #define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) | ||
| 17134 | /*! @} */ | ||
| 17135 | |||
| 17136 | /*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ | ||
| 17137 | /*! @{ */ | ||
| 17138 | #define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) | ||
| 17139 | #define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) | ||
| 17140 | /*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the | ||
| 17141 | * value reads as zero, the calibration value is not known. | ||
| 17142 | */ | ||
| 17143 | #define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) | ||
| 17144 | #define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) | ||
| 17145 | #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) | ||
| 17146 | /*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. | ||
| 17147 | */ | ||
| 17148 | #define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) | ||
| 17149 | #define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) | ||
| 17150 | #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) | ||
| 17151 | /*! NOREF - Initial value for the Systick timer. | ||
| 17152 | */ | ||
| 17153 | #define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) | ||
| 17154 | /*! @} */ | ||
| 17155 | |||
| 17156 | /*! @name CPU1STCKCAL - System tick calibration for CPU1 */ | ||
| 17157 | /*! @{ */ | ||
| 17158 | #define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) | ||
| 17159 | #define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) | ||
| 17160 | /*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value | ||
| 17161 | * reads as zero, the calibration value is not known. | ||
| 17162 | */ | ||
| 17163 | #define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) | ||
| 17164 | #define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) | ||
| 17165 | #define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) | ||
| 17166 | /*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. | ||
| 17167 | */ | ||
| 17168 | #define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) | ||
| 17169 | #define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) | ||
| 17170 | #define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) | ||
| 17171 | /*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference | ||
| 17172 | * clock provided; 1 = no reference clock provided. | ||
| 17173 | */ | ||
| 17174 | #define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) | ||
| 17175 | /*! @} */ | ||
| 17176 | |||
| 17177 | /*! @name NMISRC - NMI Source Select */ | ||
| 17178 | /*! @{ */ | ||
| 17179 | #define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) | ||
| 17180 | #define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) | ||
| 17181 | /*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. | ||
| 17182 | */ | ||
| 17183 | #define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) | ||
| 17184 | #define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) | ||
| 17185 | #define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) | ||
| 17186 | /*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. | ||
| 17187 | */ | ||
| 17188 | #define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) | ||
| 17189 | #define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) | ||
| 17190 | #define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) | ||
| 17191 | /*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. | ||
| 17192 | */ | ||
| 17193 | #define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) | ||
| 17194 | #define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) | ||
| 17195 | #define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) | ||
| 17196 | /*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. | ||
| 17197 | */ | ||
| 17198 | #define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) | ||
| 17199 | /*! @} */ | ||
| 17200 | |||
| 17201 | /*! @name PRESETCTRL0 - Peripheral reset control 0 */ | ||
| 17202 | /*! @{ */ | ||
| 17203 | #define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) | ||
| 17204 | #define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) | ||
| 17205 | /*! ROM_RST - ROM reset control. | ||
| 17206 | * 0b1..Bloc is reset. | ||
| 17207 | * 0b0..Bloc is not reset. | ||
| 17208 | */ | ||
| 17209 | #define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) | ||
| 17210 | #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) | ||
| 17211 | #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) | ||
| 17212 | /*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. | ||
| 17213 | * 0b1..Bloc is reset. | ||
| 17214 | * 0b0..Bloc is not reset. | ||
| 17215 | */ | ||
| 17216 | #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) | ||
| 17217 | #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) | ||
| 17218 | #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) | ||
| 17219 | /*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. | ||
| 17220 | * 0b1..Bloc is reset. | ||
| 17221 | * 0b0..Bloc is not reset. | ||
| 17222 | */ | ||
| 17223 | #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) | ||
| 17224 | #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) | ||
| 17225 | #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) | ||
| 17226 | /*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. | ||
| 17227 | * 0b1..Bloc is reset. | ||
| 17228 | * 0b0..Bloc is not reset. | ||
| 17229 | */ | ||
| 17230 | #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) | ||
| 17231 | #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) | ||
| 17232 | #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) | ||
| 17233 | /*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. | ||
| 17234 | * 0b1..Bloc is reset. | ||
| 17235 | * 0b0..Bloc is not reset. | ||
| 17236 | */ | ||
| 17237 | #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) | ||
| 17238 | #define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) | ||
| 17239 | #define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) | ||
| 17240 | /*! FLASH_RST - Flash controller reset control. | ||
| 17241 | * 0b1..Bloc is reset. | ||
| 17242 | * 0b0..Bloc is not reset. | ||
| 17243 | */ | ||
| 17244 | #define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) | ||
| 17245 | #define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) | ||
| 17246 | #define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) | ||
| 17247 | /*! FMC_RST - FMC controller reset control. | ||
| 17248 | * 0b1..Bloc is reset. | ||
| 17249 | * 0b0..Bloc is not reset. | ||
| 17250 | */ | ||
| 17251 | #define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) | ||
| 17252 | #define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) | ||
| 17253 | #define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) | ||
| 17254 | /*! MUX_RST - Input Mux reset control. | ||
| 17255 | * 0b1..Bloc is reset. | ||
| 17256 | * 0b0..Bloc is not reset. | ||
| 17257 | */ | ||
| 17258 | #define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) | ||
| 17259 | #define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) | ||
| 17260 | #define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) | ||
| 17261 | /*! IOCON_RST - I/O controller reset control. | ||
| 17262 | * 0b1..Bloc is reset. | ||
| 17263 | * 0b0..Bloc is not reset. | ||
| 17264 | */ | ||
| 17265 | #define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) | ||
| 17266 | #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) | ||
| 17267 | #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) | ||
| 17268 | /*! GPIO0_RST - GPIO0 reset control. | ||
| 17269 | * 0b1..Bloc is reset. | ||
| 17270 | * 0b0..Bloc is not reset. | ||
| 17271 | */ | ||
| 17272 | #define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) | ||
| 17273 | #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) | ||
| 17274 | #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) | ||
| 17275 | /*! GPIO1_RST - GPIO1 reset control. | ||
| 17276 | * 0b1..Bloc is reset. | ||
| 17277 | * 0b0..Bloc is not reset. | ||
| 17278 | */ | ||
| 17279 | #define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) | ||
| 17280 | #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) | ||
| 17281 | #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) | ||
| 17282 | /*! GPIO2_RST - GPIO2 reset control. | ||
| 17283 | * 0b1..Bloc is reset. | ||
| 17284 | * 0b0..Bloc is not reset. | ||
| 17285 | */ | ||
| 17286 | #define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) | ||
| 17287 | #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) | ||
| 17288 | #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) | ||
| 17289 | /*! GPIO3_RST - GPIO3 reset control. | ||
| 17290 | * 0b1..Bloc is reset. | ||
| 17291 | * 0b0..Bloc is not reset. | ||
| 17292 | */ | ||
| 17293 | #define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) | ||
| 17294 | #define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) | ||
| 17295 | #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) | ||
| 17296 | /*! PINT_RST - Pin interrupt (PINT) reset control. | ||
| 17297 | * 0b1..Bloc is reset. | ||
| 17298 | * 0b0..Bloc is not reset. | ||
| 17299 | */ | ||
| 17300 | #define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) | ||
| 17301 | #define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) | ||
| 17302 | #define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) | ||
| 17303 | /*! GINT_RST - Group interrupt (GINT) reset control. | ||
| 17304 | * 0b1..Bloc is reset. | ||
| 17305 | * 0b0..Bloc is not reset. | ||
| 17306 | */ | ||
| 17307 | #define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) | ||
| 17308 | #define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) | ||
| 17309 | #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) | ||
| 17310 | /*! DMA0_RST - DMA0 reset control. | ||
| 17311 | * 0b1..Bloc is reset. | ||
| 17312 | * 0b0..Bloc is not reset. | ||
| 17313 | */ | ||
| 17314 | #define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) | ||
| 17315 | #define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) | ||
| 17316 | #define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) | ||
| 17317 | /*! CRCGEN_RST - CRCGEN reset control. | ||
| 17318 | * 0b1..Bloc is reset. | ||
| 17319 | * 0b0..Bloc is not reset. | ||
| 17320 | */ | ||
| 17321 | #define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) | ||
| 17322 | #define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) | ||
| 17323 | #define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) | ||
| 17324 | /*! WWDT_RST - Watchdog Timer reset control. | ||
| 17325 | * 0b1..Bloc is reset. | ||
| 17326 | * 0b0..Bloc is not reset. | ||
| 17327 | */ | ||
| 17328 | #define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) | ||
| 17329 | #define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) | ||
| 17330 | #define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) | ||
| 17331 | /*! RTC_RST - Real Time Clock (RTC) reset control. | ||
| 17332 | * 0b1..Bloc is reset. | ||
| 17333 | * 0b0..Bloc is not reset. | ||
| 17334 | */ | ||
| 17335 | #define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) | ||
| 17336 | #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) | ||
| 17337 | #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) | ||
| 17338 | /*! MAILBOX_RST - Inter CPU communication Mailbox reset control. | ||
| 17339 | * 0b1..Bloc is reset. | ||
| 17340 | * 0b0..Bloc is not reset. | ||
| 17341 | */ | ||
| 17342 | #define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) | ||
| 17343 | #define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) | ||
| 17344 | #define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) | ||
| 17345 | /*! ADC_RST - ADC reset control. | ||
| 17346 | * 0b1..Bloc is reset. | ||
| 17347 | * 0b0..Bloc is not reset. | ||
| 17348 | */ | ||
| 17349 | #define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) | ||
| 17350 | /*! @} */ | ||
| 17351 | |||
| 17352 | /*! @name PRESETCTRL1 - Peripheral reset control 1 */ | ||
| 17353 | /*! @{ */ | ||
| 17354 | #define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) | ||
| 17355 | #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) | ||
| 17356 | /*! MRT_RST - MRT reset control. | ||
| 17357 | * 0b1..Bloc is reset. | ||
| 17358 | * 0b0..Bloc is not reset. | ||
| 17359 | */ | ||
| 17360 | #define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) | ||
| 17361 | #define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) | ||
| 17362 | #define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) | ||
| 17363 | /*! OSTIMER_RST - OS Event Timer reset control. | ||
| 17364 | * 0b1..Bloc is reset. | ||
| 17365 | * 0b0..Bloc is not reset. | ||
| 17366 | */ | ||
| 17367 | #define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) | ||
| 17368 | #define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) | ||
| 17369 | #define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) | ||
| 17370 | /*! SCT_RST - SCT reset control. | ||
| 17371 | * 0b1..Bloc is reset. | ||
| 17372 | * 0b0..Bloc is not reset. | ||
| 17373 | */ | ||
| 17374 | #define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) | ||
| 17375 | #define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) | ||
| 17376 | #define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) | ||
| 17377 | /*! SCTIPU_RST - SCTIPU reset control. | ||
| 17378 | * 0b1..Bloc is reset. | ||
| 17379 | * 0b0..Bloc is not reset. | ||
| 17380 | */ | ||
| 17381 | #define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) | ||
| 17382 | #define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) | ||
| 17383 | #define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) | ||
| 17384 | /*! UTICK_RST - UTICK reset control. | ||
| 17385 | * 0b1..Bloc is reset. | ||
| 17386 | * 0b0..Bloc is not reset. | ||
| 17387 | */ | ||
| 17388 | #define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) | ||
| 17389 | #define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) | ||
| 17390 | #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) | ||
| 17391 | /*! FC0_RST - FC0 reset control. | ||
| 17392 | * 0b1..Bloc is reset. | ||
| 17393 | * 0b0..Bloc is not reset. | ||
| 17394 | */ | ||
| 17395 | #define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) | ||
| 17396 | #define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) | ||
| 17397 | #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) | ||
| 17398 | /*! FC1_RST - FC1 reset control. | ||
| 17399 | * 0b1..Bloc is reset. | ||
| 17400 | * 0b0..Bloc is not reset. | ||
| 17401 | */ | ||
| 17402 | #define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) | ||
| 17403 | #define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) | ||
| 17404 | #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) | ||
| 17405 | /*! FC2_RST - FC2 reset control. | ||
| 17406 | * 0b1..Bloc is reset. | ||
| 17407 | * 0b0..Bloc is not reset. | ||
| 17408 | */ | ||
| 17409 | #define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) | ||
| 17410 | #define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) | ||
| 17411 | #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) | ||
| 17412 | /*! FC3_RST - FC3 reset control. | ||
| 17413 | * 0b1..Bloc is reset. | ||
| 17414 | * 0b0..Bloc is not reset. | ||
| 17415 | */ | ||
| 17416 | #define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) | ||
| 17417 | #define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) | ||
| 17418 | #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) | ||
| 17419 | /*! FC4_RST - FC4 reset control. | ||
| 17420 | * 0b1..Bloc is reset. | ||
| 17421 | * 0b0..Bloc is not reset. | ||
| 17422 | */ | ||
| 17423 | #define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) | ||
| 17424 | #define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) | ||
| 17425 | #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) | ||
| 17426 | /*! FC5_RST - FC5 reset control. | ||
| 17427 | * 0b1..Bloc is reset. | ||
| 17428 | * 0b0..Bloc is not reset. | ||
| 17429 | */ | ||
| 17430 | #define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) | ||
| 17431 | #define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) | ||
| 17432 | #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) | ||
| 17433 | /*! FC6_RST - FC6 reset control. | ||
| 17434 | * 0b1..Bloc is reset. | ||
| 17435 | * 0b0..Bloc is not reset. | ||
| 17436 | */ | ||
| 17437 | #define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) | ||
| 17438 | #define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) | ||
| 17439 | #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) | ||
| 17440 | /*! FC7_RST - FC7 reset control. | ||
| 17441 | * 0b1..Bloc is reset. | ||
| 17442 | * 0b0..Bloc is not reset. | ||
| 17443 | */ | ||
| 17444 | #define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) | ||
| 17445 | #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) | ||
| 17446 | #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) | ||
| 17447 | /*! TIMER2_RST - Timer 2 reset control. | ||
| 17448 | * 0b1..Bloc is reset. | ||
| 17449 | * 0b0..Bloc is not reset. | ||
| 17450 | */ | ||
| 17451 | #define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) | ||
| 17452 | #define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) | ||
| 17453 | #define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) | ||
| 17454 | /*! USB0_DEV_RST - USB0 DEV reset control. | ||
| 17455 | * 0b1..Bloc is reset. | ||
| 17456 | * 0b0..Bloc is not reset. | ||
| 17457 | */ | ||
| 17458 | #define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) | ||
| 17459 | #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) | ||
| 17460 | #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) | ||
| 17461 | /*! TIMER0_RST - Timer 0 reset control. | ||
| 17462 | * 0b1..Bloc is reset. | ||
| 17463 | * 0b0..Bloc is not reset. | ||
| 17464 | */ | ||
| 17465 | #define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) | ||
| 17466 | #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) | ||
| 17467 | #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) | ||
| 17468 | /*! TIMER1_RST - Timer 1 reset control. | ||
| 17469 | * 0b1..Bloc is reset. | ||
| 17470 | * 0b0..Bloc is not reset. | ||
| 17471 | */ | ||
| 17472 | #define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) | ||
| 17473 | /*! @} */ | ||
| 17474 | |||
| 17475 | /*! @name PRESETCTRL2 - Peripheral reset control 2 */ | ||
| 17476 | /*! @{ */ | ||
| 17477 | #define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) | ||
| 17478 | #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) | ||
| 17479 | /*! DMA1_RST - DMA1 reset control. | ||
| 17480 | * 0b1..Bloc is reset. | ||
| 17481 | * 0b0..Bloc is not reset. | ||
| 17482 | */ | ||
| 17483 | #define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) | ||
| 17484 | #define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) | ||
| 17485 | #define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) | ||
| 17486 | /*! COMP_RST - Comparator reset control. | ||
| 17487 | * 0b1..Bloc is reset. | ||
| 17488 | * 0b0..Bloc is not reset. | ||
| 17489 | */ | ||
| 17490 | #define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) | ||
| 17491 | #define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) | ||
| 17492 | #define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) | ||
| 17493 | /*! SDIO_RST - SDIO reset control. | ||
| 17494 | * 0b1..Bloc is reset. | ||
| 17495 | * 0b0..Bloc is not reset. | ||
| 17496 | */ | ||
| 17497 | #define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) | ||
| 17498 | #define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) | ||
| 17499 | #define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) | ||
| 17500 | /*! USB1_HOST_RST - USB1 Host reset control. | ||
| 17501 | * 0b1..Bloc is reset. | ||
| 17502 | * 0b0..Bloc is not reset. | ||
| 17503 | */ | ||
| 17504 | #define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) | ||
| 17505 | #define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) | ||
| 17506 | #define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) | ||
| 17507 | /*! USB1_DEV_RST - USB1 dev reset control. | ||
| 17508 | * 0b1..Bloc is reset. | ||
| 17509 | * 0b0..Bloc is not reset. | ||
| 17510 | */ | ||
| 17511 | #define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) | ||
| 17512 | #define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) | ||
| 17513 | #define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) | ||
| 17514 | /*! USB1_RAM_RST - USB1 RAM reset control. | ||
| 17515 | * 0b1..Bloc is reset. | ||
| 17516 | * 0b0..Bloc is not reset. | ||
| 17517 | */ | ||
| 17518 | #define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) | ||
| 17519 | #define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) | ||
| 17520 | #define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) | ||
| 17521 | /*! USB1_PHY_RST - USB1 PHY reset control. | ||
| 17522 | * 0b1..Bloc is reset. | ||
| 17523 | * 0b0..Bloc is not reset. | ||
| 17524 | */ | ||
| 17525 | #define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) | ||
| 17526 | #define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) | ||
| 17527 | #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) | ||
| 17528 | /*! FREQME_RST - Frequency meter reset control. | ||
| 17529 | * 0b1..Bloc is reset. | ||
| 17530 | * 0b0..Bloc is not reset. | ||
| 17531 | */ | ||
| 17532 | #define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) | ||
| 17533 | #define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) | ||
| 17534 | #define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) | ||
| 17535 | /*! RNG_RST - RNG reset control. | ||
| 17536 | * 0b1..Bloc is reset. | ||
| 17537 | * 0b0..Bloc is not reset. | ||
| 17538 | */ | ||
| 17539 | #define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) | ||
| 17540 | #define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) | ||
| 17541 | #define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) | ||
| 17542 | /*! SYSCTL_RST - SYSCTL Block reset. | ||
| 17543 | * 0b1..Bloc is reset. | ||
| 17544 | * 0b0..Bloc is not reset. | ||
| 17545 | */ | ||
| 17546 | #define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) | ||
| 17547 | #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) | ||
| 17548 | #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) | ||
| 17549 | /*! USB0_HOSTM_RST - USB0 Host Master reset control. | ||
| 17550 | * 0b1..Bloc is reset. | ||
| 17551 | * 0b0..Bloc is not reset. | ||
| 17552 | */ | ||
| 17553 | #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) | ||
| 17554 | #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) | ||
| 17555 | #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) | ||
| 17556 | /*! USB0_HOSTS_RST - USB0 Host Slave reset control. | ||
| 17557 | * 0b1..Bloc is reset. | ||
| 17558 | * 0b0..Bloc is not reset. | ||
| 17559 | */ | ||
| 17560 | #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) | ||
| 17561 | #define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) | ||
| 17562 | #define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) | ||
| 17563 | /*! HASH_AES_RST - HASH_AES reset control. | ||
| 17564 | * 0b1..Bloc is reset. | ||
| 17565 | * 0b0..Bloc is not reset. | ||
| 17566 | */ | ||
| 17567 | #define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) | ||
| 17568 | #define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) | ||
| 17569 | #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) | ||
| 17570 | /*! PQ_RST - Power Quad reset control. | ||
| 17571 | * 0b1..Bloc is reset. | ||
| 17572 | * 0b0..Bloc is not reset. | ||
| 17573 | */ | ||
| 17574 | #define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) | ||
| 17575 | #define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) | ||
| 17576 | #define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) | ||
| 17577 | /*! PLULUT_RST - PLU LUT reset control. | ||
| 17578 | * 0b1..Bloc is reset. | ||
| 17579 | * 0b0..Bloc is not reset. | ||
| 17580 | */ | ||
| 17581 | #define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) | ||
| 17582 | #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) | ||
| 17583 | #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) | ||
| 17584 | /*! TIMER3_RST - Timer 3 reset control. | ||
| 17585 | * 0b1..Bloc is reset. | ||
| 17586 | * 0b0..Bloc is not reset. | ||
| 17587 | */ | ||
| 17588 | #define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) | ||
| 17589 | #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) | ||
| 17590 | #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) | ||
| 17591 | /*! TIMER4_RST - Timer 4 reset control. | ||
| 17592 | * 0b1..Bloc is reset. | ||
| 17593 | * 0b0..Bloc is not reset. | ||
| 17594 | */ | ||
| 17595 | #define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) | ||
| 17596 | #define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) | ||
| 17597 | #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) | ||
| 17598 | /*! PUF_RST - PUF reset control reset control. | ||
| 17599 | * 0b1..Bloc is reset. | ||
| 17600 | * 0b0..Bloc is not reset. | ||
| 17601 | */ | ||
| 17602 | #define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) | ||
| 17603 | #define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) | ||
| 17604 | #define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) | ||
| 17605 | /*! CASPER_RST - Casper reset control. | ||
| 17606 | * 0b1..Bloc is reset. | ||
| 17607 | * 0b0..Bloc is not reset. | ||
| 17608 | */ | ||
| 17609 | #define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) | ||
| 17610 | #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) | ||
| 17611 | #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) | ||
| 17612 | /*! ANALOG_CTRL_RST - analog control reset control. | ||
| 17613 | * 0b1..Bloc is reset. | ||
| 17614 | * 0b0..Bloc is not reset. | ||
| 17615 | */ | ||
| 17616 | #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) | ||
| 17617 | #define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) | ||
| 17618 | #define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) | ||
| 17619 | /*! HS_LSPI_RST - HS LSPI reset control. | ||
| 17620 | * 0b1..Bloc is reset. | ||
| 17621 | * 0b0..Bloc is not reset. | ||
| 17622 | */ | ||
| 17623 | #define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) | ||
| 17624 | #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) | ||
| 17625 | #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) | ||
| 17626 | /*! GPIO_SEC_RST - GPIO secure reset control. | ||
| 17627 | * 0b1..Bloc is reset. | ||
| 17628 | * 0b0..Bloc is not reset. | ||
| 17629 | */ | ||
| 17630 | #define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) | ||
| 17631 | #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) | ||
| 17632 | #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) | ||
| 17633 | /*! GPIO_SEC_INT_RST - GPIO secure int reset control. | ||
| 17634 | * 0b1..Bloc is reset. | ||
| 17635 | * 0b0..Bloc is not reset. | ||
| 17636 | */ | ||
| 17637 | #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) | ||
| 17638 | /*! @} */ | ||
| 17639 | |||
| 17640 | /*! @name PRESETCTRLX - Peripheral reset control register */ | ||
| 17641 | /*! @{ */ | ||
| 17642 | #define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) | ||
| 17643 | #define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) | ||
| 17644 | /*! DATA - Data array value | ||
| 17645 | */ | ||
| 17646 | #define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) | ||
| 17647 | /*! @} */ | ||
| 17648 | |||
| 17649 | /* The count of SYSCON_PRESETCTRLX */ | ||
| 17650 | #define SYSCON_PRESETCTRLX_COUNT (3U) | ||
| 17651 | |||
| 17652 | /*! @name PRESETCTRLSET - Peripheral reset control set register */ | ||
| 17653 | /*! @{ */ | ||
| 17654 | #define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) | ||
| 17655 | #define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) | ||
| 17656 | /*! DATA - Data array value | ||
| 17657 | */ | ||
| 17658 | #define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) | ||
| 17659 | /*! @} */ | ||
| 17660 | |||
| 17661 | /* The count of SYSCON_PRESETCTRLSET */ | ||
| 17662 | #define SYSCON_PRESETCTRLSET_COUNT (3U) | ||
| 17663 | |||
| 17664 | /*! @name PRESETCTRLCLR - Peripheral reset control clear register */ | ||
| 17665 | /*! @{ */ | ||
| 17666 | #define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) | ||
| 17667 | #define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) | ||
| 17668 | /*! DATA - Data array value | ||
| 17669 | */ | ||
| 17670 | #define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) | ||
| 17671 | /*! @} */ | ||
| 17672 | |||
| 17673 | /* The count of SYSCON_PRESETCTRLCLR */ | ||
| 17674 | #define SYSCON_PRESETCTRLCLR_COUNT (3U) | ||
| 17675 | |||
| 17676 | /*! @name SWR_RESET - generate a software_reset */ | ||
| 17677 | /*! @{ */ | ||
| 17678 | #define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) | ||
| 17679 | #define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) | ||
| 17680 | /*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. | ||
| 17681 | * 0b01011010000000000000000000000001..Generate a software reset. | ||
| 17682 | * 0b00000000000000000000000000000000..Bloc is not reset. | ||
| 17683 | */ | ||
| 17684 | #define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) | ||
| 17685 | /*! @} */ | ||
| 17686 | |||
| 17687 | /*! @name AHBCLKCTRL0 - AHB Clock control 0 */ | ||
| 17688 | /*! @{ */ | ||
| 17689 | #define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) | ||
| 17690 | #define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) | ||
| 17691 | /*! ROM - Enables the clock for the ROM. | ||
| 17692 | * 0b1..Enable Clock. | ||
| 17693 | * 0b0..Disable Clock. | ||
| 17694 | */ | ||
| 17695 | #define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) | ||
| 17696 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) | ||
| 17697 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) | ||
| 17698 | /*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. | ||
| 17699 | * 0b1..Enable Clock. | ||
| 17700 | * 0b0..Disable Clock. | ||
| 17701 | */ | ||
| 17702 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) | ||
| 17703 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) | ||
| 17704 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) | ||
| 17705 | /*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. | ||
| 17706 | * 0b1..Enable Clock. | ||
| 17707 | * 0b0..Disable Clock. | ||
| 17708 | */ | ||
| 17709 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) | ||
| 17710 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) | ||
| 17711 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) | ||
| 17712 | /*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. | ||
| 17713 | * 0b1..Enable Clock. | ||
| 17714 | * 0b0..Disable Clock. | ||
| 17715 | */ | ||
| 17716 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) | ||
| 17717 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) | ||
| 17718 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) | ||
| 17719 | /*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. | ||
| 17720 | * 0b1..Enable Clock. | ||
| 17721 | * 0b0..Disable Clock. | ||
| 17722 | */ | ||
| 17723 | #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) | ||
| 17724 | #define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) | ||
| 17725 | #define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) | ||
| 17726 | /*! FLASH - Enables the clock for the Flash controller. | ||
| 17727 | * 0b1..Enable Clock. | ||
| 17728 | * 0b0..Disable Clock. | ||
| 17729 | */ | ||
| 17730 | #define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) | ||
| 17731 | #define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) | ||
| 17732 | #define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) | ||
| 17733 | /*! FMC - Enables the clock for the FMC controller. | ||
| 17734 | * 0b1..Enable Clock. | ||
| 17735 | * 0b0..Disable Clock. | ||
| 17736 | */ | ||
| 17737 | #define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) | ||
| 17738 | #define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) | ||
| 17739 | #define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) | ||
| 17740 | /*! MUX - Enables the clock for the Input Mux. | ||
| 17741 | * 0b1..Enable Clock. | ||
| 17742 | * 0b0..Disable Clock. | ||
| 17743 | */ | ||
| 17744 | #define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) | ||
| 17745 | #define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) | ||
| 17746 | #define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) | ||
| 17747 | /*! IOCON - Enables the clock for the I/O controller. | ||
| 17748 | * 0b1..Enable Clock. | ||
| 17749 | * 0b0..Disable Clock. | ||
| 17750 | */ | ||
| 17751 | #define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) | ||
| 17752 | #define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) | ||
| 17753 | #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) | ||
| 17754 | /*! GPIO0 - Enables the clock for the GPIO0. | ||
| 17755 | * 0b1..Enable Clock. | ||
| 17756 | * 0b0..Disable Clock. | ||
| 17757 | */ | ||
| 17758 | #define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) | ||
| 17759 | #define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) | ||
| 17760 | #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) | ||
| 17761 | /*! GPIO1 - Enables the clock for the GPIO1. | ||
| 17762 | * 0b1..Enable Clock. | ||
| 17763 | * 0b0..Disable Clock. | ||
| 17764 | */ | ||
| 17765 | #define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) | ||
| 17766 | #define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) | ||
| 17767 | #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) | ||
| 17768 | /*! GPIO2 - Enables the clock for the GPIO2. | ||
| 17769 | * 0b1..Enable Clock. | ||
| 17770 | * 0b0..Disable Clock. | ||
| 17771 | */ | ||
| 17772 | #define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) | ||
| 17773 | #define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) | ||
| 17774 | #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) | ||
| 17775 | /*! GPIO3 - Enables the clock for the GPIO3. | ||
| 17776 | * 0b1..Enable Clock. | ||
| 17777 | * 0b0..Disable Clock. | ||
| 17778 | */ | ||
| 17779 | #define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) | ||
| 17780 | #define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) | ||
| 17781 | #define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) | ||
| 17782 | /*! PINT - Enables the clock for the Pin interrupt (PINT). | ||
| 17783 | * 0b1..Enable Clock. | ||
| 17784 | * 0b0..Disable Clock. | ||
| 17785 | */ | ||
| 17786 | #define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) | ||
| 17787 | #define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) | ||
| 17788 | #define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) | ||
| 17789 | /*! GINT - Enables the clock for the Group interrupt (GINT). | ||
| 17790 | * 0b1..Enable Clock. | ||
| 17791 | * 0b0..Disable Clock. | ||
| 17792 | */ | ||
| 17793 | #define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) | ||
| 17794 | #define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) | ||
| 17795 | #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) | ||
| 17796 | /*! DMA0 - Enables the clock for the DMA0. | ||
| 17797 | * 0b1..Enable Clock. | ||
| 17798 | * 0b0..Disable Clock. | ||
| 17799 | */ | ||
| 17800 | #define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) | ||
| 17801 | #define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) | ||
| 17802 | #define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) | ||
| 17803 | /*! CRCGEN - Enables the clock for the CRCGEN. | ||
| 17804 | * 0b1..Enable Clock. | ||
| 17805 | * 0b0..Disable Clock. | ||
| 17806 | */ | ||
| 17807 | #define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) | ||
| 17808 | #define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) | ||
| 17809 | #define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) | ||
| 17810 | /*! WWDT - Enables the clock for the Watchdog Timer. | ||
| 17811 | * 0b1..Enable Clock. | ||
| 17812 | * 0b0..Disable Clock. | ||
| 17813 | */ | ||
| 17814 | #define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) | ||
| 17815 | #define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) | ||
| 17816 | #define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) | ||
| 17817 | /*! RTC - Enables the clock for the Real Time Clock (RTC). | ||
| 17818 | * 0b1..Enable Clock. | ||
| 17819 | * 0b0..Disable Clock. | ||
| 17820 | */ | ||
| 17821 | #define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) | ||
| 17822 | #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) | ||
| 17823 | #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) | ||
| 17824 | /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. | ||
| 17825 | * 0b1..Enable Clock. | ||
| 17826 | * 0b0..Disable Clock. | ||
| 17827 | */ | ||
| 17828 | #define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) | ||
| 17829 | #define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) | ||
| 17830 | #define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) | ||
| 17831 | /*! ADC - Enables the clock for the ADC. | ||
| 17832 | * 0b1..Enable Clock. | ||
| 17833 | * 0b0..Disable Clock. | ||
| 17834 | */ | ||
| 17835 | #define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) | ||
| 17836 | /*! @} */ | ||
| 17837 | |||
| 17838 | /*! @name AHBCLKCTRL1 - AHB Clock control 1 */ | ||
| 17839 | /*! @{ */ | ||
| 17840 | #define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) | ||
| 17841 | #define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) | ||
| 17842 | /*! MRT - Enables the clock for the MRT. | ||
| 17843 | * 0b1..Enable Clock. | ||
| 17844 | * 0b0..Disable Clock. | ||
| 17845 | */ | ||
| 17846 | #define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) | ||
| 17847 | #define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) | ||
| 17848 | #define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) | ||
| 17849 | /*! OSTIMER - Enables the clock for the OS Event Timer. | ||
| 17850 | * 0b1..Enable Clock. | ||
| 17851 | * 0b0..Disable Clock. | ||
| 17852 | */ | ||
| 17853 | #define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) | ||
| 17854 | #define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) | ||
| 17855 | #define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) | ||
| 17856 | /*! SCT - Enables the clock for the SCT. | ||
| 17857 | * 0b1..Enable Clock. | ||
| 17858 | * 0b0..Disable Clock. | ||
| 17859 | */ | ||
| 17860 | #define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) | ||
| 17861 | #define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) | ||
| 17862 | #define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) | ||
| 17863 | /*! UTICK - Enables the clock for the UTICK. | ||
| 17864 | * 0b1..Enable Clock. | ||
| 17865 | * 0b0..Disable Clock. | ||
| 17866 | */ | ||
| 17867 | #define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) | ||
| 17868 | #define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) | ||
| 17869 | #define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) | ||
| 17870 | /*! FC0 - Enables the clock for the FC0. | ||
| 17871 | * 0b1..Enable Clock. | ||
| 17872 | * 0b0..Disable Clock. | ||
| 17873 | */ | ||
| 17874 | #define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) | ||
| 17875 | #define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) | ||
| 17876 | #define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) | ||
| 17877 | /*! FC1 - Enables the clock for the FC1. | ||
| 17878 | * 0b1..Enable Clock. | ||
| 17879 | * 0b0..Disable Clock. | ||
| 17880 | */ | ||
| 17881 | #define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) | ||
| 17882 | #define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) | ||
| 17883 | #define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) | ||
| 17884 | /*! FC2 - Enables the clock for the FC2. | ||
| 17885 | * 0b1..Enable Clock. | ||
| 17886 | * 0b0..Disable Clock. | ||
| 17887 | */ | ||
| 17888 | #define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) | ||
| 17889 | #define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) | ||
| 17890 | #define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) | ||
| 17891 | /*! FC3 - Enables the clock for the FC3. | ||
| 17892 | * 0b1..Enable Clock. | ||
| 17893 | * 0b0..Disable Clock. | ||
| 17894 | */ | ||
| 17895 | #define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) | ||
| 17896 | #define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) | ||
| 17897 | #define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) | ||
| 17898 | /*! FC4 - Enables the clock for the FC4. | ||
| 17899 | * 0b1..Enable Clock. | ||
| 17900 | * 0b0..Disable Clock. | ||
| 17901 | */ | ||
| 17902 | #define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) | ||
| 17903 | #define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) | ||
| 17904 | #define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) | ||
| 17905 | /*! FC5 - Enables the clock for the FC5. | ||
| 17906 | * 0b1..Enable Clock. | ||
| 17907 | * 0b0..Disable Clock. | ||
| 17908 | */ | ||
| 17909 | #define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) | ||
| 17910 | #define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) | ||
| 17911 | #define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) | ||
| 17912 | /*! FC6 - Enables the clock for the FC6. | ||
| 17913 | * 0b1..Enable Clock. | ||
| 17914 | * 0b0..Disable Clock. | ||
| 17915 | */ | ||
| 17916 | #define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) | ||
| 17917 | #define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) | ||
| 17918 | #define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) | ||
| 17919 | /*! FC7 - Enables the clock for the FC7. | ||
| 17920 | * 0b1..Enable Clock. | ||
| 17921 | * 0b0..Disable Clock. | ||
| 17922 | */ | ||
| 17923 | #define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) | ||
| 17924 | #define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) | ||
| 17925 | #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) | ||
| 17926 | /*! TIMER2 - Enables the clock for the Timer 2. | ||
| 17927 | * 0b1..Enable Clock. | ||
| 17928 | * 0b0..Disable Clock. | ||
| 17929 | */ | ||
| 17930 | #define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) | ||
| 17931 | #define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) | ||
| 17932 | #define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) | ||
| 17933 | /*! USB0_DEV - Enables the clock for the USB0 DEV. | ||
| 17934 | * 0b1..Enable Clock. | ||
| 17935 | * 0b0..Disable Clock. | ||
| 17936 | */ | ||
| 17937 | #define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) | ||
| 17938 | #define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) | ||
| 17939 | #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) | ||
| 17940 | /*! TIMER0 - Enables the clock for the Timer 0. | ||
| 17941 | * 0b1..Enable Clock. | ||
| 17942 | * 0b0..Disable Clock. | ||
| 17943 | */ | ||
| 17944 | #define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) | ||
| 17945 | #define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) | ||
| 17946 | #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) | ||
| 17947 | /*! TIMER1 - Enables the clock for the Timer 1. | ||
| 17948 | * 0b1..Enable Clock. | ||
| 17949 | * 0b0..Disable Clock. | ||
| 17950 | */ | ||
| 17951 | #define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) | ||
| 17952 | /*! @} */ | ||
| 17953 | |||
| 17954 | /*! @name AHBCLKCTRL2 - AHB Clock control 2 */ | ||
| 17955 | /*! @{ */ | ||
| 17956 | #define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) | ||
| 17957 | #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) | ||
| 17958 | /*! DMA1 - Enables the clock for the DMA1. | ||
| 17959 | * 0b1..Enable Clock. | ||
| 17960 | * 0b0..Disable Clock. | ||
| 17961 | */ | ||
| 17962 | #define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) | ||
| 17963 | #define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) | ||
| 17964 | #define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) | ||
| 17965 | /*! COMP - Enables the clock for the Comparator. | ||
| 17966 | * 0b1..Enable Clock. | ||
| 17967 | * 0b0..Disable Clock. | ||
| 17968 | */ | ||
| 17969 | #define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) | ||
| 17970 | #define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) | ||
| 17971 | #define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) | ||
| 17972 | /*! SDIO - Enables the clock for the SDIO. | ||
| 17973 | * 0b1..Enable Clock. | ||
| 17974 | * 0b0..Disable Clock. | ||
| 17975 | */ | ||
| 17976 | #define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) | ||
| 17977 | #define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) | ||
| 17978 | #define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) | ||
| 17979 | /*! USB1_HOST - Enables the clock for the USB1 Host. | ||
| 17980 | * 0b1..Enable Clock. | ||
| 17981 | * 0b0..Disable Clock. | ||
| 17982 | */ | ||
| 17983 | #define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) | ||
| 17984 | #define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) | ||
| 17985 | #define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) | ||
| 17986 | /*! USB1_DEV - Enables the clock for the USB1 dev. | ||
| 17987 | * 0b1..Enable Clock. | ||
| 17988 | * 0b0..Disable Clock. | ||
| 17989 | */ | ||
| 17990 | #define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) | ||
| 17991 | #define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) | ||
| 17992 | #define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) | ||
| 17993 | /*! USB1_RAM - Enables the clock for the USB1 RAM. | ||
| 17994 | * 0b1..Enable Clock. | ||
| 17995 | * 0b0..Disable Clock. | ||
| 17996 | */ | ||
| 17997 | #define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) | ||
| 17998 | #define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) | ||
| 17999 | #define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) | ||
| 18000 | /*! USB1_PHY - Enables the clock for the USB1 PHY. | ||
| 18001 | * 0b1..Enable Clock. | ||
| 18002 | * 0b0..Disable Clock. | ||
| 18003 | */ | ||
| 18004 | #define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) | ||
| 18005 | #define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) | ||
| 18006 | #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) | ||
| 18007 | /*! FREQME - Enables the clock for the Frequency meter. | ||
| 18008 | * 0b1..Enable Clock. | ||
| 18009 | * 0b0..Disable Clock. | ||
| 18010 | */ | ||
| 18011 | #define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) | ||
| 18012 | #define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) | ||
| 18013 | #define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) | ||
| 18014 | /*! RNG - Enables the clock for the RNG. | ||
| 18015 | * 0b1..Enable Clock. | ||
| 18016 | * 0b0..Disable Clock. | ||
| 18017 | */ | ||
| 18018 | #define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) | ||
| 18019 | #define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) | ||
| 18020 | #define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) | ||
| 18021 | /*! SYSCTL - SYSCTL block clock. | ||
| 18022 | * 0b1..Enable Clock. | ||
| 18023 | * 0b0..Disable Clock. | ||
| 18024 | */ | ||
| 18025 | #define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) | ||
| 18026 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) | ||
| 18027 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) | ||
| 18028 | /*! USB0_HOSTM - Enables the clock for the USB0 Host Master. | ||
| 18029 | * 0b1..Enable Clock. | ||
| 18030 | * 0b0..Disable Clock. | ||
| 18031 | */ | ||
| 18032 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) | ||
| 18033 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) | ||
| 18034 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) | ||
| 18035 | /*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. | ||
| 18036 | * 0b1..Enable Clock. | ||
| 18037 | * 0b0..Disable Clock. | ||
| 18038 | */ | ||
| 18039 | #define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) | ||
| 18040 | #define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) | ||
| 18041 | #define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) | ||
| 18042 | /*! HASH_AES - Enables the clock for the HASH_AES. | ||
| 18043 | * 0b1..Enable Clock. | ||
| 18044 | * 0b0..Disable Clock. | ||
| 18045 | */ | ||
| 18046 | #define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) | ||
| 18047 | #define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) | ||
| 18048 | #define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) | ||
| 18049 | /*! PQ - Enables the clock for the Power Quad. | ||
| 18050 | * 0b1..Enable Clock. | ||
| 18051 | * 0b0..Disable Clock. | ||
| 18052 | */ | ||
| 18053 | #define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) | ||
| 18054 | #define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) | ||
| 18055 | #define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) | ||
| 18056 | /*! PLULUT - Enables the clock for the PLU LUT. | ||
| 18057 | * 0b1..Enable Clock. | ||
| 18058 | * 0b0..Disable Clock. | ||
| 18059 | */ | ||
| 18060 | #define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) | ||
| 18061 | #define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) | ||
| 18062 | #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) | ||
| 18063 | /*! TIMER3 - Enables the clock for the Timer 3. | ||
| 18064 | * 0b1..Enable Clock. | ||
| 18065 | * 0b0..Disable Clock. | ||
| 18066 | */ | ||
| 18067 | #define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) | ||
| 18068 | #define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) | ||
| 18069 | #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) | ||
| 18070 | /*! TIMER4 - Enables the clock for the Timer 4. | ||
| 18071 | * 0b1..Enable Clock. | ||
| 18072 | * 0b0..Disable Clock. | ||
| 18073 | */ | ||
| 18074 | #define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) | ||
| 18075 | #define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) | ||
| 18076 | #define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) | ||
| 18077 | /*! PUF - Enables the clock for the PUF reset control. | ||
| 18078 | * 0b1..Enable Clock. | ||
| 18079 | * 0b0..Disable Clock. | ||
| 18080 | */ | ||
| 18081 | #define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) | ||
| 18082 | #define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) | ||
| 18083 | #define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) | ||
| 18084 | /*! CASPER - Enables the clock for the Casper. | ||
| 18085 | * 0b1..Enable Clock. | ||
| 18086 | * 0b0..Disable Clock. | ||
| 18087 | */ | ||
| 18088 | #define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) | ||
| 18089 | #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) | ||
| 18090 | #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) | ||
| 18091 | /*! ANALOG_CTRL - Enables the clock for the analog control. | ||
| 18092 | * 0b1..Enable Clock. | ||
| 18093 | * 0b0..Disable Clock. | ||
| 18094 | */ | ||
| 18095 | #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) | ||
| 18096 | #define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) | ||
| 18097 | #define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) | ||
| 18098 | /*! HS_LSPI - Enables the clock for the HS LSPI. | ||
| 18099 | * 0b1..Enable Clock. | ||
| 18100 | * 0b0..Disable Clock. | ||
| 18101 | */ | ||
| 18102 | #define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) | ||
| 18103 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) | ||
| 18104 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) | ||
| 18105 | /*! GPIO_SEC - Enables the clock for the GPIO secure. | ||
| 18106 | * 0b1..Enable Clock. | ||
| 18107 | * 0b0..Disable Clock. | ||
| 18108 | */ | ||
| 18109 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) | ||
| 18110 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) | ||
| 18111 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) | ||
| 18112 | /*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. | ||
| 18113 | * 0b1..Enable Clock. | ||
| 18114 | * 0b0..Disable Clock. | ||
| 18115 | */ | ||
| 18116 | #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) | ||
| 18117 | /*! @} */ | ||
| 18118 | |||
| 18119 | /*! @name AHBCLKCTRLX - Peripheral reset control register */ | ||
| 18120 | /*! @{ */ | ||
| 18121 | #define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) | ||
| 18122 | #define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) | ||
| 18123 | /*! DATA - Data array value | ||
| 18124 | */ | ||
| 18125 | #define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) | ||
| 18126 | /*! @} */ | ||
| 18127 | |||
| 18128 | /* The count of SYSCON_AHBCLKCTRLX */ | ||
| 18129 | #define SYSCON_AHBCLKCTRLX_COUNT (3U) | ||
| 18130 | |||
| 18131 | /*! @name AHBCLKCTRLSET - Peripheral reset control register */ | ||
| 18132 | /*! @{ */ | ||
| 18133 | #define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) | ||
| 18134 | #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) | ||
| 18135 | /*! DATA - Data array value | ||
| 18136 | */ | ||
| 18137 | #define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) | ||
| 18138 | /*! @} */ | ||
| 18139 | |||
| 18140 | /* The count of SYSCON_AHBCLKCTRLSET */ | ||
| 18141 | #define SYSCON_AHBCLKCTRLSET_COUNT (3U) | ||
| 18142 | |||
| 18143 | /*! @name AHBCLKCTRLCLR - Peripheral reset control register */ | ||
| 18144 | /*! @{ */ | ||
| 18145 | #define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) | ||
| 18146 | #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) | ||
| 18147 | /*! DATA - Data array value | ||
| 18148 | */ | ||
| 18149 | #define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) | ||
| 18150 | /*! @} */ | ||
| 18151 | |||
| 18152 | /* The count of SYSCON_AHBCLKCTRLCLR */ | ||
| 18153 | #define SYSCON_AHBCLKCTRLCLR_COUNT (3U) | ||
| 18154 | |||
| 18155 | /*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ | ||
| 18156 | /*! @{ */ | ||
| 18157 | #define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) | ||
| 18158 | #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) | ||
| 18159 | /*! SEL - System Tick Timer for CPU0 source select. | ||
| 18160 | * 0b000..System Tick 0 divided clock. | ||
| 18161 | * 0b001..FRO 1MHz clock. | ||
| 18162 | * 0b010..Oscillator 32 kHz clock. | ||
| 18163 | * 0b011..No clock. | ||
| 18164 | * 0b100..No clock. | ||
| 18165 | * 0b101..No clock. | ||
| 18166 | * 0b110..No clock. | ||
| 18167 | * 0b111..No clock. | ||
| 18168 | */ | ||
| 18169 | #define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) | ||
| 18170 | /*! @} */ | ||
| 18171 | |||
| 18172 | /*! @name SYSTICKCLKSELX - Peripheral reset control register */ | ||
| 18173 | /*! @{ */ | ||
| 18174 | #define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) | ||
| 18175 | #define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) | ||
| 18176 | /*! DATA - Data array value | ||
| 18177 | */ | ||
| 18178 | #define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) | ||
| 18179 | /*! @} */ | ||
| 18180 | |||
| 18181 | /* The count of SYSCON_SYSTICKCLKSELX */ | ||
| 18182 | #define SYSCON_SYSTICKCLKSELX_COUNT (1U) | ||
| 18183 | |||
| 18184 | /*! @name TRACECLKSEL - Trace clock source select */ | ||
| 18185 | /*! @{ */ | ||
| 18186 | #define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) | ||
| 18187 | #define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) | ||
| 18188 | /*! SEL - Trace clock source select. | ||
| 18189 | * 0b000..Trace divided clock. | ||
| 18190 | * 0b001..FRO 1MHz clock. | ||
| 18191 | * 0b010..Oscillator 32 kHz clock. | ||
| 18192 | * 0b011..No clock. | ||
| 18193 | * 0b100..No clock. | ||
| 18194 | * 0b101..No clock. | ||
| 18195 | * 0b110..No clock. | ||
| 18196 | * 0b111..No clock. | ||
| 18197 | */ | ||
| 18198 | #define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) | ||
| 18199 | /*! @} */ | ||
| 18200 | |||
| 18201 | /*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ | ||
| 18202 | /*! @{ */ | ||
| 18203 | #define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) | ||
| 18204 | #define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) | ||
| 18205 | /*! SEL - CTimer 0 clock source select. | ||
| 18206 | * 0b000..Main clock. | ||
| 18207 | * 0b001..PLL0 clock. | ||
| 18208 | * 0b010..No clock. | ||
| 18209 | * 0b011..FRO 96 MHz clock. | ||
| 18210 | * 0b100..FRO 1MHz clock. | ||
| 18211 | * 0b101..MCLK clock. | ||
| 18212 | * 0b110..Oscillator 32kHz clock. | ||
| 18213 | * 0b111..No clock. | ||
| 18214 | */ | ||
| 18215 | #define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) | ||
| 18216 | /*! @} */ | ||
| 18217 | |||
| 18218 | /*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ | ||
| 18219 | /*! @{ */ | ||
| 18220 | #define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) | ||
| 18221 | #define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) | ||
| 18222 | /*! SEL - CTimer 1 clock source select. | ||
| 18223 | * 0b000..Main clock. | ||
| 18224 | * 0b001..PLL0 clock. | ||
| 18225 | * 0b010..No clock. | ||
| 18226 | * 0b011..FRO 96 MHz clock. | ||
| 18227 | * 0b100..FRO 1MHz clock. | ||
| 18228 | * 0b101..MCLK clock. | ||
| 18229 | * 0b110..Oscillator 32kHz clock. | ||
| 18230 | * 0b111..No clock. | ||
| 18231 | */ | ||
| 18232 | #define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) | ||
| 18233 | /*! @} */ | ||
| 18234 | |||
| 18235 | /*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ | ||
| 18236 | /*! @{ */ | ||
| 18237 | #define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) | ||
| 18238 | #define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) | ||
| 18239 | /*! SEL - CTimer 2 clock source select. | ||
| 18240 | * 0b000..Main clock. | ||
| 18241 | * 0b001..PLL0 clock. | ||
| 18242 | * 0b010..No clock. | ||
| 18243 | * 0b011..FRO 96 MHz clock. | ||
| 18244 | * 0b100..FRO 1MHz clock. | ||
| 18245 | * 0b101..MCLK clock. | ||
| 18246 | * 0b110..Oscillator 32kHz clock. | ||
| 18247 | * 0b111..No clock. | ||
| 18248 | */ | ||
| 18249 | #define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) | ||
| 18250 | /*! @} */ | ||
| 18251 | |||
| 18252 | /*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ | ||
| 18253 | /*! @{ */ | ||
| 18254 | #define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) | ||
| 18255 | #define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) | ||
| 18256 | /*! SEL - CTimer 3 clock source select. | ||
| 18257 | * 0b000..Main clock. | ||
| 18258 | * 0b001..PLL0 clock. | ||
| 18259 | * 0b010..No clock. | ||
| 18260 | * 0b011..FRO 96 MHz clock. | ||
| 18261 | * 0b100..FRO 1MHz clock. | ||
| 18262 | * 0b101..MCLK clock. | ||
| 18263 | * 0b110..Oscillator 32kHz clock. | ||
| 18264 | * 0b111..No clock. | ||
| 18265 | */ | ||
| 18266 | #define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) | ||
| 18267 | /*! @} */ | ||
| 18268 | |||
| 18269 | /*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ | ||
| 18270 | /*! @{ */ | ||
| 18271 | #define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) | ||
| 18272 | #define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) | ||
| 18273 | /*! SEL - CTimer 4 clock source select. | ||
| 18274 | * 0b000..Main clock. | ||
| 18275 | * 0b001..PLL0 clock. | ||
| 18276 | * 0b010..No clock. | ||
| 18277 | * 0b011..FRO 96 MHz clock. | ||
| 18278 | * 0b100..FRO 1MHz clock. | ||
| 18279 | * 0b101..MCLK clock. | ||
| 18280 | * 0b110..Oscillator 32kHz clock. | ||
| 18281 | * 0b111..No clock. | ||
| 18282 | */ | ||
| 18283 | #define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) | ||
| 18284 | /*! @} */ | ||
| 18285 | |||
| 18286 | /*! @name CTIMERCLKSELX - Peripheral reset control register */ | ||
| 18287 | /*! @{ */ | ||
| 18288 | #define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) | ||
| 18289 | #define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) | ||
| 18290 | /*! DATA - Data array value | ||
| 18291 | */ | ||
| 18292 | #define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) | ||
| 18293 | /*! @} */ | ||
| 18294 | |||
| 18295 | /* The count of SYSCON_CTIMERCLKSELX */ | ||
| 18296 | #define SYSCON_CTIMERCLKSELX_COUNT (5U) | ||
| 18297 | |||
| 18298 | /*! @name MAINCLKSELA - Main clock A source select */ | ||
| 18299 | /*! @{ */ | ||
| 18300 | #define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) | ||
| 18301 | #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) | ||
| 18302 | /*! SEL - Main clock A source select. | ||
| 18303 | * 0b000..FRO 12 MHz clock. | ||
| 18304 | * 0b001..CLKIN clock. | ||
| 18305 | * 0b010..FRO 1MHz clock. | ||
| 18306 | * 0b011..FRO 96 MHz clock. | ||
| 18307 | * 0b100..Reserved. | ||
| 18308 | * 0b101..Reserved. | ||
| 18309 | * 0b110..Reserved. | ||
| 18310 | * 0b111..Reserved. | ||
| 18311 | */ | ||
| 18312 | #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) | ||
| 18313 | /*! @} */ | ||
| 18314 | |||
| 18315 | /*! @name MAINCLKSELB - Main clock source select */ | ||
| 18316 | /*! @{ */ | ||
| 18317 | #define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) | ||
| 18318 | #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) | ||
| 18319 | /*! SEL - Main clock source select. | ||
| 18320 | * 0b000..Main Clock A. | ||
| 18321 | * 0b001..PLL0 clock. | ||
| 18322 | * 0b010..PLL1 clock. | ||
| 18323 | * 0b011..Oscillator 32 kHz clock. | ||
| 18324 | * 0b100..Reserved. | ||
| 18325 | * 0b101..Reserved. | ||
| 18326 | * 0b110..Reserved. | ||
| 18327 | * 0b111..Reserved. | ||
| 18328 | */ | ||
| 18329 | #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) | ||
| 18330 | /*! @} */ | ||
| 18331 | |||
| 18332 | /*! @name CLKOUTSEL - CLKOUT clock source select */ | ||
| 18333 | /*! @{ */ | ||
| 18334 | #define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) | ||
| 18335 | #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) | ||
| 18336 | /*! SEL - CLKOUT clock source select. | ||
| 18337 | * 0b000..Main clock. | ||
| 18338 | * 0b001..PLL0 clock. | ||
| 18339 | * 0b010..CLKIN clock. | ||
| 18340 | * 0b011..FRO 96 MHz clock. | ||
| 18341 | * 0b100..FRO 1MHz clock. | ||
| 18342 | * 0b101..PLL1 clock. | ||
| 18343 | * 0b110..Oscillator 32kHz clock. | ||
| 18344 | * 0b111..No clock. | ||
| 18345 | */ | ||
| 18346 | #define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) | ||
| 18347 | /*! @} */ | ||
| 18348 | |||
| 18349 | /*! @name PLL0CLKSEL - PLL0 clock source select */ | ||
| 18350 | /*! @{ */ | ||
| 18351 | #define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) | ||
| 18352 | #define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) | ||
| 18353 | /*! SEL - PLL0 clock source select. | ||
| 18354 | * 0b000..FRO 12 MHz clock. | ||
| 18355 | * 0b001..CLKIN clock. | ||
| 18356 | * 0b010..FRO 1MHz clock. | ||
| 18357 | * 0b011..Oscillator 32kHz clock. | ||
| 18358 | * 0b100..No clock. | ||
| 18359 | * 0b101..No clock. | ||
| 18360 | * 0b110..No clock. | ||
| 18361 | * 0b111..No clock. | ||
| 18362 | */ | ||
| 18363 | #define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) | ||
| 18364 | /*! @} */ | ||
| 18365 | |||
| 18366 | /*! @name PLL1CLKSEL - PLL1 clock source select */ | ||
| 18367 | /*! @{ */ | ||
| 18368 | #define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) | ||
| 18369 | #define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) | ||
| 18370 | /*! SEL - PLL1 clock source select. | ||
| 18371 | * 0b000..FRO 12 MHz clock. | ||
| 18372 | * 0b001..CLKIN clock. | ||
| 18373 | * 0b010..FRO 1MHz clock. | ||
| 18374 | * 0b011..Oscillator 32kHz clock. | ||
| 18375 | * 0b100..No clock. | ||
| 18376 | * 0b101..No clock. | ||
| 18377 | * 0b110..No clock. | ||
| 18378 | * 0b111..No clock. | ||
| 18379 | */ | ||
| 18380 | #define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) | ||
| 18381 | /*! @} */ | ||
| 18382 | |||
| 18383 | /*! @name ADCCLKSEL - ADC clock source select */ | ||
| 18384 | /*! @{ */ | ||
| 18385 | #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) | ||
| 18386 | #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) | ||
| 18387 | /*! SEL - ADC clock source select. | ||
| 18388 | * 0b000..Main clock. | ||
| 18389 | * 0b001..PLL0 clock. | ||
| 18390 | * 0b010..FRO 96 MHz clock. | ||
| 18391 | * 0b011..Reserved. | ||
| 18392 | * 0b100..No clock. | ||
| 18393 | * 0b101..No clock. | ||
| 18394 | * 0b110..No clock. | ||
| 18395 | * 0b111..No clock. | ||
| 18396 | */ | ||
| 18397 | #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) | ||
| 18398 | /*! @} */ | ||
| 18399 | |||
| 18400 | /*! @name USB0CLKSEL - FS USB clock source select */ | ||
| 18401 | /*! @{ */ | ||
| 18402 | #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) | ||
| 18403 | #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) | ||
| 18404 | /*! SEL - FS USB clock source select. | ||
| 18405 | * 0b000..Main clock. | ||
| 18406 | * 0b001..PLL0 clock. | ||
| 18407 | * 0b010..No clock. | ||
| 18408 | * 0b011..FRO 96 MHz clock. | ||
| 18409 | * 0b100..No clock. | ||
| 18410 | * 0b101..PLL1 clock. | ||
| 18411 | * 0b110..No clock. | ||
| 18412 | * 0b111..No clock. | ||
| 18413 | */ | ||
| 18414 | #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) | ||
| 18415 | /*! @} */ | ||
| 18416 | |||
| 18417 | /*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ | ||
| 18418 | /*! @{ */ | ||
| 18419 | #define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) | ||
| 18420 | #define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) | ||
| 18421 | /*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. | ||
| 18422 | * 0b000..Main clock. | ||
| 18423 | * 0b001..system PLL divided clock. | ||
| 18424 | * 0b010..FRO 12 MHz clock. | ||
| 18425 | * 0b011..FRO 96 MHz clock. | ||
| 18426 | * 0b100..FRO 1MHz clock. | ||
| 18427 | * 0b101..MCLK clock. | ||
| 18428 | * 0b110..Oscillator 32 kHz clock. | ||
| 18429 | * 0b111..No clock. | ||
| 18430 | */ | ||
| 18431 | #define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) | ||
| 18432 | /*! @} */ | ||
| 18433 | |||
| 18434 | /*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ | ||
| 18435 | /*! @{ */ | ||
| 18436 | #define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) | ||
| 18437 | #define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) | ||
| 18438 | /*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. | ||
| 18439 | * 0b000..Main clock. | ||
| 18440 | * 0b001..system PLL divided clock. | ||
| 18441 | * 0b010..FRO 12 MHz clock. | ||
| 18442 | * 0b011..FRO 96 MHz clock. | ||
| 18443 | * 0b100..FRO 1MHz clock. | ||
| 18444 | * 0b101..MCLK clock. | ||
| 18445 | * 0b110..Oscillator 32 kHz clock. | ||
| 18446 | * 0b111..No clock. | ||
| 18447 | */ | ||
| 18448 | #define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) | ||
| 18449 | /*! @} */ | ||
| 18450 | |||
| 18451 | /*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ | ||
| 18452 | /*! @{ */ | ||
| 18453 | #define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) | ||
| 18454 | #define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) | ||
| 18455 | /*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. | ||
| 18456 | * 0b000..Main clock. | ||
| 18457 | * 0b001..system PLL divided clock. | ||
| 18458 | * 0b010..FRO 12 MHz clock. | ||
| 18459 | * 0b011..FRO 96 MHz clock. | ||
| 18460 | * 0b100..FRO 1MHz clock. | ||
| 18461 | * 0b101..MCLK clock. | ||
| 18462 | * 0b110..Oscillator 32 kHz clock. | ||
| 18463 | * 0b111..No clock. | ||
| 18464 | */ | ||
| 18465 | #define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) | ||
| 18466 | /*! @} */ | ||
| 18467 | |||
| 18468 | /*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ | ||
| 18469 | /*! @{ */ | ||
| 18470 | #define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) | ||
| 18471 | #define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) | ||
| 18472 | /*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. | ||
| 18473 | * 0b000..Main clock. | ||
| 18474 | * 0b001..system PLL divided clock. | ||
| 18475 | * 0b010..FRO 12 MHz clock. | ||
| 18476 | * 0b011..FRO 96 MHz clock. | ||
| 18477 | * 0b100..FRO 1MHz clock. | ||
| 18478 | * 0b101..MCLK clock. | ||
| 18479 | * 0b110..Oscillator 32 kHz clock. | ||
| 18480 | * 0b111..No clock. | ||
| 18481 | */ | ||
| 18482 | #define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) | ||
| 18483 | /*! @} */ | ||
| 18484 | |||
| 18485 | /*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ | ||
| 18486 | /*! @{ */ | ||
| 18487 | #define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) | ||
| 18488 | #define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) | ||
| 18489 | /*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. | ||
| 18490 | * 0b000..Main clock. | ||
| 18491 | * 0b001..system PLL divided clock. | ||
| 18492 | * 0b010..FRO 12 MHz clock. | ||
| 18493 | * 0b011..FRO 96 MHz clock. | ||
| 18494 | * 0b100..FRO 1MHz clock. | ||
| 18495 | * 0b101..MCLK clock. | ||
| 18496 | * 0b110..Oscillator 32 kHz clock. | ||
| 18497 | * 0b111..No clock. | ||
| 18498 | */ | ||
| 18499 | #define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) | ||
| 18500 | /*! @} */ | ||
| 18501 | |||
| 18502 | /*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ | ||
| 18503 | /*! @{ */ | ||
| 18504 | #define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) | ||
| 18505 | #define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) | ||
| 18506 | /*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. | ||
| 18507 | * 0b000..Main clock. | ||
| 18508 | * 0b001..system PLL divided clock. | ||
| 18509 | * 0b010..FRO 12 MHz clock. | ||
| 18510 | * 0b011..FRO 96 MHz clock. | ||
| 18511 | * 0b100..FRO 1MHz clock. | ||
| 18512 | * 0b101..MCLK clock. | ||
| 18513 | * 0b110..Oscillator 32 kHz clock. | ||
| 18514 | * 0b111..No clock. | ||
| 18515 | */ | ||
| 18516 | #define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) | ||
| 18517 | /*! @} */ | ||
| 18518 | |||
| 18519 | /*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ | ||
| 18520 | /*! @{ */ | ||
| 18521 | #define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) | ||
| 18522 | #define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) | ||
| 18523 | /*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. | ||
| 18524 | * 0b000..Main clock. | ||
| 18525 | * 0b001..system PLL divided clock. | ||
| 18526 | * 0b010..FRO 12 MHz clock. | ||
| 18527 | * 0b011..FRO 96 MHz clock. | ||
| 18528 | * 0b100..FRO 1MHz clock. | ||
| 18529 | * 0b101..MCLK clock. | ||
| 18530 | * 0b110..Oscillator 32 kHz clock. | ||
| 18531 | * 0b111..No clock. | ||
| 18532 | */ | ||
| 18533 | #define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) | ||
| 18534 | /*! @} */ | ||
| 18535 | |||
| 18536 | /*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ | ||
| 18537 | /*! @{ */ | ||
| 18538 | #define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) | ||
| 18539 | #define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) | ||
| 18540 | /*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. | ||
| 18541 | * 0b000..Main clock. | ||
| 18542 | * 0b001..system PLL divided clock. | ||
| 18543 | * 0b010..FRO 12 MHz clock. | ||
| 18544 | * 0b011..FRO 96 MHz clock. | ||
| 18545 | * 0b100..FRO 1MHz clock. | ||
| 18546 | * 0b101..MCLK clock. | ||
| 18547 | * 0b110..Oscillator 32 kHz clock. | ||
| 18548 | * 0b111..No clock. | ||
| 18549 | */ | ||
| 18550 | #define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) | ||
| 18551 | /*! @} */ | ||
| 18552 | |||
| 18553 | /*! @name FCCLKSELX - Peripheral reset control register */ | ||
| 18554 | /*! @{ */ | ||
| 18555 | #define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) | ||
| 18556 | #define SYSCON_FCCLKSELX_DATA_SHIFT (0U) | ||
| 18557 | /*! DATA - Data array value | ||
| 18558 | */ | ||
| 18559 | #define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) | ||
| 18560 | /*! @} */ | ||
| 18561 | |||
| 18562 | /* The count of SYSCON_FCCLKSELX */ | ||
| 18563 | #define SYSCON_FCCLKSELX_COUNT (8U) | ||
| 18564 | |||
| 18565 | /*! @name HSLSPICLKSEL - HS LSPI clock source select */ | ||
| 18566 | /*! @{ */ | ||
| 18567 | #define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) | ||
| 18568 | #define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) | ||
| 18569 | /*! SEL - HS LSPI clock source select. | ||
| 18570 | * 0b000..Main clock. | ||
| 18571 | * 0b001..system PLL divided clock. | ||
| 18572 | * 0b010..FRO 12 MHz clock. | ||
| 18573 | * 0b011..FRO 96 MHz clock. | ||
| 18574 | * 0b100..FRO 1MHz clock. | ||
| 18575 | * 0b101..No clock. | ||
| 18576 | * 0b110..Oscillator 32 kHz clock. | ||
| 18577 | * 0b111..No clock. | ||
| 18578 | */ | ||
| 18579 | #define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) | ||
| 18580 | /*! @} */ | ||
| 18581 | |||
| 18582 | /*! @name MCLKCLKSEL - MCLK clock source select */ | ||
| 18583 | /*! @{ */ | ||
| 18584 | #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) | ||
| 18585 | #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) | ||
| 18586 | /*! SEL - MCLK clock source select. | ||
| 18587 | * 0b000..FRO 96 MHz clock. | ||
| 18588 | * 0b001..PLL0 clock. | ||
| 18589 | * 0b010..Reserved. | ||
| 18590 | * 0b011..Reserved. | ||
| 18591 | * 0b100..No clock. | ||
| 18592 | * 0b101..No clock. | ||
| 18593 | * 0b110..No clock. | ||
| 18594 | * 0b111..No clock. | ||
| 18595 | */ | ||
| 18596 | #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) | ||
| 18597 | /*! @} */ | ||
| 18598 | |||
| 18599 | /*! @name SCTCLKSEL - SCTimer/PWM clock source select */ | ||
| 18600 | /*! @{ */ | ||
| 18601 | #define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) | ||
| 18602 | #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) | ||
| 18603 | /*! SEL - SCTimer/PWM clock source select. | ||
| 18604 | * 0b000..Main clock. | ||
| 18605 | * 0b001..PLL0 clock. | ||
| 18606 | * 0b010..CLKIN clock. | ||
| 18607 | * 0b011..FRO 96 MHz clock. | ||
| 18608 | * 0b100..No clock. | ||
| 18609 | * 0b101..MCLK clock. | ||
| 18610 | * 0b110..No clock. | ||
| 18611 | * 0b111..No clock. | ||
| 18612 | */ | ||
| 18613 | #define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) | ||
| 18614 | /*! @} */ | ||
| 18615 | |||
| 18616 | /*! @name SDIOCLKSEL - SDIO clock source select */ | ||
| 18617 | /*! @{ */ | ||
| 18618 | #define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) | ||
| 18619 | #define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) | ||
| 18620 | /*! SEL - SDIO clock source select. | ||
| 18621 | * 0b000..Main clock. | ||
| 18622 | * 0b001..PLL0 clock. | ||
| 18623 | * 0b010..No clock. | ||
| 18624 | * 0b011..FRO 96 MHz clock. | ||
| 18625 | * 0b100..No clock. | ||
| 18626 | * 0b101..PLL1 clock. | ||
| 18627 | * 0b110..No clock. | ||
| 18628 | * 0b111..No clock. | ||
| 18629 | */ | ||
| 18630 | #define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) | ||
| 18631 | /*! @} */ | ||
| 18632 | |||
| 18633 | /*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ | ||
| 18634 | /*! @{ */ | ||
| 18635 | #define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) | ||
| 18636 | #define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) | ||
| 18637 | /*! DIV - Clock divider value. | ||
| 18638 | */ | ||
| 18639 | #define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) | ||
| 18640 | #define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) | ||
| 18641 | #define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) | ||
| 18642 | /*! RESET - Resets the divider counter. | ||
| 18643 | * 0b1..Divider is reset. | ||
| 18644 | * 0b0..Divider is not reset. | ||
| 18645 | */ | ||
| 18646 | #define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) | ||
| 18647 | #define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) | ||
| 18648 | #define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) | ||
| 18649 | /*! HALT - Halts the divider counter. | ||
| 18650 | * 0b1..Divider clock is stoped. | ||
| 18651 | * 0b0..Divider clock is running. | ||
| 18652 | */ | ||
| 18653 | #define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) | ||
| 18654 | #define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) | ||
| 18655 | #define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) | ||
| 18656 | /*! REQFLAG - Divider status flag. | ||
| 18657 | * 0b1..Clock frequency is not stable. | ||
| 18658 | * 0b0..Divider clock is stable. | ||
| 18659 | */ | ||
| 18660 | #define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) | ||
| 18661 | /*! @} */ | ||
| 18662 | |||
| 18663 | /*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ | ||
| 18664 | /*! @{ */ | ||
| 18665 | #define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) | ||
| 18666 | #define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) | ||
| 18667 | /*! DIV - Clock divider value. | ||
| 18668 | */ | ||
| 18669 | #define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) | ||
| 18670 | #define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) | ||
| 18671 | #define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) | ||
| 18672 | /*! RESET - Resets the divider counter. | ||
| 18673 | * 0b1..Divider is reset. | ||
| 18674 | * 0b0..Divider is not reset. | ||
| 18675 | */ | ||
| 18676 | #define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) | ||
| 18677 | #define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) | ||
| 18678 | #define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) | ||
| 18679 | /*! HALT - Halts the divider counter. | ||
| 18680 | * 0b1..Divider clock is stoped. | ||
| 18681 | * 0b0..Divider clock is running. | ||
| 18682 | */ | ||
| 18683 | #define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) | ||
| 18684 | #define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) | ||
| 18685 | #define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) | ||
| 18686 | /*! REQFLAG - Divider status flag. | ||
| 18687 | * 0b1..Clock frequency is not stable. | ||
| 18688 | * 0b0..Divider clock is stable. | ||
| 18689 | */ | ||
| 18690 | #define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) | ||
| 18691 | /*! @} */ | ||
| 18692 | |||
| 18693 | /*! @name TRACECLKDIV - TRACE clock divider */ | ||
| 18694 | /*! @{ */ | ||
| 18695 | #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) | ||
| 18696 | #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) | ||
| 18697 | /*! DIV - Clock divider value. | ||
| 18698 | */ | ||
| 18699 | #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) | ||
| 18700 | #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) | ||
| 18701 | #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) | ||
| 18702 | /*! RESET - Resets the divider counter. | ||
| 18703 | * 0b1..Divider is reset. | ||
| 18704 | * 0b0..Divider is not reset. | ||
| 18705 | */ | ||
| 18706 | #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) | ||
| 18707 | #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) | ||
| 18708 | #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) | ||
| 18709 | /*! HALT - Halts the divider counter. | ||
| 18710 | * 0b1..Divider clock is stoped. | ||
| 18711 | * 0b0..Divider clock is running. | ||
| 18712 | */ | ||
| 18713 | #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) | ||
| 18714 | #define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 18715 | #define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) | ||
| 18716 | /*! REQFLAG - Divider status flag. | ||
| 18717 | * 0b1..Clock frequency is not stable. | ||
| 18718 | * 0b0..Divider clock is stable. | ||
| 18719 | */ | ||
| 18720 | #define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) | ||
| 18721 | /*! @} */ | ||
| 18722 | |||
| 18723 | /*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ | ||
| 18724 | /*! @{ */ | ||
| 18725 | #define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) | ||
| 18726 | #define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) | ||
| 18727 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18728 | */ | ||
| 18729 | #define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) | ||
| 18730 | #define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) | ||
| 18731 | #define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) | ||
| 18732 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18733 | */ | ||
| 18734 | #define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) | ||
| 18735 | /*! @} */ | ||
| 18736 | |||
| 18737 | /*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ | ||
| 18738 | /*! @{ */ | ||
| 18739 | #define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) | ||
| 18740 | #define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) | ||
| 18741 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18742 | */ | ||
| 18743 | #define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) | ||
| 18744 | #define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) | ||
| 18745 | #define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) | ||
| 18746 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18747 | */ | ||
| 18748 | #define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) | ||
| 18749 | /*! @} */ | ||
| 18750 | |||
| 18751 | /*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ | ||
| 18752 | /*! @{ */ | ||
| 18753 | #define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) | ||
| 18754 | #define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) | ||
| 18755 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18756 | */ | ||
| 18757 | #define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) | ||
| 18758 | #define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) | ||
| 18759 | #define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) | ||
| 18760 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18761 | */ | ||
| 18762 | #define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) | ||
| 18763 | /*! @} */ | ||
| 18764 | |||
| 18765 | /*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ | ||
| 18766 | /*! @{ */ | ||
| 18767 | #define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) | ||
| 18768 | #define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) | ||
| 18769 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18770 | */ | ||
| 18771 | #define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) | ||
| 18772 | #define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) | ||
| 18773 | #define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) | ||
| 18774 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18775 | */ | ||
| 18776 | #define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) | ||
| 18777 | /*! @} */ | ||
| 18778 | |||
| 18779 | /*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ | ||
| 18780 | /*! @{ */ | ||
| 18781 | #define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) | ||
| 18782 | #define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) | ||
| 18783 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18784 | */ | ||
| 18785 | #define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) | ||
| 18786 | #define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) | ||
| 18787 | #define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) | ||
| 18788 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18789 | */ | ||
| 18790 | #define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) | ||
| 18791 | /*! @} */ | ||
| 18792 | |||
| 18793 | /*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ | ||
| 18794 | /*! @{ */ | ||
| 18795 | #define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) | ||
| 18796 | #define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) | ||
| 18797 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18798 | */ | ||
| 18799 | #define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) | ||
| 18800 | #define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) | ||
| 18801 | #define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) | ||
| 18802 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18803 | */ | ||
| 18804 | #define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) | ||
| 18805 | /*! @} */ | ||
| 18806 | |||
| 18807 | /*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ | ||
| 18808 | /*! @{ */ | ||
| 18809 | #define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) | ||
| 18810 | #define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) | ||
| 18811 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18812 | */ | ||
| 18813 | #define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) | ||
| 18814 | #define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) | ||
| 18815 | #define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) | ||
| 18816 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18817 | */ | ||
| 18818 | #define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) | ||
| 18819 | /*! @} */ | ||
| 18820 | |||
| 18821 | /*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ | ||
| 18822 | /*! @{ */ | ||
| 18823 | #define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) | ||
| 18824 | #define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) | ||
| 18825 | /*! DIV - Denominator of the fractional rate divider. | ||
| 18826 | */ | ||
| 18827 | #define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) | ||
| 18828 | #define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) | ||
| 18829 | #define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) | ||
| 18830 | /*! MULT - Numerator of the fractional rate divider. | ||
| 18831 | */ | ||
| 18832 | #define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) | ||
| 18833 | /*! @} */ | ||
| 18834 | |||
| 18835 | /*! @name FLEXFRGXCTRL - Peripheral reset control register */ | ||
| 18836 | /*! @{ */ | ||
| 18837 | #define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) | ||
| 18838 | #define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) | ||
| 18839 | /*! DATA - Data array value | ||
| 18840 | */ | ||
| 18841 | #define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) | ||
| 18842 | /*! @} */ | ||
| 18843 | |||
| 18844 | /* The count of SYSCON_FLEXFRGXCTRL */ | ||
| 18845 | #define SYSCON_FLEXFRGXCTRL_COUNT (8U) | ||
| 18846 | |||
| 18847 | /*! @name AHBCLKDIV - System clock divider */ | ||
| 18848 | /*! @{ */ | ||
| 18849 | #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) | ||
| 18850 | #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) | ||
| 18851 | /*! DIV - Clock divider value. | ||
| 18852 | */ | ||
| 18853 | #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) | ||
| 18854 | #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) | ||
| 18855 | #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) | ||
| 18856 | /*! RESET - Resets the divider counter. | ||
| 18857 | * 0b1..Divider is reset. | ||
| 18858 | * 0b0..Divider is not reset. | ||
| 18859 | */ | ||
| 18860 | #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) | ||
| 18861 | #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) | ||
| 18862 | #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) | ||
| 18863 | /*! HALT - Halts the divider counter. | ||
| 18864 | * 0b1..Divider clock is stoped. | ||
| 18865 | * 0b0..Divider clock is running. | ||
| 18866 | */ | ||
| 18867 | #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) | ||
| 18868 | #define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 18869 | #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) | ||
| 18870 | /*! REQFLAG - Divider status flag. | ||
| 18871 | * 0b1..Clock frequency is not stable. | ||
| 18872 | * 0b0..Divider clock is stable. | ||
| 18873 | */ | ||
| 18874 | #define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) | ||
| 18875 | /*! @} */ | ||
| 18876 | |||
| 18877 | /*! @name CLKOUTDIV - CLKOUT clock divider */ | ||
| 18878 | /*! @{ */ | ||
| 18879 | #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) | ||
| 18880 | #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) | ||
| 18881 | /*! DIV - Clock divider value. | ||
| 18882 | */ | ||
| 18883 | #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) | ||
| 18884 | #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) | ||
| 18885 | #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) | ||
| 18886 | /*! RESET - Resets the divider counter. | ||
| 18887 | * 0b1..Divider is reset. | ||
| 18888 | * 0b0..Divider is not reset. | ||
| 18889 | */ | ||
| 18890 | #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) | ||
| 18891 | #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) | ||
| 18892 | #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) | ||
| 18893 | /*! HALT - Halts the divider counter. | ||
| 18894 | * 0b1..Divider clock is stoped. | ||
| 18895 | * 0b0..Divider clock is running. | ||
| 18896 | */ | ||
| 18897 | #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) | ||
| 18898 | #define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) | ||
| 18899 | #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) | ||
| 18900 | /*! REQFLAG - Divider status flag. | ||
| 18901 | * 0b1..Clock frequency is not stable. | ||
| 18902 | * 0b0..Divider clock is stable. | ||
| 18903 | */ | ||
| 18904 | #define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) | ||
| 18905 | /*! @} */ | ||
| 18906 | |||
| 18907 | /*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ | ||
| 18908 | /*! @{ */ | ||
| 18909 | #define SYSCON_FROHFDIV_DIV_MASK (0xFFU) | ||
| 18910 | #define SYSCON_FROHFDIV_DIV_SHIFT (0U) | ||
| 18911 | /*! DIV - Clock divider value. | ||
| 18912 | */ | ||
| 18913 | #define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) | ||
| 18914 | #define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) | ||
| 18915 | #define SYSCON_FROHFDIV_RESET_SHIFT (29U) | ||
| 18916 | /*! RESET - Resets the divider counter. | ||
| 18917 | * 0b1..Divider is reset. | ||
| 18918 | * 0b0..Divider is not reset. | ||
| 18919 | */ | ||
| 18920 | #define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) | ||
| 18921 | #define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) | ||
| 18922 | #define SYSCON_FROHFDIV_HALT_SHIFT (30U) | ||
| 18923 | /*! HALT - Halts the divider counter. | ||
| 18924 | * 0b1..Divider clock is stoped. | ||
| 18925 | * 0b0..Divider clock is running. | ||
| 18926 | */ | ||
| 18927 | #define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) | ||
| 18928 | #define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) | ||
| 18929 | #define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) | ||
| 18930 | /*! REQFLAG - Divider status flag. | ||
| 18931 | * 0b1..Clock frequency is not stable. | ||
| 18932 | * 0b0..Divider clock is stable. | ||
| 18933 | */ | ||
| 18934 | #define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) | ||
| 18935 | /*! @} */ | ||
| 18936 | |||
| 18937 | /*! @name WDTCLKDIV - WDT clock divider */ | ||
| 18938 | /*! @{ */ | ||
| 18939 | #define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) | ||
| 18940 | #define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) | ||
| 18941 | /*! DIV - Clock divider value. | ||
| 18942 | */ | ||
| 18943 | #define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) | ||
| 18944 | #define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) | ||
| 18945 | #define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) | ||
| 18946 | /*! RESET - Resets the divider counter. | ||
| 18947 | * 0b1..Divider is reset. | ||
| 18948 | * 0b0..Divider is not reset. | ||
| 18949 | */ | ||
| 18950 | #define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) | ||
| 18951 | #define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) | ||
| 18952 | #define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) | ||
| 18953 | /*! HALT - Halts the divider counter. | ||
| 18954 | * 0b1..Divider clock is stoped. | ||
| 18955 | * 0b0..Divider clock is running. | ||
| 18956 | */ | ||
| 18957 | #define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) | ||
| 18958 | #define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 18959 | #define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) | ||
| 18960 | /*! REQFLAG - Divider status flag. | ||
| 18961 | * 0b1..Clock frequency is not stable. | ||
| 18962 | * 0b0..Divider clock is stable. | ||
| 18963 | */ | ||
| 18964 | #define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) | ||
| 18965 | /*! @} */ | ||
| 18966 | |||
| 18967 | /*! @name ADCCLKDIV - ADC clock divider */ | ||
| 18968 | /*! @{ */ | ||
| 18969 | #define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) | ||
| 18970 | #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) | ||
| 18971 | /*! DIV - Clock divider value. | ||
| 18972 | */ | ||
| 18973 | #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) | ||
| 18974 | #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) | ||
| 18975 | #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) | ||
| 18976 | /*! RESET - Resets the divider counter. | ||
| 18977 | * 0b1..Divider is reset. | ||
| 18978 | * 0b0..Divider is not reset. | ||
| 18979 | */ | ||
| 18980 | #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) | ||
| 18981 | #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) | ||
| 18982 | #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) | ||
| 18983 | /*! HALT - Halts the divider counter. | ||
| 18984 | * 0b1..Divider clock is stoped. | ||
| 18985 | * 0b0..Divider clock is running. | ||
| 18986 | */ | ||
| 18987 | #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) | ||
| 18988 | #define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 18989 | #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) | ||
| 18990 | /*! REQFLAG - Divider status flag. | ||
| 18991 | * 0b1..Clock frequency is not stable. | ||
| 18992 | * 0b0..Divider clock is stable. | ||
| 18993 | */ | ||
| 18994 | #define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) | ||
| 18995 | /*! @} */ | ||
| 18996 | |||
| 18997 | /*! @name USB0CLKDIV - USB0 Clock divider */ | ||
| 18998 | /*! @{ */ | ||
| 18999 | #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) | ||
| 19000 | #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) | ||
| 19001 | /*! DIV - Clock divider value. | ||
| 19002 | */ | ||
| 19003 | #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) | ||
| 19004 | #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) | ||
| 19005 | #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) | ||
| 19006 | /*! RESET - Resets the divider counter. | ||
| 19007 | * 0b1..Divider is reset. | ||
| 19008 | * 0b0..Divider is not reset. | ||
| 19009 | */ | ||
| 19010 | #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) | ||
| 19011 | #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) | ||
| 19012 | #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) | ||
| 19013 | /*! HALT - Halts the divider counter. | ||
| 19014 | * 0b1..Divider clock is stoped. | ||
| 19015 | * 0b0..Divider clock is running. | ||
| 19016 | */ | ||
| 19017 | #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) | ||
| 19018 | #define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 19019 | #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) | ||
| 19020 | /*! REQFLAG - Divider status flag. | ||
| 19021 | * 0b1..Clock frequency is not stable. | ||
| 19022 | * 0b0..Divider clock is stable. | ||
| 19023 | */ | ||
| 19024 | #define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) | ||
| 19025 | /*! @} */ | ||
| 19026 | |||
| 19027 | /*! @name MCLKDIV - I2S MCLK clock divider */ | ||
| 19028 | /*! @{ */ | ||
| 19029 | #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) | ||
| 19030 | #define SYSCON_MCLKDIV_DIV_SHIFT (0U) | ||
| 19031 | /*! DIV - Clock divider value. | ||
| 19032 | */ | ||
| 19033 | #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) | ||
| 19034 | #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) | ||
| 19035 | #define SYSCON_MCLKDIV_RESET_SHIFT (29U) | ||
| 19036 | /*! RESET - Resets the divider counter. | ||
| 19037 | * 0b1..Divider is reset. | ||
| 19038 | * 0b0..Divider is not reset. | ||
| 19039 | */ | ||
| 19040 | #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) | ||
| 19041 | #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) | ||
| 19042 | #define SYSCON_MCLKDIV_HALT_SHIFT (30U) | ||
| 19043 | /*! HALT - Halts the divider counter. | ||
| 19044 | * 0b1..Divider clock is stoped. | ||
| 19045 | * 0b0..Divider clock is running. | ||
| 19046 | */ | ||
| 19047 | #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) | ||
| 19048 | #define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 19049 | #define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) | ||
| 19050 | /*! REQFLAG - Divider status flag. | ||
| 19051 | * 0b1..Clock frequency is not stable. | ||
| 19052 | * 0b0..Divider clock is stable. | ||
| 19053 | */ | ||
| 19054 | #define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) | ||
| 19055 | /*! @} */ | ||
| 19056 | |||
| 19057 | /*! @name SCTCLKDIV - SCT/PWM clock divider */ | ||
| 19058 | /*! @{ */ | ||
| 19059 | #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) | ||
| 19060 | #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) | ||
| 19061 | /*! DIV - Clock divider value. | ||
| 19062 | */ | ||
| 19063 | #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) | ||
| 19064 | #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) | ||
| 19065 | #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) | ||
| 19066 | /*! RESET - Resets the divider counter. | ||
| 19067 | * 0b1..Divider is reset. | ||
| 19068 | * 0b0..Divider is not reset. | ||
| 19069 | */ | ||
| 19070 | #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) | ||
| 19071 | #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) | ||
| 19072 | #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) | ||
| 19073 | /*! HALT - Halts the divider counter. | ||
| 19074 | * 0b1..Divider clock is stoped. | ||
| 19075 | * 0b0..Divider clock is running. | ||
| 19076 | */ | ||
| 19077 | #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) | ||
| 19078 | #define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 19079 | #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) | ||
| 19080 | /*! REQFLAG - Divider status flag. | ||
| 19081 | * 0b1..Clock frequency is not stable. | ||
| 19082 | * 0b0..Divider clock is stable. | ||
| 19083 | */ | ||
| 19084 | #define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) | ||
| 19085 | /*! @} */ | ||
| 19086 | |||
| 19087 | /*! @name SDIOCLKDIV - SDIO clock divider */ | ||
| 19088 | /*! @{ */ | ||
| 19089 | #define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) | ||
| 19090 | #define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) | ||
| 19091 | /*! DIV - Clock divider value. | ||
| 19092 | */ | ||
| 19093 | #define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) | ||
| 19094 | #define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) | ||
| 19095 | #define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) | ||
| 19096 | /*! RESET - Resets the divider counter. | ||
| 19097 | * 0b1..Divider is reset. | ||
| 19098 | * 0b0..Divider is not reset. | ||
| 19099 | */ | ||
| 19100 | #define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) | ||
| 19101 | #define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) | ||
| 19102 | #define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) | ||
| 19103 | /*! HALT - Halts the divider counter. | ||
| 19104 | * 0b1..Divider clock is stoped. | ||
| 19105 | * 0b0..Divider clock is running. | ||
| 19106 | */ | ||
| 19107 | #define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) | ||
| 19108 | #define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 19109 | #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) | ||
| 19110 | /*! REQFLAG - Divider status flag. | ||
| 19111 | * 0b1..Clock frequency is not stable. | ||
| 19112 | * 0b0..Divider clock is stable. | ||
| 19113 | */ | ||
| 19114 | #define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) | ||
| 19115 | /*! @} */ | ||
| 19116 | |||
| 19117 | /*! @name PLL0CLKDIV - PLL0 clock divider */ | ||
| 19118 | /*! @{ */ | ||
| 19119 | #define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) | ||
| 19120 | #define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) | ||
| 19121 | /*! DIV - Clock divider value. | ||
| 19122 | */ | ||
| 19123 | #define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) | ||
| 19124 | #define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) | ||
| 19125 | #define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) | ||
| 19126 | /*! RESET - Resets the divider counter. | ||
| 19127 | * 0b1..Divider is reset. | ||
| 19128 | * 0b0..Divider is not reset. | ||
| 19129 | */ | ||
| 19130 | #define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) | ||
| 19131 | #define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) | ||
| 19132 | #define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) | ||
| 19133 | /*! HALT - Halts the divider counter. | ||
| 19134 | * 0b1..Divider clock is stoped. | ||
| 19135 | * 0b0..Divider clock is running. | ||
| 19136 | */ | ||
| 19137 | #define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) | ||
| 19138 | #define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) | ||
| 19139 | #define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) | ||
| 19140 | /*! REQFLAG - Divider status flag. | ||
| 19141 | * 0b1..Clock frequency is not stable. | ||
| 19142 | * 0b0..Divider clock is stable. | ||
| 19143 | */ | ||
| 19144 | #define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) | ||
| 19145 | /*! @} */ | ||
| 19146 | |||
| 19147 | /*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ | ||
| 19148 | /*! @{ */ | ||
| 19149 | #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) | ||
| 19150 | #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) | ||
| 19151 | /*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). | ||
| 19152 | * 0b00000000000000000000000000000001..update all clock configuration. | ||
| 19153 | * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. | ||
| 19154 | */ | ||
| 19155 | #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) | ||
| 19156 | /*! @} */ | ||
| 19157 | |||
| 19158 | /*! @name FMCCR - FMC configuration register */ | ||
| 19159 | /*! @{ */ | ||
| 19160 | #define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) | ||
| 19161 | #define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) | ||
| 19162 | /*! FETCHCFG - Instruction fetch configuration. | ||
| 19163 | * 0b00..Instruction fetches from flash are not buffered. | ||
| 19164 | * 0b01..One buffer is used for all instruction fetches. | ||
| 19165 | * 0b10..All buffers may be used for instruction fetches. | ||
| 19166 | */ | ||
| 19167 | #define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) | ||
| 19168 | #define SYSCON_FMCCR_DATACFG_MASK (0xCU) | ||
| 19169 | #define SYSCON_FMCCR_DATACFG_SHIFT (2U) | ||
| 19170 | /*! DATACFG - Data read configuration. | ||
| 19171 | * 0b00..Data accesses from flash are not buffered. | ||
| 19172 | * 0b01..One buffer is used for all data accesses. | ||
| 19173 | * 0b10..All buffers can be used for data accesses. | ||
| 19174 | */ | ||
| 19175 | #define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) | ||
| 19176 | #define SYSCON_FMCCR_ACCEL_MASK (0x10U) | ||
| 19177 | #define SYSCON_FMCCR_ACCEL_SHIFT (4U) | ||
| 19178 | /*! ACCEL - Acceleration enable. | ||
| 19179 | * 0b0..Flash acceleration is disabled. | ||
| 19180 | * 0b1..Flash acceleration is enabled. | ||
| 19181 | */ | ||
| 19182 | #define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) | ||
| 19183 | #define SYSCON_FMCCR_PREFEN_MASK (0x20U) | ||
| 19184 | #define SYSCON_FMCCR_PREFEN_SHIFT (5U) | ||
| 19185 | /*! PREFEN - Prefetch enable. | ||
| 19186 | * 0b0..No instruction prefetch is performed. | ||
| 19187 | * 0b1..Instruction prefetch is enabled. | ||
| 19188 | */ | ||
| 19189 | #define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) | ||
| 19190 | #define SYSCON_FMCCR_PREFOVR_MASK (0x40U) | ||
| 19191 | #define SYSCON_FMCCR_PREFOVR_SHIFT (6U) | ||
| 19192 | /*! PREFOVR - Prefetch override. | ||
| 19193 | * 0b0..Any previously initiated prefetch will be completed. | ||
| 19194 | * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current | ||
| 19195 | * execution address will be prefetched if not already buffered. | ||
| 19196 | */ | ||
| 19197 | #define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) | ||
| 19198 | #define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) | ||
| 19199 | #define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) | ||
| 19200 | /*! FLASHTIM - Flash memory access time. | ||
| 19201 | * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). | ||
| 19202 | * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). | ||
| 19203 | * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). | ||
| 19204 | * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). | ||
| 19205 | * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). | ||
| 19206 | * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). | ||
| 19207 | * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). | ||
| 19208 | * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). | ||
| 19209 | * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). | ||
| 19210 | * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). | ||
| 19211 | * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). | ||
| 19212 | * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). | ||
| 19213 | */ | ||
| 19214 | #define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) | ||
| 19215 | /*! @} */ | ||
| 19216 | |||
| 19217 | /*! @name USB0NEEDCLKCTRL - USB0 need clock control */ | ||
| 19218 | /*! @{ */ | ||
| 19219 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) | ||
| 19220 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) | ||
| 19221 | /*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. | ||
| 19222 | * 0b0..Under hardware control. | ||
| 19223 | * 0b1..Forced high. | ||
| 19224 | */ | ||
| 19225 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) | ||
| 19226 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) | ||
| 19227 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) | ||
| 19228 | /*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. | ||
| 19229 | * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. | ||
| 19230 | * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. | ||
| 19231 | */ | ||
| 19232 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) | ||
| 19233 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) | ||
| 19234 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) | ||
| 19235 | /*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. | ||
| 19236 | * 0b0..Under hardware control. | ||
| 19237 | * 0b1..Forced high. | ||
| 19238 | */ | ||
| 19239 | #define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) | ||
| 19240 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) | ||
| 19241 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) | ||
| 19242 | /*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. | ||
| 19243 | * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. | ||
| 19244 | * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. | ||
| 19245 | */ | ||
| 19246 | #define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) | ||
| 19247 | /*! @} */ | ||
| 19248 | |||
| 19249 | /*! @name USB0NEEDCLKSTAT - USB0 need clock status */ | ||
| 19250 | /*! @{ */ | ||
| 19251 | #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) | ||
| 19252 | #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) | ||
| 19253 | /*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. | ||
| 19254 | * 0b1..USB0 Device clock is high. | ||
| 19255 | * 0b0..USB0 Device clock is low. | ||
| 19256 | */ | ||
| 19257 | #define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) | ||
| 19258 | #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) | ||
| 19259 | #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) | ||
| 19260 | /*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. | ||
| 19261 | * 0b1..USB0 Host clock is high. | ||
| 19262 | * 0b0..USB0 Host clock is low. | ||
| 19263 | */ | ||
| 19264 | #define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) | ||
| 19265 | /*! @} */ | ||
| 19266 | |||
| 19267 | /*! @name FMCFLUSH - FMCflush control */ | ||
| 19268 | /*! @{ */ | ||
| 19269 | #define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) | ||
| 19270 | #define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) | ||
| 19271 | /*! FLUSH - Flush control | ||
| 19272 | * 0b1..Flush the FMC buffer contents. | ||
| 19273 | * 0b0..No action is performed. | ||
| 19274 | */ | ||
| 19275 | #define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) | ||
| 19276 | /*! @} */ | ||
| 19277 | |||
| 19278 | /*! @name MCLKIO - MCLK control */ | ||
| 19279 | /*! @{ */ | ||
| 19280 | #define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) | ||
| 19281 | #define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) | ||
| 19282 | /*! MCLKIO - MCLK control. | ||
| 19283 | * 0b0..input mode. | ||
| 19284 | * 0b1..output mode. | ||
| 19285 | */ | ||
| 19286 | #define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) | ||
| 19287 | /*! @} */ | ||
| 19288 | |||
| 19289 | /*! @name USB1NEEDCLKCTRL - USB1 need clock control */ | ||
| 19290 | /*! @{ */ | ||
| 19291 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) | ||
| 19292 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) | ||
| 19293 | /*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: | ||
| 19294 | * 0b0..HOST_NEEDCLK is under hardware control. | ||
| 19295 | * 0b1..HOST_NEEDCLK is forced high. | ||
| 19296 | */ | ||
| 19297 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) | ||
| 19298 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) | ||
| 19299 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) | ||
| 19300 | /*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: | ||
| 19301 | * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. | ||
| 19302 | * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. | ||
| 19303 | */ | ||
| 19304 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) | ||
| 19305 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) | ||
| 19306 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) | ||
| 19307 | /*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: | ||
| 19308 | * 0b0..HOST_NEEDCLK is under hardware control. | ||
| 19309 | * 0b1..HOST_NEEDCLK is forced high. | ||
| 19310 | */ | ||
| 19311 | #define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) | ||
| 19312 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) | ||
| 19313 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) | ||
| 19314 | /*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. | ||
| 19315 | * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. | ||
| 19316 | * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. | ||
| 19317 | */ | ||
| 19318 | #define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) | ||
| 19319 | #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) | ||
| 19320 | #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) | ||
| 19321 | /*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. | ||
| 19322 | * 0b0..Forces USB1_PHY to wake-up. | ||
| 19323 | * 0b1..Normal USB1_PHY behavior. | ||
| 19324 | */ | ||
| 19325 | #define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) | ||
| 19326 | /*! @} */ | ||
| 19327 | |||
| 19328 | /*! @name USB1NEEDCLKSTAT - USB1 need clock status */ | ||
| 19329 | /*! @{ */ | ||
| 19330 | #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) | ||
| 19331 | #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) | ||
| 19332 | /*! DEV_NEEDCLK - USB1 Device need_clock signal status:. | ||
| 19333 | * 0b1..DEV_NEEDCLK is high. | ||
| 19334 | * 0b0..DEV_NEEDCLK is low. | ||
| 19335 | */ | ||
| 19336 | #define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) | ||
| 19337 | #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) | ||
| 19338 | #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) | ||
| 19339 | /*! HOST_NEEDCLK - USB1 Host need_clock signal status:. | ||
| 19340 | * 0b1..HOST_NEEDCLK is high. | ||
| 19341 | * 0b0..HOST_NEEDCLK is low. | ||
| 19342 | */ | ||
| 19343 | #define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) | ||
| 19344 | /*! @} */ | ||
| 19345 | |||
| 19346 | /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ | ||
| 19347 | /*! @{ */ | ||
| 19348 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) | ||
| 19349 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) | ||
| 19350 | /*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. | ||
| 19351 | * 0b00..0 degree shift. | ||
| 19352 | * 0b01..90 degree shift. | ||
| 19353 | * 0b10..180 degree shift. | ||
| 19354 | * 0b11..270 degree shift. | ||
| 19355 | */ | ||
| 19356 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) | ||
| 19357 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) | ||
| 19358 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) | ||
| 19359 | /*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. | ||
| 19360 | * 0b00..0 degree shift. | ||
| 19361 | * 0b01..90 degree shift. | ||
| 19362 | * 0b10..180 degree shift. | ||
| 19363 | * 0b11..270 degree shift. | ||
| 19364 | */ | ||
| 19365 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) | ||
| 19366 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) | ||
| 19367 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) | ||
| 19368 | /*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. | ||
| 19369 | * 0b0..Bypassed. | ||
| 19370 | * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. | ||
| 19371 | */ | ||
| 19372 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) | ||
| 19373 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) | ||
| 19374 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) | ||
| 19375 | /*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. | ||
| 19376 | */ | ||
| 19377 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) | ||
| 19378 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) | ||
| 19379 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) | ||
| 19380 | /*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. | ||
| 19381 | * 0b1..Enable drive delay. | ||
| 19382 | * 0b0..Disable drive delay. | ||
| 19383 | */ | ||
| 19384 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) | ||
| 19385 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) | ||
| 19386 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) | ||
| 19387 | /*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. | ||
| 19388 | */ | ||
| 19389 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) | ||
| 19390 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) | ||
| 19391 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) | ||
| 19392 | /*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. | ||
| 19393 | * 0b1..Enables sample delay. | ||
| 19394 | * 0b0..Disables sample delay. | ||
| 19395 | */ | ||
| 19396 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) | ||
| 19397 | /*! @} */ | ||
| 19398 | |||
| 19399 | /*! @name PLL1CTRL - PLL1 550m control */ | ||
| 19400 | /*! @{ */ | ||
| 19401 | #define SYSCON_PLL1CTRL_SELR_MASK (0xFU) | ||
| 19402 | #define SYSCON_PLL1CTRL_SELR_SHIFT (0U) | ||
| 19403 | /*! SELR - Bandwidth select R value. | ||
| 19404 | */ | ||
| 19405 | #define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) | ||
| 19406 | #define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) | ||
| 19407 | #define SYSCON_PLL1CTRL_SELI_SHIFT (4U) | ||
| 19408 | /*! SELI - Bandwidth select I value. | ||
| 19409 | */ | ||
| 19410 | #define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) | ||
| 19411 | #define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) | ||
| 19412 | #define SYSCON_PLL1CTRL_SELP_SHIFT (10U) | ||
| 19413 | /*! SELP - Bandwidth select P value. | ||
| 19414 | */ | ||
| 19415 | #define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) | ||
| 19416 | #define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) | ||
| 19417 | #define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) | ||
| 19418 | /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). | ||
| 19419 | * 0b1..PLL input clock is sent directly to the PLL output. | ||
| 19420 | * 0b0..use PLL. | ||
| 19421 | */ | ||
| 19422 | #define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) | ||
| 19423 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) | ||
| 19424 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) | ||
| 19425 | /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. | ||
| 19426 | * 0b1..bypass of the divide-by-2 divider in the post-divider. | ||
| 19427 | * 0b0..use the divide-by-2 divider in the post-divider. | ||
| 19428 | */ | ||
| 19429 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) | ||
| 19430 | #define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) | ||
| 19431 | #define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) | ||
| 19432 | /*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. | ||
| 19433 | */ | ||
| 19434 | #define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) | ||
| 19435 | #define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) | ||
| 19436 | #define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) | ||
| 19437 | /*! BWDIRECT - control of the bandwidth of the PLL. | ||
| 19438 | * 0b1..modify the bandwidth of the PLL directly. | ||
| 19439 | * 0b0..the bandwidth is changed synchronously with the feedback-divider. | ||
| 19440 | */ | ||
| 19441 | #define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) | ||
| 19442 | #define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) | ||
| 19443 | #define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) | ||
| 19444 | /*! BYPASSPREDIV - bypass of the pre-divider. | ||
| 19445 | * 0b1..bypass of the pre-divider. | ||
| 19446 | * 0b0..use the pre-divider. | ||
| 19447 | */ | ||
| 19448 | #define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) | ||
| 19449 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) | ||
| 19450 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) | ||
| 19451 | /*! BYPASSPOSTDIV - bypass of the post-divider. | ||
| 19452 | * 0b1..bypass of the post-divider. | ||
| 19453 | * 0b0..use the post-divider. | ||
| 19454 | */ | ||
| 19455 | #define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) | ||
| 19456 | #define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) | ||
| 19457 | #define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) | ||
| 19458 | /*! CLKEN - enable the output clock. | ||
| 19459 | * 0b1..Enable the output clock. | ||
| 19460 | * 0b0..Disable the output clock. | ||
| 19461 | */ | ||
| 19462 | #define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) | ||
| 19463 | #define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) | ||
| 19464 | #define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) | ||
| 19465 | /*! FRMEN - 1: free running mode. | ||
| 19466 | */ | ||
| 19467 | #define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) | ||
| 19468 | #define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) | ||
| 19469 | #define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) | ||
| 19470 | /*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. | ||
| 19471 | */ | ||
| 19472 | #define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) | ||
| 19473 | #define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) | ||
| 19474 | #define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) | ||
| 19475 | /*! SKEWEN - Skew mode. | ||
| 19476 | * 0b1..skewmode is enable. | ||
| 19477 | * 0b0..skewmode is disable. | ||
| 19478 | */ | ||
| 19479 | #define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) | ||
| 19480 | /*! @} */ | ||
| 19481 | |||
| 19482 | /*! @name PLL1STAT - PLL1 550m status */ | ||
| 19483 | /*! @{ */ | ||
| 19484 | #define SYSCON_PLL1STAT_LOCK_MASK (0x1U) | ||
| 19485 | #define SYSCON_PLL1STAT_LOCK_SHIFT (0U) | ||
| 19486 | /*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. | ||
| 19487 | */ | ||
| 19488 | #define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) | ||
| 19489 | #define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) | ||
| 19490 | #define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) | ||
| 19491 | /*! PREDIVACK - pre-divider ratio change acknowledge. | ||
| 19492 | */ | ||
| 19493 | #define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) | ||
| 19494 | #define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) | ||
| 19495 | #define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) | ||
| 19496 | /*! FEEDDIVACK - feedback divider ratio change acknowledge. | ||
| 19497 | */ | ||
| 19498 | #define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) | ||
| 19499 | #define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) | ||
| 19500 | #define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) | ||
| 19501 | /*! POSTDIVACK - post-divider ratio change acknowledge. | ||
| 19502 | */ | ||
| 19503 | #define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) | ||
| 19504 | #define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) | ||
| 19505 | #define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) | ||
| 19506 | /*! FRMDET - free running detector output (active high). | ||
| 19507 | */ | ||
| 19508 | #define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) | ||
| 19509 | /*! @} */ | ||
| 19510 | |||
| 19511 | /*! @name PLL1NDEC - PLL1 550m N divider */ | ||
| 19512 | /*! @{ */ | ||
| 19513 | #define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) | ||
| 19514 | #define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) | ||
| 19515 | /*! NDIV - pre-divider divider ratio (N-divider). | ||
| 19516 | */ | ||
| 19517 | #define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) | ||
| 19518 | #define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) | ||
| 19519 | #define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) | ||
| 19520 | /*! NREQ - pre-divider ratio change request. | ||
| 19521 | */ | ||
| 19522 | #define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) | ||
| 19523 | /*! @} */ | ||
| 19524 | |||
| 19525 | /*! @name PLL1MDEC - PLL1 550m M divider */ | ||
| 19526 | /*! @{ */ | ||
| 19527 | #define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) | ||
| 19528 | #define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) | ||
| 19529 | /*! MDIV - feedback divider divider ratio (M-divider). | ||
| 19530 | */ | ||
| 19531 | #define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) | ||
| 19532 | #define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) | ||
| 19533 | #define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) | ||
| 19534 | /*! MREQ - feedback ratio change request. | ||
| 19535 | */ | ||
| 19536 | #define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) | ||
| 19537 | /*! @} */ | ||
| 19538 | |||
| 19539 | /*! @name PLL1PDEC - PLL1 550m P divider */ | ||
| 19540 | /*! @{ */ | ||
| 19541 | #define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) | ||
| 19542 | #define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) | ||
| 19543 | /*! PDIV - post-divider divider ratio (P-divider) | ||
| 19544 | */ | ||
| 19545 | #define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) | ||
| 19546 | #define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) | ||
| 19547 | #define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) | ||
| 19548 | /*! PREQ - feedback ratio change request. | ||
| 19549 | */ | ||
| 19550 | #define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) | ||
| 19551 | /*! @} */ | ||
| 19552 | |||
| 19553 | /*! @name PLL0CTRL - PLL0 550m control */ | ||
| 19554 | /*! @{ */ | ||
| 19555 | #define SYSCON_PLL0CTRL_SELR_MASK (0xFU) | ||
| 19556 | #define SYSCON_PLL0CTRL_SELR_SHIFT (0U) | ||
| 19557 | /*! SELR - Bandwidth select R value. | ||
| 19558 | */ | ||
| 19559 | #define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) | ||
| 19560 | #define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) | ||
| 19561 | #define SYSCON_PLL0CTRL_SELI_SHIFT (4U) | ||
| 19562 | /*! SELI - Bandwidth select I value. | ||
| 19563 | */ | ||
| 19564 | #define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) | ||
| 19565 | #define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) | ||
| 19566 | #define SYSCON_PLL0CTRL_SELP_SHIFT (10U) | ||
| 19567 | /*! SELP - Bandwidth select P value. | ||
| 19568 | */ | ||
| 19569 | #define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) | ||
| 19570 | #define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) | ||
| 19571 | #define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) | ||
| 19572 | /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). | ||
| 19573 | * 0b1..Bypass PLL input clock is sent directly to the PLL output. | ||
| 19574 | * 0b0..use PLL. | ||
| 19575 | */ | ||
| 19576 | #define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) | ||
| 19577 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) | ||
| 19578 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) | ||
| 19579 | /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. | ||
| 19580 | * 0b1..bypass of the divide-by-2 divider in the post-divider. | ||
| 19581 | * 0b0..use the divide-by-2 divider in the post-divider. | ||
| 19582 | */ | ||
| 19583 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) | ||
| 19584 | #define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) | ||
| 19585 | #define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) | ||
| 19586 | /*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. | ||
| 19587 | */ | ||
| 19588 | #define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) | ||
| 19589 | #define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) | ||
| 19590 | #define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) | ||
| 19591 | /*! BWDIRECT - Control of the bandwidth of the PLL. | ||
| 19592 | * 0b1..modify the bandwidth of the PLL directly. | ||
| 19593 | * 0b0..the bandwidth is changed synchronously with the feedback-divider. | ||
| 19594 | */ | ||
| 19595 | #define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) | ||
| 19596 | #define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) | ||
| 19597 | #define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) | ||
| 19598 | /*! BYPASSPREDIV - bypass of the pre-divider. | ||
| 19599 | * 0b1..bypass of the pre-divider. | ||
| 19600 | * 0b0..use the pre-divider. | ||
| 19601 | */ | ||
| 19602 | #define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) | ||
| 19603 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) | ||
| 19604 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) | ||
| 19605 | /*! BYPASSPOSTDIV - bypass of the post-divider. | ||
| 19606 | * 0b1..bypass of the post-divider. | ||
| 19607 | * 0b0..use the post-divider. | ||
| 19608 | */ | ||
| 19609 | #define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) | ||
| 19610 | #define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) | ||
| 19611 | #define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) | ||
| 19612 | /*! CLKEN - enable the output clock. | ||
| 19613 | * 0b1..enable the output clock. | ||
| 19614 | * 0b0..disable the output clock. | ||
| 19615 | */ | ||
| 19616 | #define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) | ||
| 19617 | #define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) | ||
| 19618 | #define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) | ||
| 19619 | /*! FRMEN - free running mode. | ||
| 19620 | * 0b1..free running mode is enable. | ||
| 19621 | * 0b0..free running mode is disable. | ||
| 19622 | */ | ||
| 19623 | #define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) | ||
| 19624 | #define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) | ||
| 19625 | #define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) | ||
| 19626 | /*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. | ||
| 19627 | */ | ||
| 19628 | #define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) | ||
| 19629 | #define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) | ||
| 19630 | #define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) | ||
| 19631 | /*! SKEWEN - skew mode. | ||
| 19632 | * 0b1..skew mode is enable. | ||
| 19633 | * 0b0..skew mode is disable. | ||
| 19634 | */ | ||
| 19635 | #define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) | ||
| 19636 | /*! @} */ | ||
| 19637 | |||
| 19638 | /*! @name PLL0STAT - PLL0 550m status */ | ||
| 19639 | /*! @{ */ | ||
| 19640 | #define SYSCON_PLL0STAT_LOCK_MASK (0x1U) | ||
| 19641 | #define SYSCON_PLL0STAT_LOCK_SHIFT (0U) | ||
| 19642 | /*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. | ||
| 19643 | */ | ||
| 19644 | #define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) | ||
| 19645 | #define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) | ||
| 19646 | #define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) | ||
| 19647 | /*! PREDIVACK - pre-divider ratio change acknowledge. | ||
| 19648 | */ | ||
| 19649 | #define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) | ||
| 19650 | #define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) | ||
| 19651 | #define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) | ||
| 19652 | /*! FEEDDIVACK - feedback divider ratio change acknowledge. | ||
| 19653 | */ | ||
| 19654 | #define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) | ||
| 19655 | #define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) | ||
| 19656 | #define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) | ||
| 19657 | /*! POSTDIVACK - post-divider ratio change acknowledge. | ||
| 19658 | */ | ||
| 19659 | #define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) | ||
| 19660 | #define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) | ||
| 19661 | #define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) | ||
| 19662 | /*! FRMDET - free running detector output (active high). | ||
| 19663 | */ | ||
| 19664 | #define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) | ||
| 19665 | /*! @} */ | ||
| 19666 | |||
| 19667 | /*! @name PLL0NDEC - PLL0 550m N divider */ | ||
| 19668 | /*! @{ */ | ||
| 19669 | #define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) | ||
| 19670 | #define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) | ||
| 19671 | /*! NDIV - pre-divider divider ratio (N-divider). | ||
| 19672 | */ | ||
| 19673 | #define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) | ||
| 19674 | #define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) | ||
| 19675 | #define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) | ||
| 19676 | /*! NREQ - pre-divider ratio change request. | ||
| 19677 | */ | ||
| 19678 | #define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) | ||
| 19679 | /*! @} */ | ||
| 19680 | |||
| 19681 | /*! @name PLL0PDEC - PLL0 550m P divider */ | ||
| 19682 | /*! @{ */ | ||
| 19683 | #define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) | ||
| 19684 | #define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) | ||
| 19685 | /*! PDIV - post-divider divider ratio (P-divider) | ||
| 19686 | */ | ||
| 19687 | #define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) | ||
| 19688 | #define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) | ||
| 19689 | #define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) | ||
| 19690 | /*! PREQ - feedback ratio change request. | ||
| 19691 | */ | ||
| 19692 | #define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) | ||
| 19693 | /*! @} */ | ||
| 19694 | |||
| 19695 | /*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ | ||
| 19696 | /*! @{ */ | ||
| 19697 | #define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) | ||
| 19698 | #define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) | ||
| 19699 | /*! MD_LBS - input word of the wrapper bit 31 to 0. | ||
| 19700 | */ | ||
| 19701 | #define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) | ||
| 19702 | /*! @} */ | ||
| 19703 | |||
| 19704 | /*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ | ||
| 19705 | /*! @{ */ | ||
| 19706 | #define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) | ||
| 19707 | #define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) | ||
| 19708 | /*! MD_MBS - input word of the wrapper bit 32. | ||
| 19709 | */ | ||
| 19710 | #define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) | ||
| 19711 | #define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) | ||
| 19712 | #define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) | ||
| 19713 | /*! MD_REQ - md change request. | ||
| 19714 | */ | ||
| 19715 | #define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) | ||
| 19716 | #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) | ||
| 19717 | #define SYSCON_PLL0SSCG1_MF_SHIFT (2U) | ||
| 19718 | /*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. | ||
| 19719 | */ | ||
| 19720 | #define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) | ||
| 19721 | #define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) | ||
| 19722 | #define SYSCON_PLL0SSCG1_MR_SHIFT (5U) | ||
| 19723 | /*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) | ||
| 19724 | * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. | ||
| 19725 | */ | ||
| 19726 | #define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) | ||
| 19727 | #define SYSCON_PLL0SSCG1_MC_MASK (0x300U) | ||
| 19728 | #define SYSCON_PLL0SSCG1_MC_SHIFT (8U) | ||
| 19729 | /*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a | ||
| 19730 | * triangular modulation at the output of the PLL, giving a flat frequency spectrum. | ||
| 19731 | */ | ||
| 19732 | #define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) | ||
| 19733 | #define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) | ||
| 19734 | #define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) | ||
| 19735 | /*! MDIV_EXT - to select an external mdiv value. | ||
| 19736 | */ | ||
| 19737 | #define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) | ||
| 19738 | #define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) | ||
| 19739 | #define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) | ||
| 19740 | /*! MREQ - to select an external mreq value. | ||
| 19741 | */ | ||
| 19742 | #define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) | ||
| 19743 | #define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) | ||
| 19744 | #define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) | ||
| 19745 | /*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way | ||
| 19746 | * (white noise), in order to decrease the probability that the modulated waveform will occur | ||
| 19747 | * with the same phase on a particular point on the screen. | ||
| 19748 | */ | ||
| 19749 | #define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) | ||
| 19750 | #define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) | ||
| 19751 | #define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) | ||
| 19752 | /*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. | ||
| 19753 | */ | ||
| 19754 | #define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) | ||
| 19755 | /*! @} */ | ||
| 19756 | |||
| 19757 | /*! @name CPUCTRL - CPU Control for multiple processors */ | ||
| 19758 | /*! @{ */ | ||
| 19759 | #define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) | ||
| 19760 | #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) | ||
| 19761 | /*! CPU1CLKEN - CPU1 clock enable. | ||
| 19762 | * 0b1..The CPU1 clock is enabled. | ||
| 19763 | * 0b0..The CPU1 clock is not enabled. | ||
| 19764 | */ | ||
| 19765 | #define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) | ||
| 19766 | #define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) | ||
| 19767 | #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) | ||
| 19768 | /*! CPU1RSTEN - CPU1 reset. | ||
| 19769 | * 0b1..The CPU1 is being reset. | ||
| 19770 | * 0b0..The CPU1 is not being reset. | ||
| 19771 | */ | ||
| 19772 | #define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) | ||
| 19773 | /*! @} */ | ||
| 19774 | |||
| 19775 | /*! @name CPBOOT - Coprocessor Boot Address */ | ||
| 19776 | /*! @{ */ | ||
| 19777 | #define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) | ||
| 19778 | #define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) | ||
| 19779 | /*! CPBOOT - Coprocessor Boot Address for CPU1. | ||
| 19780 | */ | ||
| 19781 | #define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) | ||
| 19782 | /*! @} */ | ||
| 19783 | |||
| 19784 | /*! @name CPSTAT - CPU Status */ | ||
| 19785 | /*! @{ */ | ||
| 19786 | #define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) | ||
| 19787 | #define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) | ||
| 19788 | /*! CPU0SLEEPING - The CPU0 sleeping state. | ||
| 19789 | * 0b1..the CPU is sleeping. | ||
| 19790 | * 0b0..the CPU is not sleeping. | ||
| 19791 | */ | ||
| 19792 | #define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) | ||
| 19793 | #define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) | ||
| 19794 | #define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) | ||
| 19795 | /*! CPU1SLEEPING - The CPU1 sleeping state. | ||
| 19796 | * 0b1..the CPU is sleeping. | ||
| 19797 | * 0b0..the CPU is not sleeping. | ||
| 19798 | */ | ||
| 19799 | #define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) | ||
| 19800 | #define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) | ||
| 19801 | #define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) | ||
| 19802 | /*! CPU0LOCKUP - The CPU0 lockup state. | ||
| 19803 | * 0b1..the CPU is in lockup. | ||
| 19804 | * 0b0..the CPU is not in lockup. | ||
| 19805 | */ | ||
| 19806 | #define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) | ||
| 19807 | #define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) | ||
| 19808 | #define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) | ||
| 19809 | /*! CPU1LOCKUP - The CPU1 lockup state. | ||
| 19810 | * 0b1..the CPU is in lockup. | ||
| 19811 | * 0b0..the CPU is not in lockup. | ||
| 19812 | */ | ||
| 19813 | #define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) | ||
| 19814 | /*! @} */ | ||
| 19815 | |||
| 19816 | /*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ | ||
| 19817 | /*! @{ */ | ||
| 19818 | #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) | ||
| 19819 | #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) | ||
| 19820 | /*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. | ||
| 19821 | * 0b1..The clock is enabled. | ||
| 19822 | * 0b0..The clock is not enabled. | ||
| 19823 | */ | ||
| 19824 | #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) | ||
| 19825 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) | ||
| 19826 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) | ||
| 19827 | /*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. | ||
| 19828 | * 0b1..The clock is enabled. | ||
| 19829 | * 0b0..The clock is not enabled. | ||
| 19830 | */ | ||
| 19831 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) | ||
| 19832 | #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) | ||
| 19833 | #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) | ||
| 19834 | /*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. | ||
| 19835 | * 0b1..The clock is enabled. | ||
| 19836 | * 0b0..The clock is not enabled. | ||
| 19837 | */ | ||
| 19838 | #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) | ||
| 19839 | #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) | ||
| 19840 | #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) | ||
| 19841 | /*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. | ||
| 19842 | * 0b1..The clock is enabled. | ||
| 19843 | * 0b0..The clock is not enabled. | ||
| 19844 | */ | ||
| 19845 | #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) | ||
| 19846 | #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) | ||
| 19847 | #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) | ||
| 19848 | /*! CLKIN_ENA - Enable clock_in clock for clock module. | ||
| 19849 | * 0b1..The clock is enabled. | ||
| 19850 | * 0b0..The clock is not enabled. | ||
| 19851 | */ | ||
| 19852 | #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) | ||
| 19853 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) | ||
| 19854 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) | ||
| 19855 | /*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. | ||
| 19856 | * 0b1..The clock is enabled. | ||
| 19857 | * 0b0..The clock is not enabled. | ||
| 19858 | */ | ||
| 19859 | #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) | ||
| 19860 | #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) | ||
| 19861 | #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) | ||
| 19862 | /*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. | ||
| 19863 | * 0b1..The clock is enabled. | ||
| 19864 | * 0b0..The clock is not enabled. | ||
| 19865 | */ | ||
| 19866 | #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) | ||
| 19867 | #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) | ||
| 19868 | #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) | ||
| 19869 | /*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. | ||
| 19870 | * 0b1..The clock is enabled. | ||
| 19871 | * 0b0..The clock is not enabled. | ||
| 19872 | */ | ||
| 19873 | #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) | ||
| 19874 | #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) | ||
| 19875 | #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) | ||
| 19876 | /*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. | ||
| 19877 | * 0b1..The clock is enabled. | ||
| 19878 | * 0b0..The clock is not enabled. | ||
| 19879 | */ | ||
| 19880 | #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) | ||
| 19881 | /*! @} */ | ||
| 19882 | |||
| 19883 | /*! @name COMP_INT_CTRL - Comparator Interrupt control */ | ||
| 19884 | /*! @{ */ | ||
| 19885 | #define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) | ||
| 19886 | #define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) | ||
| 19887 | /*! INT_ENABLE - Analog Comparator interrupt enable control:. | ||
| 19888 | * 0b1..interrupt enable. | ||
| 19889 | * 0b0..interrupt disable. | ||
| 19890 | */ | ||
| 19891 | #define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) | ||
| 19892 | #define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) | ||
| 19893 | #define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) | ||
| 19894 | /*! INT_CLEAR - Analog Comparator interrupt clear. | ||
| 19895 | * 0b0..No effect. | ||
| 19896 | * 0b1..Clear the interrupt. Self-cleared bit. | ||
| 19897 | */ | ||
| 19898 | #define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) | ||
| 19899 | #define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) | ||
| 19900 | #define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) | ||
| 19901 | /*! INT_CTRL - Comparator interrupt type selector:. | ||
| 19902 | * 0b000..The analog comparator interrupt edge sensitive is disabled. | ||
| 19903 | * 0b010..analog comparator interrupt is rising edge sensitive. | ||
| 19904 | * 0b100..analog comparator interrupt is falling edge sensitive. | ||
| 19905 | * 0b110..analog comparator interrupt is rising and falling edge sensitive. | ||
| 19906 | * 0b001..The analog comparator interrupt level sensitive is disabled. | ||
| 19907 | * 0b011..Analog Comparator interrupt is high level sensitive. | ||
| 19908 | * 0b101..Analog Comparator interrupt is low level sensitive. | ||
| 19909 | * 0b111..The analog comparator interrupt level sensitive is disabled. | ||
| 19910 | */ | ||
| 19911 | #define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) | ||
| 19912 | #define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) | ||
| 19913 | #define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) | ||
| 19914 | /*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. | ||
| 19915 | * 0b0..Select Analog Comparator filtered output as input for interrupt detection. | ||
| 19916 | * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when | ||
| 19917 | * Analog comparator is used as wake up source in Power down mode. | ||
| 19918 | */ | ||
| 19919 | #define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) | ||
| 19920 | /*! @} */ | ||
| 19921 | |||
| 19922 | /*! @name COMP_INT_STATUS - Comparator Interrupt status */ | ||
| 19923 | /*! @{ */ | ||
| 19924 | #define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) | ||
| 19925 | #define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) | ||
| 19926 | /*! STATUS - Interrupt status BEFORE Interrupt Enable. | ||
| 19927 | * 0b0..no interrupt pending. | ||
| 19928 | * 0b1..interrupt pending. | ||
| 19929 | */ | ||
| 19930 | #define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) | ||
| 19931 | #define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) | ||
| 19932 | #define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) | ||
| 19933 | /*! INT_STATUS - Interrupt status AFTER Interrupt Enable. | ||
| 19934 | * 0b0..no interrupt pending. | ||
| 19935 | * 0b1..interrupt pending. | ||
| 19936 | */ | ||
| 19937 | #define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) | ||
| 19938 | #define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) | ||
| 19939 | #define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) | ||
| 19940 | /*! VAL - comparator analog output. | ||
| 19941 | * 0b1..P+ is greater than P-. | ||
| 19942 | * 0b0..P+ is smaller than P-. | ||
| 19943 | */ | ||
| 19944 | #define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) | ||
| 19945 | /*! @} */ | ||
| 19946 | |||
| 19947 | /*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ | ||
| 19948 | /*! @{ */ | ||
| 19949 | #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) | ||
| 19950 | #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) | ||
| 19951 | /*! ROM - Control automatic clock gating of ROM controller. | ||
| 19952 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19953 | * 0b0..Automatic clock gating is not overridden. | ||
| 19954 | */ | ||
| 19955 | #define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) | ||
| 19956 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) | ||
| 19957 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) | ||
| 19958 | /*! RAMX_CTRL - Control automatic clock gating of RAMX controller. | ||
| 19959 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19960 | * 0b0..Automatic clock gating is not overridden. | ||
| 19961 | */ | ||
| 19962 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) | ||
| 19963 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) | ||
| 19964 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) | ||
| 19965 | /*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. | ||
| 19966 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19967 | * 0b0..Automatic clock gating is not overridden. | ||
| 19968 | */ | ||
| 19969 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) | ||
| 19970 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) | ||
| 19971 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) | ||
| 19972 | /*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. | ||
| 19973 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19974 | * 0b0..Automatic clock gating is not overridden. | ||
| 19975 | */ | ||
| 19976 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) | ||
| 19977 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) | ||
| 19978 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) | ||
| 19979 | /*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. | ||
| 19980 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19981 | * 0b0..Automatic clock gating is not overridden. | ||
| 19982 | */ | ||
| 19983 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) | ||
| 19984 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) | ||
| 19985 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) | ||
| 19986 | /*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. | ||
| 19987 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19988 | * 0b0..Automatic clock gating is not overridden. | ||
| 19989 | */ | ||
| 19990 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) | ||
| 19991 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) | ||
| 19992 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) | ||
| 19993 | /*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. | ||
| 19994 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 19995 | * 0b0..Automatic clock gating is not overridden. | ||
| 19996 | */ | ||
| 19997 | #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) | ||
| 19998 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) | ||
| 19999 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) | ||
| 20000 | /*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. | ||
| 20001 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20002 | * 0b0..Automatic clock gating is not overridden. | ||
| 20003 | */ | ||
| 20004 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) | ||
| 20005 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) | ||
| 20006 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) | ||
| 20007 | /*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. | ||
| 20008 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20009 | * 0b0..Automatic clock gating is not overridden. | ||
| 20010 | */ | ||
| 20011 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) | ||
| 20012 | #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) | ||
| 20013 | #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) | ||
| 20014 | /*! CRCGEN - Control automatic clock gating of CRCGEN controller. | ||
| 20015 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20016 | * 0b0..Automatic clock gating is not overridden. | ||
| 20017 | */ | ||
| 20018 | #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) | ||
| 20019 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) | ||
| 20020 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) | ||
| 20021 | /*! SDMA0 - Control automatic clock gating of DMA0 controller. | ||
| 20022 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20023 | * 0b0..Automatic clock gating is not overridden. | ||
| 20024 | */ | ||
| 20025 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) | ||
| 20026 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) | ||
| 20027 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) | ||
| 20028 | /*! SDMA1 - Control automatic clock gating of DMA1 controller. | ||
| 20029 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20030 | * 0b0..Automatic clock gating is not overridden. | ||
| 20031 | */ | ||
| 20032 | #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) | ||
| 20033 | #define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) | ||
| 20034 | #define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) | ||
| 20035 | /*! USB0 - Control automatic clock gating of USB controller. | ||
| 20036 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20037 | * 0b0..Automatic clock gating is not overridden. | ||
| 20038 | */ | ||
| 20039 | #define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) | ||
| 20040 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) | ||
| 20041 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) | ||
| 20042 | /*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. | ||
| 20043 | * 0b1..Automatic clock gating is overridden (Clock gating is disabled). | ||
| 20044 | * 0b0..Automatic clock gating is not overridden. | ||
| 20045 | */ | ||
| 20046 | #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) | ||
| 20047 | #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) | ||
| 20048 | #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) | ||
| 20049 | /*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. | ||
| 20050 | * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated | ||
| 20051 | * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated | ||
| 20052 | */ | ||
| 20053 | #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) | ||
| 20054 | /*! @} */ | ||
| 20055 | |||
| 20056 | /*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ | ||
| 20057 | /*! @{ */ | ||
| 20058 | #define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) | ||
| 20059 | #define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) | ||
| 20060 | /*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. | ||
| 20061 | * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. | ||
| 20062 | * 0b0..use the first stage of synchonization inside GPIO_INT module. | ||
| 20063 | */ | ||
| 20064 | #define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) | ||
| 20065 | /*! @} */ | ||
| 20066 | |||
| 20067 | /*! @name DEBUG_LOCK_EN - Control write access to security registers. */ | ||
| 20068 | /*! @{ */ | ||
| 20069 | #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) | ||
| 20070 | #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) | ||
| 20071 | /*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, | ||
| 20072 | * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. | ||
| 20073 | * 0b1010..1010: Enable write access to all 6 registers. | ||
| 20074 | * 0b0000..Any other value than b1010: disable write access to all 6 registers. | ||
| 20075 | */ | ||
| 20076 | #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) | ||
| 20077 | /*! @} */ | ||
| 20078 | |||
| 20079 | /*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ | ||
| 20080 | /*! @{ */ | ||
| 20081 | #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) | ||
| 20082 | #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) | ||
| 20083 | /*! CPU0_DBGEN - CPU0 Invasive debug control:. | ||
| 20084 | * 0b10..10: Invasive debug is enabled. | ||
| 20085 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20086 | */ | ||
| 20087 | #define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) | ||
| 20088 | #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) | ||
| 20089 | #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) | ||
| 20090 | /*! CPU0_NIDEN - CPU0 Non Invasive debug control:. | ||
| 20091 | * 0b10..10: Invasive debug is enabled. | ||
| 20092 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20093 | */ | ||
| 20094 | #define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) | ||
| 20095 | #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) | ||
| 20096 | #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) | ||
| 20097 | /*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. | ||
| 20098 | * 0b10..10: Invasive debug is enabled. | ||
| 20099 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20100 | */ | ||
| 20101 | #define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) | ||
| 20102 | #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) | ||
| 20103 | #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) | ||
| 20104 | /*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. | ||
| 20105 | * 0b10..10: Invasive debug is enabled. | ||
| 20106 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20107 | */ | ||
| 20108 | #define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) | ||
| 20109 | #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) | ||
| 20110 | #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) | ||
| 20111 | /*! CPU1_DBGEN - CPU1 Invasive debug control:. | ||
| 20112 | * 0b10..10: Invasive debug is enabled. | ||
| 20113 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20114 | */ | ||
| 20115 | #define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) | ||
| 20116 | #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) | ||
| 20117 | #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) | ||
| 20118 | /*! CPU1_NIDEN - CPU1 Non Invasive debug control:. | ||
| 20119 | * 0b10..10: Invasive debug is enabled. | ||
| 20120 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20121 | */ | ||
| 20122 | #define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) | ||
| 20123 | /*! @} */ | ||
| 20124 | |||
| 20125 | /*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ | ||
| 20126 | /*! @{ */ | ||
| 20127 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) | ||
| 20128 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) | ||
| 20129 | /*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. | ||
| 20130 | * 0b10..10: Invasive debug is enabled. | ||
| 20131 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20132 | */ | ||
| 20133 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) | ||
| 20134 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) | ||
| 20135 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) | ||
| 20136 | /*! CPU0_NIDEN - CPU0 Non Invasive debug control:. | ||
| 20137 | * 0b10..10: Invasive debug is enabled. | ||
| 20138 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20139 | */ | ||
| 20140 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) | ||
| 20141 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) | ||
| 20142 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) | ||
| 20143 | /*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. | ||
| 20144 | * 0b10..10: Invasive debug is enabled. | ||
| 20145 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20146 | */ | ||
| 20147 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) | ||
| 20148 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) | ||
| 20149 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) | ||
| 20150 | /*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. | ||
| 20151 | * 0b10..10: Invasive debug is enabled. | ||
| 20152 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20153 | */ | ||
| 20154 | #define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) | ||
| 20155 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) | ||
| 20156 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) | ||
| 20157 | /*! CPU1_DBGEN - CPU1 Invasive debug control:. | ||
| 20158 | * 0b10..10: Invasive debug is enabled. | ||
| 20159 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20160 | */ | ||
| 20161 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) | ||
| 20162 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) | ||
| 20163 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) | ||
| 20164 | /*! CPU1_NIDEN - CPU1 Non Invasive debug control:. | ||
| 20165 | * 0b10..10: Invasive debug is enabled. | ||
| 20166 | * 0b01..Any other value than b10: invasive debug is disable. | ||
| 20167 | */ | ||
| 20168 | #define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) | ||
| 20169 | /*! @} */ | ||
| 20170 | |||
| 20171 | /*! @name KEY_BLOCK - block quiddikey/PUF all index. */ | ||
| 20172 | /*! @{ */ | ||
| 20173 | #define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) | ||
| 20174 | #define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) | ||
| 20175 | /*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. | ||
| 20176 | */ | ||
| 20177 | #define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) | ||
| 20178 | /*! @} */ | ||
| 20179 | |||
| 20180 | /*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ | ||
| 20181 | /*! @{ */ | ||
| 20182 | #define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) | ||
| 20183 | #define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) | ||
| 20184 | /*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential | ||
| 20185 | * Beacon and Authentication Beacon) to application code. | ||
| 20186 | */ | ||
| 20187 | #define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) | ||
| 20188 | /*! @} */ | ||
| 20189 | |||
| 20190 | /*! @name DEVICE_ID0 - Device ID */ | ||
| 20191 | /*! @{ */ | ||
| 20192 | #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) | ||
| 20193 | #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) | ||
| 20194 | /*! ROM_REV_MINOR - ROM revision. | ||
| 20195 | */ | ||
| 20196 | #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) | ||
| 20197 | /*! @} */ | ||
| 20198 | |||
| 20199 | /*! @name DIEID - Chip revision ID and Number */ | ||
| 20200 | /*! @{ */ | ||
| 20201 | #define SYSCON_DIEID_REV_ID_MASK (0xFU) | ||
| 20202 | #define SYSCON_DIEID_REV_ID_SHIFT (0U) | ||
| 20203 | /*! REV_ID - Chip Metal Revision ID. | ||
| 20204 | */ | ||
| 20205 | #define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) | ||
| 20206 | #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) | ||
| 20207 | #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) | ||
| 20208 | /*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. | ||
| 20209 | */ | ||
| 20210 | #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) | ||
| 20211 | /*! @} */ | ||
| 20212 | |||
| 20213 | |||
| 20214 | /*! | ||
| 20215 | * @} | ||
| 20216 | */ /* end of group SYSCON_Register_Masks */ | ||
| 20217 | |||
| 20218 | |||
| 20219 | /* SYSCON - Peripheral instance base addresses */ | ||
| 20220 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 20221 | /** Peripheral SYSCON base address */ | ||
| 20222 | #define SYSCON_BASE (0x50000000u) | ||
| 20223 | /** Peripheral SYSCON base address */ | ||
| 20224 | #define SYSCON_BASE_NS (0x40000000u) | ||
| 20225 | /** Peripheral SYSCON base pointer */ | ||
| 20226 | #define SYSCON ((SYSCON_Type *)SYSCON_BASE) | ||
| 20227 | /** Peripheral SYSCON base pointer */ | ||
| 20228 | #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) | ||
| 20229 | /** Array initializer of SYSCON peripheral base addresses */ | ||
| 20230 | #define SYSCON_BASE_ADDRS { SYSCON_BASE } | ||
| 20231 | /** Array initializer of SYSCON peripheral base pointers */ | ||
| 20232 | #define SYSCON_BASE_PTRS { SYSCON } | ||
| 20233 | /** Array initializer of SYSCON peripheral base addresses */ | ||
| 20234 | #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } | ||
| 20235 | /** Array initializer of SYSCON peripheral base pointers */ | ||
| 20236 | #define SYSCON_BASE_PTRS_NS { SYSCON_NS } | ||
| 20237 | #else | ||
| 20238 | /** Peripheral SYSCON base address */ | ||
| 20239 | #define SYSCON_BASE (0x40000000u) | ||
| 20240 | /** Peripheral SYSCON base pointer */ | ||
| 20241 | #define SYSCON ((SYSCON_Type *)SYSCON_BASE) | ||
| 20242 | /** Array initializer of SYSCON peripheral base addresses */ | ||
| 20243 | #define SYSCON_BASE_ADDRS { SYSCON_BASE } | ||
| 20244 | /** Array initializer of SYSCON peripheral base pointers */ | ||
| 20245 | #define SYSCON_BASE_PTRS { SYSCON } | ||
| 20246 | #endif | ||
| 20247 | |||
| 20248 | /*! | ||
| 20249 | * @} | ||
| 20250 | */ /* end of group SYSCON_Peripheral_Access_Layer */ | ||
| 20251 | |||
| 20252 | |||
| 20253 | /* ---------------------------------------------------------------------------- | ||
| 20254 | -- SYSCTL Peripheral Access Layer | ||
| 20255 | ---------------------------------------------------------------------------- */ | ||
| 20256 | |||
| 20257 | /*! | ||
| 20258 | * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer | ||
| 20259 | * @{ | ||
| 20260 | */ | ||
| 20261 | |||
| 20262 | /** SYSCTL - Register Layout Typedef */ | ||
| 20263 | typedef struct { | ||
| 20264 | __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ | ||
| 20265 | uint8_t RESERVED_0[60]; | ||
| 20266 | __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ | ||
| 20267 | uint8_t RESERVED_1[32]; | ||
| 20268 | __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ | ||
| 20269 | uint8_t RESERVED_2[120]; | ||
| 20270 | __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ | ||
| 20271 | } SYSCTL_Type; | ||
| 20272 | |||
| 20273 | /* ---------------------------------------------------------------------------- | ||
| 20274 | -- SYSCTL Register Masks | ||
| 20275 | ---------------------------------------------------------------------------- */ | ||
| 20276 | |||
| 20277 | /*! | ||
| 20278 | * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks | ||
| 20279 | * @{ | ||
| 20280 | */ | ||
| 20281 | |||
| 20282 | /*! @name UPDATELCKOUT - update lock out control */ | ||
| 20283 | /*! @{ */ | ||
| 20284 | #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) | ||
| 20285 | #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) | ||
| 20286 | /*! UPDATELCKOUT - All Registers | ||
| 20287 | * 0b0..Normal Mode. Can be written to. | ||
| 20288 | * 0b1..Protected Mode. Cannot be written to. | ||
| 20289 | */ | ||
| 20290 | #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) | ||
| 20291 | /*! @} */ | ||
| 20292 | |||
| 20293 | /*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ | ||
| 20294 | /*! @{ */ | ||
| 20295 | #define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) | ||
| 20296 | #define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) | ||
| 20297 | /*! SCKINSEL - Selects the source for SCK going into this Flexcomm. | ||
| 20298 | * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. | ||
| 20299 | * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). | ||
| 20300 | * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). | ||
| 20301 | * 0b11..Reserved. | ||
| 20302 | */ | ||
| 20303 | #define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) | ||
| 20304 | #define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) | ||
| 20305 | #define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) | ||
| 20306 | /*! WSINSEL - Selects the source for WS going into this Flexcomm. | ||
| 20307 | * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. | ||
| 20308 | * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). | ||
| 20309 | * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). | ||
| 20310 | * 0b11..Reserved. | ||
| 20311 | */ | ||
| 20312 | #define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) | ||
| 20313 | #define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) | ||
| 20314 | #define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) | ||
| 20315 | /*! DATAINSEL - Selects the source for DATA input to this Flexcomm. | ||
| 20316 | * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. | ||
| 20317 | * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). | ||
| 20318 | * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). | ||
| 20319 | * 0b11..Reserved. | ||
| 20320 | */ | ||
| 20321 | #define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) | ||
| 20322 | #define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) | ||
| 20323 | #define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) | ||
| 20324 | /*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. | ||
| 20325 | * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. | ||
| 20326 | * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). | ||
| 20327 | * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). | ||
| 20328 | * 0b11..Reserved. | ||
| 20329 | */ | ||
| 20330 | #define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) | ||
| 20331 | /*! @} */ | ||
| 20332 | |||
| 20333 | /* The count of SYSCTL_FCCTRLSEL */ | ||
| 20334 | #define SYSCTL_FCCTRLSEL_COUNT (8U) | ||
| 20335 | |||
| 20336 | /*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ | ||
| 20337 | /*! @{ */ | ||
| 20338 | #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) | ||
| 20339 | #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) | ||
| 20340 | /*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. | ||
| 20341 | * 0b000..SCK for this shared signal set comes from Flexcomm 0. | ||
| 20342 | * 0b001..SCK for this shared signal set comes from Flexcomm 1. | ||
| 20343 | * 0b010..SCK for this shared signal set comes from Flexcomm 2. | ||
| 20344 | * 0b011..SCK for this shared signal set comes from Flexcomm 3. | ||
| 20345 | * 0b100..SCK for this shared signal set comes from Flexcomm 4. | ||
| 20346 | * 0b101..SCK for this shared signal set comes from Flexcomm 5. | ||
| 20347 | * 0b110..SCK for this shared signal set comes from Flexcomm 6. | ||
| 20348 | * 0b111..SCK for this shared signal set comes from Flexcomm 7. | ||
| 20349 | */ | ||
| 20350 | #define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) | ||
| 20351 | #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) | ||
| 20352 | #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) | ||
| 20353 | /*! SHAREDWSSEL - Selects the source for WS of this shared signal set. | ||
| 20354 | * 0b000..WS for this shared signal set comes from Flexcomm 0. | ||
| 20355 | * 0b001..WS for this shared signal set comes from Flexcomm 1. | ||
| 20356 | * 0b010..WS for this shared signal set comes from Flexcomm 2. | ||
| 20357 | * 0b011..WS for this shared signal set comes from Flexcomm 3. | ||
| 20358 | * 0b100..WS for this shared signal set comes from Flexcomm 4. | ||
| 20359 | * 0b101..WS for this shared signal set comes from Flexcomm 5. | ||
| 20360 | * 0b110..WS for this shared signal set comes from Flexcomm 6. | ||
| 20361 | * 0b111..WS for this shared signal set comes from Flexcomm 7. | ||
| 20362 | */ | ||
| 20363 | #define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) | ||
| 20364 | #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) | ||
| 20365 | #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) | ||
| 20366 | /*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. | ||
| 20367 | * 0b000..DATA input for this shared signal set comes from Flexcomm 0. | ||
| 20368 | * 0b001..DATA input for this shared signal set comes from Flexcomm 1. | ||
| 20369 | * 0b010..DATA input for this shared signal set comes from Flexcomm 2. | ||
| 20370 | * 0b011..DATA input for this shared signal set comes from Flexcomm 3. | ||
| 20371 | * 0b100..DATA input for this shared signal set comes from Flexcomm 4. | ||
| 20372 | * 0b101..DATA input for this shared signal set comes from Flexcomm 5. | ||
| 20373 | * 0b110..DATA input for this shared signal set comes from Flexcomm 6. | ||
| 20374 | * 0b111..DATA input for this shared signal set comes from Flexcomm 7. | ||
| 20375 | */ | ||
| 20376 | #define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) | ||
| 20377 | #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) | ||
| 20378 | #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) | ||
| 20379 | /*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. | ||
| 20380 | * 0b0..Data output from FC0 does not contribute to this shared set. | ||
| 20381 | * 0b1..Data output from FC0 does contribute to this shared set. | ||
| 20382 | */ | ||
| 20383 | #define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) | ||
| 20384 | #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) | ||
| 20385 | #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) | ||
| 20386 | /*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. | ||
| 20387 | * 0b0..Data output from FC1 does not contribute to this shared set. | ||
| 20388 | * 0b1..Data output from FC1 does contribute to this shared set. | ||
| 20389 | */ | ||
| 20390 | #define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) | ||
| 20391 | #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) | ||
| 20392 | #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) | ||
| 20393 | /*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. | ||
| 20394 | * 0b0..Data output from FC2 does not contribute to this shared set. | ||
| 20395 | * 0b1..Data output from FC2 does contribute to this shared set. | ||
| 20396 | */ | ||
| 20397 | #define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) | ||
| 20398 | #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) | ||
| 20399 | #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) | ||
| 20400 | /*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. | ||
| 20401 | * 0b0..Data output from FC4 does not contribute to this shared set. | ||
| 20402 | * 0b1..Data output from FC4 does contribute to this shared set. | ||
| 20403 | */ | ||
| 20404 | #define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) | ||
| 20405 | #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) | ||
| 20406 | #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) | ||
| 20407 | /*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. | ||
| 20408 | * 0b0..Data output from FC5 does not contribute to this shared set. | ||
| 20409 | * 0b1..Data output from FC5 does contribute to this shared set. | ||
| 20410 | */ | ||
| 20411 | #define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) | ||
| 20412 | #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) | ||
| 20413 | #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) | ||
| 20414 | /*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. | ||
| 20415 | * 0b0..Data output from FC6 does not contribute to this shared set. | ||
| 20416 | * 0b1..Data output from FC6 does contribute to this shared set. | ||
| 20417 | */ | ||
| 20418 | #define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) | ||
| 20419 | #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) | ||
| 20420 | #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) | ||
| 20421 | /*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. | ||
| 20422 | * 0b0..Data output from FC7 does not contribute to this shared set. | ||
| 20423 | * 0b1..Data output from FC7 does contribute to this shared set. | ||
| 20424 | */ | ||
| 20425 | #define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) | ||
| 20426 | /*! @} */ | ||
| 20427 | |||
| 20428 | /* The count of SYSCTL_SHAREDCTRLSET */ | ||
| 20429 | #define SYSCTL_SHAREDCTRLSET_COUNT (2U) | ||
| 20430 | |||
| 20431 | /*! @name USB_HS_STATUS - Status register for USB HS */ | ||
| 20432 | /*! @{ */ | ||
| 20433 | #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) | ||
| 20434 | #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) | ||
| 20435 | /*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. | ||
| 20436 | * 0b0..3v3 supply is good. | ||
| 20437 | * 0b1..3v3 supply is too low. | ||
| 20438 | */ | ||
| 20439 | #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) | ||
| 20440 | /*! @} */ | ||
| 20441 | |||
| 20442 | |||
| 20443 | /*! | ||
| 20444 | * @} | ||
| 20445 | */ /* end of group SYSCTL_Register_Masks */ | ||
| 20446 | |||
| 20447 | |||
| 20448 | /* SYSCTL - Peripheral instance base addresses */ | ||
| 20449 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 20450 | /** Peripheral SYSCTL base address */ | ||
| 20451 | #define SYSCTL_BASE (0x50023000u) | ||
| 20452 | /** Peripheral SYSCTL base address */ | ||
| 20453 | #define SYSCTL_BASE_NS (0x40023000u) | ||
| 20454 | /** Peripheral SYSCTL base pointer */ | ||
| 20455 | #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) | ||
| 20456 | /** Peripheral SYSCTL base pointer */ | ||
| 20457 | #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) | ||
| 20458 | /** Array initializer of SYSCTL peripheral base addresses */ | ||
| 20459 | #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } | ||
| 20460 | /** Array initializer of SYSCTL peripheral base pointers */ | ||
| 20461 | #define SYSCTL_BASE_PTRS { SYSCTL } | ||
| 20462 | /** Array initializer of SYSCTL peripheral base addresses */ | ||
| 20463 | #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } | ||
| 20464 | /** Array initializer of SYSCTL peripheral base pointers */ | ||
| 20465 | #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } | ||
| 20466 | #else | ||
| 20467 | /** Peripheral SYSCTL base address */ | ||
| 20468 | #define SYSCTL_BASE (0x40023000u) | ||
| 20469 | /** Peripheral SYSCTL base pointer */ | ||
| 20470 | #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) | ||
| 20471 | /** Array initializer of SYSCTL peripheral base addresses */ | ||
| 20472 | #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } | ||
| 20473 | /** Array initializer of SYSCTL peripheral base pointers */ | ||
| 20474 | #define SYSCTL_BASE_PTRS { SYSCTL } | ||
| 20475 | #endif | ||
| 20476 | |||
| 20477 | /*! | ||
| 20478 | * @} | ||
| 20479 | */ /* end of group SYSCTL_Peripheral_Access_Layer */ | ||
| 20480 | |||
| 20481 | |||
| 20482 | /* ---------------------------------------------------------------------------- | ||
| 20483 | -- USART Peripheral Access Layer | ||
| 20484 | ---------------------------------------------------------------------------- */ | ||
| 20485 | |||
| 20486 | /*! | ||
| 20487 | * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer | ||
| 20488 | * @{ | ||
| 20489 | */ | ||
| 20490 | |||
| 20491 | /** USART - Register Layout Typedef */ | ||
| 20492 | typedef struct { | ||
| 20493 | __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ | ||
| 20494 | __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ | ||
| 20495 | __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ | ||
| 20496 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ | ||
| 20497 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ | ||
| 20498 | uint8_t RESERVED_0[12]; | ||
| 20499 | __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ | ||
| 20500 | __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ | ||
| 20501 | __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ | ||
| 20502 | __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ | ||
| 20503 | uint8_t RESERVED_1[3536]; | ||
| 20504 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ | ||
| 20505 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ | ||
| 20506 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ | ||
| 20507 | uint8_t RESERVED_2[4]; | ||
| 20508 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ | ||
| 20509 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ | ||
| 20510 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ | ||
| 20511 | uint8_t RESERVED_3[4]; | ||
| 20512 | __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ | ||
| 20513 | uint8_t RESERVED_4[12]; | ||
| 20514 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ | ||
| 20515 | uint8_t RESERVED_5[12]; | ||
| 20516 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ | ||
| 20517 | uint8_t RESERVED_6[440]; | ||
| 20518 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ | ||
| 20519 | } USART_Type; | ||
| 20520 | |||
| 20521 | /* ---------------------------------------------------------------------------- | ||
| 20522 | -- USART Register Masks | ||
| 20523 | ---------------------------------------------------------------------------- */ | ||
| 20524 | |||
| 20525 | /*! | ||
| 20526 | * @addtogroup USART_Register_Masks USART Register Masks | ||
| 20527 | * @{ | ||
| 20528 | */ | ||
| 20529 | |||
| 20530 | /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ | ||
| 20531 | /*! @{ */ | ||
| 20532 | #define USART_CFG_ENABLE_MASK (0x1U) | ||
| 20533 | #define USART_CFG_ENABLE_SHIFT (0U) | ||
| 20534 | /*! ENABLE - USART Enable. | ||
| 20535 | * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, | ||
| 20536 | * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control | ||
| 20537 | * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the | ||
| 20538 | * transmitter has been reset and is therefore available. | ||
| 20539 | * 0b1..Enabled. The USART is enabled for operation. | ||
| 20540 | */ | ||
| 20541 | #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) | ||
| 20542 | #define USART_CFG_DATALEN_MASK (0xCU) | ||
| 20543 | #define USART_CFG_DATALEN_SHIFT (2U) | ||
| 20544 | /*! DATALEN - Selects the data size for the USART. | ||
| 20545 | * 0b00..7 bit Data length. | ||
| 20546 | * 0b01..8 bit Data length. | ||
| 20547 | * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. | ||
| 20548 | * 0b11..Reserved. | ||
| 20549 | */ | ||
| 20550 | #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) | ||
| 20551 | #define USART_CFG_PARITYSEL_MASK (0x30U) | ||
| 20552 | #define USART_CFG_PARITYSEL_SHIFT (4U) | ||
| 20553 | /*! PARITYSEL - Selects what type of parity is used by the USART. | ||
| 20554 | * 0b00..No parity. | ||
| 20555 | * 0b01..Reserved. | ||
| 20556 | * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, | ||
| 20557 | * and the number of 1s in a received character is expected to be even. | ||
| 20558 | * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, | ||
| 20559 | * and the number of 1s in a received character is expected to be odd. | ||
| 20560 | */ | ||
| 20561 | #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) | ||
| 20562 | #define USART_CFG_STOPLEN_MASK (0x40U) | ||
| 20563 | #define USART_CFG_STOPLEN_SHIFT (6U) | ||
| 20564 | /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. | ||
| 20565 | * 0b0..1 stop bit. | ||
| 20566 | * 0b1..2 stop bits. This setting should only be used for asynchronous communication. | ||
| 20567 | */ | ||
| 20568 | #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) | ||
| 20569 | #define USART_CFG_MODE32K_MASK (0x80U) | ||
| 20570 | #define USART_CFG_MODE32K_SHIFT (7U) | ||
| 20571 | /*! MODE32K - Selects standard or 32 kHz clocking mode. | ||
| 20572 | * 0b0..Disabled. USART uses standard clocking. | ||
| 20573 | * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. | ||
| 20574 | */ | ||
| 20575 | #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) | ||
| 20576 | #define USART_CFG_LINMODE_MASK (0x100U) | ||
| 20577 | #define USART_CFG_LINMODE_SHIFT (8U) | ||
| 20578 | /*! LINMODE - LIN break mode enable. | ||
| 20579 | * 0b0..Disabled. Break detect and generate is configured for normal operation. | ||
| 20580 | * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. | ||
| 20581 | */ | ||
| 20582 | #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) | ||
| 20583 | #define USART_CFG_CTSEN_MASK (0x200U) | ||
| 20584 | #define USART_CFG_CTSEN_SHIFT (9U) | ||
| 20585 | /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input | ||
| 20586 | * pin, or from the USART's own RTS if loopback mode is enabled. | ||
| 20587 | * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. | ||
| 20588 | * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. | ||
| 20589 | */ | ||
| 20590 | #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) | ||
| 20591 | #define USART_CFG_SYNCEN_MASK (0x800U) | ||
| 20592 | #define USART_CFG_SYNCEN_SHIFT (11U) | ||
| 20593 | /*! SYNCEN - Selects synchronous or asynchronous operation. | ||
| 20594 | * 0b0..Asynchronous mode. | ||
| 20595 | * 0b1..Synchronous mode. | ||
| 20596 | */ | ||
| 20597 | #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) | ||
| 20598 | #define USART_CFG_CLKPOL_MASK (0x1000U) | ||
| 20599 | #define USART_CFG_CLKPOL_SHIFT (12U) | ||
| 20600 | /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. | ||
| 20601 | * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. | ||
| 20602 | * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. | ||
| 20603 | */ | ||
| 20604 | #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) | ||
| 20605 | #define USART_CFG_SYNCMST_MASK (0x4000U) | ||
| 20606 | #define USART_CFG_SYNCMST_SHIFT (14U) | ||
| 20607 | /*! SYNCMST - Synchronous mode Master select. | ||
| 20608 | * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. | ||
| 20609 | * 0b1..Master. When synchronous mode is enabled, the USART is a master. | ||
| 20610 | */ | ||
| 20611 | #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) | ||
| 20612 | #define USART_CFG_LOOP_MASK (0x8000U) | ||
| 20613 | #define USART_CFG_LOOP_SHIFT (15U) | ||
| 20614 | /*! LOOP - Selects data loopback mode. | ||
| 20615 | * 0b0..Normal operation. | ||
| 20616 | * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial | ||
| 20617 | * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD | ||
| 20618 | * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device | ||
| 20619 | * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. | ||
| 20620 | */ | ||
| 20621 | #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) | ||
| 20622 | #define USART_CFG_OETA_MASK (0x40000U) | ||
| 20623 | #define USART_CFG_OETA_SHIFT (18U) | ||
| 20624 | /*! OETA - Output Enable Turnaround time enable for RS-485 operation. | ||
| 20625 | * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. | ||
| 20626 | * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the | ||
| 20627 | * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins | ||
| 20628 | * before it is deasserted. | ||
| 20629 | */ | ||
| 20630 | #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) | ||
| 20631 | #define USART_CFG_AUTOADDR_MASK (0x80000U) | ||
| 20632 | #define USART_CFG_AUTOADDR_SHIFT (19U) | ||
| 20633 | /*! AUTOADDR - Automatic Address matching enable. | ||
| 20634 | * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the | ||
| 20635 | * possibility of versatile addressing (e.g. respond to more than one address). | ||
| 20636 | * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in | ||
| 20637 | * the ADDR register as the address to match. | ||
| 20638 | */ | ||
| 20639 | #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) | ||
| 20640 | #define USART_CFG_OESEL_MASK (0x100000U) | ||
| 20641 | #define USART_CFG_OESEL_SHIFT (20U) | ||
| 20642 | /*! OESEL - Output Enable Select. | ||
| 20643 | * 0b0..Standard. The RTS signal is used as the standard flow control function. | ||
| 20644 | * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. | ||
| 20645 | */ | ||
| 20646 | #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) | ||
| 20647 | #define USART_CFG_OEPOL_MASK (0x200000U) | ||
| 20648 | #define USART_CFG_OEPOL_SHIFT (21U) | ||
| 20649 | /*! OEPOL - Output Enable Polarity. | ||
| 20650 | * 0b0..Low. If selected by OESEL, the output enable is active low. | ||
| 20651 | * 0b1..High. If selected by OESEL, the output enable is active high. | ||
| 20652 | */ | ||
| 20653 | #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) | ||
| 20654 | #define USART_CFG_RXPOL_MASK (0x400000U) | ||
| 20655 | #define USART_CFG_RXPOL_SHIFT (22U) | ||
| 20656 | /*! RXPOL - Receive data polarity. | ||
| 20657 | * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start | ||
| 20658 | * bit is 0, data is not inverted, and the stop bit is 1. | ||
| 20659 | * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is | ||
| 20660 | * 0, start bit is 1, data is inverted, and the stop bit is 0. | ||
| 20661 | */ | ||
| 20662 | #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) | ||
| 20663 | #define USART_CFG_TXPOL_MASK (0x800000U) | ||
| 20664 | #define USART_CFG_TXPOL_SHIFT (23U) | ||
| 20665 | /*! TXPOL - Transmit data polarity. | ||
| 20666 | * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is | ||
| 20667 | * 0, data is not inverted, and the stop bit is 1. | ||
| 20668 | * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value | ||
| 20669 | * is 0, start bit is 1, data is inverted, and the stop bit is 0. | ||
| 20670 | */ | ||
| 20671 | #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) | ||
| 20672 | /*! @} */ | ||
| 20673 | |||
| 20674 | /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ | ||
| 20675 | /*! @{ */ | ||
| 20676 | #define USART_CTL_TXBRKEN_MASK (0x2U) | ||
| 20677 | #define USART_CTL_TXBRKEN_SHIFT (1U) | ||
| 20678 | /*! TXBRKEN - Break Enable. | ||
| 20679 | * 0b0..Normal operation. | ||
| 20680 | * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit | ||
| 20681 | * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the | ||
| 20682 | * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled | ||
| 20683 | * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. | ||
| 20684 | */ | ||
| 20685 | #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) | ||
| 20686 | #define USART_CTL_ADDRDET_MASK (0x4U) | ||
| 20687 | #define USART_CTL_ADDRDET_SHIFT (2U) | ||
| 20688 | /*! ADDRDET - Enable address detect mode. | ||
| 20689 | * 0b0..Disabled. The USART presents all incoming data. | ||
| 20690 | * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data | ||
| 20691 | * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, | ||
| 20692 | * generating a received data interrupt. Software can then check the data to see if this is an address that | ||
| 20693 | * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled | ||
| 20694 | * normally. | ||
| 20695 | */ | ||
| 20696 | #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) | ||
| 20697 | #define USART_CTL_TXDIS_MASK (0x40U) | ||
| 20698 | #define USART_CTL_TXDIS_SHIFT (6U) | ||
| 20699 | /*! TXDIS - Transmit Disable. | ||
| 20700 | * 0b0..Not disabled. USART transmitter is not disabled. | ||
| 20701 | * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This | ||
| 20702 | * feature can be used to facilitate software flow control. | ||
| 20703 | */ | ||
| 20704 | #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) | ||
| 20705 | #define USART_CTL_CC_MASK (0x100U) | ||
| 20706 | #define USART_CTL_CC_SHIFT (8U) | ||
| 20707 | /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. | ||
| 20708 | * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to | ||
| 20709 | * complete a character that is being received. | ||
| 20710 | * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on | ||
| 20711 | * Un_RxD independently from transmission on Un_TXD). | ||
| 20712 | */ | ||
| 20713 | #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) | ||
| 20714 | #define USART_CTL_CLRCCONRX_MASK (0x200U) | ||
| 20715 | #define USART_CTL_CLRCCONRX_SHIFT (9U) | ||
| 20716 | /*! CLRCCONRX - Clear Continuous Clock. | ||
| 20717 | * 0b0..No effect. No effect on the CC bit. | ||
| 20718 | * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. | ||
| 20719 | */ | ||
| 20720 | #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) | ||
| 20721 | #define USART_CTL_AUTOBAUD_MASK (0x10000U) | ||
| 20722 | #define USART_CTL_AUTOBAUD_SHIFT (16U) | ||
| 20723 | /*! AUTOBAUD - Autobaud enable. | ||
| 20724 | * 0b0..Disabled. USART is in normal operating mode. | ||
| 20725 | * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The | ||
| 20726 | * first start bit of RX is measured and used the update the BRG register to match the received data rate. | ||
| 20727 | * AUTOBAUD is cleared once this process is complete, or if there is an AERR. | ||
| 20728 | */ | ||
| 20729 | #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) | ||
| 20730 | /*! @} */ | ||
| 20731 | |||
| 20732 | /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ | ||
| 20733 | /*! @{ */ | ||
| 20734 | #define USART_STAT_RXIDLE_MASK (0x2U) | ||
| 20735 | #define USART_STAT_RXIDLE_SHIFT (1U) | ||
| 20736 | /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of | ||
| 20737 | * receiving data. When 1, indicates that the receiver is not currently in the process of receiving | ||
| 20738 | * data. | ||
| 20739 | */ | ||
| 20740 | #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) | ||
| 20741 | #define USART_STAT_TXIDLE_MASK (0x8U) | ||
| 20742 | #define USART_STAT_TXIDLE_SHIFT (3U) | ||
| 20743 | /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of | ||
| 20744 | * sending data.When 1, indicate that the transmitter is not currently in the process of sending | ||
| 20745 | * data. | ||
| 20746 | */ | ||
| 20747 | #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) | ||
| 20748 | #define USART_STAT_CTS_MASK (0x10U) | ||
| 20749 | #define USART_STAT_CTS_SHIFT (4U) | ||
| 20750 | /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the | ||
| 20751 | * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode | ||
| 20752 | * is enabled. | ||
| 20753 | */ | ||
| 20754 | #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) | ||
| 20755 | #define USART_STAT_DELTACTS_MASK (0x20U) | ||
| 20756 | #define USART_STAT_DELTACTS_SHIFT (5U) | ||
| 20757 | /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. | ||
| 20758 | */ | ||
| 20759 | #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) | ||
| 20760 | #define USART_STAT_TXDISSTAT_MASK (0x40U) | ||
| 20761 | #define USART_STAT_TXDISSTAT_SHIFT (6U) | ||
| 20762 | /*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART | ||
| 20763 | * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). | ||
| 20764 | */ | ||
| 20765 | #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) | ||
| 20766 | #define USART_STAT_RXBRK_MASK (0x400U) | ||
| 20767 | #define USART_STAT_RXBRK_SHIFT (10U) | ||
| 20768 | /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection | ||
| 20769 | * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also | ||
| 20770 | * be set when this condition occurs because the stop bit(s) for the character would be missing. | ||
| 20771 | * RXBRK is cleared when the Un_RXD pin goes high. | ||
| 20772 | */ | ||
| 20773 | #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) | ||
| 20774 | #define USART_STAT_DELTARXBRK_MASK (0x800U) | ||
| 20775 | #define USART_STAT_DELTARXBRK_SHIFT (11U) | ||
| 20776 | /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. | ||
| 20777 | */ | ||
| 20778 | #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) | ||
| 20779 | #define USART_STAT_START_MASK (0x1000U) | ||
| 20780 | #define USART_STAT_START_SHIFT (12U) | ||
| 20781 | /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily | ||
| 20782 | * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. | ||
| 20783 | * Cleared by software. | ||
| 20784 | */ | ||
| 20785 | #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) | ||
| 20786 | #define USART_STAT_FRAMERRINT_MASK (0x2000U) | ||
| 20787 | #define USART_STAT_FRAMERRINT_SHIFT (13U) | ||
| 20788 | /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a | ||
| 20789 | * missing stop bit at the expected location. This could be an indication of a baud rate or | ||
| 20790 | * configuration mismatch with the transmitting source. | ||
| 20791 | */ | ||
| 20792 | #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) | ||
| 20793 | #define USART_STAT_PARITYERRINT_MASK (0x4000U) | ||
| 20794 | #define USART_STAT_PARITYERRINT_SHIFT (14U) | ||
| 20795 | /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. | ||
| 20796 | */ | ||
| 20797 | #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) | ||
| 20798 | #define USART_STAT_RXNOISEINT_MASK (0x8000U) | ||
| 20799 | #define USART_STAT_RXNOISEINT_SHIFT (15U) | ||
| 20800 | /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to | ||
| 20801 | * determine the value of each received data bit, except in synchronous mode. This acts as a | ||
| 20802 | * noise filter if one sample disagrees. This flag is set when a received data bit contains one | ||
| 20803 | * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or | ||
| 20804 | * loss of synchronization during data reception. | ||
| 20805 | */ | ||
| 20806 | #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) | ||
| 20807 | #define USART_STAT_ABERR_MASK (0x10000U) | ||
| 20808 | #define USART_STAT_ABERR_SHIFT (16U) | ||
| 20809 | /*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the | ||
| 20810 | * end of the start bit that is being measured, essentially an auto baud time-out. | ||
| 20811 | */ | ||
| 20812 | #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) | ||
| 20813 | /*! @} */ | ||
| 20814 | |||
| 20815 | /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ | ||
| 20816 | /*! @{ */ | ||
| 20817 | #define USART_INTENSET_TXIDLEEN_MASK (0x8U) | ||
| 20818 | #define USART_INTENSET_TXIDLEEN_SHIFT (3U) | ||
| 20819 | /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). | ||
| 20820 | */ | ||
| 20821 | #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) | ||
| 20822 | #define USART_INTENSET_DELTACTSEN_MASK (0x20U) | ||
| 20823 | #define USART_INTENSET_DELTACTSEN_SHIFT (5U) | ||
| 20824 | /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. | ||
| 20825 | */ | ||
| 20826 | #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) | ||
| 20827 | #define USART_INTENSET_TXDISEN_MASK (0x40U) | ||
| 20828 | #define USART_INTENSET_TXDISEN_SHIFT (6U) | ||
| 20829 | /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by | ||
| 20830 | * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. | ||
| 20831 | */ | ||
| 20832 | #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) | ||
| 20833 | #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) | ||
| 20834 | #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) | ||
| 20835 | /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection | ||
| 20836 | * of a received break condition (break condition asserted or deasserted). | ||
| 20837 | */ | ||
| 20838 | #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) | ||
| 20839 | #define USART_INTENSET_STARTEN_MASK (0x1000U) | ||
| 20840 | #define USART_INTENSET_STARTEN_SHIFT (12U) | ||
| 20841 | /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. | ||
| 20842 | */ | ||
| 20843 | #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) | ||
| 20844 | #define USART_INTENSET_FRAMERREN_MASK (0x2000U) | ||
| 20845 | #define USART_INTENSET_FRAMERREN_SHIFT (13U) | ||
| 20846 | /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. | ||
| 20847 | */ | ||
| 20848 | #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) | ||
| 20849 | #define USART_INTENSET_PARITYERREN_MASK (0x4000U) | ||
| 20850 | #define USART_INTENSET_PARITYERREN_SHIFT (14U) | ||
| 20851 | /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. | ||
| 20852 | */ | ||
| 20853 | #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) | ||
| 20854 | #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) | ||
| 20855 | #define USART_INTENSET_RXNOISEEN_SHIFT (15U) | ||
| 20856 | /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. | ||
| 20857 | */ | ||
| 20858 | #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) | ||
| 20859 | #define USART_INTENSET_ABERREN_MASK (0x10000U) | ||
| 20860 | #define USART_INTENSET_ABERREN_SHIFT (16U) | ||
| 20861 | /*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. | ||
| 20862 | */ | ||
| 20863 | #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) | ||
| 20864 | /*! @} */ | ||
| 20865 | |||
| 20866 | /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ | ||
| 20867 | /*! @{ */ | ||
| 20868 | #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) | ||
| 20869 | #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) | ||
| 20870 | /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20871 | */ | ||
| 20872 | #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) | ||
| 20873 | #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) | ||
| 20874 | #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) | ||
| 20875 | /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20876 | */ | ||
| 20877 | #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) | ||
| 20878 | #define USART_INTENCLR_TXDISCLR_MASK (0x40U) | ||
| 20879 | #define USART_INTENCLR_TXDISCLR_SHIFT (6U) | ||
| 20880 | /*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20881 | */ | ||
| 20882 | #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) | ||
| 20883 | #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) | ||
| 20884 | #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) | ||
| 20885 | /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20886 | */ | ||
| 20887 | #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) | ||
| 20888 | #define USART_INTENCLR_STARTCLR_MASK (0x1000U) | ||
| 20889 | #define USART_INTENCLR_STARTCLR_SHIFT (12U) | ||
| 20890 | /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20891 | */ | ||
| 20892 | #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) | ||
| 20893 | #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) | ||
| 20894 | #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) | ||
| 20895 | /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20896 | */ | ||
| 20897 | #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) | ||
| 20898 | #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) | ||
| 20899 | #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) | ||
| 20900 | /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20901 | */ | ||
| 20902 | #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) | ||
| 20903 | #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) | ||
| 20904 | #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) | ||
| 20905 | /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20906 | */ | ||
| 20907 | #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) | ||
| 20908 | #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) | ||
| 20909 | #define USART_INTENCLR_ABERRCLR_SHIFT (16U) | ||
| 20910 | /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. | ||
| 20911 | */ | ||
| 20912 | #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) | ||
| 20913 | /*! @} */ | ||
| 20914 | |||
| 20915 | /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ | ||
| 20916 | /*! @{ */ | ||
| 20917 | #define USART_BRG_BRGVAL_MASK (0xFFFFU) | ||
| 20918 | #define USART_BRG_BRGVAL_SHIFT (0U) | ||
| 20919 | /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on | ||
| 20920 | * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is | ||
| 20921 | * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART | ||
| 20922 | * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. | ||
| 20923 | */ | ||
| 20924 | #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) | ||
| 20925 | /*! @} */ | ||
| 20926 | |||
| 20927 | /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ | ||
| 20928 | /*! @{ */ | ||
| 20929 | #define USART_INTSTAT_TXIDLE_MASK (0x8U) | ||
| 20930 | #define USART_INTSTAT_TXIDLE_SHIFT (3U) | ||
| 20931 | /*! TXIDLE - Transmitter Idle status. | ||
| 20932 | */ | ||
| 20933 | #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) | ||
| 20934 | #define USART_INTSTAT_DELTACTS_MASK (0x20U) | ||
| 20935 | #define USART_INTSTAT_DELTACTS_SHIFT (5U) | ||
| 20936 | /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. | ||
| 20937 | */ | ||
| 20938 | #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) | ||
| 20939 | #define USART_INTSTAT_TXDISINT_MASK (0x40U) | ||
| 20940 | #define USART_INTSTAT_TXDISINT_SHIFT (6U) | ||
| 20941 | /*! TXDISINT - Transmitter Disabled Interrupt flag. | ||
| 20942 | */ | ||
| 20943 | #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) | ||
| 20944 | #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) | ||
| 20945 | #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) | ||
| 20946 | /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. | ||
| 20947 | */ | ||
| 20948 | #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) | ||
| 20949 | #define USART_INTSTAT_START_MASK (0x1000U) | ||
| 20950 | #define USART_INTSTAT_START_SHIFT (12U) | ||
| 20951 | /*! START - This bit is set when a start is detected on the receiver input. | ||
| 20952 | */ | ||
| 20953 | #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) | ||
| 20954 | #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) | ||
| 20955 | #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) | ||
| 20956 | /*! FRAMERRINT - Framing Error interrupt flag. | ||
| 20957 | */ | ||
| 20958 | #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) | ||
| 20959 | #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) | ||
| 20960 | #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) | ||
| 20961 | /*! PARITYERRINT - Parity Error interrupt flag. | ||
| 20962 | */ | ||
| 20963 | #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) | ||
| 20964 | #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) | ||
| 20965 | #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) | ||
| 20966 | /*! RXNOISEINT - Received Noise interrupt flag. | ||
| 20967 | */ | ||
| 20968 | #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) | ||
| 20969 | #define USART_INTSTAT_ABERRINT_MASK (0x10000U) | ||
| 20970 | #define USART_INTSTAT_ABERRINT_SHIFT (16U) | ||
| 20971 | /*! ABERRINT - Auto baud Error Interrupt flag. | ||
| 20972 | */ | ||
| 20973 | #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) | ||
| 20974 | /*! @} */ | ||
| 20975 | |||
| 20976 | /*! @name OSR - Oversample selection register for asynchronous communication. */ | ||
| 20977 | /*! @{ */ | ||
| 20978 | #define USART_OSR_OSRVAL_MASK (0xFU) | ||
| 20979 | #define USART_OSR_OSRVAL_SHIFT (0U) | ||
| 20980 | /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to | ||
| 20981 | * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive | ||
| 20982 | * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. | ||
| 20983 | */ | ||
| 20984 | #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) | ||
| 20985 | /*! @} */ | ||
| 20986 | |||
| 20987 | /*! @name ADDR - Address register for automatic address matching. */ | ||
| 20988 | /*! @{ */ | ||
| 20989 | #define USART_ADDR_ADDRESS_MASK (0xFFU) | ||
| 20990 | #define USART_ADDR_ADDRESS_SHIFT (0U) | ||
| 20991 | /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is | ||
| 20992 | * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). | ||
| 20993 | */ | ||
| 20994 | #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) | ||
| 20995 | /*! @} */ | ||
| 20996 | |||
| 20997 | /*! @name FIFOCFG - FIFO configuration and enable register. */ | ||
| 20998 | /*! @{ */ | ||
| 20999 | #define USART_FIFOCFG_ENABLETX_MASK (0x1U) | ||
| 21000 | #define USART_FIFOCFG_ENABLETX_SHIFT (0U) | ||
| 21001 | /*! ENABLETX - Enable the transmit FIFO. | ||
| 21002 | * 0b0..The transmit FIFO is not enabled. | ||
| 21003 | * 0b1..The transmit FIFO is enabled. | ||
| 21004 | */ | ||
| 21005 | #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) | ||
| 21006 | #define USART_FIFOCFG_ENABLERX_MASK (0x2U) | ||
| 21007 | #define USART_FIFOCFG_ENABLERX_SHIFT (1U) | ||
| 21008 | /*! ENABLERX - Enable the receive FIFO. | ||
| 21009 | * 0b0..The receive FIFO is not enabled. | ||
| 21010 | * 0b1..The receive FIFO is enabled. | ||
| 21011 | */ | ||
| 21012 | #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) | ||
| 21013 | #define USART_FIFOCFG_SIZE_MASK (0x30U) | ||
| 21014 | #define USART_FIFOCFG_SIZE_SHIFT (4U) | ||
| 21015 | /*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 | ||
| 21016 | * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. | ||
| 21017 | */ | ||
| 21018 | #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) | ||
| 21019 | #define USART_FIFOCFG_DMATX_MASK (0x1000U) | ||
| 21020 | #define USART_FIFOCFG_DMATX_SHIFT (12U) | ||
| 21021 | /*! DMATX - DMA configuration for transmit. | ||
| 21022 | * 0b0..DMA is not used for the transmit function. | ||
| 21023 | * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 21024 | */ | ||
| 21025 | #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) | ||
| 21026 | #define USART_FIFOCFG_DMARX_MASK (0x2000U) | ||
| 21027 | #define USART_FIFOCFG_DMARX_SHIFT (13U) | ||
| 21028 | /*! DMARX - DMA configuration for receive. | ||
| 21029 | * 0b0..DMA is not used for the receive function. | ||
| 21030 | * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. | ||
| 21031 | */ | ||
| 21032 | #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) | ||
| 21033 | #define USART_FIFOCFG_WAKETX_MASK (0x4000U) | ||
| 21034 | #define USART_FIFOCFG_WAKETX_SHIFT (14U) | ||
| 21035 | /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power | ||
| 21036 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 21037 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 21038 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 21039 | * Wake-up control register. | ||
| 21040 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 21041 | * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in | ||
| 21042 | * FIFOTRIG, even when the TXLVL interrupt is not enabled. | ||
| 21043 | */ | ||
| 21044 | #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) | ||
| 21045 | #define USART_FIFOCFG_WAKERX_MASK (0x8000U) | ||
| 21046 | #define USART_FIFOCFG_WAKERX_SHIFT (15U) | ||
| 21047 | /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power | ||
| 21048 | * modes (up to power-down, as long as the peripheral function works in that power mode) without | ||
| 21049 | * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The | ||
| 21050 | * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware | ||
| 21051 | * Wake-up control register. | ||
| 21052 | * 0b0..Only enabled interrupts will wake up the device form reduced power modes. | ||
| 21053 | * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in | ||
| 21054 | * FIFOTRIG, even when the RXLVL interrupt is not enabled. | ||
| 21055 | */ | ||
| 21056 | #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) | ||
| 21057 | #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) | ||
| 21058 | #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) | ||
| 21059 | /*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. | ||
| 21060 | */ | ||
| 21061 | #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) | ||
| 21062 | #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) | ||
| 21063 | #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) | ||
| 21064 | /*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. | ||
| 21065 | */ | ||
| 21066 | #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) | ||
| 21067 | /*! @} */ | ||
| 21068 | |||
| 21069 | /*! @name FIFOSTAT - FIFO status register. */ | ||
| 21070 | /*! @{ */ | ||
| 21071 | #define USART_FIFOSTAT_TXERR_MASK (0x1U) | ||
| 21072 | #define USART_FIFOSTAT_TXERR_SHIFT (0U) | ||
| 21073 | /*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow | ||
| 21074 | * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is | ||
| 21075 | * needed. Cleared by writing a 1 to this bit. | ||
| 21076 | */ | ||
| 21077 | #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) | ||
| 21078 | #define USART_FIFOSTAT_RXERR_MASK (0x2U) | ||
| 21079 | #define USART_FIFOSTAT_RXERR_SHIFT (1U) | ||
| 21080 | /*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA | ||
| 21081 | * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. | ||
| 21082 | */ | ||
| 21083 | #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) | ||
| 21084 | #define USART_FIFOSTAT_PERINT_MASK (0x8U) | ||
| 21085 | #define USART_FIFOSTAT_PERINT_SHIFT (3U) | ||
| 21086 | /*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted | ||
| 21087 | * an interrupt. The details can be found by reading the peripheral's STAT register. | ||
| 21088 | */ | ||
| 21089 | #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) | ||
| 21090 | #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) | ||
| 21091 | #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) | ||
| 21092 | /*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. | ||
| 21093 | */ | ||
| 21094 | #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) | ||
| 21095 | #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) | ||
| 21096 | #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) | ||
| 21097 | /*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be | ||
| 21098 | * written. When 0, the transmit FIFO is full and another write would cause it to overflow. | ||
| 21099 | */ | ||
| 21100 | #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) | ||
| 21101 | #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) | ||
| 21102 | #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) | ||
| 21103 | /*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. | ||
| 21104 | */ | ||
| 21105 | #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) | ||
| 21106 | #define USART_FIFOSTAT_RXFULL_MASK (0x80U) | ||
| 21107 | #define USART_FIFOSTAT_RXFULL_SHIFT (7U) | ||
| 21108 | /*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to | ||
| 21109 | * prevent the peripheral from causing an overflow. | ||
| 21110 | */ | ||
| 21111 | #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) | ||
| 21112 | #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) | ||
| 21113 | #define USART_FIFOSTAT_TXLVL_SHIFT (8U) | ||
| 21114 | /*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY | ||
| 21115 | * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at | ||
| 21116 | * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be | ||
| 21117 | * 0. | ||
| 21118 | */ | ||
| 21119 | #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) | ||
| 21120 | #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) | ||
| 21121 | #define USART_FIFOSTAT_RXLVL_SHIFT (16U) | ||
| 21122 | /*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and | ||
| 21123 | * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the | ||
| 21124 | * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be | ||
| 21125 | * 1. | ||
| 21126 | */ | ||
| 21127 | #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) | ||
| 21128 | /*! @} */ | ||
| 21129 | |||
| 21130 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ | ||
| 21131 | /*! @{ */ | ||
| 21132 | #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) | ||
| 21133 | #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) | ||
| 21134 | /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 21135 | * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. | ||
| 21136 | * 0b0..Transmit FIFO level does not generate a FIFO level trigger. | ||
| 21137 | * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. | ||
| 21138 | */ | ||
| 21139 | #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) | ||
| 21140 | #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) | ||
| 21141 | #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) | ||
| 21142 | /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled | ||
| 21143 | * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. | ||
| 21144 | * 0b0..Receive FIFO level does not generate a FIFO level trigger. | ||
| 21145 | * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. | ||
| 21146 | */ | ||
| 21147 | #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) | ||
| 21148 | #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) | ||
| 21149 | #define USART_FIFOTRIG_TXLVL_SHIFT (8U) | ||
| 21150 | /*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled | ||
| 21151 | * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to | ||
| 21152 | * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO | ||
| 21153 | * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX | ||
| 21154 | * FIFO level decreases to 15 entries (is no longer full). | ||
| 21155 | */ | ||
| 21156 | #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) | ||
| 21157 | #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) | ||
| 21158 | #define USART_FIFOTRIG_RXLVL_SHIFT (16U) | ||
| 21159 | /*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data | ||
| 21160 | * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level | ||
| 21161 | * can wake up the device just enough to perform DMA, then return to the reduced power mode. See | ||
| 21162 | * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no | ||
| 21163 | * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX | ||
| 21164 | * FIFO has received 16 entries (has become full). | ||
| 21165 | */ | ||
| 21166 | #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) | ||
| 21167 | /*! @} */ | ||
| 21168 | |||
| 21169 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ | ||
| 21170 | /*! @{ */ | ||
| 21171 | #define USART_FIFOINTENSET_TXERR_MASK (0x1U) | ||
| 21172 | #define USART_FIFOINTENSET_TXERR_SHIFT (0U) | ||
| 21173 | /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. | ||
| 21174 | * 0b0..No interrupt will be generated for a transmit error. | ||
| 21175 | * 0b1..An interrupt will be generated when a transmit error occurs. | ||
| 21176 | */ | ||
| 21177 | #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) | ||
| 21178 | #define USART_FIFOINTENSET_RXERR_MASK (0x2U) | ||
| 21179 | #define USART_FIFOINTENSET_RXERR_SHIFT (1U) | ||
| 21180 | /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. | ||
| 21181 | * 0b0..No interrupt will be generated for a receive error. | ||
| 21182 | * 0b1..An interrupt will be generated when a receive error occurs. | ||
| 21183 | */ | ||
| 21184 | #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) | ||
| 21185 | #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) | ||
| 21186 | #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) | ||
| 21187 | /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level | ||
| 21188 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 21189 | * 0b0..No interrupt will be generated based on the TX FIFO level. | ||
| 21190 | * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases | ||
| 21191 | * to the level specified by TXLVL in the FIFOTRIG register. | ||
| 21192 | */ | ||
| 21193 | #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) | ||
| 21194 | #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) | ||
| 21195 | #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) | ||
| 21196 | /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level | ||
| 21197 | * specified by the TXLVL field in the FIFOTRIG register. | ||
| 21198 | * 0b0..No interrupt will be generated based on the RX FIFO level. | ||
| 21199 | * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level | ||
| 21200 | * increases to the level specified by RXLVL in the FIFOTRIG register. | ||
| 21201 | */ | ||
| 21202 | #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) | ||
| 21203 | /*! @} */ | ||
| 21204 | |||
| 21205 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ | ||
| 21206 | /*! @{ */ | ||
| 21207 | #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) | ||
| 21208 | #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) | ||
| 21209 | /*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 21210 | */ | ||
| 21211 | #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) | ||
| 21212 | #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) | ||
| 21213 | #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) | ||
| 21214 | /*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 21215 | */ | ||
| 21216 | #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) | ||
| 21217 | #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) | ||
| 21218 | #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) | ||
| 21219 | /*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 21220 | */ | ||
| 21221 | #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) | ||
| 21222 | #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) | ||
| 21223 | #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) | ||
| 21224 | /*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. | ||
| 21225 | */ | ||
| 21226 | #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) | ||
| 21227 | /*! @} */ | ||
| 21228 | |||
| 21229 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ | ||
| 21230 | /*! @{ */ | ||
| 21231 | #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) | ||
| 21232 | #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) | ||
| 21233 | /*! TXERR - TX FIFO error. | ||
| 21234 | */ | ||
| 21235 | #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) | ||
| 21236 | #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) | ||
| 21237 | #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) | ||
| 21238 | /*! RXERR - RX FIFO error. | ||
| 21239 | */ | ||
| 21240 | #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) | ||
| 21241 | #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) | ||
| 21242 | #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) | ||
| 21243 | /*! TXLVL - Transmit FIFO level interrupt. | ||
| 21244 | */ | ||
| 21245 | #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) | ||
| 21246 | #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) | ||
| 21247 | #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) | ||
| 21248 | /*! RXLVL - Receive FIFO level interrupt. | ||
| 21249 | */ | ||
| 21250 | #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) | ||
| 21251 | #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) | ||
| 21252 | #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) | ||
| 21253 | /*! PERINT - Peripheral interrupt. | ||
| 21254 | */ | ||
| 21255 | #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) | ||
| 21256 | /*! @} */ | ||
| 21257 | |||
| 21258 | /*! @name FIFOWR - FIFO write data. */ | ||
| 21259 | /*! @{ */ | ||
| 21260 | #define USART_FIFOWR_TXDATA_MASK (0x1FFU) | ||
| 21261 | #define USART_FIFOWR_TXDATA_SHIFT (0U) | ||
| 21262 | /*! TXDATA - Transmit data to the FIFO. | ||
| 21263 | */ | ||
| 21264 | #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) | ||
| 21265 | /*! @} */ | ||
| 21266 | |||
| 21267 | /*! @name FIFORD - FIFO read data. */ | ||
| 21268 | /*! @{ */ | ||
| 21269 | #define USART_FIFORD_RXDATA_MASK (0x1FFU) | ||
| 21270 | #define USART_FIFORD_RXDATA_SHIFT (0U) | ||
| 21271 | /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. | ||
| 21272 | */ | ||
| 21273 | #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) | ||
| 21274 | #define USART_FIFORD_FRAMERR_MASK (0x2000U) | ||
| 21275 | #define USART_FIFORD_FRAMERR_SHIFT (13U) | ||
| 21276 | /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along | ||
| 21277 | * with from the FIFO, and indicates that the character was received with a missing stop bit at | ||
| 21278 | * the expected location. This could be an indication of a baud rate or configuration mismatch | ||
| 21279 | * with the transmitting source. | ||
| 21280 | */ | ||
| 21281 | #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) | ||
| 21282 | #define USART_FIFORD_PARITYERR_MASK (0x4000U) | ||
| 21283 | #define USART_FIFORD_PARITYERR_SHIFT (14U) | ||
| 21284 | /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along | ||
| 21285 | * with from the FIFO. This bit will be set when a parity error is detected in a received | ||
| 21286 | * character. | ||
| 21287 | */ | ||
| 21288 | #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) | ||
| 21289 | #define USART_FIFORD_RXNOISE_MASK (0x8000U) | ||
| 21290 | #define USART_FIFORD_RXNOISE_SHIFT (15U) | ||
| 21291 | /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. | ||
| 21292 | */ | ||
| 21293 | #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) | ||
| 21294 | /*! @} */ | ||
| 21295 | |||
| 21296 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ | ||
| 21297 | /*! @{ */ | ||
| 21298 | #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) | ||
| 21299 | #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) | ||
| 21300 | /*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. | ||
| 21301 | */ | ||
| 21302 | #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) | ||
| 21303 | #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) | ||
| 21304 | #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) | ||
| 21305 | /*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along | ||
| 21306 | * with from the FIFO, and indicates that the character was received with a missing stop bit at | ||
| 21307 | * the expected location. This could be an indication of a baud rate or configuration mismatch | ||
| 21308 | * with the transmitting source. | ||
| 21309 | */ | ||
| 21310 | #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) | ||
| 21311 | #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) | ||
| 21312 | #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) | ||
| 21313 | /*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along | ||
| 21314 | * with from the FIFO. This bit will be set when a parity error is detected in a received | ||
| 21315 | * character. | ||
| 21316 | */ | ||
| 21317 | #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) | ||
| 21318 | #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) | ||
| 21319 | #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) | ||
| 21320 | /*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. | ||
| 21321 | */ | ||
| 21322 | #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) | ||
| 21323 | /*! @} */ | ||
| 21324 | |||
| 21325 | /*! @name ID - Peripheral identification register. */ | ||
| 21326 | /*! @{ */ | ||
| 21327 | #define USART_ID_APERTURE_MASK (0xFFU) | ||
| 21328 | #define USART_ID_APERTURE_SHIFT (0U) | ||
| 21329 | /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. | ||
| 21330 | */ | ||
| 21331 | #define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) | ||
| 21332 | #define USART_ID_MINOR_REV_MASK (0xF00U) | ||
| 21333 | #define USART_ID_MINOR_REV_SHIFT (8U) | ||
| 21334 | /*! MINOR_REV - Minor revision of module implementation. | ||
| 21335 | */ | ||
| 21336 | #define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) | ||
| 21337 | #define USART_ID_MAJOR_REV_MASK (0xF000U) | ||
| 21338 | #define USART_ID_MAJOR_REV_SHIFT (12U) | ||
| 21339 | /*! MAJOR_REV - Major revision of module implementation. | ||
| 21340 | */ | ||
| 21341 | #define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) | ||
| 21342 | #define USART_ID_ID_MASK (0xFFFF0000U) | ||
| 21343 | #define USART_ID_ID_SHIFT (16U) | ||
| 21344 | /*! ID - Module identifier for the selected function. | ||
| 21345 | */ | ||
| 21346 | #define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) | ||
| 21347 | /*! @} */ | ||
| 21348 | |||
| 21349 | |||
| 21350 | /*! | ||
| 21351 | * @} | ||
| 21352 | */ /* end of group USART_Register_Masks */ | ||
| 21353 | |||
| 21354 | |||
| 21355 | /* USART - Peripheral instance base addresses */ | ||
| 21356 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 21357 | /** Peripheral USART0 base address */ | ||
| 21358 | #define USART0_BASE (0x50086000u) | ||
| 21359 | /** Peripheral USART0 base address */ | ||
| 21360 | #define USART0_BASE_NS (0x40086000u) | ||
| 21361 | /** Peripheral USART0 base pointer */ | ||
| 21362 | #define USART0 ((USART_Type *)USART0_BASE) | ||
| 21363 | /** Peripheral USART0 base pointer */ | ||
| 21364 | #define USART0_NS ((USART_Type *)USART0_BASE_NS) | ||
| 21365 | /** Peripheral USART1 base address */ | ||
| 21366 | #define USART1_BASE (0x50087000u) | ||
| 21367 | /** Peripheral USART1 base address */ | ||
| 21368 | #define USART1_BASE_NS (0x40087000u) | ||
| 21369 | /** Peripheral USART1 base pointer */ | ||
| 21370 | #define USART1 ((USART_Type *)USART1_BASE) | ||
| 21371 | /** Peripheral USART1 base pointer */ | ||
| 21372 | #define USART1_NS ((USART_Type *)USART1_BASE_NS) | ||
| 21373 | /** Peripheral USART2 base address */ | ||
| 21374 | #define USART2_BASE (0x50088000u) | ||
| 21375 | /** Peripheral USART2 base address */ | ||
| 21376 | #define USART2_BASE_NS (0x40088000u) | ||
| 21377 | /** Peripheral USART2 base pointer */ | ||
| 21378 | #define USART2 ((USART_Type *)USART2_BASE) | ||
| 21379 | /** Peripheral USART2 base pointer */ | ||
| 21380 | #define USART2_NS ((USART_Type *)USART2_BASE_NS) | ||
| 21381 | /** Peripheral USART3 base address */ | ||
| 21382 | #define USART3_BASE (0x50089000u) | ||
| 21383 | /** Peripheral USART3 base address */ | ||
| 21384 | #define USART3_BASE_NS (0x40089000u) | ||
| 21385 | /** Peripheral USART3 base pointer */ | ||
| 21386 | #define USART3 ((USART_Type *)USART3_BASE) | ||
| 21387 | /** Peripheral USART3 base pointer */ | ||
| 21388 | #define USART3_NS ((USART_Type *)USART3_BASE_NS) | ||
| 21389 | /** Peripheral USART4 base address */ | ||
| 21390 | #define USART4_BASE (0x5008A000u) | ||
| 21391 | /** Peripheral USART4 base address */ | ||
| 21392 | #define USART4_BASE_NS (0x4008A000u) | ||
| 21393 | /** Peripheral USART4 base pointer */ | ||
| 21394 | #define USART4 ((USART_Type *)USART4_BASE) | ||
| 21395 | /** Peripheral USART4 base pointer */ | ||
| 21396 | #define USART4_NS ((USART_Type *)USART4_BASE_NS) | ||
| 21397 | /** Peripheral USART5 base address */ | ||
| 21398 | #define USART5_BASE (0x50096000u) | ||
| 21399 | /** Peripheral USART5 base address */ | ||
| 21400 | #define USART5_BASE_NS (0x40096000u) | ||
| 21401 | /** Peripheral USART5 base pointer */ | ||
| 21402 | #define USART5 ((USART_Type *)USART5_BASE) | ||
| 21403 | /** Peripheral USART5 base pointer */ | ||
| 21404 | #define USART5_NS ((USART_Type *)USART5_BASE_NS) | ||
| 21405 | /** Peripheral USART6 base address */ | ||
| 21406 | #define USART6_BASE (0x50097000u) | ||
| 21407 | /** Peripheral USART6 base address */ | ||
| 21408 | #define USART6_BASE_NS (0x40097000u) | ||
| 21409 | /** Peripheral USART6 base pointer */ | ||
| 21410 | #define USART6 ((USART_Type *)USART6_BASE) | ||
| 21411 | /** Peripheral USART6 base pointer */ | ||
| 21412 | #define USART6_NS ((USART_Type *)USART6_BASE_NS) | ||
| 21413 | /** Peripheral USART7 base address */ | ||
| 21414 | #define USART7_BASE (0x50098000u) | ||
| 21415 | /** Peripheral USART7 base address */ | ||
| 21416 | #define USART7_BASE_NS (0x40098000u) | ||
| 21417 | /** Peripheral USART7 base pointer */ | ||
| 21418 | #define USART7 ((USART_Type *)USART7_BASE) | ||
| 21419 | /** Peripheral USART7 base pointer */ | ||
| 21420 | #define USART7_NS ((USART_Type *)USART7_BASE_NS) | ||
| 21421 | /** Array initializer of USART peripheral base addresses */ | ||
| 21422 | #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } | ||
| 21423 | /** Array initializer of USART peripheral base pointers */ | ||
| 21424 | #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } | ||
| 21425 | /** Array initializer of USART peripheral base addresses */ | ||
| 21426 | #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } | ||
| 21427 | /** Array initializer of USART peripheral base pointers */ | ||
| 21428 | #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } | ||
| 21429 | #else | ||
| 21430 | /** Peripheral USART0 base address */ | ||
| 21431 | #define USART0_BASE (0x40086000u) | ||
| 21432 | /** Peripheral USART0 base pointer */ | ||
| 21433 | #define USART0 ((USART_Type *)USART0_BASE) | ||
| 21434 | /** Peripheral USART1 base address */ | ||
| 21435 | #define USART1_BASE (0x40087000u) | ||
| 21436 | /** Peripheral USART1 base pointer */ | ||
| 21437 | #define USART1 ((USART_Type *)USART1_BASE) | ||
| 21438 | /** Peripheral USART2 base address */ | ||
| 21439 | #define USART2_BASE (0x40088000u) | ||
| 21440 | /** Peripheral USART2 base pointer */ | ||
| 21441 | #define USART2 ((USART_Type *)USART2_BASE) | ||
| 21442 | /** Peripheral USART3 base address */ | ||
| 21443 | #define USART3_BASE (0x40089000u) | ||
| 21444 | /** Peripheral USART3 base pointer */ | ||
| 21445 | #define USART3 ((USART_Type *)USART3_BASE) | ||
| 21446 | /** Peripheral USART4 base address */ | ||
| 21447 | #define USART4_BASE (0x4008A000u) | ||
| 21448 | /** Peripheral USART4 base pointer */ | ||
| 21449 | #define USART4 ((USART_Type *)USART4_BASE) | ||
| 21450 | /** Peripheral USART5 base address */ | ||
| 21451 | #define USART5_BASE (0x40096000u) | ||
| 21452 | /** Peripheral USART5 base pointer */ | ||
| 21453 | #define USART5 ((USART_Type *)USART5_BASE) | ||
| 21454 | /** Peripheral USART6 base address */ | ||
| 21455 | #define USART6_BASE (0x40097000u) | ||
| 21456 | /** Peripheral USART6 base pointer */ | ||
| 21457 | #define USART6 ((USART_Type *)USART6_BASE) | ||
| 21458 | /** Peripheral USART7 base address */ | ||
| 21459 | #define USART7_BASE (0x40098000u) | ||
| 21460 | /** Peripheral USART7 base pointer */ | ||
| 21461 | #define USART7 ((USART_Type *)USART7_BASE) | ||
| 21462 | /** Array initializer of USART peripheral base addresses */ | ||
| 21463 | #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } | ||
| 21464 | /** Array initializer of USART peripheral base pointers */ | ||
| 21465 | #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } | ||
| 21466 | #endif | ||
| 21467 | /** Interrupt vectors for the USART peripheral type */ | ||
| 21468 | #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } | ||
| 21469 | |||
| 21470 | /*! | ||
| 21471 | * @} | ||
| 21472 | */ /* end of group USART_Peripheral_Access_Layer */ | ||
| 21473 | |||
| 21474 | |||
| 21475 | /* ---------------------------------------------------------------------------- | ||
| 21476 | -- USB Peripheral Access Layer | ||
| 21477 | ---------------------------------------------------------------------------- */ | ||
| 21478 | |||
| 21479 | /*! | ||
| 21480 | * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer | ||
| 21481 | * @{ | ||
| 21482 | */ | ||
| 21483 | |||
| 21484 | /** USB - Register Layout Typedef */ | ||
| 21485 | typedef struct { | ||
| 21486 | __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ | ||
| 21487 | __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ | ||
| 21488 | __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ | ||
| 21489 | __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ | ||
| 21490 | __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ | ||
| 21491 | __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ | ||
| 21492 | __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ | ||
| 21493 | __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ | ||
| 21494 | __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ | ||
| 21495 | __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ | ||
| 21496 | __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ | ||
| 21497 | uint8_t RESERVED_0[8]; | ||
| 21498 | __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ | ||
| 21499 | } USB_Type; | ||
| 21500 | |||
| 21501 | /* ---------------------------------------------------------------------------- | ||
| 21502 | -- USB Register Masks | ||
| 21503 | ---------------------------------------------------------------------------- */ | ||
| 21504 | |||
| 21505 | /*! | ||
| 21506 | * @addtogroup USB_Register_Masks USB Register Masks | ||
| 21507 | * @{ | ||
| 21508 | */ | ||
| 21509 | |||
| 21510 | /*! @name DEVCMDSTAT - USB Device Command/Status register */ | ||
| 21511 | /*! @{ */ | ||
| 21512 | #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) | ||
| 21513 | #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) | ||
| 21514 | /*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit | ||
| 21515 | * is set, the device will respond on packets for function address DEV_ADDR. When receiving a | ||
| 21516 | * SetAddress Control Request from the USB host, software must program the new address before | ||
| 21517 | * completing the status phase of the SetAddress Control Request. | ||
| 21518 | */ | ||
| 21519 | #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) | ||
| 21520 | #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) | ||
| 21521 | #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) | ||
| 21522 | /*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. | ||
| 21523 | */ | ||
| 21524 | #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) | ||
| 21525 | #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) | ||
| 21526 | #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) | ||
| 21527 | /*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this | ||
| 21528 | * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW | ||
| 21529 | * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the | ||
| 21530 | * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. | ||
| 21531 | */ | ||
| 21532 | #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) | ||
| 21533 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) | ||
| 21534 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) | ||
| 21535 | /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: | ||
| 21536 | * 0b0..USB_NEEDCLK has normal function. | ||
| 21537 | * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. | ||
| 21538 | */ | ||
| 21539 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) | ||
| 21540 | #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) | ||
| 21541 | #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) | ||
| 21542 | /*! LPM_SUP - LPM Supported: | ||
| 21543 | * 0b0..LPM not supported. | ||
| 21544 | * 0b1..LPM supported. | ||
| 21545 | */ | ||
| 21546 | #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) | ||
| 21547 | #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) | ||
| 21548 | #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) | ||
| 21549 | /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP | ||
| 21550 | * 0b0..Only acknowledged packets generate an interrupt | ||
| 21551 | * 0b1..Both acknowledged and NAKed packets generate interrupts. | ||
| 21552 | */ | ||
| 21553 | #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) | ||
| 21554 | #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) | ||
| 21555 | #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) | ||
| 21556 | /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP | ||
| 21557 | * 0b0..Only acknowledged packets generate an interrupt | ||
| 21558 | * 0b1..Both acknowledged and NAKed packets generate interrupts. | ||
| 21559 | */ | ||
| 21560 | #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) | ||
| 21561 | #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) | ||
| 21562 | #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) | ||
| 21563 | /*! INTONNAK_CO - Interrupt on NAK for control OUT EP | ||
| 21564 | * 0b0..Only acknowledged packets generate an interrupt | ||
| 21565 | * 0b1..Both acknowledged and NAKed packets generate interrupts. | ||
| 21566 | */ | ||
| 21567 | #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) | ||
| 21568 | #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) | ||
| 21569 | #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) | ||
| 21570 | /*! INTONNAK_CI - Interrupt on NAK for control IN EP | ||
| 21571 | * 0b0..Only acknowledged packets generate an interrupt | ||
| 21572 | * 0b1..Both acknowledged and NAKed packets generate interrupts. | ||
| 21573 | */ | ||
| 21574 | #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) | ||
| 21575 | #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) | ||
| 21576 | #define USB_DEVCMDSTAT_DCON_SHIFT (16U) | ||
| 21577 | /*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device | ||
| 21578 | * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and | ||
| 21579 | * the VBUSDEBOUNCED bit is one. | ||
| 21580 | */ | ||
| 21581 | #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) | ||
| 21582 | #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) | ||
| 21583 | #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) | ||
| 21584 | /*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set | ||
| 21585 | * to 1 when the device hasn't seen any activity on its upstream port for more than 3 | ||
| 21586 | * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and | ||
| 21587 | * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen | ||
| 21588 | * when the device is connected (Connect bit = 1). When the device is not connected or not | ||
| 21589 | * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. | ||
| 21590 | */ | ||
| 21591 | #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) | ||
| 21592 | #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) | ||
| 21593 | #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) | ||
| 21594 | /*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is | ||
| 21595 | * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the | ||
| 21596 | * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend | ||
| 21597 | * bit = 1) and the software writes a zero to this bit, the device will generate a remote | ||
| 21598 | * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this | ||
| 21599 | * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the | ||
| 21600 | * LPM_SUPP bit is equal to one. | ||
| 21601 | */ | ||
| 21602 | #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) | ||
| 21603 | #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) | ||
| 21604 | #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) | ||
| 21605 | /*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake | ||
| 21606 | * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the | ||
| 21607 | * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset | ||
| 21608 | * is received. Software can use this bit to check if the remote wake-up feature is enabled by the | ||
| 21609 | * host for the LPM transaction. | ||
| 21610 | */ | ||
| 21611 | #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) | ||
| 21612 | #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) | ||
| 21613 | #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) | ||
| 21614 | /*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up | ||
| 21615 | * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. | ||
| 21616 | */ | ||
| 21617 | #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) | ||
| 21618 | #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) | ||
| 21619 | #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) | ||
| 21620 | /*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit | ||
| 21621 | * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The | ||
| 21622 | * device is disconnected - The device receives resume signaling on its upstream port. The bit is | ||
| 21623 | * reset by writing a one to it. | ||
| 21624 | */ | ||
| 21625 | #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) | ||
| 21626 | #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) | ||
| 21627 | #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) | ||
| 21628 | /*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On | ||
| 21629 | * a bus reset the device will automatically go to the default state (unconfigured and responding | ||
| 21630 | * to address 0). The bit is reset by writing a one to it. | ||
| 21631 | */ | ||
| 21632 | #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) | ||
| 21633 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) | ||
| 21634 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) | ||
| 21635 | /*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when | ||
| 21636 | * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and | ||
| 21637 | * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. | ||
| 21638 | */ | ||
| 21639 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) | ||
| 21640 | /*! @} */ | ||
| 21641 | |||
| 21642 | /*! @name INFO - USB Info register */ | ||
| 21643 | /*! @{ */ | ||
| 21644 | #define USB_INFO_FRAME_NR_MASK (0x7FFU) | ||
| 21645 | #define USB_INFO_FRAME_NR_SHIFT (0U) | ||
| 21646 | /*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. | ||
| 21647 | * In case no SOF was received by the device at the beginning of a frame, the frame number | ||
| 21648 | * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC | ||
| 21649 | * error, the frame number returned will be the corrupted frame number as received by the device. | ||
| 21650 | */ | ||
| 21651 | #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) | ||
| 21652 | #define USB_INFO_ERR_CODE_MASK (0x7800U) | ||
| 21653 | #define USB_INFO_ERR_CODE_SHIFT (11U) | ||
| 21654 | /*! ERR_CODE - The error code which last occurred: | ||
| 21655 | * 0b0000..No error | ||
| 21656 | * 0b0001..PID encoding error | ||
| 21657 | * 0b0010..PID unknown | ||
| 21658 | * 0b0011..Packet unexpected | ||
| 21659 | * 0b0100..Token CRC error | ||
| 21660 | * 0b0101..Data CRC error | ||
| 21661 | * 0b0110..Time out | ||
| 21662 | * 0b0111..Babble | ||
| 21663 | * 0b1000..Truncated EOP | ||
| 21664 | * 0b1001..Sent/Received NAK | ||
| 21665 | * 0b1010..Sent Stall | ||
| 21666 | * 0b1011..Overrun | ||
| 21667 | * 0b1100..Sent empty packet | ||
| 21668 | * 0b1101..Bitstuff error | ||
| 21669 | * 0b1110..Sync error | ||
| 21670 | * 0b1111..Wrong data toggle | ||
| 21671 | */ | ||
| 21672 | #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) | ||
| 21673 | #define USB_INFO_MINREV_MASK (0xFF0000U) | ||
| 21674 | #define USB_INFO_MINREV_SHIFT (16U) | ||
| 21675 | /*! MINREV - Minor Revision. | ||
| 21676 | */ | ||
| 21677 | #define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) | ||
| 21678 | #define USB_INFO_MAJREV_MASK (0xFF000000U) | ||
| 21679 | #define USB_INFO_MAJREV_SHIFT (24U) | ||
| 21680 | /*! MAJREV - Major Revision. | ||
| 21681 | */ | ||
| 21682 | #define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) | ||
| 21683 | /*! @} */ | ||