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1/*
2** ###################################################################
3** Processors: LPC5528JBD100
4** LPC5528JBD64
5** LPC5528JEV98
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
13** Version: rev. 1.1, 2019-05-16
14** Build: b200928
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for LPC5528
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 1.0 (2018-08-22)
30** Initial version based on v0.2UM
31** - rev. 1.1 (2019-05-16)
32** Initial A1 version based on v1.3UM
33**
34** ###################################################################
35*/
36
37/*!
38 * @file LPC5528.h
39 * @version 1.1
40 * @date 2019-05-16
41 * @brief CMSIS Peripheral Access Layer for LPC5528
42 *
43 * CMSIS Peripheral Access Layer for LPC5528
44 */
45
46#ifndef _LPC5528_H_
47#define _LPC5528_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0100U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
75 MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
76 BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
77 UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
78 SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
79 SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
80 DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
81 PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
82 SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
83
84 /* Device specific interrupts */
85 WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
86 DMA0_IRQn = 1, /**< DMA0 controller */
87 GINT0_IRQn = 2, /**< GPIO group 0 */
88 GINT1_IRQn = 3, /**< GPIO group 1 */
89 PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
90 PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
91 PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
92 PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
93 UTICK0_IRQn = 8, /**< Micro-tick Timer */
94 MRT0_IRQn = 9, /**< Multi-rate timer */
95 CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
96 CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
97 SCT0_IRQn = 12, /**< SCTimer/PWM */
98 CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
99 FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
100 FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
101 FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
102 FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
103 FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
104 FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
105 FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
106 FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
107 ADC0_IRQn = 22, /**< ADC0 */
108 Reserved39_IRQn = 23, /**< Reserved interrupt */
109 ACMP_IRQn = 24, /**< ACMP interrupts */
110 Reserved41_IRQn = 25, /**< Reserved interrupt */
111 Reserved42_IRQn = 26, /**< Reserved interrupt */
112 USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
113 USB0_IRQn = 28, /**< USB device */
114 RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
115 Reserved46_IRQn = 30, /**< Reserved interrupt */
116 Reserved47_IRQn = 31, /**< Reserved interrupt */
117 PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
118 PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
119 PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
120 PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
121 CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
122 CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
123 OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
124 Reserved55_IRQn = 39, /**< Reserved interrupt */
125 Reserved56_IRQn = 40, /**< Reserved interrupt */
126 Reserved57_IRQn = 41, /**< Reserved interrupt */
127 SDIO_IRQn = 42, /**< SD/MMC */
128 Reserved59_IRQn = 43, /**< Reserved interrupt */
129 Reserved60_IRQn = 44, /**< Reserved interrupt */
130 Reserved61_IRQn = 45, /**< Reserved interrupt */
131 USB1_PHY_IRQn = 46, /**< USB1_PHY */
132 USB1_IRQn = 47, /**< USB1 interrupt */
133 USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
134 SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
135 SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
136 SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
137 PLU_IRQn = 52, /**< PLU interrupt */
138 SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
139 Reserved70_IRQn = 54, /**< Reserved interrupt */
140 CASER_IRQn = 55, /**< CASPER interrupt */
141 Reserved72_IRQn = 56, /**< Reserved interrupt */
142 PQ_IRQn = 57, /**< PQ interrupt */
143 DMA1_IRQn = 58, /**< DMA1 interrupt */
144 FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
145} IRQn_Type;
146
147/*!
148 * @}
149 */ /* end of group Interrupt_vector_numbers */
150
151
152/* ----------------------------------------------------------------------------
153 -- Cortex M33 Core Configuration
154 ---------------------------------------------------------------------------- */
155
156/*!
157 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
158 * @{
159 */
160
161#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
162#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
163#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
164#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
165#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
166#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
167
168#include "core_cm33.h" /* Core Peripheral Access Layer */
169#include "system_LPC5528.h" /* Device specific configuration file */
170
171/*!
172 * @}
173 */ /* end of group Cortex_Core_Configuration */
174
175
176/* ----------------------------------------------------------------------------
177 -- Mapping Information
178 ---------------------------------------------------------------------------- */
179
180/*!
181 * @addtogroup Mapping_Information Mapping Information
182 * @{
183 */
184
185/** Mapping Information */
186/*!
187 * @addtogroup dma_request
188 * @{
189 */
190
191/*******************************************************************************
192 * Definitions
193 ******************************************************************************/
194
195/*!
196 * @brief Structure for the DMA hardware request
197 *
198 * Defines the structure for the DMA hardware request collections. The user can configure the
199 * hardware request to trigger the DMA transfer accordingly. The index
200 * of the hardware request varies according to the to SoC.
201 */
202typedef enum _dma_request_source
203{
204 kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
205 kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
206 kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
207 kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
208 kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
209 kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
210 kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
211 kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
212 kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
213 kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
214 kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
215 kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
216 kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
217 kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
218 kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
219 kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
220 kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
221 kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
222 kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
223 kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
224 kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
225 kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
226 kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
227 kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
228 kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
229 kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
230 kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
231 kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
232 kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
233 kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
234 kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
235} dma_request_source_t;
236
237/* @} */
238
239
240/*!
241 * @}
242 */ /* end of group Mapping_Information */
243
244
245/* ----------------------------------------------------------------------------
246 -- Device Peripheral Access Layer
247 ---------------------------------------------------------------------------- */
248
249/*!
250 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
251 * @{
252 */
253
254
255/*
256** Start of section using anonymous unions
257*/
258
259#if defined(__ARMCC_VERSION)
260 #if (__ARMCC_VERSION >= 6010050)
261 #pragma clang diagnostic push
262 #else
263 #pragma push
264 #pragma anon_unions
265 #endif
266#elif defined(__GNUC__)
267 /* anonymous unions are enabled by default */
268#elif defined(__IAR_SYSTEMS_ICC__)
269 #pragma language=extended
270#else
271 #error Not supported compiler type
272#endif
273
274/* ----------------------------------------------------------------------------
275 -- ADC Peripheral Access Layer
276 ---------------------------------------------------------------------------- */
277
278/*!
279 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
280 * @{
281 */
282
283/** ADC - Register Layout Typedef */
284typedef struct {
285 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
286 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
287 uint8_t RESERVED_0[8];
288 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
289 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
290 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
291 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
292 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
293 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
294 uint8_t RESERVED_1[12];
295 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
296 __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
297 uint8_t RESERVED_2[4];
298 __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
299 uint8_t RESERVED_3[92];
300 __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
301 __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
302 uint8_t RESERVED_4[8];
303 __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
304 __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
305 struct { /* offset: 0x100, array step: 0x8 */
306 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
307 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
308 } CMD[15];
309 uint8_t RESERVED_5[136];
310 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
311 uint8_t RESERVED_6[240];
312 __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
313 uint8_t RESERVED_7[248];
314 __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
315 uint8_t RESERVED_8[124];
316 __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
317 uint8_t RESERVED_9[2680];
318 __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */
319} ADC_Type;
320
321/* ----------------------------------------------------------------------------
322 -- ADC Register Masks
323 ---------------------------------------------------------------------------- */
324
325/*!
326 * @addtogroup ADC_Register_Masks ADC Register Masks
327 * @{
328 */
329
330/*! @name VERID - Version ID Register */
331/*! @{ */
332#define ADC_VERID_RES_MASK (0x1U)
333#define ADC_VERID_RES_SHIFT (0U)
334/*! RES - Resolution
335 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
336 * 0b1..Up to 16-bit differential/16-bit single ended resolution supported.
337 */
338#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
339#define ADC_VERID_DIFFEN_MASK (0x2U)
340#define ADC_VERID_DIFFEN_SHIFT (1U)
341/*! DIFFEN - Differential Supported
342 * 0b0..Differential operation not supported.
343 * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
344 */
345#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
346#define ADC_VERID_MVI_MASK (0x8U)
347#define ADC_VERID_MVI_SHIFT (3U)
348/*! MVI - Multi Vref Implemented
349 * 0b0..Single voltage reference high (VREFH) input supported.
350 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
351 */
352#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
353#define ADC_VERID_CSW_MASK (0x70U)
354#define ADC_VERID_CSW_SHIFT (4U)
355/*! CSW - Channel Scale Width
356 * 0b000..Channel scaling not supported.
357 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
358 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
359 */
360#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
361#define ADC_VERID_VR1RNGI_MASK (0x100U)
362#define ADC_VERID_VR1RNGI_SHIFT (8U)
363/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
364 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
365 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
366 */
367#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
368#define ADC_VERID_IADCKI_MASK (0x200U)
369#define ADC_VERID_IADCKI_SHIFT (9U)
370/*! IADCKI - Internal ADC Clock implemented
371 * 0b0..Internal clock source not implemented.
372 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
373 */
374#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
375#define ADC_VERID_CALOFSI_MASK (0x400U)
376#define ADC_VERID_CALOFSI_SHIFT (10U)
377/*! CALOFSI - Calibration Function Implemented
378 * 0b0..Calibration Not Implemented.
379 * 0b1..Calibration Implemented.
380 */
381#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
382#define ADC_VERID_NUM_SEC_MASK (0x800U)
383#define ADC_VERID_NUM_SEC_SHIFT (11U)
384/*! NUM_SEC - Number of Single Ended Outputs Supported
385 * 0b0..This design supports one single ended conversion at a time.
386 * 0b1..This design supports two simultanious single ended conversions.
387 */
388#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
389#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
390#define ADC_VERID_NUM_FIFO_SHIFT (12U)
391/*! NUM_FIFO - Number of FIFOs
392 * 0b000..N/A
393 * 0b001..This design supports one result FIFO.
394 * 0b010..This design supports two result FIFOs.
395 * 0b011..This design supports three result FIFOs.
396 * 0b100..This design supports four result FIFOs.
397 */
398#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
399#define ADC_VERID_MINOR_MASK (0xFF0000U)
400#define ADC_VERID_MINOR_SHIFT (16U)
401/*! MINOR - Minor Version Number
402 */
403#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
404#define ADC_VERID_MAJOR_MASK (0xFF000000U)
405#define ADC_VERID_MAJOR_SHIFT (24U)
406/*! MAJOR - Major Version Number
407 */
408#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
409/*! @} */
410
411/*! @name PARAM - Parameter Register */
412/*! @{ */
413#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
414#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
415/*! TRIG_NUM - Trigger Number
416 */
417#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
418#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
419#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
420/*! FIFOSIZE - Result FIFO Depth
421 * 0b00000001..Result FIFO depth = 1 dataword.
422 * 0b00000100..Result FIFO depth = 4 datawords.
423 * 0b00001000..Result FIFO depth = 8 datawords.
424 * 0b00010000..Result FIFO depth = 16 datawords.
425 * 0b00100000..Result FIFO depth = 32 datawords.
426 * 0b01000000..Result FIFO depth = 64 datawords.
427 */
428#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
429#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
430#define ADC_PARAM_CV_NUM_SHIFT (16U)
431/*! CV_NUM - Compare Value Number
432 */
433#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
434#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
435#define ADC_PARAM_CMD_NUM_SHIFT (24U)
436/*! CMD_NUM - Command Buffer Number
437 */
438#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
439/*! @} */
440
441/*! @name CTRL - ADC Control Register */
442/*! @{ */
443#define ADC_CTRL_ADCEN_MASK (0x1U)
444#define ADC_CTRL_ADCEN_SHIFT (0U)
445/*! ADCEN - ADC Enable
446 * 0b0..ADC is disabled.
447 * 0b1..ADC is enabled.
448 */
449#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
450#define ADC_CTRL_RST_MASK (0x2U)
451#define ADC_CTRL_RST_SHIFT (1U)
452/*! RST - Software Reset
453 * 0b0..ADC logic is not reset.
454 * 0b1..ADC logic is reset.
455 */
456#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
457#define ADC_CTRL_DOZEN_MASK (0x4U)
458#define ADC_CTRL_DOZEN_SHIFT (2U)
459/*! DOZEN - Doze Enable
460 * 0b0..ADC is enabled in Doze mode.
461 * 0b1..ADC is disabled in Doze mode.
462 */
463#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
464#define ADC_CTRL_CAL_REQ_MASK (0x8U)
465#define ADC_CTRL_CAL_REQ_SHIFT (3U)
466/*! CAL_REQ - Auto-Calibration Request
467 * 0b0..No request for auto-calibration has been made.
468 * 0b1..A request for auto-calibration has been made
469 */
470#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
471#define ADC_CTRL_CALOFS_MASK (0x10U)
472#define ADC_CTRL_CALOFS_SHIFT (4U)
473/*! CALOFS - Configure for offset calibration function
474 * 0b0..Calibration function disabled
475 * 0b1..Request for offset calibration function
476 */
477#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
478#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
479#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
480/*! RSTFIFO0 - Reset FIFO 0
481 * 0b0..No effect.
482 * 0b1..FIFO 0 is reset.
483 */
484#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
485#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
486#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
487/*! RSTFIFO1 - Reset FIFO 1
488 * 0b0..No effect.
489 * 0b1..FIFO 1 is reset.
490 */
491#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
492#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
493#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
494/*! CAL_AVGS - Auto-Calibration Averages
495 * 0b000..Single conversion.
496 * 0b001..2 conversions averaged.
497 * 0b010..4 conversions averaged.
498 * 0b011..8 conversions averaged.
499 * 0b100..16 conversions averaged.
500 * 0b101..32 conversions averaged.
501 * 0b110..64 conversions averaged.
502 * 0b111..128 conversions averaged.
503 */
504#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
505/*! @} */
506
507/*! @name STAT - ADC Status Register */
508/*! @{ */
509#define ADC_STAT_RDY0_MASK (0x1U)
510#define ADC_STAT_RDY0_SHIFT (0U)
511/*! RDY0 - Result FIFO 0 Ready Flag
512 * 0b0..Result FIFO 0 data level not above watermark level.
513 * 0b1..Result FIFO 0 holding data above watermark level.
514 */
515#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
516#define ADC_STAT_FOF0_MASK (0x2U)
517#define ADC_STAT_FOF0_SHIFT (1U)
518/*! FOF0 - Result FIFO 0 Overflow Flag
519 * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
520 * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
521 */
522#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
523#define ADC_STAT_RDY1_MASK (0x4U)
524#define ADC_STAT_RDY1_SHIFT (2U)
525/*! RDY1 - Result FIFO1 Ready Flag
526 * 0b0..Result FIFO1 data level not above watermark level.
527 * 0b1..Result FIFO1 holding data above watermark level.
528 */
529#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
530#define ADC_STAT_FOF1_MASK (0x8U)
531#define ADC_STAT_FOF1_SHIFT (3U)
532/*! FOF1 - Result FIFO1 Overflow Flag
533 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
534 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
535 */
536#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
537#define ADC_STAT_TEXC_INT_MASK (0x100U)
538#define ADC_STAT_TEXC_INT_SHIFT (8U)
539/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
540 * 0b0..No trigger exceptions have occurred.
541 * 0b1..A trigger exception has occurred and is pending acknowledgement.
542 */
543#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
544#define ADC_STAT_TCOMP_INT_MASK (0x200U)
545#define ADC_STAT_TCOMP_INT_SHIFT (9U)
546/*! TCOMP_INT - Interrupt Flag For Trigger Completion
547 * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
548 * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
549 */
550#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
551#define ADC_STAT_CAL_RDY_MASK (0x400U)
552#define ADC_STAT_CAL_RDY_SHIFT (10U)
553/*! CAL_RDY - Calibration Ready
554 * 0b0..Calibration is incomplete or hasn't been ran.
555 * 0b1..The ADC is calibrated.
556 */
557#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
558#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
559#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
560/*! ADC_ACTIVE - ADC Active
561 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
562 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
563 */
564#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
565#define ADC_STAT_TRGACT_MASK (0xF0000U)
566#define ADC_STAT_TRGACT_SHIFT (16U)
567/*! TRGACT - Trigger Active
568 * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
569 * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
570 * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
571 * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
572 */
573#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
574#define ADC_STAT_CMDACT_MASK (0xF000000U)
575#define ADC_STAT_CMDACT_SHIFT (24U)
576/*! CMDACT - Command Active
577 * 0b0000..No command is currently in progress.
578 * 0b0001..Command 1 currently being executed.
579 * 0b0010..Command 2 currently being executed.
580 * 0b0011-0b1111..Associated command number is currently being executed.
581 */
582#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
583/*! @} */
584
585/*! @name IE - Interrupt Enable Register */
586/*! @{ */
587#define ADC_IE_FWMIE0_MASK (0x1U)
588#define ADC_IE_FWMIE0_SHIFT (0U)
589/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
590 * 0b0..FIFO 0 watermark interrupts are not enabled.
591 * 0b1..FIFO 0 watermark interrupts are enabled.
592 */
593#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
594#define ADC_IE_FOFIE0_MASK (0x2U)
595#define ADC_IE_FOFIE0_SHIFT (1U)
596/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
597 * 0b0..FIFO 0 overflow interrupts are not enabled.
598 * 0b1..FIFO 0 overflow interrupts are enabled.
599 */
600#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
601#define ADC_IE_FWMIE1_MASK (0x4U)
602#define ADC_IE_FWMIE1_SHIFT (2U)
603/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
604 * 0b0..FIFO1 watermark interrupts are not enabled.
605 * 0b1..FIFO1 watermark interrupts are enabled.
606 */
607#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
608#define ADC_IE_FOFIE1_MASK (0x8U)
609#define ADC_IE_FOFIE1_SHIFT (3U)
610/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
611 * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
612 * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
613 */
614#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
615#define ADC_IE_TEXC_IE_MASK (0x100U)
616#define ADC_IE_TEXC_IE_SHIFT (8U)
617/*! TEXC_IE - Trigger Exception Interrupt Enable
618 * 0b0..Trigger exception interrupts are disabled.
619 * 0b1..Trigger exception interrupts are enabled.
620 */
621#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
622#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
623#define ADC_IE_TCOMP_IE_SHIFT (16U)
624/*! TCOMP_IE - Trigger Completion Interrupt Enable
625 * 0b0000000000000000..Trigger completion interrupts are disabled.
626 * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
627 * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
628 * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
629 * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
630 */
631#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
632/*! @} */
633
634/*! @name DE - DMA Enable Register */
635/*! @{ */
636#define ADC_DE_FWMDE0_MASK (0x1U)
637#define ADC_DE_FWMDE0_SHIFT (0U)
638/*! FWMDE0 - FIFO 0 Watermark DMA Enable
639 * 0b0..DMA request disabled.
640 * 0b1..DMA request enabled.
641 */
642#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
643#define ADC_DE_FWMDE1_MASK (0x2U)
644#define ADC_DE_FWMDE1_SHIFT (1U)
645/*! FWMDE1 - FIFO1 Watermark DMA Enable
646 * 0b0..DMA request disabled.
647 * 0b1..DMA request enabled.
648 */
649#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
650/*! @} */
651
652/*! @name CFG - ADC Configuration Register */
653/*! @{ */
654#define ADC_CFG_TPRICTRL_MASK (0x3U)
655#define ADC_CFG_TPRICTRL_SHIFT (0U)
656/*! TPRICTRL - ADC trigger priority control
657 * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
658 * and the new command specified by the trigger is started.
659 * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after
660 * after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
661 * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
662 * 0b10..If a higher priority trigger is received during command processing, the current command will be
663 * completed (averaging, looping, compare) before servicing the higher priority trigger.
664 * 0b11..RESERVED
665 */
666#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
667#define ADC_CFG_PWRSEL_MASK (0x30U)
668#define ADC_CFG_PWRSEL_SHIFT (4U)
669/*! PWRSEL - Power Configuration Select
670 * 0b00..Lowest power setting.
671 * 0b01..Higher power setting than 0b0.
672 * 0b10..Higher power setting than 0b1.
673 * 0b11..Highest power setting.
674 */
675#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
676#define ADC_CFG_REFSEL_MASK (0xC0U)
677#define ADC_CFG_REFSEL_SHIFT (6U)
678/*! REFSEL - Voltage Reference Selection
679 * 0b00..(Default) Option 1 setting.
680 * 0b01..Option 2 setting.
681 * 0b10..Option 3 setting.
682 * 0b11..Reserved
683 */
684#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
685#define ADC_CFG_TRES_MASK (0x100U)
686#define ADC_CFG_TRES_SHIFT (8U)
687/*! TRES - Trigger Resume Enable
688 * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
689 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
690 */
691#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
692#define ADC_CFG_TCMDRES_MASK (0x200U)
693#define ADC_CFG_TCMDRES_SHIFT (9U)
694/*! TCMDRES - Trigger Command Resume
695 * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
696 * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
697 */
698#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
699#define ADC_CFG_HPT_EXDI_MASK (0x400U)
700#define ADC_CFG_HPT_EXDI_SHIFT (10U)
701/*! HPT_EXDI - High Priority Trigger Exception Disable
702 * 0b0..High priority trigger exceptions are enabled.
703 * 0b1..High priority trigger exceptions are disabled.
704 */
705#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
706#define ADC_CFG_PUDLY_MASK (0xFF0000U)
707#define ADC_CFG_PUDLY_SHIFT (16U)
708/*! PUDLY - Power Up Delay
709 */
710#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
711#define ADC_CFG_PWREN_MASK (0x10000000U)
712#define ADC_CFG_PWREN_SHIFT (28U)
713/*! PWREN - ADC Analog Pre-Enable
714 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
715 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
716 * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
717 * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
718 * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
719 * executed.
720 */
721#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
722/*! @} */
723
724/*! @name PAUSE - ADC Pause Register */
725/*! @{ */
726#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
727#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
728/*! PAUSEDLY - Pause Delay
729 */
730#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
731#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
732#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
733/*! PAUSEEN - PAUSE Option Enable
734 * 0b0..Pause operation disabled
735 * 0b1..Pause operation enabled
736 */
737#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
738/*! @} */
739
740/*! @name SWTRIG - Software Trigger Register */
741/*! @{ */
742#define ADC_SWTRIG_SWT0_MASK (0x1U)
743#define ADC_SWTRIG_SWT0_SHIFT (0U)
744/*! SWT0 - Software trigger 0 event
745 * 0b0..No trigger 0 event generated.
746 * 0b1..Trigger 0 event generated.
747 */
748#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
749#define ADC_SWTRIG_SWT1_MASK (0x2U)
750#define ADC_SWTRIG_SWT1_SHIFT (1U)
751/*! SWT1 - Software trigger 1 event
752 * 0b0..No trigger 1 event generated.
753 * 0b1..Trigger 1 event generated.
754 */
755#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
756#define ADC_SWTRIG_SWT2_MASK (0x4U)
757#define ADC_SWTRIG_SWT2_SHIFT (2U)
758/*! SWT2 - Software trigger 2 event
759 * 0b0..No trigger 2 event generated.
760 * 0b1..Trigger 2 event generated.
761 */
762#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
763#define ADC_SWTRIG_SWT3_MASK (0x8U)
764#define ADC_SWTRIG_SWT3_SHIFT (3U)
765/*! SWT3 - Software trigger 3 event
766 * 0b0..No trigger 3 event generated.
767 * 0b1..Trigger 3 event generated.
768 */
769#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
770#define ADC_SWTRIG_SWT4_MASK (0x10U)
771#define ADC_SWTRIG_SWT4_SHIFT (4U)
772/*! SWT4 - Software trigger 4 event
773 * 0b0..No trigger 4 event generated.
774 * 0b1..Trigger 4 event generated.
775 */
776#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
777#define ADC_SWTRIG_SWT5_MASK (0x20U)
778#define ADC_SWTRIG_SWT5_SHIFT (5U)
779/*! SWT5 - Software trigger 5 event
780 * 0b0..No trigger 5 event generated.
781 * 0b1..Trigger 5 event generated.
782 */
783#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
784#define ADC_SWTRIG_SWT6_MASK (0x40U)
785#define ADC_SWTRIG_SWT6_SHIFT (6U)
786/*! SWT6 - Software trigger 6 event
787 * 0b0..No trigger 6 event generated.
788 * 0b1..Trigger 6 event generated.
789 */
790#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
791#define ADC_SWTRIG_SWT7_MASK (0x80U)
792#define ADC_SWTRIG_SWT7_SHIFT (7U)
793/*! SWT7 - Software trigger 7 event
794 * 0b0..No trigger 7 event generated.
795 * 0b1..Trigger 7 event generated.
796 */
797#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
798#define ADC_SWTRIG_SWT8_MASK (0x100U)
799#define ADC_SWTRIG_SWT8_SHIFT (8U)
800/*! SWT8 - Software trigger 8 event
801 * 0b0..No trigger 8 event generated.
802 * 0b1..Trigger 8 event generated.
803 */
804#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
805#define ADC_SWTRIG_SWT9_MASK (0x200U)
806#define ADC_SWTRIG_SWT9_SHIFT (9U)
807/*! SWT9 - Software trigger 9 event
808 * 0b0..No trigger 9 event generated.
809 * 0b1..Trigger 9 event generated.
810 */
811#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
812#define ADC_SWTRIG_SWT10_MASK (0x400U)
813#define ADC_SWTRIG_SWT10_SHIFT (10U)
814/*! SWT10 - Software trigger 10 event
815 * 0b0..No trigger 10 event generated.
816 * 0b1..Trigger 10 event generated.
817 */
818#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
819#define ADC_SWTRIG_SWT11_MASK (0x800U)
820#define ADC_SWTRIG_SWT11_SHIFT (11U)
821/*! SWT11 - Software trigger 11 event
822 * 0b0..No trigger 11 event generated.
823 * 0b1..Trigger 11 event generated.
824 */
825#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
826#define ADC_SWTRIG_SWT12_MASK (0x1000U)
827#define ADC_SWTRIG_SWT12_SHIFT (12U)
828/*! SWT12 - Software trigger 12 event
829 * 0b0..No trigger 12 event generated.
830 * 0b1..Trigger 12 event generated.
831 */
832#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
833#define ADC_SWTRIG_SWT13_MASK (0x2000U)
834#define ADC_SWTRIG_SWT13_SHIFT (13U)
835/*! SWT13 - Software trigger 13 event
836 * 0b0..No trigger 13 event generated.
837 * 0b1..Trigger 13 event generated.
838 */
839#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
840#define ADC_SWTRIG_SWT14_MASK (0x4000U)
841#define ADC_SWTRIG_SWT14_SHIFT (14U)
842/*! SWT14 - Software trigger 14 event
843 * 0b0..No trigger 14 event generated.
844 * 0b1..Trigger 14 event generated.
845 */
846#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
847#define ADC_SWTRIG_SWT15_MASK (0x8000U)
848#define ADC_SWTRIG_SWT15_SHIFT (15U)
849/*! SWT15 - Software trigger 15 event
850 * 0b0..No trigger 15 event generated.
851 * 0b1..Trigger 15 event generated.
852 */
853#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
854/*! @} */
855
856/*! @name TSTAT - Trigger Status Register */
857/*! @{ */
858#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
859#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
860/*! TEXC_NUM - Trigger Exception Number
861 * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
862 * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
863 * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
864 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
865 * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
866 */
867#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
868#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
869#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
870/*! TCOMP_FLAG - Trigger Completion Flag
871 * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
872 * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
873 * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
874 * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
875 * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
876 */
877#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
878/*! @} */
879
880/*! @name OFSTRIM - ADC Offset Trim Register */
881/*! @{ */
882#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
883#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
884/*! OFSTRIM_A - Trim for offset
885 */
886#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
887#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
888#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
889/*! OFSTRIM_B - Trim for offset
890 */
891#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
892/*! @} */
893
894/*! @name TCTRL - Trigger Control Register */
895/*! @{ */
896#define ADC_TCTRL_HTEN_MASK (0x1U)
897#define ADC_TCTRL_HTEN_SHIFT (0U)
898/*! HTEN - Trigger enable
899 * 0b0..Hardware trigger source disabled
900 * 0b1..Hardware trigger source enabled
901 */
902#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
903#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
904#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
905/*! FIFO_SEL_A - SAR Result Destination For Channel A
906 * 0b0..Result written to FIFO 0
907 * 0b1..Result written to FIFO 1
908 */
909#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
910#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
911#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
912/*! FIFO_SEL_B - SAR Result Destination For Channel B
913 * 0b0..Result written to FIFO 0
914 * 0b1..Result written to FIFO 1
915 */
916#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
917#define ADC_TCTRL_TPRI_MASK (0xF00U)
918#define ADC_TCTRL_TPRI_SHIFT (8U)
919/*! TPRI - Trigger priority setting
920 * 0b0000..Set to highest priority, Level 1
921 * 0b0001-0b1110..Set to corresponding priority level
922 * 0b1111..Set to lowest priority, Level 16
923 */
924#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
925#define ADC_TCTRL_RSYNC_MASK (0x8000U)
926#define ADC_TCTRL_RSYNC_SHIFT (15U)
927/*! RSYNC - Trigger Resync
928 */
929#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
930#define ADC_TCTRL_TDLY_MASK (0xF0000U)
931#define ADC_TCTRL_TDLY_SHIFT (16U)
932/*! TDLY - Trigger delay select
933 */
934#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
935#define ADC_TCTRL_TCMD_MASK (0xF000000U)
936#define ADC_TCTRL_TCMD_SHIFT (24U)
937/*! TCMD - Trigger command select
938 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
939 * 0b0001..CMD1 is executed
940 * 0b0010-0b1110..Corresponding CMD is executed
941 * 0b1111..CMD15 is executed
942 */
943#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
944/*! @} */
945
946/* The count of ADC_TCTRL */
947#define ADC_TCTRL_COUNT (16U)
948
949/*! @name FCTRL - FIFO Control Register */
950/*! @{ */
951#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
952#define ADC_FCTRL_FCOUNT_SHIFT (0U)
953/*! FCOUNT - Result FIFO counter
954 */
955#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
956#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
957#define ADC_FCTRL_FWMARK_SHIFT (16U)
958/*! FWMARK - Watermark level selection
959 */
960#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
961/*! @} */
962
963/* The count of ADC_FCTRL */
964#define ADC_FCTRL_COUNT (2U)
965
966/*! @name GCC - Gain Calibration Control */
967/*! @{ */
968#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
969#define ADC_GCC_GAIN_CAL_SHIFT (0U)
970/*! GAIN_CAL - Gain Calibration Value
971 */
972#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
973#define ADC_GCC_RDY_MASK (0x1000000U)
974#define ADC_GCC_RDY_SHIFT (24U)
975/*! RDY - Gain Calibration Value Valid
976 * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
977 * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
978 */
979#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
980/*! @} */
981
982/* The count of ADC_GCC */
983#define ADC_GCC_COUNT (2U)
984
985/*! @name GCR - Gain Calculation Result */
986/*! @{ */
987#define ADC_GCR_GCALR_MASK (0xFFFFU)
988#define ADC_GCR_GCALR_SHIFT (0U)
989/*! GCALR - Gain Calculation Result
990 */
991#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
992#define ADC_GCR_RDY_MASK (0x1000000U)
993#define ADC_GCR_RDY_SHIFT (24U)
994/*! RDY - Gain Calculation Ready
995 * 0b0..The gain offset calculation value is invalid.
996 * 0b1..The gain calibration value is valid.
997 */
998#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
999/*! @} */
1000
1001/* The count of ADC_GCR */
1002#define ADC_GCR_COUNT (2U)
1003
1004/*! @name CMDL - ADC Command Low Buffer Register */
1005/*! @{ */
1006#define ADC_CMDL_ADCH_MASK (0x1FU)
1007#define ADC_CMDL_ADCH_SHIFT (0U)
1008/*! ADCH - Input channel select
1009 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1010 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1011 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1012 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1013 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1014 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1015 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1016 */
1017#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1018#define ADC_CMDL_CTYPE_MASK (0x60U)
1019#define ADC_CMDL_CTYPE_SHIFT (5U)
1020/*! CTYPE - Conversion Type
1021 * 0b00..Single-Ended Mode. Only A side channel is converted.
1022 * 0b01..Single-Ended Mode. Only B side channel is converted.
1023 * 0b10..Differential Mode. A-B.
1024 * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
1025 */
1026#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
1027#define ADC_CMDL_MODE_MASK (0x80U)
1028#define ADC_CMDL_MODE_SHIFT (7U)
1029/*! MODE - Select resolution of conversions
1030 * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
1031 * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
1032 */
1033#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
1034/*! @} */
1035
1036/* The count of ADC_CMDL */
1037#define ADC_CMDL_COUNT (15U)
1038
1039/*! @name CMDH - ADC Command High Buffer Register */
1040/*! @{ */
1041#define ADC_CMDH_CMPEN_MASK (0x3U)
1042#define ADC_CMDH_CMPEN_SHIFT (0U)
1043/*! CMPEN - Compare Function Enable
1044 * 0b00..Compare disabled.
1045 * 0b01..Reserved
1046 * 0b10..Compare enabled. Store on true.
1047 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1048 */
1049#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1050#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
1051#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
1052/*! WAIT_TRIG - Wait for trigger assertion before execution.
1053 * 0b0..This command will be automatically executed.
1054 * 0b1..The active trigger must be asserted again before executing this command.
1055 */
1056#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
1057#define ADC_CMDH_LWI_MASK (0x80U)
1058#define ADC_CMDH_LWI_SHIFT (7U)
1059/*! LWI - Loop with Increment
1060 * 0b0..Auto channel increment disabled
1061 * 0b1..Auto channel increment enabled
1062 */
1063#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1064#define ADC_CMDH_STS_MASK (0x700U)
1065#define ADC_CMDH_STS_SHIFT (8U)
1066/*! STS - Sample Time Select
1067 * 0b000..Minimum sample time of 3 ADCK cycles.
1068 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1069 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1070 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1071 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1072 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1073 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1074 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1075 */
1076#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1077#define ADC_CMDH_AVGS_MASK (0x7000U)
1078#define ADC_CMDH_AVGS_SHIFT (12U)
1079/*! AVGS - Hardware Average Select
1080 * 0b000..Single conversion.
1081 * 0b001..2 conversions averaged.
1082 * 0b010..4 conversions averaged.
1083 * 0b011..8 conversions averaged.
1084 * 0b100..16 conversions averaged.
1085 * 0b101..32 conversions averaged.
1086 * 0b110..64 conversions averaged.
1087 * 0b111..128 conversions averaged.
1088 */
1089#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1090#define ADC_CMDH_LOOP_MASK (0xF0000U)
1091#define ADC_CMDH_LOOP_SHIFT (16U)
1092/*! LOOP - Loop Count Select
1093 * 0b0000..Looping not enabled. Command executes 1 time.
1094 * 0b0001..Loop 1 time. Command executes 2 times.
1095 * 0b0010..Loop 2 times. Command executes 3 times.
1096 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1097 * 0b1111..Loop 15 times. Command executes 16 times.
1098 */
1099#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1100#define ADC_CMDH_NEXT_MASK (0xF000000U)
1101#define ADC_CMDH_NEXT_SHIFT (24U)
1102/*! NEXT - Next Command Select
1103 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1104 * trigger pending, begin command associated with lower priority trigger.
1105 * 0b0001..Select CMD1 command buffer register as next command.
1106 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1107 * 0b1111..Select CMD15 command buffer register as next command.
1108 */
1109#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1110/*! @} */
1111
1112/* The count of ADC_CMDH */
1113#define ADC_CMDH_COUNT (15U)
1114
1115/*! @name CV - Compare Value Register */
1116/*! @{ */
1117#define ADC_CV_CVL_MASK (0xFFFFU)
1118#define ADC_CV_CVL_SHIFT (0U)
1119/*! CVL - Compare Value Low.
1120 */
1121#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1122#define ADC_CV_CVH_MASK (0xFFFF0000U)
1123#define ADC_CV_CVH_SHIFT (16U)
1124/*! CVH - Compare Value High.
1125 */
1126#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1127/*! @} */
1128
1129/* The count of ADC_CV */
1130#define ADC_CV_COUNT (4U)
1131
1132/*! @name RESFIFO - ADC Data Result FIFO Register */
1133/*! @{ */
1134#define ADC_RESFIFO_D_MASK (0xFFFFU)
1135#define ADC_RESFIFO_D_SHIFT (0U)
1136/*! D - Data result
1137 */
1138#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1139#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
1140#define ADC_RESFIFO_TSRC_SHIFT (16U)
1141/*! TSRC - Trigger Source
1142 * 0b0000..Trigger source 0 initiated this conversion.
1143 * 0b0001..Trigger source 1 initiated this conversion.
1144 * 0b0010-0b1110..Corresponding trigger source initiated this conversion.
1145 * 0b1111..Trigger source 15 initiated this conversion.
1146 */
1147#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1148#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1149#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1150/*! LOOPCNT - Loop count value
1151 * 0b0000..Result is from initial conversion in command.
1152 * 0b0001..Result is from second conversion in command.
1153 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1154 * 0b1111..Result is from 16th conversion in command.
1155 */
1156#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1157#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1158#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1159/*! CMDSRC - Command Buffer Source
1160 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1161 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1162 * 0b0001..CMD1 buffer used as control settings for this conversion.
1163 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1164 * 0b1111..CMD15 buffer used as control settings for this conversion.
1165 */
1166#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1167#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1168#define ADC_RESFIFO_VALID_SHIFT (31U)
1169/*! VALID - FIFO entry is valid
1170 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1171 * 0b1..FIFO record read from RESFIFO is valid.
1172 */
1173#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1174/*! @} */
1175
1176/* The count of ADC_RESFIFO */
1177#define ADC_RESFIFO_COUNT (2U)
1178
1179/*! @name CAL_GAR - Calibration General A-Side Registers */
1180/*! @{ */
1181#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
1182#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
1183/*! CAL_GAR_VAL - Calibration General A Side Register Element
1184 */
1185#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
1186/*! @} */
1187
1188/* The count of ADC_CAL_GAR */
1189#define ADC_CAL_GAR_COUNT (33U)
1190
1191/*! @name CAL_GBR - Calibration General B-Side Registers */
1192/*! @{ */
1193#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
1194#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
1195/*! CAL_GBR_VAL - Calibration General B Side Register Element
1196 */
1197#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
1198/*! @} */
1199
1200/* The count of ADC_CAL_GBR */
1201#define ADC_CAL_GBR_COUNT (33U)
1202
1203/*! @name TST - ADC Test Register */
1204/*! @{ */
1205#define ADC_TST_CST_LONG_MASK (0x1U)
1206#define ADC_TST_CST_LONG_SHIFT (0U)
1207/*! CST_LONG - Calibration Sample Time Long
1208 * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.
1209 * 0b1..Increased sample time. 67 ADCK cycles total sample time.
1210 */
1211#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
1212#define ADC_TST_FOFFM_MASK (0x100U)
1213#define ADC_TST_FOFFM_SHIFT (8U)
1214/*! FOFFM - Force M-side positive offset
1215 * 0b0..Normal operation. No forced offset.
1216 * 0b1..Test configuration. Forced positive offset on MDAC.
1217 */
1218#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
1219#define ADC_TST_FOFFP_MASK (0x200U)
1220#define ADC_TST_FOFFP_SHIFT (9U)
1221/*! FOFFP - Force P-side positive offset
1222 * 0b0..Normal operation. No forced offset.
1223 * 0b1..Test configuration. Forced positive offset on PDAC.
1224 */
1225#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
1226#define ADC_TST_FOFFM2_MASK (0x400U)
1227#define ADC_TST_FOFFM2_SHIFT (10U)
1228/*! FOFFM2 - Force M-side negative offset
1229 * 0b0..Normal operation. No forced offset.
1230 * 0b1..Test configuration. Forced negative offset on MDAC.
1231 */
1232#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
1233#define ADC_TST_FOFFP2_MASK (0x800U)
1234#define ADC_TST_FOFFP2_SHIFT (11U)
1235/*! FOFFP2 - Force P-side negative offset
1236 * 0b0..Normal operation. No forced offset.
1237 * 0b1..Test configuration. Forced negative offset on PDAC.
1238 */
1239#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
1240#define ADC_TST_TESTEN_MASK (0x800000U)
1241#define ADC_TST_TESTEN_SHIFT (23U)
1242/*! TESTEN - Enable test configuration
1243 * 0b0..Normal operation. Test configuration not enabled.
1244 * 0b1..Hardware BIST Test in progress.
1245 */
1246#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
1247/*! @} */
1248
1249
1250/*!
1251 * @}
1252 */ /* end of group ADC_Register_Masks */
1253
1254
1255/* ADC - Peripheral instance base addresses */
1256#if (__ARM_FEATURE_CMSE & 0x2)
1257 /** Peripheral ADC0 base address */
1258 #define ADC0_BASE (0x500A0000u)
1259 /** Peripheral ADC0 base address */
1260 #define ADC0_BASE_NS (0x400A0000u)
1261 /** Peripheral ADC0 base pointer */
1262 #define ADC0 ((ADC_Type *)ADC0_BASE)
1263 /** Peripheral ADC0 base pointer */
1264 #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
1265 /** Array initializer of ADC peripheral base addresses */
1266 #define ADC_BASE_ADDRS { ADC0_BASE }
1267 /** Array initializer of ADC peripheral base pointers */
1268 #define ADC_BASE_PTRS { ADC0 }
1269 /** Array initializer of ADC peripheral base addresses */
1270 #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
1271 /** Array initializer of ADC peripheral base pointers */
1272 #define ADC_BASE_PTRS_NS { ADC0_NS }
1273#else
1274 /** Peripheral ADC0 base address */
1275 #define ADC0_BASE (0x400A0000u)
1276 /** Peripheral ADC0 base pointer */
1277 #define ADC0 ((ADC_Type *)ADC0_BASE)
1278 /** Array initializer of ADC peripheral base addresses */
1279 #define ADC_BASE_ADDRS { ADC0_BASE }
1280 /** Array initializer of ADC peripheral base pointers */
1281 #define ADC_BASE_PTRS { ADC0 }
1282#endif
1283/** Interrupt vectors for the ADC peripheral type */
1284#define ADC_IRQS { ADC0_IRQn }
1285
1286/*!
1287 * @}
1288 */ /* end of group ADC_Peripheral_Access_Layer */
1289
1290
1291/* ----------------------------------------------------------------------------
1292 -- AHB_SECURE_CTRL Peripheral Access Layer
1293 ---------------------------------------------------------------------------- */
1294
1295/*!
1296 * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer
1297 * @{
1298 */
1299
1300/** AHB_SECURE_CTRL - Register Layout Typedef */
1301typedef struct {
1302 struct { /* offset: 0x0, array step: 0x30 */
1303 __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
1304 uint8_t RESERVED_0[12];
1305 __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
1306 uint8_t RESERVED_1[4];
1307 __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
1308 } SEC_CTRL_FLASH_ROM[1];
1309 struct { /* offset: 0x30, array step: 0x14 */
1310 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
1311 uint8_t RESERVED_0[12];
1312 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
1313 } SEC_CTRL_RAMX[1];
1314 uint8_t RESERVED_0[12];
1315 struct { /* offset: 0x50, array step: 0x18 */
1316 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
1317 uint8_t RESERVED_0[12];
1318 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */
1319 } SEC_CTRL_RAM0[1];
1320 uint8_t RESERVED_1[8];
1321 struct { /* offset: 0x70, array step: 0x18 */
1322 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
1323 uint8_t RESERVED_0[12];
1324 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */
1325 } SEC_CTRL_RAM1[1];
1326 uint8_t RESERVED_2[8];
1327 struct { /* offset: 0x90, array step: 0x18 */
1328 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
1329 uint8_t RESERVED_0[12];
1330 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */
1331 } SEC_CTRL_RAM2[1];
1332 uint8_t RESERVED_3[8];
1333 struct { /* offset: 0xB0, array step: 0x18 */
1334 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
1335 uint8_t RESERVED_0[12];
1336 __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */
1337 } SEC_CTRL_RAM3[1];
1338 uint8_t RESERVED_4[8];
1339 struct { /* offset: 0xD0, array step: 0x14 */
1340 __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
1341 uint8_t RESERVED_0[12];
1342 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */
1343 } SEC_CTRL_RAM4[1];
1344 uint8_t RESERVED_5[12];
1345 struct { /* offset: 0xF0, array step: 0x30 */
1346 __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
1347 uint8_t RESERVED_0[12];
1348 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */
1349 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */
1350 __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */
1351 uint8_t RESERVED_1[4];
1352 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */
1353 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */
1354 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */
1355 __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */
1356 } SEC_CTRL_APB_BRIDGE[1];
1357 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */
1358 __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */
1359 uint8_t RESERVED_6[8];
1360 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */
1361 __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */
1362 uint8_t RESERVED_7[8];
1363 struct { /* offset: 0x140, array step: 0x14 */
1364 __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
1365 __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
1366 uint8_t RESERVED_0[8];
1367 __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */
1368 } SEC_CTRL_AHB_PORT10[1];
1369 uint8_t RESERVED_8[12];
1370 struct { /* offset: 0x160, array step: 0x14 */
1371 __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */
1372 uint8_t RESERVED_0[12];
1373 __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */
1374 } SEC_CTRL_USB_HS[1];
1375 uint8_t RESERVED_9[3212];
1376 __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */
1377 uint8_t RESERVED_10[80];
1378 __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */
1379 uint8_t RESERVED_11[80];
1380 __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
1381 uint8_t RESERVED_12[124];
1382 __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
1383 __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
1384 uint8_t RESERVED_13[8];
1385 __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
1386 __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
1387 uint8_t RESERVED_14[36];
1388 __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
1389 uint8_t RESERVED_15[16];
1390 __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
1391 __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
1392 uint8_t RESERVED_16[20];
1393 __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
1394 __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
1395 uint8_t RESERVED_17[4];
1396 __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
1397 __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
1398} AHB_SECURE_CTRL_Type;
1399
1400/* ----------------------------------------------------------------------------
1401 -- AHB_SECURE_CTRL Register Masks
1402 ---------------------------------------------------------------------------- */
1403
1404/*!
1405 * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks
1406 * @{
1407 */
1408
1409/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
1410/*! @{ */
1411#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
1412#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
1413/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
1414 * 0b00..Non-secure and Non-priviledge user access allowed.
1415 * 0b01..Non-secure and Privilege access allowed.
1416 * 0b10..Secure and Non-priviledge user access allowed.
1417 * 0b11..Secure and Priviledge user access allowed.
1418 */
1419#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
1420#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
1421#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
1422/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
1423 * 0b00..Non-secure and Non-priviledge user access allowed.
1424 * 0b01..Non-secure and Privilege access allowed.
1425 * 0b10..Secure and Non-priviledge user access allowed.
1426 * 0b11..Secure and Priviledge user access allowed.
1427 */
1428#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
1429/*! @} */
1430
1431/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
1432#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
1433
1434/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */
1435/*! @{ */
1436#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
1437#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
1438/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1439 * 0b00..Non-secure and Non-priviledge user access allowed.
1440 * 0b01..Non-secure and Privilege access allowed.
1441 * 0b10..Secure and Non-priviledge user access allowed.
1442 * 0b11..Secure and Priviledge user access allowed.
1443 */
1444#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
1445#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
1446#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
1447/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1448 * 0b00..Non-secure and Non-priviledge user access allowed.
1449 * 0b01..Non-secure and Privilege access allowed.
1450 * 0b10..Secure and Non-priviledge user access allowed.
1451 * 0b11..Secure and Priviledge user access allowed.
1452 */
1453#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
1454#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
1455#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
1456/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1457 * 0b00..Non-secure and Non-priviledge user access allowed.
1458 * 0b01..Non-secure and Privilege access allowed.
1459 * 0b10..Secure and Non-priviledge user access allowed.
1460 * 0b11..Secure and Priviledge user access allowed.
1461 */
1462#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
1463#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
1464#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
1465/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1466 * 0b00..Non-secure and Non-priviledge user access allowed.
1467 * 0b01..Non-secure and Privilege access allowed.
1468 * 0b10..Secure and Non-priviledge user access allowed.
1469 * 0b11..Secure and Priviledge user access allowed.
1470 */
1471#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
1472#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
1473#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
1474/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1475 * 0b00..Non-secure and Non-priviledge user access allowed.
1476 * 0b01..Non-secure and Privilege access allowed.
1477 * 0b10..Secure and Non-priviledge user access allowed.
1478 * 0b11..Secure and Priviledge user access allowed.
1479 */
1480#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
1481#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
1482#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
1483/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1484 * 0b00..Non-secure and Non-priviledge user access allowed.
1485 * 0b01..Non-secure and Privilege access allowed.
1486 * 0b10..Secure and Non-priviledge user access allowed.
1487 * 0b11..Secure and Priviledge user access allowed.
1488 */
1489#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
1490#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
1491#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
1492/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1493 * 0b00..Non-secure and Non-priviledge user access allowed.
1494 * 0b01..Non-secure and Privilege access allowed.
1495 * 0b10..Secure and Non-priviledge user access allowed.
1496 * 0b11..Secure and Priviledge user access allowed.
1497 */
1498#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
1499#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
1500#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
1501/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1502 * 0b00..Non-secure and Non-priviledge user access allowed.
1503 * 0b01..Non-secure and Privilege access allowed.
1504 * 0b10..Secure and Non-priviledge user access allowed.
1505 * 0b11..Secure and Priviledge user access allowed.
1506 */
1507#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
1508/*! @} */
1509
1510/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1511#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)
1512
1513/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
1514#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)
1515
1516/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
1517/*! @{ */
1518#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
1519#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
1520/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1521 * 0b00..Non-secure and Non-priviledge user access allowed.
1522 * 0b01..Non-secure and Privilege access allowed.
1523 * 0b10..Secure and Non-priviledge user access allowed.
1524 * 0b11..Secure and Priviledge user access allowed.
1525 */
1526#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
1527#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
1528#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
1529/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1530 * 0b00..Non-secure and Non-priviledge user access allowed.
1531 * 0b01..Non-secure and Privilege access allowed.
1532 * 0b10..Secure and Non-priviledge user access allowed.
1533 * 0b11..Secure and Priviledge user access allowed.
1534 */
1535#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
1536#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
1537#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
1538/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1539 * 0b00..Non-secure and Non-priviledge user access allowed.
1540 * 0b01..Non-secure and Privilege access allowed.
1541 * 0b10..Secure and Non-priviledge user access allowed.
1542 * 0b11..Secure and Priviledge user access allowed.
1543 */
1544#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
1545#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
1546#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
1547/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1548 * 0b00..Non-secure and Non-priviledge user access allowed.
1549 * 0b01..Non-secure and Privilege access allowed.
1550 * 0b10..Secure and Non-priviledge user access allowed.
1551 * 0b11..Secure and Priviledge user access allowed.
1552 */
1553#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
1554#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
1555#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
1556/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1557 * 0b00..Non-secure and Non-priviledge user access allowed.
1558 * 0b01..Non-secure and Privilege access allowed.
1559 * 0b10..Secure and Non-priviledge user access allowed.
1560 * 0b11..Secure and Priviledge user access allowed.
1561 */
1562#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
1563#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
1564#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
1565/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1566 * 0b00..Non-secure and Non-priviledge user access allowed.
1567 * 0b01..Non-secure and Privilege access allowed.
1568 * 0b10..Secure and Non-priviledge user access allowed.
1569 * 0b11..Secure and Priviledge user access allowed.
1570 */
1571#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
1572#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
1573#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
1574/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1575 * 0b00..Non-secure and Non-priviledge user access allowed.
1576 * 0b01..Non-secure and Privilege access allowed.
1577 * 0b10..Secure and Non-priviledge user access allowed.
1578 * 0b11..Secure and Priviledge user access allowed.
1579 */
1580#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
1581#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
1582#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
1583/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1584 * 0b00..Non-secure and Non-priviledge user access allowed.
1585 * 0b01..Non-secure and Privilege access allowed.
1586 * 0b10..Secure and Non-priviledge user access allowed.
1587 * 0b11..Secure and Priviledge user access allowed.
1588 */
1589#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
1590/*! @} */
1591
1592/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1593#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)
1594
1595/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
1596#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)
1597
1598/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
1599/*! @{ */
1600#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
1601#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
1602/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
1603 * 0b00..Non-secure and Non-priviledge user access allowed.
1604 * 0b01..Non-secure and Privilege access allowed.
1605 * 0b10..Secure and Non-priviledge user access allowed.
1606 * 0b11..Secure and Priviledge user access allowed.
1607 */
1608#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
1609/*! @} */
1610
1611/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
1612#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)
1613
1614/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
1615/*! @{ */
1616#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
1617#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
1618/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1619 * 0b00..Non-secure and Non-priviledge user access allowed.
1620 * 0b01..Non-secure and Privilege access allowed.
1621 * 0b10..Secure and Non-priviledge user access allowed.
1622 * 0b11..Secure and Priviledge user access allowed.
1623 */
1624#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
1625#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
1626#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
1627/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1628 * 0b00..Non-secure and Non-priviledge user access allowed.
1629 * 0b01..Non-secure and Privilege access allowed.
1630 * 0b10..Secure and Non-priviledge user access allowed.
1631 * 0b11..Secure and Priviledge user access allowed.
1632 */
1633#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
1634#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
1635#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
1636/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1637 * 0b00..Non-secure and Non-priviledge user access allowed.
1638 * 0b01..Non-secure and Privilege access allowed.
1639 * 0b10..Secure and Non-priviledge user access allowed.
1640 * 0b11..Secure and Priviledge user access allowed.
1641 */
1642#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
1643#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
1644#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
1645/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1646 * 0b00..Non-secure and Non-priviledge user access allowed.
1647 * 0b01..Non-secure and Privilege access allowed.
1648 * 0b10..Secure and Non-priviledge user access allowed.
1649 * 0b11..Secure and Priviledge user access allowed.
1650 */
1651#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
1652#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
1653#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U)
1654/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1655 * 0b00..Non-secure and Non-priviledge user access allowed.
1656 * 0b01..Non-secure and Privilege access allowed.
1657 * 0b10..Secure and Non-priviledge user access allowed.
1658 * 0b11..Secure and Priviledge user access allowed.
1659 */
1660#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
1661#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
1662#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U)
1663/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1664 * 0b00..Non-secure and Non-priviledge user access allowed.
1665 * 0b01..Non-secure and Privilege access allowed.
1666 * 0b10..Secure and Non-priviledge user access allowed.
1667 * 0b11..Secure and Priviledge user access allowed.
1668 */
1669#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
1670#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
1671#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U)
1672/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1673 * 0b00..Non-secure and Non-priviledge user access allowed.
1674 * 0b01..Non-secure and Privilege access allowed.
1675 * 0b10..Secure and Non-priviledge user access allowed.
1676 * 0b11..Secure and Priviledge user access allowed.
1677 */
1678#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
1679#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
1680#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U)
1681/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1682 * 0b00..Non-secure and Non-priviledge user access allowed.
1683 * 0b01..Non-secure and Privilege access allowed.
1684 * 0b10..Secure and Non-priviledge user access allowed.
1685 * 0b11..Secure and Priviledge user access allowed.
1686 */
1687#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
1688/*! @} */
1689
1690/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1691#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U)
1692
1693/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
1694#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U)
1695
1696/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
1697/*! @{ */
1698#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
1699#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
1700/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
1701 * 0b00..Non-secure and Non-priviledge user access allowed.
1702 * 0b01..Non-secure and Privilege access allowed.
1703 * 0b10..Secure and Non-priviledge user access allowed.
1704 * 0b11..Secure and Priviledge user access allowed.
1705 */
1706#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
1707/*! @} */
1708
1709/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
1710#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)
1711
1712/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
1713/*! @{ */
1714#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
1715#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
1716/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1717 * 0b00..Non-secure and Non-priviledge user access allowed.
1718 * 0b01..Non-secure and Privilege access allowed.
1719 * 0b10..Secure and Non-priviledge user access allowed.
1720 * 0b11..Secure and Priviledge user access allowed.
1721 */
1722#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
1723#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
1724#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
1725/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1726 * 0b00..Non-secure and Non-priviledge user access allowed.
1727 * 0b01..Non-secure and Privilege access allowed.
1728 * 0b10..Secure and Non-priviledge user access allowed.
1729 * 0b11..Secure and Priviledge user access allowed.
1730 */
1731#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
1732#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
1733#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
1734/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1735 * 0b00..Non-secure and Non-priviledge user access allowed.
1736 * 0b01..Non-secure and Privilege access allowed.
1737 * 0b10..Secure and Non-priviledge user access allowed.
1738 * 0b11..Secure and Priviledge user access allowed.
1739 */
1740#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
1741#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
1742#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
1743/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1744 * 0b00..Non-secure and Non-priviledge user access allowed.
1745 * 0b01..Non-secure and Privilege access allowed.
1746 * 0b10..Secure and Non-priviledge user access allowed.
1747 * 0b11..Secure and Priviledge user access allowed.
1748 */
1749#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
1750#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
1751#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
1752/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1753 * 0b00..Non-secure and Non-priviledge user access allowed.
1754 * 0b01..Non-secure and Privilege access allowed.
1755 * 0b10..Secure and Non-priviledge user access allowed.
1756 * 0b11..Secure and Priviledge user access allowed.
1757 */
1758#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
1759#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
1760#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
1761/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1762 * 0b00..Non-secure and Non-priviledge user access allowed.
1763 * 0b01..Non-secure and Privilege access allowed.
1764 * 0b10..Secure and Non-priviledge user access allowed.
1765 * 0b11..Secure and Priviledge user access allowed.
1766 */
1767#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
1768#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
1769#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
1770/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1771 * 0b00..Non-secure and Non-priviledge user access allowed.
1772 * 0b01..Non-secure and Privilege access allowed.
1773 * 0b10..Secure and Non-priviledge user access allowed.
1774 * 0b11..Secure and Priviledge user access allowed.
1775 */
1776#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
1777#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
1778#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
1779/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1780 * 0b00..Non-secure and Non-priviledge user access allowed.
1781 * 0b01..Non-secure and Privilege access allowed.
1782 * 0b10..Secure and Non-priviledge user access allowed.
1783 * 0b11..Secure and Priviledge user access allowed.
1784 */
1785#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
1786/*! @} */
1787
1788/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1789#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U)
1790
1791/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
1792#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U)
1793
1794/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
1795/*! @{ */
1796#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
1797#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
1798/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
1799 * 0b00..Non-secure and Non-priviledge user access allowed.
1800 * 0b01..Non-secure and Privilege access allowed.
1801 * 0b10..Secure and Non-priviledge user access allowed.
1802 * 0b11..Secure and Priviledge user access allowed.
1803 */
1804#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
1805/*! @} */
1806
1807/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
1808#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)
1809
1810/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
1811/*! @{ */
1812#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
1813#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
1814/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1815 * 0b00..Non-secure and Non-priviledge user access allowed.
1816 * 0b01..Non-secure and Privilege access allowed.
1817 * 0b10..Secure and Non-priviledge user access allowed.
1818 * 0b11..Secure and Priviledge user access allowed.
1819 */
1820#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
1821#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
1822#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
1823/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1824 * 0b00..Non-secure and Non-priviledge user access allowed.
1825 * 0b01..Non-secure and Privilege access allowed.
1826 * 0b10..Secure and Non-priviledge user access allowed.
1827 * 0b11..Secure and Priviledge user access allowed.
1828 */
1829#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
1830#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
1831#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
1832/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1833 * 0b00..Non-secure and Non-priviledge user access allowed.
1834 * 0b01..Non-secure and Privilege access allowed.
1835 * 0b10..Secure and Non-priviledge user access allowed.
1836 * 0b11..Secure and Priviledge user access allowed.
1837 */
1838#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
1839#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
1840#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
1841/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1842 * 0b00..Non-secure and Non-priviledge user access allowed.
1843 * 0b01..Non-secure and Privilege access allowed.
1844 * 0b10..Secure and Non-priviledge user access allowed.
1845 * 0b11..Secure and Priviledge user access allowed.
1846 */
1847#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
1848#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U)
1849#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U)
1850/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1851 * 0b00..Non-secure and Non-priviledge user access allowed.
1852 * 0b01..Non-secure and Privilege access allowed.
1853 * 0b10..Secure and Non-priviledge user access allowed.
1854 * 0b11..Secure and Priviledge user access allowed.
1855 */
1856#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
1857#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U)
1858#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U)
1859/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1860 * 0b00..Non-secure and Non-priviledge user access allowed.
1861 * 0b01..Non-secure and Privilege access allowed.
1862 * 0b10..Secure and Non-priviledge user access allowed.
1863 * 0b11..Secure and Priviledge user access allowed.
1864 */
1865#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
1866#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U)
1867#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U)
1868/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1869 * 0b00..Non-secure and Non-priviledge user access allowed.
1870 * 0b01..Non-secure and Privilege access allowed.
1871 * 0b10..Secure and Non-priviledge user access allowed.
1872 * 0b11..Secure and Priviledge user access allowed.
1873 */
1874#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
1875#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U)
1876#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U)
1877/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1878 * 0b00..Non-secure and Non-priviledge user access allowed.
1879 * 0b01..Non-secure and Privilege access allowed.
1880 * 0b10..Secure and Non-priviledge user access allowed.
1881 * 0b11..Secure and Priviledge user access allowed.
1882 */
1883#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
1884/*! @} */
1885
1886/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1887#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U)
1888
1889/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
1890#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U)
1891
1892/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
1893/*! @{ */
1894#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
1895#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
1896/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
1897 * 0b00..Non-secure and Non-priviledge user access allowed.
1898 * 0b01..Non-secure and Privilege access allowed.
1899 * 0b10..Secure and Non-priviledge user access allowed.
1900 * 0b11..Secure and Priviledge user access allowed.
1901 */
1902#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
1903/*! @} */
1904
1905/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
1906#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)
1907
1908/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
1909/*! @{ */
1910#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
1911#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
1912/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
1913 * 0b00..Non-secure and Non-priviledge user access allowed.
1914 * 0b01..Non-secure and Privilege access allowed.
1915 * 0b10..Secure and Non-priviledge user access allowed.
1916 * 0b11..Secure and Priviledge user access allowed.
1917 */
1918#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
1919#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
1920#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
1921/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
1922 * 0b00..Non-secure and Non-priviledge user access allowed.
1923 * 0b01..Non-secure and Privilege access allowed.
1924 * 0b10..Secure and Non-priviledge user access allowed.
1925 * 0b11..Secure and Priviledge user access allowed.
1926 */
1927#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
1928#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
1929#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
1930/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
1931 * 0b00..Non-secure and Non-priviledge user access allowed.
1932 * 0b01..Non-secure and Privilege access allowed.
1933 * 0b10..Secure and Non-priviledge user access allowed.
1934 * 0b11..Secure and Priviledge user access allowed.
1935 */
1936#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
1937#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
1938#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
1939/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
1940 * 0b00..Non-secure and Non-priviledge user access allowed.
1941 * 0b01..Non-secure and Privilege access allowed.
1942 * 0b10..Secure and Non-priviledge user access allowed.
1943 * 0b11..Secure and Priviledge user access allowed.
1944 */
1945#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
1946#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U)
1947#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U)
1948/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
1949 * 0b00..Non-secure and Non-priviledge user access allowed.
1950 * 0b01..Non-secure and Privilege access allowed.
1951 * 0b10..Secure and Non-priviledge user access allowed.
1952 * 0b11..Secure and Priviledge user access allowed.
1953 */
1954#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
1955#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U)
1956#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U)
1957/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
1958 * 0b00..Non-secure and Non-priviledge user access allowed.
1959 * 0b01..Non-secure and Privilege access allowed.
1960 * 0b10..Secure and Non-priviledge user access allowed.
1961 * 0b11..Secure and Priviledge user access allowed.
1962 */
1963#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
1964#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U)
1965#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U)
1966/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
1967 * 0b00..Non-secure and Non-priviledge user access allowed.
1968 * 0b01..Non-secure and Privilege access allowed.
1969 * 0b10..Secure and Non-priviledge user access allowed.
1970 * 0b11..Secure and Priviledge user access allowed.
1971 */
1972#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
1973#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U)
1974#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U)
1975/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
1976 * 0b00..Non-secure and Non-priviledge user access allowed.
1977 * 0b01..Non-secure and Privilege access allowed.
1978 * 0b10..Secure and Non-priviledge user access allowed.
1979 * 0b11..Secure and Priviledge user access allowed.
1980 */
1981#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
1982/*! @} */
1983
1984/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1985#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U)
1986
1987/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
1988#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U)
1989
1990/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */
1991/*! @{ */
1992#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)
1993#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)
1994/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
1995 * 0b00..Non-secure and Non-priviledge user access allowed.
1996 * 0b01..Non-secure and Privilege access allowed.
1997 * 0b10..Secure and Non-priviledge user access allowed.
1998 * 0b11..Secure and Priviledge user access allowed.
1999 */
2000#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
2001/*! @} */
2002
2003/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */
2004#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U)
2005
2006/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */
2007/*! @{ */
2008#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U)
2009#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U)
2010/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2011 * 0b00..Non-secure and Non-priviledge user access allowed.
2012 * 0b01..Non-secure and Privilege access allowed.
2013 * 0b10..Secure and Non-priviledge user access allowed.
2014 * 0b11..Secure and Priviledge user access allowed.
2015 */
2016#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
2017#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U)
2018#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U)
2019/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2020 * 0b00..Non-secure and Non-priviledge user access allowed.
2021 * 0b01..Non-secure and Privilege access allowed.
2022 * 0b10..Secure and Non-priviledge user access allowed.
2023 * 0b11..Secure and Priviledge user access allowed.
2024 */
2025#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
2026#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U)
2027#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U)
2028/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2029 * 0b00..Non-secure and Non-priviledge user access allowed.
2030 * 0b01..Non-secure and Privilege access allowed.
2031 * 0b10..Secure and Non-priviledge user access allowed.
2032 * 0b11..Secure and Priviledge user access allowed.
2033 */
2034#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
2035#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U)
2036#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U)
2037/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2038 * 0b00..Non-secure and Non-priviledge user access allowed.
2039 * 0b01..Non-secure and Privilege access allowed.
2040 * 0b10..Secure and Non-priviledge user access allowed.
2041 * 0b11..Secure and Priviledge user access allowed.
2042 */
2043#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
2044#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U)
2045#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U)
2046/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
2047 * 0b00..Non-secure and Non-priviledge user access allowed.
2048 * 0b01..Non-secure and Privilege access allowed.
2049 * 0b10..Secure and Non-priviledge user access allowed.
2050 * 0b11..Secure and Priviledge user access allowed.
2051 */
2052#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
2053#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U)
2054#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U)
2055/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
2056 * 0b00..Non-secure and Non-priviledge user access allowed.
2057 * 0b01..Non-secure and Privilege access allowed.
2058 * 0b10..Secure and Non-priviledge user access allowed.
2059 * 0b11..Secure and Priviledge user access allowed.
2060 */
2061#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
2062#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U)
2063#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U)
2064/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
2065 * 0b00..Non-secure and Non-priviledge user access allowed.
2066 * 0b01..Non-secure and Privilege access allowed.
2067 * 0b10..Secure and Non-priviledge user access allowed.
2068 * 0b11..Secure and Priviledge user access allowed.
2069 */
2070#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
2071#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U)
2072#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U)
2073/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
2074 * 0b00..Non-secure and Non-priviledge user access allowed.
2075 * 0b01..Non-secure and Privilege access allowed.
2076 * 0b10..Secure and Non-priviledge user access allowed.
2077 * 0b11..Secure and Priviledge user access allowed.
2078 */
2079#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
2080/*! @} */
2081
2082/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2083#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U)
2084
2085/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
2086#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U)
2087
2088/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */
2089/*! @{ */
2090#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)
2091#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)
2092/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
2093 * 0b00..Non-secure and Non-priviledge user access allowed.
2094 * 0b01..Non-secure and Privilege access allowed.
2095 * 0b10..Secure and Non-priviledge user access allowed.
2096 * 0b11..Secure and Priviledge user access allowed.
2097 */
2098#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
2099/*! @} */
2100
2101/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */
2102#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U)
2103
2104/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */
2105/*! @{ */
2106#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U)
2107#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U)
2108/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
2109 * 0b00..Non-secure and Non-priviledge user access allowed.
2110 * 0b01..Non-secure and Privilege access allowed.
2111 * 0b10..Secure and Non-priviledge user access allowed.
2112 * 0b11..Secure and Priviledge user access allowed.
2113 */
2114#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
2115#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U)
2116#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U)
2117/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
2118 * 0b00..Non-secure and Non-priviledge user access allowed.
2119 * 0b01..Non-secure and Privilege access allowed.
2120 * 0b10..Secure and Non-priviledge user access allowed.
2121 * 0b11..Secure and Priviledge user access allowed.
2122 */
2123#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
2124#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U)
2125#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U)
2126/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
2127 * 0b00..Non-secure and Non-priviledge user access allowed.
2128 * 0b01..Non-secure and Privilege access allowed.
2129 * 0b10..Secure and Non-priviledge user access allowed.
2130 * 0b11..Secure and Priviledge user access allowed.
2131 */
2132#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
2133#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U)
2134#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U)
2135/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
2136 * 0b00..Non-secure and Non-priviledge user access allowed.
2137 * 0b01..Non-secure and Privilege access allowed.
2138 * 0b10..Secure and Non-priviledge user access allowed.
2139 * 0b11..Secure and Priviledge user access allowed.
2140 */
2141#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
2142/*! @} */
2143
2144/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2145#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U)
2146
2147/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
2148#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U)
2149
2150/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
2151/*! @{ */
2152#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
2153#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
2154/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
2155 * 0b00..Non-secure and Non-priviledge user access allowed.
2156 * 0b01..Non-secure and Privilege access allowed.
2157 * 0b10..Secure and Non-priviledge user access allowed.
2158 * 0b11..Secure and Priviledge user access allowed.
2159 */
2160#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
2161#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
2162#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
2163/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
2164 * 0b00..Non-secure and Non-priviledge user access allowed.
2165 * 0b01..Non-secure and Privilege access allowed.
2166 * 0b10..Secure and Non-priviledge user access allowed.
2167 * 0b11..Secure and Priviledge user access allowed.
2168 */
2169#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
2170/*! @} */
2171
2172/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
2173#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
2174
2175/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2176/*! @{ */
2177#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
2178#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
2179/*! SYSCON_RULE - System Configuration
2180 * 0b00..Non-secure and Non-priviledge user access allowed.
2181 * 0b01..Non-secure and Privilege access allowed.
2182 * 0b10..Secure and Non-priviledge user access allowed.
2183 * 0b11..Secure and Priviledge user access allowed.
2184 */
2185#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
2186#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
2187#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
2188/*! IOCON_RULE - I/O Configuration
2189 * 0b00..Non-secure and Non-priviledge user access allowed.
2190 * 0b01..Non-secure and Privilege access allowed.
2191 * 0b10..Secure and Non-priviledge user access allowed.
2192 * 0b11..Secure and Priviledge user access allowed.
2193 */
2194#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
2195#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
2196#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
2197/*! GINT0_RULE - GPIO input Interrupt 0
2198 * 0b00..Non-secure and Non-priviledge user access allowed.
2199 * 0b01..Non-secure and Privilege access allowed.
2200 * 0b10..Secure and Non-priviledge user access allowed.
2201 * 0b11..Secure and Priviledge user access allowed.
2202 */
2203#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
2204#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
2205#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
2206/*! GINT1_RULE - GPIO input Interrupt 1
2207 * 0b00..Non-secure and Non-priviledge user access allowed.
2208 * 0b01..Non-secure and Privilege access allowed.
2209 * 0b10..Secure and Non-priviledge user access allowed.
2210 * 0b11..Secure and Priviledge user access allowed.
2211 */
2212#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
2213#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
2214#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
2215/*! PINT_RULE - Pin Interrupt and Pattern match
2216 * 0b00..Non-secure and Non-priviledge user access allowed.
2217 * 0b01..Non-secure and Privilege access allowed.
2218 * 0b10..Secure and Non-priviledge user access allowed.
2219 * 0b11..Secure and Priviledge user access allowed.
2220 */
2221#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
2222#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
2223#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
2224/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
2225 * 0b00..Non-secure and Non-priviledge user access allowed.
2226 * 0b01..Non-secure and Privilege access allowed.
2227 * 0b10..Secure and Non-priviledge user access allowed.
2228 * 0b11..Secure and Priviledge user access allowed.
2229 */
2230#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
2231#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
2232#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
2233/*! INPUTMUX_RULE - Peripheral input multiplexing
2234 * 0b00..Non-secure and Non-priviledge user access allowed.
2235 * 0b01..Non-secure and Privilege access allowed.
2236 * 0b10..Secure and Non-priviledge user access allowed.
2237 * 0b11..Secure and Priviledge user access allowed.
2238 */
2239#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
2240/*! @} */
2241
2242/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
2243#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
2244
2245/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2246/*! @{ */
2247#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
2248#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
2249/*! CTIMER0_RULE - Standard counter/Timer 0
2250 * 0b00..Non-secure and Non-priviledge user access allowed.
2251 * 0b01..Non-secure and Privilege access allowed.
2252 * 0b10..Secure and Non-priviledge user access allowed.
2253 * 0b11..Secure and Priviledge user access allowed.
2254 */
2255#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
2256#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
2257#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
2258/*! CTIMER1_RULE - Standard counter/Timer 1
2259 * 0b00..Non-secure and Non-priviledge user access allowed.
2260 * 0b01..Non-secure and Privilege access allowed.
2261 * 0b10..Secure and Non-priviledge user access allowed.
2262 * 0b11..Secure and Priviledge user access allowed.
2263 */
2264#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
2265#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
2266#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
2267/*! WWDT_RULE - Windiwed wtachdog Timer
2268 * 0b00..Non-secure and Non-priviledge user access allowed.
2269 * 0b01..Non-secure and Privilege access allowed.
2270 * 0b10..Secure and Non-priviledge user access allowed.
2271 * 0b11..Secure and Priviledge user access allowed.
2272 */
2273#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
2274#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
2275#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
2276/*! MRT_RULE - Multi-rate Timer
2277 * 0b00..Non-secure and Non-priviledge user access allowed.
2278 * 0b01..Non-secure and Privilege access allowed.
2279 * 0b10..Secure and Non-priviledge user access allowed.
2280 * 0b11..Secure and Priviledge user access allowed.
2281 */
2282#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
2283#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
2284#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
2285/*! UTICK_RULE - Micro-Timer
2286 * 0b00..Non-secure and Non-priviledge user access allowed.
2287 * 0b01..Non-secure and Privilege access allowed.
2288 * 0b10..Secure and Non-priviledge user access allowed.
2289 * 0b11..Secure and Priviledge user access allowed.
2290 */
2291#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
2292/*! @} */
2293
2294/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
2295#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
2296
2297/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
2298/*! @{ */
2299#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
2300#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
2301/*! ANACTRL_RULE - Analog Modules controller
2302 * 0b00..Non-secure and Non-priviledge user access allowed.
2303 * 0b01..Non-secure and Privilege access allowed.
2304 * 0b10..Secure and Non-priviledge user access allowed.
2305 * 0b11..Secure and Priviledge user access allowed.
2306 */
2307#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
2308/*! @} */
2309
2310/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
2311#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
2312
2313/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2314/*! @{ */
2315#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
2316#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
2317/*! PMC_RULE - Power Management Controller
2318 * 0b00..Non-secure and Non-priviledge user access allowed.
2319 * 0b01..Non-secure and Privilege access allowed.
2320 * 0b10..Secure and Non-priviledge user access allowed.
2321 * 0b11..Secure and Priviledge user access allowed.
2322 */
2323#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
2324#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
2325#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
2326/*! SYSCTRL_RULE - System Controller
2327 * 0b00..Non-secure and Non-priviledge user access allowed.
2328 * 0b01..Non-secure and Privilege access allowed.
2329 * 0b10..Secure and Non-priviledge user access allowed.
2330 * 0b11..Secure and Priviledge user access allowed.
2331 */
2332#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
2333/*! @} */
2334
2335/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
2336#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
2337
2338/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2339/*! @{ */
2340#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
2341#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
2342/*! CTIMER2_RULE - Standard counter/Timer 2
2343 * 0b00..Non-secure and Non-priviledge user access allowed.
2344 * 0b01..Non-secure and Privilege access allowed.
2345 * 0b10..Secure and Non-priviledge user access allowed.
2346 * 0b11..Secure and Priviledge user access allowed.
2347 */
2348#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
2349#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
2350#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
2351/*! CTIMER3_RULE - Standard counter/Timer 3
2352 * 0b00..Non-secure and Non-priviledge user access allowed.
2353 * 0b01..Non-secure and Privilege access allowed.
2354 * 0b10..Secure and Non-priviledge user access allowed.
2355 * 0b11..Secure and Priviledge user access allowed.
2356 */
2357#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
2358#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
2359#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
2360/*! CTIMER4_RULE - Standard counter/Timer 4
2361 * 0b00..Non-secure and Non-priviledge user access allowed.
2362 * 0b01..Non-secure and Privilege access allowed.
2363 * 0b10..Secure and Non-priviledge user access allowed.
2364 * 0b11..Secure and Priviledge user access allowed.
2365 */
2366#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
2367#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
2368#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
2369/*! RTC_RULE - Real Time Counter
2370 * 0b00..Non-secure and Non-priviledge user access allowed.
2371 * 0b01..Non-secure and Privilege access allowed.
2372 * 0b10..Secure and Non-priviledge user access allowed.
2373 * 0b11..Secure and Priviledge user access allowed.
2374 */
2375#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
2376#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
2377#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
2378/*! OSEVENT_RULE - OS Event Timer
2379 * 0b00..Non-secure and Non-priviledge user access allowed.
2380 * 0b01..Non-secure and Privilege access allowed.
2381 * 0b10..Secure and Non-priviledge user access allowed.
2382 * 0b11..Secure and Priviledge user access allowed.
2383 */
2384#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
2385/*! @} */
2386
2387/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
2388#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
2389
2390/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2391/*! @{ */
2392#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
2393#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
2394/*! FLASH_CTRL_RULE - Flash Controller
2395 * 0b00..Non-secure and Non-priviledge user access allowed.
2396 * 0b01..Non-secure and Privilege access allowed.
2397 * 0b10..Secure and Non-priviledge user access allowed.
2398 * 0b11..Secure and Priviledge user access allowed.
2399 */
2400#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
2401#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
2402#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
2403/*! PRINCE_RULE - Prince
2404 * 0b00..Non-secure and Non-priviledge user access allowed.
2405 * 0b01..Non-secure and Privilege access allowed.
2406 * 0b10..Secure and Non-priviledge user access allowed.
2407 * 0b11..Secure and Priviledge user access allowed.
2408 */
2409#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
2410/*! @} */
2411
2412/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
2413#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
2414
2415/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
2416/*! @{ */
2417#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
2418#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
2419/*! USBHPHY_RULE - USB High Speed Phy controller
2420 * 0b00..Non-secure and Non-priviledge user access allowed.
2421 * 0b01..Non-secure and Privilege access allowed.
2422 * 0b10..Secure and Non-priviledge user access allowed.
2423 * 0b11..Secure and Priviledge user access allowed.
2424 */
2425#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
2426#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
2427#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
2428/*! RNG_RULE - True Random Number Generator
2429 * 0b00..Non-secure and Non-priviledge user access allowed.
2430 * 0b01..Non-secure and Privilege access allowed.
2431 * 0b10..Secure and Non-priviledge user access allowed.
2432 * 0b11..Secure and Priviledge user access allowed.
2433 */
2434#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
2435#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
2436#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
2437/*! PUF_RULE - PUF
2438 * 0b00..Non-secure and Non-priviledge user access allowed.
2439 * 0b01..Non-secure and Privilege access allowed.
2440 * 0b10..Secure and Non-priviledge user access allowed.
2441 * 0b11..Secure and Priviledge user access allowed.
2442 */
2443#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
2444#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
2445#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
2446/*! PLU_RULE - Programmable Look-Up logic
2447 * 0b00..Non-secure and Non-priviledge user access allowed.
2448 * 0b01..Non-secure and Privilege access allowed.
2449 * 0b10..Secure and Non-priviledge user access allowed.
2450 * 0b11..Secure and Priviledge user access allowed.
2451 */
2452#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
2453/*! @} */
2454
2455/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
2456#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)
2457
2458/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
2459/*! @{ */
2460#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
2461#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
2462/*! DMA0_RULE - DMA Controller
2463 * 0b00..Non-secure and Non-priviledge user access allowed.
2464 * 0b01..Non-secure and Privilege access allowed.
2465 * 0b10..Secure and Non-priviledge user access allowed.
2466 * 0b11..Secure and Priviledge user access allowed.
2467 */
2468#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
2469#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
2470#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
2471/*! FS_USB_DEV_RULE - USB Full-speed device
2472 * 0b00..Non-secure and Non-priviledge user access allowed.
2473 * 0b01..Non-secure and Privilege access allowed.
2474 * 0b10..Secure and Non-priviledge user access allowed.
2475 * 0b11..Secure and Priviledge user access allowed.
2476 */
2477#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
2478#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
2479#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
2480/*! SCT_RULE - SCTimer
2481 * 0b00..Non-secure and Non-priviledge user access allowed.
2482 * 0b01..Non-secure and Privilege access allowed.
2483 * 0b10..Secure and Non-priviledge user access allowed.
2484 * 0b11..Secure and Priviledge user access allowed.
2485 */
2486#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
2487#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
2488#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
2489/*! FLEXCOMM0_RULE - Flexcomm interface 0
2490 * 0b00..Non-secure and Non-priviledge user access allowed.
2491 * 0b01..Non-secure and Privilege access allowed.
2492 * 0b10..Secure and Non-priviledge user access allowed.
2493 * 0b11..Secure and Priviledge user access allowed.
2494 */
2495#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
2496#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
2497#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
2498/*! FLEXCOMM1_RULE - Flexcomm interface 1
2499 * 0b00..Non-secure and Non-priviledge user access allowed.
2500 * 0b01..Non-secure and Privilege access allowed.
2501 * 0b10..Secure and Non-priviledge user access allowed.
2502 * 0b11..Secure and Priviledge user access allowed.
2503 */
2504#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
2505/*! @} */
2506
2507/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
2508/*! @{ */
2509#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
2510#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
2511/*! FLEXCOMM2_RULE - Flexcomm interface 2
2512 * 0b00..Non-secure and Non-priviledge user access allowed.
2513 * 0b01..Non-secure and Privilege access allowed.
2514 * 0b10..Secure and Non-priviledge user access allowed.
2515 * 0b11..Secure and Priviledge user access allowed.
2516 */
2517#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
2518#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
2519#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
2520/*! FLEXCOMM3_RULE - Flexcomm interface 3
2521 * 0b00..Non-secure and Non-priviledge user access allowed.
2522 * 0b01..Non-secure and Privilege access allowed.
2523 * 0b10..Secure and Non-priviledge user access allowed.
2524 * 0b11..Secure and Priviledge user access allowed.
2525 */
2526#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
2527#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
2528#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
2529/*! FLEXCOMM4_RULE - Flexcomm interface 4
2530 * 0b00..Non-secure and Non-priviledge user access allowed.
2531 * 0b01..Non-secure and Privilege access allowed.
2532 * 0b10..Secure and Non-priviledge user access allowed.
2533 * 0b11..Secure and Priviledge user access allowed.
2534 */
2535#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
2536#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U)
2537#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U)
2538/*! MAILBOX_RULE - Inter CPU communication Mailbox
2539 * 0b00..Non-secure and Non-priviledge user access allowed.
2540 * 0b01..Non-secure and Privilege access allowed.
2541 * 0b10..Secure and Non-priviledge user access allowed.
2542 * 0b11..Secure and Priviledge user access allowed.
2543 */
2544#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
2545#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
2546#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
2547/*! GPIO0_RULE - High Speed GPIO
2548 * 0b00..Non-secure and Non-priviledge user access allowed.
2549 * 0b01..Non-secure and Privilege access allowed.
2550 * 0b10..Secure and Non-priviledge user access allowed.
2551 * 0b11..Secure and Priviledge user access allowed.
2552 */
2553#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
2554/*! @} */
2555
2556/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
2557/*! @{ */
2558#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
2559#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
2560/*! USB_HS_DEV_RULE - USB high Speed device registers
2561 * 0b00..Non-secure and Non-priviledge user access allowed.
2562 * 0b01..Non-secure and Privilege access allowed.
2563 * 0b10..Secure and Non-priviledge user access allowed.
2564 * 0b11..Secure and Priviledge user access allowed.
2565 */
2566#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
2567#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
2568#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
2569/*! CRC_RULE - CRC engine
2570 * 0b00..Non-secure and Non-priviledge user access allowed.
2571 * 0b01..Non-secure and Privilege access allowed.
2572 * 0b10..Secure and Non-priviledge user access allowed.
2573 * 0b11..Secure and Priviledge user access allowed.
2574 */
2575#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
2576#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
2577#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
2578/*! FLEXCOMM5_RULE - Flexcomm interface 5
2579 * 0b00..Non-secure and Non-priviledge user access allowed.
2580 * 0b01..Non-secure and Privilege access allowed.
2581 * 0b10..Secure and Non-priviledge user access allowed.
2582 * 0b11..Secure and Priviledge user access allowed.
2583 */
2584#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
2585#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
2586#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
2587/*! FLEXCOMM6_RULE - Flexcomm interface 6
2588 * 0b00..Non-secure and Non-priviledge user access allowed.
2589 * 0b01..Non-secure and Privilege access allowed.
2590 * 0b10..Secure and Non-priviledge user access allowed.
2591 * 0b11..Secure and Priviledge user access allowed.
2592 */
2593#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
2594/*! @} */
2595
2596/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
2597/*! @{ */
2598#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
2599#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
2600/*! FLEXCOMM7_RULE - Flexcomm interface 7
2601 * 0b00..Non-secure and Non-priviledge user access allowed.
2602 * 0b01..Non-secure and Privilege access allowed.
2603 * 0b10..Secure and Non-priviledge user access allowed.
2604 * 0b11..Secure and Priviledge user access allowed.
2605 */
2606#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
2607#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U)
2608#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U)
2609/*! SDIO_RULE - SDMMC card interface
2610 * 0b00..Non-secure and Non-priviledge user access allowed.
2611 * 0b01..Non-secure and Privilege access allowed.
2612 * 0b10..Secure and Non-priviledge user access allowed.
2613 * 0b11..Secure and Priviledge user access allowed.
2614 */
2615#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
2616#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
2617#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
2618/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
2619 * 0b00..Non-secure and Non-priviledge user access allowed.
2620 * 0b01..Non-secure and Privilege access allowed.
2621 * 0b10..Secure and Non-priviledge user access allowed.
2622 * 0b11..Secure and Priviledge user access allowed.
2623 */
2624#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
2625#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
2626#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
2627/*! HS_LSPI_RULE - High Speed SPI
2628 * 0b00..Non-secure and Non-priviledge user access allowed.
2629 * 0b01..Non-secure and Privilege access allowed.
2630 * 0b10..Secure and Non-priviledge user access allowed.
2631 * 0b11..Secure and Priviledge user access allowed.
2632 */
2633#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
2634/*! @} */
2635
2636/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */
2637/*! @{ */
2638#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
2639#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
2640/*! ADC_RULE - ADC
2641 * 0b00..Non-secure and Non-priviledge user access allowed.
2642 * 0b01..Non-secure and Privilege access allowed.
2643 * 0b10..Secure and Non-priviledge user access allowed.
2644 * 0b11..Secure and Priviledge user access allowed.
2645 */
2646#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
2647#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
2648#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
2649/*! USB_FS_HOST_RULE - USB Full Speed Host registers.
2650 * 0b00..Non-secure and Non-priviledge user access allowed.
2651 * 0b01..Non-secure and Privilege access allowed.
2652 * 0b10..Secure and Non-priviledge user access allowed.
2653 * 0b11..Secure and Priviledge user access allowed.
2654 */
2655#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
2656#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
2657#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
2658/*! USB_HS_HOST_RULE - USB High speed host registers
2659 * 0b00..Non-secure and Non-priviledge user access allowed.
2660 * 0b01..Non-secure and Privilege access allowed.
2661 * 0b10..Secure and Non-priviledge user access allowed.
2662 * 0b11..Secure and Priviledge user access allowed.
2663 */
2664#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
2665#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
2666#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
2667/*! HASH_RULE - SHA-2 crypto registers
2668 * 0b00..Non-secure and Non-priviledge user access allowed.
2669 * 0b01..Non-secure and Privilege access allowed.
2670 * 0b10..Secure and Non-priviledge user access allowed.
2671 * 0b11..Secure and Priviledge user access allowed.
2672 */
2673#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
2674#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
2675#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
2676/*! CASPER_RULE - RSA/ECC crypto accelerator
2677 * 0b00..Non-secure and Non-priviledge user access allowed.
2678 * 0b01..Non-secure and Privilege access allowed.
2679 * 0b10..Secure and Non-priviledge user access allowed.
2680 * 0b11..Secure and Priviledge user access allowed.
2681 */
2682#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
2683#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U)
2684#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U)
2685/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator)
2686 * 0b00..Non-secure and Non-priviledge user access allowed.
2687 * 0b01..Non-secure and Privilege access allowed.
2688 * 0b10..Secure and Non-priviledge user access allowed.
2689 * 0b11..Secure and Priviledge user access allowed.
2690 */
2691#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
2692#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
2693#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
2694/*! DMA1_RULE - DMA Controller (Secure)
2695 * 0b00..Non-secure and Non-priviledge user access allowed.
2696 * 0b01..Non-secure and Privilege access allowed.
2697 * 0b10..Secure and Non-priviledge user access allowed.
2698 * 0b11..Secure and Priviledge user access allowed.
2699 */
2700#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
2701/*! @} */
2702
2703/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */
2704#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U)
2705
2706/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */
2707/*! @{ */
2708#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
2709#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
2710/*! GPIO1_RULE - Secure High Speed GPIO
2711 * 0b00..Non-secure and Non-priviledge user access allowed.
2712 * 0b01..Non-secure and Privilege access allowed.
2713 * 0b10..Secure and Non-priviledge user access allowed.
2714 * 0b11..Secure and Priviledge user access allowed.
2715 */
2716#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
2717#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
2718#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
2719/*! AHB_SEC_CTRL_RULE - AHB Secure Controller
2720 * 0b00..Non-secure and Non-priviledge user access allowed.
2721 * 0b01..Non-secure and Privilege access allowed.
2722 * 0b10..Secure and Non-priviledge user access allowed.
2723 * 0b11..Secure and Priviledge user access allowed.
2724 */
2725#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
2726/*! @} */
2727
2728/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */
2729#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U)
2730
2731/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
2732/*! @{ */
2733#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
2734#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
2735/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
2736 * 0b00..Non-secure and Non-priviledge user access allowed.
2737 * 0b01..Non-secure and Privilege access allowed.
2738 * 0b10..Secure and Non-priviledge user access allowed.
2739 * 0b11..Secure and Priviledge user access allowed.
2740 */
2741#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
2742#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
2743#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
2744/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
2745 * 0b00..Non-secure and Non-priviledge user access allowed.
2746 * 0b01..Non-secure and Privilege access allowed.
2747 * 0b10..Secure and Non-priviledge user access allowed.
2748 * 0b11..Secure and Priviledge user access allowed.
2749 */
2750#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
2751#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
2752#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
2753/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
2754 * 0b00..Non-secure and Non-priviledge user access allowed.
2755 * 0b01..Non-secure and Privilege access allowed.
2756 * 0b10..Secure and Non-priviledge user access allowed.
2757 * 0b11..Secure and Priviledge user access allowed.
2758 */
2759#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
2760#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
2761#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
2762/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
2763 * 0b00..Non-secure and Non-priviledge user access allowed.
2764 * 0b01..Non-secure and Privilege access allowed.
2765 * 0b10..Secure and Non-priviledge user access allowed.
2766 * 0b11..Secure and Priviledge user access allowed.
2767 */
2768#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
2769/*! @} */
2770
2771/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2772#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U)
2773
2774/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
2775#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U)
2776
2777/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
2778/*! @{ */
2779#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
2780#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
2781/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
2782 * 0b00..Non-secure and Non-priviledge user access allowed.
2783 * 0b01..Non-secure and Privilege access allowed.
2784 * 0b10..Secure and Non-priviledge user access allowed.
2785 * 0b11..Secure and Priviledge user access allowed.
2786 */
2787#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
2788/*! @} */
2789
2790/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
2791#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)
2792
2793/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
2794/*! @{ */
2795#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
2796#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
2797/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF
2798 * 0b00..Non-secure and Non-priviledge user access allowed.
2799 * 0b01..Non-secure and Privilege access allowed.
2800 * 0b10..Secure and Non-priviledge user access allowed.
2801 * 0b11..Secure and Priviledge user access allowed.
2802 */
2803#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
2804#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
2805#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
2806/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF
2807 * 0b00..Non-secure and Non-priviledge user access allowed.
2808 * 0b01..Non-secure and Privilege access allowed.
2809 * 0b10..Secure and Non-priviledge user access allowed.
2810 * 0b11..Secure and Priviledge user access allowed.
2811 */
2812#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
2813#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
2814#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
2815/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF
2816 * 0b00..Non-secure and Non-priviledge user access allowed.
2817 * 0b01..Non-secure and Privilege access allowed.
2818 * 0b10..Secure and Non-priviledge user access allowed.
2819 * 0b11..Secure and Priviledge user access allowed.
2820 */
2821#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
2822#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
2823#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
2824/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF
2825 * 0b00..Non-secure and Non-priviledge user access allowed.
2826 * 0b01..Non-secure and Privilege access allowed.
2827 * 0b10..Secure and Non-priviledge user access allowed.
2828 * 0b11..Secure and Priviledge user access allowed.
2829 */
2830#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
2831/*! @} */
2832
2833/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2834#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U)
2835
2836/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
2837#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U)
2838
2839/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */
2840/*! @{ */
2841#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
2842#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
2843/*! SEC_VIO_ADDR - security violation address for AHB port
2844 */
2845#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
2846/*! @} */
2847
2848/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
2849#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U)
2850
2851/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */
2852/*! @{ */
2853#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
2854#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
2855/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
2856 * 0b0..Read access.
2857 * 0b1..Write access.
2858 */
2859#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
2860#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
2861#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
2862/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
2863 * 0b0..Code access.
2864 * 0b1..Data access.
2865 */
2866#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
2867#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
2868#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
2869/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
2870 */
2871#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
2872#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
2873#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
2874/*! SEC_VIO_INFO_MASTER - security violation master number
2875 * 0b0000..CPU0 Code.
2876 * 0b0001..CPU0 System.
2877 * 0b0010..CPU1 Data.
2878 * 0b0011..CPU1 System.
2879 * 0b0100..USB-HS Device.
2880 * 0b0101..SDMA0.
2881 * 0b1000..SDIO.
2882 * 0b1001..PowerQuad.
2883 * 0b1010..HASH.
2884 * 0b1011..USB-FS Host.
2885 * 0b1100..SDMA1.
2886 */
2887#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
2888/*! @} */
2889
2890/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
2891#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U)
2892
2893/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
2894/*! @{ */
2895#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
2896#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
2897/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
2898 * 0b0..Not valid.
2899 * 0b1..Valid (violation occurred).
2900 */
2901#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
2902#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
2903#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
2904/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
2905 * 0b0..Not valid.
2906 * 0b1..Valid (violation occurred).
2907 */
2908#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
2909#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
2910#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
2911/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
2912 * 0b0..Not valid.
2913 * 0b1..Valid (violation occurred).
2914 */
2915#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
2916#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
2917#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
2918/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
2919 * 0b0..Not valid.
2920 * 0b1..Valid (violation occurred).
2921 */
2922#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
2923#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
2924#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
2925/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
2926 * 0b0..Not valid.
2927 * 0b1..Valid (violation occurred).
2928 */
2929#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
2930#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
2931#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
2932/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
2933 * 0b0..Not valid.
2934 * 0b1..Valid (violation occurred).
2935 */
2936#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
2937#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
2938#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
2939/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
2940 * 0b0..Not valid.
2941 * 0b1..Valid (violation occurred).
2942 */
2943#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
2944#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
2945#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
2946/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
2947 * 0b0..Not valid.
2948 * 0b1..Valid (violation occurred).
2949 */
2950#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
2951#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
2952#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
2953/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
2954 * 0b0..Not valid.
2955 * 0b1..Valid (violation occurred).
2956 */
2957#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
2958#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
2959#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
2960/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
2961 * 0b0..Not valid.
2962 * 0b1..Valid (violation occurred).
2963 */
2964#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
2965#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
2966#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
2967/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear.
2968 * 0b0..Not valid.
2969 * 0b1..Valid (violation occurred).
2970 */
2971#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
2972#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
2973#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
2974/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear.
2975 * 0b0..Not valid.
2976 * 0b1..Valid (violation occurred).
2977 */
2978#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
2979/*! @} */
2980
2981/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
2982/*! @{ */
2983#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
2984#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
2985/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
2986 * 0b1..Pin state is readable by non-secure world.
2987 * 0b0..Pin state is blocked to non-secure world.
2988 */
2989#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
2990#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
2991#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
2992/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
2993 * 0b1..Pin state is readable by non-secure world.
2994 * 0b0..Pin state is blocked to non-secure world.
2995 */
2996#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
2997#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
2998#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
2999/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
3000 * 0b1..Pin state is readable by non-secure world.
3001 * 0b0..Pin state is blocked to non-secure world.
3002 */
3003#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
3004#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
3005#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
3006/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
3007 * 0b1..Pin state is readable by non-secure world.
3008 * 0b0..Pin state is blocked to non-secure world.
3009 */
3010#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
3011#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
3012#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
3013/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
3014 * 0b1..Pin state is readable by non-secure world.
3015 * 0b0..Pin state is blocked to non-secure world.
3016 */
3017#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
3018#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
3019#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
3020/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
3021 * 0b1..Pin state is readable by non-secure world.
3022 * 0b0..Pin state is blocked to non-secure world.
3023 */
3024#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
3025#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
3026#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
3027/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
3028 * 0b1..Pin state is readable by non-secure world.
3029 * 0b0..Pin state is blocked to non-secure world.
3030 */
3031#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
3032#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
3033#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
3034/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
3035 * 0b1..Pin state is readable by non-secure world.
3036 * 0b0..Pin state is blocked to non-secure world.
3037 */
3038#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
3039#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
3040#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
3041/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
3042 * 0b1..Pin state is readable by non-secure world.
3043 * 0b0..Pin state is blocked to non-secure world.
3044 */
3045#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
3046#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
3047#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
3048/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
3049 * 0b1..Pin state is readable by non-secure world.
3050 * 0b0..Pin state is blocked to non-secure world.
3051 */
3052#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
3053#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
3054#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
3055/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
3056 * 0b1..Pin state is readable by non-secure world.
3057 * 0b0..Pin state is blocked to non-secure world.
3058 */
3059#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
3060#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
3061#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
3062/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
3063 * 0b1..Pin state is readable by non-secure world.
3064 * 0b0..Pin state is blocked to non-secure world.
3065 */
3066#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
3067#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
3068#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
3069/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
3070 * 0b1..Pin state is readable by non-secure world.
3071 * 0b0..Pin state is blocked to non-secure world.
3072 */
3073#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
3074#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
3075#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
3076/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
3077 * 0b1..Pin state is readable by non-secure world.
3078 * 0b0..Pin state is blocked to non-secure world.
3079 */
3080#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
3081#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
3082#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
3083/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
3084 * 0b1..Pin state is readable by non-secure world.
3085 * 0b0..Pin state is blocked to non-secure world.
3086 */
3087#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
3088#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
3089#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
3090/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
3091 * 0b1..Pin state is readable by non-secure world.
3092 * 0b0..Pin state is blocked to non-secure world.
3093 */
3094#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
3095#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
3096#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
3097/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
3098 * 0b1..Pin state is readable by non-secure world.
3099 * 0b0..Pin state is blocked to non-secure world.
3100 */
3101#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
3102#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
3103#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
3104/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
3105 * 0b1..Pin state is readable by non-secure world.
3106 * 0b0..Pin state is blocked to non-secure world.
3107 */
3108#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
3109#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
3110#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
3111/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
3112 * 0b1..Pin state is readable by non-secure world.
3113 * 0b0..Pin state is blocked to non-secure world.
3114 */
3115#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
3116#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
3117#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
3118/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
3119 * 0b1..Pin state is readable by non-secure world.
3120 * 0b0..Pin state is blocked to non-secure world.
3121 */
3122#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
3123#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
3124#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
3125/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
3126 * 0b1..Pin state is readable by non-secure world.
3127 * 0b0..Pin state is blocked to non-secure world.
3128 */
3129#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
3130#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
3131#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
3132/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
3133 * 0b1..Pin state is readable by non-secure world.
3134 * 0b0..Pin state is blocked to non-secure world.
3135 */
3136#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
3137#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
3138#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
3139/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
3140 * 0b1..Pin state is readable by non-secure world.
3141 * 0b0..Pin state is blocked to non-secure world.
3142 */
3143#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
3144#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
3145#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
3146/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
3147 * 0b1..Pin state is readable by non-secure world.
3148 * 0b0..Pin state is blocked to non-secure world.
3149 */
3150#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
3151#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
3152#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
3153/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
3154 * 0b1..Pin state is readable by non-secure world.
3155 * 0b0..Pin state is blocked to non-secure world.
3156 */
3157#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
3158#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
3159#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
3160/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
3161 * 0b1..Pin state is readable by non-secure world.
3162 * 0b0..Pin state is blocked to non-secure world.
3163 */
3164#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
3165#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
3166#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
3167/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
3168 * 0b1..Pin state is readable by non-secure world.
3169 * 0b0..Pin state is blocked to non-secure world.
3170 */
3171#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
3172#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
3173#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
3174/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
3175 * 0b1..Pin state is readable by non-secure world.
3176 * 0b0..Pin state is blocked to non-secure world.
3177 */
3178#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
3179#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
3180#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
3181/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
3182 * 0b1..Pin state is readable by non-secure world.
3183 * 0b0..Pin state is blocked to non-secure world.
3184 */
3185#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
3186#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
3187#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
3188/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
3189 * 0b1..Pin state is readable by non-secure world.
3190 * 0b0..Pin state is blocked to non-secure world.
3191 */
3192#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
3193#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
3194#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
3195/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
3196 * 0b1..Pin state is readable by non-secure world.
3197 * 0b0..Pin state is blocked to non-secure world.
3198 */
3199#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
3200#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
3201#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
3202/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
3203 * 0b1..Pin state is readable by non-secure world.
3204 * 0b0..Pin state is blocked to non-secure world.
3205 */
3206#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
3207/*! @} */
3208
3209/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
3210/*! @{ */
3211#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
3212#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
3213/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
3214 * 0b1..Pin state is readable by non-secure world.
3215 * 0b0..Pin state is blocked to non-secure world.
3216 */
3217#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
3218#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
3219#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
3220/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
3221 * 0b1..Pin state is readable by non-secure world.
3222 * 0b0..Pin state is blocked to non-secure world.
3223 */
3224#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
3225#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
3226#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
3227/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
3228 * 0b1..Pin state is readable by non-secure world.
3229 * 0b0..Pin state is blocked to non-secure world.
3230 */
3231#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
3232#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
3233#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
3234/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
3235 * 0b1..Pin state is readable by non-secure world.
3236 * 0b0..Pin state is blocked to non-secure world.
3237 */
3238#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
3239#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
3240#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
3241/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
3242 * 0b1..Pin state is readable by non-secure world.
3243 * 0b0..Pin state is blocked to non-secure world.
3244 */
3245#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
3246#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
3247#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
3248/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
3249 * 0b1..Pin state is readable by non-secure world.
3250 * 0b0..Pin state is blocked to non-secure world.
3251 */
3252#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
3253#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
3254#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
3255/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
3256 * 0b1..Pin state is readable by non-secure world.
3257 * 0b0..Pin state is blocked to non-secure world.
3258 */
3259#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
3260#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
3261#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
3262/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
3263 * 0b1..Pin state is readable by non-secure world.
3264 * 0b0..Pin state is blocked to non-secure world.
3265 */
3266#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
3267#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
3268#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
3269/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
3270 * 0b1..Pin state is readable by non-secure world.
3271 * 0b0..Pin state is blocked to non-secure world.
3272 */
3273#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
3274#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
3275#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
3276/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
3277 * 0b1..Pin state is readable by non-secure world.
3278 * 0b0..Pin state is blocked to non-secure world.
3279 */
3280#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
3281#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
3282#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
3283/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
3284 * 0b1..Pin state is readable by non-secure world.
3285 * 0b0..Pin state is blocked to non-secure world.
3286 */
3287#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
3288#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
3289#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
3290/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
3291 * 0b1..Pin state is readable by non-secure world.
3292 * 0b0..Pin state is blocked to non-secure world.
3293 */
3294#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
3295#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
3296#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
3297/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
3298 * 0b1..Pin state is readable by non-secure world.
3299 * 0b0..Pin state is blocked to non-secure world.
3300 */
3301#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
3302#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
3303#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
3304/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
3305 * 0b1..Pin state is readable by non-secure world.
3306 * 0b0..Pin state is blocked to non-secure world.
3307 */
3308#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
3309#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
3310#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
3311/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
3312 * 0b1..Pin state is readable by non-secure world.
3313 * 0b0..Pin state is blocked to non-secure world.
3314 */
3315#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
3316#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
3317#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
3318/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
3319 * 0b1..Pin state is readable by non-secure world.
3320 * 0b0..Pin state is blocked to non-secure world.
3321 */
3322#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
3323#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
3324#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
3325/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
3326 * 0b1..Pin state is readable by non-secure world.
3327 * 0b0..Pin state is blocked to non-secure world.
3328 */
3329#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
3330#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
3331#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
3332/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
3333 * 0b1..Pin state is readable by non-secure world.
3334 * 0b0..Pin state is blocked to non-secure world.
3335 */
3336#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
3337#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
3338#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
3339/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
3340 * 0b1..Pin state is readable by non-secure world.
3341 * 0b0..Pin state is blocked to non-secure world.
3342 */
3343#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
3344#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
3345#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
3346/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
3347 * 0b1..Pin state is readable by non-secure world.
3348 * 0b0..Pin state is blocked to non-secure world.
3349 */
3350#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
3351#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
3352#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
3353/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
3354 * 0b1..Pin state is readable by non-secure world.
3355 * 0b0..Pin state is blocked to non-secure world.
3356 */
3357#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
3358#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
3359#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
3360/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
3361 * 0b1..Pin state is readable by non-secure world.
3362 * 0b0..Pin state is blocked to non-secure world.
3363 */
3364#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
3365#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
3366#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
3367/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
3368 * 0b1..Pin state is readable by non-secure world.
3369 * 0b0..Pin state is blocked to non-secure world.
3370 */
3371#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
3372#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
3373#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
3374/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
3375 * 0b1..Pin state is readable by non-secure world.
3376 * 0b0..Pin state is blocked to non-secure world.
3377 */
3378#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
3379#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
3380#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
3381/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
3382 * 0b1..Pin state is readable by non-secure world.
3383 * 0b0..Pin state is blocked to non-secure world.
3384 */
3385#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
3386#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
3387#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
3388/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
3389 * 0b1..Pin state is readable by non-secure world.
3390 * 0b0..Pin state is blocked to non-secure world.
3391 */
3392#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
3393#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
3394#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
3395/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
3396 * 0b1..Pin state is readable by non-secure world.
3397 * 0b0..Pin state is blocked to non-secure world.
3398 */
3399#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
3400#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
3401#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
3402/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
3403 * 0b1..Pin state is readable by non-secure world.
3404 * 0b0..Pin state is blocked to non-secure world.
3405 */
3406#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
3407#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
3408#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
3409/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
3410 * 0b1..Pin state is readable by non-secure world.
3411 * 0b0..Pin state is blocked to non-secure world.
3412 */
3413#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
3414#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
3415#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
3416/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
3417 * 0b1..Pin state is readable by non-secure world.
3418 * 0b0..Pin state is blocked to non-secure world.
3419 */
3420#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
3421#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
3422#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
3423/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
3424 * 0b1..Pin state is readable by non-secure world.
3425 * 0b0..Pin state is blocked to non-secure world.
3426 */
3427#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
3428#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
3429#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
3430/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
3431 * 0b1..Pin state is readable by non-secure world.
3432 * 0b0..Pin state is blocked to non-secure world.
3433 */
3434#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
3435/*! @} */
3436
3437/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */
3438/*! @{ */
3439#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)
3440#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)
3441/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
3442 * 0b0..
3443 * 0b1..
3444 */
3445#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
3446#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)
3447#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)
3448/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.
3449 * 0b0..
3450 * 0b1..
3451 */
3452#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
3453#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)
3454#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)
3455/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.
3456 * 0b0..
3457 * 0b1..
3458 */
3459#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
3460#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)
3461#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)
3462/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.
3463 * 0b0..
3464 * 0b1..
3465 */
3466#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
3467#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)
3468#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)
3469/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.
3470 * 0b0..
3471 * 0b1..
3472 */
3473#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
3474#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)
3475#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)
3476/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.
3477 * 0b0..
3478 * 0b1..
3479 */
3480#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
3481#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)
3482#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)
3483/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.
3484 * 0b0..
3485 * 0b1..
3486 */
3487#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
3488#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)
3489#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)
3490/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.
3491 * 0b0..
3492 * 0b1..
3493 */
3494#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
3495#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)
3496#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)
3497/*! UTICK_IRQ - Micro Tick Timer interrupt.
3498 * 0b0..
3499 * 0b1..
3500 */
3501#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
3502#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)
3503#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)
3504/*! MRT_IRQ - Multi-Rate Timer interrupt.
3505 * 0b0..
3506 * 0b1..
3507 */
3508#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
3509#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)
3510#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)
3511/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.
3512 * 0b0..
3513 * 0b1..
3514 */
3515#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
3516#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)
3517#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)
3518/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.
3519 * 0b0..
3520 * 0b1..
3521 */
3522#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
3523#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)
3524#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)
3525/*! SCT_IRQ - SCTimer/PWM interrupt.
3526 * 0b0..
3527 * 0b1..
3528 */
3529#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
3530#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)
3531#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)
3532/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.
3533 * 0b0..
3534 * 0b1..
3535 */
3536#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
3537#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)
3538#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)
3539/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
3540 * 0b0..
3541 * 0b1..
3542 */
3543#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
3544#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)
3545#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)
3546/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
3547 * 0b0..
3548 * 0b1..
3549 */
3550#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
3551#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)
3552#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)
3553/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
3554 * 0b0..
3555 * 0b1..
3556 */
3557#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
3558#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)
3559#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)
3560/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
3561 * 0b0..
3562 * 0b1..
3563 */
3564#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
3565#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)
3566#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)
3567/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
3568 * 0b0..
3569 * 0b1..
3570 */
3571#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
3572#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)
3573#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)
3574/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
3575 * 0b0..
3576 * 0b1..
3577 */
3578#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
3579#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)
3580#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)
3581/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
3582 * 0b0..
3583 * 0b1..
3584 */
3585#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
3586#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)
3587#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)
3588/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
3589 * 0b0..
3590 * 0b1..
3591 */
3592#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
3593#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)
3594#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)
3595/*! ADC_IRQ - General Purpose ADC interrupt.
3596 * 0b0..
3597 * 0b1..
3598 */
3599#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
3600#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)
3601#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)
3602/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3603 * 0b0..
3604 * 0b1..
3605 */
3606#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
3607#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)
3608#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)
3609/*! ACMP_IRQ - Analog Comparator interrupt.
3610 * 0b0..
3611 * 0b1..
3612 */
3613#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
3614#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)
3615#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)
3616/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3617 * 0b0..
3618 * 0b1..
3619 */
3620#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
3621#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)
3622#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)
3623/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3624 * 0b0..
3625 * 0b1..
3626 */
3627#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
3628#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)
3629#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)
3630/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.
3631 * 0b0..
3632 * 0b1..
3633 */
3634#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
3635#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)
3636#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)
3637/*! USB0_IRQ - USB Full Speed Controller interrupt.
3638 * 0b0..
3639 * 0b1..
3640 */
3641#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
3642#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)
3643#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)
3644/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
3645 * 0b0..
3646 * 0b1..
3647 */
3648#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
3649#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)
3650#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)
3651/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3652 * 0b0..
3653 * 0b1..
3654 */
3655#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
3656#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)
3657#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)
3658/*! MAILBOX_IRQ - Mailbox interrupt.
3659 * 0b0..
3660 * 0b1..
3661 */
3662#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
3663/*! @} */
3664
3665/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */
3666/*! @{ */
3667#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)
3668#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)
3669/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.
3670 * 0b0..
3671 * 0b1..
3672 */
3673#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
3674#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)
3675#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)
3676/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.
3677 * 0b0..
3678 * 0b1..
3679 */
3680#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
3681#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)
3682#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)
3683/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.
3684 * 0b0..
3685 * 0b1..
3686 */
3687#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
3688#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)
3689#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)
3690/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.
3691 * 0b0..
3692 * 0b1..
3693 */
3694#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
3695#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)
3696#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)
3697/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.
3698 * 0b0..
3699 * 0b1..
3700 */
3701#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
3702#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)
3703#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)
3704/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.
3705 * 0b0..
3706 * 0b1..
3707 */
3708#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
3709#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)
3710#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)
3711/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts
3712 * 0b0..
3713 * 0b1..
3714 */
3715#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
3716#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)
3717#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)
3718/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
3719 * 0b0..
3720 * 0b1..
3721 */
3722#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
3723#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)
3724#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)
3725/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
3726 * 0b0..
3727 * 0b1..
3728 */
3729#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
3730#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)
3731#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)
3732/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
3733 * 0b0..
3734 * 0b1..
3735 */
3736#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
3737#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)
3738#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)
3739/*! SDIO_IRQ - SDIO Controller interrupt.
3740 * 0b0..
3741 * 0b1..
3742 */
3743#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
3744#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)
3745#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)
3746/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
3747 * 0b0..
3748 * 0b1..
3749 */
3750#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
3751#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)
3752#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)
3753/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.
3754 * 0b0..
3755 * 0b1..
3756 */
3757#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
3758#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)
3759#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)
3760/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.
3761 * 0b0..
3762 * 0b1..
3763 */
3764#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
3765#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)
3766#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)
3767/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.
3768 * 0b0..
3769 * 0b1..
3770 */
3771#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
3772#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)
3773#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)
3774/*! USB1_IRQ - USB High Speed Controller interrupt.
3775 * 0b0..
3776 * 0b1..
3777 */
3778#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
3779#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)
3780#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)
3781/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.
3782 * 0b0..
3783 * 0b1..
3784 */
3785#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
3786#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)
3787#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)
3788/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.
3789 * 0b0..
3790 * 0b1..
3791 */
3792#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
3793#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)
3794#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)
3795/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
3796 * 0b0..
3797 * 0b1..
3798 */
3799#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
3800#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)
3801#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)
3802/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
3803 * 0b0..
3804 * 0b1..
3805 */
3806#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
3807#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)
3808#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)
3809/*! PLU_IRQ - Programmable Look-Up Controller interrupt.
3810 * 0b0..
3811 * 0b1..
3812 */
3813#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
3814#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)
3815#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)
3816/*! SEC_VIO_IRQ - Security Violation interrupt.
3817 * 0b0..
3818 * 0b1..
3819 */
3820#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
3821#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)
3822#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)
3823/*! SHA_IRQ - HASH-AES interrupt.
3824 * 0b0..
3825 * 0b1..
3826 */
3827#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
3828#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)
3829#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)
3830/*! CASPER_IRQ - CASPER interrupt.
3831 * 0b0..
3832 * 0b1..
3833 */
3834#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
3835#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)
3836#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)
3837/*! PUFKEY_IRQ - PUF interrupt.
3838 * 0b0..
3839 * 0b1..
3840 */
3841#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
3842#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)
3843#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)
3844/*! PQ_IRQ - Power Quad interrupt.
3845 * 0b0..
3846 * 0b1..
3847 */
3848#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
3849#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)
3850#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)
3851/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt
3852 * 0b0..
3853 * 0b1..
3854 */
3855#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
3856#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)
3857#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)
3858/*! LSPI_HS_IRQ - High Speed SPI interrupt
3859 * 0b0..
3860 * 0b1..
3861 */
3862#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
3863/*! @} */
3864
3865/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
3866/*! @{ */
3867#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
3868#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
3869/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
3870 * 0b10..Writable.
3871 * 0b01..Restricted mode.
3872 */
3873#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
3874#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
3875#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
3876/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
3877 * 0b10..Writable.
3878 * 0b01..Restricted mode.
3879 */
3880#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
3881#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)
3882#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)
3883/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock.
3884 * 0b10..Writable.
3885 * 0b01..Restricted mode.
3886 */
3887#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
3888#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)
3889#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)
3890/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock.
3891 * 0b10..Writable.
3892 * 0b01..Restricted mode.
3893 */
3894#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
3895/*! @} */
3896
3897/*! @name MASTER_SEC_LEVEL - master secure level register */
3898/*! @{ */
3899#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U)
3900#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U)
3901/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus.
3902 * 0b00..Non-secure and Non-priviledge user access allowed.
3903 * 0b01..Non-secure and Privilege access allowed.
3904 * 0b10..Secure and Non-priviledge user access allowed.
3905 * 0b11..Secure and Priviledge user access allowed.
3906 */
3907#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
3908#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U)
3909#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U)
3910/*! CPU1S - Micro-Cortex M33 (CPU1) System bus.
3911 * 0b00..Non-secure and Non-priviledge user access allowed.
3912 * 0b01..Non-secure and Privilege access allowed.
3913 * 0b10..Secure and Non-priviledge user access allowed.
3914 * 0b11..Secure and Priviledge user access allowed.
3915 */
3916#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
3917#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
3918#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
3919/*! USBFSD - USB Full Speed Device.
3920 * 0b00..Non-secure and Non-priviledge user access allowed.
3921 * 0b01..Non-secure and Privilege access allowed.
3922 * 0b10..Secure and Non-priviledge user access allowed.
3923 * 0b11..Secure and Priviledge user access allowed.
3924 */
3925#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
3926#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
3927#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
3928/*! SDMA0 - System DMA 0.
3929 * 0b00..Non-secure and Non-priviledge user access allowed.
3930 * 0b01..Non-secure and Privilege access allowed.
3931 * 0b10..Secure and Non-priviledge user access allowed.
3932 * 0b11..Secure and Priviledge user access allowed.
3933 */
3934#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
3935#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
3936#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
3937/*! SDIO - SDIO.
3938 * 0b00..Non-secure and Non-priviledge user access allowed.
3939 * 0b01..Non-secure and Privilege access allowed.
3940 * 0b10..Secure and Non-priviledge user access allowed.
3941 * 0b11..Secure and Priviledge user access allowed.
3942 */
3943#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
3944#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)
3945#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)
3946/*! PQ - Power Quad.
3947 * 0b00..Non-secure and Non-priviledge user access allowed.
3948 * 0b01..Non-secure and Privilege access allowed.
3949 * 0b10..Secure and Non-priviledge user access allowed.
3950 * 0b11..Secure and Priviledge user access allowed.
3951 */
3952#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
3953#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
3954#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
3955/*! HASH - Hash.
3956 * 0b00..Non-secure and Non-priviledge user access allowed.
3957 * 0b01..Non-secure and Privilege access allowed.
3958 * 0b10..Secure and Non-priviledge user access allowed.
3959 * 0b11..Secure and Priviledge user access allowed.
3960 */
3961#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
3962#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
3963#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
3964/*! USBFSH - USB Full speed Host.
3965 * 0b00..Non-secure and Non-priviledge user access allowed.
3966 * 0b01..Non-secure and Privilege access allowed.
3967 * 0b10..Secure and Non-priviledge user access allowed.
3968 * 0b11..Secure and Priviledge user access allowed.
3969 */
3970#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
3971#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
3972#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
3973/*! SDMA1 - System DMA 1 security level.
3974 * 0b00..Non-secure and Non-priviledge user access allowed.
3975 * 0b01..Non-secure and Privilege access allowed.
3976 * 0b10..Secure and Non-priviledge user access allowed.
3977 * 0b11..Secure and Priviledge user access allowed.
3978 */
3979#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
3980#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
3981#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
3982/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
3983 * 0b10..Writable.
3984 * 0b01..Restricted mode.
3985 */
3986#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
3987/*! @} */
3988
3989/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
3990/*! @{ */
3991#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U)
3992#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U)
3993/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
3994 * 0b11..Non-secure and Non-priviledge user access allowed.
3995 * 0b10..Non-secure and Privilege access allowed.
3996 * 0b01..Secure and Non-priviledge user access allowed.
3997 * 0b00..Secure and Priviledge user access allowed.
3998 */
3999#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
4000#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U)
4001#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U)
4002/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
4003 * 0b11..Non-secure and Non-priviledge user access allowed.
4004 * 0b10..Non-secure and Privilege access allowed.
4005 * 0b01..Secure and Non-priviledge user access allowed.
4006 * 0b00..Secure and Priviledge user access allowed.
4007 */
4008#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
4009#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
4010#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
4011/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
4012 * 0b11..Non-secure and Non-priviledge user access allowed.
4013 * 0b10..Non-secure and Privilege access allowed.
4014 * 0b01..Secure and Non-priviledge user access allowed.
4015 * 0b00..Secure and Priviledge user access allowed.
4016 */
4017#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
4018#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
4019#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
4020/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
4021 * 0b11..Non-secure and Non-priviledge user access allowed.
4022 * 0b10..Non-secure and Privilege access allowed.
4023 * 0b01..Secure and Non-priviledge user access allowed.
4024 * 0b00..Secure and Priviledge user access allowed.
4025 */
4026#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
4027#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)
4028#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)
4029/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
4030 * 0b11..Non-secure and Non-priviledge user access allowed.
4031 * 0b10..Non-secure and Privilege access allowed.
4032 * 0b01..Secure and Non-priviledge user access allowed.
4033 * 0b00..Secure and Priviledge user access allowed.
4034 */
4035#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
4036#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)
4037#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)
4038/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
4039 * 0b11..Non-secure and Non-priviledge user access allowed.
4040 * 0b10..Non-secure and Privilege access allowed.
4041 * 0b01..Secure and Non-priviledge user access allowed.
4042 * 0b00..Secure and Priviledge user access allowed.
4043 */
4044#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
4045#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
4046#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
4047/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
4048 * 0b11..Non-secure and Non-priviledge user access allowed.
4049 * 0b10..Non-secure and Privilege access allowed.
4050 * 0b01..Secure and Non-priviledge user access allowed.
4051 * 0b00..Secure and Priviledge user access allowed.
4052 */
4053#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
4054#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
4055#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
4056/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
4057 * 0b11..Non-secure and Non-priviledge user access allowed.
4058 * 0b10..Non-secure and Privilege access allowed.
4059 * 0b01..Secure and Non-priviledge user access allowed.
4060 * 0b00..Secure and Priviledge user access allowed.
4061 */
4062#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
4063#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
4064#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
4065/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
4066 * 0b11..Non-secure and Non-priviledge user access allowed.
4067 * 0b10..Non-secure and Privilege access allowed.
4068 * 0b01..Secure and Non-priviledge user access allowed.
4069 * 0b00..Secure and Priviledge user access allowed.
4070 */
4071#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
4072#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
4073#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
4074/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
4075 * 0b10..Writable.
4076 * 0b01..Restricted mode.
4077 */
4078#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
4079/*! @} */
4080
4081/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
4082/*! @{ */
4083#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4084#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4085/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
4086 * 0b10..Writable.
4087 * 0b01..Restricted mode.
4088 */
4089#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
4090#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4091#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4092/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
4093 * 0b10..Writable.
4094 * 0b01..Restricted mode.
4095 */
4096#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
4097#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
4098#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
4099/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
4100 * 0b10..Writable.
4101 * 0b01..Restricted mode.
4102 */
4103#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
4104#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
4105#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
4106/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
4107 * 0b10..Writable.
4108 * 0b01..Restricted mode.
4109 */
4110#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
4111#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
4112#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
4113/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
4114 * 0b10..Writable.
4115 * 0b01..Restricted mode.
4116 */
4117#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
4118#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
4119#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
4120/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
4121 * 0b10..Writable.
4122 * 0b01..Restricted mode.
4123 */
4124#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
4125/*! @} */
4126
4127/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */
4128/*! @{ */
4129#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
4130#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
4131/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
4132 * 0b10..Writable.
4133 * 0b01..Restricted mode.
4134 */
4135#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
4136#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
4137#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
4138/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
4139 * 0b10..Writable.
4140 * 0b01..Restricted mode.
4141 */
4142#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
4143#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U)
4144#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U)
4145/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock.
4146 * 0b10..Writable.
4147 * 0b01..Restricted mode.
4148 */
4149#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
4150/*! @} */
4151
4152/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
4153/*! @{ */
4154#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
4155#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
4156/*! WRITE_LOCK - Write lock.
4157 * 0b10..Secure control registers can be written.
4158 * 0b01..Restricted mode.
4159 */
4160#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
4161#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4162#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4163/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4164 * 0b10..Disable check.
4165 * 0b01..Restricted mode.
4166 */
4167#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
4168#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4169#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4170/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4171 * 0b10..Disable check.
4172 * 0b01..Restricted mode.
4173 */
4174#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
4175#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4176#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4177/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4178 * 0b10..Disable check.
4179 * 0b01..Restricted mode.
4180 */
4181#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
4182#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4183#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4184/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4185 * 0b10..Enable abort fort secure checker.
4186 * 0b01..Disable abort fort secure checker.
4187 */
4188#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
4189#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4190#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4191/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4192 * 0b10..Simple master in strict mode.
4193 * 0b01..Simple master in tier mode.
4194 */
4195#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4196#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4197#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4198/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4199 * 0b10..Smart master in strict mode.
4200 * 0b01..Smart master in tier mode.
4201 */
4202#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4203#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
4204#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
4205/*! IDAU_ALL_NS - Disable IDAU.
4206 * 0b10..IDAU is enabled.
4207 * 0b01..IDAU is disable.
4208 */
4209#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
4210/*! @} */
4211
4212/*! @name MISC_CTRL_REG - secure control register */
4213/*! @{ */
4214#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
4215#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
4216/*! WRITE_LOCK - Write lock.
4217 * 0b10..Secure control registers can be written.
4218 * 0b01..Restricted mode.
4219 */
4220#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
4221#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
4222#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
4223/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
4224 * 0b10..Disable check.
4225 * 0b01..Restricted mode.
4226 */
4227#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
4228#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
4229#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
4230/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
4231 * 0b10..Disable check.
4232 * 0b01..Restricted mode.
4233 */
4234#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
4235#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
4236#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
4237/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
4238 * 0b10..Disable check.
4239 * 0b01..Restricted mode.
4240 */
4241#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
4242#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
4243#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
4244/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
4245 * 0b10..Enable abort fort secure checker.
4246 * 0b01..Disable abort fort secure checker.
4247 */
4248#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
4249#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
4250#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
4251/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
4252 * 0b10..Simple master in strict mode.
4253 * 0b01..Simple master in tier mode.
4254 */
4255#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
4256#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
4257#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
4258/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
4259 * 0b10..Smart master in strict mode.
4260 * 0b01..Smart master in tier mode.
4261 */
4262#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
4263#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
4264#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
4265/*! IDAU_ALL_NS - Disable IDAU.
4266 * 0b10..IDAU is enabled.
4267 * 0b01..IDAU is disable.
4268 */
4269#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
4270/*! @} */
4271
4272
4273/*!
4274 * @}
4275 */ /* end of group AHB_SECURE_CTRL_Register_Masks */
4276
4277
4278/* AHB_SECURE_CTRL - Peripheral instance base addresses */
4279#if (__ARM_FEATURE_CMSE & 0x2)
4280 /** Peripheral AHB_SECURE_CTRL base address */
4281 #define AHB_SECURE_CTRL_BASE (0x500AC000u)
4282 /** Peripheral AHB_SECURE_CTRL base address */
4283 #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
4284 /** Peripheral AHB_SECURE_CTRL base pointer */
4285 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4286 /** Peripheral AHB_SECURE_CTRL base pointer */
4287 #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
4288 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4289 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4290 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4291 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4292 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4293 #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
4294 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4295 #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
4296#else
4297 /** Peripheral AHB_SECURE_CTRL base address */
4298 #define AHB_SECURE_CTRL_BASE (0x400AC000u)
4299 /** Peripheral AHB_SECURE_CTRL base pointer */
4300 #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
4301 /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
4302 #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
4303 /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
4304 #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
4305#endif
4306
4307/*!
4308 * @}
4309 */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
4310
4311
4312/* ----------------------------------------------------------------------------
4313 -- ANACTRL Peripheral Access Layer
4314 ---------------------------------------------------------------------------- */
4315
4316/*!
4317 * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
4318 * @{
4319 */
4320
4321/** ANACTRL - Register Layout Typedef */
4322typedef struct {
4323 uint8_t RESERVED_0[4];
4324 __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
4325 uint8_t RESERVED_1[4];
4326 __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
4327 __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
4328 __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
4329 uint8_t RESERVED_2[8];
4330 __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
4331 __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
4332 uint8_t RESERVED_3[8];
4333 __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
4334 __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
4335 uint8_t RESERVED_4[8];
4336 __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */
4337 __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */
4338 __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */
4339 uint8_t RESERVED_5[180];
4340 __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */
4341} ANACTRL_Type;
4342
4343/* ----------------------------------------------------------------------------
4344 -- ANACTRL Register Masks
4345 ---------------------------------------------------------------------------- */
4346
4347/*!
4348 * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
4349 * @{
4350 */
4351
4352/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
4353/*! @{ */
4354#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
4355#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
4356/*! FLASH_PWRDWN - Flash Power Down status.
4357 * 0b0..Flash is not in power down mode.
4358 * 0b1..Flash is in power down mode.
4359 */
4360#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
4361#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
4362#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
4363/*! FLASH_INIT_ERROR - Flash initialization error status.
4364 * 0b0..No error.
4365 * 0b1..At least one error occured during flash initialization..
4366 */
4367#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
4368/*! @} */
4369
4370/*! @name FREQ_ME_CTRL - Frequency Measure function control register */
4371/*! @{ */
4372#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
4373#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
4374/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
4375 */
4376#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
4377#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
4378#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
4379/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
4380 * when the measurement cycle has completed and there is valid capture data in the CAPVAL field
4381 * (bits 30:0).
4382 */
4383#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
4384/*! @} */
4385
4386/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
4387/*! @{ */
4388#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
4389#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
4390/*! ENA_12MHZCLK - 12 MHz clock control.
4391 * 0b0..12 MHz clock is disabled.
4392 * 0b1..12 MHz clock is enabled.
4393 */
4394#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
4395#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)
4396#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)
4397/*! ENA_48MHZCLK - 48 MHz clock control.
4398 * 0b0..Reserved.
4399 * 0b1..48 MHz clock is enabled.
4400 */
4401#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
4402#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
4403#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
4404/*! DAC_TRIM - Frequency trim.
4405 */
4406#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
4407#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
4408#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
4409/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into f