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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16')
50 files changed, 40851 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/LPC55S16.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/LPC55S16.h new file mode 100644 index 000000000..30e70cfe0 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/LPC55S16.h | |||
| @@ -0,0 +1,29088 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: LPC55S16JBD100 | ||
| 4 | ** LPC55S16JBD64 | ||
| 5 | ** LPC55S16JEV98 | ||
| 6 | ** | ||
| 7 | ** Compilers: GNU C Compiler | ||
| 8 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 9 | ** Keil ARM C/C++ Compiler | ||
| 10 | ** MCUXpresso Compiler | ||
| 11 | ** | ||
| 12 | ** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 | ||
| 13 | ** Version: rev. 1.1, 2019-12-03 | ||
| 14 | ** Build: b200311 | ||
| 15 | ** | ||
| 16 | ** Abstract: | ||
| 17 | ** CMSIS Peripheral Access Layer for LPC55S16 | ||
| 18 | ** | ||
| 19 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 20 | ** Copyright 2016-2020 NXP | ||
| 21 | ** All rights reserved. | ||
| 22 | ** | ||
| 23 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 24 | ** | ||
| 25 | ** http: www.nxp.com | ||
| 26 | ** mail: [email protected] | ||
| 27 | ** | ||
| 28 | ** Revisions: | ||
| 29 | ** - rev. 1.0 (2018-08-22) | ||
| 30 | ** Initial version based on v0.2UM | ||
| 31 | ** - rev. 1.1 (2019-12-03) | ||
| 32 | ** Initial version based on v0.6UM | ||
| 33 | ** | ||
| 34 | ** ################################################################### | ||
| 35 | */ | ||
| 36 | |||
| 37 | /*! | ||
| 38 | * @file LPC55S16.h | ||
| 39 | * @version 1.1 | ||
| 40 | * @date 2019-12-03 | ||
| 41 | * @brief CMSIS Peripheral Access Layer for LPC55S16 | ||
| 42 | * | ||
| 43 | * CMSIS Peripheral Access Layer for LPC55S16 | ||
| 44 | */ | ||
| 45 | |||
| 46 | #ifndef _LPC55S16_H_ | ||
| 47 | #define _LPC55S16_H_ /**< Symbol preventing repeated inclusion */ | ||
| 48 | |||
| 49 | /** Memory map major version (memory maps with equal major version number are | ||
| 50 | * compatible) */ | ||
| 51 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 52 | /** Memory map minor version */ | ||
| 53 | #define MCU_MEM_MAP_VERSION_MINOR 0x0001U | ||
| 54 | |||
| 55 | |||
| 56 | /* ---------------------------------------------------------------------------- | ||
| 57 | -- Interrupt vector numbers | ||
| 58 | ---------------------------------------------------------------------------- */ | ||
| 59 | |||
| 60 | /*! | ||
| 61 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 62 | * @{ | ||
| 63 | */ | ||
| 64 | |||
| 65 | /** Interrupt Number Definitions */ | ||
| 66 | #define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */ | ||
| 67 | |||
| 68 | typedef enum IRQn { | ||
| 69 | /* Auxiliary constants */ | ||
| 70 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 71 | |||
| 72 | /* Core interrupts */ | ||
| 73 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 74 | HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ | ||
| 75 | MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ | ||
| 76 | BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ | ||
| 77 | UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ | ||
| 78 | SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ | ||
| 79 | SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ | ||
| 80 | DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ | ||
| 81 | PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ | ||
| 82 | SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ | ||
| 83 | |||
| 84 | /* Device specific interrupts */ | ||
| 85 | WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ | ||
| 86 | DMA0_IRQn = 1, /**< DMA0 controller */ | ||
| 87 | GINT0_IRQn = 2, /**< GPIO group 0 */ | ||
| 88 | GINT1_IRQn = 3, /**< GPIO group 1 */ | ||
| 89 | PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ | ||
| 90 | PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ | ||
| 91 | PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ | ||
| 92 | PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ | ||
| 93 | UTICK0_IRQn = 8, /**< Micro-tick Timer */ | ||
| 94 | MRT0_IRQn = 9, /**< Multi-rate timer */ | ||
| 95 | CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ | ||
| 96 | CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ | ||
| 97 | SCT0_IRQn = 12, /**< SCTimer/PWM */ | ||
| 98 | CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ | ||
| 99 | FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 100 | FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 101 | FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 102 | FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 103 | FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 104 | FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 105 | FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 106 | FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ | ||
| 107 | ADC0_IRQn = 22, /**< ADC0 */ | ||
| 108 | Reserved39_IRQn = 23, /**< Reserved interrupt */ | ||
| 109 | ACMP_IRQn = 24, /**< ACMP interrupts */ | ||
| 110 | Reserved41_IRQn = 25, /**< Reserved interrupt */ | ||
| 111 | Reserved42_IRQn = 26, /**< Reserved interrupt */ | ||
| 112 | USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ | ||
| 113 | USB0_IRQn = 28, /**< USB device */ | ||
| 114 | RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ | ||
| 115 | Reserved46_IRQn = 30, /**< Reserved interrupt */ | ||
| 116 | Reserved47_IRQn = 31, /**< Reserved interrupt */ | ||
| 117 | PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ | ||
| 118 | PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ | ||
| 119 | PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ | ||
| 120 | PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ | ||
| 121 | CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ | ||
| 122 | CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ | ||
| 123 | OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ | ||
| 124 | Reserved55_IRQn = 39, /**< Reserved interrupt */ | ||
| 125 | Reserved56_IRQn = 40, /**< Reserved interrupt */ | ||
| 126 | Reserved57_IRQn = 41, /**< Reserved interrupt */ | ||
| 127 | Reserved58_IRQn = 42, /**< Reserved interrupt */ | ||
| 128 | CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ | ||
| 129 | CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ | ||
| 130 | Reserved61_IRQn = 45, /**< Reserved interrupt */ | ||
| 131 | USB1_PHY_IRQn = 46, /**< USB1_PHY */ | ||
| 132 | USB1_IRQn = 47, /**< USB1 interrupt */ | ||
| 133 | USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ | ||
| 134 | SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ | ||
| 135 | SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ | ||
| 136 | SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ | ||
| 137 | PLU_IRQn = 52, /**< PLU interrupt */ | ||
| 138 | SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ | ||
| 139 | HASHCRYPT_IRQn = 54, /**< SHA interrupt */ | ||
| 140 | CASER_IRQn = 55, /**< CASPER interrupt */ | ||
| 141 | PUF_IRQn = 56, /**< PUF interrupt */ | ||
| 142 | Reserved73_IRQn = 57, /**< Reserved interrupt */ | ||
| 143 | DMA1_IRQn = 58, /**< DMA1 interrupt */ | ||
| 144 | FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ | ||
| 145 | CodeWDG_IRQn = 60 /**< CodeWDG interrupt */ | ||
| 146 | } IRQn_Type; | ||
| 147 | |||
| 148 | /*! | ||
| 149 | * @} | ||
| 150 | */ /* end of group Interrupt_vector_numbers */ | ||
| 151 | |||
| 152 | |||
| 153 | /* ---------------------------------------------------------------------------- | ||
| 154 | -- Cortex M33 Core Configuration | ||
| 155 | ---------------------------------------------------------------------------- */ | ||
| 156 | |||
| 157 | /*! | ||
| 158 | * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration | ||
| 159 | * @{ | ||
| 160 | */ | ||
| 161 | |||
| 162 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ | ||
| 163 | #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ | ||
| 164 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 165 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ | ||
| 166 | #define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ | ||
| 167 | #define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ | ||
| 168 | |||
| 169 | #include "core_cm33.h" /* Core Peripheral Access Layer */ | ||
| 170 | #include "system_LPC55S16.h" /* Device specific configuration file */ | ||
| 171 | |||
| 172 | /*! | ||
| 173 | * @} | ||
| 174 | */ /* end of group Cortex_Core_Configuration */ | ||
| 175 | |||
| 176 | |||
| 177 | /* ---------------------------------------------------------------------------- | ||
| 178 | -- Mapping Information | ||
| 179 | ---------------------------------------------------------------------------- */ | ||
| 180 | |||
| 181 | /*! | ||
| 182 | * @addtogroup Mapping_Information Mapping Information | ||
| 183 | * @{ | ||
| 184 | */ | ||
| 185 | |||
| 186 | /** Mapping Information */ | ||
| 187 | /*! | ||
| 188 | * @addtogroup dma_request | ||
| 189 | * @{ | ||
| 190 | */ | ||
| 191 | |||
| 192 | /******************************************************************************* | ||
| 193 | * Definitions | ||
| 194 | ******************************************************************************/ | ||
| 195 | |||
| 196 | /*! | ||
| 197 | * @brief Structure for the DMA hardware request | ||
| 198 | * | ||
| 199 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 200 | * hardware request to trigger the DMA transfer accordingly. The index | ||
| 201 | * of the hardware request varies according to the to SoC. | ||
| 202 | */ | ||
| 203 | typedef enum _dma_request_source | ||
| 204 | { | ||
| 205 | kDma0RequestHashCrypt = 0U, /**< HashCrypt */ | ||
| 206 | kDma1RequestHashCrypt = 0U, /**< HashCrypt */ | ||
| 207 | kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 208 | kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ | ||
| 209 | kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 210 | kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ | ||
| 211 | kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 212 | kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ | ||
| 213 | kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 214 | kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ | ||
| 215 | kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 216 | kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ | ||
| 217 | kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 218 | kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ | ||
| 219 | kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 220 | kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ | ||
| 221 | kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 222 | kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ | ||
| 223 | kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 224 | kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ | ||
| 225 | kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ | ||
| 226 | kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ | ||
| 227 | kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ | ||
| 228 | kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ | ||
| 229 | kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ | ||
| 230 | kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ | ||
| 231 | kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ | ||
| 232 | kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ | ||
| 233 | kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ | ||
| 234 | kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ | ||
| 235 | kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ | ||
| 236 | kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ | ||
| 237 | kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ | ||
| 238 | } dma_request_source_t; | ||
| 239 | |||
| 240 | /* @} */ | ||
| 241 | |||
| 242 | |||
| 243 | /*! | ||
| 244 | * @} | ||
| 245 | */ /* end of group Mapping_Information */ | ||
| 246 | |||
| 247 | |||
| 248 | /* ---------------------------------------------------------------------------- | ||
| 249 | -- Device Peripheral Access Layer | ||
| 250 | ---------------------------------------------------------------------------- */ | ||
| 251 | |||
| 252 | /*! | ||
| 253 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 254 | * @{ | ||
| 255 | */ | ||
| 256 | |||
| 257 | |||
| 258 | /* | ||
| 259 | ** Start of section using anonymous unions | ||
| 260 | */ | ||
| 261 | |||
| 262 | #if defined(__ARMCC_VERSION) | ||
| 263 | #if (__ARMCC_VERSION >= 6010050) | ||
| 264 | #pragma clang diagnostic push | ||
| 265 | #else | ||
| 266 | #pragma push | ||
| 267 | #pragma anon_unions | ||
| 268 | #endif | ||
| 269 | #elif defined(__GNUC__) | ||
| 270 | /* anonymous unions are enabled by default */ | ||
| 271 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 272 | #pragma language=extended | ||
| 273 | #else | ||
| 274 | #error Not supported compiler type | ||
| 275 | #endif | ||
| 276 | |||
| 277 | /* ---------------------------------------------------------------------------- | ||
| 278 | -- ADC Peripheral Access Layer | ||
| 279 | ---------------------------------------------------------------------------- */ | ||
| 280 | |||
| 281 | /*! | ||
| 282 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 283 | * @{ | ||
| 284 | */ | ||
| 285 | |||
| 286 | /** ADC - Register Layout Typedef */ | ||
| 287 | typedef struct { | ||
| 288 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ | ||
| 289 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ | ||
| 290 | uint8_t RESERVED_0[8]; | ||
| 291 | __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ | ||
| 292 | __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ | ||
| 293 | __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ | ||
| 294 | __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ | ||
| 295 | __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ | ||
| 296 | __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ | ||
| 297 | uint8_t RESERVED_1[12]; | ||
| 298 | __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ | ||
| 299 | __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ | ||
| 300 | uint8_t RESERVED_2[4]; | ||
| 301 | __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ | ||
| 302 | uint8_t RESERVED_3[92]; | ||
| 303 | __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ | ||
| 304 | __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ | ||
| 305 | uint8_t RESERVED_4[8]; | ||
| 306 | __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ | ||
| 307 | __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ | ||
| 308 | struct { /* offset: 0x100, array step: 0x8 */ | ||
| 309 | __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ | ||
| 310 | __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ | ||
| 311 | } CMD[15]; | ||
| 312 | uint8_t RESERVED_5[136]; | ||
| 313 | __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ | ||
| 314 | uint8_t RESERVED_6[240]; | ||
| 315 | __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ | ||
| 316 | uint8_t RESERVED_7[248]; | ||
| 317 | __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ | ||
| 318 | uint8_t RESERVED_8[124]; | ||
| 319 | __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ | ||
| 320 | } ADC_Type; | ||
| 321 | |||
| 322 | /* ---------------------------------------------------------------------------- | ||
| 323 | -- ADC Register Masks | ||
| 324 | ---------------------------------------------------------------------------- */ | ||
| 325 | |||
| 326 | /*! | ||
| 327 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 328 | * @{ | ||
| 329 | */ | ||
| 330 | |||
| 331 | /*! @name VERID - Version ID Register */ | ||
| 332 | /*! @{ */ | ||
| 333 | #define ADC_VERID_RES_MASK (0x1U) | ||
| 334 | #define ADC_VERID_RES_SHIFT (0U) | ||
| 335 | /*! RES - Resolution | ||
| 336 | * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. | ||
| 337 | * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. | ||
| 338 | */ | ||
| 339 | #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) | ||
| 340 | #define ADC_VERID_DIFFEN_MASK (0x2U) | ||
| 341 | #define ADC_VERID_DIFFEN_SHIFT (1U) | ||
| 342 | /*! DIFFEN - Differential Supported | ||
| 343 | * 0b0..Differential operation not supported. | ||
| 344 | * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. | ||
| 345 | */ | ||
| 346 | #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) | ||
| 347 | #define ADC_VERID_MVI_MASK (0x8U) | ||
| 348 | #define ADC_VERID_MVI_SHIFT (3U) | ||
| 349 | /*! MVI - Multi Vref Implemented | ||
| 350 | * 0b0..Single voltage reference high (VREFH) input supported. | ||
| 351 | * 0b1..Multiple voltage reference high (VREFH) inputs supported. | ||
| 352 | */ | ||
| 353 | #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) | ||
| 354 | #define ADC_VERID_CSW_MASK (0x70U) | ||
| 355 | #define ADC_VERID_CSW_SHIFT (4U) | ||
| 356 | /*! CSW - Channel Scale Width | ||
| 357 | * 0b000..Channel scaling not supported. | ||
| 358 | * 0b001..Channel scaling supported. 1-bit CSCALE control field. | ||
| 359 | * 0b110..Channel scaling supported. 6-bit CSCALE control field. | ||
| 360 | */ | ||
| 361 | #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) | ||
| 362 | #define ADC_VERID_VR1RNGI_MASK (0x100U) | ||
| 363 | #define ADC_VERID_VR1RNGI_SHIFT (8U) | ||
| 364 | /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented | ||
| 365 | * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. | ||
| 366 | * 0b1..Range control required. CFG[VREF1RNG] is implemented. | ||
| 367 | */ | ||
| 368 | #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) | ||
| 369 | #define ADC_VERID_IADCKI_MASK (0x200U) | ||
| 370 | #define ADC_VERID_IADCKI_SHIFT (9U) | ||
| 371 | /*! IADCKI - Internal ADC Clock implemented | ||
| 372 | * 0b0..Internal clock source not implemented. | ||
| 373 | * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. | ||
| 374 | */ | ||
| 375 | #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) | ||
| 376 | #define ADC_VERID_CALOFSI_MASK (0x400U) | ||
| 377 | #define ADC_VERID_CALOFSI_SHIFT (10U) | ||
| 378 | /*! CALOFSI - Calibration Function Implemented | ||
| 379 | * 0b0..Calibration Not Implemented. | ||
| 380 | * 0b1..Calibration Implemented. | ||
| 381 | */ | ||
| 382 | #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) | ||
| 383 | #define ADC_VERID_NUM_SEC_MASK (0x800U) | ||
| 384 | #define ADC_VERID_NUM_SEC_SHIFT (11U) | ||
| 385 | /*! NUM_SEC - Number of Single Ended Outputs Supported | ||
| 386 | * 0b0..This design supports one single ended conversion at a time. | ||
| 387 | * 0b1..This design supports two simultanious single ended conversions. | ||
| 388 | */ | ||
| 389 | #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) | ||
| 390 | #define ADC_VERID_NUM_FIFO_MASK (0x7000U) | ||
| 391 | #define ADC_VERID_NUM_FIFO_SHIFT (12U) | ||
| 392 | /*! NUM_FIFO - Number of FIFOs | ||
| 393 | * 0b000..N/A | ||
| 394 | * 0b001..This design supports one result FIFO. | ||
| 395 | * 0b010..This design supports two result FIFOs. | ||
| 396 | * 0b011..This design supports three result FIFOs. | ||
| 397 | * 0b100..This design supports four result FIFOs. | ||
| 398 | */ | ||
| 399 | #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) | ||
| 400 | #define ADC_VERID_MINOR_MASK (0xFF0000U) | ||
| 401 | #define ADC_VERID_MINOR_SHIFT (16U) | ||
| 402 | /*! MINOR - Minor Version Number | ||
| 403 | */ | ||
| 404 | #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) | ||
| 405 | #define ADC_VERID_MAJOR_MASK (0xFF000000U) | ||
| 406 | #define ADC_VERID_MAJOR_SHIFT (24U) | ||
| 407 | /*! MAJOR - Major Version Number | ||
| 408 | */ | ||
| 409 | #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) | ||
| 410 | /*! @} */ | ||
| 411 | |||
| 412 | /*! @name PARAM - Parameter Register */ | ||
| 413 | /*! @{ */ | ||
| 414 | #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) | ||
| 415 | #define ADC_PARAM_TRIG_NUM_SHIFT (0U) | ||
| 416 | /*! TRIG_NUM - Trigger Number | ||
| 417 | */ | ||
| 418 | #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) | ||
| 419 | #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) | ||
| 420 | #define ADC_PARAM_FIFOSIZE_SHIFT (8U) | ||
| 421 | /*! FIFOSIZE - Result FIFO Depth | ||
| 422 | * 0b00000001..Result FIFO depth = 1 dataword. | ||
| 423 | * 0b00000100..Result FIFO depth = 4 datawords. | ||
| 424 | * 0b00001000..Result FIFO depth = 8 datawords. | ||
| 425 | * 0b00010000..Result FIFO depth = 16 datawords. | ||
| 426 | * 0b00100000..Result FIFO depth = 32 datawords. | ||
| 427 | * 0b01000000..Result FIFO depth = 64 datawords. | ||
| 428 | */ | ||
| 429 | #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) | ||
| 430 | #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) | ||
| 431 | #define ADC_PARAM_CV_NUM_SHIFT (16U) | ||
| 432 | /*! CV_NUM - Compare Value Number | ||
| 433 | */ | ||
| 434 | #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) | ||
| 435 | #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) | ||
| 436 | #define ADC_PARAM_CMD_NUM_SHIFT (24U) | ||
| 437 | /*! CMD_NUM - Command Buffer Number | ||
| 438 | */ | ||
| 439 | #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) | ||
| 440 | /*! @} */ | ||
| 441 | |||
| 442 | /*! @name CTRL - ADC Control Register */ | ||
| 443 | /*! @{ */ | ||
| 444 | #define ADC_CTRL_ADCEN_MASK (0x1U) | ||
| 445 | #define ADC_CTRL_ADCEN_SHIFT (0U) | ||
| 446 | /*! ADCEN - ADC Enable | ||
| 447 | * 0b0..ADC is disabled. | ||
| 448 | * 0b1..ADC is enabled. | ||
| 449 | */ | ||
| 450 | #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) | ||
| 451 | #define ADC_CTRL_RST_MASK (0x2U) | ||
| 452 | #define ADC_CTRL_RST_SHIFT (1U) | ||
| 453 | /*! RST - Software Reset | ||
| 454 | * 0b0..ADC logic is not reset. | ||
| 455 | * 0b1..ADC logic is reset. | ||
| 456 | */ | ||
| 457 | #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) | ||
| 458 | #define ADC_CTRL_DOZEN_MASK (0x4U) | ||
| 459 | #define ADC_CTRL_DOZEN_SHIFT (2U) | ||
| 460 | /*! DOZEN - Doze Enable | ||
| 461 | * 0b0..ADC is enabled in Doze mode. | ||
| 462 | * 0b1..ADC is disabled in Doze mode. | ||
| 463 | */ | ||
| 464 | #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) | ||
| 465 | #define ADC_CTRL_CAL_REQ_MASK (0x8U) | ||
| 466 | #define ADC_CTRL_CAL_REQ_SHIFT (3U) | ||
| 467 | /*! CAL_REQ - Auto-Calibration Request | ||
| 468 | * 0b0..No request for auto-calibration has been made. | ||
| 469 | * 0b1..A request for auto-calibration has been made | ||
| 470 | */ | ||
| 471 | #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) | ||
| 472 | #define ADC_CTRL_CALOFS_MASK (0x10U) | ||
| 473 | #define ADC_CTRL_CALOFS_SHIFT (4U) | ||
| 474 | /*! CALOFS - Configure for offset calibration function | ||
| 475 | * 0b0..Calibration function disabled | ||
| 476 | * 0b1..Request for offset calibration function | ||
| 477 | */ | ||
| 478 | #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) | ||
| 479 | #define ADC_CTRL_RSTFIFO0_MASK (0x100U) | ||
| 480 | #define ADC_CTRL_RSTFIFO0_SHIFT (8U) | ||
| 481 | /*! RSTFIFO0 - Reset FIFO 0 | ||
| 482 | * 0b0..No effect. | ||
| 483 | * 0b1..FIFO 0 is reset. | ||
| 484 | */ | ||
| 485 | #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) | ||
| 486 | #define ADC_CTRL_RSTFIFO1_MASK (0x200U) | ||
| 487 | #define ADC_CTRL_RSTFIFO1_SHIFT (9U) | ||
| 488 | /*! RSTFIFO1 - Reset FIFO 1 | ||
| 489 | * 0b0..No effect. | ||
| 490 | * 0b1..FIFO 1 is reset. | ||
| 491 | */ | ||
| 492 | #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) | ||
| 493 | #define ADC_CTRL_CAL_AVGS_MASK (0x70000U) | ||
| 494 | #define ADC_CTRL_CAL_AVGS_SHIFT (16U) | ||
| 495 | /*! CAL_AVGS - Auto-Calibration Averages | ||
| 496 | * 0b000..Single conversion. | ||
| 497 | * 0b001..2 conversions averaged. | ||
| 498 | * 0b010..4 conversions averaged. | ||
| 499 | * 0b011..8 conversions averaged. | ||
| 500 | * 0b100..16 conversions averaged. | ||
| 501 | * 0b101..32 conversions averaged. | ||
| 502 | * 0b110..64 conversions averaged. | ||
| 503 | * 0b111..128 conversions averaged. | ||
| 504 | */ | ||
| 505 | #define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) | ||
| 506 | /*! @} */ | ||
| 507 | |||
| 508 | /*! @name STAT - ADC Status Register */ | ||
| 509 | /*! @{ */ | ||
| 510 | #define ADC_STAT_RDY0_MASK (0x1U) | ||
| 511 | #define ADC_STAT_RDY0_SHIFT (0U) | ||
| 512 | /*! RDY0 - Result FIFO 0 Ready Flag | ||
| 513 | * 0b0..Result FIFO 0 data level not above watermark level. | ||
| 514 | * 0b1..Result FIFO 0 holding data above watermark level. | ||
| 515 | */ | ||
| 516 | #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) | ||
| 517 | #define ADC_STAT_FOF0_MASK (0x2U) | ||
| 518 | #define ADC_STAT_FOF0_SHIFT (1U) | ||
| 519 | /*! FOF0 - Result FIFO 0 Overflow Flag | ||
| 520 | * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 521 | * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. | ||
| 522 | */ | ||
| 523 | #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) | ||
| 524 | #define ADC_STAT_RDY1_MASK (0x4U) | ||
| 525 | #define ADC_STAT_RDY1_SHIFT (2U) | ||
| 526 | /*! RDY1 - Result FIFO1 Ready Flag | ||
| 527 | * 0b0..Result FIFO1 data level not above watermark level. | ||
| 528 | * 0b1..Result FIFO1 holding data above watermark level. | ||
| 529 | */ | ||
| 530 | #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) | ||
| 531 | #define ADC_STAT_FOF1_MASK (0x8U) | ||
| 532 | #define ADC_STAT_FOF1_SHIFT (3U) | ||
| 533 | /*! FOF1 - Result FIFO1 Overflow Flag | ||
| 534 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 535 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 536 | */ | ||
| 537 | #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) | ||
| 538 | #define ADC_STAT_TEXC_INT_MASK (0x100U) | ||
| 539 | #define ADC_STAT_TEXC_INT_SHIFT (8U) | ||
| 540 | /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception | ||
| 541 | * 0b0..No trigger exceptions have occurred. | ||
| 542 | * 0b1..A trigger exception has occurred and is pending acknowledgement. | ||
| 543 | */ | ||
| 544 | #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) | ||
| 545 | #define ADC_STAT_TCOMP_INT_MASK (0x200U) | ||
| 546 | #define ADC_STAT_TCOMP_INT_SHIFT (9U) | ||
| 547 | /*! TCOMP_INT - Interrupt Flag For Trigger Completion | ||
| 548 | * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. | ||
| 549 | * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. | ||
| 550 | */ | ||
| 551 | #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) | ||
| 552 | #define ADC_STAT_CAL_RDY_MASK (0x400U) | ||
| 553 | #define ADC_STAT_CAL_RDY_SHIFT (10U) | ||
| 554 | /*! CAL_RDY - Calibration Ready | ||
| 555 | * 0b0..Calibration is incomplete or hasn't been ran. | ||
| 556 | * 0b1..The ADC is calibrated. | ||
| 557 | */ | ||
| 558 | #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) | ||
| 559 | #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) | ||
| 560 | #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) | ||
| 561 | /*! ADC_ACTIVE - ADC Active | ||
| 562 | * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. | ||
| 563 | * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. | ||
| 564 | */ | ||
| 565 | #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) | ||
| 566 | #define ADC_STAT_TRGACT_MASK (0xF0000U) | ||
| 567 | #define ADC_STAT_TRGACT_SHIFT (16U) | ||
| 568 | /*! TRGACT - Trigger Active | ||
| 569 | * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. | ||
| 570 | * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. | ||
| 571 | * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. | ||
| 572 | * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. | ||
| 573 | */ | ||
| 574 | #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) | ||
| 575 | #define ADC_STAT_CMDACT_MASK (0xF000000U) | ||
| 576 | #define ADC_STAT_CMDACT_SHIFT (24U) | ||
| 577 | /*! CMDACT - Command Active | ||
| 578 | * 0b0000..No command is currently in progress. | ||
| 579 | * 0b0001..Command 1 currently being executed. | ||
| 580 | * 0b0010..Command 2 currently being executed. | ||
| 581 | * 0b0011-0b1111..Associated command number is currently being executed. | ||
| 582 | */ | ||
| 583 | #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) | ||
| 584 | /*! @} */ | ||
| 585 | |||
| 586 | /*! @name IE - Interrupt Enable Register */ | ||
| 587 | /*! @{ */ | ||
| 588 | #define ADC_IE_FWMIE0_MASK (0x1U) | ||
| 589 | #define ADC_IE_FWMIE0_SHIFT (0U) | ||
| 590 | /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable | ||
| 591 | * 0b0..FIFO 0 watermark interrupts are not enabled. | ||
| 592 | * 0b1..FIFO 0 watermark interrupts are enabled. | ||
| 593 | */ | ||
| 594 | #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) | ||
| 595 | #define ADC_IE_FOFIE0_MASK (0x2U) | ||
| 596 | #define ADC_IE_FOFIE0_SHIFT (1U) | ||
| 597 | /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable | ||
| 598 | * 0b0..FIFO 0 overflow interrupts are not enabled. | ||
| 599 | * 0b1..FIFO 0 overflow interrupts are enabled. | ||
| 600 | */ | ||
| 601 | #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) | ||
| 602 | #define ADC_IE_FWMIE1_MASK (0x4U) | ||
| 603 | #define ADC_IE_FWMIE1_SHIFT (2U) | ||
| 604 | /*! FWMIE1 - FIFO1 Watermark Interrupt Enable | ||
| 605 | * 0b0..FIFO1 watermark interrupts are not enabled. | ||
| 606 | * 0b1..FIFO1 watermark interrupts are enabled. | ||
| 607 | */ | ||
| 608 | #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) | ||
| 609 | #define ADC_IE_FOFIE1_MASK (0x8U) | ||
| 610 | #define ADC_IE_FOFIE1_SHIFT (3U) | ||
| 611 | /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable | ||
| 612 | * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 613 | * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. | ||
| 614 | */ | ||
| 615 | #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) | ||
| 616 | #define ADC_IE_TEXC_IE_MASK (0x100U) | ||
| 617 | #define ADC_IE_TEXC_IE_SHIFT (8U) | ||
| 618 | /*! TEXC_IE - Trigger Exception Interrupt Enable | ||
| 619 | * 0b0..Trigger exception interrupts are disabled. | ||
| 620 | * 0b1..Trigger exception interrupts are enabled. | ||
| 621 | */ | ||
| 622 | #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) | ||
| 623 | #define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) | ||
| 624 | #define ADC_IE_TCOMP_IE_SHIFT (16U) | ||
| 625 | /*! TCOMP_IE - Trigger Completion Interrupt Enable | ||
| 626 | * 0b0000000000000000..Trigger completion interrupts are disabled. | ||
| 627 | * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. | ||
| 628 | * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. | ||
| 629 | * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. | ||
| 630 | * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. | ||
| 631 | */ | ||
| 632 | #define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) | ||
| 633 | /*! @} */ | ||
| 634 | |||
| 635 | /*! @name DE - DMA Enable Register */ | ||
| 636 | /*! @{ */ | ||
| 637 | #define ADC_DE_FWMDE0_MASK (0x1U) | ||
| 638 | #define ADC_DE_FWMDE0_SHIFT (0U) | ||
| 639 | /*! FWMDE0 - FIFO 0 Watermark DMA Enable | ||
| 640 | * 0b0..DMA request disabled. | ||
| 641 | * 0b1..DMA request enabled. | ||
| 642 | */ | ||
| 643 | #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) | ||
| 644 | #define ADC_DE_FWMDE1_MASK (0x2U) | ||
| 645 | #define ADC_DE_FWMDE1_SHIFT (1U) | ||
| 646 | /*! FWMDE1 - FIFO1 Watermark DMA Enable | ||
| 647 | * 0b0..DMA request disabled. | ||
| 648 | * 0b1..DMA request enabled. | ||
| 649 | */ | ||
| 650 | #define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) | ||
| 651 | /*! @} */ | ||
| 652 | |||
| 653 | /*! @name CFG - ADC Configuration Register */ | ||
| 654 | /*! @{ */ | ||
| 655 | #define ADC_CFG_TPRICTRL_MASK (0x3U) | ||
| 656 | #define ADC_CFG_TPRICTRL_SHIFT (0U) | ||
| 657 | /*! TPRICTRL - ADC trigger priority control | ||
| 658 | * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted | ||
| 659 | * and the new command specified by the trigger is started. | ||
| 660 | * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after | ||
| 661 | * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. | ||
| 662 | * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. | ||
| 663 | * 0b10..If a higher priority trigger is received during command processing, the current command will be | ||
| 664 | * completed (averaging, looping, compare) before servicing the higher priority trigger. | ||
| 665 | * 0b11..RESERVED | ||
| 666 | */ | ||
| 667 | #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) | ||
| 668 | #define ADC_CFG_PWRSEL_MASK (0x30U) | ||
| 669 | #define ADC_CFG_PWRSEL_SHIFT (4U) | ||
| 670 | /*! PWRSEL - Power Configuration Select | ||
| 671 | * 0b00..Lowest power setting. | ||
| 672 | * 0b01..Higher power setting than 0b0. | ||
| 673 | * 0b10..Higher power setting than 0b1. | ||
| 674 | * 0b11..Highest power setting. | ||
| 675 | */ | ||
| 676 | #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) | ||
| 677 | #define ADC_CFG_REFSEL_MASK (0xC0U) | ||
| 678 | #define ADC_CFG_REFSEL_SHIFT (6U) | ||
| 679 | /*! REFSEL - Voltage Reference Selection | ||
| 680 | * 0b00..(Default) Option 1 setting. | ||
| 681 | * 0b01..Option 2 setting. | ||
| 682 | * 0b10..Option 3 setting. | ||
| 683 | * 0b11..Reserved | ||
| 684 | */ | ||
| 685 | #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) | ||
| 686 | #define ADC_CFG_TRES_MASK (0x100U) | ||
| 687 | #define ADC_CFG_TRES_SHIFT (8U) | ||
| 688 | /*! TRES - Trigger Resume Enable | ||
| 689 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. | ||
| 690 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. | ||
| 691 | */ | ||
| 692 | #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) | ||
| 693 | #define ADC_CFG_TCMDRES_MASK (0x200U) | ||
| 694 | #define ADC_CFG_TCMDRES_SHIFT (9U) | ||
| 695 | /*! TCMDRES - Trigger Command Resume | ||
| 696 | * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. | ||
| 697 | * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. | ||
| 698 | */ | ||
| 699 | #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) | ||
| 700 | #define ADC_CFG_HPT_EXDI_MASK (0x400U) | ||
| 701 | #define ADC_CFG_HPT_EXDI_SHIFT (10U) | ||
| 702 | /*! HPT_EXDI - High Priority Trigger Exception Disable | ||
| 703 | * 0b0..High priority trigger exceptions are enabled. | ||
| 704 | * 0b1..High priority trigger exceptions are disabled. | ||
| 705 | */ | ||
| 706 | #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) | ||
| 707 | #define ADC_CFG_PUDLY_MASK (0xFF0000U) | ||
| 708 | #define ADC_CFG_PUDLY_SHIFT (16U) | ||
| 709 | /*! PUDLY - Power Up Delay | ||
| 710 | */ | ||
| 711 | #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) | ||
| 712 | #define ADC_CFG_PWREN_MASK (0x10000000U) | ||
| 713 | #define ADC_CFG_PWREN_SHIFT (28U) | ||
| 714 | /*! PWREN - ADC Analog Pre-Enable | ||
| 715 | * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. | ||
| 716 | * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost | ||
| 717 | * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN | ||
| 718 | * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. | ||
| 719 | * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be | ||
| 720 | * executed. | ||
| 721 | */ | ||
| 722 | #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) | ||
| 723 | /*! @} */ | ||
| 724 | |||
| 725 | /*! @name PAUSE - ADC Pause Register */ | ||
| 726 | /*! @{ */ | ||
| 727 | #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) | ||
| 728 | #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) | ||
| 729 | /*! PAUSEDLY - Pause Delay | ||
| 730 | */ | ||
| 731 | #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) | ||
| 732 | #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) | ||
| 733 | #define ADC_PAUSE_PAUSEEN_SHIFT (31U) | ||
| 734 | /*! PAUSEEN - PAUSE Option Enable | ||
| 735 | * 0b0..Pause operation disabled | ||
| 736 | * 0b1..Pause operation enabled | ||
| 737 | */ | ||
| 738 | #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) | ||
| 739 | /*! @} */ | ||
| 740 | |||
| 741 | /*! @name SWTRIG - Software Trigger Register */ | ||
| 742 | /*! @{ */ | ||
| 743 | #define ADC_SWTRIG_SWT0_MASK (0x1U) | ||
| 744 | #define ADC_SWTRIG_SWT0_SHIFT (0U) | ||
| 745 | /*! SWT0 - Software trigger 0 event | ||
| 746 | * 0b0..No trigger 0 event generated. | ||
| 747 | * 0b1..Trigger 0 event generated. | ||
| 748 | */ | ||
| 749 | #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) | ||
| 750 | #define ADC_SWTRIG_SWT1_MASK (0x2U) | ||
| 751 | #define ADC_SWTRIG_SWT1_SHIFT (1U) | ||
| 752 | /*! SWT1 - Software trigger 1 event | ||
| 753 | * 0b0..No trigger 1 event generated. | ||
| 754 | * 0b1..Trigger 1 event generated. | ||
| 755 | */ | ||
| 756 | #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) | ||
| 757 | #define ADC_SWTRIG_SWT2_MASK (0x4U) | ||
| 758 | #define ADC_SWTRIG_SWT2_SHIFT (2U) | ||
| 759 | /*! SWT2 - Software trigger 2 event | ||
| 760 | * 0b0..No trigger 2 event generated. | ||
| 761 | * 0b1..Trigger 2 event generated. | ||
| 762 | */ | ||
| 763 | #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) | ||
| 764 | #define ADC_SWTRIG_SWT3_MASK (0x8U) | ||
| 765 | #define ADC_SWTRIG_SWT3_SHIFT (3U) | ||
| 766 | /*! SWT3 - Software trigger 3 event | ||
| 767 | * 0b0..No trigger 3 event generated. | ||
| 768 | * 0b1..Trigger 3 event generated. | ||
| 769 | */ | ||
| 770 | #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) | ||
| 771 | #define ADC_SWTRIG_SWT4_MASK (0x10U) | ||
| 772 | #define ADC_SWTRIG_SWT4_SHIFT (4U) | ||
| 773 | /*! SWT4 - Software trigger 4 event | ||
| 774 | * 0b0..No trigger 4 event generated. | ||
| 775 | * 0b1..Trigger 4 event generated. | ||
| 776 | */ | ||
| 777 | #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) | ||
| 778 | #define ADC_SWTRIG_SWT5_MASK (0x20U) | ||
| 779 | #define ADC_SWTRIG_SWT5_SHIFT (5U) | ||
| 780 | /*! SWT5 - Software trigger 5 event | ||
| 781 | * 0b0..No trigger 5 event generated. | ||
| 782 | * 0b1..Trigger 5 event generated. | ||
| 783 | */ | ||
| 784 | #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) | ||
| 785 | #define ADC_SWTRIG_SWT6_MASK (0x40U) | ||
| 786 | #define ADC_SWTRIG_SWT6_SHIFT (6U) | ||
| 787 | /*! SWT6 - Software trigger 6 event | ||
| 788 | * 0b0..No trigger 6 event generated. | ||
| 789 | * 0b1..Trigger 6 event generated. | ||
| 790 | */ | ||
| 791 | #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) | ||
| 792 | #define ADC_SWTRIG_SWT7_MASK (0x80U) | ||
| 793 | #define ADC_SWTRIG_SWT7_SHIFT (7U) | ||
| 794 | /*! SWT7 - Software trigger 7 event | ||
| 795 | * 0b0..No trigger 7 event generated. | ||
| 796 | * 0b1..Trigger 7 event generated. | ||
| 797 | */ | ||
| 798 | #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) | ||
| 799 | #define ADC_SWTRIG_SWT8_MASK (0x100U) | ||
| 800 | #define ADC_SWTRIG_SWT8_SHIFT (8U) | ||
| 801 | /*! SWT8 - Software trigger 8 event | ||
| 802 | * 0b0..No trigger 8 event generated. | ||
| 803 | * 0b1..Trigger 8 event generated. | ||
| 804 | */ | ||
| 805 | #define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) | ||
| 806 | #define ADC_SWTRIG_SWT9_MASK (0x200U) | ||
| 807 | #define ADC_SWTRIG_SWT9_SHIFT (9U) | ||
| 808 | /*! SWT9 - Software trigger 9 event | ||
| 809 | * 0b0..No trigger 9 event generated. | ||
| 810 | * 0b1..Trigger 9 event generated. | ||
| 811 | */ | ||
| 812 | #define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) | ||
| 813 | #define ADC_SWTRIG_SWT10_MASK (0x400U) | ||
| 814 | #define ADC_SWTRIG_SWT10_SHIFT (10U) | ||
| 815 | /*! SWT10 - Software trigger 10 event | ||
| 816 | * 0b0..No trigger 10 event generated. | ||
| 817 | * 0b1..Trigger 10 event generated. | ||
| 818 | */ | ||
| 819 | #define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) | ||
| 820 | #define ADC_SWTRIG_SWT11_MASK (0x800U) | ||
| 821 | #define ADC_SWTRIG_SWT11_SHIFT (11U) | ||
| 822 | /*! SWT11 - Software trigger 11 event | ||
| 823 | * 0b0..No trigger 11 event generated. | ||
| 824 | * 0b1..Trigger 11 event generated. | ||
| 825 | */ | ||
| 826 | #define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) | ||
| 827 | #define ADC_SWTRIG_SWT12_MASK (0x1000U) | ||
| 828 | #define ADC_SWTRIG_SWT12_SHIFT (12U) | ||
| 829 | /*! SWT12 - Software trigger 12 event | ||
| 830 | * 0b0..No trigger 12 event generated. | ||
| 831 | * 0b1..Trigger 12 event generated. | ||
| 832 | */ | ||
| 833 | #define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) | ||
| 834 | #define ADC_SWTRIG_SWT13_MASK (0x2000U) | ||
| 835 | #define ADC_SWTRIG_SWT13_SHIFT (13U) | ||
| 836 | /*! SWT13 - Software trigger 13 event | ||
| 837 | * 0b0..No trigger 13 event generated. | ||
| 838 | * 0b1..Trigger 13 event generated. | ||
| 839 | */ | ||
| 840 | #define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) | ||
| 841 | #define ADC_SWTRIG_SWT14_MASK (0x4000U) | ||
| 842 | #define ADC_SWTRIG_SWT14_SHIFT (14U) | ||
| 843 | /*! SWT14 - Software trigger 14 event | ||
| 844 | * 0b0..No trigger 14 event generated. | ||
| 845 | * 0b1..Trigger 14 event generated. | ||
| 846 | */ | ||
| 847 | #define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) | ||
| 848 | #define ADC_SWTRIG_SWT15_MASK (0x8000U) | ||
| 849 | #define ADC_SWTRIG_SWT15_SHIFT (15U) | ||
| 850 | /*! SWT15 - Software trigger 15 event | ||
| 851 | * 0b0..No trigger 15 event generated. | ||
| 852 | * 0b1..Trigger 15 event generated. | ||
| 853 | */ | ||
| 854 | #define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) | ||
| 855 | /*! @} */ | ||
| 856 | |||
| 857 | /*! @name TSTAT - Trigger Status Register */ | ||
| 858 | /*! @{ */ | ||
| 859 | #define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) | ||
| 860 | #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) | ||
| 861 | /*! TEXC_NUM - Trigger Exception Number | ||
| 862 | * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. | ||
| 863 | * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. | ||
| 864 | * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. | ||
| 865 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. | ||
| 866 | * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. | ||
| 867 | */ | ||
| 868 | #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) | ||
| 869 | #define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) | ||
| 870 | #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) | ||
| 871 | /*! TCOMP_FLAG - Trigger Completion Flag | ||
| 872 | * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. | ||
| 873 | * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. | ||
| 874 | * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. | ||
| 875 | * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. | ||
| 876 | * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. | ||
| 877 | */ | ||
| 878 | #define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) | ||
| 879 | /*! @} */ | ||
| 880 | |||
| 881 | /*! @name OFSTRIM - ADC Offset Trim Register */ | ||
| 882 | /*! @{ */ | ||
| 883 | #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) | ||
| 884 | #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) | ||
| 885 | /*! OFSTRIM_A - Trim for offset | ||
| 886 | */ | ||
| 887 | #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) | ||
| 888 | #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) | ||
| 889 | #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) | ||
| 890 | /*! OFSTRIM_B - Trim for offset | ||
| 891 | */ | ||
| 892 | #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) | ||
| 893 | /*! @} */ | ||
| 894 | |||
| 895 | /*! @name TCTRL - Trigger Control Register */ | ||
| 896 | /*! @{ */ | ||
| 897 | #define ADC_TCTRL_HTEN_MASK (0x1U) | ||
| 898 | #define ADC_TCTRL_HTEN_SHIFT (0U) | ||
| 899 | /*! HTEN - Trigger enable | ||
| 900 | * 0b0..Hardware trigger source disabled | ||
| 901 | * 0b1..Hardware trigger source enabled | ||
| 902 | */ | ||
| 903 | #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) | ||
| 904 | #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) | ||
| 905 | #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) | ||
| 906 | /*! FIFO_SEL_A - SAR Result Destination For Channel A | ||
| 907 | * 0b0..Result written to FIFO 0 | ||
| 908 | * 0b1..Result written to FIFO 1 | ||
| 909 | */ | ||
| 910 | #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) | ||
| 911 | #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) | ||
| 912 | #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) | ||
| 913 | /*! FIFO_SEL_B - SAR Result Destination For Channel B | ||
| 914 | * 0b0..Result written to FIFO 0 | ||
| 915 | * 0b1..Result written to FIFO 1 | ||
| 916 | */ | ||
| 917 | #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) | ||
| 918 | #define ADC_TCTRL_TPRI_MASK (0xF00U) | ||
| 919 | #define ADC_TCTRL_TPRI_SHIFT (8U) | ||
| 920 | /*! TPRI - Trigger priority setting | ||
| 921 | * 0b0000..Set to highest priority, Level 1 | ||
| 922 | * 0b0001-0b1110..Set to corresponding priority level | ||
| 923 | * 0b1111..Set to lowest priority, Level 16 | ||
| 924 | */ | ||
| 925 | #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) | ||
| 926 | #define ADC_TCTRL_RSYNC_MASK (0x8000U) | ||
| 927 | #define ADC_TCTRL_RSYNC_SHIFT (15U) | ||
| 928 | /*! RSYNC - Trigger Resync | ||
| 929 | */ | ||
| 930 | #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) | ||
| 931 | #define ADC_TCTRL_TDLY_MASK (0xF0000U) | ||
| 932 | #define ADC_TCTRL_TDLY_SHIFT (16U) | ||
| 933 | /*! TDLY - Trigger delay select | ||
| 934 | */ | ||
| 935 | #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) | ||
| 936 | #define ADC_TCTRL_TCMD_MASK (0xF000000U) | ||
| 937 | #define ADC_TCTRL_TCMD_SHIFT (24U) | ||
| 938 | /*! TCMD - Trigger command select | ||
| 939 | * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. | ||
| 940 | * 0b0001..CMD1 is executed | ||
| 941 | * 0b0010-0b1110..Corresponding CMD is executed | ||
| 942 | * 0b1111..CMD15 is executed | ||
| 943 | */ | ||
| 944 | #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) | ||
| 945 | /*! @} */ | ||
| 946 | |||
| 947 | /* The count of ADC_TCTRL */ | ||
| 948 | #define ADC_TCTRL_COUNT (16U) | ||
| 949 | |||
| 950 | /*! @name FCTRL - FIFO Control Register */ | ||
| 951 | /*! @{ */ | ||
| 952 | #define ADC_FCTRL_FCOUNT_MASK (0x1FU) | ||
| 953 | #define ADC_FCTRL_FCOUNT_SHIFT (0U) | ||
| 954 | /*! FCOUNT - Result FIFO counter | ||
| 955 | */ | ||
| 956 | #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) | ||
| 957 | #define ADC_FCTRL_FWMARK_MASK (0xF0000U) | ||
| 958 | #define ADC_FCTRL_FWMARK_SHIFT (16U) | ||
| 959 | /*! FWMARK - Watermark level selection | ||
| 960 | */ | ||
| 961 | #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) | ||
| 962 | /*! @} */ | ||
| 963 | |||
| 964 | /* The count of ADC_FCTRL */ | ||
| 965 | #define ADC_FCTRL_COUNT (2U) | ||
| 966 | |||
| 967 | /*! @name GCC - Gain Calibration Control */ | ||
| 968 | /*! @{ */ | ||
| 969 | #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) | ||
| 970 | #define ADC_GCC_GAIN_CAL_SHIFT (0U) | ||
| 971 | /*! GAIN_CAL - Gain Calibration Value | ||
| 972 | */ | ||
| 973 | #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) | ||
| 974 | #define ADC_GCC_RDY_MASK (0x1000000U) | ||
| 975 | #define ADC_GCC_RDY_SHIFT (24U) | ||
| 976 | /*! RDY - Gain Calibration Value Valid | ||
| 977 | * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. | ||
| 978 | * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. | ||
| 979 | */ | ||
| 980 | #define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) | ||
| 981 | /*! @} */ | ||
| 982 | |||
| 983 | /* The count of ADC_GCC */ | ||
| 984 | #define ADC_GCC_COUNT (2U) | ||
| 985 | |||
| 986 | /*! @name GCR - Gain Calculation Result */ | ||
| 987 | /*! @{ */ | ||
| 988 | #define ADC_GCR_GCALR_MASK (0xFFFFU) | ||
| 989 | #define ADC_GCR_GCALR_SHIFT (0U) | ||
| 990 | /*! GCALR - Gain Calculation Result | ||
| 991 | */ | ||
| 992 | #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) | ||
| 993 | #define ADC_GCR_RDY_MASK (0x1000000U) | ||
| 994 | #define ADC_GCR_RDY_SHIFT (24U) | ||
| 995 | /*! RDY - Gain Calculation Ready | ||
| 996 | * 0b0..The gain offset calculation value is invalid. | ||
| 997 | * 0b1..The gain calibration value is valid. | ||
| 998 | */ | ||
| 999 | #define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) | ||
| 1000 | /*! @} */ | ||
| 1001 | |||
| 1002 | /* The count of ADC_GCR */ | ||
| 1003 | #define ADC_GCR_COUNT (2U) | ||
| 1004 | |||
| 1005 | /*! @name CMDL - ADC Command Low Buffer Register */ | ||
| 1006 | /*! @{ */ | ||
| 1007 | #define ADC_CMDL_ADCH_MASK (0x1FU) | ||
| 1008 | #define ADC_CMDL_ADCH_SHIFT (0U) | ||
| 1009 | /*! ADCH - Input channel select | ||
| 1010 | * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. | ||
| 1011 | * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. | ||
| 1012 | * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. | ||
| 1013 | * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. | ||
| 1014 | * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. | ||
| 1015 | * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. | ||
| 1016 | * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. | ||
| 1017 | */ | ||
| 1018 | #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) | ||
| 1019 | #define ADC_CMDL_CTYPE_MASK (0x60U) | ||
| 1020 | #define ADC_CMDL_CTYPE_SHIFT (5U) | ||
| 1021 | /*! CTYPE - Conversion Type | ||
| 1022 | * 0b00..Single-Ended Mode. Only A side channel is converted. | ||
| 1023 | * 0b01..Single-Ended Mode. Only B side channel is converted. | ||
| 1024 | * 0b10..Differential Mode. A-B. | ||
| 1025 | * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. | ||
| 1026 | */ | ||
| 1027 | #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) | ||
| 1028 | #define ADC_CMDL_MODE_MASK (0x80U) | ||
| 1029 | #define ADC_CMDL_MODE_SHIFT (7U) | ||
| 1030 | /*! MODE - Select resolution of conversions | ||
| 1031 | * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. | ||
| 1032 | * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. | ||
| 1033 | */ | ||
| 1034 | #define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) | ||
| 1035 | /*! @} */ | ||
| 1036 | |||
| 1037 | /* The count of ADC_CMDL */ | ||
| 1038 | #define ADC_CMDL_COUNT (15U) | ||
| 1039 | |||
| 1040 | /*! @name CMDH - ADC Command High Buffer Register */ | ||
| 1041 | /*! @{ */ | ||
| 1042 | #define ADC_CMDH_CMPEN_MASK (0x3U) | ||
| 1043 | #define ADC_CMDH_CMPEN_SHIFT (0U) | ||
| 1044 | /*! CMPEN - Compare Function Enable | ||
| 1045 | * 0b00..Compare disabled. | ||
| 1046 | * 0b01..Reserved | ||
| 1047 | * 0b10..Compare enabled. Store on true. | ||
| 1048 | * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. | ||
| 1049 | */ | ||
| 1050 | #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) | ||
| 1051 | #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) | ||
| 1052 | #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) | ||
| 1053 | /*! WAIT_TRIG - Wait for trigger assertion before execution. | ||
| 1054 | * 0b0..This command will be automatically executed. | ||
| 1055 | * 0b1..The active trigger must be asserted again before executing this command. | ||
| 1056 | */ | ||
| 1057 | #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) | ||
| 1058 | #define ADC_CMDH_LWI_MASK (0x80U) | ||
| 1059 | #define ADC_CMDH_LWI_SHIFT (7U) | ||
| 1060 | /*! LWI - Loop with Increment | ||
| 1061 | * 0b0..Auto channel increment disabled | ||
| 1062 | * 0b1..Auto channel increment enabled | ||
| 1063 | */ | ||
| 1064 | #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) | ||
| 1065 | #define ADC_CMDH_STS_MASK (0x700U) | ||
| 1066 | #define ADC_CMDH_STS_SHIFT (8U) | ||
| 1067 | /*! STS - Sample Time Select | ||
| 1068 | * 0b000..Minimum sample time of 3 ADCK cycles. | ||
| 1069 | * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. | ||
| 1070 | * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. | ||
| 1071 | * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. | ||
| 1072 | * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. | ||
| 1073 | * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. | ||
| 1074 | * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. | ||
| 1075 | * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. | ||
| 1076 | */ | ||
| 1077 | #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) | ||
| 1078 | #define ADC_CMDH_AVGS_MASK (0x7000U) | ||
| 1079 | #define ADC_CMDH_AVGS_SHIFT (12U) | ||
| 1080 | /*! AVGS - Hardware Average Select | ||
| 1081 | * 0b000..Single conversion. | ||
| 1082 | * 0b001..2 conversions averaged. | ||
| 1083 | * 0b010..4 conversions averaged. | ||
| 1084 | * 0b011..8 conversions averaged. | ||
| 1085 | * 0b100..16 conversions averaged. | ||
| 1086 | * 0b101..32 conversions averaged. | ||
| 1087 | * 0b110..64 conversions averaged. | ||
| 1088 | * 0b111..128 conversions averaged. | ||
| 1089 | */ | ||
| 1090 | #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) | ||
| 1091 | #define ADC_CMDH_LOOP_MASK (0xF0000U) | ||
| 1092 | #define ADC_CMDH_LOOP_SHIFT (16U) | ||
| 1093 | /*! LOOP - Loop Count Select | ||
| 1094 | * 0b0000..Looping not enabled. Command executes 1 time. | ||
| 1095 | * 0b0001..Loop 1 time. Command executes 2 times. | ||
| 1096 | * 0b0010..Loop 2 times. Command executes 3 times. | ||
| 1097 | * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. | ||
| 1098 | * 0b1111..Loop 15 times. Command executes 16 times. | ||
| 1099 | */ | ||
| 1100 | #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) | ||
| 1101 | #define ADC_CMDH_NEXT_MASK (0xF000000U) | ||
| 1102 | #define ADC_CMDH_NEXT_SHIFT (24U) | ||
| 1103 | /*! NEXT - Next Command Select | ||
| 1104 | * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority | ||
| 1105 | * trigger pending, begin command associated with lower priority trigger. | ||
| 1106 | * 0b0001..Select CMD1 command buffer register as next command. | ||
| 1107 | * 0b0010-0b1110..Select corresponding CMD command buffer register as next command | ||
| 1108 | * 0b1111..Select CMD15 command buffer register as next command. | ||
| 1109 | */ | ||
| 1110 | #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) | ||
| 1111 | /*! @} */ | ||
| 1112 | |||
| 1113 | /* The count of ADC_CMDH */ | ||
| 1114 | #define ADC_CMDH_COUNT (15U) | ||
| 1115 | |||
| 1116 | /*! @name CV - Compare Value Register */ | ||
| 1117 | /*! @{ */ | ||
| 1118 | #define ADC_CV_CVL_MASK (0xFFFFU) | ||
| 1119 | #define ADC_CV_CVL_SHIFT (0U) | ||
| 1120 | /*! CVL - Compare Value Low. | ||
| 1121 | */ | ||
| 1122 | #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) | ||
| 1123 | #define ADC_CV_CVH_MASK (0xFFFF0000U) | ||
| 1124 | #define ADC_CV_CVH_SHIFT (16U) | ||
| 1125 | /*! CVH - Compare Value High. | ||
| 1126 | */ | ||
| 1127 | #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) | ||
| 1128 | /*! @} */ | ||
| 1129 | |||
| 1130 | /* The count of ADC_CV */ | ||
| 1131 | #define ADC_CV_COUNT (4U) | ||
| 1132 | |||
| 1133 | /*! @name RESFIFO - ADC Data Result FIFO Register */ | ||
| 1134 | /*! @{ */ | ||
| 1135 | #define ADC_RESFIFO_D_MASK (0xFFFFU) | ||
| 1136 | #define ADC_RESFIFO_D_SHIFT (0U) | ||
| 1137 | /*! D - Data result | ||
| 1138 | */ | ||
| 1139 | #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) | ||
| 1140 | #define ADC_RESFIFO_TSRC_MASK (0xF0000U) | ||
| 1141 | #define ADC_RESFIFO_TSRC_SHIFT (16U) | ||
| 1142 | /*! TSRC - Trigger Source | ||
| 1143 | * 0b0000..Trigger source 0 initiated this conversion. | ||
| 1144 | * 0b0001..Trigger source 1 initiated this conversion. | ||
| 1145 | * 0b0010-0b1110..Corresponding trigger source initiated this conversion. | ||
| 1146 | * 0b1111..Trigger source 15 initiated this conversion. | ||
| 1147 | */ | ||
| 1148 | #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) | ||
| 1149 | #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) | ||
| 1150 | #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) | ||
| 1151 | /*! LOOPCNT - Loop count value | ||
| 1152 | * 0b0000..Result is from initial conversion in command. | ||
| 1153 | * 0b0001..Result is from second conversion in command. | ||
| 1154 | * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. | ||
| 1155 | * 0b1111..Result is from 16th conversion in command. | ||
| 1156 | */ | ||
| 1157 | #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) | ||
| 1158 | #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) | ||
| 1159 | #define ADC_RESFIFO_CMDSRC_SHIFT (24U) | ||
| 1160 | /*! CMDSRC - Command Buffer Source | ||
| 1161 | * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state | ||
| 1162 | * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. | ||
| 1163 | * 0b0001..CMD1 buffer used as control settings for this conversion. | ||
| 1164 | * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. | ||
| 1165 | * 0b1111..CMD15 buffer used as control settings for this conversion. | ||
| 1166 | */ | ||
| 1167 | #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) | ||
| 1168 | #define ADC_RESFIFO_VALID_MASK (0x80000000U) | ||
| 1169 | #define ADC_RESFIFO_VALID_SHIFT (31U) | ||
| 1170 | /*! VALID - FIFO entry is valid | ||
| 1171 | * 0b0..FIFO is empty. Discard any read from RESFIFO. | ||
| 1172 | * 0b1..FIFO record read from RESFIFO is valid. | ||
| 1173 | */ | ||
| 1174 | #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) | ||
| 1175 | /*! @} */ | ||
| 1176 | |||
| 1177 | /* The count of ADC_RESFIFO */ | ||
| 1178 | #define ADC_RESFIFO_COUNT (2U) | ||
| 1179 | |||
| 1180 | /*! @name CAL_GAR - Calibration General A-Side Registers */ | ||
| 1181 | /*! @{ */ | ||
| 1182 | #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) | ||
| 1183 | #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) | ||
| 1184 | /*! CAL_GAR_VAL - Calibration General A Side Register Element | ||
| 1185 | */ | ||
| 1186 | #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) | ||
| 1187 | /*! @} */ | ||
| 1188 | |||
| 1189 | /* The count of ADC_CAL_GAR */ | ||
| 1190 | #define ADC_CAL_GAR_COUNT (33U) | ||
| 1191 | |||
| 1192 | /*! @name CAL_GBR - Calibration General B-Side Registers */ | ||
| 1193 | /*! @{ */ | ||
| 1194 | #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) | ||
| 1195 | #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) | ||
| 1196 | /*! CAL_GBR_VAL - Calibration General B Side Register Element | ||
| 1197 | */ | ||
| 1198 | #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) | ||
| 1199 | /*! @} */ | ||
| 1200 | |||
| 1201 | /* The count of ADC_CAL_GBR */ | ||
| 1202 | #define ADC_CAL_GBR_COUNT (33U) | ||
| 1203 | |||
| 1204 | |||
| 1205 | /*! | ||
| 1206 | * @} | ||
| 1207 | */ /* end of group ADC_Register_Masks */ | ||
| 1208 | |||
| 1209 | |||
| 1210 | /* ADC - Peripheral instance base addresses */ | ||
| 1211 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 1212 | /** Peripheral ADC0 base address */ | ||
| 1213 | #define ADC0_BASE (0x500A0000u) | ||
| 1214 | /** Peripheral ADC0 base address */ | ||
| 1215 | #define ADC0_BASE_NS (0x400A0000u) | ||
| 1216 | /** Peripheral ADC0 base pointer */ | ||
| 1217 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1218 | /** Peripheral ADC0 base pointer */ | ||
| 1219 | #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) | ||
| 1220 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1221 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1222 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1223 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1224 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1225 | #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } | ||
| 1226 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1227 | #define ADC_BASE_PTRS_NS { ADC0_NS } | ||
| 1228 | #else | ||
| 1229 | /** Peripheral ADC0 base address */ | ||
| 1230 | #define ADC0_BASE (0x400A0000u) | ||
| 1231 | /** Peripheral ADC0 base pointer */ | ||
| 1232 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1233 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1234 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1235 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1236 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1237 | #endif | ||
| 1238 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1239 | #define ADC_IRQS { ADC0_IRQn } | ||
| 1240 | |||
| 1241 | /*! | ||
| 1242 | * @} | ||
| 1243 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1244 | |||
| 1245 | |||
| 1246 | /* ---------------------------------------------------------------------------- | ||
| 1247 | -- AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1248 | ---------------------------------------------------------------------------- */ | ||
| 1249 | |||
| 1250 | /*! | ||
| 1251 | * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer | ||
| 1252 | * @{ | ||
| 1253 | */ | ||
| 1254 | |||
| 1255 | /** AHB_SECURE_CTRL - Register Layout Typedef */ | ||
| 1256 | typedef struct { | ||
| 1257 | struct { /* offset: 0x0, array step: 0x30 */ | ||
| 1258 | __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ | ||
| 1259 | uint8_t RESERVED_0[12]; | ||
| 1260 | __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ | ||
| 1261 | uint8_t RESERVED_1[12]; | ||
| 1262 | __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ | ||
| 1263 | } SEC_CTRL_FLASH_ROM[1]; | ||
| 1264 | struct { /* offset: 0x30, array step: 0x14 */ | ||
| 1265 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ | ||
| 1266 | uint8_t RESERVED_0[12]; | ||
| 1267 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ | ||
| 1268 | } SEC_CTRL_RAMX[1]; | ||
| 1269 | uint8_t RESERVED_0[12]; | ||
| 1270 | struct { /* offset: 0x50, array step: 0x14 */ | ||
| 1271 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */ | ||
| 1272 | uint8_t RESERVED_0[12]; | ||
| 1273 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */ | ||
| 1274 | } SEC_CTRL_RAM0[1]; | ||
| 1275 | uint8_t RESERVED_1[12]; | ||
| 1276 | struct { /* offset: 0x70, array step: 0x14 */ | ||
| 1277 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */ | ||
| 1278 | uint8_t RESERVED_0[12]; | ||
| 1279 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */ | ||
| 1280 | } SEC_CTRL_RAM1[1]; | ||
| 1281 | uint8_t RESERVED_2[12]; | ||
| 1282 | struct { /* offset: 0x90, array step: 0x14 */ | ||
| 1283 | __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */ | ||
| 1284 | uint8_t RESERVED_0[12]; | ||
| 1285 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */ | ||
| 1286 | } SEC_CTRL_RAM2[1]; | ||
| 1287 | uint8_t RESERVED_3[12]; | ||
| 1288 | struct { /* offset: 0xB0, array step: 0x14 */ | ||
| 1289 | __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0xB0, array step: 0x14 */ | ||
| 1290 | uint8_t RESERVED_0[12]; | ||
| 1291 | __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0xC0, array step: index*0x14, index2*0x4 */ | ||
| 1292 | } SEC_CTRL_USB_HS[1]; | ||
| 1293 | uint8_t RESERVED_4[12]; | ||
| 1294 | struct { /* offset: 0xD0, array step: 0x30 */ | ||
| 1295 | __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */ | ||
| 1296 | uint8_t RESERVED_0[12]; | ||
| 1297 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */ | ||
| 1298 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */ | ||
| 1299 | __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */ | ||
| 1300 | uint8_t RESERVED_1[4]; | ||
| 1301 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */ | ||
| 1302 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */ | ||
| 1303 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */ | ||
| 1304 | __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */ | ||
| 1305 | } SEC_CTRL_APB_BRIDGE[1]; | ||
| 1306 | __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */ | ||
| 1307 | __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */ | ||
| 1308 | uint8_t RESERVED_5[8]; | ||
| 1309 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */ | ||
| 1310 | __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */ | ||
| 1311 | uint8_t RESERVED_6[8]; | ||
| 1312 | struct { /* offset: 0x120, array step: 0x14 */ | ||
| 1313 | __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */ | ||
| 1314 | __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */ | ||
| 1315 | uint8_t RESERVED_0[8]; | ||
| 1316 | __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */ | ||
| 1317 | } SEC_CTRL_AHB_PORT9[1]; | ||
| 1318 | uint8_t RESERVED_7[3276]; | ||
| 1319 | __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ | ||
| 1320 | uint8_t RESERVED_8[88]; | ||
| 1321 | __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ | ||
| 1322 | uint8_t RESERVED_9[88]; | ||
| 1323 | __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ | ||
| 1324 | uint8_t RESERVED_10[124]; | ||
| 1325 | __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ | ||
| 1326 | __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ | ||
| 1327 | uint8_t RESERVED_11[52]; | ||
| 1328 | __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ | ||
| 1329 | uint8_t RESERVED_12[16]; | ||
| 1330 | __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ | ||
| 1331 | __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ | ||
| 1332 | uint8_t RESERVED_13[20]; | ||
| 1333 | __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ | ||
| 1334 | uint8_t RESERVED_14[8]; | ||
| 1335 | __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ | ||
| 1336 | __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ | ||
| 1337 | } AHB_SECURE_CTRL_Type; | ||
| 1338 | |||
| 1339 | /* ---------------------------------------------------------------------------- | ||
| 1340 | -- AHB_SECURE_CTRL Register Masks | ||
| 1341 | ---------------------------------------------------------------------------- */ | ||
| 1342 | |||
| 1343 | /*! | ||
| 1344 | * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks | ||
| 1345 | * @{ | ||
| 1346 | */ | ||
| 1347 | |||
| 1348 | /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ | ||
| 1349 | /*! @{ */ | ||
| 1350 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) | ||
| 1351 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) | ||
| 1352 | /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF | ||
| 1353 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1354 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1355 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1356 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1357 | */ | ||
| 1358 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) | ||
| 1359 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) | ||
| 1360 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) | ||
| 1361 | /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF | ||
| 1362 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1363 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1364 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1365 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1366 | */ | ||
| 1367 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) | ||
| 1368 | /*! @} */ | ||
| 1369 | |||
| 1370 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ | ||
| 1371 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) | ||
| 1372 | |||
| 1373 | /*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */ | ||
| 1374 | /*! @{ */ | ||
| 1375 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1376 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1377 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1378 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1379 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1380 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1381 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1382 | */ | ||
| 1383 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) | ||
| 1384 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1385 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1386 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1387 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1388 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1389 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1390 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1391 | */ | ||
| 1392 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) | ||
| 1393 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1394 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1395 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1396 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1397 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1398 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1399 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1400 | */ | ||
| 1401 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) | ||
| 1402 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1403 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1404 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1405 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1406 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1407 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1408 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1409 | */ | ||
| 1410 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) | ||
| 1411 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1412 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1413 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1414 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1415 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1416 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1417 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1418 | */ | ||
| 1419 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) | ||
| 1420 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1421 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1422 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1423 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1424 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1425 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1426 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1427 | */ | ||
| 1428 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) | ||
| 1429 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1430 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1431 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1432 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1433 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1434 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1435 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1436 | */ | ||
| 1437 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) | ||
| 1438 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1439 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1440 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1441 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1442 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1443 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1444 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1445 | */ | ||
| 1446 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) | ||
| 1447 | /*! @} */ | ||
| 1448 | |||
| 1449 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1450 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) | ||
| 1451 | |||
| 1452 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ | ||
| 1453 | #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U) | ||
| 1454 | |||
| 1455 | /*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ | ||
| 1456 | /*! @{ */ | ||
| 1457 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1458 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1459 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1460 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1461 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1462 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1463 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1464 | */ | ||
| 1465 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) | ||
| 1466 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1467 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1468 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1469 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1470 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1471 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1472 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1473 | */ | ||
| 1474 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) | ||
| 1475 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1476 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1477 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1478 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1479 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1480 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1481 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1482 | */ | ||
| 1483 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) | ||
| 1484 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1485 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1486 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1487 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1488 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1489 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1490 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1491 | */ | ||
| 1492 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) | ||
| 1493 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1494 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1495 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1496 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1497 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1498 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1499 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1500 | */ | ||
| 1501 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) | ||
| 1502 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1503 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1504 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1505 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1506 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1507 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1508 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1509 | */ | ||
| 1510 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) | ||
| 1511 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1512 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1513 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1514 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1515 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1516 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1517 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1518 | */ | ||
| 1519 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) | ||
| 1520 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1521 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1522 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1523 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1524 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1525 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1526 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1527 | */ | ||
| 1528 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) | ||
| 1529 | /*! @} */ | ||
| 1530 | |||
| 1531 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1532 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) | ||
| 1533 | |||
| 1534 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ | ||
| 1535 | #define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) | ||
| 1536 | |||
| 1537 | /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ | ||
| 1538 | /*! @{ */ | ||
| 1539 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) | ||
| 1540 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) | ||
| 1541 | /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF | ||
| 1542 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1543 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1544 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1545 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1546 | */ | ||
| 1547 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) | ||
| 1548 | /*! @} */ | ||
| 1549 | |||
| 1550 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ | ||
| 1551 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) | ||
| 1552 | |||
| 1553 | /*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ | ||
| 1554 | /*! @{ */ | ||
| 1555 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1556 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1557 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1558 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1559 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1560 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1561 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1562 | */ | ||
| 1563 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) | ||
| 1564 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1565 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1566 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1567 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1568 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1569 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1570 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1571 | */ | ||
| 1572 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) | ||
| 1573 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1574 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1575 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1576 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1577 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1578 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1579 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1580 | */ | ||
| 1581 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) | ||
| 1582 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1583 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1584 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1585 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1586 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1587 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1588 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1589 | */ | ||
| 1590 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) | ||
| 1591 | /*! @} */ | ||
| 1592 | |||
| 1593 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1594 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) | ||
| 1595 | |||
| 1596 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ | ||
| 1597 | #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) | ||
| 1598 | |||
| 1599 | /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ | ||
| 1600 | /*! @{ */ | ||
| 1601 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) | ||
| 1602 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) | ||
| 1603 | /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF | ||
| 1604 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1605 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1606 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1607 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1608 | */ | ||
| 1609 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) | ||
| 1610 | /*! @} */ | ||
| 1611 | |||
| 1612 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ | ||
| 1613 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) | ||
| 1614 | |||
| 1615 | /*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ | ||
| 1616 | /*! @{ */ | ||
| 1617 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1618 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1619 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1620 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1621 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1622 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1623 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1624 | */ | ||
| 1625 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) | ||
| 1626 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1627 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1628 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1629 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1630 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1631 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1632 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1633 | */ | ||
| 1634 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) | ||
| 1635 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1636 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1637 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1638 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1639 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1640 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1641 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1642 | */ | ||
| 1643 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) | ||
| 1644 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1645 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1646 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1647 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1648 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1649 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1650 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1651 | */ | ||
| 1652 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) | ||
| 1653 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) | ||
| 1654 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) | ||
| 1655 | /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' | ||
| 1656 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1657 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1658 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1659 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1660 | */ | ||
| 1661 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) | ||
| 1662 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) | ||
| 1663 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) | ||
| 1664 | /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' | ||
| 1665 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1666 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1667 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1668 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1669 | */ | ||
| 1670 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) | ||
| 1671 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) | ||
| 1672 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) | ||
| 1673 | /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' | ||
| 1674 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1675 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1676 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1677 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1678 | */ | ||
| 1679 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) | ||
| 1680 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) | ||
| 1681 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) | ||
| 1682 | /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' | ||
| 1683 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1684 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1685 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1686 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1687 | */ | ||
| 1688 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) | ||
| 1689 | /*! @} */ | ||
| 1690 | |||
| 1691 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1692 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) | ||
| 1693 | |||
| 1694 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ | ||
| 1695 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U) | ||
| 1696 | |||
| 1697 | /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ | ||
| 1698 | /*! @{ */ | ||
| 1699 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) | ||
| 1700 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) | ||
| 1701 | /*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF | ||
| 1702 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1703 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1704 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1705 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1706 | */ | ||
| 1707 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) | ||
| 1708 | /*! @} */ | ||
| 1709 | |||
| 1710 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ | ||
| 1711 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) | ||
| 1712 | |||
| 1713 | /*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ | ||
| 1714 | /*! @{ */ | ||
| 1715 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1716 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1717 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1718 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1719 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1720 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1721 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1722 | */ | ||
| 1723 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) | ||
| 1724 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1725 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1726 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1727 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1728 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1729 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1730 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1731 | */ | ||
| 1732 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) | ||
| 1733 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1734 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1735 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1736 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1737 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1738 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1739 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1740 | */ | ||
| 1741 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) | ||
| 1742 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1743 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1744 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1745 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1746 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1747 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1748 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1749 | */ | ||
| 1750 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) | ||
| 1751 | /*! @} */ | ||
| 1752 | |||
| 1753 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1754 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) | ||
| 1755 | |||
| 1756 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ | ||
| 1757 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U) | ||
| 1758 | |||
| 1759 | /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ | ||
| 1760 | /*! @{ */ | ||
| 1761 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) | ||
| 1762 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) | ||
| 1763 | /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF | ||
| 1764 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1765 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1766 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1767 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1768 | */ | ||
| 1769 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) | ||
| 1770 | /*! @} */ | ||
| 1771 | |||
| 1772 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ | ||
| 1773 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) | ||
| 1774 | |||
| 1775 | /*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ | ||
| 1776 | /*! @{ */ | ||
| 1777 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) | ||
| 1778 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) | ||
| 1779 | /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' | ||
| 1780 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1781 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1782 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1783 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1784 | */ | ||
| 1785 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) | ||
| 1786 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) | ||
| 1787 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) | ||
| 1788 | /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' | ||
| 1789 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1790 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1791 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1792 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1793 | */ | ||
| 1794 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) | ||
| 1795 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) | ||
| 1796 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) | ||
| 1797 | /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' | ||
| 1798 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1799 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1800 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1801 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1802 | */ | ||
| 1803 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) | ||
| 1804 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) | ||
| 1805 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) | ||
| 1806 | /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' | ||
| 1807 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1808 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1809 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1810 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1811 | */ | ||
| 1812 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) | ||
| 1813 | /*! @} */ | ||
| 1814 | |||
| 1815 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1816 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) | ||
| 1817 | |||
| 1818 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ | ||
| 1819 | #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U) | ||
| 1820 | |||
| 1821 | /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ | ||
| 1822 | /*! @{ */ | ||
| 1823 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) | ||
| 1824 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) | ||
| 1825 | /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF | ||
| 1826 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1827 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1828 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1829 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1830 | */ | ||
| 1831 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) | ||
| 1832 | /*! @} */ | ||
| 1833 | |||
| 1834 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ | ||
| 1835 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) | ||
| 1836 | |||
| 1837 | /*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ | ||
| 1838 | /*! @{ */ | ||
| 1839 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) | ||
| 1840 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) | ||
| 1841 | /*! SRAM_SECT_0_RULE - Address space: 0x2001_0000 - 0x2001_0FFF | ||
| 1842 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1843 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1844 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1845 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1846 | */ | ||
| 1847 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) | ||
| 1848 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) | ||
| 1849 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) | ||
| 1850 | /*! SRAM_SECT_1_RULE - Address space: 0x2001_1000 - 0x2001_1FFF | ||
| 1851 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1852 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1853 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1854 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1855 | */ | ||
| 1856 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) | ||
| 1857 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) | ||
| 1858 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) | ||
| 1859 | /*! SRAM_SECT_2_RULE - Address space: 0x2001_2000 - 0x2001_2FFF | ||
| 1860 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1861 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1862 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1863 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1864 | */ | ||
| 1865 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) | ||
| 1866 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) | ||
| 1867 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) | ||
| 1868 | /*! SRAM_SECT_3_RULE - Address space: 0x2001_3000 - 0x2001_3FFF | ||
| 1869 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1870 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1871 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1872 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1873 | */ | ||
| 1874 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) | ||
| 1875 | /*! @} */ | ||
| 1876 | |||
| 1877 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 1878 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) | ||
| 1879 | |||
| 1880 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ | ||
| 1881 | #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) | ||
| 1882 | |||
| 1883 | /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ | ||
| 1884 | /*! @{ */ | ||
| 1885 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) | ||
| 1886 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) | ||
| 1887 | /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 | ||
| 1888 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1889 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1890 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1891 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1892 | */ | ||
| 1893 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) | ||
| 1894 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) | ||
| 1895 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) | ||
| 1896 | /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 | ||
| 1897 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1898 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1899 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1900 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1901 | */ | ||
| 1902 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) | ||
| 1903 | /*! @} */ | ||
| 1904 | |||
| 1905 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ | ||
| 1906 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) | ||
| 1907 | |||
| 1908 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 1909 | /*! @{ */ | ||
| 1910 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) | ||
| 1911 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) | ||
| 1912 | /*! SYSCON_RULE - System Configuration | ||
| 1913 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1914 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1915 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1916 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1917 | */ | ||
| 1918 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) | ||
| 1919 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) | ||
| 1920 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) | ||
| 1921 | /*! IOCON_RULE - I/O Configuration | ||
| 1922 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1923 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1924 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1925 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1926 | */ | ||
| 1927 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) | ||
| 1928 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) | ||
| 1929 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) | ||
| 1930 | /*! GINT0_RULE - GPIO input Interrupt 0 | ||
| 1931 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1932 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1933 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1934 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1935 | */ | ||
| 1936 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) | ||
| 1937 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) | ||
| 1938 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) | ||
| 1939 | /*! GINT1_RULE - GPIO input Interrupt 1 | ||
| 1940 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1941 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1942 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1943 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1944 | */ | ||
| 1945 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) | ||
| 1946 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) | ||
| 1947 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) | ||
| 1948 | /*! PINT_RULE - Pin Interrupt and Pattern match | ||
| 1949 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1950 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1951 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1952 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1953 | */ | ||
| 1954 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) | ||
| 1955 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) | ||
| 1956 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) | ||
| 1957 | /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match | ||
| 1958 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1959 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1960 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1961 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1962 | */ | ||
| 1963 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) | ||
| 1964 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) | ||
| 1965 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) | ||
| 1966 | /*! INPUTMUX_RULE - Peripheral input multiplexing | ||
| 1967 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1968 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1969 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1970 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1971 | */ | ||
| 1972 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) | ||
| 1973 | /*! @} */ | ||
| 1974 | |||
| 1975 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ | ||
| 1976 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) | ||
| 1977 | |||
| 1978 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 1979 | /*! @{ */ | ||
| 1980 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) | ||
| 1981 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) | ||
| 1982 | /*! CTIMER0_RULE - Standard counter/Timer 0 | ||
| 1983 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1984 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1985 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1986 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1987 | */ | ||
| 1988 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) | ||
| 1989 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) | ||
| 1990 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) | ||
| 1991 | /*! CTIMER1_RULE - Standard counter/Timer 1 | ||
| 1992 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 1993 | * 0b01..Non-secure and Privilege access allowed. | ||
| 1994 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 1995 | * 0b11..Secure and Priviledge user access allowed. | ||
| 1996 | */ | ||
| 1997 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) | ||
| 1998 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) | ||
| 1999 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) | ||
| 2000 | /*! WWDT_RULE - Windiwed wtachdog Timer | ||
| 2001 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2002 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2003 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2004 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2005 | */ | ||
| 2006 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) | ||
| 2007 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) | ||
| 2008 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) | ||
| 2009 | /*! MRT_RULE - Multi-rate Timer | ||
| 2010 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2011 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2012 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2013 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2014 | */ | ||
| 2015 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) | ||
| 2016 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) | ||
| 2017 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) | ||
| 2018 | /*! UTICK_RULE - Micro-Timer | ||
| 2019 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2020 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2021 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2022 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2023 | */ | ||
| 2024 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) | ||
| 2025 | /*! @} */ | ||
| 2026 | |||
| 2027 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ | ||
| 2028 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) | ||
| 2029 | |||
| 2030 | /*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ | ||
| 2031 | /*! @{ */ | ||
| 2032 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) | ||
| 2033 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) | ||
| 2034 | /*! ANACTRL_RULE - Analog Modules controller | ||
| 2035 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2036 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2037 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2038 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2039 | */ | ||
| 2040 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) | ||
| 2041 | /*! @} */ | ||
| 2042 | |||
| 2043 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ | ||
| 2044 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) | ||
| 2045 | |||
| 2046 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2047 | /*! @{ */ | ||
| 2048 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) | ||
| 2049 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) | ||
| 2050 | /*! PMC_RULE - Power Management Controller | ||
| 2051 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2052 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2053 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2054 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2055 | */ | ||
| 2056 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) | ||
| 2057 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) | ||
| 2058 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) | ||
| 2059 | /*! SYSCTRL_RULE - System Controller | ||
| 2060 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2061 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2062 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2063 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2064 | */ | ||
| 2065 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) | ||
| 2066 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U) | ||
| 2067 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U) | ||
| 2068 | /*! SPI_FILTER_RULE - SPI FILTER control | ||
| 2069 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2070 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2071 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2072 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2073 | */ | ||
| 2074 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK) | ||
| 2075 | /*! @} */ | ||
| 2076 | |||
| 2077 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ | ||
| 2078 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) | ||
| 2079 | |||
| 2080 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2081 | /*! @{ */ | ||
| 2082 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) | ||
| 2083 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) | ||
| 2084 | /*! CTIMER2_RULE - Standard counter/Timer 2 | ||
| 2085 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2086 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2087 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2088 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2089 | */ | ||
| 2090 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) | ||
| 2091 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) | ||
| 2092 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) | ||
| 2093 | /*! CTIMER3_RULE - Standard counter/Timer 3 | ||
| 2094 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2095 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2096 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2097 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2098 | */ | ||
| 2099 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) | ||
| 2100 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) | ||
| 2101 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) | ||
| 2102 | /*! CTIMER4_RULE - Standard counter/Timer 4 | ||
| 2103 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2104 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2105 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2106 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2107 | */ | ||
| 2108 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) | ||
| 2109 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) | ||
| 2110 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) | ||
| 2111 | /*! RTC_RULE - Real Time Counter | ||
| 2112 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2113 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2114 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2115 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2116 | */ | ||
| 2117 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) | ||
| 2118 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) | ||
| 2119 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) | ||
| 2120 | /*! OSEVENT_RULE - OS Event Timer | ||
| 2121 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2122 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2123 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2124 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2125 | */ | ||
| 2126 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) | ||
| 2127 | /*! @} */ | ||
| 2128 | |||
| 2129 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ | ||
| 2130 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) | ||
| 2131 | |||
| 2132 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2133 | /*! @{ */ | ||
| 2134 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) | ||
| 2135 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) | ||
| 2136 | /*! FLASH_CTRL_RULE - Flash Controller | ||
| 2137 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2138 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2139 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2140 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2141 | */ | ||
| 2142 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) | ||
| 2143 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) | ||
| 2144 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) | ||
| 2145 | /*! PRINCE_RULE - Prince | ||
| 2146 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2147 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2148 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2149 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2150 | */ | ||
| 2151 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) | ||
| 2152 | /*! @} */ | ||
| 2153 | |||
| 2154 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ | ||
| 2155 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) | ||
| 2156 | |||
| 2157 | /*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ | ||
| 2158 | /*! @{ */ | ||
| 2159 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) | ||
| 2160 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) | ||
| 2161 | /*! USBHPHY_RULE - USB High Speed Phy controller | ||
| 2162 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2163 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2164 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2165 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2166 | */ | ||
| 2167 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) | ||
| 2168 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) | ||
| 2169 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) | ||
| 2170 | /*! RNG_RULE - True Random Number Generator | ||
| 2171 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2172 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2173 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2174 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2175 | */ | ||
| 2176 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) | ||
| 2177 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) | ||
| 2178 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) | ||
| 2179 | /*! PUF_RULE - PUF | ||
| 2180 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2181 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2182 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2183 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2184 | */ | ||
| 2185 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) | ||
| 2186 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) | ||
| 2187 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) | ||
| 2188 | /*! PLU_RULE - Programmable Look-Up logic | ||
| 2189 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2190 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2191 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2192 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2193 | */ | ||
| 2194 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) | ||
| 2195 | /*! @} */ | ||
| 2196 | |||
| 2197 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ | ||
| 2198 | #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) | ||
| 2199 | |||
| 2200 | /*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2201 | /*! @{ */ | ||
| 2202 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) | ||
| 2203 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) | ||
| 2204 | /*! DMA0_RULE - DMA Controller | ||
| 2205 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2206 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2207 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2208 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2209 | */ | ||
| 2210 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK) | ||
| 2211 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) | ||
| 2212 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) | ||
| 2213 | /*! FS_USB_DEV_RULE - USB Full-speed device | ||
| 2214 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2215 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2216 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2217 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2218 | */ | ||
| 2219 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) | ||
| 2220 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) | ||
| 2221 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U) | ||
| 2222 | /*! SCT_RULE - SCTimer | ||
| 2223 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2224 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2225 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2226 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2227 | */ | ||
| 2228 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK) | ||
| 2229 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) | ||
| 2230 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) | ||
| 2231 | /*! FLEXCOMM0_RULE - Flexcomm interface 0 | ||
| 2232 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2233 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2234 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2235 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2236 | */ | ||
| 2237 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) | ||
| 2238 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) | ||
| 2239 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) | ||
| 2240 | /*! FLEXCOMM1_RULE - Flexcomm interface 1 | ||
| 2241 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2242 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2243 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2244 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2245 | */ | ||
| 2246 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) | ||
| 2247 | /*! @} */ | ||
| 2248 | |||
| 2249 | /*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2250 | /*! @{ */ | ||
| 2251 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) | ||
| 2252 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) | ||
| 2253 | /*! FLEXCOMM2_RULE - Flexcomm interface 2 | ||
| 2254 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2255 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2256 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2257 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2258 | */ | ||
| 2259 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) | ||
| 2260 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) | ||
| 2261 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) | ||
| 2262 | /*! FLEXCOMM3_RULE - Flexcomm interface 3 | ||
| 2263 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2264 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2265 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2266 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2267 | */ | ||
| 2268 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) | ||
| 2269 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) | ||
| 2270 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) | ||
| 2271 | /*! FLEXCOMM4_RULE - Flexcomm interface 4 | ||
| 2272 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2273 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2274 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2275 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2276 | */ | ||
| 2277 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) | ||
| 2278 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) | ||
| 2279 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) | ||
| 2280 | /*! GPIO0_RULE - High Speed GPIO | ||
| 2281 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2282 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2283 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2284 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2285 | */ | ||
| 2286 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK) | ||
| 2287 | /*! @} */ | ||
| 2288 | |||
| 2289 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2290 | /*! @{ */ | ||
| 2291 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) | ||
| 2292 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) | ||
| 2293 | /*! USB_HS_DEV_RULE - USB high Speed device registers | ||
| 2294 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2295 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2296 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2297 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2298 | */ | ||
| 2299 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) | ||
| 2300 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) | ||
| 2301 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U) | ||
| 2302 | /*! CRC_RULE - CRC engine | ||
| 2303 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2304 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2305 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2306 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2307 | */ | ||
| 2308 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK) | ||
| 2309 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) | ||
| 2310 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) | ||
| 2311 | /*! FLEXCOMM5_RULE - Flexcomm interface 5 | ||
| 2312 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2313 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2314 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2315 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2316 | */ | ||
| 2317 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) | ||
| 2318 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) | ||
| 2319 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) | ||
| 2320 | /*! FLEXCOMM6_RULE - Flexcomm interface 6 | ||
| 2321 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2322 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2323 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2324 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2325 | */ | ||
| 2326 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) | ||
| 2327 | /*! @} */ | ||
| 2328 | |||
| 2329 | /*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2330 | /*! @{ */ | ||
| 2331 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) | ||
| 2332 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) | ||
| 2333 | /*! FLEXCOMM7_RULE - Flexcomm interface 7 | ||
| 2334 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2335 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2336 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2337 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2338 | */ | ||
| 2339 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) | ||
| 2340 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) | ||
| 2341 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) | ||
| 2342 | /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) | ||
| 2343 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2344 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2345 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2346 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2347 | */ | ||
| 2348 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) | ||
| 2349 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U) | ||
| 2350 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U) | ||
| 2351 | /*! CAN0_RULE - CAN-FD | ||
| 2352 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2353 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2354 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2355 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2356 | */ | ||
| 2357 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK) | ||
| 2358 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) | ||
| 2359 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) | ||
| 2360 | /*! HS_LSPI_RULE - High Speed SPI | ||
| 2361 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2362 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2363 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2364 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2365 | */ | ||
| 2366 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK) | ||
| 2367 | /*! @} */ | ||
| 2368 | |||
| 2369 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ | ||
| 2370 | /*! @{ */ | ||
| 2371 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U) | ||
| 2372 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U) | ||
| 2373 | /*! ADC_RULE - ADC | ||
| 2374 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2375 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2376 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2377 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2378 | */ | ||
| 2379 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK) | ||
| 2380 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) | ||
| 2381 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) | ||
| 2382 | /*! USB_FS_HOST_RULE - USB Full Speed Host registers. | ||
| 2383 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2384 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2385 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2386 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2387 | */ | ||
| 2388 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) | ||
| 2389 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) | ||
| 2390 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) | ||
| 2391 | /*! USB_HS_HOST_RULE - USB High speed host registers | ||
| 2392 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2393 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2394 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2395 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2396 | */ | ||
| 2397 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) | ||
| 2398 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) | ||
| 2399 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U) | ||
| 2400 | /*! HASH_RULE - SHA-2 crypto registers | ||
| 2401 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2402 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2403 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2404 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2405 | */ | ||
| 2406 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK) | ||
| 2407 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) | ||
| 2408 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) | ||
| 2409 | /*! CASPER_RULE - RSA/ECC crypto accelerator | ||
| 2410 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2411 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2412 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2413 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2414 | */ | ||
| 2415 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK) | ||
| 2416 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) | ||
| 2417 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) | ||
| 2418 | /*! DMA1_RULE - DMA Controller (Secure) | ||
| 2419 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2420 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2421 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2422 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2423 | */ | ||
| 2424 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK) | ||
| 2425 | /*! @} */ | ||
| 2426 | |||
| 2427 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */ | ||
| 2428 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U) | ||
| 2429 | |||
| 2430 | /*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ | ||
| 2431 | /*! @{ */ | ||
| 2432 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) | ||
| 2433 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) | ||
| 2434 | /*! GPIO1_RULE - Secure High Speed GPIO | ||
| 2435 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2436 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2437 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2438 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2439 | */ | ||
| 2440 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK) | ||
| 2441 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) | ||
| 2442 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) | ||
| 2443 | /*! AHB_SEC_CTRL_RULE - AHB Secure Controller | ||
| 2444 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2445 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2446 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2447 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2448 | */ | ||
| 2449 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) | ||
| 2450 | /*! @} */ | ||
| 2451 | |||
| 2452 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */ | ||
| 2453 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U) | ||
| 2454 | |||
| 2455 | /*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ | ||
| 2456 | /*! @{ */ | ||
| 2457 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) | ||
| 2458 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) | ||
| 2459 | /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF | ||
| 2460 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2461 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2462 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2463 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2464 | */ | ||
| 2465 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) | ||
| 2466 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) | ||
| 2467 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) | ||
| 2468 | /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF | ||
| 2469 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2470 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2471 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2472 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2473 | */ | ||
| 2474 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) | ||
| 2475 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) | ||
| 2476 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) | ||
| 2477 | /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF | ||
| 2478 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2479 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2480 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2481 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2482 | */ | ||
| 2483 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) | ||
| 2484 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) | ||
| 2485 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) | ||
| 2486 | /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF | ||
| 2487 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 2488 | * 0b01..Non-secure and Privilege access allowed. | ||
| 2489 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 2490 | * 0b11..Secure and Priviledge user access allowed. | ||
| 2491 | */ | ||
| 2492 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) | ||
| 2493 | /*! @} */ | ||
| 2494 | |||
| 2495 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2496 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) | ||
| 2497 | |||
| 2498 | /* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ | ||
| 2499 | #define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) | ||
| 2500 | |||
| 2501 | /*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ | ||
| 2502 | /*! @{ */ | ||
| 2503 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) | ||
| 2504 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) | ||
| 2505 | /*! SEC_VIO_ADDR - security violation address for AHB layer | ||
| 2506 | */ | ||
| 2507 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) | ||
| 2508 | /*! @} */ | ||
| 2509 | |||
| 2510 | /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ | ||
| 2511 | #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U) | ||
| 2512 | |||
| 2513 | /*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ | ||
| 2514 | /*! @{ */ | ||
| 2515 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) | ||
| 2516 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) | ||
| 2517 | /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. | ||
| 2518 | * 0b0..Read access. | ||
| 2519 | * 0b1..Write access. | ||
| 2520 | */ | ||
| 2521 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) | ||
| 2522 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) | ||
| 2523 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) | ||
| 2524 | /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. | ||
| 2525 | * 0b0..Code access. | ||
| 2526 | * 0b1..Data access. | ||
| 2527 | */ | ||
| 2528 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) | ||
| 2529 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) | ||
| 2530 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) | ||
| 2531 | /*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level | ||
| 2532 | */ | ||
| 2533 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) | ||
| 2534 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) | ||
| 2535 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) | ||
| 2536 | /*! SEC_VIO_INFO_MASTER - security violation master number | ||
| 2537 | * 0b0000..CPU0 Code. | ||
| 2538 | * 0b0001..CPU0 System. | ||
| 2539 | * 0b0100..USB-HS Device. | ||
| 2540 | * 0b0101..SDMA0. | ||
| 2541 | * 0b1010..HASH. | ||
| 2542 | * 0b1011..USB-FS Host. | ||
| 2543 | * 0b1100..SDMA1. | ||
| 2544 | * 0b1101..CAN-FD. | ||
| 2545 | */ | ||
| 2546 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) | ||
| 2547 | /*! @} */ | ||
| 2548 | |||
| 2549 | /* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ | ||
| 2550 | #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U) | ||
| 2551 | |||
| 2552 | /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ | ||
| 2553 | /*! @{ */ | ||
| 2554 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) | ||
| 2555 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) | ||
| 2556 | /*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. | ||
| 2557 | * 0b0..Not valid. | ||
| 2558 | * 0b1..Valid (violation occurred). | ||
| 2559 | */ | ||
| 2560 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) | ||
| 2561 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) | ||
| 2562 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) | ||
| 2563 | /*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. | ||
| 2564 | * 0b0..Not valid. | ||
| 2565 | * 0b1..Valid (violation occurred). | ||
| 2566 | */ | ||
| 2567 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) | ||
| 2568 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) | ||
| 2569 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) | ||
| 2570 | /*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. | ||
| 2571 | * 0b0..Not valid. | ||
| 2572 | * 0b1..Valid (violation occurred). | ||
| 2573 | */ | ||
| 2574 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) | ||
| 2575 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) | ||
| 2576 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) | ||
| 2577 | /*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. | ||
| 2578 | * 0b0..Not valid. | ||
| 2579 | * 0b1..Valid (violation occurred). | ||
| 2580 | */ | ||
| 2581 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) | ||
| 2582 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) | ||
| 2583 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) | ||
| 2584 | /*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. | ||
| 2585 | * 0b0..Not valid. | ||
| 2586 | * 0b1..Valid (violation occurred). | ||
| 2587 | */ | ||
| 2588 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) | ||
| 2589 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) | ||
| 2590 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) | ||
| 2591 | /*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. | ||
| 2592 | * 0b0..Not valid. | ||
| 2593 | * 0b1..Valid (violation occurred). | ||
| 2594 | */ | ||
| 2595 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) | ||
| 2596 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) | ||
| 2597 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) | ||
| 2598 | /*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. | ||
| 2599 | * 0b0..Not valid. | ||
| 2600 | * 0b1..Valid (violation occurred). | ||
| 2601 | */ | ||
| 2602 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) | ||
| 2603 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) | ||
| 2604 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) | ||
| 2605 | /*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. | ||
| 2606 | * 0b0..Not valid. | ||
| 2607 | * 0b1..Valid (violation occurred). | ||
| 2608 | */ | ||
| 2609 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) | ||
| 2610 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) | ||
| 2611 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) | ||
| 2612 | /*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. | ||
| 2613 | * 0b0..Not valid. | ||
| 2614 | * 0b1..Valid (violation occurred). | ||
| 2615 | */ | ||
| 2616 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) | ||
| 2617 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) | ||
| 2618 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) | ||
| 2619 | /*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. | ||
| 2620 | * 0b0..Not valid. | ||
| 2621 | * 0b1..Valid (violation occurred). | ||
| 2622 | */ | ||
| 2623 | #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) | ||
| 2624 | /*! @} */ | ||
| 2625 | |||
| 2626 | /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ | ||
| 2627 | /*! @{ */ | ||
| 2628 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) | ||
| 2629 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) | ||
| 2630 | /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 | ||
| 2631 | * 0b1..Pin state is readable by non-secure world. | ||
| 2632 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2633 | */ | ||
| 2634 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) | ||
| 2635 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) | ||
| 2636 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) | ||
| 2637 | /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 | ||
| 2638 | * 0b1..Pin state is readable by non-secure world. | ||
| 2639 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2640 | */ | ||
| 2641 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) | ||
| 2642 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) | ||
| 2643 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) | ||
| 2644 | /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 | ||
| 2645 | * 0b1..Pin state is readable by non-secure world. | ||
| 2646 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2647 | */ | ||
| 2648 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) | ||
| 2649 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) | ||
| 2650 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) | ||
| 2651 | /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 | ||
| 2652 | * 0b1..Pin state is readable by non-secure world. | ||
| 2653 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2654 | */ | ||
| 2655 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) | ||
| 2656 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) | ||
| 2657 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) | ||
| 2658 | /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 | ||
| 2659 | * 0b1..Pin state is readable by non-secure world. | ||
| 2660 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2661 | */ | ||
| 2662 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) | ||
| 2663 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) | ||
| 2664 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) | ||
| 2665 | /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 | ||
| 2666 | * 0b1..Pin state is readable by non-secure world. | ||
| 2667 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2668 | */ | ||
| 2669 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) | ||
| 2670 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) | ||
| 2671 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) | ||
| 2672 | /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 | ||
| 2673 | * 0b1..Pin state is readable by non-secure world. | ||
| 2674 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2675 | */ | ||
| 2676 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) | ||
| 2677 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) | ||
| 2678 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) | ||
| 2679 | /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 | ||
| 2680 | * 0b1..Pin state is readable by non-secure world. | ||
| 2681 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2682 | */ | ||
| 2683 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) | ||
| 2684 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) | ||
| 2685 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) | ||
| 2686 | /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 | ||
| 2687 | * 0b1..Pin state is readable by non-secure world. | ||
| 2688 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2689 | */ | ||
| 2690 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) | ||
| 2691 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) | ||
| 2692 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) | ||
| 2693 | /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 | ||
| 2694 | * 0b1..Pin state is readable by non-secure world. | ||
| 2695 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2696 | */ | ||
| 2697 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) | ||
| 2698 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) | ||
| 2699 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) | ||
| 2700 | /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 | ||
| 2701 | * 0b1..Pin state is readable by non-secure world. | ||
| 2702 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2703 | */ | ||
| 2704 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) | ||
| 2705 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) | ||
| 2706 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) | ||
| 2707 | /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 | ||
| 2708 | * 0b1..Pin state is readable by non-secure world. | ||
| 2709 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2710 | */ | ||
| 2711 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) | ||
| 2712 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 2713 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) | ||
| 2714 | /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 | ||
| 2715 | * 0b1..Pin state is readable by non-secure world. | ||
| 2716 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2717 | */ | ||
| 2718 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) | ||
| 2719 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 2720 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) | ||
| 2721 | /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 | ||
| 2722 | * 0b1..Pin state is readable by non-secure world. | ||
| 2723 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2724 | */ | ||
| 2725 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) | ||
| 2726 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 2727 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) | ||
| 2728 | /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 | ||
| 2729 | * 0b1..Pin state is readable by non-secure world. | ||
| 2730 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2731 | */ | ||
| 2732 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) | ||
| 2733 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 2734 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) | ||
| 2735 | /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 | ||
| 2736 | * 0b1..Pin state is readable by non-secure world. | ||
| 2737 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2738 | */ | ||
| 2739 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) | ||
| 2740 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 2741 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) | ||
| 2742 | /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 | ||
| 2743 | * 0b1..Pin state is readable by non-secure world. | ||
| 2744 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2745 | */ | ||
| 2746 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) | ||
| 2747 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 2748 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) | ||
| 2749 | /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 | ||
| 2750 | * 0b1..Pin state is readable by non-secure world. | ||
| 2751 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2752 | */ | ||
| 2753 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) | ||
| 2754 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 2755 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) | ||
| 2756 | /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 | ||
| 2757 | * 0b1..Pin state is readable by non-secure world. | ||
| 2758 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2759 | */ | ||
| 2760 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) | ||
| 2761 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 2762 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) | ||
| 2763 | /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 | ||
| 2764 | * 0b1..Pin state is readable by non-secure world. | ||
| 2765 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2766 | */ | ||
| 2767 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) | ||
| 2768 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 2769 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) | ||
| 2770 | /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 | ||
| 2771 | * 0b1..Pin state is readable by non-secure world. | ||
| 2772 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2773 | */ | ||
| 2774 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) | ||
| 2775 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 2776 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) | ||
| 2777 | /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 | ||
| 2778 | * 0b1..Pin state is readable by non-secure world. | ||
| 2779 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2780 | */ | ||
| 2781 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) | ||
| 2782 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 2783 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) | ||
| 2784 | /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 | ||
| 2785 | * 0b1..Pin state is readable by non-secure world. | ||
| 2786 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2787 | */ | ||
| 2788 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) | ||
| 2789 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 2790 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) | ||
| 2791 | /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 | ||
| 2792 | * 0b1..Pin state is readable by non-secure world. | ||
| 2793 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2794 | */ | ||
| 2795 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) | ||
| 2796 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 2797 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) | ||
| 2798 | /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 | ||
| 2799 | * 0b1..Pin state is readable by non-secure world. | ||
| 2800 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2801 | */ | ||
| 2802 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) | ||
| 2803 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 2804 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) | ||
| 2805 | /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 | ||
| 2806 | * 0b1..Pin state is readable by non-secure world. | ||
| 2807 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2808 | */ | ||
| 2809 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) | ||
| 2810 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 2811 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) | ||
| 2812 | /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 | ||
| 2813 | * 0b1..Pin state is readable by non-secure world. | ||
| 2814 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2815 | */ | ||
| 2816 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) | ||
| 2817 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 2818 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) | ||
| 2819 | /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 | ||
| 2820 | * 0b1..Pin state is readable by non-secure world. | ||
| 2821 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2822 | */ | ||
| 2823 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) | ||
| 2824 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 2825 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) | ||
| 2826 | /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 | ||
| 2827 | * 0b1..Pin state is readable by non-secure world. | ||
| 2828 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2829 | */ | ||
| 2830 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) | ||
| 2831 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 2832 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) | ||
| 2833 | /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 | ||
| 2834 | * 0b1..Pin state is readable by non-secure world. | ||
| 2835 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2836 | */ | ||
| 2837 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) | ||
| 2838 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 2839 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) | ||
| 2840 | /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 | ||
| 2841 | * 0b1..Pin state is readable by non-secure world. | ||
| 2842 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2843 | */ | ||
| 2844 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) | ||
| 2845 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 2846 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) | ||
| 2847 | /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 | ||
| 2848 | * 0b1..Pin state is readable by non-secure world. | ||
| 2849 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2850 | */ | ||
| 2851 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) | ||
| 2852 | /*! @} */ | ||
| 2853 | |||
| 2854 | /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ | ||
| 2855 | /*! @{ */ | ||
| 2856 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) | ||
| 2857 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) | ||
| 2858 | /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 | ||
| 2859 | * 0b1..Pin state is readable by non-secure world. | ||
| 2860 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2861 | */ | ||
| 2862 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) | ||
| 2863 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) | ||
| 2864 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) | ||
| 2865 | /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 | ||
| 2866 | * 0b1..Pin state is readable by non-secure world. | ||
| 2867 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2868 | */ | ||
| 2869 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) | ||
| 2870 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) | ||
| 2871 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) | ||
| 2872 | /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 | ||
| 2873 | * 0b1..Pin state is readable by non-secure world. | ||
| 2874 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2875 | */ | ||
| 2876 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) | ||
| 2877 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) | ||
| 2878 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) | ||
| 2879 | /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 | ||
| 2880 | * 0b1..Pin state is readable by non-secure world. | ||
| 2881 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2882 | */ | ||
| 2883 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) | ||
| 2884 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) | ||
| 2885 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) | ||
| 2886 | /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 | ||
| 2887 | * 0b1..Pin state is readable by non-secure world. | ||
| 2888 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2889 | */ | ||
| 2890 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) | ||
| 2891 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) | ||
| 2892 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) | ||
| 2893 | /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 | ||
| 2894 | * 0b1..Pin state is readable by non-secure world. | ||
| 2895 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2896 | */ | ||
| 2897 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) | ||
| 2898 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) | ||
| 2899 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) | ||
| 2900 | /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 | ||
| 2901 | * 0b1..Pin state is readable by non-secure world. | ||
| 2902 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2903 | */ | ||
| 2904 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) | ||
| 2905 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) | ||
| 2906 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) | ||
| 2907 | /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 | ||
| 2908 | * 0b1..Pin state is readable by non-secure world. | ||
| 2909 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2910 | */ | ||
| 2911 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) | ||
| 2912 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) | ||
| 2913 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) | ||
| 2914 | /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 | ||
| 2915 | * 0b1..Pin state is readable by non-secure world. | ||
| 2916 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2917 | */ | ||
| 2918 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) | ||
| 2919 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) | ||
| 2920 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) | ||
| 2921 | /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 | ||
| 2922 | * 0b1..Pin state is readable by non-secure world. | ||
| 2923 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2924 | */ | ||
| 2925 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) | ||
| 2926 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) | ||
| 2927 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) | ||
| 2928 | /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 | ||
| 2929 | * 0b1..Pin state is readable by non-secure world. | ||
| 2930 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2931 | */ | ||
| 2932 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) | ||
| 2933 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) | ||
| 2934 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) | ||
| 2935 | /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 | ||
| 2936 | * 0b1..Pin state is readable by non-secure world. | ||
| 2937 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2938 | */ | ||
| 2939 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) | ||
| 2940 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) | ||
| 2941 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) | ||
| 2942 | /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 | ||
| 2943 | * 0b1..Pin state is readable by non-secure world. | ||
| 2944 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2945 | */ | ||
| 2946 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) | ||
| 2947 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) | ||
| 2948 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) | ||
| 2949 | /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 | ||
| 2950 | * 0b1..Pin state is readable by non-secure world. | ||
| 2951 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2952 | */ | ||
| 2953 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) | ||
| 2954 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) | ||
| 2955 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) | ||
| 2956 | /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 | ||
| 2957 | * 0b1..Pin state is readable by non-secure world. | ||
| 2958 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2959 | */ | ||
| 2960 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) | ||
| 2961 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) | ||
| 2962 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) | ||
| 2963 | /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 | ||
| 2964 | * 0b1..Pin state is readable by non-secure world. | ||
| 2965 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2966 | */ | ||
| 2967 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) | ||
| 2968 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) | ||
| 2969 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) | ||
| 2970 | /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 | ||
| 2971 | * 0b1..Pin state is readable by non-secure world. | ||
| 2972 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2973 | */ | ||
| 2974 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) | ||
| 2975 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) | ||
| 2976 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) | ||
| 2977 | /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 | ||
| 2978 | * 0b1..Pin state is readable by non-secure world. | ||
| 2979 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2980 | */ | ||
| 2981 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) | ||
| 2982 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) | ||
| 2983 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) | ||
| 2984 | /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 | ||
| 2985 | * 0b1..Pin state is readable by non-secure world. | ||
| 2986 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2987 | */ | ||
| 2988 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) | ||
| 2989 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) | ||
| 2990 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) | ||
| 2991 | /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 | ||
| 2992 | * 0b1..Pin state is readable by non-secure world. | ||
| 2993 | * 0b0..Pin state is blocked to non-secure world. | ||
| 2994 | */ | ||
| 2995 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) | ||
| 2996 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) | ||
| 2997 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) | ||
| 2998 | /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 | ||
| 2999 | * 0b1..Pin state is readable by non-secure world. | ||
| 3000 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3001 | */ | ||
| 3002 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) | ||
| 3003 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) | ||
| 3004 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) | ||
| 3005 | /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 | ||
| 3006 | * 0b1..Pin state is readable by non-secure world. | ||
| 3007 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3008 | */ | ||
| 3009 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) | ||
| 3010 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) | ||
| 3011 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) | ||
| 3012 | /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 | ||
| 3013 | * 0b1..Pin state is readable by non-secure world. | ||
| 3014 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3015 | */ | ||
| 3016 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) | ||
| 3017 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) | ||
| 3018 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) | ||
| 3019 | /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 | ||
| 3020 | * 0b1..Pin state is readable by non-secure world. | ||
| 3021 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3022 | */ | ||
| 3023 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) | ||
| 3024 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) | ||
| 3025 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) | ||
| 3026 | /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 | ||
| 3027 | * 0b1..Pin state is readable by non-secure world. | ||
| 3028 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3029 | */ | ||
| 3030 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) | ||
| 3031 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) | ||
| 3032 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) | ||
| 3033 | /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 | ||
| 3034 | * 0b1..Pin state is readable by non-secure world. | ||
| 3035 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3036 | */ | ||
| 3037 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) | ||
| 3038 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) | ||
| 3039 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) | ||
| 3040 | /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 | ||
| 3041 | * 0b1..Pin state is readable by non-secure world. | ||
| 3042 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3043 | */ | ||
| 3044 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) | ||
| 3045 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) | ||
| 3046 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) | ||
| 3047 | /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 | ||
| 3048 | * 0b1..Pin state is readable by non-secure world. | ||
| 3049 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3050 | */ | ||
| 3051 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) | ||
| 3052 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) | ||
| 3053 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) | ||
| 3054 | /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 | ||
| 3055 | * 0b1..Pin state is readable by non-secure world. | ||
| 3056 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3057 | */ | ||
| 3058 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) | ||
| 3059 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) | ||
| 3060 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) | ||
| 3061 | /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 | ||
| 3062 | * 0b1..Pin state is readable by non-secure world. | ||
| 3063 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3064 | */ | ||
| 3065 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) | ||
| 3066 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) | ||
| 3067 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) | ||
| 3068 | /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 | ||
| 3069 | * 0b1..Pin state is readable by non-secure world. | ||
| 3070 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3071 | */ | ||
| 3072 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) | ||
| 3073 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) | ||
| 3074 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) | ||
| 3075 | /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 | ||
| 3076 | * 0b1..Pin state is readable by non-secure world. | ||
| 3077 | * 0b0..Pin state is blocked to non-secure world. | ||
| 3078 | */ | ||
| 3079 | #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) | ||
| 3080 | /*! @} */ | ||
| 3081 | |||
| 3082 | /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ | ||
| 3083 | /*! @{ */ | ||
| 3084 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) | ||
| 3085 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) | ||
| 3086 | /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. | ||
| 3087 | * 0b10..Writable. | ||
| 3088 | * 0b01..Restricted mode. | ||
| 3089 | */ | ||
| 3090 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) | ||
| 3091 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) | ||
| 3092 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) | ||
| 3093 | /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. | ||
| 3094 | * 0b10..Writable. | ||
| 3095 | * 0b01..Restricted mode. | ||
| 3096 | */ | ||
| 3097 | #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) | ||
| 3098 | /*! @} */ | ||
| 3099 | |||
| 3100 | /*! @name MASTER_SEC_LEVEL - master secure level register */ | ||
| 3101 | /*! @{ */ | ||
| 3102 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) | ||
| 3103 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) | ||
| 3104 | /*! USBFSD - USB Full Speed Device. | ||
| 3105 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3106 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3107 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3108 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3109 | */ | ||
| 3110 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) | ||
| 3111 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) | ||
| 3112 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) | ||
| 3113 | /*! SDMA0 - System DMA 0. | ||
| 3114 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3115 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3116 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3117 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3118 | */ | ||
| 3119 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) | ||
| 3120 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) | ||
| 3121 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) | ||
| 3122 | /*! HASH - Hash. | ||
| 3123 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3124 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3125 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3126 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3127 | */ | ||
| 3128 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) | ||
| 3129 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) | ||
| 3130 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) | ||
| 3131 | /*! USBFSH - USB Full speed Host. | ||
| 3132 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3133 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3134 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3135 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3136 | */ | ||
| 3137 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) | ||
| 3138 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) | ||
| 3139 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) | ||
| 3140 | /*! SDMA1 - System DMA 1 security level. | ||
| 3141 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3142 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3143 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3144 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3145 | */ | ||
| 3146 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) | ||
| 3147 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U) | ||
| 3148 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U) | ||
| 3149 | /*! CANFD - CAN FD. | ||
| 3150 | * 0b00..Non-secure and Non-priviledge user access allowed. | ||
| 3151 | * 0b01..Non-secure and Privilege access allowed. | ||
| 3152 | * 0b10..Secure and Non-priviledge user access allowed. | ||
| 3153 | * 0b11..Secure and Priviledge user access allowed. | ||
| 3154 | */ | ||
| 3155 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK) | ||
| 3156 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) | ||
| 3157 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) | ||
| 3158 | /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. | ||
| 3159 | * 0b10..Writable. | ||
| 3160 | * 0b01..Restricted mode. | ||
| 3161 | */ | ||
| 3162 | #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) | ||
| 3163 | /*! @} */ | ||
| 3164 | |||
| 3165 | /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ | ||
| 3166 | /*! @{ */ | ||
| 3167 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) | ||
| 3168 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) | ||
| 3169 | /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) | ||
| 3170 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3171 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3172 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3173 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3174 | */ | ||
| 3175 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) | ||
| 3176 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) | ||
| 3177 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) | ||
| 3178 | /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) | ||
| 3179 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3180 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3181 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3182 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3183 | */ | ||
| 3184 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) | ||
| 3185 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) | ||
| 3186 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) | ||
| 3187 | /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) | ||
| 3188 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3189 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3190 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3191 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3192 | */ | ||
| 3193 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) | ||
| 3194 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) | ||
| 3195 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) | ||
| 3196 | /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) | ||
| 3197 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3198 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3199 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3200 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3201 | */ | ||
| 3202 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) | ||
| 3203 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) | ||
| 3204 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) | ||
| 3205 | /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) | ||
| 3206 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3207 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3208 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3209 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3210 | */ | ||
| 3211 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) | ||
| 3212 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U) | ||
| 3213 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U) | ||
| 3214 | /*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) | ||
| 3215 | * 0b11..Non-secure and Non-priviledge user access allowed. | ||
| 3216 | * 0b10..Non-secure and Privilege access allowed. | ||
| 3217 | * 0b01..Secure and Non-priviledge user access allowed. | ||
| 3218 | * 0b00..Secure and Priviledge user access allowed. | ||
| 3219 | */ | ||
| 3220 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK) | ||
| 3221 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) | ||
| 3222 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) | ||
| 3223 | /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. | ||
| 3224 | * 0b10..Writable. | ||
| 3225 | * 0b01..Restricted mode. | ||
| 3226 | */ | ||
| 3227 | #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) | ||
| 3228 | /*! @} */ | ||
| 3229 | |||
| 3230 | /*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ | ||
| 3231 | /*! @{ */ | ||
| 3232 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) | ||
| 3233 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) | ||
| 3234 | /*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. | ||
| 3235 | * 0b10..Writable. | ||
| 3236 | * 0b01..Restricted mode. | ||
| 3237 | */ | ||
| 3238 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) | ||
| 3239 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) | ||
| 3240 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) | ||
| 3241 | /*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. | ||
| 3242 | * 0b10..Writable. | ||
| 3243 | * 0b01..Restricted mode. | ||
| 3244 | */ | ||
| 3245 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) | ||
| 3246 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) | ||
| 3247 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) | ||
| 3248 | /*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. | ||
| 3249 | * 0b10..Writable. | ||
| 3250 | * 0b01..Restricted mode. | ||
| 3251 | */ | ||
| 3252 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) | ||
| 3253 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) | ||
| 3254 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) | ||
| 3255 | /*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. | ||
| 3256 | * 0b10..Writable. | ||
| 3257 | * 0b01..Restricted mode. | ||
| 3258 | */ | ||
| 3259 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) | ||
| 3260 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) | ||
| 3261 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) | ||
| 3262 | /*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. | ||
| 3263 | * 0b10..Writable. | ||
| 3264 | * 0b01..Restricted mode. | ||
| 3265 | */ | ||
| 3266 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) | ||
| 3267 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) | ||
| 3268 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) | ||
| 3269 | /*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. | ||
| 3270 | * 0b10..Writable. | ||
| 3271 | * 0b01..Restricted mode. | ||
| 3272 | */ | ||
| 3273 | #define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) | ||
| 3274 | /*! @} */ | ||
| 3275 | |||
| 3276 | /*! @name MISC_CTRL_DP_REG - secure control duplicate register */ | ||
| 3277 | /*! @{ */ | ||
| 3278 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) | ||
| 3279 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) | ||
| 3280 | /*! WRITE_LOCK - Write lock. | ||
| 3281 | * 0b10..Secure control registers can be written. | ||
| 3282 | * 0b01..Restricted mode. | ||
| 3283 | */ | ||
| 3284 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) | ||
| 3285 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 3286 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 3287 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 3288 | * 0b10..Disable check. | ||
| 3289 | * 0b01..Restricted mode. | ||
| 3290 | */ | ||
| 3291 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 3292 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 3293 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 3294 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 3295 | * 0b10..Disable check. | ||
| 3296 | * 0b01..Restricted mode. | ||
| 3297 | */ | ||
| 3298 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 3299 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 3300 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 3301 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 3302 | * 0b10..Disable check. | ||
| 3303 | * 0b01..Restricted mode. | ||
| 3304 | */ | ||
| 3305 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 3306 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 3307 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 3308 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 3309 | * 0b10..Enable abort fort secure checker. | ||
| 3310 | * 0b01..Disable abort fort secure checker. | ||
| 3311 | */ | ||
| 3312 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 3313 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 3314 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 3315 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 3316 | * 0b10..Simple master in strict mode. | ||
| 3317 | * 0b01..Simple master in tier mode. | ||
| 3318 | */ | ||
| 3319 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 3320 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 3321 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 3322 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 3323 | * 0b10..Smart master in strict mode. | ||
| 3324 | * 0b01..Smart master in tier mode. | ||
| 3325 | */ | ||
| 3326 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 3327 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 3328 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 3329 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 3330 | * 0b10..IDAU is enabled. | ||
| 3331 | * 0b01..IDAU is disable. | ||
| 3332 | */ | ||
| 3333 | #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) | ||
| 3334 | /*! @} */ | ||
| 3335 | |||
| 3336 | /*! @name MISC_CTRL_REG - secure control register */ | ||
| 3337 | /*! @{ */ | ||
| 3338 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) | ||
| 3339 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) | ||
| 3340 | /*! WRITE_LOCK - Write lock. | ||
| 3341 | * 0b10..Secure control registers can be written. | ||
| 3342 | * 0b01..Restricted mode. | ||
| 3343 | */ | ||
| 3344 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) | ||
| 3345 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) | ||
| 3346 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) | ||
| 3347 | /*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. | ||
| 3348 | * 0b10..Disable check. | ||
| 3349 | * 0b01..Restricted mode. | ||
| 3350 | */ | ||
| 3351 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) | ||
| 3352 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) | ||
| 3353 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) | ||
| 3354 | /*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. | ||
| 3355 | * 0b10..Disable check. | ||
| 3356 | * 0b01..Restricted mode. | ||
| 3357 | */ | ||
| 3358 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) | ||
| 3359 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) | ||
| 3360 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) | ||
| 3361 | /*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. | ||
| 3362 | * 0b10..Disable check. | ||
| 3363 | * 0b01..Restricted mode. | ||
| 3364 | */ | ||
| 3365 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) | ||
| 3366 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) | ||
| 3367 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) | ||
| 3368 | /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. | ||
| 3369 | * 0b10..Enable abort fort secure checker. | ||
| 3370 | * 0b01..Disable abort fort secure checker. | ||
| 3371 | */ | ||
| 3372 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) | ||
| 3373 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) | ||
| 3374 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) | ||
| 3375 | /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. | ||
| 3376 | * 0b10..Simple master in strict mode. | ||
| 3377 | * 0b01..Simple master in tier mode. | ||
| 3378 | */ | ||
| 3379 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) | ||
| 3380 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) | ||
| 3381 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) | ||
| 3382 | /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. | ||
| 3383 | * 0b10..Smart master in strict mode. | ||
| 3384 | * 0b01..Smart master in tier mode. | ||
| 3385 | */ | ||
| 3386 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) | ||
| 3387 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) | ||
| 3388 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) | ||
| 3389 | /*! IDAU_ALL_NS - Disable IDAU. | ||
| 3390 | * 0b10..IDAU is enabled. | ||
| 3391 | * 0b01..IDAU is disable. | ||
| 3392 | */ | ||
| 3393 | #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) | ||
| 3394 | /*! @} */ | ||
| 3395 | |||
| 3396 | |||
| 3397 | /*! | ||
| 3398 | * @} | ||
| 3399 | */ /* end of group AHB_SECURE_CTRL_Register_Masks */ | ||
| 3400 | |||
| 3401 | |||
| 3402 | /* AHB_SECURE_CTRL - Peripheral instance base addresses */ | ||
| 3403 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 3404 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3405 | #define AHB_SECURE_CTRL_BASE (0x500AC000u) | ||
| 3406 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3407 | #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) | ||
| 3408 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3409 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 3410 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3411 | #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) | ||
| 3412 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3413 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 3414 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3415 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 3416 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3417 | #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } | ||
| 3418 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3419 | #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } | ||
| 3420 | #else | ||
| 3421 | /** Peripheral AHB_SECURE_CTRL base address */ | ||
| 3422 | #define AHB_SECURE_CTRL_BASE (0x400AC000u) | ||
| 3423 | /** Peripheral AHB_SECURE_CTRL base pointer */ | ||
| 3424 | #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) | ||
| 3425 | /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ | ||
| 3426 | #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } | ||
| 3427 | /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ | ||
| 3428 | #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } | ||
| 3429 | #endif | ||
| 3430 | |||
| 3431 | /*! | ||
| 3432 | * @} | ||
| 3433 | */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ | ||
| 3434 | |||
| 3435 | |||
| 3436 | /* ---------------------------------------------------------------------------- | ||
| 3437 | -- ANACTRL Peripheral Access Layer | ||
| 3438 | ---------------------------------------------------------------------------- */ | ||
| 3439 | |||
| 3440 | /*! | ||
| 3441 | * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer | ||
| 3442 | * @{ | ||
| 3443 | */ | ||
| 3444 | |||
| 3445 | /** ANACTRL - Register Layout Typedef */ | ||
| 3446 | typedef struct { | ||
| 3447 | uint8_t RESERVED_0[4]; | ||
| 3448 | __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ | ||
| 3449 | uint8_t RESERVED_1[4]; | ||
| 3450 | __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ | ||
| 3451 | __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ | ||
| 3452 | __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ | ||
| 3453 | uint8_t RESERVED_2[8]; | ||
| 3454 | __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ | ||
| 3455 | __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ | ||
| 3456 | uint8_t RESERVED_3[8]; | ||
| 3457 | __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ | ||
| 3458 | __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ | ||
| 3459 | uint8_t RESERVED_4[192]; | ||
| 3460 | __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ | ||
| 3461 | } ANACTRL_Type; | ||
| 3462 | |||
| 3463 | /* ---------------------------------------------------------------------------- | ||
| 3464 | -- ANACTRL Register Masks | ||
| 3465 | ---------------------------------------------------------------------------- */ | ||
| 3466 | |||
| 3467 | /*! | ||
| 3468 | * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks | ||
| 3469 | * @{ | ||
| 3470 | */ | ||
| 3471 | |||
| 3472 | /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ | ||
| 3473 | /*! @{ */ | ||
| 3474 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) | ||
| 3475 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) | ||
| 3476 | /*! FLASH_PWRDWN - Flash Power Down status. | ||
| 3477 | * 0b0..Flash is not in power down mode. | ||
| 3478 | * 0b1..Flash is in power down mode. | ||
| 3479 | */ | ||
| 3480 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) | ||
| 3481 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) | ||
| 3482 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) | ||
| 3483 | /*! FLASH_INIT_ERROR - Flash initialization error status. | ||
| 3484 | * 0b0..No error. | ||
| 3485 | * 0b1..At least one error occured during flash initialization.. | ||
| 3486 | */ | ||
| 3487 | #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) | ||
| 3488 | /*! @} */ | ||
| 3489 | |||
| 3490 | /*! @name FREQ_ME_CTRL - Frequency Measure function control register */ | ||
| 3491 | /*! @{ */ | ||
| 3492 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) | ||
| 3493 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) | ||
| 3494 | /*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale | ||
| 3495 | */ | ||
| 3496 | #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) | ||
| 3497 | #define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) | ||
| 3498 | #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) | ||
| 3499 | /*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit | ||
| 3500 | * when the measurement cycle has completed and there is valid capture data in the CAPVAL field | ||
| 3501 | * (bits 30:0). | ||
| 3502 | */ | ||
| 3503 | #define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) | ||
| 3504 | /*! @} */ | ||
| 3505 | |||
| 3506 | /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ | ||
| 3507 | /*! @{ */ | ||
| 3508 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) | ||
| 3509 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) | ||
| 3510 | /*! ENA_12MHZCLK - 12 MHz clock control. | ||
| 3511 | * 0b0..12 MHz clock is disabled. | ||
| 3512 | * 0b1..12 MHz clock is enabled. | ||
| 3513 | */ | ||
| 3514 | #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) | ||
| 3515 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) | ||
| 3516 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) | ||
| 3517 | /*! DAC_TRIM - Frequency trim. | ||
| 3518 | */ | ||
| 3519 | #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) | ||
| 3520 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) | ||
| 3521 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) | ||
| 3522 | /*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, | ||
| 3523 | * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF | ||
| 3524 | * packets. | ||
| 3525 | */ | ||
| 3526 | #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) | ||
| 3527 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) | ||
| 3528 | #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) | ||
| 3529 | /*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. | ||
| 3530 | */ | ||
| 3531 | #define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) | ||
| 3532 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) | ||
| 3533 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) | ||
| 3534 | /*! ENA_96MHZCLK - 96 MHz clock control. | ||
| 3535 | * 0b0..96 MHz clock is disabled. | ||
| 3536 | * 0b1..96 MHz clock is enabled. | ||
| 3537 | */ | ||
| 3538 | #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) | ||
| 3539 | /*! @} */ | ||
| 3540 | |||
| 3541 | /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ | ||
| 3542 | /*! @{ */ | ||
| 3543 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) | ||
| 3544 | #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) | ||
| 3545 | /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. | ||
| 3546 | * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). | ||
| 3547 | * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by | ||
| 3548 | * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). | ||
| 3549 | */ | ||
| 3550 | #define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) | ||
| 3551 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) | ||
| 3552 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) | ||
| 3553 | /*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses | ||
| 3554 | * the threshold voltage of a SLVT transistor, this output signal will go high. It is also | ||
| 3555 | * possible to observe the clk_valid signal. | ||
| 3556 | */ | ||
| 3557 | #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) | ||
| 3558 | /*! @} */ | ||
| 3559 | |||
| 3560 | /*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ | ||
| 3561 | /*! @{ */ | ||
| 3562 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) | ||
| 3563 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) | ||
| 3564 | /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. | ||
| 3565 | * 0b0..XO AC buffer bypass is disabled. | ||
| 3566 | * 0b1..XO AC buffer bypass is enabled. | ||
| 3567 | */ | ||
| 3568 | #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) | ||
| 3569 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) | ||
| 3570 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) | ||
| 3571 | /*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. | ||
| 3572 | * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. | ||
| 3573 | * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. | ||
| 3574 | */ | ||
| 3575 | #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) | ||
| 3576 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) | ||
| 3577 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) | ||
| 3578 | /*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. | ||
| 3579 | * 0b0..High speed Crystal oscillator output to CPU system is disabled. | ||
| 3580 | * 0b1..High speed Crystal oscillator output to CPU system is enabled. | ||
| 3581 | */ | ||
| 3582 | #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) | ||
| 3583 | /*! @} */ | ||
| 3584 | |||
| 3585 | /*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ | ||
| 3586 | /*! @{ */ | ||
| 3587 | #define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) | ||
| 3588 | #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) | ||
| 3589 | /*! XO_READY - Indicates XO out frequency statibilty. | ||
| 3590 | * 0b0..XO output frequency is not yet stable. | ||
| 3591 | * 0b1..XO output frequency is stable. | ||
| 3592 | */ | ||
| 3593 | #define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) | ||
| 3594 | /*! @} */ | ||
| 3595 | |||
| 3596 | /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ | ||
| 3597 | /*! @{ */ | ||
| 3598 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) | ||
| 3599 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) | ||
| 3600 | /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. | ||
| 3601 | * 0b0..BOD VBAT interrupt is disabled. | ||
| 3602 | * 0b1..BOD VBAT interrupt is enabled. | ||
| 3603 | */ | ||
| 3604 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) | ||
| 3605 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) | ||
| 3606 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) | ||
| 3607 | /*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3608 | */ | ||
| 3609 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) | ||
| 3610 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) | ||
| 3611 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) | ||
| 3612 | /*! BODCORE_INT_ENABLE - BOD CORE interrupt control. | ||
| 3613 | * 0b0..BOD CORE interrupt is disabled. | ||
| 3614 | * 0b1..BOD CORE interrupt is enabled. | ||
| 3615 | */ | ||
| 3616 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) | ||
| 3617 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) | ||
| 3618 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) | ||
| 3619 | /*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3620 | */ | ||
| 3621 | #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) | ||
| 3622 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) | ||
| 3623 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) | ||
| 3624 | /*! DCDC_INT_ENABLE - DCDC interrupt control. | ||
| 3625 | * 0b0..DCDC interrupt is disabled. | ||
| 3626 | * 0b1..DCDC interrupt is enabled. | ||
| 3627 | */ | ||
| 3628 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) | ||
| 3629 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) | ||
| 3630 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) | ||
| 3631 | /*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. | ||
| 3632 | */ | ||
| 3633 | #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) | ||
| 3634 | /*! @} */ | ||
| 3635 | |||
| 3636 | /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ | ||
| 3637 | /*! @{ */ | ||
| 3638 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) | ||
| 3639 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) | ||
| 3640 | /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. | ||
| 3641 | * 0b0..No interrupt pending.. | ||
| 3642 | * 0b1..Interrupt pending.. | ||
| 3643 | */ | ||
| 3644 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) | ||
| 3645 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) | ||
| 3646 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) | ||
| 3647 | /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. | ||
| 3648 | * 0b0..No interrupt pending.. | ||
| 3649 | * 0b1..Interrupt pending.. | ||
| 3650 | */ | ||
| 3651 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) | ||
| 3652 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) | ||
| 3653 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) | ||
| 3654 | /*! BODVBAT_VAL - Current value of BOD VBAT power status output. | ||
| 3655 | * 0b0..VBAT voltage level is below the threshold. | ||
| 3656 | * 0b1..VBAT voltage level is above the threshold. | ||
| 3657 | */ | ||
| 3658 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) | ||
| 3659 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) | ||
| 3660 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) | ||
| 3661 | /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. | ||
| 3662 | * 0b0..No interrupt pending.. | ||
| 3663 | * 0b1..Interrupt pending.. | ||
| 3664 | */ | ||
| 3665 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) | ||
| 3666 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) | ||
| 3667 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) | ||
| 3668 | /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. | ||
| 3669 | * 0b0..No interrupt pending.. | ||
| 3670 | * 0b1..Interrupt pending.. | ||
| 3671 | */ | ||
| 3672 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) | ||
| 3673 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) | ||
| 3674 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) | ||
| 3675 | /*! BODCORE_VAL - Current value of BOD CORE power status output. | ||
| 3676 | * 0b0..CORE voltage level is below the threshold. | ||
| 3677 | * 0b1..CORE voltage level is above the threshold. | ||
| 3678 | */ | ||
| 3679 | #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) | ||
| 3680 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) | ||
| 3681 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) | ||
| 3682 | /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. | ||
| 3683 | * 0b0..No interrupt pending.. | ||
| 3684 | * 0b1..Interrupt pending.. | ||
| 3685 | */ | ||
| 3686 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) | ||
| 3687 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) | ||
| 3688 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) | ||
| 3689 | /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. | ||
| 3690 | * 0b0..No interrupt pending.. | ||
| 3691 | * 0b1..Interrupt pending.. | ||
| 3692 | */ | ||
| 3693 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) | ||
| 3694 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) | ||
| 3695 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) | ||
| 3696 | /*! DCDC_VAL - Current value of DCDC power status output. | ||
| 3697 | * 0b0..DCDC output Voltage is below the targeted regulation level. | ||
| 3698 | * 0b1..DCDC output Voltage is above the targeted regulation level. | ||
| 3699 | */ | ||
| 3700 | #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) | ||
| 3701 | /*! @} */ | ||
| 3702 | |||
| 3703 | /*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ | ||
| 3704 | /*! @{ */ | ||
| 3705 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) | ||
| 3706 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) | ||
| 3707 | /*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. | ||
| 3708 | * 0b00..High speed Crystal oscillator output to ADC is disabled. | ||
| 3709 | * 0b01..High speed Crystal oscillator output to ADC is enable. | ||
| 3710 | */ | ||
| 3711 | #define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) | ||
| 3712 | /*! @} */ | ||
| 3713 | |||
| 3714 | |||
| 3715 | /*! | ||
| 3716 | * @} | ||
| 3717 | */ /* end of group ANACTRL_Register_Masks */ | ||
| 3718 | |||
| 3719 | |||
| 3720 | /* ANACTRL - Peripheral instance base addresses */ | ||
| 3721 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 3722 | /** Peripheral ANACTRL base address */ | ||
| 3723 | #define ANACTRL_BASE (0x50013000u) | ||
| 3724 | /** Peripheral ANACTRL base address */ | ||
| 3725 | #define ANACTRL_BASE_NS (0x40013000u) | ||
| 3726 | /** Peripheral ANACTRL base pointer */ | ||
| 3727 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 3728 | /** Peripheral ANACTRL base pointer */ | ||
| 3729 | #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) | ||
| 3730 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3731 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 3732 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3733 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 3734 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3735 | #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } | ||
| 3736 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3737 | #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } | ||
| 3738 | #else | ||
| 3739 | /** Peripheral ANACTRL base address */ | ||
| 3740 | #define ANACTRL_BASE (0x40013000u) | ||
| 3741 | /** Peripheral ANACTRL base pointer */ | ||
| 3742 | #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) | ||
| 3743 | /** Array initializer of ANACTRL peripheral base addresses */ | ||
| 3744 | #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } | ||
| 3745 | /** Array initializer of ANACTRL peripheral base pointers */ | ||
| 3746 | #define ANACTRL_BASE_PTRS { ANACTRL } | ||
| 3747 | #endif | ||
| 3748 | |||
| 3749 | /*! | ||
| 3750 | * @} | ||
| 3751 | */ /* end of group ANACTRL_Peripheral_Access_Layer */ | ||
| 3752 | |||
| 3753 | |||
| 3754 | /* ---------------------------------------------------------------------------- | ||
| 3755 | -- CAN Peripheral Access Layer | ||
| 3756 | ---------------------------------------------------------------------------- */ | ||
| 3757 | |||
| 3758 | /*! | ||
| 3759 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer | ||
| 3760 | * @{ | ||
| 3761 | */ | ||
| 3762 | |||
| 3763 | /** CAN - Register Layout Typedef */ | ||
| 3764 | typedef struct { | ||
| 3765 | uint8_t RESERVED_0[12]; | ||
| 3766 | __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ | ||
| 3767 | __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ | ||
| 3768 | uint8_t RESERVED_1[4]; | ||
| 3769 | __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ | ||
| 3770 | __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ | ||
| 3771 | __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ | ||
| 3772 | __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ | ||
| 3773 | __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ | ||
| 3774 | __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ | ||
| 3775 | uint8_t RESERVED_2[16]; | ||
| 3776 | __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ | ||
| 3777 | __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ | ||
| 3778 | __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ | ||
| 3779 | uint8_t RESERVED_3[4]; | ||
| 3780 | __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ | ||
| 3781 | __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ | ||
| 3782 | __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ | ||
| 3783 | __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ | ||
| 3784 | uint8_t RESERVED_4[32]; | ||
| 3785 | __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ | ||
| 3786 | __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ | ||
| 3787 | __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ | ||
| 3788 | uint8_t RESERVED_5[4]; | ||
| 3789 | __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ | ||
| 3790 | __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ | ||
| 3791 | __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ | ||
| 3792 | __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ | ||
| 3793 | __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ | ||
| 3794 | __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ | ||
| 3795 | __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ | ||
| 3796 | __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ | ||
| 3797 | __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ | ||
| 3798 | __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ | ||
| 3799 | __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ | ||
| 3800 | __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ | ||
| 3801 | __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ | ||
| 3802 | __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ | ||
| 3803 | __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ | ||
| 3804 | __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ | ||
| 3805 | __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ | ||
| 3806 | __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ | ||
| 3807 | __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ | ||
| 3808 | __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ | ||
| 3809 | __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ | ||
| 3810 | __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ | ||
| 3811 | uint8_t RESERVED_6[8]; | ||
| 3812 | __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ | ||
| 3813 | __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ | ||
| 3814 | __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ | ||
| 3815 | uint8_t RESERVED_7[260]; | ||
| 3816 | __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ | ||
| 3817 | uint8_t RESERVED_8[508]; | ||
| 3818 | __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ | ||
| 3819 | uint8_t RESERVED_9[508]; | ||
| 3820 | __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ | ||
| 3821 | } CAN_Type; | ||
| 3822 | |||
| 3823 | /* ---------------------------------------------------------------------------- | ||
| 3824 | -- CAN Register Masks | ||
| 3825 | ---------------------------------------------------------------------------- */ | ||
| 3826 | |||
| 3827 | /*! | ||
| 3828 | * @addtogroup CAN_Register_Masks CAN Register Masks | ||
| 3829 | * @{ | ||
| 3830 | */ | ||
| 3831 | |||
| 3832 | /*! @name DBTP - Data Bit Timing Prescaler Register */ | ||
| 3833 | /*! @{ */ | ||
| 3834 | #define CAN_DBTP_DSJW_MASK (0xFU) | ||
| 3835 | #define CAN_DBTP_DSJW_SHIFT (0U) | ||
| 3836 | /*! DSJW - Data (re)synchronization jump width. | ||
| 3837 | */ | ||
| 3838 | #define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) | ||
| 3839 | #define CAN_DBTP_DTSEG2_MASK (0xF0U) | ||
| 3840 | #define CAN_DBTP_DTSEG2_SHIFT (4U) | ||
| 3841 | /*! DTSEG2 - Data time segment after sample point. | ||
| 3842 | */ | ||
| 3843 | #define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) | ||
| 3844 | #define CAN_DBTP_DTSEG1_MASK (0x1F00U) | ||
| 3845 | #define CAN_DBTP_DTSEG1_SHIFT (8U) | ||
| 3846 | /*! DTSEG1 - Data time segment before sample point. | ||
| 3847 | */ | ||
| 3848 | #define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) | ||
| 3849 | #define CAN_DBTP_DBRP_MASK (0x1F0000U) | ||
| 3850 | #define CAN_DBTP_DBRP_SHIFT (16U) | ||
| 3851 | /*! DBRP - Data bit rate prescaler. | ||
| 3852 | */ | ||
| 3853 | #define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) | ||
| 3854 | #define CAN_DBTP_TDC_MASK (0x800000U) | ||
| 3855 | #define CAN_DBTP_TDC_SHIFT (23U) | ||
| 3856 | /*! TDC - Transmitter delay compensation. | ||
| 3857 | */ | ||
| 3858 | #define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) | ||
| 3859 | /*! @} */ | ||
| 3860 | |||
| 3861 | /*! @name TEST - Test Register */ | ||
| 3862 | /*! @{ */ | ||
| 3863 | #define CAN_TEST_LBCK_MASK (0x10U) | ||
| 3864 | #define CAN_TEST_LBCK_SHIFT (4U) | ||
| 3865 | /*! LBCK - Loop back mode. | ||
| 3866 | */ | ||
| 3867 | #define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) | ||
| 3868 | #define CAN_TEST_TX_MASK (0x60U) | ||
| 3869 | #define CAN_TEST_TX_SHIFT (5U) | ||
| 3870 | /*! TX - Control of transmit pin. | ||
| 3871 | */ | ||
| 3872 | #define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) | ||
| 3873 | #define CAN_TEST_RX_MASK (0x80U) | ||
| 3874 | #define CAN_TEST_RX_SHIFT (7U) | ||
| 3875 | /*! RX - Monitors the actual value of the CAN_RXD. | ||
| 3876 | */ | ||
| 3877 | #define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) | ||
| 3878 | /*! @} */ | ||
| 3879 | |||
| 3880 | /*! @name CCCR - CC Control Register */ | ||
| 3881 | /*! @{ */ | ||
| 3882 | #define CAN_CCCR_INIT_MASK (0x1U) | ||
| 3883 | #define CAN_CCCR_INIT_SHIFT (0U) | ||
| 3884 | /*! INIT - Initialization. | ||
| 3885 | */ | ||
| 3886 | #define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) | ||
| 3887 | #define CAN_CCCR_CCE_MASK (0x2U) | ||
| 3888 | #define CAN_CCCR_CCE_SHIFT (1U) | ||
| 3889 | /*! CCE - Configuration change enable. | ||
| 3890 | */ | ||
| 3891 | #define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) | ||
| 3892 | #define CAN_CCCR_ASM_MASK (0x4U) | ||
| 3893 | #define CAN_CCCR_ASM_SHIFT (2U) | ||
| 3894 | /*! ASM - Restricted operational mode. | ||
| 3895 | */ | ||
| 3896 | #define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) | ||
| 3897 | #define CAN_CCCR_CSA_MASK (0x8U) | ||
| 3898 | #define CAN_CCCR_CSA_SHIFT (3U) | ||
| 3899 | /*! CSA - Clock Stop Acknowledge. | ||
| 3900 | */ | ||
| 3901 | #define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) | ||
| 3902 | #define CAN_CCCR_CSR_MASK (0x10U) | ||
| 3903 | #define CAN_CCCR_CSR_SHIFT (4U) | ||
| 3904 | /*! CSR - Clock Stop Request. | ||
| 3905 | */ | ||
| 3906 | #define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) | ||
| 3907 | #define CAN_CCCR_MON_MASK (0x20U) | ||
| 3908 | #define CAN_CCCR_MON_SHIFT (5U) | ||
| 3909 | /*! MON - Bus monitoring mode. | ||
| 3910 | */ | ||
| 3911 | #define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) | ||
| 3912 | #define CAN_CCCR_DAR_MASK (0x40U) | ||
| 3913 | #define CAN_CCCR_DAR_SHIFT (6U) | ||
| 3914 | /*! DAR - Disable automatic retransmission. | ||
| 3915 | */ | ||
| 3916 | #define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) | ||
| 3917 | #define CAN_CCCR_TEST_MASK (0x80U) | ||
| 3918 | #define CAN_CCCR_TEST_SHIFT (7U) | ||
| 3919 | /*! TEST - Test mode enable. | ||
| 3920 | */ | ||
| 3921 | #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) | ||
| 3922 | #define CAN_CCCR_FDOE_MASK (0x100U) | ||
| 3923 | #define CAN_CCCR_FDOE_SHIFT (8U) | ||
| 3924 | /*! FDOE - CAN FD operation enable. | ||
| 3925 | */ | ||
| 3926 | #define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) | ||
| 3927 | #define CAN_CCCR_BRSE_MASK (0x200U) | ||
| 3928 | #define CAN_CCCR_BRSE_SHIFT (9U) | ||
| 3929 | /*! BRSE - When CAN FD operation is disabled, this bit is not evaluated. | ||
| 3930 | */ | ||
| 3931 | #define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) | ||
| 3932 | #define CAN_CCCR_PXHD_MASK (0x1000U) | ||
| 3933 | #define CAN_CCCR_PXHD_SHIFT (12U) | ||
| 3934 | /*! PXHD - Protocol exception handling disable. | ||
| 3935 | */ | ||
| 3936 | #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) | ||
| 3937 | #define CAN_CCCR_EFBI_MASK (0x2000U) | ||
| 3938 | #define CAN_CCCR_EFBI_SHIFT (13U) | ||
| 3939 | /*! EFBI - Edge filtering during bus integration. | ||
| 3940 | */ | ||
| 3941 | #define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) | ||
| 3942 | #define CAN_CCCR_TXP_MASK (0x4000U) | ||
| 3943 | #define CAN_CCCR_TXP_SHIFT (14U) | ||
| 3944 | /*! TXP - Transmit pause. | ||
| 3945 | */ | ||
| 3946 | #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) | ||
| 3947 | #define CAN_CCCR_NISO_MASK (0x8000U) | ||
| 3948 | #define CAN_CCCR_NISO_SHIFT (15U) | ||
| 3949 | /*! NISO - Non ISO operation. | ||
| 3950 | */ | ||
| 3951 | #define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) | ||
| 3952 | /*! @} */ | ||
| 3953 | |||
| 3954 | /*! @name NBTP - Nominal Bit Timing and Prescaler Register */ | ||
| 3955 | /*! @{ */ | ||
| 3956 | #define CAN_NBTP_NTSEG2_MASK (0x7FU) | ||
| 3957 | #define CAN_NBTP_NTSEG2_SHIFT (0U) | ||
| 3958 | /*! NTSEG2 - Nominal time segment after sample point. | ||
| 3959 | */ | ||
| 3960 | #define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) | ||
| 3961 | #define CAN_NBTP_NTSEG1_MASK (0xFF00U) | ||
| 3962 | #define CAN_NBTP_NTSEG1_SHIFT (8U) | ||
| 3963 | /*! NTSEG1 - Nominal time segment before sample point. | ||
| 3964 | */ | ||
| 3965 | #define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) | ||
| 3966 | #define CAN_NBTP_NBRP_MASK (0x1FF0000U) | ||
| 3967 | #define CAN_NBTP_NBRP_SHIFT (16U) | ||
| 3968 | /*! NBRP - Nominal bit rate prescaler. | ||
| 3969 | */ | ||
| 3970 | #define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) | ||
| 3971 | #define CAN_NBTP_NSJW_MASK (0xFE000000U) | ||
| 3972 | #define CAN_NBTP_NSJW_SHIFT (25U) | ||
| 3973 | /*! NSJW - Nominal (re)synchronization jump width. | ||
| 3974 | */ | ||
| 3975 | #define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) | ||
| 3976 | /*! @} */ | ||
| 3977 | |||
| 3978 | /*! @name TSCC - Timestamp Counter Configuration */ | ||
| 3979 | /*! @{ */ | ||
| 3980 | #define CAN_TSCC_TSS_MASK (0x3U) | ||
| 3981 | #define CAN_TSCC_TSS_SHIFT (0U) | ||
| 3982 | /*! TSS - Timestamp select. | ||
| 3983 | */ | ||
| 3984 | #define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) | ||
| 3985 | #define CAN_TSCC_TCP_MASK (0xF0000U) | ||
| 3986 | #define CAN_TSCC_TCP_SHIFT (16U) | ||
| 3987 | /*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. | ||
| 3988 | */ | ||
| 3989 | #define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) | ||
| 3990 | /*! @} */ | ||
| 3991 | |||
| 3992 | /*! @name TSCV - Timestamp Counter Value */ | ||
| 3993 | /*! @{ */ | ||
| 3994 | #define CAN_TSCV_TSC_MASK (0xFFFFU) | ||
| 3995 | #define CAN_TSCV_TSC_SHIFT (0U) | ||
| 3996 | /*! TSC - Timestamp counter. | ||
| 3997 | */ | ||
| 3998 | #define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) | ||
| 3999 | /*! @} */ | ||
| 4000 | |||
| 4001 | /*! @name TOCC - Timeout Counter Configuration */ | ||
| 4002 | /*! @{ */ | ||
| 4003 | #define CAN_TOCC_ETOC_MASK (0x1U) | ||
| 4004 | #define CAN_TOCC_ETOC_SHIFT (0U) | ||
| 4005 | /*! ETOC - Enable timeout counter. | ||
| 4006 | */ | ||
| 4007 | #define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) | ||
| 4008 | #define CAN_TOCC_TOS_MASK (0x6U) | ||
| 4009 | #define CAN_TOCC_TOS_SHIFT (1U) | ||
| 4010 | /*! TOS - Timeout select. | ||
| 4011 | */ | ||
| 4012 | #define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) | ||
| 4013 | #define CAN_TOCC_TOP_MASK (0xFFFF0000U) | ||
| 4014 | #define CAN_TOCC_TOP_SHIFT (16U) | ||
| 4015 | /*! TOP - Timeout period. | ||
| 4016 | */ | ||
| 4017 | #define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) | ||
| 4018 | /*! @} */ | ||
| 4019 | |||
| 4020 | /*! @name TOCV - Timeout Counter Value */ | ||
| 4021 | /*! @{ */ | ||
| 4022 | #define CAN_TOCV_TOC_MASK (0xFFFFU) | ||
| 4023 | #define CAN_TOCV_TOC_SHIFT (0U) | ||
| 4024 | /*! TOC - Timeout counter. | ||
| 4025 | */ | ||
| 4026 | #define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) | ||
| 4027 | /*! @} */ | ||
| 4028 | |||
| 4029 | /*! @name ECR - Error Counter Register */ | ||
| 4030 | /*! @{ */ | ||
| 4031 | #define CAN_ECR_TEC_MASK (0xFFU) | ||
| 4032 | #define CAN_ECR_TEC_SHIFT (0U) | ||
| 4033 | /*! TEC - Transmit error counter. | ||
| 4034 | */ | ||
| 4035 | #define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) | ||
| 4036 | #define CAN_ECR_REC_MASK (0x7F00U) | ||
| 4037 | #define CAN_ECR_REC_SHIFT (8U) | ||
| 4038 | /*! REC - Receive error counter. | ||
| 4039 | */ | ||
| 4040 | #define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) | ||
| 4041 | #define CAN_ECR_RP_MASK (0x8000U) | ||
| 4042 | #define CAN_ECR_RP_SHIFT (15U) | ||
| 4043 | /*! RP - Receive error passive. | ||
| 4044 | */ | ||
| 4045 | #define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) | ||
| 4046 | #define CAN_ECR_CEL_MASK (0xFF0000U) | ||
| 4047 | #define CAN_ECR_CEL_SHIFT (16U) | ||
| 4048 | /*! CEL - CAN error logging. | ||
| 4049 | */ | ||
| 4050 | #define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) | ||
| 4051 | /*! @} */ | ||
| 4052 | |||
| 4053 | /*! @name PSR - Protocol Status Register */ | ||
| 4054 | /*! @{ */ | ||
| 4055 | #define CAN_PSR_LEC_MASK (0x7U) | ||
| 4056 | #define CAN_PSR_LEC_SHIFT (0U) | ||
| 4057 | /*! LEC - Last error code. | ||
| 4058 | */ | ||
| 4059 | #define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) | ||
| 4060 | #define CAN_PSR_ACT_MASK (0x18U) | ||
| 4061 | #define CAN_PSR_ACT_SHIFT (3U) | ||
| 4062 | /*! ACT - Activity. | ||
| 4063 | */ | ||
| 4064 | #define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) | ||
| 4065 | #define CAN_PSR_EP_MASK (0x20U) | ||
| 4066 | #define CAN_PSR_EP_SHIFT (5U) | ||
| 4067 | /*! EP - Error Passive. | ||
| 4068 | */ | ||
| 4069 | #define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) | ||
| 4070 | #define CAN_PSR_EW_MASK (0x40U) | ||
| 4071 | #define CAN_PSR_EW_SHIFT (6U) | ||
| 4072 | /*! EW - Warning status. | ||
| 4073 | */ | ||
| 4074 | #define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) | ||
| 4075 | #define CAN_PSR_BO_MASK (0x80U) | ||
| 4076 | #define CAN_PSR_BO_SHIFT (7U) | ||
| 4077 | /*! BO - Bus Off Status. | ||
| 4078 | */ | ||
| 4079 | #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) | ||
| 4080 | #define CAN_PSR_DLEC_MASK (0x700U) | ||
| 4081 | #define CAN_PSR_DLEC_SHIFT (8U) | ||
| 4082 | /*! DLEC - Data phase last error code. | ||
| 4083 | */ | ||
| 4084 | #define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) | ||
| 4085 | #define CAN_PSR_RESI_MASK (0x800U) | ||
| 4086 | #define CAN_PSR_RESI_SHIFT (11U) | ||
| 4087 | /*! RESI - ESI flag of the last received CAN FD message. | ||
| 4088 | */ | ||
| 4089 | #define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) | ||
| 4090 | #define CAN_PSR_RBRS_MASK (0x1000U) | ||
| 4091 | #define CAN_PSR_RBRS_SHIFT (12U) | ||
| 4092 | /*! RBRS - BRS flag of last received CAN FD message. | ||
| 4093 | */ | ||
| 4094 | #define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) | ||
| 4095 | #define CAN_PSR_RFDF_MASK (0x2000U) | ||
| 4096 | #define CAN_PSR_RFDF_SHIFT (13U) | ||
| 4097 | /*! RFDF - Received a CAN FD message. | ||
| 4098 | */ | ||
| 4099 | #define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) | ||
| 4100 | #define CAN_PSR_PXE_MASK (0x4000U) | ||
| 4101 | #define CAN_PSR_PXE_SHIFT (14U) | ||
| 4102 | /*! PXE - Protocol exception event. | ||
| 4103 | */ | ||
| 4104 | #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) | ||
| 4105 | #define CAN_PSR_TDCV_MASK (0x7F0000U) | ||
| 4106 | #define CAN_PSR_TDCV_SHIFT (16U) | ||
| 4107 | /*! TDCV - Transmitter delay compensation value. | ||
| 4108 | */ | ||
| 4109 | #define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) | ||
| 4110 | /*! @} */ | ||
| 4111 | |||
| 4112 | /*! @name TDCR - Transmitter Delay Compensator Register */ | ||
| 4113 | /*! @{ */ | ||
| 4114 | #define CAN_TDCR_TDCF_MASK (0x7FU) | ||
| 4115 | #define CAN_TDCR_TDCF_SHIFT (0U) | ||
| 4116 | /*! TDCF - Transmitter delay compensation filter window length. | ||
| 4117 | */ | ||
| 4118 | #define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) | ||
| 4119 | #define CAN_TDCR_TDCO_MASK (0x7F00U) | ||
| 4120 | #define CAN_TDCR_TDCO_SHIFT (8U) | ||
| 4121 | /*! TDCO - Transmitter delay compensation offset. | ||
| 4122 | */ | ||
| 4123 | #define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) | ||
| 4124 | /*! @} */ | ||
| 4125 | |||
| 4126 | /*! @name IR - Interrupt Register */ | ||
| 4127 | /*! @{ */ | ||
| 4128 | #define CAN_IR_RF0N_MASK (0x1U) | ||
| 4129 | #define CAN_IR_RF0N_SHIFT (0U) | ||
| 4130 | /*! RF0N - Rx FIFO 0 new message. | ||
| 4131 | */ | ||
| 4132 | #define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) | ||
| 4133 | #define CAN_IR_RF0W_MASK (0x2U) | ||
| 4134 | #define CAN_IR_RF0W_SHIFT (1U) | ||
| 4135 | /*! RF0W - Rx FIFO 0 watermark reached. | ||
| 4136 | */ | ||
| 4137 | #define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) | ||
| 4138 | #define CAN_IR_RF0F_MASK (0x4U) | ||
| 4139 | #define CAN_IR_RF0F_SHIFT (2U) | ||
| 4140 | /*! RF0F - Rx FIFO 0 full. | ||
| 4141 | */ | ||
| 4142 | #define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) | ||
| 4143 | #define CAN_IR_RF0L_MASK (0x8U) | ||
| 4144 | #define CAN_IR_RF0L_SHIFT (3U) | ||
| 4145 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 4146 | */ | ||
| 4147 | #define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) | ||
| 4148 | #define CAN_IR_RF1N_MASK (0x10U) | ||
| 4149 | #define CAN_IR_RF1N_SHIFT (4U) | ||
| 4150 | /*! RF1N - Rx FIFO 1 new message. | ||
| 4151 | */ | ||
| 4152 | #define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) | ||
| 4153 | #define CAN_IR_RF1W_MASK (0x20U) | ||
| 4154 | #define CAN_IR_RF1W_SHIFT (5U) | ||
| 4155 | /*! RF1W - Rx FIFO 1 watermark reached. | ||
| 4156 | */ | ||
| 4157 | #define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) | ||
| 4158 | #define CAN_IR_RF1F_MASK (0x40U) | ||
| 4159 | #define CAN_IR_RF1F_SHIFT (6U) | ||
| 4160 | /*! RF1F - Rx FIFO 1 full. | ||
| 4161 | */ | ||
| 4162 | #define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) | ||
| 4163 | #define CAN_IR_RF1L_MASK (0x80U) | ||
| 4164 | #define CAN_IR_RF1L_SHIFT (7U) | ||
| 4165 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 4166 | */ | ||
| 4167 | #define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) | ||
| 4168 | #define CAN_IR_HPM_MASK (0x100U) | ||
| 4169 | #define CAN_IR_HPM_SHIFT (8U) | ||
| 4170 | /*! HPM - High priority message. | ||
| 4171 | */ | ||
| 4172 | #define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) | ||
| 4173 | #define CAN_IR_TC_MASK (0x200U) | ||
| 4174 | #define CAN_IR_TC_SHIFT (9U) | ||
| 4175 | /*! TC - Transmission completed. | ||
| 4176 | */ | ||
| 4177 | #define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) | ||
| 4178 | #define CAN_IR_TCF_MASK (0x400U) | ||
| 4179 | #define CAN_IR_TCF_SHIFT (10U) | ||
| 4180 | /*! TCF - Transmission cancellation finished. | ||
| 4181 | */ | ||
| 4182 | #define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) | ||
| 4183 | #define CAN_IR_TFE_MASK (0x800U) | ||
| 4184 | #define CAN_IR_TFE_SHIFT (11U) | ||
| 4185 | /*! TFE - Tx FIFO empty. | ||
| 4186 | */ | ||
| 4187 | #define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) | ||
| 4188 | #define CAN_IR_TEFN_MASK (0x1000U) | ||
| 4189 | #define CAN_IR_TEFN_SHIFT (12U) | ||
| 4190 | /*! TEFN - Tx event FIFO new entry. | ||
| 4191 | */ | ||
| 4192 | #define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) | ||
| 4193 | #define CAN_IR_TEFW_MASK (0x2000U) | ||
| 4194 | #define CAN_IR_TEFW_SHIFT (13U) | ||
| 4195 | /*! TEFW - Tx event FIFO watermark reached. | ||
| 4196 | */ | ||
| 4197 | #define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) | ||
| 4198 | #define CAN_IR_TEFF_MASK (0x4000U) | ||
| 4199 | #define CAN_IR_TEFF_SHIFT (14U) | ||
| 4200 | /*! TEFF - Tx event FIFO full. | ||
| 4201 | */ | ||
| 4202 | #define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) | ||
| 4203 | #define CAN_IR_TEFL_MASK (0x8000U) | ||
| 4204 | #define CAN_IR_TEFL_SHIFT (15U) | ||
| 4205 | /*! TEFL - Tx event FIFO element lost. | ||
| 4206 | */ | ||
| 4207 | #define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) | ||
| 4208 | #define CAN_IR_TSW_MASK (0x10000U) | ||
| 4209 | #define CAN_IR_TSW_SHIFT (16U) | ||
| 4210 | /*! TSW - Timestamp wraparound. | ||
| 4211 | */ | ||
| 4212 | #define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) | ||
| 4213 | #define CAN_IR_MRAF_MASK (0x20000U) | ||
| 4214 | #define CAN_IR_MRAF_SHIFT (17U) | ||
| 4215 | /*! MRAF - Message RAM access failure. | ||
| 4216 | */ | ||
| 4217 | #define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) | ||
| 4218 | #define CAN_IR_TOO_MASK (0x40000U) | ||
| 4219 | #define CAN_IR_TOO_SHIFT (18U) | ||
| 4220 | /*! TOO - Timeout occurred. | ||
| 4221 | */ | ||
| 4222 | #define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) | ||
| 4223 | #define CAN_IR_DRX_MASK (0x80000U) | ||
| 4224 | #define CAN_IR_DRX_SHIFT (19U) | ||
| 4225 | /*! DRX - Message stored in dedicated Rx buffer. | ||
| 4226 | */ | ||
| 4227 | #define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) | ||
| 4228 | #define CAN_IR_BEC_MASK (0x100000U) | ||
| 4229 | #define CAN_IR_BEC_SHIFT (20U) | ||
| 4230 | /*! BEC - Bit error corrected. | ||
| 4231 | */ | ||
| 4232 | #define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) | ||
| 4233 | #define CAN_IR_BEU_MASK (0x200000U) | ||
| 4234 | #define CAN_IR_BEU_SHIFT (21U) | ||
| 4235 | /*! BEU - Bit error uncorrected. | ||
| 4236 | */ | ||
| 4237 | #define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) | ||
| 4238 | #define CAN_IR_ELO_MASK (0x400000U) | ||
| 4239 | #define CAN_IR_ELO_SHIFT (22U) | ||
| 4240 | /*! ELO - Error logging overflow. | ||
| 4241 | */ | ||
| 4242 | #define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) | ||
| 4243 | #define CAN_IR_EP_MASK (0x800000U) | ||
| 4244 | #define CAN_IR_EP_SHIFT (23U) | ||
| 4245 | /*! EP - Error passive. | ||
| 4246 | */ | ||
| 4247 | #define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) | ||
| 4248 | #define CAN_IR_EW_MASK (0x1000000U) | ||
| 4249 | #define CAN_IR_EW_SHIFT (24U) | ||
| 4250 | /*! EW - Warning status. | ||
| 4251 | */ | ||
| 4252 | #define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) | ||
| 4253 | #define CAN_IR_BO_MASK (0x2000000U) | ||
| 4254 | #define CAN_IR_BO_SHIFT (25U) | ||
| 4255 | /*! BO - Bus_Off Status. | ||
| 4256 | */ | ||
| 4257 | #define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) | ||
| 4258 | #define CAN_IR_WDI_MASK (0x4000000U) | ||
| 4259 | #define CAN_IR_WDI_SHIFT (26U) | ||
| 4260 | /*! WDI - Watchdog interrupt. | ||
| 4261 | */ | ||
| 4262 | #define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) | ||
| 4263 | #define CAN_IR_PEA_MASK (0x8000000U) | ||
| 4264 | #define CAN_IR_PEA_SHIFT (27U) | ||
| 4265 | /*! PEA - Protocol error in arbitration phase. | ||
| 4266 | */ | ||
| 4267 | #define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) | ||
| 4268 | #define CAN_IR_PED_MASK (0x10000000U) | ||
| 4269 | #define CAN_IR_PED_SHIFT (28U) | ||
| 4270 | /*! PED - Protocol error in data phase. | ||
| 4271 | */ | ||
| 4272 | #define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) | ||
| 4273 | #define CAN_IR_ARA_MASK (0x20000000U) | ||
| 4274 | #define CAN_IR_ARA_SHIFT (29U) | ||
| 4275 | /*! ARA - Access to reserved address. | ||
| 4276 | */ | ||
| 4277 | #define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) | ||
| 4278 | /*! @} */ | ||
| 4279 | |||
| 4280 | /*! @name IE - Interrupt Enable */ | ||
| 4281 | /*! @{ */ | ||
| 4282 | #define CAN_IE_RF0NE_MASK (0x1U) | ||
| 4283 | #define CAN_IE_RF0NE_SHIFT (0U) | ||
| 4284 | /*! RF0NE - Rx FIFO 0 new message interrupt enable. | ||
| 4285 | */ | ||
| 4286 | #define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) | ||
| 4287 | #define CAN_IE_RF0WE_MASK (0x2U) | ||
| 4288 | #define CAN_IE_RF0WE_SHIFT (1U) | ||
| 4289 | /*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. | ||
| 4290 | */ | ||
| 4291 | #define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) | ||
| 4292 | #define CAN_IE_RF0FE_MASK (0x4U) | ||
| 4293 | #define CAN_IE_RF0FE_SHIFT (2U) | ||
| 4294 | /*! RF0FE - Rx FIFO 0 full interrupt enable. | ||
| 4295 | */ | ||
| 4296 | #define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) | ||
| 4297 | #define CAN_IE_RF0LE_MASK (0x8U) | ||
| 4298 | #define CAN_IE_RF0LE_SHIFT (3U) | ||
| 4299 | /*! RF0LE - Rx FIFO 0 message lost interrupt enable. | ||
| 4300 | */ | ||
| 4301 | #define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) | ||
| 4302 | #define CAN_IE_RF1NE_MASK (0x10U) | ||
| 4303 | #define CAN_IE_RF1NE_SHIFT (4U) | ||
| 4304 | /*! RF1NE - Rx FIFO 1 new message interrupt enable. | ||
| 4305 | */ | ||
| 4306 | #define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) | ||
| 4307 | #define CAN_IE_RF1WE_MASK (0x20U) | ||
| 4308 | #define CAN_IE_RF1WE_SHIFT (5U) | ||
| 4309 | /*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. | ||
| 4310 | */ | ||
| 4311 | #define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) | ||
| 4312 | #define CAN_IE_RF1FE_MASK (0x40U) | ||
| 4313 | #define CAN_IE_RF1FE_SHIFT (6U) | ||
| 4314 | /*! RF1FE - Rx FIFO 1 full interrupt enable. | ||
| 4315 | */ | ||
| 4316 | #define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) | ||
| 4317 | #define CAN_IE_RF1LE_MASK (0x80U) | ||
| 4318 | #define CAN_IE_RF1LE_SHIFT (7U) | ||
| 4319 | /*! RF1LE - Rx FIFO 1 message lost interrupt enable. | ||
| 4320 | */ | ||
| 4321 | #define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) | ||
| 4322 | #define CAN_IE_HPME_MASK (0x100U) | ||
| 4323 | #define CAN_IE_HPME_SHIFT (8U) | ||
| 4324 | /*! HPME - High priority message interrupt enable. | ||
| 4325 | */ | ||
| 4326 | #define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) | ||
| 4327 | #define CAN_IE_TCE_MASK (0x200U) | ||
| 4328 | #define CAN_IE_TCE_SHIFT (9U) | ||
| 4329 | /*! TCE - Transmission completed interrupt enable. | ||
| 4330 | */ | ||
| 4331 | #define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) | ||
| 4332 | #define CAN_IE_TCFE_MASK (0x400U) | ||
| 4333 | #define CAN_IE_TCFE_SHIFT (10U) | ||
| 4334 | /*! TCFE - Transmission cancellation finished interrupt enable. | ||
| 4335 | */ | ||
| 4336 | #define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) | ||
| 4337 | #define CAN_IE_TFEE_MASK (0x800U) | ||
| 4338 | #define CAN_IE_TFEE_SHIFT (11U) | ||
| 4339 | /*! TFEE - Tx FIFO empty interrupt enable. | ||
| 4340 | */ | ||
| 4341 | #define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) | ||
| 4342 | #define CAN_IE_TEFNE_MASK (0x1000U) | ||
| 4343 | #define CAN_IE_TEFNE_SHIFT (12U) | ||
| 4344 | /*! TEFNE - Tx event FIFO new entry interrupt enable. | ||
| 4345 | */ | ||
| 4346 | #define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) | ||
| 4347 | #define CAN_IE_TEFWE_MASK (0x2000U) | ||
| 4348 | #define CAN_IE_TEFWE_SHIFT (13U) | ||
| 4349 | /*! TEFWE - Tx event FIFO watermark reached interrupt enable. | ||
| 4350 | */ | ||
| 4351 | #define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) | ||
| 4352 | #define CAN_IE_TEFFE_MASK (0x4000U) | ||
| 4353 | #define CAN_IE_TEFFE_SHIFT (14U) | ||
| 4354 | /*! TEFFE - Tx event FIFO full interrupt enable. | ||
| 4355 | */ | ||
| 4356 | #define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) | ||
| 4357 | #define CAN_IE_TEFLE_MASK (0x8000U) | ||
| 4358 | #define CAN_IE_TEFLE_SHIFT (15U) | ||
| 4359 | /*! TEFLE - Tx event FIFO element lost interrupt enable. | ||
| 4360 | */ | ||
| 4361 | #define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) | ||
| 4362 | #define CAN_IE_TSWE_MASK (0x10000U) | ||
| 4363 | #define CAN_IE_TSWE_SHIFT (16U) | ||
| 4364 | /*! TSWE - Timestamp wraparound interrupt enable. | ||
| 4365 | */ | ||
| 4366 | #define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) | ||
| 4367 | #define CAN_IE_MRAFE_MASK (0x20000U) | ||
| 4368 | #define CAN_IE_MRAFE_SHIFT (17U) | ||
| 4369 | /*! MRAFE - Message RAM access failure interrupt enable. | ||
| 4370 | */ | ||
| 4371 | #define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) | ||
| 4372 | #define CAN_IE_TOOE_MASK (0x40000U) | ||
| 4373 | #define CAN_IE_TOOE_SHIFT (18U) | ||
| 4374 | /*! TOOE - Timeout occurred interrupt enable. | ||
| 4375 | */ | ||
| 4376 | #define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) | ||
| 4377 | #define CAN_IE_DRXE_MASK (0x80000U) | ||
| 4378 | #define CAN_IE_DRXE_SHIFT (19U) | ||
| 4379 | /*! DRXE - Message stored in dedicated Rx buffer interrupt enable. | ||
| 4380 | */ | ||
| 4381 | #define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) | ||
| 4382 | #define CAN_IE_BECE_MASK (0x100000U) | ||
| 4383 | #define CAN_IE_BECE_SHIFT (20U) | ||
| 4384 | /*! BECE - Bit error corrected interrupt enable. | ||
| 4385 | */ | ||
| 4386 | #define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) | ||
| 4387 | #define CAN_IE_BEUE_MASK (0x200000U) | ||
| 4388 | #define CAN_IE_BEUE_SHIFT (21U) | ||
| 4389 | /*! BEUE - Bit error uncorrected interrupt enable. | ||
| 4390 | */ | ||
| 4391 | #define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) | ||
| 4392 | #define CAN_IE_ELOE_MASK (0x400000U) | ||
| 4393 | #define CAN_IE_ELOE_SHIFT (22U) | ||
| 4394 | /*! ELOE - Error logging overflow interrupt enable. | ||
| 4395 | */ | ||
| 4396 | #define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) | ||
| 4397 | #define CAN_IE_EPE_MASK (0x800000U) | ||
| 4398 | #define CAN_IE_EPE_SHIFT (23U) | ||
| 4399 | /*! EPE - Error passive interrupt enable. | ||
| 4400 | */ | ||
| 4401 | #define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) | ||
| 4402 | #define CAN_IE_EWE_MASK (0x1000000U) | ||
| 4403 | #define CAN_IE_EWE_SHIFT (24U) | ||
| 4404 | /*! EWE - Warning status interrupt enable. | ||
| 4405 | */ | ||
| 4406 | #define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) | ||
| 4407 | #define CAN_IE_BOE_MASK (0x2000000U) | ||
| 4408 | #define CAN_IE_BOE_SHIFT (25U) | ||
| 4409 | /*! BOE - Bus_Off Status interrupt enable. | ||
| 4410 | */ | ||
| 4411 | #define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) | ||
| 4412 | #define CAN_IE_WDIE_MASK (0x4000000U) | ||
| 4413 | #define CAN_IE_WDIE_SHIFT (26U) | ||
| 4414 | /*! WDIE - Watchdog interrupt enable. | ||
| 4415 | */ | ||
| 4416 | #define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) | ||
| 4417 | #define CAN_IE_PEAE_MASK (0x8000000U) | ||
| 4418 | #define CAN_IE_PEAE_SHIFT (27U) | ||
| 4419 | /*! PEAE - Protocol error in arbitration phase interrupt enable. | ||
| 4420 | */ | ||
| 4421 | #define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) | ||
| 4422 | #define CAN_IE_PEDE_MASK (0x10000000U) | ||
| 4423 | #define CAN_IE_PEDE_SHIFT (28U) | ||
| 4424 | /*! PEDE - Protocol error in data phase interrupt enable. | ||
| 4425 | */ | ||
| 4426 | #define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) | ||
| 4427 | #define CAN_IE_ARAE_MASK (0x20000000U) | ||
| 4428 | #define CAN_IE_ARAE_SHIFT (29U) | ||
| 4429 | /*! ARAE - Access to reserved address interrupt enable. | ||
| 4430 | */ | ||
| 4431 | #define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) | ||
| 4432 | /*! @} */ | ||
| 4433 | |||
| 4434 | /*! @name ILS - Interrupt Line Select */ | ||
| 4435 | /*! @{ */ | ||
| 4436 | #define CAN_ILS_RF0NL_MASK (0x1U) | ||
| 4437 | #define CAN_ILS_RF0NL_SHIFT (0U) | ||
| 4438 | /*! RF0NL - Rx FIFO 0 new message interrupt line. | ||
| 4439 | */ | ||
| 4440 | #define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) | ||
| 4441 | #define CAN_ILS_RF0WL_MASK (0x2U) | ||
| 4442 | #define CAN_ILS_RF0WL_SHIFT (1U) | ||
| 4443 | /*! RF0WL - Rx FIFO 0 watermark reached interrupt line. | ||
| 4444 | */ | ||
| 4445 | #define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) | ||
| 4446 | #define CAN_ILS_RF0FL_MASK (0x4U) | ||
| 4447 | #define CAN_ILS_RF0FL_SHIFT (2U) | ||
| 4448 | /*! RF0FL - Rx FIFO 0 full interrupt line. | ||
| 4449 | */ | ||
| 4450 | #define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) | ||
| 4451 | #define CAN_ILS_RF0LL_MASK (0x8U) | ||
| 4452 | #define CAN_ILS_RF0LL_SHIFT (3U) | ||
| 4453 | /*! RF0LL - Rx FIFO 0 message lost interrupt line. | ||
| 4454 | */ | ||
| 4455 | #define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) | ||
| 4456 | #define CAN_ILS_RF1NL_MASK (0x10U) | ||
| 4457 | #define CAN_ILS_RF1NL_SHIFT (4U) | ||
| 4458 | /*! RF1NL - Rx FIFO 1 new message interrupt line. | ||
| 4459 | */ | ||
| 4460 | #define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) | ||
| 4461 | #define CAN_ILS_RF1WL_MASK (0x20U) | ||
| 4462 | #define CAN_ILS_RF1WL_SHIFT (5U) | ||
| 4463 | /*! RF1WL - Rx FIFO 1 watermark reached interrupt line. | ||
| 4464 | */ | ||
| 4465 | #define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) | ||
| 4466 | #define CAN_ILS_RF1FL_MASK (0x40U) | ||
| 4467 | #define CAN_ILS_RF1FL_SHIFT (6U) | ||
| 4468 | /*! RF1FL - Rx FIFO 1 full interrupt line. | ||
| 4469 | */ | ||
| 4470 | #define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) | ||
| 4471 | #define CAN_ILS_RF1LL_MASK (0x80U) | ||
| 4472 | #define CAN_ILS_RF1LL_SHIFT (7U) | ||
| 4473 | /*! RF1LL - Rx FIFO 1 message lost interrupt line. | ||
| 4474 | */ | ||
| 4475 | #define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) | ||
| 4476 | #define CAN_ILS_HPML_MASK (0x100U) | ||
| 4477 | #define CAN_ILS_HPML_SHIFT (8U) | ||
| 4478 | /*! HPML - High priority message interrupt line. | ||
| 4479 | */ | ||
| 4480 | #define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) | ||
| 4481 | #define CAN_ILS_TCL_MASK (0x200U) | ||
| 4482 | #define CAN_ILS_TCL_SHIFT (9U) | ||
| 4483 | /*! TCL - Transmission completed interrupt line. | ||
| 4484 | */ | ||
| 4485 | #define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) | ||
| 4486 | #define CAN_ILS_TCFL_MASK (0x400U) | ||
| 4487 | #define CAN_ILS_TCFL_SHIFT (10U) | ||
| 4488 | /*! TCFL - Transmission cancellation finished interrupt line. | ||
| 4489 | */ | ||
| 4490 | #define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) | ||
| 4491 | #define CAN_ILS_TFEL_MASK (0x800U) | ||
| 4492 | #define CAN_ILS_TFEL_SHIFT (11U) | ||
| 4493 | /*! TFEL - Tx FIFO empty interrupt line. | ||
| 4494 | */ | ||
| 4495 | #define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) | ||
| 4496 | #define CAN_ILS_TEFNL_MASK (0x1000U) | ||
| 4497 | #define CAN_ILS_TEFNL_SHIFT (12U) | ||
| 4498 | /*! TEFNL - Tx event FIFO new entry interrupt line. | ||
| 4499 | */ | ||
| 4500 | #define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) | ||
| 4501 | #define CAN_ILS_TEFWL_MASK (0x2000U) | ||
| 4502 | #define CAN_ILS_TEFWL_SHIFT (13U) | ||
| 4503 | /*! TEFWL - Tx event FIFO watermark reached interrupt line. | ||
| 4504 | */ | ||
| 4505 | #define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) | ||
| 4506 | #define CAN_ILS_TEFFL_MASK (0x4000U) | ||
| 4507 | #define CAN_ILS_TEFFL_SHIFT (14U) | ||
| 4508 | /*! TEFFL - Tx event FIFO full interrupt line. | ||
| 4509 | */ | ||
| 4510 | #define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) | ||
| 4511 | #define CAN_ILS_TEFLL_MASK (0x8000U) | ||
| 4512 | #define CAN_ILS_TEFLL_SHIFT (15U) | ||
| 4513 | /*! TEFLL - Tx event FIFO element lost interrupt line. | ||
| 4514 | */ | ||
| 4515 | #define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) | ||
| 4516 | #define CAN_ILS_TSWL_MASK (0x10000U) | ||
| 4517 | #define CAN_ILS_TSWL_SHIFT (16U) | ||
| 4518 | /*! TSWL - Timestamp wraparound interrupt line. | ||
| 4519 | */ | ||
| 4520 | #define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) | ||
| 4521 | #define CAN_ILS_MRAFL_MASK (0x20000U) | ||
| 4522 | #define CAN_ILS_MRAFL_SHIFT (17U) | ||
| 4523 | /*! MRAFL - Message RAM access failure interrupt line. | ||
| 4524 | */ | ||
| 4525 | #define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) | ||
| 4526 | #define CAN_ILS_TOOL_MASK (0x40000U) | ||
| 4527 | #define CAN_ILS_TOOL_SHIFT (18U) | ||
| 4528 | /*! TOOL - Timeout occurred interrupt line. | ||
| 4529 | */ | ||
| 4530 | #define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) | ||
| 4531 | #define CAN_ILS_DRXL_MASK (0x80000U) | ||
| 4532 | #define CAN_ILS_DRXL_SHIFT (19U) | ||
| 4533 | /*! DRXL - Message stored in dedicated Rx buffer interrupt line. | ||
| 4534 | */ | ||
| 4535 | #define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) | ||
| 4536 | #define CAN_ILS_BECL_MASK (0x100000U) | ||
| 4537 | #define CAN_ILS_BECL_SHIFT (20U) | ||
| 4538 | /*! BECL - Bit error corrected interrupt line. | ||
| 4539 | */ | ||
| 4540 | #define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) | ||
| 4541 | #define CAN_ILS_BEUL_MASK (0x200000U) | ||
| 4542 | #define CAN_ILS_BEUL_SHIFT (21U) | ||
| 4543 | /*! BEUL - Bit error uncorrected interrupt line. | ||
| 4544 | */ | ||
| 4545 | #define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) | ||
| 4546 | #define CAN_ILS_ELOL_MASK (0x400000U) | ||
| 4547 | #define CAN_ILS_ELOL_SHIFT (22U) | ||
| 4548 | /*! ELOL - Error logging overflow interrupt line. | ||
| 4549 | */ | ||
| 4550 | #define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) | ||
| 4551 | #define CAN_ILS_EPL_MASK (0x800000U) | ||
| 4552 | #define CAN_ILS_EPL_SHIFT (23U) | ||
| 4553 | /*! EPL - Error passive interrupt line. | ||
| 4554 | */ | ||
| 4555 | #define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) | ||
| 4556 | #define CAN_ILS_EWL_MASK (0x1000000U) | ||
| 4557 | #define CAN_ILS_EWL_SHIFT (24U) | ||
| 4558 | /*! EWL - Warning status interrupt line. | ||
| 4559 | */ | ||
| 4560 | #define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) | ||
| 4561 | #define CAN_ILS_BOL_MASK (0x2000000U) | ||
| 4562 | #define CAN_ILS_BOL_SHIFT (25U) | ||
| 4563 | /*! BOL - Bus_Off Status interrupt line. | ||
| 4564 | */ | ||
| 4565 | #define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) | ||
| 4566 | #define CAN_ILS_WDIL_MASK (0x4000000U) | ||
| 4567 | #define CAN_ILS_WDIL_SHIFT (26U) | ||
| 4568 | /*! WDIL - Watchdog interrupt line. | ||
| 4569 | */ | ||
| 4570 | #define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) | ||
| 4571 | #define CAN_ILS_PEAL_MASK (0x8000000U) | ||
| 4572 | #define CAN_ILS_PEAL_SHIFT (27U) | ||
| 4573 | /*! PEAL - Protocol error in arbitration phase interrupt line. | ||
| 4574 | */ | ||
| 4575 | #define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) | ||
| 4576 | #define CAN_ILS_PEDL_MASK (0x10000000U) | ||
| 4577 | #define CAN_ILS_PEDL_SHIFT (28U) | ||
| 4578 | /*! PEDL - Protocol error in data phase interrupt line. | ||
| 4579 | */ | ||
| 4580 | #define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) | ||
| 4581 | #define CAN_ILS_ARAL_MASK (0x20000000U) | ||
| 4582 | #define CAN_ILS_ARAL_SHIFT (29U) | ||
| 4583 | /*! ARAL - Access to reserved address interrupt line. | ||
| 4584 | */ | ||
| 4585 | #define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) | ||
| 4586 | /*! @} */ | ||
| 4587 | |||
| 4588 | /*! @name ILE - Interrupt Line Enable */ | ||
| 4589 | /*! @{ */ | ||
| 4590 | #define CAN_ILE_EINT0_MASK (0x1U) | ||
| 4591 | #define CAN_ILE_EINT0_SHIFT (0U) | ||
| 4592 | /*! EINT0 - Enable interrupt line 0. | ||
| 4593 | */ | ||
| 4594 | #define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) | ||
| 4595 | #define CAN_ILE_EINT1_MASK (0x2U) | ||
| 4596 | #define CAN_ILE_EINT1_SHIFT (1U) | ||
| 4597 | /*! EINT1 - Enable interrupt line 1. | ||
| 4598 | */ | ||
| 4599 | #define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) | ||
| 4600 | /*! @} */ | ||
| 4601 | |||
| 4602 | /*! @name GFC - Global Filter Configuration */ | ||
| 4603 | /*! @{ */ | ||
| 4604 | #define CAN_GFC_RRFE_MASK (0x1U) | ||
| 4605 | #define CAN_GFC_RRFE_SHIFT (0U) | ||
| 4606 | /*! RRFE - Reject remote frames extended. | ||
| 4607 | */ | ||
| 4608 | #define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) | ||
| 4609 | #define CAN_GFC_RRFS_MASK (0x2U) | ||
| 4610 | #define CAN_GFC_RRFS_SHIFT (1U) | ||
| 4611 | /*! RRFS - Reject remote frames standard. | ||
| 4612 | */ | ||
| 4613 | #define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) | ||
| 4614 | #define CAN_GFC_ANFE_MASK (0xCU) | ||
| 4615 | #define CAN_GFC_ANFE_SHIFT (2U) | ||
| 4616 | /*! ANFE - Accept non-matching frames extended. | ||
| 4617 | */ | ||
| 4618 | #define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) | ||
| 4619 | #define CAN_GFC_ANFS_MASK (0x30U) | ||
| 4620 | #define CAN_GFC_ANFS_SHIFT (4U) | ||
| 4621 | /*! ANFS - Accept non-matching frames standard. | ||
| 4622 | */ | ||
| 4623 | #define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) | ||
| 4624 | /*! @} */ | ||
| 4625 | |||
| 4626 | /*! @name SIDFC - Standard ID Filter Configuration */ | ||
| 4627 | /*! @{ */ | ||
| 4628 | #define CAN_SIDFC_FLSSA_MASK (0xFFFCU) | ||
| 4629 | #define CAN_SIDFC_FLSSA_SHIFT (2U) | ||
| 4630 | /*! FLSSA - Filter list standard start address. | ||
| 4631 | */ | ||
| 4632 | #define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) | ||
| 4633 | #define CAN_SIDFC_LSS_MASK (0xFF0000U) | ||
| 4634 | #define CAN_SIDFC_LSS_SHIFT (16U) | ||
| 4635 | /*! LSS - List size standard 0 = No standard message ID filter. | ||
| 4636 | */ | ||
| 4637 | #define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) | ||
| 4638 | /*! @} */ | ||
| 4639 | |||
| 4640 | /*! @name XIDFC - Extended ID Filter Configuration */ | ||
| 4641 | /*! @{ */ | ||
| 4642 | #define CAN_XIDFC_FLESA_MASK (0xFFFCU) | ||
| 4643 | #define CAN_XIDFC_FLESA_SHIFT (2U) | ||
| 4644 | /*! FLESA - Filter list extended start address. | ||
| 4645 | */ | ||
| 4646 | #define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) | ||
| 4647 | #define CAN_XIDFC_LSE_MASK (0xFF0000U) | ||
| 4648 | #define CAN_XIDFC_LSE_SHIFT (16U) | ||
| 4649 | /*! LSE - List size extended 0 = No extended message ID filter. | ||
| 4650 | */ | ||
| 4651 | #define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) | ||
| 4652 | /*! @} */ | ||
| 4653 | |||
| 4654 | /*! @name XIDAM - Extended ID AND Mask */ | ||
| 4655 | /*! @{ */ | ||
| 4656 | #define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) | ||
| 4657 | #define CAN_XIDAM_EIDM_SHIFT (0U) | ||
| 4658 | /*! EIDM - Extended ID mask. | ||
| 4659 | */ | ||
| 4660 | #define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) | ||
| 4661 | /*! @} */ | ||
| 4662 | |||
| 4663 | /*! @name HPMS - High Priority Message Status */ | ||
| 4664 | /*! @{ */ | ||
| 4665 | #define CAN_HPMS_BIDX_MASK (0x3FU) | ||
| 4666 | #define CAN_HPMS_BIDX_SHIFT (0U) | ||
| 4667 | /*! BIDX - Buffer index. | ||
| 4668 | */ | ||
| 4669 | #define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) | ||
| 4670 | #define CAN_HPMS_MSI_MASK (0xC0U) | ||
| 4671 | #define CAN_HPMS_MSI_SHIFT (6U) | ||
| 4672 | /*! MSI - Message storage indicator. | ||
| 4673 | */ | ||
| 4674 | #define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) | ||
| 4675 | #define CAN_HPMS_FIDX_MASK (0x7F00U) | ||
| 4676 | #define CAN_HPMS_FIDX_SHIFT (8U) | ||
| 4677 | /*! FIDX - Filter index. | ||
| 4678 | */ | ||
| 4679 | #define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) | ||
| 4680 | #define CAN_HPMS_FLST_MASK (0x8000U) | ||
| 4681 | #define CAN_HPMS_FLST_SHIFT (15U) | ||
| 4682 | /*! FLST - Filter list. | ||
| 4683 | */ | ||
| 4684 | #define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) | ||
| 4685 | /*! @} */ | ||
| 4686 | |||
| 4687 | /*! @name NDAT1 - New Data 1 */ | ||
| 4688 | /*! @{ */ | ||
| 4689 | #define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) | ||
| 4690 | #define CAN_NDAT1_ND_SHIFT (0U) | ||
| 4691 | /*! ND - New Data. | ||
| 4692 | */ | ||
| 4693 | #define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) | ||
| 4694 | /*! @} */ | ||
| 4695 | |||
| 4696 | /*! @name NDAT2 - New Data 2 */ | ||
| 4697 | /*! @{ */ | ||
| 4698 | #define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) | ||
| 4699 | #define CAN_NDAT2_ND_SHIFT (0U) | ||
| 4700 | /*! ND - New Data. | ||
| 4701 | */ | ||
| 4702 | #define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) | ||
| 4703 | /*! @} */ | ||
| 4704 | |||
| 4705 | /*! @name RXF0C - Rx FIFO 0 Configuration */ | ||
| 4706 | /*! @{ */ | ||
| 4707 | #define CAN_RXF0C_F0SA_MASK (0xFFFCU) | ||
| 4708 | #define CAN_RXF0C_F0SA_SHIFT (2U) | ||
| 4709 | /*! F0SA - Rx FIFO 0 start address. | ||
| 4710 | */ | ||
| 4711 | #define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) | ||
| 4712 | #define CAN_RXF0C_F0S_MASK (0x7F0000U) | ||
| 4713 | #define CAN_RXF0C_F0S_SHIFT (16U) | ||
| 4714 | /*! F0S - Rx FIFO 0 size. | ||
| 4715 | */ | ||
| 4716 | #define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) | ||
| 4717 | #define CAN_RXF0C_F0WM_MASK (0x7F000000U) | ||
| 4718 | #define CAN_RXF0C_F0WM_SHIFT (24U) | ||
| 4719 | /*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. | ||
| 4720 | */ | ||
| 4721 | #define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) | ||
| 4722 | #define CAN_RXF0C_F0OM_MASK (0x80000000U) | ||
| 4723 | #define CAN_RXF0C_F0OM_SHIFT (31U) | ||
| 4724 | /*! F0OM - FIFO 0 operation mode. | ||
| 4725 | */ | ||
| 4726 | #define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) | ||
| 4727 | /*! @} */ | ||
| 4728 | |||
| 4729 | /*! @name RXF0S - Rx FIFO 0 Status */ | ||
| 4730 | /*! @{ */ | ||
| 4731 | #define CAN_RXF0S_F0FL_MASK (0x7FU) | ||
| 4732 | #define CAN_RXF0S_F0FL_SHIFT (0U) | ||
| 4733 | /*! F0FL - Rx FIFO 0 fill level. | ||
| 4734 | */ | ||
| 4735 | #define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) | ||
| 4736 | #define CAN_RXF0S_F0GI_MASK (0x3F00U) | ||
| 4737 | #define CAN_RXF0S_F0GI_SHIFT (8U) | ||
| 4738 | /*! F0GI - Rx FIFO 0 get index. | ||
| 4739 | */ | ||
| 4740 | #define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) | ||
| 4741 | #define CAN_RXF0S_F0PI_MASK (0x3F0000U) | ||
| 4742 | #define CAN_RXF0S_F0PI_SHIFT (16U) | ||
| 4743 | /*! F0PI - Rx FIFO 0 put index. | ||
| 4744 | */ | ||
| 4745 | #define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) | ||
| 4746 | #define CAN_RXF0S_F0F_MASK (0x1000000U) | ||
| 4747 | #define CAN_RXF0S_F0F_SHIFT (24U) | ||
| 4748 | /*! F0F - Rx FIFO 0 full. | ||
| 4749 | */ | ||
| 4750 | #define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) | ||
| 4751 | #define CAN_RXF0S_RF0L_MASK (0x2000000U) | ||
| 4752 | #define CAN_RXF0S_RF0L_SHIFT (25U) | ||
| 4753 | /*! RF0L - Rx FIFO 0 message lost. | ||
| 4754 | */ | ||
| 4755 | #define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) | ||
| 4756 | /*! @} */ | ||
| 4757 | |||
| 4758 | /*! @name RXF0A - Rx FIFO 0 Acknowledge */ | ||
| 4759 | /*! @{ */ | ||
| 4760 | #define CAN_RXF0A_F0AI_MASK (0x3FU) | ||
| 4761 | #define CAN_RXF0A_F0AI_SHIFT (0U) | ||
| 4762 | /*! F0AI - Rx FIFO 0 acknowledge index. | ||
| 4763 | */ | ||
| 4764 | #define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) | ||
| 4765 | /*! @} */ | ||
| 4766 | |||
| 4767 | /*! @name RXBC - Rx Buffer Configuration */ | ||
| 4768 | /*! @{ */ | ||
| 4769 | #define CAN_RXBC_RBSA_MASK (0xFFFCU) | ||
| 4770 | #define CAN_RXBC_RBSA_SHIFT (2U) | ||
| 4771 | /*! RBSA - Rx buffer start address. | ||
| 4772 | */ | ||
| 4773 | #define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) | ||
| 4774 | /*! @} */ | ||
| 4775 | |||
| 4776 | /*! @name RXF1C - Rx FIFO 1 Configuration */ | ||
| 4777 | /*! @{ */ | ||
| 4778 | #define CAN_RXF1C_F1SA_MASK (0xFFFCU) | ||
| 4779 | #define CAN_RXF1C_F1SA_SHIFT (2U) | ||
| 4780 | /*! F1SA - Rx FIFO 1 start address. | ||
| 4781 | */ | ||
| 4782 | #define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) | ||
| 4783 | #define CAN_RXF1C_F1S_MASK (0x7F0000U) | ||
| 4784 | #define CAN_RXF1C_F1S_SHIFT (16U) | ||
| 4785 | /*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. | ||
| 4786 | */ | ||
| 4787 | #define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) | ||
| 4788 | #define CAN_RXF1C_F1WM_MASK (0x7F000000U) | ||
| 4789 | #define CAN_RXF1C_F1WM_SHIFT (24U) | ||
| 4790 | /*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. | ||
| 4791 | */ | ||
| 4792 | #define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) | ||
| 4793 | #define CAN_RXF1C_F1OM_MASK (0x80000000U) | ||
| 4794 | #define CAN_RXF1C_F1OM_SHIFT (31U) | ||
| 4795 | /*! F1OM - FIFO 1 operation mode. | ||
| 4796 | */ | ||
| 4797 | #define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) | ||
| 4798 | /*! @} */ | ||
| 4799 | |||
| 4800 | /*! @name RXF1S - Rx FIFO 1 Status */ | ||
| 4801 | /*! @{ */ | ||
| 4802 | #define CAN_RXF1S_F1FL_MASK (0x7FU) | ||
| 4803 | #define CAN_RXF1S_F1FL_SHIFT (0U) | ||
| 4804 | /*! F1FL - Rx FIFO 1 fill level. | ||
| 4805 | */ | ||
| 4806 | #define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) | ||
| 4807 | #define CAN_RXF1S_F1GI_MASK (0x3F00U) | ||
| 4808 | #define CAN_RXF1S_F1GI_SHIFT (8U) | ||
| 4809 | /*! F1GI - Rx FIFO 1 get index. | ||
| 4810 | */ | ||
| 4811 | #define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) | ||
| 4812 | #define CAN_RXF1S_F1PI_MASK (0x3F0000U) | ||
| 4813 | #define CAN_RXF1S_F1PI_SHIFT (16U) | ||
| 4814 | /*! F1PI - Rx FIFO 1 put index. | ||
| 4815 | */ | ||
| 4816 | #define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) | ||
| 4817 | #define CAN_RXF1S_F1F_MASK (0x1000000U) | ||
| 4818 | #define CAN_RXF1S_F1F_SHIFT (24U) | ||
| 4819 | /*! F1F - Rx FIFO 1 full. | ||
| 4820 | */ | ||
| 4821 | #define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) | ||
| 4822 | #define CAN_RXF1S_RF1L_MASK (0x2000000U) | ||
| 4823 | #define CAN_RXF1S_RF1L_SHIFT (25U) | ||
| 4824 | /*! RF1L - Rx FIFO 1 message lost. | ||
| 4825 | */ | ||
| 4826 | #define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) | ||
| 4827 | /*! @} */ | ||
| 4828 | |||
| 4829 | /*! @name RXF1A - Rx FIFO 1 Acknowledge */ | ||
| 4830 | /*! @{ */ | ||
| 4831 | #define CAN_RXF1A_F1AI_MASK (0x3FU) | ||
| 4832 | #define CAN_RXF1A_F1AI_SHIFT (0U) | ||
| 4833 | /*! F1AI - Rx FIFO 1 acknowledge index. | ||
| 4834 | */ | ||
| 4835 | #define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) | ||
| 4836 | /*! @} */ | ||
| 4837 | |||
| 4838 | /*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ | ||
| 4839 | /*! @{ */ | ||
| 4840 | #define CAN_RXESC_F0DS_MASK (0x7U) | ||
| 4841 | #define CAN_RXESC_F0DS_SHIFT (0U) | ||
| 4842 | /*! F0DS - Rx FIFO 0 data field size. | ||
| 4843 | */ | ||
| 4844 | #define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) | ||
| 4845 | #define CAN_RXESC_F1DS_MASK (0x70U) | ||
| 4846 | #define CAN_RXESC_F1DS_SHIFT (4U) | ||
| 4847 | /*! F1DS - Rx FIFO 1 data field size. | ||
| 4848 | */ | ||
| 4849 | #define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) | ||
| 4850 | #define CAN_RXESC_RBDS_MASK (0x700U) | ||
| 4851 | #define CAN_RXESC_RBDS_SHIFT (8U) | ||
| 4852 | /*! RBDS - . | ||
| 4853 | */ | ||
| 4854 | #define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) | ||
| 4855 | /*! @} */ | ||
| 4856 | |||
| 4857 | /*! @name TXBC - Tx Buffer Configuration */ | ||
| 4858 | /*! @{ */ | ||
| 4859 | #define CAN_TXBC_TBSA_MASK (0xFFFCU) | ||
| 4860 | #define CAN_TXBC_TBSA_SHIFT (2U) | ||
| 4861 | /*! TBSA - Tx buffers start address. | ||
| 4862 | */ | ||
| 4863 | #define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) | ||
| 4864 | #define CAN_TXBC_NDTB_MASK (0x3F0000U) | ||
| 4865 | #define CAN_TXBC_NDTB_SHIFT (16U) | ||
| 4866 | /*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. | ||
| 4867 | */ | ||
| 4868 | #define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) | ||
| 4869 | #define CAN_TXBC_TFQS_MASK (0x3F000000U) | ||
| 4870 | #define CAN_TXBC_TFQS_SHIFT (24U) | ||
| 4871 | /*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. | ||
| 4872 | */ | ||
| 4873 | #define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) | ||
| 4874 | #define CAN_TXBC_TFQM_MASK (0x40000000U) | ||
| 4875 | #define CAN_TXBC_TFQM_SHIFT (30U) | ||
| 4876 | /*! TFQM - Tx FIFO/queue mode. | ||
| 4877 | */ | ||
| 4878 | #define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) | ||
| 4879 | /*! @} */ | ||
| 4880 | |||
| 4881 | /*! @name TXFQS - Tx FIFO/Queue Status */ | ||
| 4882 | /*! @{ */ | ||
| 4883 | #define CAN_TXFQS_TFGI_MASK (0x1F00U) | ||
| 4884 | #define CAN_TXFQS_TFGI_SHIFT (8U) | ||
| 4885 | /*! TFGI - Tx FIFO get index. | ||
| 4886 | */ | ||
| 4887 | #define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) | ||
| 4888 | #define CAN_TXFQS_TFQPI_MASK (0x1F0000U) | ||
| 4889 | #define CAN_TXFQS_TFQPI_SHIFT (16U) | ||
| 4890 | /*! TFQPI - Tx FIFO/queue put index. | ||
| 4891 | */ | ||
| 4892 | #define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) | ||
| 4893 | #define CAN_TXFQS_TFQF_MASK (0x200000U) | ||
| 4894 | #define CAN_TXFQS_TFQF_SHIFT (21U) | ||
| 4895 | /*! TFQF - Tx FIFO/queue full. | ||
| 4896 | */ | ||
| 4897 | #define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) | ||
| 4898 | /*! @} */ | ||
| 4899 | |||
| 4900 | /*! @name TXESC - Tx Buffer Element Size Configuration */ | ||
| 4901 | /*! @{ */ | ||
| 4902 | #define CAN_TXESC_TBDS_MASK (0x7U) | ||
| 4903 | #define CAN_TXESC_TBDS_SHIFT (0U) | ||
| 4904 | /*! TBDS - Tx buffer data field size. | ||
| 4905 | */ | ||
| 4906 | #define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) | ||
| 4907 | /*! @} */ | ||
| 4908 | |||
| 4909 | /*! @name TXBRP - Tx Buffer Request Pending */ | ||
| 4910 | /*! @{ */ | ||
| 4911 | #define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) | ||
| 4912 | #define CAN_TXBRP_TRP_SHIFT (0U) | ||
| 4913 | /*! TRP - Transmission request pending. | ||
| 4914 | */ | ||
| 4915 | #define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) | ||
| 4916 | /*! @} */ | ||
| 4917 | |||
| 4918 | /*! @name TXBAR - Tx Buffer Add Request */ | ||
| 4919 | /*! @{ */ | ||
| 4920 | #define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) | ||
| 4921 | #define CAN_TXBAR_AR_SHIFT (0U) | ||
| 4922 | /*! AR - Add request. | ||
| 4923 | */ | ||
| 4924 | #define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) | ||
| 4925 | /*! @} */ | ||
| 4926 | |||
| 4927 | /*! @name TXBCR - Tx Buffer Cancellation Request */ | ||
| 4928 | /*! @{ */ | ||
| 4929 | #define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) | ||
| 4930 | #define CAN_TXBCR_CR_SHIFT (0U) | ||
| 4931 | /*! CR - Cancellation request. | ||
| 4932 | */ | ||
| 4933 | #define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) | ||
| 4934 | /*! @} */ | ||
| 4935 | |||
| 4936 | /*! @name TXBTO - Tx Buffer Transmission Occurred */ | ||
| 4937 | /*! @{ */ | ||
| 4938 | #define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) | ||
| 4939 | #define CAN_TXBTO_TO_SHIFT (0U) | ||
| 4940 | /*! TO - Transmission occurred. | ||
| 4941 | */ | ||
| 4942 | #define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) | ||
| 4943 | /*! @} */ | ||
| 4944 | |||
| 4945 | /*! @name TXBCF - Tx Buffer Cancellation Finished */ | ||
| 4946 | /*! @{ */ | ||
| 4947 | #define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) | ||
| 4948 | #define CAN_TXBCF_TO_SHIFT (0U) | ||
| 4949 | /*! TO - Cancellation finished. | ||
| 4950 | */ | ||
| 4951 | #define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) | ||
| 4952 | /*! @} */ | ||
| 4953 | |||
| 4954 | /*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ | ||
| 4955 | /*! @{ */ | ||
| 4956 | #define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) | ||
| 4957 | #define CAN_TXBTIE_TIE_SHIFT (0U) | ||
| 4958 | /*! TIE - Transmission interrupt enable. | ||
| 4959 | */ | ||
| 4960 | #define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) | ||
| 4961 | /*! @} */ | ||
| 4962 | |||
| 4963 | /*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ | ||
| 4964 | /*! @{ */ | ||
| 4965 | #define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) | ||
| 4966 | #define CAN_TXBCIE_CFIE_SHIFT (0U) | ||
| 4967 | /*! CFIE - Cancellation finished interrupt enable. | ||
| 4968 | */ | ||
| 4969 | #define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) | ||
| 4970 | /*! @} */ | ||
| 4971 | |||
| 4972 | /*! @name TXEFC - Tx Event FIFO Configuration */ | ||
| 4973 | /*! @{ */ | ||
| 4974 | #define CAN_TXEFC_EFSA_MASK (0xFFFCU) | ||
| 4975 | #define CAN_TXEFC_EFSA_SHIFT (2U) | ||
| 4976 | /*! EFSA - Event FIFO start address. | ||
| 4977 | */ | ||
| 4978 | #define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) | ||
| 4979 | #define CAN_TXEFC_EFS_MASK (0x3F0000U) | ||
| 4980 | #define CAN_TXEFC_EFS_SHIFT (16U) | ||
| 4981 | /*! EFS - Event FIFO size 0 = Tx event FIFO disabled. | ||
| 4982 | */ | ||
| 4983 | #define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) | ||
| 4984 | #define CAN_TXEFC_EFWM_MASK (0x3F000000U) | ||
| 4985 | #define CAN_TXEFC_EFWM_SHIFT (24U) | ||
| 4986 | /*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. | ||
| 4987 | */ | ||
| 4988 | #define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) | ||
| 4989 | /*! @} */ | ||
| 4990 | |||
| 4991 | /*! @name TXEFS - Tx Event FIFO Status */ | ||
| 4992 | /*! @{ */ | ||
| 4993 | #define CAN_TXEFS_EFFL_MASK (0x3FU) | ||
| 4994 | #define CAN_TXEFS_EFFL_SHIFT (0U) | ||
| 4995 | /*! EFFL - Event FIFO fill level. | ||
| 4996 | */ | ||
| 4997 | #define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) | ||
| 4998 | #define CAN_TXEFS_EFGI_MASK (0x1F00U) | ||
| 4999 | #define CAN_TXEFS_EFGI_SHIFT (8U) | ||
| 5000 | /*! EFGI - Event FIFO get index. | ||
| 5001 | */ | ||
| 5002 | #define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) | ||
| 5003 | #define CAN_TXEFS_EFPI_MASK (0x3F0000U) | ||
| 5004 | #define CAN_TXEFS_EFPI_SHIFT (16U) | ||
| 5005 | /*! EFPI - Event FIFO put index. | ||
| 5006 | */ | ||
| 5007 | #define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) | ||
| 5008 | #define CAN_TXEFS_EFF_MASK (0x1000000U) | ||
| 5009 | #define CAN_TXEFS_EFF_SHIFT (24U) | ||
| 5010 | /*! EFF - Event FIFO full. | ||
| 5011 | */ | ||
| 5012 | #define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) | ||
| 5013 | #define CAN_TXEFS_TEFL_MASK (0x2000000U) | ||
| 5014 | #define CAN_TXEFS_TEFL_SHIFT (25U) | ||
| 5015 | /*! TEFL - Tx event FIFO element lost. | ||
| 5016 | */ | ||
| 5017 | #define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) | ||
| 5018 | /*! @} */ | ||
| 5019 | |||
| 5020 | /*! @name TXEFA - Tx Event FIFO Acknowledge */ | ||
| 5021 | /*! @{ */ | ||
| 5022 | #define CAN_TXEFA_EFAI_MASK (0x1FU) | ||
| 5023 | #define CAN_TXEFA_EFAI_SHIFT (0U) | ||
| 5024 | /*! EFAI - Event FIFO acknowledge index. | ||
| 5025 | */ | ||
| 5026 | #define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) | ||
| 5027 | /*! @} */ | ||
| 5028 | |||
| 5029 | /*! @name MRBA - CAN Message RAM Base Address */ | ||
| 5030 | /*! @{ */ | ||
| 5031 | #define CAN_MRBA_BA_MASK (0xFFFF0000U) | ||
| 5032 | #define CAN_MRBA_BA_SHIFT (16U) | ||
| 5033 | /*! BA - Base address for the message RAM in the chip memory map. | ||
| 5034 | */ | ||
| 5035 | #define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) | ||
| 5036 | /*! @} */ | ||
| 5037 | |||
| 5038 | /*! @name ETSCC - External Timestamp Counter Configuration */ | ||
| 5039 | /*! @{ */ | ||
| 5040 | #define CAN_ETSCC_ETCP_MASK (0x7FFU) | ||
| 5041 | #define CAN_ETSCC_ETCP_SHIFT (0U) | ||
| 5042 | /*! ETCP - External timestamp prescaler value. | ||
| 5043 | */ | ||
| 5044 | #define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) | ||
| 5045 | #define CAN_ETSCC_ETCE_MASK (0x80000000U) | ||
| 5046 | #define CAN_ETSCC_ETCE_SHIFT (31U) | ||
| 5047 | /*! ETCE - External timestamp counter enable. | ||
| 5048 | */ | ||
| 5049 | #define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) | ||
| 5050 | /*! @} */ | ||
| 5051 | |||
| 5052 | /*! @name ETSCV - External Timestamp Counter Value */ | ||
| 5053 | /*! @{ */ | ||
| 5054 | #define CAN_ETSCV_ETSC_MASK (0xFFFFU) | ||
| 5055 | #define CAN_ETSCV_ETSC_SHIFT (0U) | ||
| 5056 | /*! ETSC - External timestamp counter. | ||
| 5057 | */ | ||
| 5058 | #define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) | ||
| 5059 | /*! @} */ | ||
| 5060 | |||
| 5061 | |||
| 5062 | /*! | ||
| 5063 | * @} | ||
| 5064 | */ /* end of group CAN_Register_Masks */ | ||
| 5065 | |||
| 5066 | |||
| 5067 | /* CAN - Peripheral instance base addresses */ | ||
| 5068 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5069 | /** Peripheral CAN0 base address */ | ||
| 5070 | #define CAN0_BASE (0x5009D000u) | ||
| 5071 | /** Peripheral CAN0 base address */ | ||
| 5072 | #define CAN0_BASE_NS (0x4009D000u) | ||
| 5073 | /** Peripheral CAN0 base pointer */ | ||
| 5074 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 5075 | /** Peripheral CAN0 base pointer */ | ||
| 5076 | #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) | ||
| 5077 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5078 | #define CAN_BASE_ADDRS { CAN0_BASE } | ||
| 5079 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5080 | #define CAN_BASE_PTRS { CAN0 } | ||
| 5081 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5082 | #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } | ||
| 5083 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5084 | #define CAN_BASE_PTRS_NS { CAN0_NS } | ||
| 5085 | #else | ||
| 5086 | /** Peripheral CAN0 base address */ | ||
| 5087 | #define CAN0_BASE (0x4009D000u) | ||
| 5088 | /** Peripheral CAN0 base pointer */ | ||
| 5089 | #define CAN0 ((CAN_Type *)CAN0_BASE) | ||
| 5090 | /** Array initializer of CAN peripheral base addresses */ | ||
| 5091 | #define CAN_BASE_ADDRS { CAN0_BASE } | ||
| 5092 | /** Array initializer of CAN peripheral base pointers */ | ||
| 5093 | #define CAN_BASE_PTRS { CAN0 } | ||
| 5094 | #endif | ||
| 5095 | /** Interrupt vectors for the CAN peripheral type */ | ||
| 5096 | #define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } | ||
| 5097 | |||
| 5098 | /*! | ||
| 5099 | * @} | ||
| 5100 | */ /* end of group CAN_Peripheral_Access_Layer */ | ||
| 5101 | |||
| 5102 | |||
| 5103 | /* ---------------------------------------------------------------------------- | ||
| 5104 | -- CASPER Peripheral Access Layer | ||
| 5105 | ---------------------------------------------------------------------------- */ | ||
| 5106 | |||
| 5107 | /*! | ||
| 5108 | * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer | ||
| 5109 | * @{ | ||
| 5110 | */ | ||
| 5111 | |||
| 5112 | /** CASPER - Register Layout Typedef */ | ||
| 5113 | typedef struct { | ||
| 5114 | __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ | ||
| 5115 | __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ | ||
| 5116 | __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ | ||
| 5117 | __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ | ||
| 5118 | __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ | ||
| 5119 | __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ | ||
| 5120 | __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ | ||
| 5121 | uint8_t RESERVED_0[4]; | ||
| 5122 | __IO uint32_t AREG; /**< A register, offset: 0x20 */ | ||
| 5123 | __IO uint32_t BREG; /**< B register, offset: 0x24 */ | ||
| 5124 | __IO uint32_t CREG; /**< C register, offset: 0x28 */ | ||
| 5125 | __IO uint32_t DREG; /**< D register, offset: 0x2C */ | ||
| 5126 | __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ | ||
| 5127 | __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ | ||
| 5128 | __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ | ||
| 5129 | __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ | ||
| 5130 | uint8_t RESERVED_1[32]; | ||
| 5131 | __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ | ||
| 5132 | __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ | ||
| 5133 | uint8_t RESERVED_2[24]; | ||
| 5134 | __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ | ||
| 5135 | } CASPER_Type; | ||
| 5136 | |||
| 5137 | /* ---------------------------------------------------------------------------- | ||
| 5138 | -- CASPER Register Masks | ||
| 5139 | ---------------------------------------------------------------------------- */ | ||
| 5140 | |||
| 5141 | /*! | ||
| 5142 | * @addtogroup CASPER_Register_Masks CASPER Register Masks | ||
| 5143 | * @{ | ||
| 5144 | */ | ||
| 5145 | |||
| 5146 | /*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ | ||
| 5147 | /*! @{ */ | ||
| 5148 | #define CASPER_CTRL0_ABBPAIR_MASK (0x1U) | ||
| 5149 | #define CASPER_CTRL0_ABBPAIR_SHIFT (0U) | ||
| 5150 | /*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up | ||
| 5151 | * 0b0..Bank-pair 0 (1st) | ||
| 5152 | * 0b1..Bank-pair 1 (2nd) | ||
| 5153 | */ | ||
| 5154 | #define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) | ||
| 5155 | #define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) | ||
| 5156 | #define CASPER_CTRL0_ABOFF_SHIFT (2U) | ||
| 5157 | /*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code | ||
| 5158 | * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed | ||
| 5159 | * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up | ||
| 5160 | */ | ||
| 5161 | #define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) | ||
| 5162 | #define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) | ||
| 5163 | #define CASPER_CTRL0_CDBPAIR_SHIFT (16U) | ||
| 5164 | /*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up | ||
| 5165 | * 0b0..Bank-pair 0 (1st) | ||
| 5166 | * 0b1..Bank-pair 1 (2nd) | ||
| 5167 | */ | ||
| 5168 | #define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) | ||
| 5169 | #define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) | ||
| 5170 | #define CASPER_CTRL0_CDOFF_SHIFT (18U) | ||
| 5171 | /*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees | ||
| 5172 | * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 | ||
| 5173 | * bit operation. Ideally not in the same RAM as the AB values | ||
| 5174 | */ | ||
| 5175 | #define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) | ||
| 5176 | /*! @} */ | ||
| 5177 | |||
| 5178 | /*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ | ||
| 5179 | /*! @{ */ | ||
| 5180 | #define CASPER_CTRL1_ITER_MASK (0xFFU) | ||
| 5181 | #define CASPER_CTRL1_ITER_SHIFT (0U) | ||
| 5182 | /*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. | ||
| 5183 | */ | ||
| 5184 | #define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) | ||
| 5185 | #define CASPER_CTRL1_MODE_MASK (0xFF00U) | ||
| 5186 | #define CASPER_CTRL1_MODE_SHIFT (8U) | ||
| 5187 | /*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. | ||
| 5188 | */ | ||
| 5189 | #define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) | ||
| 5190 | #define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) | ||
| 5191 | #define CASPER_CTRL1_RESBPAIR_SHIFT (16U) | ||
| 5192 | /*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally | ||
| 5193 | * this is not the same bank as ABBPAIR (when 4-up supported) | ||
| 5194 | * 0b0..Bank-pair 0 (1st) | ||
| 5195 | * 0b1..Bank-pair 1 (2nd) | ||
| 5196 | */ | ||
| 5197 | #define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) | ||
| 5198 | #define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) | ||
| 5199 | #define CASPER_CTRL1_RESOFF_SHIFT (18U) | ||
| 5200 | /*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally | ||
| 5201 | * not in the same RAM as the AB and CD values | ||
| 5202 | */ | ||
| 5203 | #define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) | ||
| 5204 | #define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) | ||
| 5205 | #define CASPER_CTRL1_CSKIP_SHIFT (30U) | ||
| 5206 | /*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: | ||
| 5207 | * 0b00..No Skip | ||
| 5208 | * 0b01..Skip if Carry is 1 | ||
| 5209 | * 0b10..Skip if Carry is 0 | ||
| 5210 | * 0b11..Set CTRLOFF to CDOFF and Skip | ||
| 5211 | */ | ||
| 5212 | #define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) | ||
| 5213 | /*! @} */ | ||
| 5214 | |||
| 5215 | /*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ | ||
| 5216 | /*! @{ */ | ||
| 5217 | #define CASPER_LOADER_COUNT_MASK (0xFFU) | ||
| 5218 | #define CASPER_LOADER_COUNT_SHIFT (0U) | ||
| 5219 | /*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one | ||
| 5220 | * op - does not iterate, write N means N control pairs to load | ||
| 5221 | */ | ||
| 5222 | #define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) | ||
| 5223 | #define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) | ||
| 5224 | #define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) | ||
| 5225 | /*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not | ||
| 5226 | * matter which bank is used as this is loaded when not performing an operation. | ||
| 5227 | * 0b0..Bank-pair 0 (1st) | ||
| 5228 | * 0b1..Bank-pair 1 (2nd) | ||
| 5229 | */ | ||
| 5230 | #define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) | ||
| 5231 | #define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) | ||
| 5232 | #define CASPER_LOADER_CTRLOFF_SHIFT (18U) | ||
| 5233 | /*! CTRLOFF - DWord Offset of CTRL pair to load next. | ||
| 5234 | */ | ||
| 5235 | #define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) | ||
| 5236 | /*! @} */ | ||
| 5237 | |||
| 5238 | /*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ | ||
| 5239 | /*! @{ */ | ||
| 5240 | #define CASPER_STATUS_DONE_MASK (0x1U) | ||
| 5241 | #define CASPER_STATUS_DONE_SHIFT (0U) | ||
| 5242 | /*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. | ||
| 5243 | * 0b0..Busy or just cleared | ||
| 5244 | * 0b1..Completed last operation | ||
| 5245 | */ | ||
| 5246 | #define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) | ||
| 5247 | #define CASPER_STATUS_CARRY_MASK (0x10U) | ||
| 5248 | #define CASPER_STATUS_CARRY_SHIFT (4U) | ||
| 5249 | /*! CARRY - Last carry value if operation produced a carry bit | ||
| 5250 | * 0b0..Carry was 0 or no carry | ||
| 5251 | * 0b1..Carry was 1 | ||
| 5252 | */ | ||
| 5253 | #define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) | ||
| 5254 | #define CASPER_STATUS_BUSY_MASK (0x20U) | ||
| 5255 | #define CASPER_STATUS_BUSY_SHIFT (5U) | ||
| 5256 | /*! BUSY - Indicates if the accelerator is busy performing an operation | ||
| 5257 | * 0b0..Not busy - is idle | ||
| 5258 | * 0b1..Is busy | ||
| 5259 | */ | ||
| 5260 | #define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) | ||
| 5261 | /*! @} */ | ||
| 5262 | |||
| 5263 | /*! @name INTENSET - Sets interrupts */ | ||
| 5264 | /*! @{ */ | ||
| 5265 | #define CASPER_INTENSET_DONE_MASK (0x1U) | ||
| 5266 | #define CASPER_INTENSET_DONE_SHIFT (0U) | ||
| 5267 | /*! DONE - Set if the accelerator should interrupt when done. | ||
| 5268 | * 0b0..Do not interrupt when done | ||
| 5269 | * 0b1..Interrupt when done | ||
| 5270 | */ | ||
| 5271 | #define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) | ||
| 5272 | /*! @} */ | ||
| 5273 | |||
| 5274 | /*! @name INTENCLR - Clears interrupts */ | ||
| 5275 | /*! @{ */ | ||
| 5276 | #define CASPER_INTENCLR_DONE_MASK (0x1U) | ||
| 5277 | #define CASPER_INTENCLR_DONE_SHIFT (0U) | ||
| 5278 | /*! DONE - Written to clear an interrupt set with INTENSET. | ||
| 5279 | * 0b0..If written 0, ignored | ||
| 5280 | * 0b1..If written 1, do not Interrupt when done | ||
| 5281 | */ | ||
| 5282 | #define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) | ||
| 5283 | /*! @} */ | ||
| 5284 | |||
| 5285 | /*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ | ||
| 5286 | /*! @{ */ | ||
| 5287 | #define CASPER_INTSTAT_DONE_MASK (0x1U) | ||
| 5288 | #define CASPER_INTSTAT_DONE_SHIFT (0U) | ||
| 5289 | /*! DONE - If set, interrupt is caused by accelerator being done. | ||
| 5290 | * 0b0..Not caused by accelerator being done | ||
| 5291 | * 0b1..Caused by accelerator being done | ||
| 5292 | */ | ||
| 5293 | #define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) | ||
| 5294 | /*! @} */ | ||
| 5295 | |||
| 5296 | /*! @name AREG - A register */ | ||
| 5297 | /*! @{ */ | ||
| 5298 | #define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5299 | #define CASPER_AREG_REG_VALUE_SHIFT (0U) | ||
| 5300 | /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, | ||
| 5301 | * but is available when accelerator not busy. | ||
| 5302 | */ | ||
| 5303 | #define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) | ||
| 5304 | /*! @} */ | ||
| 5305 | |||
| 5306 | /*! @name BREG - B register */ | ||
| 5307 | /*! @{ */ | ||
| 5308 | #define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5309 | #define CASPER_BREG_REG_VALUE_SHIFT (0U) | ||
| 5310 | /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, | ||
| 5311 | * but is available when accelerator not busy. | ||
| 5312 | */ | ||
| 5313 | #define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) | ||
| 5314 | /*! @} */ | ||
| 5315 | |||
| 5316 | /*! @name CREG - C register */ | ||
| 5317 | /*! @{ */ | ||
| 5318 | #define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5319 | #define CASPER_CREG_REG_VALUE_SHIFT (0U) | ||
| 5320 | /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, | ||
| 5321 | * but is available when accelerator not busy. | ||
| 5322 | */ | ||
| 5323 | #define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) | ||
| 5324 | /*! @} */ | ||
| 5325 | |||
| 5326 | /*! @name DREG - D register */ | ||
| 5327 | /*! @{ */ | ||
| 5328 | #define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5329 | #define CASPER_DREG_REG_VALUE_SHIFT (0U) | ||
| 5330 | /*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, | ||
| 5331 | * but is available when accelerator not busy. | ||
| 5332 | */ | ||
| 5333 | #define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) | ||
| 5334 | /*! @} */ | ||
| 5335 | |||
| 5336 | /*! @name RES0 - Result register 0 */ | ||
| 5337 | /*! @{ */ | ||
| 5338 | #define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5339 | #define CASPER_RES0_REG_VALUE_SHIFT (0U) | ||
| 5340 | /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally | ||
| 5341 | * written or read by application, but is available when accelerator not busy. | ||
| 5342 | */ | ||
| 5343 | #define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) | ||
| 5344 | /*! @} */ | ||
| 5345 | |||
| 5346 | /*! @name RES1 - Result register 1 */ | ||
| 5347 | /*! @{ */ | ||
| 5348 | #define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5349 | #define CASPER_RES1_REG_VALUE_SHIFT (0U) | ||
| 5350 | /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally | ||
| 5351 | * written or read by application, but is available when accelerator not busy. | ||
| 5352 | */ | ||
| 5353 | #define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) | ||
| 5354 | /*! @} */ | ||
| 5355 | |||
| 5356 | /*! @name RES2 - Result register 2 */ | ||
| 5357 | /*! @{ */ | ||
| 5358 | #define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5359 | #define CASPER_RES2_REG_VALUE_SHIFT (0U) | ||
| 5360 | /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally | ||
| 5361 | * written or read by application, but is available when accelerator not busy. | ||
| 5362 | */ | ||
| 5363 | #define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) | ||
| 5364 | /*! @} */ | ||
| 5365 | |||
| 5366 | /*! @name RES3 - Result register 3 */ | ||
| 5367 | /*! @{ */ | ||
| 5368 | #define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) | ||
| 5369 | #define CASPER_RES3_REG_VALUE_SHIFT (0U) | ||
| 5370 | /*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally | ||
| 5371 | * written or read by application, but is available when accelerator not busy. | ||
| 5372 | */ | ||
| 5373 | #define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) | ||
| 5374 | /*! @} */ | ||
| 5375 | |||
| 5376 | /*! @name MASK - Optional mask register */ | ||
| 5377 | /*! @{ */ | ||
| 5378 | #define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) | ||
| 5379 | #define CASPER_MASK_MASK_SHIFT (0U) | ||
| 5380 | /*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values | ||
| 5381 | */ | ||
| 5382 | #define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) | ||
| 5383 | /*! @} */ | ||
| 5384 | |||
| 5385 | /*! @name REMASK - Optional re-mask register */ | ||
| 5386 | /*! @{ */ | ||
| 5387 | #define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) | ||
| 5388 | #define CASPER_REMASK_MASK_SHIFT (0U) | ||
| 5389 | /*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values | ||
| 5390 | */ | ||
| 5391 | #define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) | ||
| 5392 | /*! @} */ | ||
| 5393 | |||
| 5394 | /*! @name LOCK - Security lock register */ | ||
| 5395 | /*! @{ */ | ||
| 5396 | #define CASPER_LOCK_LOCK_MASK (0x1U) | ||
| 5397 | #define CASPER_LOCK_LOCK_SHIFT (0U) | ||
| 5398 | /*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. | ||
| 5399 | * 0b0..unlock | ||
| 5400 | * 0b1..Lock to current security level | ||
| 5401 | */ | ||
| 5402 | #define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) | ||
| 5403 | #define CASPER_LOCK_KEY_MASK (0x1FFF0U) | ||
| 5404 | #define CASPER_LOCK_KEY_SHIFT (4U) | ||
| 5405 | /*! KEY - Must be written as 0x73D to change the register. | ||
| 5406 | * 0b0011100111101..If set during write, will allow lock or unlock | ||
| 5407 | */ | ||
| 5408 | #define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) | ||
| 5409 | /*! @} */ | ||
| 5410 | |||
| 5411 | |||
| 5412 | /*! | ||
| 5413 | * @} | ||
| 5414 | */ /* end of group CASPER_Register_Masks */ | ||
| 5415 | |||
| 5416 | |||
| 5417 | /* CASPER - Peripheral instance base addresses */ | ||
| 5418 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5419 | /** Peripheral CASPER base address */ | ||
| 5420 | #define CASPER_BASE (0x500A5000u) | ||
| 5421 | /** Peripheral CASPER base address */ | ||
| 5422 | #define CASPER_BASE_NS (0x400A5000u) | ||
| 5423 | /** Peripheral CASPER base pointer */ | ||
| 5424 | #define CASPER ((CASPER_Type *)CASPER_BASE) | ||
| 5425 | /** Peripheral CASPER base pointer */ | ||
| 5426 | #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) | ||
| 5427 | /** Array initializer of CASPER peripheral base addresses */ | ||
| 5428 | #define CASPER_BASE_ADDRS { CASPER_BASE } | ||
| 5429 | /** Array initializer of CASPER peripheral base pointers */ | ||
| 5430 | #define CASPER_BASE_PTRS { CASPER } | ||
| 5431 | /** Array initializer of CASPER peripheral base addresses */ | ||
| 5432 | #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } | ||
| 5433 | /** Array initializer of CASPER peripheral base pointers */ | ||
| 5434 | #define CASPER_BASE_PTRS_NS { CASPER_NS } | ||
| 5435 | #else | ||
| 5436 | /** Peripheral CASPER base address */ | ||
| 5437 | #define CASPER_BASE (0x400A5000u) | ||
| 5438 | /** Peripheral CASPER base pointer */ | ||
| 5439 | #define CASPER ((CASPER_Type *)CASPER_BASE) | ||
| 5440 | /** Array initializer of CASPER peripheral base addresses */ | ||
| 5441 | #define CASPER_BASE_ADDRS { CASPER_BASE } | ||
| 5442 | /** Array initializer of CASPER peripheral base pointers */ | ||
| 5443 | #define CASPER_BASE_PTRS { CASPER } | ||
| 5444 | #endif | ||
| 5445 | |||
| 5446 | /*! | ||
| 5447 | * @} | ||
| 5448 | */ /* end of group CASPER_Peripheral_Access_Layer */ | ||
| 5449 | |||
| 5450 | |||
| 5451 | /* ---------------------------------------------------------------------------- | ||
| 5452 | -- CDOG Peripheral Access Layer | ||
| 5453 | ---------------------------------------------------------------------------- */ | ||
| 5454 | |||
| 5455 | /*! | ||
| 5456 | * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer | ||
| 5457 | * @{ | ||
| 5458 | */ | ||
| 5459 | |||
| 5460 | /** CDOG - Register Layout Typedef */ | ||
| 5461 | typedef struct { | ||
| 5462 | __IO uint32_t CONTROL; /**< The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself., offset: 0x0 */ | ||
| 5463 | __IO uint32_t RELOAD; /**< Instruction timer reload, offset: 0x4 */ | ||
| 5464 | __IO uint32_t INSTRUCTION_TIMER; /**< The INSTRUCTION TIMER itself, offset: 0x8 */ | ||
| 5465 | __IO uint32_t SECURE_COUNTER; /**< Also known as SEC_CNT, offset: 0xC */ | ||
| 5466 | __I uint32_t STATUS; /**< Status register (1 of 2), offset: 0x10 */ | ||
| 5467 | __I uint32_t STATUS2; /**< STATUS register (2 of 2), offset: 0x14 */ | ||
| 5468 | __IO uint32_t FLAGS; /**< Hardware flags, offset: 0x18 */ | ||
| 5469 | __IO uint32_t PERSISTENT; /**< Persistent (Ad. Hoc., quasi-NV) data storage, offset: 0x1C */ | ||
| 5470 | __O uint32_t START; /**< Write address for issuing the START command., offset: 0x20 */ | ||
| 5471 | __O uint32_t STOP; /**< Write address for issuing the STOP command., offset: 0x24 */ | ||
| 5472 | __O uint32_t RESTART; /**< Write address for issuing the RESTART command., offset: 0x28 */ | ||
| 5473 | __O uint32_t ADD; /**< Write address for issuing the ADD command., offset: 0x2C */ | ||
| 5474 | __O uint32_t ADD1; /**< Write address for issuing the ADD1 command., offset: 0x30 */ | ||
| 5475 | __O uint32_t ADD16; /**< Write address for issuing the ADD16 command., offset: 0x34 */ | ||
| 5476 | __O uint32_t ADD256; /**< Write address for issuing the ADD16 command., offset: 0x38 */ | ||
| 5477 | __O uint32_t SUB; /**< Write address for issuing the SUB command., offset: 0x3C */ | ||
| 5478 | __O uint32_t SUB1; /**< Write address for issuing the SUB1 command., offset: 0x40 */ | ||
| 5479 | __O uint32_t SUB16; /**< Write address for issuing the SUB16 command., offset: 0x44 */ | ||
| 5480 | __O uint32_t SUB256; /**< Write address for issuing the SUB256 command., offset: 0x48 */ | ||
| 5481 | } CDOG_Type; | ||
| 5482 | |||
| 5483 | /* ---------------------------------------------------------------------------- | ||
| 5484 | -- CDOG Register Masks | ||
| 5485 | ---------------------------------------------------------------------------- */ | ||
| 5486 | |||
| 5487 | /*! | ||
| 5488 | * @addtogroup CDOG_Register_Masks CDOG Register Masks | ||
| 5489 | * @{ | ||
| 5490 | */ | ||
| 5491 | |||
| 5492 | /*! @name CONTROL - The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. */ | ||
| 5493 | /*! @{ */ | ||
| 5494 | #define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) | ||
| 5495 | #define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) | ||
| 5496 | /*! LOCK_CTRL - Lock control field | ||
| 5497 | */ | ||
| 5498 | #define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) | ||
| 5499 | #define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) | ||
| 5500 | #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) | ||
| 5501 | /*! TIMEOUT_CTRL - TIMEOUT control | ||
| 5502 | */ | ||
| 5503 | #define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) | ||
| 5504 | #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) | ||
| 5505 | #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) | ||
| 5506 | /*! MISCOMPARE_CTRL - MISCOMPARE control field | ||
| 5507 | */ | ||
| 5508 | #define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) | ||
| 5509 | #define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) | ||
| 5510 | #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) | ||
| 5511 | /*! SEQUENCE_CTRL - SEQUENCE control field | ||
| 5512 | */ | ||
| 5513 | #define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) | ||
| 5514 | #define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) | ||
| 5515 | #define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) | ||
| 5516 | /*! CONTROL_CTRL - CONTROL control field | ||
| 5517 | */ | ||
| 5518 | #define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) | ||
| 5519 | #define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) | ||
| 5520 | #define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) | ||
| 5521 | /*! STATE_CTRL - STATE control field | ||
| 5522 | */ | ||
| 5523 | #define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) | ||
| 5524 | #define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) | ||
| 5525 | #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) | ||
| 5526 | /*! ADDRESS_CTRL - ADDRESS control field | ||
| 5527 | */ | ||
| 5528 | #define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) | ||
| 5529 | #define CDOG_CONTROL_Un_Imps_MASK (0xFF00000U) | ||
| 5530 | #define CDOG_CONTROL_Un_Imps_SHIFT (20U) | ||
| 5531 | /*! Un_Imps - The un-imps are un-IMPs! | ||
| 5532 | */ | ||
| 5533 | #define CDOG_CONTROL_Un_Imps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_Un_Imps_SHIFT)) & CDOG_CONTROL_Un_Imps_MASK) | ||
| 5534 | #define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) | ||
| 5535 | #define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) | ||
| 5536 | /*! IRQ_PAUSE - IRQ pause control field | ||
| 5537 | */ | ||
| 5538 | #define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) | ||
| 5539 | #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) | ||
| 5540 | #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) | ||
| 5541 | /*! DEBUG_HALT_CTRL - DEBUG_HALT control field | ||
| 5542 | */ | ||
| 5543 | #define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) | ||
| 5544 | /*! @} */ | ||
| 5545 | |||
| 5546 | /*! @name RELOAD - Instruction timer reload */ | ||
| 5547 | /*! @{ */ | ||
| 5548 | #define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) | ||
| 5549 | #define CDOG_RELOAD_RLOAD_SHIFT (0U) | ||
| 5550 | /*! RLOAD - Inst. Timer reload value | ||
| 5551 | */ | ||
| 5552 | #define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) | ||
| 5553 | /*! @} */ | ||
| 5554 | |||
| 5555 | /*! @name INSTRUCTION_TIMER - The INSTRUCTION TIMER itself */ | ||
| 5556 | /*! @{ */ | ||
| 5557 | #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) | ||
| 5558 | #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) | ||
| 5559 | /*! INSTIM - INSTRUCTION TIMER 32-bit value | ||
| 5560 | */ | ||
| 5561 | #define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) | ||
| 5562 | /*! @} */ | ||
| 5563 | |||
| 5564 | /*! @name SECURE_COUNTER - Also known as SEC_CNT */ | ||
| 5565 | /*! @{ */ | ||
| 5566 | #define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) | ||
| 5567 | #define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) | ||
| 5568 | /*! SECCNT - Secure Counter | ||
| 5569 | */ | ||
| 5570 | #define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) | ||
| 5571 | /*! @} */ | ||
| 5572 | |||
| 5573 | /*! @name STATUS - Status register (1 of 2) */ | ||
| 5574 | /*! @{ */ | ||
| 5575 | #define CDOG_STATUS_NUMTOF_MASK (0xFFU) | ||
| 5576 | #define CDOG_STATUS_NUMTOF_SHIFT (0U) | ||
| 5577 | /*! NUMTOF - Number of Timeout Faults | ||
| 5578 | */ | ||
| 5579 | #define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) | ||
| 5580 | #define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) | ||
| 5581 | #define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) | ||
| 5582 | /*! NUMMISCOMPF - Number of Miscompare Faults | ||
| 5583 | */ | ||
| 5584 | #define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) | ||
| 5585 | #define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) | ||
| 5586 | #define CDOG_STATUS_NUMILSEQF_SHIFT (16U) | ||
| 5587 | /*! NUMILSEQF - Number of illegal sequence faults | ||
| 5588 | */ | ||
| 5589 | #define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) | ||
| 5590 | #define CDOG_STATUS_CURST_MASK (0xF000000U) | ||
| 5591 | #define CDOG_STATUS_CURST_SHIFT (24U) | ||
| 5592 | /*! CURST - Current State | ||
| 5593 | */ | ||
| 5594 | #define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) | ||
| 5595 | #define CDOG_STATUS_uN_iMps_MASK (0xF0000000U) | ||
| 5596 | #define CDOG_STATUS_uN_iMps_SHIFT (28U) | ||
| 5597 | /*! uN_iMps - Un implemented | ||
| 5598 | */ | ||
| 5599 | #define CDOG_STATUS_uN_iMps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_uN_iMps_SHIFT)) & CDOG_STATUS_uN_iMps_MASK) | ||
| 5600 | /*! @} */ | ||
| 5601 | |||
| 5602 | /*! @name STATUS2 - STATUS register (2 of 2) */ | ||
| 5603 | /*! @{ */ | ||
| 5604 | #define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) | ||
| 5605 | #define CDOG_STATUS2_NUMCNTF_SHIFT (0U) | ||
| 5606 | /*! NUMCNTF - Number (of) control faults | ||
| 5607 | */ | ||
| 5608 | #define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) | ||
| 5609 | #define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) | ||
| 5610 | #define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) | ||
| 5611 | /*! NUMILLSTF - Number (of) state faults | ||
| 5612 | */ | ||
| 5613 | #define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) | ||
| 5614 | #define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) | ||
| 5615 | #define CDOG_STATUS2_NUMILLA_SHIFT (16U) | ||
| 5616 | /*! NUMILLA - Number of (illegal) address faults | ||
| 5617 | */ | ||
| 5618 | #define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) | ||
| 5619 | #define CDOG_STATUS2_un_imPs_MASK (0xFF000000U) | ||
| 5620 | #define CDOG_STATUS2_un_imPs_SHIFT (24U) | ||
| 5621 | /*! un_imPs - Unimplemented bits, such as these here, aren't there. | ||
| 5622 | */ | ||
| 5623 | #define CDOG_STATUS2_un_imPs(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_un_imPs_SHIFT)) & CDOG_STATUS2_un_imPs_MASK) | ||
| 5624 | /*! @} */ | ||
| 5625 | |||
| 5626 | /*! @name FLAGS - Hardware flags */ | ||
| 5627 | /*! @{ */ | ||
| 5628 | #define CDOG_FLAGS_TO_FLAG_MASK (0x1U) | ||
| 5629 | #define CDOG_FLAGS_TO_FLAG_SHIFT (0U) | ||
| 5630 | /*! TO_FLAG - Timeout flag | ||
| 5631 | */ | ||
| 5632 | #define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) | ||
| 5633 | #define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) | ||
| 5634 | #define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) | ||
| 5635 | /*! MISCOM_FLAG - Miscompare flag | ||
| 5636 | */ | ||
| 5637 | #define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) | ||
| 5638 | #define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) | ||
| 5639 | #define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) | ||
| 5640 | /*! SEQ_FLAG - Sequence flag | ||
| 5641 | */ | ||
| 5642 | #define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) | ||
| 5643 | #define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) | ||
| 5644 | #define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) | ||
| 5645 | /*! CNT_FLAG - Control (fault) flag | ||
| 5646 | */ | ||
| 5647 | #define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) | ||
| 5648 | #define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) | ||
| 5649 | #define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) | ||
| 5650 | /*! STATE_FLAG - State flag | ||
| 5651 | */ | ||
| 5652 | #define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) | ||
| 5653 | #define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) | ||
| 5654 | #define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) | ||
| 5655 | /*! ADDR_FLAG - Address flag | ||
| 5656 | */ | ||
| 5657 | #define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) | ||
| 5658 | #define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) | ||
| 5659 | #define CDOG_FLAGS_POR_FLAG_SHIFT (16U) | ||
| 5660 | /*! POR_FLAG - Power-on reset flag | ||
| 5661 | */ | ||
| 5662 | #define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) | ||
| 5663 | /*! @} */ | ||
| 5664 | |||
| 5665 | /*! @name PERSISTENT - Persistent (Ad. Hoc., quasi-NV) data storage */ | ||
| 5666 | /*! @{ */ | ||
| 5667 | #define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) | ||
| 5668 | #define CDOG_PERSISTENT_PERSIS_SHIFT (0U) | ||
| 5669 | /*! PERSIS - 32 regs free for user SW to enjoy | ||
| 5670 | */ | ||
| 5671 | #define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) | ||
| 5672 | /*! @} */ | ||
| 5673 | |||
| 5674 | /*! @name START - Write address for issuing the START command. */ | ||
| 5675 | /*! @{ */ | ||
| 5676 | #define CDOG_START_STRT_MASK (0xFFFFFFFFU) | ||
| 5677 | #define CDOG_START_STRT_SHIFT (0U) | ||
| 5678 | /*! STRT - Address of start command access | ||
| 5679 | */ | ||
| 5680 | #define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) | ||
| 5681 | /*! @} */ | ||
| 5682 | |||
| 5683 | /*! @name STOP - Write address for issuing the STOP command. */ | ||
| 5684 | /*! @{ */ | ||
| 5685 | #define CDOG_STOP_STP_MASK (0xFFFFFFFFU) | ||
| 5686 | #define CDOG_STOP_STP_SHIFT (0U) | ||
| 5687 | /*! STP - Address of stop command access | ||
| 5688 | */ | ||
| 5689 | #define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) | ||
| 5690 | /*! @} */ | ||
| 5691 | |||
| 5692 | /*! @name RESTART - Write address for issuing the RESTART command. */ | ||
| 5693 | /*! @{ */ | ||
| 5694 | #define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) | ||
| 5695 | #define CDOG_RESTART_RSTRT_SHIFT (0U) | ||
| 5696 | /*! RSTRT - Write address for issuing the RESTART command. | ||
| 5697 | */ | ||
| 5698 | #define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) | ||
| 5699 | /*! @} */ | ||
| 5700 | |||
| 5701 | /*! @name ADD - Write address for issuing the ADD command. */ | ||
| 5702 | /*! @{ */ | ||
| 5703 | #define CDOG_ADD_AD_MASK (0xFFFFFFFFU) | ||
| 5704 | #define CDOG_ADD_AD_SHIFT (0U) | ||
| 5705 | /*! AD - Address of ADD command | ||
| 5706 | */ | ||
| 5707 | #define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) | ||
| 5708 | /*! @} */ | ||
| 5709 | |||
| 5710 | /*! @name ADD1 - Write address for issuing the ADD1 command. */ | ||
| 5711 | /*! @{ */ | ||
| 5712 | #define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) | ||
| 5713 | #define CDOG_ADD1_AD1_SHIFT (0U) | ||
| 5714 | /*! AD1 - Address of ADD1 command. | ||
| 5715 | */ | ||
| 5716 | #define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) | ||
| 5717 | /*! @} */ | ||
| 5718 | |||
| 5719 | /*! @name ADD16 - Write address for issuing the ADD16 command. */ | ||
| 5720 | /*! @{ */ | ||
| 5721 | #define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) | ||
| 5722 | #define CDOG_ADD16_AD16_SHIFT (0U) | ||
| 5723 | /*! AD16 - Address of ADD16 | ||
| 5724 | */ | ||
| 5725 | #define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) | ||
| 5726 | /*! @} */ | ||
| 5727 | |||
| 5728 | /*! @name ADD256 - Write address for issuing the ADD16 command. */ | ||
| 5729 | /*! @{ */ | ||
| 5730 | #define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) | ||
| 5731 | #define CDOG_ADD256_AD256_SHIFT (0U) | ||
| 5732 | /*! AD256 - Address of ADD256 command | ||
| 5733 | */ | ||
| 5734 | #define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) | ||
| 5735 | /*! @} */ | ||
| 5736 | |||
| 5737 | /*! @name SUB - Write address for issuing the SUB command. */ | ||
| 5738 | /*! @{ */ | ||
| 5739 | #define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) | ||
| 5740 | #define CDOG_SUB_S0B_SHIFT (0U) | ||
| 5741 | /*! S0B - Address of SUB command. | ||
| 5742 | */ | ||
| 5743 | #define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) | ||
| 5744 | /*! @} */ | ||
| 5745 | |||
| 5746 | /*! @name SUB1 - Write address for issuing the SUB1 command. */ | ||
| 5747 | /*! @{ */ | ||
| 5748 | #define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) | ||
| 5749 | #define CDOG_SUB1_S1B_SHIFT (0U) | ||
| 5750 | /*! S1B - Address of SUB1 command. | ||
| 5751 | */ | ||
| 5752 | #define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) | ||
| 5753 | /*! @} */ | ||
| 5754 | |||
| 5755 | /*! @name SUB16 - Write address for issuing the SUB16 command. */ | ||
| 5756 | /*! @{ */ | ||
| 5757 | #define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) | ||
| 5758 | #define CDOG_SUB16_SB16_SHIFT (0U) | ||
| 5759 | /*! SB16 - Address of SUB16 command. | ||
| 5760 | */ | ||
| 5761 | #define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) | ||
| 5762 | /*! @} */ | ||
| 5763 | |||
| 5764 | /*! @name SUB256 - Write address for issuing the SUB256 command. */ | ||
| 5765 | /*! @{ */ | ||
| 5766 | #define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) | ||
| 5767 | #define CDOG_SUB256_SB256_SHIFT (0U) | ||
| 5768 | /*! SB256 - Address of (you guessed it) SUB256 command. | ||
| 5769 | */ | ||
| 5770 | #define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) | ||
| 5771 | /*! @} */ | ||
| 5772 | |||
| 5773 | |||
| 5774 | /*! | ||
| 5775 | * @} | ||
| 5776 | */ /* end of group CDOG_Register_Masks */ | ||
| 5777 | |||
| 5778 | |||
| 5779 | /* CDOG - Peripheral instance base addresses */ | ||
| 5780 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5781 | /** Peripheral CDOG base address */ | ||
| 5782 | #define CDOG_BASE (0x500A1000u) | ||
| 5783 | /** Peripheral CDOG base address */ | ||
| 5784 | #define CDOG_BASE_NS (0x400A1000u) | ||
| 5785 | /** Peripheral CDOG base pointer */ | ||
| 5786 | #define CDOG ((CDOG_Type *)CDOG_BASE) | ||
| 5787 | /** Peripheral CDOG base pointer */ | ||
| 5788 | #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) | ||
| 5789 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5790 | #define CDOG_BASE_ADDRS { CDOG_BASE } | ||
| 5791 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5792 | #define CDOG_BASE_PTRS { CDOG } | ||
| 5793 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5794 | #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } | ||
| 5795 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5796 | #define CDOG_BASE_PTRS_NS { CDOG_NS } | ||
| 5797 | #else | ||
| 5798 | /** Peripheral CDOG base address */ | ||
| 5799 | #define CDOG_BASE (0x400A1000u) | ||
| 5800 | /** Peripheral CDOG base pointer */ | ||
| 5801 | #define CDOG ((CDOG_Type *)CDOG_BASE) | ||
| 5802 | /** Array initializer of CDOG peripheral base addresses */ | ||
| 5803 | #define CDOG_BASE_ADDRS { CDOG_BASE } | ||
| 5804 | /** Array initializer of CDOG peripheral base pointers */ | ||
| 5805 | #define CDOG_BASE_PTRS { CDOG } | ||
| 5806 | #endif | ||
| 5807 | |||
| 5808 | /*! | ||
| 5809 | * @} | ||
| 5810 | */ /* end of group CDOG_Peripheral_Access_Layer */ | ||
| 5811 | |||
| 5812 | |||
| 5813 | /* ---------------------------------------------------------------------------- | ||
| 5814 | -- CRC Peripheral Access Layer | ||
| 5815 | ---------------------------------------------------------------------------- */ | ||
| 5816 | |||
| 5817 | /*! | ||
| 5818 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 5819 | * @{ | ||
| 5820 | */ | ||
| 5821 | |||
| 5822 | /** CRC - Register Layout Typedef */ | ||
| 5823 | typedef struct { | ||
| 5824 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ | ||
| 5825 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ | ||
| 5826 | union { /* offset: 0x8 */ | ||
| 5827 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ | ||
| 5828 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ | ||
| 5829 | }; | ||
| 5830 | } CRC_Type; | ||
| 5831 | |||
| 5832 | /* ---------------------------------------------------------------------------- | ||
| 5833 | -- CRC Register Masks | ||
| 5834 | ---------------------------------------------------------------------------- */ | ||
| 5835 | |||
| 5836 | /*! | ||
| 5837 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 5838 | * @{ | ||
| 5839 | */ | ||
| 5840 | |||
| 5841 | /*! @name MODE - CRC mode register */ | ||
| 5842 | /*! @{ */ | ||
| 5843 | #define CRC_MODE_CRC_POLY_MASK (0x3U) | ||
| 5844 | #define CRC_MODE_CRC_POLY_SHIFT (0U) | ||
| 5845 | /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial | ||
| 5846 | */ | ||
| 5847 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) | ||
| 5848 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) | ||
| 5849 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) | ||
| 5850 | /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) | ||
| 5851 | */ | ||
| 5852 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) | ||
| 5853 | #define CRC_MODE_CMPL_WR_MASK (0x8U) | ||
| 5854 | #define CRC_MODE_CMPL_WR_SHIFT (3U) | ||
| 5855 | /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA | ||
| 5856 | */ | ||
| 5857 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) | ||
| 5858 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) | ||
| 5859 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) | ||
| 5860 | /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM | ||
| 5861 | */ | ||
| 5862 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) | ||
| 5863 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) | ||
| 5864 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) | ||
| 5865 | /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM | ||
| 5866 | */ | ||
| 5867 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) | ||
| 5868 | /*! @} */ | ||
| 5869 | |||
| 5870 | /*! @name SEED - CRC seed register */ | ||
| 5871 | /*! @{ */ | ||
| 5872 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) | ||
| 5873 | #define CRC_SEED_CRC_SEED_SHIFT (0U) | ||
| 5874 | /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with | ||
| 5875 | * selected bit order and 1's complement pre-processes. A write access to this register will | ||
| 5876 | * overrule the CRC calculation in progresses. | ||
| 5877 | */ | ||
| 5878 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) | ||
| 5879 | /*! @} */ | ||
| 5880 | |||
| 5881 | /*! @name SUM - CRC checksum register */ | ||
| 5882 | /*! @{ */ | ||
| 5883 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) | ||
| 5884 | #define CRC_SUM_CRC_SUM_SHIFT (0U) | ||
| 5885 | /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. | ||
| 5886 | */ | ||
| 5887 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) | ||
| 5888 | /*! @} */ | ||
| 5889 | |||
| 5890 | /*! @name WR_DATA - CRC data register */ | ||
| 5891 | /*! @{ */ | ||
| 5892 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) | ||
| 5893 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) | ||
| 5894 | /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with | ||
| 5895 | * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and | ||
| 5896 | * accept back-to-back transactions. | ||
| 5897 | */ | ||
| 5898 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) | ||
| 5899 | /*! @} */ | ||
| 5900 | |||
| 5901 | |||
| 5902 | /*! | ||
| 5903 | * @} | ||
| 5904 | */ /* end of group CRC_Register_Masks */ | ||
| 5905 | |||
| 5906 | |||
| 5907 | /* CRC - Peripheral instance base addresses */ | ||
| 5908 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 5909 | /** Peripheral CRC_ENGINE base address */ | ||
| 5910 | #define CRC_ENGINE_BASE (0x50095000u) | ||
| 5911 | /** Peripheral CRC_ENGINE base address */ | ||
| 5912 | #define CRC_ENGINE_BASE_NS (0x40095000u) | ||
| 5913 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5914 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5915 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5916 | #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) | ||
| 5917 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5918 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5919 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5920 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5921 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5922 | #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } | ||
| 5923 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5924 | #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } | ||
| 5925 | #else | ||
| 5926 | /** Peripheral CRC_ENGINE base address */ | ||
| 5927 | #define CRC_ENGINE_BASE (0x40095000u) | ||
| 5928 | /** Peripheral CRC_ENGINE base pointer */ | ||
| 5929 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) | ||
| 5930 | /** Array initializer of CRC peripheral base addresses */ | ||
| 5931 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } | ||
| 5932 | /** Array initializer of CRC peripheral base pointers */ | ||
| 5933 | #define CRC_BASE_PTRS { CRC_ENGINE } | ||
| 5934 | #endif | ||
| 5935 | |||
| 5936 | /*! | ||
| 5937 | * @} | ||
| 5938 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 5939 | |||
| 5940 | |||
| 5941 | /* ---------------------------------------------------------------------------- | ||
| 5942 | -- CTIMER Peripheral Access Layer | ||
| 5943 | ---------------------------------------------------------------------------- */ | ||
| 5944 | |||
| 5945 | /*! | ||
| 5946 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer | ||
| 5947 | * @{ | ||
| 5948 | */ | ||
| 5949 | |||
| 5950 | /** CTIMER - Register Layout Typedef */ | ||
| 5951 | typedef struct { | ||
| 5952 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ | ||
| 5953 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ | ||
| 5954 | __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ | ||
| 5955 | __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ | ||
| 5956 | __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ | ||
| 5957 | __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ | ||
| 5958 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ | ||
| 5959 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ | ||
| 5960 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ | ||
| 5961 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ | ||
| 5962 | uint8_t RESERVED_0[48]; | ||
| 5963 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ | ||
| 5964 | __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ | ||
| 5965 | __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ | ||
| 5966 | } CTIMER_Type; | ||
| 5967 | |||
| 5968 | /* ---------------------------------------------------------------------------- | ||
| 5969 | -- CTIMER Register Masks | ||
| 5970 | ---------------------------------------------------------------------------- */ | ||
| 5971 | |||
| 5972 | /*! | ||
| 5973 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks | ||
| 5974 | * @{ | ||
| 5975 | */ | ||
| 5976 | |||
| 5977 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ | ||
| 5978 | /*! @{ */ | ||
| 5979 | #define CTIMER_IR_MR0INT_MASK (0x1U) | ||
| 5980 | #define CTIMER_IR_MR0INT_SHIFT (0U) | ||
| 5981 | /*! MR0INT - Interrupt flag for match channel 0. | ||
| 5982 | */ | ||
| 5983 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) | ||
| 5984 | #define CTIMER_IR_MR1INT_MASK (0x2U) | ||
| 5985 | #define CTIMER_IR_MR1INT_SHIFT (1U) | ||
| 5986 | /*! MR1INT - Interrupt flag for match channel 1. | ||
| 5987 | */ | ||
| 5988 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) | ||
| 5989 | #define CTIMER_IR_MR2INT_MASK (0x4U) | ||
| 5990 | #define CTIMER_IR_MR2INT_SHIFT (2U) | ||
| 5991 | /*! MR2INT - Interrupt flag for match channel 2. | ||
| 5992 | */ | ||
| 5993 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) | ||
| 5994 | #define CTIMER_IR_MR3INT_MASK (0x8U) | ||
| 5995 | #define CTIMER_IR_MR3INT_SHIFT (3U) | ||
| 5996 | /*! MR3INT - Interrupt flag for match channel 3. | ||
| 5997 | */ | ||
| 5998 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) | ||
| 5999 | #define CTIMER_IR_CR0INT_MASK (0x10U) | ||
| 6000 | #define CTIMER_IR_CR0INT_SHIFT (4U) | ||
| 6001 | /*! CR0INT - Interrupt flag for capture channel 0 event. | ||
| 6002 | */ | ||
| 6003 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) | ||
| 6004 | #define CTIMER_IR_CR1INT_MASK (0x20U) | ||
| 6005 | #define CTIMER_IR_CR1INT_SHIFT (5U) | ||
| 6006 | /*! CR1INT - Interrupt flag for capture channel 1 event. | ||
| 6007 | */ | ||
| 6008 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) | ||
| 6009 | #define CTIMER_IR_CR2INT_MASK (0x40U) | ||
| 6010 | #define CTIMER_IR_CR2INT_SHIFT (6U) | ||
| 6011 | /*! CR2INT - Interrupt flag for capture channel 2 event. | ||
| 6012 | */ | ||
| 6013 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) | ||
| 6014 | #define CTIMER_IR_CR3INT_MASK (0x80U) | ||
| 6015 | #define CTIMER_IR_CR3INT_SHIFT (7U) | ||
| 6016 | /*! CR3INT - Interrupt flag for capture channel 3 event. | ||
| 6017 | */ | ||
| 6018 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) | ||
| 6019 | /*! @} */ | ||
| 6020 | |||
| 6021 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ | ||
| 6022 | /*! @{ */ | ||
| 6023 | #define CTIMER_TCR_CEN_MASK (0x1U) | ||
| 6024 | #define CTIMER_TCR_CEN_SHIFT (0U) | ||
| 6025 | /*! CEN - Counter enable. | ||
| 6026 | * 0b0..Disabled.The counters are disabled. | ||
| 6027 | * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. | ||
| 6028 | */ | ||
| 6029 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) | ||
| 6030 | #define CTIMER_TCR_CRST_MASK (0x2U) | ||
| 6031 | #define CTIMER_TCR_CRST_SHIFT (1U) | ||
| 6032 | /*! CRST - Counter reset. | ||
| 6033 | * 0b0..Disabled. Do nothing. | ||
| 6034 | * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of | ||
| 6035 | * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. | ||
| 6036 | */ | ||
| 6037 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) | ||
| 6038 | /*! @} */ | ||
| 6039 | |||
| 6040 | /*! @name TC - Timer Counter */ | ||
| 6041 | /*! @{ */ | ||
| 6042 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) | ||
| 6043 | #define CTIMER_TC_TCVAL_SHIFT (0U) | ||
| 6044 | /*! TCVAL - Timer counter value. | ||
| 6045 | */ | ||
| 6046 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) | ||
| 6047 | /*! @} */ | ||
| 6048 | |||
| 6049 | /*! @name PR - Prescale Register */ | ||
| 6050 | /*! @{ */ | ||
| 6051 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) | ||
| 6052 | #define CTIMER_PR_PRVAL_SHIFT (0U) | ||
| 6053 | /*! PRVAL - Prescale counter value. | ||
| 6054 | */ | ||
| 6055 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) | ||
| 6056 | /*! @} */ | ||
| 6057 | |||
| 6058 | /*! @name PC - Prescale Counter */ | ||
| 6059 | /*! @{ */ | ||
| 6060 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) | ||
| 6061 | #define CTIMER_PC_PCVAL_SHIFT (0U) | ||
| 6062 | /*! PCVAL - Prescale counter value. | ||
| 6063 | */ | ||
| 6064 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) | ||
| 6065 | /*! @} */ | ||
| 6066 | |||
| 6067 | /*! @name MCR - Match Control Register */ | ||
| 6068 | /*! @{ */ | ||
| 6069 | #define CTIMER_MCR_MR0I_MASK (0x1U) | ||
| 6070 | #define CTIMER_MCR_MR0I_SHIFT (0U) | ||
| 6071 | /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. | ||
| 6072 | */ | ||
| 6073 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) | ||
| 6074 | #define CTIMER_MCR_MR0R_MASK (0x2U) | ||
| 6075 | #define CTIMER_MCR_MR0R_SHIFT (1U) | ||
| 6076 | /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. | ||
| 6077 | */ | ||
| 6078 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) | ||
| 6079 | #define CTIMER_MCR_MR0S_MASK (0x4U) | ||
| 6080 | #define CTIMER_MCR_MR0S_SHIFT (2U) | ||
| 6081 | /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. | ||
| 6082 | */ | ||
| 6083 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) | ||
| 6084 | #define CTIMER_MCR_MR1I_MASK (0x8U) | ||
| 6085 | #define CTIMER_MCR_MR1I_SHIFT (3U) | ||
| 6086 | /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. | ||
| 6087 | */ | ||
| 6088 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) | ||
| 6089 | #define CTIMER_MCR_MR1R_MASK (0x10U) | ||
| 6090 | #define CTIMER_MCR_MR1R_SHIFT (4U) | ||
| 6091 | /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. | ||
| 6092 | */ | ||
| 6093 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) | ||
| 6094 | #define CTIMER_MCR_MR1S_MASK (0x20U) | ||
| 6095 | #define CTIMER_MCR_MR1S_SHIFT (5U) | ||
| 6096 | /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. | ||
| 6097 | */ | ||
| 6098 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) | ||
| 6099 | #define CTIMER_MCR_MR2I_MASK (0x40U) | ||
| 6100 | #define CTIMER_MCR_MR2I_SHIFT (6U) | ||
| 6101 | /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. | ||
| 6102 | */ | ||
| 6103 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) | ||
| 6104 | #define CTIMER_MCR_MR2R_MASK (0x80U) | ||
| 6105 | #define CTIMER_MCR_MR2R_SHIFT (7U) | ||
| 6106 | /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. | ||
| 6107 | */ | ||
| 6108 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) | ||
| 6109 | #define CTIMER_MCR_MR2S_MASK (0x100U) | ||
| 6110 | #define CTIMER_MCR_MR2S_SHIFT (8U) | ||
| 6111 | /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. | ||
| 6112 | */ | ||
| 6113 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) | ||
| 6114 | #define CTIMER_MCR_MR3I_MASK (0x200U) | ||
| 6115 | #define CTIMER_MCR_MR3I_SHIFT (9U) | ||
| 6116 | /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. | ||
| 6117 | */ | ||
| 6118 | #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) | ||
| 6119 | #define CTIMER_MCR_MR3R_MASK (0x400U) | ||
| 6120 | #define CTIMER_MCR_MR3R_SHIFT (10U) | ||
| 6121 | /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. | ||
| 6122 | */ | ||
| 6123 | #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) | ||
| 6124 | #define CTIMER_MCR_MR3S_MASK (0x800U) | ||
| 6125 | #define CTIMER_MCR_MR3S_SHIFT (11U) | ||
| 6126 | /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. | ||
| 6127 | */ | ||
| 6128 | #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) | ||
| 6129 | #define CTIMER_MCR_MR0RL_MASK (0x1000000U) | ||
| 6130 | #define CTIMER_MCR_MR0RL_SHIFT (24U) | ||
| 6131 | /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero | ||
| 6132 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 6133 | */ | ||
| 6134 | #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) | ||
| 6135 | #define CTIMER_MCR_MR1RL_MASK (0x2000000U) | ||
| 6136 | #define CTIMER_MCR_MR1RL_SHIFT (25U) | ||
| 6137 | /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero | ||
| 6138 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 6139 | */ | ||
| 6140 | #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) | ||
| 6141 | #define CTIMER_MCR_MR2RL_MASK (0x4000000U) | ||
| 6142 | #define CTIMER_MCR_MR2RL_SHIFT (26U) | ||
| 6143 | /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero | ||
| 6144 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 6145 | */ | ||
| 6146 | #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) | ||
| 6147 | #define CTIMER_MCR_MR3RL_MASK (0x8000000U) | ||
| 6148 | #define CTIMER_MCR_MR3RL_SHIFT (27U) | ||
| 6149 | /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero | ||
| 6150 | * (either via a match event or a write to bit 1 of the TCR). | ||
| 6151 | */ | ||
| 6152 | #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) | ||
| 6153 | /*! @} */ | ||
| 6154 | |||
| 6155 | /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ | ||
| 6156 | /*! @{ */ | ||
| 6157 | #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) | ||
| 6158 | #define CTIMER_MR_MATCH_SHIFT (0U) | ||
| 6159 | /*! MATCH - Timer counter match value. | ||
| 6160 | */ | ||
| 6161 | #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) | ||
| 6162 | /*! @} */ | ||
| 6163 | |||
| 6164 | /* The count of CTIMER_MR */ | ||
| 6165 | #define CTIMER_MR_COUNT (4U) | ||
| 6166 | |||
| 6167 | /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ | ||
| 6168 | /*! @{ */ | ||
| 6169 | #define CTIMER_CCR_CAP0RE_MASK (0x1U) | ||
| 6170 | #define CTIMER_CCR_CAP0RE_SHIFT (0U) | ||
| 6171 | /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with | ||
| 6172 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6173 | */ | ||
| 6174 | #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) | ||
| 6175 | #define CTIMER_CCR_CAP0FE_MASK (0x2U) | ||
| 6176 | #define CTIMER_CCR_CAP0FE_SHIFT (1U) | ||
| 6177 | /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with | ||
| 6178 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6179 | */ | ||
| 6180 | #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) | ||
| 6181 | #define CTIMER_CCR_CAP0I_MASK (0x4U) | ||
| 6182 | #define CTIMER_CCR_CAP0I_SHIFT (2U) | ||
| 6183 | /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. | ||
| 6184 | */ | ||
| 6185 | #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) | ||
| 6186 | #define CTIMER_CCR_CAP1RE_MASK (0x8U) | ||
| 6187 | #define CTIMER_CCR_CAP1RE_SHIFT (3U) | ||
| 6188 | /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with | ||
| 6189 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6190 | */ | ||
| 6191 | #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) | ||
| 6192 | #define CTIMER_CCR_CAP1FE_MASK (0x10U) | ||
| 6193 | #define CTIMER_CCR_CAP1FE_SHIFT (4U) | ||
| 6194 | /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with | ||
| 6195 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6196 | */ | ||
| 6197 | #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) | ||
| 6198 | #define CTIMER_CCR_CAP1I_MASK (0x20U) | ||
| 6199 | #define CTIMER_CCR_CAP1I_SHIFT (5U) | ||
| 6200 | /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. | ||
| 6201 | */ | ||
| 6202 | #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) | ||
| 6203 | #define CTIMER_CCR_CAP2RE_MASK (0x40U) | ||
| 6204 | #define CTIMER_CCR_CAP2RE_SHIFT (6U) | ||
| 6205 | /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with | ||
| 6206 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6207 | */ | ||
| 6208 | #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) | ||
| 6209 | #define CTIMER_CCR_CAP2FE_MASK (0x80U) | ||
| 6210 | #define CTIMER_CCR_CAP2FE_SHIFT (7U) | ||
| 6211 | /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with | ||
| 6212 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6213 | */ | ||
| 6214 | #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) | ||
| 6215 | #define CTIMER_CCR_CAP2I_MASK (0x100U) | ||
| 6216 | #define CTIMER_CCR_CAP2I_SHIFT (8U) | ||
| 6217 | /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. | ||
| 6218 | */ | ||
| 6219 | #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) | ||
| 6220 | #define CTIMER_CCR_CAP3RE_MASK (0x200U) | ||
| 6221 | #define CTIMER_CCR_CAP3RE_SHIFT (9U) | ||
| 6222 | /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with | ||
| 6223 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6224 | */ | ||
| 6225 | #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) | ||
| 6226 | #define CTIMER_CCR_CAP3FE_MASK (0x400U) | ||
| 6227 | #define CTIMER_CCR_CAP3FE_SHIFT (10U) | ||
| 6228 | /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with | ||
| 6229 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 6230 | */ | ||
| 6231 | #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) | ||
| 6232 | #define CTIMER_CCR_CAP3I_MASK (0x800U) | ||
| 6233 | #define CTIMER_CCR_CAP3I_SHIFT (11U) | ||
| 6234 | /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. | ||
| 6235 | */ | ||
| 6236 | #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) | ||
| 6237 | /*! @} */ | ||
| 6238 | |||
| 6239 | /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ | ||
| 6240 | /*! @{ */ | ||
| 6241 | #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) | ||
| 6242 | #define CTIMER_CR_CAP_SHIFT (0U) | ||
| 6243 | /*! CAP - Timer counter capture value. | ||
| 6244 | */ | ||
| 6245 | #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) | ||
| 6246 | /*! @} */ | ||
| 6247 | |||
| 6248 | /* The count of CTIMER_CR */ | ||
| 6249 | #define CTIMER_CR_COUNT (4U) | ||
| 6250 | |||
| 6251 | /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ | ||
| 6252 | /*! @{ */ | ||
| 6253 | #define CTIMER_EMR_EM0_MASK (0x1U) | ||
| 6254 | #define CTIMER_EMR_EM0_SHIFT (0U) | ||
| 6255 | /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output | ||
| 6256 | * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, | ||
| 6257 | * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if | ||
| 6258 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 6259 | */ | ||
| 6260 | #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) | ||
| 6261 | #define CTIMER_EMR_EM1_MASK (0x2U) | ||
| 6262 | #define CTIMER_EMR_EM1_SHIFT (1U) | ||
| 6263 | /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output | ||
| 6264 | * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, | ||
| 6265 | * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if | ||
| 6266 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 6267 | */ | ||
| 6268 | #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) | ||
| 6269 | #define CTIMER_EMR_EM2_MASK (0x4U) | ||
| 6270 | #define CTIMER_EMR_EM2_SHIFT (2U) | ||
| 6271 | /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output | ||
| 6272 | * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, | ||
| 6273 | * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if | ||
| 6274 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 6275 | */ | ||
| 6276 | #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) | ||
| 6277 | #define CTIMER_EMR_EM3_MASK (0x8U) | ||
| 6278 | #define CTIMER_EMR_EM3_SHIFT (3U) | ||
| 6279 | /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output | ||
| 6280 | * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, | ||
| 6281 | * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins | ||
| 6282 | * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 6283 | */ | ||
| 6284 | #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) | ||
| 6285 | #define CTIMER_EMR_EMC0_MASK (0x30U) | ||
| 6286 | #define CTIMER_EMR_EMC0_SHIFT (4U) | ||
| 6287 | /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. | ||
| 6288 | * 0b00..Do Nothing. | ||
| 6289 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). | ||
| 6290 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). | ||
| 6291 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 6292 | */ | ||
| 6293 | #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) | ||
| 6294 | #define CTIMER_EMR_EMC1_MASK (0xC0U) | ||
| 6295 | #define CTIMER_EMR_EMC1_SHIFT (6U) | ||
| 6296 | /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. | ||
| 6297 | * 0b00..Do Nothing. | ||
| 6298 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). | ||
| 6299 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). | ||
| 6300 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 6301 | */ | ||
| 6302 | #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) | ||
| 6303 | #define CTIMER_EMR_EMC2_MASK (0x300U) | ||
| 6304 | #define CTIMER_EMR_EMC2_SHIFT (8U) | ||
| 6305 | /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. | ||
| 6306 | * 0b00..Do Nothing. | ||
| 6307 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). | ||
| 6308 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). | ||
| 6309 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 6310 | */ | ||
| 6311 | #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) | ||
| 6312 | #define CTIMER_EMR_EMC3_MASK (0xC00U) | ||
| 6313 | #define CTIMER_EMR_EMC3_SHIFT (10U) | ||
| 6314 | /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. | ||
| 6315 | * 0b00..Do Nothing. | ||
| 6316 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). | ||
| 6317 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). | ||
| 6318 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 6319 | */ | ||
| 6320 | #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) | ||
| 6321 | /*! @} */ | ||
| 6322 | |||
| 6323 | /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ | ||
| 6324 | /*! @{ */ | ||
| 6325 | #define CTIMER_CTCR_CTMODE_MASK (0x3U) | ||
| 6326 | #define CTIMER_CTCR_CTMODE_SHIFT (0U) | ||
| 6327 | /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment | ||
| 6328 | * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC | ||
| 6329 | * is incremented when the Prescale Counter matches the Prescale Register. | ||
| 6330 | * 0b00..Timer Mode. Incremented every rising APB bus clock edge. | ||
| 6331 | * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. | ||
| 6332 | * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. | ||
| 6333 | * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. | ||
| 6334 | */ | ||
| 6335 | #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) | ||
| 6336 | #define CTIMER_CTCR_CINSEL_MASK (0xCU) | ||
| 6337 | #define CTIMER_CTCR_CINSEL_SHIFT (2U) | ||
| 6338 | /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which | ||
| 6339 | * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input | ||
| 6340 | * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be | ||
| 6341 | * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the | ||
| 6342 | * same timer. | ||
| 6343 | * 0b00..Channel 0. CAPn.0 for CTIMERn | ||
| 6344 | * 0b01..Channel 1. CAPn.1 for CTIMERn | ||
| 6345 | * 0b10..Channel 2. CAPn.2 for CTIMERn | ||
| 6346 | * 0b11..Channel 3. CAPn.3 for CTIMERn | ||
| 6347 | */ | ||
| 6348 | #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) | ||
| 6349 | #define CTIMER_CTCR_ENCC_MASK (0x10U) | ||
| 6350 | #define CTIMER_CTCR_ENCC_SHIFT (4U) | ||
| 6351 | /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the | ||
| 6352 | * capture-edge event specified in bits 7:5 occurs. | ||
| 6353 | */ | ||
| 6354 | #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) | ||
| 6355 | #define CTIMER_CTCR_SELCC_MASK (0xE0U) | ||
| 6356 | #define CTIMER_CTCR_SELCC_SHIFT (5U) | ||
| 6357 | /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the | ||
| 6358 | * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to | ||
| 6359 | * 0x3 and 0x6 to 0x7 are reserved. | ||
| 6360 | * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 6361 | * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 6362 | * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 6363 | * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 6364 | * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 6365 | * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 6366 | */ | ||
| 6367 | #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) | ||
| 6368 | /*! @} */ | ||
| 6369 | |||
| 6370 | /*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ | ||
| 6371 | /*! @{ */ | ||
| 6372 | #define CTIMER_PWMC_PWMEN0_MASK (0x1U) | ||
| 6373 | #define CTIMER_PWMC_PWMEN0_SHIFT (0U) | ||
| 6374 | /*! PWMEN0 - PWM mode enable for channel0. | ||
| 6375 | * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. | ||
| 6376 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. | ||
| 6377 | */ | ||
| 6378 | #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) | ||
| 6379 | #define CTIMER_PWMC_PWMEN1_MASK (0x2U) | ||
| 6380 | #define CTIMER_PWMC_PWMEN1_SHIFT (1U) | ||
| 6381 | /*! PWMEN1 - PWM mode enable for channel1. | ||
| 6382 | * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. | ||
| 6383 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. | ||
| 6384 | */ | ||
| 6385 | #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) | ||
| 6386 | #define CTIMER_PWMC_PWMEN2_MASK (0x4U) | ||
| 6387 | #define CTIMER_PWMC_PWMEN2_SHIFT (2U) | ||
| 6388 | /*! PWMEN2 - PWM mode enable for channel2. | ||
| 6389 | * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. | ||
| 6390 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. | ||
| 6391 | */ | ||
| 6392 | #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) | ||
| 6393 | #define CTIMER_PWMC_PWMEN3_MASK (0x8U) | ||
| 6394 | #define CTIMER_PWMC_PWMEN3_SHIFT (3U) | ||
| 6395 | /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. | ||
| 6396 | * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. | ||
| 6397 | * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. | ||
| 6398 | */ | ||
| 6399 | #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) | ||
| 6400 | /*! @} */ | ||
| 6401 | |||
| 6402 | /*! @name MSR - Match Shadow Register */ | ||
| 6403 | /*! @{ */ | ||
| 6404 | #define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) | ||
| 6405 | #define CTIMER_MSR_SHADOW_SHIFT (0U) | ||
| 6406 | /*! SHADOW - Timer counter match shadow value. | ||
| 6407 | */ | ||
| 6408 | #define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) | ||
| 6409 | /*! @} */ | ||
| 6410 | |||
| 6411 | /* The count of CTIMER_MSR */ | ||
| 6412 | #define CTIMER_MSR_COUNT (4U) | ||
| 6413 | |||
| 6414 | |||
| 6415 | /*! | ||
| 6416 | * @} | ||
| 6417 | */ /* end of group CTIMER_Register_Masks */ | ||
| 6418 | |||
| 6419 | |||
| 6420 | /* CTIMER - Peripheral instance base addresses */ | ||
| 6421 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 6422 | /** Peripheral CTIMER0 base address */ | ||
| 6423 | #define CTIMER0_BASE (0x50008000u) | ||
| 6424 | /** Peripheral CTIMER0 base address */ | ||
| 6425 | #define CTIMER0_BASE_NS (0x40008000u) | ||
| 6426 | /** Peripheral CTIMER0 base pointer */ | ||
| 6427 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 6428 | /** Peripheral CTIMER0 base pointer */ | ||
| 6429 | #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) | ||
| 6430 | /** Peripheral CTIMER1 base address */ | ||
| 6431 | #define CTIMER1_BASE (0x50009000u) | ||
| 6432 | /** Peripheral CTIMER1 base address */ | ||
| 6433 | #define CTIMER1_BASE_NS (0x40009000u) | ||
| 6434 | /** Peripheral CTIMER1 base pointer */ | ||
| 6435 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) | ||
| 6436 | /** Peripheral CTIMER1 base pointer */ | ||
| 6437 | #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) | ||
| 6438 | /** Peripheral CTIMER2 base address */ | ||
| 6439 | #define CTIMER2_BASE (0x50028000u) | ||
| 6440 | /** Peripheral CTIMER2 base address */ | ||
| 6441 | #define CTIMER2_BASE_NS (0x40028000u) | ||
| 6442 | /** Peripheral CTIMER2 base pointer */ | ||
| 6443 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) | ||
| 6444 | /** Peripheral CTIMER2 base pointer */ | ||
| 6445 | #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) | ||
| 6446 | /** Peripheral CTIMER3 base address */ | ||
| 6447 | #define CTIMER3_BASE (0x50029000u) | ||
| 6448 | /** Peripheral CTIMER3 base address */ | ||
| 6449 | #define CTIMER3_BASE_NS (0x40029000u) | ||
| 6450 | /** Peripheral CTIMER3 base pointer */ | ||
| 6451 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) | ||
| 6452 | /** Peripheral CTIMER3 base pointer */ | ||
| 6453 | #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) | ||
| 6454 | /** Peripheral CTIMER4 base address */ | ||
| 6455 | #define CTIMER4_BASE (0x5002A000u) | ||
| 6456 | /** Peripheral CTIMER4 base address */ | ||
| 6457 | #define CTIMER4_BASE_NS (0x4002A000u) | ||
| 6458 | /** Peripheral CTIMER4 base pointer */ | ||
| 6459 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) | ||
| 6460 | /** Peripheral CTIMER4 base pointer */ | ||
| 6461 | #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) | ||
| 6462 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 6463 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } | ||
| 6464 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 6465 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } | ||
| 6466 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 6467 | #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } | ||
| 6468 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 6469 | #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } | ||
| 6470 | #else | ||
| 6471 | /** Peripheral CTIMER0 base address */ | ||
| 6472 | #define CTIMER0_BASE (0x40008000u) | ||
| 6473 | /** Peripheral CTIMER0 base pointer */ | ||
| 6474 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 6475 | /** Peripheral CTIMER1 base address */ | ||
| 6476 | #define CTIMER1_BASE (0x40009000u) | ||
| 6477 | /** Peripheral CTIMER1 base pointer */ | ||
| 6478 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) | ||
| 6479 | /** Peripheral CTIMER2 base address */ | ||
| 6480 | #define CTIMER2_BASE (0x40028000u) | ||
| 6481 | /** Peripheral CTIMER2 base pointer */ | ||
| 6482 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) | ||
| 6483 | /** Peripheral CTIMER3 base address */ | ||
| 6484 | #define CTIMER3_BASE (0x40029000u) | ||
| 6485 | /** Peripheral CTIMER3 base pointer */ | ||
| 6486 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) | ||
| 6487 | /** Peripheral CTIMER4 base address */ | ||
| 6488 | #define CTIMER4_BASE (0x4002A000u) | ||
| 6489 | /** Peripheral CTIMER4 base pointer */ | ||
| 6490 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) | ||
| 6491 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 6492 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } | ||
| 6493 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 6494 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } | ||
| 6495 | #endif | ||
| 6496 | /** Interrupt vectors for the CTIMER peripheral type */ | ||
| 6497 | #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } | ||
| 6498 | |||
| 6499 | /*! | ||
| 6500 | * @} | ||
| 6501 | */ /* end of group CTIMER_Peripheral_Access_Layer */ | ||
| 6502 | |||
| 6503 | |||
| 6504 | /* ---------------------------------------------------------------------------- | ||
| 6505 | -- DBGMAILBOX Peripheral Access Layer | ||
| 6506 | ---------------------------------------------------------------------------- */ | ||
| 6507 | |||
| 6508 | /*! | ||
| 6509 | * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer | ||
| 6510 | * @{ | ||
| 6511 | */ | ||
| 6512 | |||
| 6513 | /** DBGMAILBOX - Register Layout Typedef */ | ||
| 6514 | typedef struct { | ||
| 6515 | __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ | ||
| 6516 | __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ | ||
| 6517 | __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ | ||
| 6518 | uint8_t RESERVED_0[240]; | ||
| 6519 | __I uint32_t ID; /**< Identification register, offset: 0xFC */ | ||
| 6520 | } DBGMAILBOX_Type; | ||
| 6521 | |||
| 6522 | /* ---------------------------------------------------------------------------- | ||
| 6523 | -- DBGMAILBOX Register Masks | ||
| 6524 | ---------------------------------------------------------------------------- */ | ||
| 6525 | |||
| 6526 | /*! | ||
| 6527 | * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks | ||
| 6528 | * @{ | ||
| 6529 | */ | ||
| 6530 | |||
| 6531 | /*! @name CSW - CRC mode register */ | ||
| 6532 | /*! @{ */ | ||
| 6533 | #define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) | ||
| 6534 | #define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) | ||
| 6535 | /*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation | ||
| 6536 | */ | ||
| 6537 | #define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) | ||
| 6538 | #define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) | ||
| 6539 | #define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) | ||
| 6540 | /*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) | ||
| 6541 | */ | ||
| 6542 | #define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) | ||
| 6543 | #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) | ||
| 6544 | #define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) | ||
| 6545 | /*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) | ||
| 6546 | */ | ||
| 6547 | #define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) | ||
| 6548 | #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) | ||
| 6549 | #define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) | ||
| 6550 | /*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) | ||
| 6551 | */ | ||
| 6552 | #define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) | ||
| 6553 | #define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) | ||
| 6554 | #define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) | ||
| 6555 | /*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to | ||
| 6556 | * this bit will cause a soft reset for DM. | ||
| 6557 | */ | ||
| 6558 | #define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) | ||
| 6559 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) | ||
| 6560 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) | ||
| 6561 | /*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is | ||
| 6562 | * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) | ||
| 6563 | */ | ||
| 6564 | #define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) | ||
| 6565 | /*! @} */ | ||
| 6566 | |||
| 6567 | /*! @name REQUEST - CRC seed register */ | ||
| 6568 | /*! @{ */ | ||
| 6569 | #define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) | ||
| 6570 | #define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) | ||
| 6571 | /*! REQ - Request Value | ||
| 6572 | */ | ||
| 6573 | #define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) | ||
| 6574 | /*! @} */ | ||
| 6575 | |||
| 6576 | /*! @name RETURN - Return value from ROM. */ | ||
| 6577 | /*! @{ */ | ||
| 6578 | #define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) | ||
| 6579 | #define DBGMAILBOX_RETURN_RET_SHIFT (0U) | ||
| 6580 | /*! RET - The Return value from ROM. | ||
| 6581 | */ | ||
| 6582 | #define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) | ||
| 6583 | /*! @} */ | ||
| 6584 | |||
| 6585 | /*! @name ID - Identification register */ | ||
| 6586 | /*! @{ */ | ||
| 6587 | #define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) | ||
| 6588 | #define DBGMAILBOX_ID_ID_SHIFT (0U) | ||
| 6589 | /*! ID - Identification value. | ||
| 6590 | */ | ||
| 6591 | #define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) | ||
| 6592 | /*! @} */ | ||
| 6593 | |||
| 6594 | |||
| 6595 | /*! | ||
| 6596 | * @} | ||
| 6597 | */ /* end of group DBGMAILBOX_Register_Masks */ | ||
| 6598 | |||
| 6599 | |||
| 6600 | /* DBGMAILBOX - Peripheral instance base addresses */ | ||
| 6601 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 6602 | /** Peripheral DBGMAILBOX base address */ | ||
| 6603 | #define DBGMAILBOX_BASE (0x5009C000u) | ||
| 6604 | /** Peripheral DBGMAILBOX base address */ | ||
| 6605 | #define DBGMAILBOX_BASE_NS (0x4009C000u) | ||
| 6606 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 6607 | #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) | ||
| 6608 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 6609 | #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) | ||
| 6610 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 6611 | #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } | ||
| 6612 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 6613 | #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } | ||
| 6614 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 6615 | #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } | ||
| 6616 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 6617 | #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } | ||
| 6618 | #else | ||
| 6619 | /** Peripheral DBGMAILBOX base address */ | ||
| 6620 | #define DBGMAILBOX_BASE (0x4009C000u) | ||
| 6621 | /** Peripheral DBGMAILBOX base pointer */ | ||
| 6622 | #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) | ||
| 6623 | /** Array initializer of DBGMAILBOX peripheral base addresses */ | ||
| 6624 | #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } | ||
| 6625 | /** Array initializer of DBGMAILBOX peripheral base pointers */ | ||
| 6626 | #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } | ||
| 6627 | #endif | ||
| 6628 | |||
| 6629 | /*! | ||
| 6630 | * @} | ||
| 6631 | */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ | ||
| 6632 | |||
| 6633 | |||
| 6634 | /* ---------------------------------------------------------------------------- | ||
| 6635 | -- DMA Peripheral Access Layer | ||
| 6636 | ---------------------------------------------------------------------------- */ | ||
| 6637 | |||
| 6638 | /*! | ||
| 6639 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 6640 | * @{ | ||
| 6641 | */ | ||
| 6642 | |||
| 6643 | /** DMA - Register Layout Typedef */ | ||
| 6644 | typedef struct { | ||
| 6645 | __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ | ||
| 6646 | __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ | ||
| 6647 | __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ | ||
| 6648 | uint8_t RESERVED_0[20]; | ||
| 6649 | struct { /* offset: 0x20, array step: 0x5C */ | ||
| 6650 | __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ | ||
| 6651 | uint8_t RESERVED_0[4]; | ||
| 6652 | __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ | ||
| 6653 | uint8_t RESERVED_1[4]; | ||
| 6654 | __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ | ||
| 6655 | uint8_t RESERVED_2[4]; | ||
| 6656 | __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ | ||
| 6657 | uint8_t RESERVED_3[4]; | ||
| 6658 | __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ | ||
| 6659 | uint8_t RESERVED_4[4]; | ||
| 6660 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ | ||
| 6661 | uint8_t RESERVED_5[4]; | ||
| 6662 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ | ||
| 6663 | uint8_t RESERVED_6[4]; | ||
| 6664 | __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ | ||
| 6665 | uint8_t RESERVED_7[4]; | ||
| 6666 | __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ | ||
| 6667 | uint8_t RESERVED_8[4]; | ||
| 6668 | __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ | ||
| 6669 | uint8_t RESERVED_9[4]; | ||
| 6670 | __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ | ||
| 6671 | uint8_t RESERVED_10[4]; | ||
| 6672 | __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ | ||
| 6673 | } COMMON[1]; | ||
| 6674 | uint8_t RESERVED_1[900]; | ||
| 6675 | struct { /* offset: 0x400, array step: 0x10 */ | ||
| 6676 | __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ | ||
| 6677 | __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ | ||
| 6678 | __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ | ||
| 6679 | uint8_t RESERVED_0[4]; | ||
| 6680 | } CHANNEL[23]; | ||
| 6681 | } DMA_Type; | ||
| 6682 | |||
| 6683 | /* ---------------------------------------------------------------------------- | ||
| 6684 | -- DMA Register Masks | ||
| 6685 | ---------------------------------------------------------------------------- */ | ||
| 6686 | |||
| 6687 | /*! | ||
| 6688 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 6689 | * @{ | ||
| 6690 | */ | ||
| 6691 | |||
| 6692 | /*! @name CTRL - DMA control. */ | ||
| 6693 | /*! @{ */ | ||
| 6694 | #define DMA_CTRL_ENABLE_MASK (0x1U) | ||
| 6695 | #define DMA_CTRL_ENABLE_SHIFT (0U) | ||
| 6696 | /*! ENABLE - DMA controller master enable. | ||
| 6697 | * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when | ||
| 6698 | * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. | ||
| 6699 | * 0b1..Enabled. The DMA controller is enabled. | ||
| 6700 | */ | ||
| 6701 | #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) | ||
| 6702 | /*! @} */ | ||
| 6703 | |||
| 6704 | /*! @name INTSTAT - Interrupt status. */ | ||
| 6705 | /*! @{ */ | ||
| 6706 | #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) | ||
| 6707 | #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) | ||
| 6708 | /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. | ||
| 6709 | * 0b0..Not pending. No enabled interrupts are pending. | ||
| 6710 | * 0b1..Pending. At least one enabled interrupt is pending. | ||
| 6711 | */ | ||
| 6712 | #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) | ||
| 6713 | #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) | ||
| 6714 | #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) | ||
| 6715 | /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. | ||
| 6716 | * 0b0..Not pending. No error interrupts are pending. | ||
| 6717 | * 0b1..Pending. At least one error interrupt is pending. | ||
| 6718 | */ | ||
| 6719 | #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) | ||
| 6720 | /*! @} */ | ||
| 6721 | |||
| 6722 | /*! @name SRAMBASE - SRAM address of the channel configuration table. */ | ||
| 6723 | /*! @{ */ | ||
| 6724 | #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) | ||
| 6725 | #define DMA_SRAMBASE_OFFSET_SHIFT (9U) | ||
| 6726 | /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the | ||
| 6727 | * table must begin on a 512 byte boundary. | ||
| 6728 | */ | ||
| 6729 | #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) | ||
| 6730 | /*! @} */ | ||
| 6731 | |||
| 6732 | /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ | ||
| 6733 | /*! @{ */ | ||
| 6734 | #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) | ||
| 6735 | #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) | ||
| 6736 | /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = | ||
| 6737 | * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. | ||
| 6738 | */ | ||
| 6739 | #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) | ||
| 6740 | /*! @} */ | ||
| 6741 | |||
| 6742 | /* The count of DMA_COMMON_ENABLESET */ | ||
| 6743 | #define DMA_COMMON_ENABLESET_COUNT (1U) | ||
| 6744 | |||
| 6745 | /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ | ||
| 6746 | /*! @{ */ | ||
| 6747 | #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) | ||
| 6748 | #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) | ||
| 6749 | /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears | ||
| 6750 | * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits | ||
| 6751 | * are reserved. | ||
| 6752 | */ | ||
| 6753 | #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) | ||
| 6754 | /*! @} */ | ||
| 6755 | |||
| 6756 | /* The count of DMA_COMMON_ENABLECLR */ | ||
| 6757 | #define DMA_COMMON_ENABLECLR_COUNT (1U) | ||
| 6758 | |||
| 6759 | /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ | ||
| 6760 | /*! @{ */ | ||
| 6761 | #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) | ||
| 6762 | #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) | ||
| 6763 | /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 6764 | * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. | ||
| 6765 | */ | ||
| 6766 | #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) | ||
| 6767 | /*! @} */ | ||
| 6768 | |||
| 6769 | /* The count of DMA_COMMON_ACTIVE */ | ||
| 6770 | #define DMA_COMMON_ACTIVE_COUNT (1U) | ||
| 6771 | |||
| 6772 | /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ | ||
| 6773 | /*! @{ */ | ||
| 6774 | #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) | ||
| 6775 | #define DMA_COMMON_BUSY_BSY_SHIFT (0U) | ||
| 6776 | /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 6777 | * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. | ||
| 6778 | */ | ||
| 6779 | #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) | ||
| 6780 | /*! @} */ | ||
| 6781 | |||
| 6782 | /* The count of DMA_COMMON_BUSY */ | ||
| 6783 | #define DMA_COMMON_BUSY_COUNT (1U) | ||
| 6784 | |||
| 6785 | /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ | ||
| 6786 | /*! @{ */ | ||
| 6787 | #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) | ||
| 6788 | #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) | ||
| 6789 | /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 6790 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is | ||
| 6791 | * not active. 1 = error interrupt is active. | ||
| 6792 | */ | ||
| 6793 | #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) | ||
| 6794 | /*! @} */ | ||
| 6795 | |||
| 6796 | /* The count of DMA_COMMON_ERRINT */ | ||
| 6797 | #define DMA_COMMON_ERRINT_COUNT (1U) | ||
| 6798 | |||
| 6799 | /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ | ||
| 6800 | /*! @{ */ | ||
| 6801 | #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) | ||
| 6802 | #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) | ||
| 6803 | /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The | ||
| 6804 | * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = | ||
| 6805 | * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. | ||
| 6806 | */ | ||
| 6807 | #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) | ||
| 6808 | /*! @} */ | ||
| 6809 | |||
| 6810 | /* The count of DMA_COMMON_INTENSET */ | ||
| 6811 | #define DMA_COMMON_INTENSET_COUNT (1U) | ||
| 6812 | |||
| 6813 | /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ | ||
| 6814 | /*! @{ */ | ||
| 6815 | #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) | ||
| 6816 | #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) | ||
| 6817 | /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n | ||
| 6818 | * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are | ||
| 6819 | * reserved. | ||
| 6820 | */ | ||
| 6821 | #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) | ||
| 6822 | /*! @} */ | ||
| 6823 | |||
| 6824 | /* The count of DMA_COMMON_INTENCLR */ | ||
| 6825 | #define DMA_COMMON_INTENCLR_COUNT (1U) | ||
| 6826 | |||
| 6827 | /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ | ||
| 6828 | /*! @{ */ | ||
| 6829 | #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) | ||
| 6830 | #define DMA_COMMON_INTA_IA_SHIFT (0U) | ||
| 6831 | /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 6832 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 6833 | * interrupt A is not active. 1 = the DMA channel interrupt A is active. | ||
| 6834 | */ | ||
| 6835 | #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) | ||
| 6836 | /*! @} */ | ||
| 6837 | |||
| 6838 | /* The count of DMA_COMMON_INTA */ | ||
| 6839 | #define DMA_COMMON_INTA_COUNT (1U) | ||
| 6840 | |||
| 6841 | /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ | ||
| 6842 | /*! @{ */ | ||
| 6843 | #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) | ||
| 6844 | #define DMA_COMMON_INTB_IB_SHIFT (0U) | ||
| 6845 | /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 6846 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 6847 | * interrupt B is not active. 1 = the DMA channel interrupt B is active. | ||
| 6848 | */ | ||
| 6849 | #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) | ||
| 6850 | /*! @} */ | ||
| 6851 | |||
| 6852 | /* The count of DMA_COMMON_INTB */ | ||
| 6853 | #define DMA_COMMON_INTB_COUNT (1U) | ||
| 6854 | |||
| 6855 | /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ | ||
| 6856 | /*! @{ */ | ||
| 6857 | #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) | ||
| 6858 | #define DMA_COMMON_SETVALID_SV_SHIFT (0U) | ||
| 6859 | /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits | ||
| 6860 | * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the | ||
| 6861 | * VALIDPENDING control bit for DMA channel n | ||
| 6862 | */ | ||
| 6863 | #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) | ||
| 6864 | /*! @} */ | ||
| 6865 | |||
| 6866 | /* The count of DMA_COMMON_SETVALID */ | ||
| 6867 | #define DMA_COMMON_SETVALID_COUNT (1U) | ||
| 6868 | |||
| 6869 | /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ | ||
| 6870 | /*! @{ */ | ||
| 6871 | #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) | ||
| 6872 | #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) | ||
| 6873 | /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number | ||
| 6874 | * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = | ||
| 6875 | * sets the TRIG bit for DMA channel n. | ||
| 6876 | */ | ||
| 6877 | #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) | ||
| 6878 | /*! @} */ | ||
| 6879 | |||
| 6880 | /* The count of DMA_COMMON_SETTRIG */ | ||
| 6881 | #define DMA_COMMON_SETTRIG_COUNT (1U) | ||
| 6882 | |||
| 6883 | /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ | ||
| 6884 | /*! @{ */ | ||
| 6885 | #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) | ||
| 6886 | #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) | ||
| 6887 | /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. | ||
| 6888 | * 1 = aborts DMA operations on channel n. | ||
| 6889 | */ | ||
| 6890 | #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) | ||
| 6891 | /*! @} */ | ||
| 6892 | |||
| 6893 | /* The count of DMA_COMMON_ABORT */ | ||
| 6894 | #define DMA_COMMON_ABORT_COUNT (1U) | ||
| 6895 | |||
| 6896 | /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ | ||
| 6897 | /*! @{ */ | ||
| 6898 | #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) | ||
| 6899 | #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) | ||
| 6900 | /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory | ||
| 6901 | * move, any peripheral DMA request associated with that channel can be disabled to prevent any | ||
| 6902 | * interaction between the peripheral and the DMA controller. | ||
| 6903 | * 0b0..Disabled. Peripheral DMA requests are disabled. | ||
| 6904 | * 0b1..Enabled. Peripheral DMA requests are enabled. | ||
| 6905 | */ | ||
| 6906 | #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) | ||
| 6907 | #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) | ||
| 6908 | #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) | ||
| 6909 | /*! HWTRIGEN - Hardware Triggering Enable for this channel. | ||
| 6910 | * 0b0..Disabled. Hardware triggering is not used. | ||
| 6911 | * 0b1..Enabled. Use hardware triggering. | ||
| 6912 | */ | ||
| 6913 | #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) | ||
| 6914 | #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) | ||
| 6915 | #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) | ||
| 6916 | /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. | ||
| 6917 | * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. | ||
| 6918 | * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. | ||
| 6919 | */ | ||
| 6920 | #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) | ||
| 6921 | #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) | ||
| 6922 | #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) | ||
| 6923 | /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. | ||
| 6924 | * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. | ||
| 6925 | * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = | ||
| 6926 | * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the | ||
| 6927 | * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger | ||
| 6928 | * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the | ||
| 6929 | * current BURSTPOWER length are completed. | ||
| 6930 | */ | ||
| 6931 | #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) | ||
| 6932 | #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) | ||
| 6933 | #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) | ||
| 6934 | /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. | ||
| 6935 | * 0b0..Single transfer. Hardware trigger causes a single transfer. | ||
| 6936 | * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a | ||
| 6937 | * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a | ||
| 6938 | * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is | ||
| 6939 | * complete. | ||
| 6940 | */ | ||
| 6941 | #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) | ||
| 6942 | #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) | ||
| 6943 | #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) | ||
| 6944 | /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when | ||
| 6945 | * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). | ||
| 6946 | * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many | ||
| 6947 | * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that | ||
| 6948 | * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: | ||
| 6949 | * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = | ||
| 6950 | * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The | ||
| 6951 | * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even | ||
| 6952 | * multiple of the burst size. | ||
| 6953 | */ | ||
| 6954 | #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) | ||
| 6955 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) | ||
| 6956 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) | ||
| 6957 | /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is | ||
| 6958 | * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this | ||
| 6959 | * could be used to read several sequential registers from a peripheral for each DMA burst, | ||
| 6960 | * reading the same registers again for each burst. | ||
| 6961 | * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. | ||
| 6962 | * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. | ||
| 6963 | */ | ||
| 6964 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) | ||
| 6965 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) | ||
| 6966 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) | ||
| 6967 | /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is | ||
| 6968 | * 'wrapped', meaning that the destination address range for each burst will be the same. As an | ||
| 6969 | * example, this could be used to write several sequential registers to a peripheral for each DMA | ||
| 6970 | * burst, writing the same registers again for each burst. | ||
| 6971 | * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. | ||
| 6972 | * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. | ||
| 6973 | */ | ||
| 6974 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) | ||
| 6975 | #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) | ||
| 6976 | #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) | ||
| 6977 | /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority | ||
| 6978 | * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. | ||
| 6979 | */ | ||
| 6980 | #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) | ||
| 6981 | /*! @} */ | ||
| 6982 | |||
| 6983 | /* The count of DMA_CHANNEL_CFG */ | ||
| 6984 | #define DMA_CHANNEL_CFG_COUNT (23U) | ||
| 6985 | |||
| 6986 | /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ | ||
| 6987 | /*! @{ */ | ||
| 6988 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) | ||
| 6989 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) | ||
| 6990 | /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the | ||
| 6991 | * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. | ||
| 6992 | * 0b0..No effect. No effect on DMA operation. | ||
| 6993 | * 0b1..Valid pending. | ||
| 6994 | */ | ||
| 6995 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) | ||
| 6996 | #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) | ||
| 6997 | #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) | ||
| 6998 | /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is | ||
| 6999 | * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. | ||
| 7000 | * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. | ||
| 7001 | * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. | ||
| 7002 | */ | ||
| 7003 | #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) | ||
| 7004 | /*! @} */ | ||
| 7005 | |||
| 7006 | /* The count of DMA_CHANNEL_CTLSTAT */ | ||
| 7007 | #define DMA_CHANNEL_CTLSTAT_COUNT (23U) | ||
| 7008 | |||
| 7009 | /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ | ||
| 7010 | /*! @{ */ | ||
| 7011 | #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) | ||
| 7012 | #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) | ||
| 7013 | /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor | ||
| 7014 | * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. | ||
| 7015 | * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. | ||
| 7016 | * 0b1..Valid. The current channel descriptor is considered valid. | ||
| 7017 | */ | ||
| 7018 | #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) | ||
| 7019 | #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) | ||
| 7020 | #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) | ||
| 7021 | /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current | ||
| 7022 | * descriptor is exhausted. Reloading allows ping-pong and linked transfers. | ||
| 7023 | * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. | ||
| 7024 | * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. | ||
| 7025 | */ | ||
| 7026 | #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) | ||
| 7027 | #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) | ||
| 7028 | #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) | ||
| 7029 | /*! SWTRIG - Software Trigger. | ||
| 7030 | * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by | ||
| 7031 | * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. | ||
| 7032 | * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not | ||
| 7033 | * be used with level triggering when TRIGBURST = 0. | ||
| 7034 | */ | ||
| 7035 | #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) | ||
| 7036 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) | ||
| 7037 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) | ||
| 7038 | /*! CLRTRIG - Clear Trigger. | ||
| 7039 | * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. | ||
| 7040 | * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted | ||
| 7041 | */ | ||
| 7042 | #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) | ||
| 7043 | #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) | ||
| 7044 | #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) | ||
| 7045 | /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between | ||
| 7046 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 7047 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 7048 | * 0b0..No effect. | ||
| 7049 | * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. | ||
| 7050 | */ | ||
| 7051 | #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) | ||
| 7052 | #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) | ||
| 7053 | #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) | ||
| 7054 | /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between | ||
| 7055 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 7056 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 7057 | * 0b0..No effect. | ||
| 7058 | * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. | ||
| 7059 | */ | ||
| 7060 | #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) | ||
| 7061 | #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) | ||
| 7062 | #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) | ||
| 7063 | /*! WIDTH - Transfer width used for this DMA channel. | ||
| 7064 | * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). | ||
| 7065 | * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). | ||
| 7066 | * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). | ||
| 7067 | * 0b11..Reserved. Reserved setting, do not use. | ||
| 7068 | */ | ||
| 7069 | #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) | ||
| 7070 | #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) | ||
| 7071 | #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) | ||
| 7072 | /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. | ||
| 7073 | * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. | ||
| 7074 | * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is | ||
| 7075 | * the usual case when the source is memory. | ||
| 7076 | * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 7077 | * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 7078 | */ | ||
| 7079 | #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) | ||
| 7080 | #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) | ||
| 7081 | #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) | ||
| 7082 | /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. | ||
| 7083 | * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when | ||
| 7084 | * the destination is a peripheral device. | ||
| 7085 | * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. | ||
| 7086 | * This is the usual case when the destination is memory. | ||
| 7087 | * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 7088 | * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 7089 | */ | ||
| 7090 | #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) | ||
| 7091 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) | ||
| 7092 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) | ||
| 7093 | /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes | ||
| 7094 | * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller | ||
| 7095 | * uses this bit field during transfer to count down. Hence, it cannot be used by software to read | ||
| 7096 | * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 | ||
| 7097 | * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of | ||
| 7098 | * 1,024 transfers will be performed. | ||
| 7099 | */ | ||
| 7100 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) | ||
| 7101 | /*! @} */ | ||
| 7102 | |||
| 7103 | /* The count of DMA_CHANNEL_XFERCFG */ | ||
| 7104 | #define DMA_CHANNEL_XFERCFG_COUNT (23U) | ||
| 7105 | |||
| 7106 | |||
| 7107 | /*! | ||
| 7108 | * @} | ||
| 7109 | */ /* end of group DMA_Register_Masks */ | ||
| 7110 | |||
| 7111 | |||
| 7112 | /* DMA - Peripheral instance base addresses */ | ||
| 7113 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 7114 | /** Peripheral DMA0 base address */ | ||
| 7115 | #define DMA0_BASE (0x50082000u) | ||
| 7116 | /** Peripheral DMA0 base address */ | ||
| 7117 | #define DMA0_BASE_NS (0x40082000u) | ||
| 7118 | /** Peripheral DMA0 base pointer */ | ||
| 7119 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 7120 | /** Peripheral DMA0 base pointer */ | ||
| 7121 | #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) | ||
| 7122 | /** Peripheral DMA1 base address */ | ||
| 7123 | #define DMA1_BASE (0x500A7000u) | ||
| 7124 | /** Peripheral DMA1 base address */ | ||
| 7125 | #define DMA1_BASE_NS (0x400A7000u) | ||
| 7126 | /** Peripheral DMA1 base pointer */ | ||
| 7127 | #define DMA1 ((DMA_Type *)DMA1_BASE) | ||
| 7128 | /** Peripheral DMA1 base pointer */ | ||
| 7129 | #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) | ||
| 7130 | /** Array initializer of DMA peripheral base addresses */ | ||
| 7131 | #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } | ||
| 7132 | /** Array initializer of DMA peripheral base pointers */ | ||
| 7133 | #define DMA_BASE_PTRS { DMA0, DMA1 } | ||
| 7134 | /** Array initializer of DMA peripheral base addresses */ | ||
| 7135 | #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } | ||
| 7136 | /** Array initializer of DMA peripheral base pointers */ | ||
| 7137 | #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } | ||
| 7138 | #else | ||
| 7139 | /** Peripheral DMA0 base address */ | ||
| 7140 | #define DMA0_BASE (0x40082000u) | ||
| 7141 | /** Peripheral DMA0 base pointer */ | ||
| 7142 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 7143 | /** Peripheral DMA1 base address */ | ||
| 7144 | #define DMA1_BASE (0x400A7000u) | ||
| 7145 | /** Peripheral DMA1 base pointer */ | ||
| 7146 | #define DMA1 ((DMA_Type *)DMA1_BASE) | ||
| 7147 | /** Array initializer of DMA peripheral base addresses */ | ||
| 7148 | #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } | ||
| 7149 | /** Array initializer of DMA peripheral base pointers */ | ||
| 7150 | #define DMA_BASE_PTRS { DMA0, DMA1 } | ||
| 7151 | #endif | ||
| 7152 | /** Interrupt vectors for the DMA peripheral type */ | ||
| 7153 | #define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } | ||
| 7154 | |||
| 7155 | /*! | ||
| 7156 | * @} | ||
| 7157 | */ /* end of group DMA_Peripheral_Access_Layer */ | ||
| 7158 | |||
| 7159 | |||
| 7160 | /* ---------------------------------------------------------------------------- | ||
| 7161 | -- FLASH Peripheral Access Layer | ||
| 7162 | ---------------------------------------------------------------------------- */ | ||
| 7163 | |||
| 7164 | /*! | ||
| 7165 | * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer | ||
| 7166 | * @{ | ||
| 7167 | */ | ||
| 7168 | |||
| 7169 | /** FLASH - Register Layout Typedef */ | ||
| 7170 | typedef struct { | ||
| 7171 | __O uint32_t CMD; /**< command register, offset: 0x0 */ | ||
| 7172 | __O uint32_t EVENT; /**< event register, offset: 0x4 */ | ||
| 7173 | uint8_t RESERVED_0[8]; | ||
| 7174 | __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ | ||
| 7175 | __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ | ||
| 7176 | uint8_t RESERVED_1[104]; | ||
| 7177 | __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ | ||
| 7178 | uint8_t RESERVED_2[3912]; | ||
| 7179 | __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ | ||
| 7180 | __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ | ||
| 7181 | __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ | ||
| 7182 | __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ | ||
| 7183 | __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ | ||
| 7184 | __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ | ||
| 7185 | uint8_t RESERVED_3[12]; | ||
| 7186 | __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ | ||
| 7187 | } FLASH_Type; | ||
| 7188 | |||
| 7189 | /* ---------------------------------------------------------------------------- | ||
| 7190 | -- FLASH Register Masks | ||
| 7191 | ---------------------------------------------------------------------------- */ | ||
| 7192 | |||
| 7193 | /*! | ||
| 7194 | * @addtogroup FLASH_Register_Masks FLASH Register Masks | ||
| 7195 | * @{ | ||
| 7196 | */ | ||
| 7197 | |||
| 7198 | /*! @name CMD - command register */ | ||
| 7199 | /*! @{ */ | ||
| 7200 | #define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) | ||
| 7201 | #define FLASH_CMD_CMD_SHIFT (0U) | ||
| 7202 | /*! CMD - command register. | ||
| 7203 | */ | ||
| 7204 | #define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) | ||
| 7205 | /*! @} */ | ||
| 7206 | |||
| 7207 | /*! @name EVENT - event register */ | ||
| 7208 | /*! @{ */ | ||
| 7209 | #define FLASH_EVENT_RST_MASK (0x1U) | ||
| 7210 | #define FLASH_EVENT_RST_SHIFT (0U) | ||
| 7211 | /*! RST - When bit is set, the controller and flash are reset. | ||
| 7212 | */ | ||
| 7213 | #define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) | ||
| 7214 | #define FLASH_EVENT_WAKEUP_MASK (0x2U) | ||
| 7215 | #define FLASH_EVENT_WAKEUP_SHIFT (1U) | ||
| 7216 | /*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. | ||
| 7217 | */ | ||
| 7218 | #define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) | ||
| 7219 | #define FLASH_EVENT_ABORT_MASK (0x4U) | ||
| 7220 | #define FLASH_EVENT_ABORT_SHIFT (2U) | ||
| 7221 | /*! ABORT - When bit is set, a running program/erase command is aborted. | ||
| 7222 | */ | ||
| 7223 | #define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) | ||
| 7224 | /*! @} */ | ||
| 7225 | |||
| 7226 | /*! @name STARTA - start (or only) address for next flash command */ | ||
| 7227 | /*! @{ */ | ||
| 7228 | #define FLASH_STARTA_STARTA_MASK (0x3FFFFU) | ||
| 7229 | #define FLASH_STARTA_STARTA_SHIFT (0U) | ||
| 7230 | /*! STARTA - Address / Start address for commands that take an address (range) as a parameter. | ||
| 7231 | */ | ||
| 7232 | #define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) | ||
| 7233 | /*! @} */ | ||
| 7234 | |||
| 7235 | /*! @name STOPA - end address for next flash command, if command operates on address ranges */ | ||
| 7236 | /*! @{ */ | ||
| 7237 | #define FLASH_STOPA_STOPA_MASK (0x3FFFFU) | ||
| 7238 | #define FLASH_STOPA_STOPA_SHIFT (0U) | ||
| 7239 | /*! STOPA - Stop address for commands that take an address range as a parameter (the word specified | ||
| 7240 | * by STOPA is included in the address range). | ||
| 7241 | */ | ||
| 7242 | #define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) | ||
| 7243 | /*! @} */ | ||
| 7244 | |||
| 7245 | /*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ | ||
| 7246 | /*! @{ */ | ||
| 7247 | #define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) | ||
| 7248 | #define FLASH_DATAW_DATAW_SHIFT (0U) | ||
| 7249 | #define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) | ||
| 7250 | /*! @} */ | ||
| 7251 | |||
| 7252 | /* The count of FLASH_DATAW */ | ||
| 7253 | #define FLASH_DATAW_COUNT (4U) | ||
| 7254 | |||
| 7255 | /*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ | ||
| 7256 | /*! @{ */ | ||
| 7257 | #define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) | ||
| 7258 | #define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) | ||
| 7259 | /*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 7260 | */ | ||
| 7261 | #define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) | ||
| 7262 | #define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) | ||
| 7263 | #define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) | ||
| 7264 | /*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 7265 | */ | ||
| 7266 | #define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) | ||
| 7267 | #define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) | ||
| 7268 | #define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) | ||
| 7269 | /*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 7270 | */ | ||
| 7271 | #define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) | ||
| 7272 | #define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 7273 | #define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 7274 | /*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. | ||
| 7275 | */ | ||
| 7276 | #define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) | ||
| 7277 | /*! @} */ | ||
| 7278 | |||
| 7279 | /*! @name INT_SET_ENABLE - Set interrupt enable bits */ | ||
| 7280 | /*! @{ */ | ||
| 7281 | #define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) | ||
| 7282 | #define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) | ||
| 7283 | /*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 7284 | */ | ||
| 7285 | #define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) | ||
| 7286 | #define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) | ||
| 7287 | #define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) | ||
| 7288 | /*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 7289 | */ | ||
| 7290 | #define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) | ||
| 7291 | #define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) | ||
| 7292 | #define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) | ||
| 7293 | /*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 7294 | */ | ||
| 7295 | #define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) | ||
| 7296 | #define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 7297 | #define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 7298 | /*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. | ||
| 7299 | */ | ||
| 7300 | #define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) | ||
| 7301 | /*! @} */ | ||
| 7302 | |||
| 7303 | /*! @name INT_STATUS - Interrupt status bits */ | ||
| 7304 | /*! @{ */ | ||
| 7305 | #define FLASH_INT_STATUS_FAIL_MASK (0x1U) | ||
| 7306 | #define FLASH_INT_STATUS_FAIL_SHIFT (0U) | ||
| 7307 | /*! FAIL - This status bit is set if execution of a (legal) command failed. | ||
| 7308 | */ | ||
| 7309 | #define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) | ||
| 7310 | #define FLASH_INT_STATUS_ERR_MASK (0x2U) | ||
| 7311 | #define FLASH_INT_STATUS_ERR_SHIFT (1U) | ||
| 7312 | /*! ERR - This status bit is set if execution of an illegal command is detected. | ||
| 7313 | */ | ||
| 7314 | #define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) | ||
| 7315 | #define FLASH_INT_STATUS_DONE_MASK (0x4U) | ||
| 7316 | #define FLASH_INT_STATUS_DONE_SHIFT (2U) | ||
| 7317 | /*! DONE - This status bit is set at the end of command execution. | ||
| 7318 | */ | ||
| 7319 | #define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) | ||
| 7320 | #define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) | ||
| 7321 | #define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) | ||
| 7322 | /*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested | ||
| 7323 | * read, or a speculative read, or reads performed by a controller command), a correctable or | ||
| 7324 | * uncorrectable error is detected by ECC decoding logic. | ||
| 7325 | */ | ||
| 7326 | #define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) | ||
| 7327 | /*! @} */ | ||
| 7328 | |||
| 7329 | /*! @name INT_ENABLE - Interrupt enable bits */ | ||
| 7330 | /*! @{ */ | ||
| 7331 | #define FLASH_INT_ENABLE_FAIL_MASK (0x1U) | ||
| 7332 | #define FLASH_INT_ENABLE_FAIL_SHIFT (0U) | ||
| 7333 | /*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 7334 | */ | ||
| 7335 | #define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) | ||
| 7336 | #define FLASH_INT_ENABLE_ERR_MASK (0x2U) | ||
| 7337 | #define FLASH_INT_ENABLE_ERR_SHIFT (1U) | ||
| 7338 | /*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 7339 | */ | ||
| 7340 | #define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) | ||
| 7341 | #define FLASH_INT_ENABLE_DONE_MASK (0x4U) | ||
| 7342 | #define FLASH_INT_ENABLE_DONE_SHIFT (2U) | ||
| 7343 | /*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 7344 | */ | ||
| 7345 | #define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) | ||
| 7346 | #define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) | ||
| 7347 | #define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) | ||
| 7348 | /*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. | ||
| 7349 | */ | ||
| 7350 | #define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) | ||
| 7351 | /*! @} */ | ||
| 7352 | |||
| 7353 | /*! @name INT_CLR_STATUS - Clear interrupt status bits */ | ||
| 7354 | /*! @{ */ | ||
| 7355 | #define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) | ||
| 7356 | #define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) | ||
| 7357 | /*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 7358 | */ | ||
| 7359 | #define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) | ||
| 7360 | #define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) | ||
| 7361 | #define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) | ||
| 7362 | /*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 7363 | */ | ||
| 7364 | #define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) | ||
| 7365 | #define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) | ||
| 7366 | #define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) | ||
| 7367 | /*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 7368 | */ | ||
| 7369 | #define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) | ||
| 7370 | #define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) | ||
| 7371 | #define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) | ||
| 7372 | /*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. | ||
| 7373 | */ | ||
| 7374 | #define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) | ||
| 7375 | /*! @} */ | ||
| 7376 | |||
| 7377 | /*! @name INT_SET_STATUS - Set interrupt status bits */ | ||
| 7378 | /*! @{ */ | ||
| 7379 | #define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) | ||
| 7380 | #define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) | ||
| 7381 | /*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 7382 | */ | ||
| 7383 | #define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) | ||
| 7384 | #define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) | ||
| 7385 | #define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) | ||
| 7386 | /*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 7387 | */ | ||
| 7388 | #define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) | ||
| 7389 | #define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) | ||
| 7390 | #define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) | ||
| 7391 | /*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 7392 | */ | ||
| 7393 | #define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) | ||
| 7394 | #define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) | ||
| 7395 | #define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) | ||
| 7396 | /*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. | ||
| 7397 | */ | ||
| 7398 | #define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) | ||
| 7399 | /*! @} */ | ||
| 7400 | |||
| 7401 | /*! @name MODULE_ID - Controller+Memory module identification */ | ||
| 7402 | /*! @{ */ | ||
| 7403 | #define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) | ||
| 7404 | #define FLASH_MODULE_ID_APERTURE_SHIFT (0U) | ||
| 7405 | /*! APERTURE - Aperture i. | ||
| 7406 | */ | ||
| 7407 | #define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) | ||
| 7408 | #define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) | ||
| 7409 | #define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) | ||
| 7410 | /*! MINOR_REV - Minor revision i. | ||
| 7411 | */ | ||
| 7412 | #define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) | ||
| 7413 | #define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) | ||
| 7414 | #define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) | ||
| 7415 | /*! MAJOR_REV - Major revision i. | ||
| 7416 | */ | ||
| 7417 | #define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) | ||
| 7418 | #define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) | ||
| 7419 | #define FLASH_MODULE_ID_ID_SHIFT (16U) | ||
| 7420 | /*! ID - Identifier. | ||
| 7421 | */ | ||
| 7422 | #define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) | ||
| 7423 | /*! @} */ | ||
| 7424 | |||
| 7425 | |||
| 7426 | /*! | ||
| 7427 | * @} | ||
| 7428 | */ /* end of group FLASH_Register_Masks */ | ||
| 7429 | |||
| 7430 | |||
| 7431 | /* FLASH - Peripheral instance base addresses */ | ||
| 7432 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 7433 | /** Peripheral FLASH base address */ | ||
| 7434 | #define FLASH_BASE (0x50034000u) | ||
| 7435 | /** Peripheral FLASH base address */ | ||
| 7436 | #define FLASH_BASE_NS (0x40034000u) | ||
| 7437 | /** Peripheral FLASH base pointer */ | ||
| 7438 | #define FLASH ((FLASH_Type *)FLASH_BASE) | ||
| 7439 | /** Peripheral FLASH base pointer */ | ||
| 7440 | #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) | ||
| 7441 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 7442 | #define FLASH_BASE_ADDRS { FLASH_BASE } | ||
| 7443 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 7444 | #define FLASH_BASE_PTRS { FLASH } | ||
| 7445 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 7446 | #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } | ||
| 7447 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 7448 | #define FLASH_BASE_PTRS_NS { FLASH_NS } | ||
| 7449 | #else | ||
| 7450 | /** Peripheral FLASH base address */ | ||
| 7451 | #define FLASH_BASE (0x40034000u) | ||
| 7452 | /** Peripheral FLASH base pointer */ | ||
| 7453 | #define FLASH ((FLASH_Type *)FLASH_BASE) | ||
| 7454 | /** Array initializer of FLASH peripheral base addresses */ | ||
| 7455 | #define FLASH_BASE_ADDRS { FLASH_BASE } | ||
| 7456 | /** Array initializer of FLASH peripheral base pointers */ | ||
| 7457 | #define FLASH_BASE_PTRS { FLASH } | ||
| 7458 | #endif | ||
| 7459 | |||
| 7460 | /*! | ||
| 7461 | * @} | ||
| 7462 | */ /* end of group FLASH_Peripheral_Access_Layer */ | ||
| 7463 | |||
| 7464 | |||
| 7465 | /* ---------------------------------------------------------------------------- | ||
| 7466 | -- FLASH_CFPA Peripheral Access Layer | ||
| 7467 | ---------------------------------------------------------------------------- */ | ||
| 7468 | |||
| 7469 | /*! | ||
| 7470 | * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer | ||
| 7471 | * @{ | ||
| 7472 | */ | ||
| 7473 | |||
| 7474 | /** FLASH_CFPA - Register Layout Typedef */ | ||
| 7475 | typedef struct { | ||
| 7476 | __IO uint32_t HEADER; /**< ., offset: 0x0 */ | ||
| 7477 | __IO uint32_t VERSION; /**< ., offset: 0x4 */ | ||
| 7478 | __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ | ||
| 7479 | __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ | ||
| 7480 | __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ | ||
| 7481 | uint8_t RESERVED_0[4]; | ||
| 7482 | __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ | ||
| 7483 | __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ | ||
| 7484 | __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ | ||
| 7485 | __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ | ||
| 7486 | __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ | ||
| 7487 | __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ | ||
| 7488 | union { /* offset: 0x30 */ | ||
| 7489 | __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ | ||
| 7490 | struct { /* offset: 0x30 */ | ||
| 7491 | __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ | ||
| 7492 | __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ | ||
| 7493 | __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ | ||
| 7494 | } PRINCE_REGION0_IV_CODE_CORE; | ||
| 7495 | }; | ||
| 7496 | union { /* offset: 0x68 */ | ||
| 7497 | __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ | ||
| 7498 | struct { /* offset: 0x68 */ | ||
| 7499 | __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ | ||
| 7500 | __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ | ||
| 7501 | __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ | ||
| 7502 | } PRINCE_REGION1_IV_CODE_CORE; | ||
| 7503 | }; | ||
| 7504 | union { /* offset: 0xA0 */ | ||
| 7505 | __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ | ||
| 7506 | struct { /* offset: 0xA0 */ | ||
| 7507 | __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ | ||
| 7508 | __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ | ||
| 7509 | __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ | ||
| 7510 | } PRINCE_REGION2_IV_CODE_CORE; | ||
| 7511 | }; | ||
| 7512 | uint8_t RESERVED_1[40]; | ||
| 7513 | __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ | ||
| 7514 | __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ | ||
| 7515 | } FLASH_CFPA_Type; | ||
| 7516 | |||
| 7517 | /* ---------------------------------------------------------------------------- | ||
| 7518 | -- FLASH_CFPA Register Masks | ||
| 7519 | ---------------------------------------------------------------------------- */ | ||
| 7520 | |||
| 7521 | /*! | ||
| 7522 | * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks | ||
| 7523 | * @{ | ||
| 7524 | */ | ||
| 7525 | |||
| 7526 | /*! @name HEADER - . */ | ||
| 7527 | /*! @{ */ | ||
| 7528 | #define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) | ||
| 7529 | #define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) | ||
| 7530 | /*! FIELD - . | ||
| 7531 | */ | ||
| 7532 | #define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) | ||
| 7533 | /*! @} */ | ||
| 7534 | |||
| 7535 | /*! @name VERSION - . */ | ||
| 7536 | /*! @{ */ | ||
| 7537 | #define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 7538 | #define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) | ||
| 7539 | /*! FIELD - . | ||
| 7540 | */ | ||
| 7541 | #define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) | ||
| 7542 | /*! @} */ | ||
| 7543 | |||
| 7544 | /*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ | ||
| 7545 | /*! @{ */ | ||
| 7546 | #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 7547 | #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) | ||
| 7548 | /*! FIELD - . | ||
| 7549 | */ | ||
| 7550 | #define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) | ||
| 7551 | /*! @} */ | ||
| 7552 | |||
| 7553 | /*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ | ||
| 7554 | /*! @{ */ | ||
| 7555 | #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) | ||
| 7556 | #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) | ||
| 7557 | /*! FIELD - . | ||
| 7558 | */ | ||
| 7559 | #define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) | ||
| 7560 | /*! @} */ | ||
| 7561 | |||
| 7562 | /*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ | ||
| 7563 | /*! @{ */ | ||
| 7564 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7565 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) | ||
| 7566 | /*! FIELD - . | ||
| 7567 | */ | ||
| 7568 | #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) | ||
| 7569 | /*! @} */ | ||
| 7570 | |||
| 7571 | /*! @name ROTKH_REVOKE - . */ | ||
| 7572 | /*! @{ */ | ||
| 7573 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) | ||
| 7574 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) | ||
| 7575 | /*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 7576 | */ | ||
| 7577 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) | ||
| 7578 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) | ||
| 7579 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) | ||
| 7580 | /*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 7581 | */ | ||
| 7582 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) | ||
| 7583 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) | ||
| 7584 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) | ||
| 7585 | /*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked | ||
| 7586 | */ | ||
| 7587 | #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) | ||
| 7588 | /*! @} */ | ||
| 7589 | |||
| 7590 | /*! @name VENDOR_USAGE - . */ | ||
| 7591 | /*! @{ */ | ||
| 7592 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) | ||
| 7593 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) | ||
| 7594 | /*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. | ||
| 7595 | */ | ||
| 7596 | #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) | ||
| 7597 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 7598 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) | ||
| 7599 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 7600 | */ | ||
| 7601 | #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) | ||
| 7602 | /*! @} */ | ||
| 7603 | |||
| 7604 | /*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ | ||
| 7605 | /*! @{ */ | ||
| 7606 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) | ||
| 7607 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) | ||
| 7608 | /*! NIDEN - Non Secure non-invasive debug enable | ||
| 7609 | * 0b0..Use DAP to enable | ||
| 7610 | * 0b1..Fixed state | ||
| 7611 | */ | ||
| 7612 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) | ||
| 7613 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) | ||
| 7614 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) | ||
| 7615 | /*! DBGEN - Non Secure debug enable | ||
| 7616 | * 0b0..Use DAP to enable | ||
| 7617 | * 0b1..Fixed state | ||
| 7618 | */ | ||
| 7619 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) | ||
| 7620 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) | ||
| 7621 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) | ||
| 7622 | /*! SPNIDEN - Secure non-invasive debug enable | ||
| 7623 | * 0b0..Use DAP to enable | ||
| 7624 | * 0b1..Fixed state | ||
| 7625 | */ | ||
| 7626 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) | ||
| 7627 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) | ||
| 7628 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) | ||
| 7629 | /*! SPIDEN - Secure invasive debug enable | ||
| 7630 | * 0b0..Use DAP to enable | ||
| 7631 | * 0b1..Fixed state | ||
| 7632 | */ | ||
| 7633 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) | ||
| 7634 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) | ||
| 7635 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) | ||
| 7636 | /*! TAPEN - JTAG TAP enable | ||
| 7637 | * 0b0..Use DAP to enable | ||
| 7638 | * 0b1..Fixed state | ||
| 7639 | */ | ||
| 7640 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) | ||
| 7641 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) | ||
| 7642 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) | ||
| 7643 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable | ||
| 7644 | * 0b0..Use DAP to enable | ||
| 7645 | * 0b1..Fixed state | ||
| 7646 | */ | ||
| 7647 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) | ||
| 7648 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) | ||
| 7649 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) | ||
| 7650 | /*! ISP_CMD_EN - ISP Boot Command enable | ||
| 7651 | * 0b0..Use DAP to enable | ||
| 7652 | * 0b1..Fixed state | ||
| 7653 | */ | ||
| 7654 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) | ||
| 7655 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) | ||
| 7656 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) | ||
| 7657 | /*! FA_CMD_EN - FA Command enable | ||
| 7658 | * 0b0..Use DAP to enable | ||
| 7659 | * 0b1..Fixed state | ||
| 7660 | */ | ||
| 7661 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) | ||
| 7662 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) | ||
| 7663 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) | ||
| 7664 | /*! ME_CMD_EN - Flash Mass Erase Command enable | ||
| 7665 | * 0b0..Use DAP to enable | ||
| 7666 | * 0b1..Fixed state | ||
| 7667 | */ | ||
| 7668 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) | ||
| 7669 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) | ||
| 7670 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) | ||
| 7671 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable | ||
| 7672 | * 0b0..Use DAP to enable | ||
| 7673 | * 0b1..Fixed state | ||
| 7674 | */ | ||
| 7675 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) | ||
| 7676 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) | ||
| 7677 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) | ||
| 7678 | /*! UUID_CHECK - Enforce UUID match during Debug authentication. | ||
| 7679 | */ | ||
| 7680 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) | ||
| 7681 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 7682 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) | ||
| 7683 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 7684 | */ | ||
| 7685 | #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) | ||
| 7686 | /*! @} */ | ||
| 7687 | |||
| 7688 | /*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ | ||
| 7689 | /*! @{ */ | ||
| 7690 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) | ||
| 7691 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) | ||
| 7692 | /*! NIDEN - Non Secure non-invasive debug fixed state | ||
| 7693 | * 0b0..Disable | ||
| 7694 | * 0b1..Enable | ||
| 7695 | */ | ||
| 7696 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) | ||
| 7697 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) | ||
| 7698 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) | ||
| 7699 | /*! DBGEN - Non Secure debug fixed state | ||
| 7700 | * 0b0..Disable | ||
| 7701 | * 0b1..Enable | ||
| 7702 | */ | ||
| 7703 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) | ||
| 7704 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) | ||
| 7705 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) | ||
| 7706 | /*! SPNIDEN - Secure non-invasive debug fixed state | ||
| 7707 | * 0b0..Disable | ||
| 7708 | * 0b1..Enable | ||
| 7709 | */ | ||
| 7710 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) | ||
| 7711 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) | ||
| 7712 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) | ||
| 7713 | /*! SPIDEN - Secure invasive debug fixed state | ||
| 7714 | * 0b0..Disable | ||
| 7715 | * 0b1..Enable | ||
| 7716 | */ | ||
| 7717 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) | ||
| 7718 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) | ||
| 7719 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) | ||
| 7720 | /*! TAPEN - JTAG TAP fixed state | ||
| 7721 | * 0b0..Disable | ||
| 7722 | * 0b1..Enable | ||
| 7723 | */ | ||
| 7724 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) | ||
| 7725 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) | ||
| 7726 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) | ||
| 7727 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state | ||
| 7728 | * 0b0..Disable | ||
| 7729 | * 0b1..Enable | ||
| 7730 | */ | ||
| 7731 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) | ||
| 7732 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) | ||
| 7733 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) | ||
| 7734 | /*! ISP_CMD_EN - ISP Boot Command fixed state | ||
| 7735 | * 0b0..Disable | ||
| 7736 | * 0b1..Enable | ||
| 7737 | */ | ||
| 7738 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) | ||
| 7739 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) | ||
| 7740 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) | ||
| 7741 | /*! FA_CMD_EN - FA Command fixed state | ||
| 7742 | * 0b0..Disable | ||
| 7743 | * 0b1..Enable | ||
| 7744 | */ | ||
| 7745 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) | ||
| 7746 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) | ||
| 7747 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) | ||
| 7748 | /*! ME_CMD_EN - Flash Mass Erase Command fixed state | ||
| 7749 | * 0b0..Disable | ||
| 7750 | * 0b1..Enable | ||
| 7751 | */ | ||
| 7752 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) | ||
| 7753 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) | ||
| 7754 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) | ||
| 7755 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state | ||
| 7756 | * 0b0..Disable | ||
| 7757 | * 0b1..Enable | ||
| 7758 | */ | ||
| 7759 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) | ||
| 7760 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 7761 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) | ||
| 7762 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 7763 | */ | ||
| 7764 | #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) | ||
| 7765 | /*! @} */ | ||
| 7766 | |||
| 7767 | /*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ | ||
| 7768 | /*! @{ */ | ||
| 7769 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7770 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) | ||
| 7771 | /*! FIELD - . | ||
| 7772 | */ | ||
| 7773 | #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) | ||
| 7774 | /*! @} */ | ||
| 7775 | |||
| 7776 | /*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ | ||
| 7777 | /*! @{ */ | ||
| 7778 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) | ||
| 7779 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) | ||
| 7780 | /*! FIELD - . | ||
| 7781 | */ | ||
| 7782 | #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) | ||
| 7783 | /*! @} */ | ||
| 7784 | |||
| 7785 | /*! @name PRINCE_REGION0_IV_CODE - . */ | ||
| 7786 | /*! @{ */ | ||
| 7787 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7788 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) | ||
| 7789 | /*! FIELD - . | ||
| 7790 | */ | ||
| 7791 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) | ||
| 7792 | /*! @} */ | ||
| 7793 | |||
| 7794 | /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ | ||
| 7795 | #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) | ||
| 7796 | |||
| 7797 | /*! @name PRINCE_REGION0_IV_HEADER0 - . */ | ||
| 7798 | /*! @{ */ | ||
| 7799 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7800 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 7801 | /*! FIELD - . | ||
| 7802 | */ | ||
| 7803 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) | ||
| 7804 | /*! @} */ | ||
| 7805 | |||
| 7806 | /*! @name PRINCE_REGION0_IV_HEADER1 - . */ | ||
| 7807 | /*! @{ */ | ||
| 7808 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 7809 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 7810 | /*! TYPE - . | ||
| 7811 | */ | ||
| 7812 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) | ||
| 7813 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 7814 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 7815 | /*! INDEX - . | ||
| 7816 | */ | ||
| 7817 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) | ||
| 7818 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7819 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 7820 | /*! SIZE - . | ||
| 7821 | */ | ||
| 7822 | #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) | ||
| 7823 | /*! @} */ | ||
| 7824 | |||
| 7825 | /*! @name PRINCE_REGION0_IV_BODY - . */ | ||
| 7826 | /*! @{ */ | ||
| 7827 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7828 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) | ||
| 7829 | /*! FIELD - . | ||
| 7830 | */ | ||
| 7831 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) | ||
| 7832 | /*! @} */ | ||
| 7833 | |||
| 7834 | /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ | ||
| 7835 | #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) | ||
| 7836 | |||
| 7837 | /*! @name PRINCE_REGION1_IV_CODE - . */ | ||
| 7838 | /*! @{ */ | ||
| 7839 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7840 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) | ||
| 7841 | /*! FIELD - . | ||
| 7842 | */ | ||
| 7843 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) | ||
| 7844 | /*! @} */ | ||
| 7845 | |||
| 7846 | /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ | ||
| 7847 | #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) | ||
| 7848 | |||
| 7849 | /*! @name PRINCE_REGION1_IV_HEADER0 - . */ | ||
| 7850 | /*! @{ */ | ||
| 7851 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7852 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 7853 | /*! FIELD - . | ||
| 7854 | */ | ||
| 7855 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) | ||
| 7856 | /*! @} */ | ||
| 7857 | |||
| 7858 | /*! @name PRINCE_REGION1_IV_HEADER1 - . */ | ||
| 7859 | /*! @{ */ | ||
| 7860 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 7861 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 7862 | /*! TYPE - . | ||
| 7863 | */ | ||
| 7864 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) | ||
| 7865 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 7866 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 7867 | /*! INDEX - . | ||
| 7868 | */ | ||
| 7869 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) | ||
| 7870 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7871 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 7872 | /*! SIZE - . | ||
| 7873 | */ | ||
| 7874 | #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) | ||
| 7875 | /*! @} */ | ||
| 7876 | |||
| 7877 | /*! @name PRINCE_REGION1_IV_BODY - . */ | ||
| 7878 | /*! @{ */ | ||
| 7879 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7880 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) | ||
| 7881 | /*! FIELD - . | ||
| 7882 | */ | ||
| 7883 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) | ||
| 7884 | /*! @} */ | ||
| 7885 | |||
| 7886 | /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ | ||
| 7887 | #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) | ||
| 7888 | |||
| 7889 | /*! @name PRINCE_REGION2_IV_CODE - . */ | ||
| 7890 | /*! @{ */ | ||
| 7891 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 7892 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) | ||
| 7893 | /*! FIELD - . | ||
| 7894 | */ | ||
| 7895 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) | ||
| 7896 | /*! @} */ | ||
| 7897 | |||
| 7898 | /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ | ||
| 7899 | #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) | ||
| 7900 | |||
| 7901 | /*! @name PRINCE_REGION2_IV_HEADER0 - . */ | ||
| 7902 | /*! @{ */ | ||
| 7903 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 7904 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) | ||
| 7905 | /*! FIELD - . | ||
| 7906 | */ | ||
| 7907 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) | ||
| 7908 | /*! @} */ | ||
| 7909 | |||
| 7910 | /*! @name PRINCE_REGION2_IV_HEADER1 - . */ | ||
| 7911 | /*! @{ */ | ||
| 7912 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) | ||
| 7913 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) | ||
| 7914 | /*! TYPE - . | ||
| 7915 | */ | ||
| 7916 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) | ||
| 7917 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) | ||
| 7918 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) | ||
| 7919 | /*! INDEX - . | ||
| 7920 | */ | ||
| 7921 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) | ||
| 7922 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 7923 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) | ||
| 7924 | /*! SIZE - . | ||
| 7925 | */ | ||
| 7926 | #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) | ||
| 7927 | /*! @} */ | ||
| 7928 | |||
| 7929 | /*! @name PRINCE_REGION2_IV_BODY - . */ | ||
| 7930 | /*! @{ */ | ||
| 7931 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 7932 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) | ||
| 7933 | /*! FIELD - . | ||
| 7934 | */ | ||
| 7935 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) | ||
| 7936 | /*! @} */ | ||
| 7937 | |||
| 7938 | /* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ | ||
| 7939 | #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) | ||
| 7940 | |||
| 7941 | /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ | ||
| 7942 | /*! @{ */ | ||
| 7943 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) | ||
| 7944 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) | ||
| 7945 | /*! FIELD - . | ||
| 7946 | */ | ||
| 7947 | #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) | ||
| 7948 | /*! @} */ | ||
| 7949 | |||
| 7950 | /* The count of FLASH_CFPA_CUSTOMER_DEFINED */ | ||
| 7951 | #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) | ||
| 7952 | |||
| 7953 | /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ | ||
| 7954 | /*! @{ */ | ||
| 7955 | #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) | ||
| 7956 | #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) | ||
| 7957 | /*! FIELD - . | ||
| 7958 | */ | ||
| 7959 | #define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) | ||
| 7960 | /*! @} */ | ||
| 7961 | |||
| 7962 | /* The count of FLASH_CFPA_SHA256_DIGEST */ | ||
| 7963 | #define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) | ||
| 7964 | |||
| 7965 | |||
| 7966 | /*! | ||
| 7967 | * @} | ||
| 7968 | */ /* end of group FLASH_CFPA_Register_Masks */ | ||
| 7969 | |||
| 7970 | |||
| 7971 | /* FLASH_CFPA - Peripheral instance base addresses */ | ||
| 7972 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 7973 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 7974 | #define FLASH_CFPA0_BASE (0x1003E000u) | ||
| 7975 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 7976 | #define FLASH_CFPA0_BASE_NS (0x3E000u) | ||
| 7977 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 7978 | #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) | ||
| 7979 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 7980 | #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) | ||
| 7981 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 7982 | #define FLASH_CFPA1_BASE (0x1003E200u) | ||
| 7983 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 7984 | #define FLASH_CFPA1_BASE_NS (0x3E200u) | ||
| 7985 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 7986 | #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) | ||
| 7987 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 7988 | #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) | ||
| 7989 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 7990 | #define FLASH_CFPA_SCRATCH_BASE (0x1003DE00u) | ||
| 7991 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 7992 | #define FLASH_CFPA_SCRATCH_BASE_NS (0x3DE00u) | ||
| 7993 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 7994 | #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) | ||
| 7995 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 7996 | #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) | ||
| 7997 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 7998 | #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } | ||
| 7999 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 8000 | #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } | ||
| 8001 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 8002 | #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } | ||
| 8003 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 8004 | #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } | ||
| 8005 | #else | ||
| 8006 | /** Peripheral FLASH_CFPA0 base address */ | ||
| 8007 | #define FLASH_CFPA0_BASE (0x3E000u) | ||
| 8008 | /** Peripheral FLASH_CFPA0 base pointer */ | ||
| 8009 | #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) | ||
| 8010 | /** Peripheral FLASH_CFPA1 base address */ | ||
| 8011 | #define FLASH_CFPA1_BASE (0x3E200u) | ||
| 8012 | /** Peripheral FLASH_CFPA1 base pointer */ | ||
| 8013 | #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) | ||
| 8014 | /** Peripheral FLASH_CFPA_SCRATCH base address */ | ||
| 8015 | #define FLASH_CFPA_SCRATCH_BASE (0x3DE00u) | ||
| 8016 | /** Peripheral FLASH_CFPA_SCRATCH base pointer */ | ||
| 8017 | #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) | ||
| 8018 | /** Array initializer of FLASH_CFPA peripheral base addresses */ | ||
| 8019 | #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } | ||
| 8020 | /** Array initializer of FLASH_CFPA peripheral base pointers */ | ||
| 8021 | #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } | ||
| 8022 | #endif | ||
| 8023 | |||
| 8024 | /*! | ||
| 8025 | * @} | ||
| 8026 | */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ | ||
| 8027 | |||
| 8028 | |||
| 8029 | /* ---------------------------------------------------------------------------- | ||
| 8030 | -- FLASH_CMPA Peripheral Access Layer | ||
| 8031 | ---------------------------------------------------------------------------- */ | ||
| 8032 | |||
| 8033 | /*! | ||
| 8034 | * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer | ||
| 8035 | * @{ | ||
| 8036 | */ | ||
| 8037 | |||
| 8038 | /** FLASH_CMPA - Register Layout Typedef */ | ||
| 8039 | typedef struct { | ||
| 8040 | __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ | ||
| 8041 | __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ | ||
| 8042 | __IO uint32_t USB_ID; /**< ., offset: 0x8 */ | ||
| 8043 | __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ | ||
| 8044 | __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */ | ||
| 8045 | __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */ | ||
| 8046 | __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */ | ||
| 8047 | __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ | ||
| 8048 | __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ | ||
| 8049 | __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ | ||
| 8050 | __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ | ||
| 8051 | __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ | ||
| 8052 | __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ | ||
| 8053 | __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ | ||
| 8054 | __IO uint32_t FLASH_REMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x38 */ | ||
| 8055 | __IO uint32_t FLASH_REMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x3C */ | ||
| 8056 | uint8_t RESERVED_0[16]; | ||
| 8057 | __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ | ||
| 8058 | uint8_t RESERVED_1[144]; | ||
| 8059 | __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ | ||
| 8060 | __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ | ||
| 8061 | } FLASH_CMPA_Type; | ||
| 8062 | |||
| 8063 | /* ---------------------------------------------------------------------------- | ||
| 8064 | -- FLASH_CMPA Register Masks | ||
| 8065 | ---------------------------------------------------------------------------- */ | ||
| 8066 | |||
| 8067 | /*! | ||
| 8068 | * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks | ||
| 8069 | * @{ | ||
| 8070 | */ | ||
| 8071 | |||
| 8072 | /*! @name BOOT_CFG - . */ | ||
| 8073 | /*! @{ */ | ||
| 8074 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) | ||
| 8075 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) | ||
| 8076 | /*! DEFAULT_ISP_MODE - Default ISP mode: | ||
| 8077 | * 0b000..Auto ISP | ||
| 8078 | * 0b001..USB_HID_MSC | ||
| 8079 | * 0b010..SPI Slave ISP | ||
| 8080 | * 0b011..I2C Slave ISP | ||
| 8081 | * 0b111..Disable ISP fall through | ||
| 8082 | */ | ||
| 8083 | #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) | ||
| 8084 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) | ||
| 8085 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) | ||
| 8086 | /*! BOOT_SPEED - Core clock: | ||
| 8087 | * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE | ||
| 8088 | * 0b10..48MHz FRO | ||
| 8089 | */ | ||
| 8090 | #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) | ||
| 8091 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) | ||
| 8092 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) | ||
| 8093 | /*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle | ||
| 8094 | * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO | ||
| 8095 | * pin | ||
| 8096 | */ | ||
| 8097 | #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) | ||
| 8098 | /*! @} */ | ||
| 8099 | |||
| 8100 | /*! @name SPI_FLASH_CFG - . */ | ||
| 8101 | /*! @{ */ | ||
| 8102 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) | ||
| 8103 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) | ||
| 8104 | /*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. | ||
| 8105 | */ | ||
| 8106 | #define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) | ||
| 8107 | /*! @} */ | ||
| 8108 | |||
| 8109 | /*! @name USB_ID - . */ | ||
| 8110 | /*! @{ */ | ||
| 8111 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) | ||
| 8112 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) | ||
| 8113 | /*! USB_VENDOR_ID - . | ||
| 8114 | */ | ||
| 8115 | #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) | ||
| 8116 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) | ||
| 8117 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) | ||
| 8118 | /*! USB_PRODUCT_ID - . | ||
| 8119 | */ | ||
| 8120 | #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) | ||
| 8121 | /*! @} */ | ||
| 8122 | |||
| 8123 | /*! @name SDIO_CFG - . */ | ||
| 8124 | /*! @{ */ | ||
| 8125 | #define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) | ||
| 8126 | #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) | ||
| 8127 | /*! FIELD - . | ||
| 8128 | */ | ||
| 8129 | #define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) | ||
| 8130 | /*! @} */ | ||
| 8131 | |||
| 8132 | /*! @name CC_SOCU_PIN - . */ | ||
| 8133 | /*! @{ */ | ||
| 8134 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) | ||
| 8135 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) | ||
| 8136 | /*! NIDEN - Non Secure non-invasive debug enable | ||
| 8137 | * 0b0..Use DAP to enable | ||
| 8138 | * 0b1..Fixed state | ||
| 8139 | */ | ||
| 8140 | #define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) | ||
| 8141 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) | ||
| 8142 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) | ||
| 8143 | /*! DBGEN - Non Secure debug enable | ||
| 8144 | * 0b0..Use DAP to enable | ||
| 8145 | * 0b1..Fixed state | ||
| 8146 | */ | ||
| 8147 | #define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) | ||
| 8148 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) | ||
| 8149 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) | ||
| 8150 | /*! SPNIDEN - Secure non-invasive debug enable | ||
| 8151 | * 0b0..Use DAP to enable | ||
| 8152 | * 0b1..Fixed state | ||
| 8153 | */ | ||
| 8154 | #define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) | ||
| 8155 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) | ||
| 8156 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) | ||
| 8157 | /*! SPIDEN - Secure invasive debug enable | ||
| 8158 | * 0b0..Use DAP to enable | ||
| 8159 | * 0b1..Fixed state | ||
| 8160 | */ | ||
| 8161 | #define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) | ||
| 8162 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) | ||
| 8163 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) | ||
| 8164 | /*! TAPEN - JTAG TAP enable | ||
| 8165 | * 0b0..Use DAP to enable | ||
| 8166 | * 0b1..Fixed state | ||
| 8167 | */ | ||
| 8168 | #define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) | ||
| 8169 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) | ||
| 8170 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) | ||
| 8171 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable | ||
| 8172 | * 0b0..Use DAP to enable | ||
| 8173 | * 0b1..Fixed state | ||
| 8174 | */ | ||
| 8175 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) | ||
| 8176 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) | ||
| 8177 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) | ||
| 8178 | /*! ISP_CMD_EN - ISP Boot Command enable | ||
| 8179 | * 0b0..Use DAP to enable | ||
| 8180 | * 0b1..Fixed state | ||
| 8181 | */ | ||
| 8182 | #define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) | ||
| 8183 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) | ||
| 8184 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) | ||
| 8185 | /*! FA_CMD_EN - FA Command enable | ||
| 8186 | * 0b0..Use DAP to enable | ||
| 8187 | * 0b1..Fixed state | ||
| 8188 | */ | ||
| 8189 | #define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) | ||
| 8190 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) | ||
| 8191 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) | ||
| 8192 | /*! ME_CMD_EN - Flash Mass Erase Command enable | ||
| 8193 | * 0b0..Use DAP to enable | ||
| 8194 | * 0b1..Fixed state | ||
| 8195 | */ | ||
| 8196 | #define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) | ||
| 8197 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) | ||
| 8198 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) | ||
| 8199 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable | ||
| 8200 | * 0b0..Use DAP to enable | ||
| 8201 | * 0b1..Fixed state | ||
| 8202 | */ | ||
| 8203 | #define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) | ||
| 8204 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) | ||
| 8205 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) | ||
| 8206 | /*! UUID_CHECK - Enforce UUID match during Debug authentication. | ||
| 8207 | */ | ||
| 8208 | #define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) | ||
| 8209 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 8210 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) | ||
| 8211 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 8212 | */ | ||
| 8213 | #define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) | ||
| 8214 | /*! @} */ | ||
| 8215 | |||
| 8216 | /*! @name CC_SOCU_DFLT - . */ | ||
| 8217 | /*! @{ */ | ||
| 8218 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) | ||
| 8219 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) | ||
| 8220 | /*! NIDEN - Non Secure non-invasive debug fixed state | ||
| 8221 | * 0b0..Disable | ||
| 8222 | * 0b1..Enable | ||
| 8223 | */ | ||
| 8224 | #define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) | ||
| 8225 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) | ||
| 8226 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) | ||
| 8227 | /*! DBGEN - Non Secure debug fixed state | ||
| 8228 | * 0b0..Disable | ||
| 8229 | * 0b1..Enable | ||
| 8230 | */ | ||
| 8231 | #define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) | ||
| 8232 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) | ||
| 8233 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) | ||
| 8234 | /*! SPNIDEN - Secure non-invasive debug fixed state | ||
| 8235 | * 0b0..Disable | ||
| 8236 | * 0b1..Enable | ||
| 8237 | */ | ||
| 8238 | #define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) | ||
| 8239 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) | ||
| 8240 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) | ||
| 8241 | /*! SPIDEN - Secure invasive debug fixed state | ||
| 8242 | * 0b0..Disable | ||
| 8243 | * 0b1..Enable | ||
| 8244 | */ | ||
| 8245 | #define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) | ||
| 8246 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) | ||
| 8247 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) | ||
| 8248 | /*! TAPEN - JTAG TAP fixed state | ||
| 8249 | * 0b0..Disable | ||
| 8250 | * 0b1..Enable | ||
| 8251 | */ | ||
| 8252 | #define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) | ||
| 8253 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) | ||
| 8254 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) | ||
| 8255 | /*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state | ||
| 8256 | * 0b0..Disable | ||
| 8257 | * 0b1..Enable | ||
| 8258 | */ | ||
| 8259 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) | ||
| 8260 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) | ||
| 8261 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) | ||
| 8262 | /*! ISP_CMD_EN - ISP Boot Command fixed state | ||
| 8263 | * 0b0..Disable | ||
| 8264 | * 0b1..Enable | ||
| 8265 | */ | ||
| 8266 | #define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) | ||
| 8267 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) | ||
| 8268 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) | ||
| 8269 | /*! FA_CMD_EN - FA Command fixed state | ||
| 8270 | * 0b0..Disable | ||
| 8271 | * 0b1..Enable | ||
| 8272 | */ | ||
| 8273 | #define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) | ||
| 8274 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) | ||
| 8275 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) | ||
| 8276 | /*! ME_CMD_EN - Flash Mass Erase Command fixed state | ||
| 8277 | * 0b0..Disable | ||
| 8278 | * 0b1..Enable | ||
| 8279 | */ | ||
| 8280 | #define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) | ||
| 8281 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) | ||
| 8282 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) | ||
| 8283 | /*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state | ||
| 8284 | * 0b0..Disable | ||
| 8285 | * 0b1..Enable | ||
| 8286 | */ | ||
| 8287 | #define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) | ||
| 8288 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) | ||
| 8289 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) | ||
| 8290 | /*! INVERSE_VALUE - inverse value of bits [15:0] | ||
| 8291 | */ | ||
| 8292 | #define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) | ||
| 8293 | /*! @} */ | ||
| 8294 | |||
| 8295 | /*! @name VENDOR_USAGE - . */ | ||
| 8296 | /*! @{ */ | ||
| 8297 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) | ||
| 8298 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) | ||
| 8299 | /*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. | ||
| 8300 | */ | ||
| 8301 | #define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) | ||
| 8302 | /*! @} */ | ||
| 8303 | |||
| 8304 | /*! @name SECURE_BOOT_CFG - . */ | ||
| 8305 | /*! @{ */ | ||
| 8306 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) | ||
| 8307 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) | ||
| 8308 | /*! RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys | ||
| 8309 | */ | ||
| 8310 | #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) | ||
| 8311 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) | ||
| 8312 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) | ||
| 8313 | /*! DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included | ||
| 8314 | */ | ||
| 8315 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) | ||
| 8316 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) | ||
| 8317 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) | ||
| 8318 | /*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included | ||
| 8319 | */ | ||
| 8320 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) | ||
| 8321 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) | ||
| 8322 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) | ||
| 8323 | /*! SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE | ||
| 8324 | */ | ||
| 8325 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) | ||
| 8326 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) | ||
| 8327 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) | ||
| 8328 | /*! TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to | ||
| 8329 | * NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. | ||
| 8330 | */ | ||
| 8331 | #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) | ||
| 8332 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) | ||
| 8333 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) | ||
| 8334 | /*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation | ||
| 8335 | */ | ||
| 8336 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) | ||
| 8337 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) | ||
| 8338 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) | ||
| 8339 | /*! BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet | ||
| 8340 | */ | ||
| 8341 | #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) | ||
| 8342 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) | ||
| 8343 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) | ||
| 8344 | /*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE | ||
| 8345 | */ | ||
| 8346 | #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) | ||
| 8347 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_PSA_BS_CALC_MASK (0x30000U) | ||
| 8348 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_PSA_BS_CALC_SHIFT (16U) | ||
| 8349 | /*! SKIP_PSA_BS_CALC - Skip PSA boot state calculation computation. | ||
| 8350 | */ | ||
| 8351 | #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_PSA_BS_CALC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_PSA_BS_CALC_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_PSA_BS_CALC_MASK) | ||
| 8352 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_NXP_CFG_MASK (0xC0000U) | ||
| 8353 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_NXP_CFG_SHIFT (18U) | ||
| 8354 | /*! PSA_INC_NXP_CFG - Include NXP area in PSA computation. | ||
| 8355 | */ | ||
| 8356 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_NXP_CFG_MASK) | ||
| 8357 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_CUST_CFG_MASK (0x300000U) | ||
| 8358 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_CUST_CFG_SHIFT (20U) | ||
| 8359 | /*! PSA_CUST_CFG - Include Customer factory area (including keys) in PSA computation. | ||
| 8360 | */ | ||
| 8361 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_PSA_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_PSA_CUST_CFG_MASK) | ||
| 8362 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_SEC_EPOCH_MASK (0xC00000U) | ||
| 8363 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_SEC_EPOCH_SHIFT (22U) | ||
| 8364 | /*! PSA_INC_SEC_EPOCH - Include security EPOCH in PSA and PSA_boot state computation as per PSA specification. | ||
| 8365 | */ | ||
| 8366 | #define FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_PSA_INC_SEC_EPOCH_MASK) | ||
| 8367 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) | ||
| 8368 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) | ||
| 8369 | /*! SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, | ||
| 8370 | * 11 - Boot signed images. (internal flash, RSA signed) | ||
| 8371 | */ | ||
| 8372 | #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) | ||
| 8373 | /*! @} */ | ||
| 8374 | |||
| 8375 | /*! @name PRINCE_BASE_ADDR - . */ | ||
| 8376 | /*! @{ */ | ||
| 8377 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) | ||
| 8378 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) | ||
| 8379 | /*! ADDR0_PRG - Programmable portion of the base address of region 0. | ||
| 8380 | */ | ||
| 8381 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) | ||
| 8382 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) | ||
| 8383 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) | ||
| 8384 | /*! ADDR1_PRG - Programmable portion of the base address of region 1. | ||
| 8385 | */ | ||
| 8386 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) | ||
| 8387 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) | ||
| 8388 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) | ||
| 8389 | /*! ADDR2_PRG - Programmable portion of the base address of region 2. | ||
| 8390 | */ | ||
| 8391 | #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) | ||
| 8392 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) | ||
| 8393 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) | ||
| 8394 | /*! LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 8395 | */ | ||
| 8396 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) | ||
| 8397 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) | ||
| 8398 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) | ||
| 8399 | /*! LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 8400 | */ | ||
| 8401 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) | ||
| 8402 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) | ||
| 8403 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) | ||
| 8404 | /*! LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. | ||
| 8405 | */ | ||
| 8406 | #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) | ||
| 8407 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) | ||
| 8408 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) | ||
| 8409 | /*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased | ||
| 8410 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 8411 | */ | ||
| 8412 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) | ||
| 8413 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) | ||
| 8414 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) | ||
| 8415 | /*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased | ||
| 8416 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 8417 | */ | ||
| 8418 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) | ||
| 8419 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) | ||
| 8420 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) | ||
| 8421 | /*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased | ||
| 8422 | * together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. | ||
| 8423 | */ | ||
| 8424 | #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) | ||
| 8425 | /*! @} */ | ||
| 8426 | |||
| 8427 | /*! @name PRINCE_SR_0 - Region 0, sub-region enable */ | ||
| 8428 | /*! @{ */ | ||
| 8429 | #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8430 | #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) | ||
| 8431 | /*! FIELD - . | ||
| 8432 | */ | ||
| 8433 | #define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) | ||
| 8434 | /*! @} */ | ||
| 8435 | |||
| 8436 | /*! @name PRINCE_SR_1 - Region 1, sub-region enable */ | ||
| 8437 | /*! @{ */ | ||
| 8438 | #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) | ||
| 8439 | #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) | ||
| 8440 | /*! FIELD - . | ||
| 8441 | */ | ||
| 8442 | #define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) | ||
| 8443 | /*! @} */ | ||
| 8444 | |||
| 8445 | /*! @name PRINCE_SR_2 - Region 2, sub-region enable */ | ||
| 8446 | /*! @{ */ | ||
| 8447 | #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) | ||
| 8448 | #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) | ||
| 8449 | /*! FIELD - . | ||
| 8450 | */ | ||
| 8451 | #define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) | ||
| 8452 | /*! @} */ | ||
| 8453 | |||
| 8454 | /*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ | ||
| 8455 | /*! @{ */ | ||
| 8456 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) | ||
| 8457 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) | ||
| 8458 | /*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. | ||
| 8459 | */ | ||
| 8460 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) | ||
| 8461 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) | ||
| 8462 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) | ||
| 8463 | /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8464 | */ | ||
| 8465 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) | ||
| 8466 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) | ||
| 8467 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) | ||
| 8468 | /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8469 | */ | ||
| 8470 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) | ||
| 8471 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) | ||
| 8472 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) | ||
| 8473 | /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8474 | */ | ||
| 8475 | #define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) | ||
| 8476 | /*! @} */ | ||
| 8477 | |||
| 8478 | /*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ | ||
| 8479 | /*! @{ */ | ||
| 8480 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) | ||
| 8481 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) | ||
| 8482 | /*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid. | ||
| 8483 | */ | ||
| 8484 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) | ||
| 8485 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) | ||
| 8486 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) | ||
| 8487 | /*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8488 | */ | ||
| 8489 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) | ||
| 8490 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) | ||
| 8491 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) | ||
| 8492 | /*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8493 | */ | ||
| 8494 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) | ||
| 8495 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) | ||
| 8496 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) | ||
| 8497 | /*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. | ||
| 8498 | */ | ||
| 8499 | #define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) | ||
| 8500 | /*! @} */ | ||
| 8501 | |||
| 8502 | /*! @name FLASH_REMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ | ||
| 8503 | /*! @{ */ | ||
| 8504 | #define FLASH_CMPA_FLASH_REMAP_SIZE_FLASH_REMAP_SIZE_MASK (0xFFFFFFFFU) | ||
| 8505 | #define FLASH_CMPA_FLASH_REMAP_SIZE_FLASH_REMAP_SIZE_SHIFT (0U) | ||
| 8506 | /*! FLASH_REMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The | ||
| 8507 | * 12 LSBs are ignored, so the size granularity is 4KB. | ||
| 8508 | */ | ||
| 8509 | #define FLASH_CMPA_FLASH_REMAP_SIZE_FLASH_REMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_SIZE_FLASH_REMAP_SIZE_SHIFT)) & FLASH_CMPA_FLASH_REMAP_SIZE_FLASH_REMAP_SIZE_MASK) | ||
| 8510 | /*! @} */ | ||
| 8511 | |||
| 8512 | /*! @name FLASH_REMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ | ||
| 8513 | /*! @{ */ | ||
| 8514 | #define FLASH_CMPA_FLASH_REMAP_OFFSET_FLASH_REMAP_OFFSET_MASK (0xFFFFFFFFU) | ||
| 8515 | #define FLASH_CMPA_FLASH_REMAP_OFFSET_FLASH_REMAP_OFFSET_SHIFT (0U) | ||
| 8516 | /*! FLASH_REMAP_OFFSET - This 32-bit register contains the offset by which the image is to be | ||
| 8517 | * remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. | ||
| 8518 | */ | ||
| 8519 | #define FLASH_CMPA_FLASH_REMAP_OFFSET_FLASH_REMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_OFFSET_FLASH_REMAP_OFFSET_SHIFT)) & FLASH_CMPA_FLASH_REMAP_OFFSET_FLASH_REMAP_OFFSET_MASK) | ||
| 8520 | /*! @} */ | ||
| 8521 | |||
| 8522 | /*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ | ||
| 8523 | /*! @{ */ | ||
| 8524 | #define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) | ||
| 8525 | #define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) | ||
| 8526 | /*! FIELD - . | ||
| 8527 | */ | ||
| 8528 | #define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) | ||
| 8529 | /*! @} */ | ||
| 8530 | |||
| 8531 | /* The count of FLASH_CMPA_ROTKH */ | ||
| 8532 | #define FLASH_CMPA_ROTKH_COUNT (8U) | ||
| 8533 | |||
| 8534 | /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ | ||
| 8535 | /*! @{ */ | ||
| 8536 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) | ||
| 8537 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) | ||
| 8538 | /*! FIELD - . | ||
| 8539 | */ | ||
| 8540 | #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) | ||
| 8541 | /*! @} */ | ||
| 8542 | |||
| 8543 | /* The count of FLASH_CMPA_CUSTOMER_DEFINED */ | ||
| 8544 | #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) | ||
| 8545 | |||
| 8546 | /*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ | ||
| 8547 | /*! @{ */ | ||
| 8548 | #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) | ||
| 8549 | #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) | ||
| 8550 | /*! FIELD - . | ||
| 8551 | */ | ||
| 8552 | #define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) | ||
| 8553 | /*! @} */ | ||
| 8554 | |||
| 8555 | /* The count of FLASH_CMPA_SHA256_DIGEST */ | ||
| 8556 | #define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) | ||
| 8557 | |||
| 8558 | |||
| 8559 | /*! | ||
| 8560 | * @} | ||
| 8561 | */ /* end of group FLASH_CMPA_Register_Masks */ | ||
| 8562 | |||
| 8563 | |||
| 8564 | /* FLASH_CMPA - Peripheral instance base addresses */ | ||
| 8565 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 8566 | /** Peripheral FLASH_CMPA base address */ | ||
| 8567 | #define FLASH_CMPA_BASE (0x1003E400u) | ||
| 8568 | /** Peripheral FLASH_CMPA base address */ | ||
| 8569 | #define FLASH_CMPA_BASE_NS (0x3E400u) | ||
| 8570 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 8571 | #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) | ||
| 8572 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 8573 | #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) | ||
| 8574 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 8575 | #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } | ||
| 8576 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 8577 | #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } | ||
| 8578 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 8579 | #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } | ||
| 8580 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 8581 | #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } | ||
| 8582 | #else | ||
| 8583 | /** Peripheral FLASH_CMPA base address */ | ||
| 8584 | #define FLASH_CMPA_BASE (0x3E400u) | ||
| 8585 | /** Peripheral FLASH_CMPA base pointer */ | ||
| 8586 | #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) | ||
| 8587 | /** Array initializer of FLASH_CMPA peripheral base addresses */ | ||
| 8588 | #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } | ||
| 8589 | /** Array initializer of FLASH_CMPA peripheral base pointers */ | ||
| 8590 | #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } | ||
| 8591 | #endif | ||
| 8592 | |||
| 8593 | /*! | ||
| 8594 | * @} | ||
| 8595 | */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ | ||
| 8596 | |||
| 8597 | |||
| 8598 | /* ---------------------------------------------------------------------------- | ||
| 8599 | -- FLASH_KEY_STORE Peripheral Access Layer | ||
| 8600 | ---------------------------------------------------------------------------- */ | ||
| 8601 | |||
| 8602 | /*! | ||
| 8603 | * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer | ||
| 8604 | * @{ | ||
| 8605 | */ | ||
| 8606 | |||
| 8607 | /** FLASH_KEY_STORE - Register Layout Typedef */ | ||
| 8608 | typedef struct { | ||
| 8609 | struct { /* offset: 0x0 */ | ||
| 8610 | __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ | ||
| 8611 | __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ | ||
| 8612 | } KEY_STORE_HEADER; | ||
| 8613 | __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ | ||
| 8614 | union { /* offset: 0x4B0 */ | ||
| 8615 | __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ | ||
| 8616 | struct { /* offset: 0x4B0 */ | ||
| 8617 | __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ | ||
| 8618 | __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ | ||
| 8619 | __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ | ||
| 8620 | } SBKEY_KEY_CODE_CORE; | ||
| 8621 | }; | ||
| 8622 | union { /* offset: 0x4E8 */ | ||
| 8623 | __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ | ||
| 8624 | struct { /* offset: 0x4E8 */ | ||
| 8625 | __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ | ||
| 8626 | __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ | ||
| 8627 | __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ | ||
| 8628 | } USER_KEK_KEY_CODE_CORE; | ||
| 8629 | }; | ||
| 8630 | union { /* offset: 0x520 */ | ||
| 8631 | __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ | ||
| 8632 | struct { /* offset: 0x520 */ | ||
| 8633 | __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ | ||
| 8634 | __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ | ||
| 8635 | __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ | ||
| 8636 | } UDS_KEY_CODE_CORE; | ||
| 8637 | }; | ||
| 8638 | union { /* offset: 0x558 */ | ||
| 8639 | __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ | ||
| 8640 | struct { /* offset: 0x558 */ | ||
| 8641 | __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ | ||
| 8642 | __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ | ||
| 8643 | __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ | ||
| 8644 | } PRINCE_REGION0_KEY_CODE_CORE; | ||
| 8645 | }; | ||
| 8646 | union { /* offset: 0x590 */ | ||
| 8647 | __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ | ||
| 8648 | struct { /* offset: 0x590 */ | ||
| 8649 | __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ | ||
| 8650 | __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ | ||
| 8651 | __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ | ||
| 8652 | } PRINCE_REGION1_KEY_CODE_CORE; | ||
| 8653 | }; | ||
| 8654 | union { /* offset: 0x5C8 */ | ||
| 8655 | __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ | ||
| 8656 | struct { /* offset: 0x5C8 */ | ||
| 8657 | __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ | ||
| 8658 | __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ | ||
| 8659 | __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ | ||
| 8660 | } PRINCE_REGION2_KEY_CODE_CORE; | ||
| 8661 | }; | ||
| 8662 | } FLASH_KEY_STORE_Type; | ||
| 8663 | |||
| 8664 | /* ---------------------------------------------------------------------------- | ||
| 8665 | -- FLASH_KEY_STORE Register Masks | ||
| 8666 | ---------------------------------------------------------------------------- */ | ||
| 8667 | |||
| 8668 | /*! | ||
| 8669 | * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks | ||
| 8670 | * @{ | ||
| 8671 | */ | ||
| 8672 | |||
| 8673 | /*! @name HEADER - Valid Key Sore Header : 0x95959595 */ | ||
| 8674 | /*! @{ */ | ||
| 8675 | #define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) | ||
| 8676 | #define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) | ||
| 8677 | /*! FIELD - . | ||
| 8678 | */ | ||
| 8679 | #define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) | ||
| 8680 | /*! @} */ | ||
| 8681 | |||
| 8682 | /*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ | ||
| 8683 | /*! @{ */ | ||
| 8684 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) | ||
| 8685 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) | ||
| 8686 | /*! FIELD - . | ||
| 8687 | */ | ||
| 8688 | #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) | ||
| 8689 | /*! @} */ | ||
| 8690 | |||
| 8691 | /*! @name ACTIVATION_CODE - . */ | ||
| 8692 | /*! @{ */ | ||
| 8693 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8694 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) | ||
| 8695 | /*! FIELD - . | ||
| 8696 | */ | ||
| 8697 | #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) | ||
| 8698 | /*! @} */ | ||
| 8699 | |||
| 8700 | /* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ | ||
| 8701 | #define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) | ||
| 8702 | |||
| 8703 | /*! @name SBKEY_KEY_CODE - . */ | ||
| 8704 | /*! @{ */ | ||
| 8705 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8706 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8707 | /*! FIELD - . | ||
| 8708 | */ | ||
| 8709 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) | ||
| 8710 | /*! @} */ | ||
| 8711 | |||
| 8712 | /* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ | ||
| 8713 | #define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) | ||
| 8714 | |||
| 8715 | /*! @name SBKEY_HEADER0 - . */ | ||
| 8716 | /*! @{ */ | ||
| 8717 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8718 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) | ||
| 8719 | /*! FIELD - . | ||
| 8720 | */ | ||
| 8721 | #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) | ||
| 8722 | /*! @} */ | ||
| 8723 | |||
| 8724 | /*! @name SBKEY_HEADER1 - . */ | ||
| 8725 | /*! @{ */ | ||
| 8726 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) | ||
| 8727 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) | ||
| 8728 | /*! TYPE - . | ||
| 8729 | */ | ||
| 8730 | #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) | ||
| 8731 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) | ||
| 8732 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) | ||
| 8733 | /*! INDEX - . | ||
| 8734 | */ | ||
| 8735 | #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) | ||
| 8736 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8737 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) | ||
| 8738 | /*! SIZE - . | ||
| 8739 | */ | ||
| 8740 | #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) | ||
| 8741 | /*! @} */ | ||
| 8742 | |||
| 8743 | /*! @name SBKEY_BODY - . */ | ||
| 8744 | /*! @{ */ | ||
| 8745 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8746 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) | ||
| 8747 | /*! FIELD - . | ||
| 8748 | */ | ||
| 8749 | #define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) | ||
| 8750 | /*! @} */ | ||
| 8751 | |||
| 8752 | /* The count of FLASH_KEY_STORE_SBKEY_BODY */ | ||
| 8753 | #define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) | ||
| 8754 | |||
| 8755 | /*! @name USER_KEK_KEY_CODE - . */ | ||
| 8756 | /*! @{ */ | ||
| 8757 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8758 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8759 | /*! FIELD - . | ||
| 8760 | */ | ||
| 8761 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) | ||
| 8762 | /*! @} */ | ||
| 8763 | |||
| 8764 | /* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ | ||
| 8765 | #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) | ||
| 8766 | |||
| 8767 | /*! @name USER_KEK_HEADER0 - . */ | ||
| 8768 | /*! @{ */ | ||
| 8769 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8770 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) | ||
| 8771 | /*! FIELD - . | ||
| 8772 | */ | ||
| 8773 | #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) | ||
| 8774 | /*! @} */ | ||
| 8775 | |||
| 8776 | /*! @name USER_KEK_HEADER1 - . */ | ||
| 8777 | /*! @{ */ | ||
| 8778 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) | ||
| 8779 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) | ||
| 8780 | /*! TYPE - . | ||
| 8781 | */ | ||
| 8782 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) | ||
| 8783 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) | ||
| 8784 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) | ||
| 8785 | /*! INDEX - . | ||
| 8786 | */ | ||
| 8787 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) | ||
| 8788 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8789 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) | ||
| 8790 | /*! SIZE - . | ||
| 8791 | */ | ||
| 8792 | #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) | ||
| 8793 | /*! @} */ | ||
| 8794 | |||
| 8795 | /*! @name USER_KEK_BODY - . */ | ||
| 8796 | /*! @{ */ | ||
| 8797 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8798 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) | ||
| 8799 | /*! FIELD - . | ||
| 8800 | */ | ||
| 8801 | #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) | ||
| 8802 | /*! @} */ | ||
| 8803 | |||
| 8804 | /* The count of FLASH_KEY_STORE_USER_KEK_BODY */ | ||
| 8805 | #define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) | ||
| 8806 | |||
| 8807 | /*! @name UDS_KEY_CODE - . */ | ||
| 8808 | /*! @{ */ | ||
| 8809 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8810 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8811 | /*! FIELD - . | ||
| 8812 | */ | ||
| 8813 | #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) | ||
| 8814 | /*! @} */ | ||
| 8815 | |||
| 8816 | /* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ | ||
| 8817 | #define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) | ||
| 8818 | |||
| 8819 | /*! @name UDS_HEADER0 - . */ | ||
| 8820 | /*! @{ */ | ||
| 8821 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8822 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) | ||
| 8823 | /*! FIELD - . | ||
| 8824 | */ | ||
| 8825 | #define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) | ||
| 8826 | /*! @} */ | ||
| 8827 | |||
| 8828 | /*! @name UDS_HEADER1 - . */ | ||
| 8829 | /*! @{ */ | ||
| 8830 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) | ||
| 8831 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) | ||
| 8832 | /*! TYPE - . | ||
| 8833 | */ | ||
| 8834 | #define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) | ||
| 8835 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) | ||
| 8836 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) | ||
| 8837 | /*! INDEX - . | ||
| 8838 | */ | ||
| 8839 | #define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) | ||
| 8840 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8841 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) | ||
| 8842 | /*! SIZE - . | ||
| 8843 | */ | ||
| 8844 | #define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) | ||
| 8845 | /*! @} */ | ||
| 8846 | |||
| 8847 | /*! @name UDS_BODY - . */ | ||
| 8848 | /*! @{ */ | ||
| 8849 | #define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8850 | #define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) | ||
| 8851 | /*! FIELD - . | ||
| 8852 | */ | ||
| 8853 | #define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) | ||
| 8854 | /*! @} */ | ||
| 8855 | |||
| 8856 | /* The count of FLASH_KEY_STORE_UDS_BODY */ | ||
| 8857 | #define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) | ||
| 8858 | |||
| 8859 | /*! @name PRINCE_REGION0_KEY_CODE - . */ | ||
| 8860 | /*! @{ */ | ||
| 8861 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8862 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8863 | /*! FIELD - . | ||
| 8864 | */ | ||
| 8865 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) | ||
| 8866 | /*! @} */ | ||
| 8867 | |||
| 8868 | /* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ | ||
| 8869 | #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) | ||
| 8870 | |||
| 8871 | /*! @name PRINCE_REGION0_HEADER0 - . */ | ||
| 8872 | /*! @{ */ | ||
| 8873 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8874 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) | ||
| 8875 | /*! FIELD - . | ||
| 8876 | */ | ||
| 8877 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) | ||
| 8878 | /*! @} */ | ||
| 8879 | |||
| 8880 | /*! @name PRINCE_REGION0_HEADER1 - . */ | ||
| 8881 | /*! @{ */ | ||
| 8882 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) | ||
| 8883 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) | ||
| 8884 | /*! TYPE - . | ||
| 8885 | */ | ||
| 8886 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) | ||
| 8887 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) | ||
| 8888 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) | ||
| 8889 | /*! INDEX - . | ||
| 8890 | */ | ||
| 8891 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) | ||
| 8892 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8893 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) | ||
| 8894 | /*! SIZE - . | ||
| 8895 | */ | ||
| 8896 | #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) | ||
| 8897 | /*! @} */ | ||
| 8898 | |||
| 8899 | /*! @name PRINCE_REGION0_BODY - . */ | ||
| 8900 | /*! @{ */ | ||
| 8901 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8902 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) | ||
| 8903 | /*! FIELD - . | ||
| 8904 | */ | ||
| 8905 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) | ||
| 8906 | /*! @} */ | ||
| 8907 | |||
| 8908 | /* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ | ||
| 8909 | #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) | ||
| 8910 | |||
| 8911 | /*! @name PRINCE_REGION1_KEY_CODE - . */ | ||
| 8912 | /*! @{ */ | ||
| 8913 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8914 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8915 | /*! FIELD - . | ||
| 8916 | */ | ||
| 8917 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) | ||
| 8918 | /*! @} */ | ||
| 8919 | |||
| 8920 | /* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ | ||
| 8921 | #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) | ||
| 8922 | |||
| 8923 | /*! @name PRINCE_REGION1_HEADER0 - . */ | ||
| 8924 | /*! @{ */ | ||
| 8925 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8926 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) | ||
| 8927 | /*! FIELD - . | ||
| 8928 | */ | ||
| 8929 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) | ||
| 8930 | /*! @} */ | ||
| 8931 | |||
| 8932 | /*! @name PRINCE_REGION1_HEADER1 - . */ | ||
| 8933 | /*! @{ */ | ||
| 8934 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) | ||
| 8935 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) | ||
| 8936 | /*! TYPE - . | ||
| 8937 | */ | ||
| 8938 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) | ||
| 8939 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) | ||
| 8940 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) | ||
| 8941 | /*! INDEX - . | ||
| 8942 | */ | ||
| 8943 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) | ||
| 8944 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8945 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) | ||
| 8946 | /*! SIZE - . | ||
| 8947 | */ | ||
| 8948 | #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) | ||
| 8949 | /*! @} */ | ||
| 8950 | |||
| 8951 | /*! @name PRINCE_REGION1_BODY - . */ | ||
| 8952 | /*! @{ */ | ||
| 8953 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 8954 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) | ||
| 8955 | /*! FIELD - . | ||
| 8956 | */ | ||
| 8957 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) | ||
| 8958 | /*! @} */ | ||
| 8959 | |||
| 8960 | /* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ | ||
| 8961 | #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) | ||
| 8962 | |||
| 8963 | /*! @name PRINCE_REGION2_KEY_CODE - . */ | ||
| 8964 | /*! @{ */ | ||
| 8965 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) | ||
| 8966 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) | ||
| 8967 | /*! FIELD - . | ||
| 8968 | */ | ||
| 8969 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) | ||
| 8970 | /*! @} */ | ||
| 8971 | |||
| 8972 | /* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ | ||
| 8973 | #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) | ||
| 8974 | |||
| 8975 | /*! @name PRINCE_REGION2_HEADER0 - . */ | ||
| 8976 | /*! @{ */ | ||
| 8977 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) | ||
| 8978 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) | ||
| 8979 | /*! FIELD - . | ||
| 8980 | */ | ||
| 8981 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) | ||
| 8982 | /*! @} */ | ||
| 8983 | |||
| 8984 | /*! @name PRINCE_REGION2_HEADER1 - . */ | ||
| 8985 | /*! @{ */ | ||
| 8986 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) | ||
| 8987 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) | ||
| 8988 | /*! TYPE - . | ||
| 8989 | */ | ||
| 8990 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) | ||
| 8991 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) | ||
| 8992 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) | ||
| 8993 | /*! INDEX - . | ||
| 8994 | */ | ||
| 8995 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) | ||
| 8996 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) | ||
| 8997 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) | ||
| 8998 | /*! SIZE - . | ||
| 8999 | */ | ||
| 9000 | #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) | ||
| 9001 | /*! @} */ | ||
| 9002 | |||
| 9003 | /*! @name PRINCE_REGION2_BODY - . */ | ||
| 9004 | /*! @{ */ | ||
| 9005 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) | ||
| 9006 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) | ||
| 9007 | /*! FIELD - . | ||
| 9008 | */ | ||
| 9009 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) | ||
| 9010 | /*! @} */ | ||
| 9011 | |||
| 9012 | /* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ | ||
| 9013 | #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) | ||
| 9014 | |||
| 9015 | |||
| 9016 | /*! | ||
| 9017 | * @} | ||
| 9018 | */ /* end of group FLASH_KEY_STORE_Register_Masks */ | ||
| 9019 | |||
| 9020 | |||
| 9021 | /* FLASH_KEY_STORE - Peripheral instance base addresses */ | ||
| 9022 | #if (__ARM_FEATURE_CMSE & 0x2) | ||
| 9023 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 9024 | #define FLASH_KEY_STORE_BASE (0x1003E600u) | ||
| 9025 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 9026 | #define FLASH_KEY_STORE_BASE_NS (0x3E600u) | ||
| 9027 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 9028 | #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) | ||
| 9029 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 9030 | #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) | ||
| 9031 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 9032 | #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } | ||
| 9033 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 9034 | #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } | ||
| 9035 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 9036 | #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } | ||
| 9037 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 9038 | #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } | ||
| 9039 | #else | ||
| 9040 | /** Peripheral FLASH_KEY_STORE base address */ | ||
| 9041 | #define FLASH_KEY_STORE_BASE (0x3E600u) | ||
| 9042 | /** Peripheral FLASH_KEY_STORE base pointer */ | ||
| 9043 | #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) | ||
| 9044 | /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ | ||
| 9045 | #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } | ||
| 9046 | /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ | ||
| 9047 | #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } | ||
| 9048 | #endif | ||
| 9049 | |||
| 9050 | /*! | ||
| 9051 | * @} | ||
| 9052 | */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ | ||
| 9053 | |||
| 9054 | |||