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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/drivers/fsl_clock.h
new file mode 100644
index 000000000..efae65398
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/drivers/fsl_clock.h
@@ -0,0 +1,1264 @@
1/*
2 * Copyright 2017 - 2020 , NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.3.4. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
26/*@}*/
27
28/*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
40#endif
41
42/*!
43 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
44 *
45 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
46 * would cache the recent calulation and accelerate the execution to get the
47 * right settings.
48 */
49#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
50#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
51#endif
52
53/* Definition for delay API in clock driver, users can redefine it to the real application. */
54#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
55#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL)
56#endif
57
58/*! @brief Clock ip name array for ROM. */
59#define ROM_CLOCKS \
60 { \
61 kCLOCK_Rom \
62 }
63/*! @brief Clock ip name array for SRAM. */
64#define SRAM_CLOCKS \
65 { \
66 kCLOCK_Sram1, kCLOCK_Sram2 \
67 }
68/*! @brief Clock ip name array for FLASH. */
69#define FLASH_CLOCKS \
70 { \
71 kCLOCK_Flash \
72 }
73/*! @brief Clock ip name array for FMC. */
74#define FMC_CLOCKS \
75 { \
76 kCLOCK_Fmc \
77 }
78/*! @brief Clock ip name array for INPUTMUX. */
79#define INPUTMUX_CLOCKS \
80 { \
81 kCLOCK_InputMux0 \
82 }
83/*! @brief Clock ip name array for IOCON. */
84#define IOCON_CLOCKS \
85 { \
86 kCLOCK_Iocon \
87 }
88/*! @brief Clock ip name array for GPIO. */
89#define GPIO_CLOCKS \
90 { \
91 kCLOCK_Gpio0, kCLOCK_Gpio1 \
92 }
93/*! @brief Clock ip name array for PINT. */
94#define PINT_CLOCKS \
95 { \
96 kCLOCK_Pint \
97 }
98/*! @brief Clock ip name array for GINT. */
99#define GINT_CLOCKS \
100 { \
101 kCLOCK_Gint, kCLOCK_Gint \
102 }
103/*! @brief Clock ip name array for DMA. */
104#define DMA_CLOCKS \
105 { \
106 kCLOCK_Dma0, kCLOCK_Dma1 \
107 }
108/*! @brief Clock ip name array for CRC. */
109#define CRC_CLOCKS \
110 { \
111 kCLOCK_Crc \
112 }
113/*! @brief Clock ip name array for WWDT. */
114#define WWDT_CLOCKS \
115 { \
116 kCLOCK_Wwdt \
117 }
118/*! @brief Clock ip name array for RTC. */
119#define RTC_CLOCKS \
120 { \
121 kCLOCK_Rtc \
122 }
123/*! @brief Clock ip name array for Mailbox. */
124#define MAILBOX_CLOCKS \
125 { \
126 kCLOCK_Mailbox \
127 }
128/*! @brief Clock ip name array for LPADC. */
129#define LPADC_CLOCKS \
130 { \
131 kCLOCK_Adc0 \
132 }
133/*! @brief Clock ip name array for MRT. */
134#define MRT_CLOCKS \
135 { \
136 kCLOCK_Mrt \
137 }
138/*! @brief Clock ip name array for OSTIMER. */
139#define OSTIMER_CLOCKS \
140 { \
141 kCLOCK_OsTimer0 \
142 }
143/*! @brief Clock ip name array for SCT0. */
144#define SCT_CLOCKS \
145 { \
146 kCLOCK_Sct0 \
147 }
148/*! @brief Clock ip name array for MCAN. */
149#define MCAN_CLOCKS \
150 { \
151 kCLOCK_Mcan \
152 }
153/*! @brief Clock ip name array for UTICK. */
154#define UTICK_CLOCKS \
155 { \
156 kCLOCK_Utick0 \
157 }
158/*! @brief Clock ip name array for FLEXCOMM. */
159#define FLEXCOMM_CLOCKS \
160 { \
161 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \
162 kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \
163 }
164/*! @brief Clock ip name array for LPUART. */
165#define LPUART_CLOCKS \
166 { \
167 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
168 kCLOCK_MinUart6, kCLOCK_MinUart7 \
169 }
170
171/*! @brief Clock ip name array for BI2C. */
172#define BI2C_CLOCKS \
173 { \
174 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
175 }
176/*! @brief Clock ip name array for LSPI. */
177#define LPSPI_CLOCKS \
178 { \
179 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
180 }
181/*! @brief Clock ip name array for FLEXI2S. */
182#define FLEXI2S_CLOCKS \
183 { \
184 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
185 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
186 }
187/*! @brief Clock ip name array for CTIMER. */
188#define CTIMER_CLOCKS \
189 { \
190 kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
191 }
192/*! @brief Clock ip name array for EZHA */
193#define EZHA_CLOCKS \
194 { \
195 kCLOCK_Ezha \
196 }
197/*! @brief Clock ip name array for EZHB */
198#define EZHB_CLOCKS \
199 { \
200 kCLOCK_Ezhb \
201 }
202/*! @brief Clock ip name array for COMP */
203#define COMP_CLOCKS \
204 { \
205 kCLOCK_Comp \
206 }
207/*! @brief Clock ip name array for USB1CLK. */
208#define USB1CLK_CLOCKS \
209 { \
210 kCLOCK_Usb1Clk \
211 }
212/*! @brief Clock ip name array for FREQME. */
213#define FREQME_CLOCKS \
214 { \
215 kCLOCK_Freqme \
216 }
217/*! @brief Clock ip name array for USBRAM. */
218#define USBRAM_CLOCKS \
219 { \
220 kCLOCK_UsbRam1 \
221 }
222/*! @brief Clock ip name array for CWT. */
223#define CWT_CLOCKS \
224 { \
225 kCLOCK_Cwt \
226 }
227/*! @brief Clock ip name array for RNG. */
228#define RNG_CLOCKS \
229 { \
230 kCLOCK_Rng \
231 }
232/*! @brief Clock ip name array for USBHMR0. */
233#define USBHMR0_CLOCKS \
234 { \
235 kCLOCK_Usbhmr0 \
236 }
237/*! @brief Clock ip name array for USBHSL0. */
238#define USBHSL0_CLOCKS \
239 { \
240 kCLOCK_Usbhsl0 \
241 }
242/*! @brief Clock ip name array for HashCrypt. */
243#define HASHCRYPT_CLOCKS \
244 { \
245 kCLOCK_HashCrypt \
246 }
247/*! @brief Clock ip name array for PLULUT. */
248#define PLULUT_CLOCKS \
249 { \
250 kCLOCK_PluLut \
251 }
252/*! @brief Clock ip name array for PUF. */
253#define PUF_CLOCKS \
254 { \
255 kCLOCK_Puf \
256 }
257/*! @brief Clock ip name array for CASPER. */
258#define CASPER_CLOCKS \
259 { \
260 kCLOCK_Casper \
261 }
262/*! @brief Clock ip name array for ANALOGCTRL. */
263#define ANALOGCTRL_CLOCKS \
264 { \
265 kCLOCK_AnalogCtrl \
266 }
267/*! @brief Clock ip name array for HS_LSPI. */
268#define HS_LSPI_CLOCKS \
269 { \
270 kCLOCK_Hs_Lspi \
271 }
272/*! @brief Clock ip name array for GPIO_SEC. */
273#define GPIO_SEC_CLOCKS \
274 { \
275 kCLOCK_Gpio_Sec \
276 }
277/*! @brief Clock ip name array for GPIO_SEC_INT. */
278#define GPIO_SEC_INT_CLOCKS \
279 { \
280 kCLOCK_Gpio_Sec_Int \
281 }
282/*! @brief Clock ip name array for USBD. */
283#define USBD_CLOCKS \
284 { \
285 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
286 }
287/*! @brief Clock ip name array for USBH. */
288#define USBH_CLOCKS \
289 { \
290 kCLOCK_Usbh1 \
291 }
292#define PLU_CLOCKS \
293 { \
294 kCLOCK_PluLut \
295 }
296#define SYSCTL_CLOCKS \
297 { \
298 kCLOCK_Sysctl \
299 }
300/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
301/*------------------------------------------------------------------------------
302 clock_ip_name_t definition:
303------------------------------------------------------------------------------*/
304
305#define CLK_GATE_REG_OFFSET_SHIFT 8U
306#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
307#define CLK_GATE_BIT_SHIFT_SHIFT 0U
308#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
309
310#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
311 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
312 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
313
314#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
315#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
316
317#define AHB_CLK_CTRL0 0
318#define AHB_CLK_CTRL1 1
319#define AHB_CLK_CTRL2 2
320
321/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
322typedef enum _clock_ip_name
323{
324 kCLOCK_IpInvalid = 0U,
325 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
326 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
327 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
328 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
329 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
330 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
331 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
332 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
333 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
334 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
335 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
336 kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
337 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
338 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
339 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
340 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
341 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
342 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
343 kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
344 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
345 kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
346 kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
347 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
348 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
349 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
350 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
351 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
352 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
353 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
354 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
355 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
356 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
357 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
358 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
359 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
360 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
361 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
362 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
363 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
364 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
365 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
366 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
367 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
368 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
369 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
370 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
371 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
372 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
373 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
374 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
375 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
376 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
377 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
378 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
379 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
380 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
381 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
382 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
383 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
384 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
385 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
386 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
387 kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
388 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
389 kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
390 kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
391 kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
392 kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
393 kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
394 kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
395 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
396 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
397 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
398 kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
399 kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
400 kCLOCK_Cwt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
401 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
402 kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
403 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
404 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
405 kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
406 kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
407 kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
408 kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
409 kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
410 kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
411 kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
412 kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
413 kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
414 kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
415} clock_ip_name_t;
416
417/*! @brief Peripherals clock source definition. */
418#define BUS_CLK kCLOCK_BusClk
419
420#define I2C0_CLK_SRC BUS_CLK
421
422/*! @brief Clock name used to get clock frequency. */
423typedef enum _clock_name
424{
425 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
426 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
427 kCLOCK_ClockOut, /*!< CLOCKOUT */
428 kCLOCK_FroHf, /*!< FRO48/96 */
429 kCLOCK_Pll1Out, /*!< PLL1 Output */
430 kCLOCK_Mclk, /*!< MCLK */
431 kCLOCK_Fro12M, /*!< FRO12M */
432 kCLOCK_Fro1M, /*!< FRO1M */
433 kCLOCK_ExtClk, /*!< External Clock */
434 kCLOCK_Pll0Out, /*!< PLL0 Output */
435 kCLOCK_FlexI2S, /*!< FlexI2S clock */
436
437} clock_name_t;
438
439/*! @brief Clock Mux Switches
440 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
441 * starting from LSB upwards
442 *
443 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
444 *
445 */
446
447#define CLK_ATTACH_ID(mux, sel, pos) \
448 ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
449#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
450#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
451
452#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
453#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
454#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
455#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
456#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
457
458#define CM_SYSTICKCLKSEL0 0
459#define CM_TRACECLKSEL 2
460#define CM_CTIMERCLKSEL0 3
461#define CM_CTIMERCLKSEL1 4
462#define CM_CTIMERCLKSEL2 5
463#define CM_CTIMERCLKSEL3 6
464#define CM_CTIMERCLKSEL4 7
465#define CM_MAINCLKSELA 8
466#define CM_MAINCLKSELB 9
467#define CM_CLKOUTCLKSEL 10
468#define CM_PLL0CLKSEL 12
469#define CM_PLL1CLKSEL 13
470#define CM_MCANCLKSEL 16
471#define CM_ADCASYNCCLKSEL 17
472#define CM_USB0CLKSEL 18
473#define CM_CLK32KCLKSEL 19
474#define CM_FXCOMCLKSEL0 20
475#define CM_FXCOMCLKSEL1 21
476#define CM_FXCOMCLKSEL2 22
477#define CM_FXCOMCLKSEL3 23
478#define CM_FXCOMCLKSEL4 24
479#define CM_FXCOMCLKSEL5 25
480#define CM_FXCOMCLKSEL6 26
481#define CM_FXCOMCLKSEL7 27
482#define CM_HSLSPICLKSEL 28
483#define CM_MCLKCLKSEL 32
484#define CM_SCTCLKSEL 36
485
486#define CM_OSTIMERCLKSEL (62U)
487#define CM_RTCOSC32KCLKSEL 63U
488
489typedef enum _clock_attach_id
490{
491
492 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
493 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
494 kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
495 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
496 kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
497 kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
498 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
499
500 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
501 kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
502 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
503 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
504 kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
505 kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
506 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
507 kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
508
509 kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
510 kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
511 kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
512 kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
513 kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
514
515 kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0),
516 kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1),
517 kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2),
518 kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7),
519
520 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
521 kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
522 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
523 kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4),
524 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
525
526 kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
527 kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
528 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
529 kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
530 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
531
532 kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0),
533 kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1),
534 kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7),
535
536 kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
537 kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
538 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
539 kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
540 kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
541 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
542 kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
543 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
544
545 kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
546 kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
547 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
548 kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
549 kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
550 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
551 kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
552 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
553
554 kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
555 kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
556 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
557 kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
558 kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
559 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
560 kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
561 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
562
563 kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
564 kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
565 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
566 kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
567 kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
568 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
569 kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
570 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
571
572 kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
573 kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
574 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
575 kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
576 kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
577 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
578 kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
579 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
580
581 kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
582 kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
583 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
584 kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
585 kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
586 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
587 kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
588 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
589
590 kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
591 kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
592 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
593 kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
594 kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
595 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
596 kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
597 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
598
599 kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
600 kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
601 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
602 kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
603 kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
604 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
605 kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
606 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
607
608 kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
609 kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
610 kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
611 kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
612 kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
613 kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
614 kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
615
616 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
617 kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
618 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
619
620 kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
621 kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
622 kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
623 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
624 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
625 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
626
627 kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
628 kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
629
630 kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0),
631 kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1),
632 kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2),
633
634 kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
635 kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
636 kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
637 kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
638
639 kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
640 kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
641 kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
642 kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
643
644 kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
645 kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
646 kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
647 kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
648 kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
649
650 kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
651 kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
652 kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
653 kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
654 kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
655 kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
656 kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
657
658 kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
659 kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
660 kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
661 kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
662 kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
663 kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
664 kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
665
666 kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
667 kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
668 kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
669 kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
670 kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
671 kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
672 kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
673
674 kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
675 kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
676 kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
677 kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
678 kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
679 kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
680 kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
681
682 kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
683 kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
684 kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
685 kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
686 kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
687 kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
688 kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
689 kNONE_to_NONE = (int)0x80000000U,
690} clock_attach_id_t;
691
692/* Clock dividers */
693typedef enum _clock_div_name
694{
695 kCLOCK_DivSystickClk0 = 0,
696 kCLOCK_DivArmTrClkDiv = 2,
697 kCLOCK_DivCanClk = 3,
698 kCLOCK_DivFlexFrg0 = 8,
699 kCLOCK_DivFlexFrg1 = 9,
700 kCLOCK_DivFlexFrg2 = 10,
701 kCLOCK_DivFlexFrg3 = 11,
702 kCLOCK_DivFlexFrg4 = 12,
703 kCLOCK_DivFlexFrg5 = 13,
704 kCLOCK_DivFlexFrg6 = 14,
705 kCLOCK_DivFlexFrg7 = 15,
706 kCLOCK_DivAhbClk = 32,
707 kCLOCK_DivClkOut = 33,
708 kCLOCK_DivFrohfClk = 34,
709 kCLOCK_DivWdtClk = 35,
710 kCLOCK_DivAdcAsyncClk = 37,
711 kCLOCK_DivUsb0Clk = 38,
712 kCLOCK_DivFro1mClk = 40,
713 kCLOCK_DivMClk = 43,
714 kCLOCK_DivSctClk = 45,
715 kCLOCK_DivPll0Clk = 49
716} clock_div_name_t;
717
718/*******************************************************************************
719 * API
720 ******************************************************************************/
721
722#if defined(__cplusplus)
723extern "C" {
724#endif /* __cplusplus */
725
726/**
727 * @brief Enable the clock for specific IP.
728 * @param clk : Clock to be enabled.
729 * @return Nothing
730 */
731static inline void CLOCK_EnableClock(clock_ip_name_t clk)
732{
733 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
734 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
735}
736/**
737 * @brief Disable the clock for specific IP.
738 * @param clk : Clock to be Disabled.
739 * @return Nothing
740 */
741static inline void CLOCK_DisableClock(clock_ip_name_t clk)
742{
743 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
744 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
745}
746/**
747 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
748 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
749 * enabled.
750 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
751 * @return returns success or fail status.
752 */
753status_t CLOCK_SetupFROClocking(uint32_t iFreq);
754/**
755 * @brief Set the flash wait states for the input freuqency.
756 * @param system_freq_hz : Input frequency
757 * @return Nothing
758 */
759void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz);
760/**
761 * @brief Initialize the external osc clock to given frequency.
762 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
763 * @return returns success or fail status.
764 */
765status_t CLOCK_SetupExtClocking(uint32_t iFreq);
766/**
767 * @brief Initialize the I2S MCLK clock to given frequency.
768 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
769 * @return returns success or fail status.
770 */
771status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);
772/**
773 * @brief Initialize the PLU CLKIN clock to given frequency.
774 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
775 * @return returns success or fail status.
776 */
777status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);
778/**
779 * @brief Configure the clock selection muxes.
780 * @param connection : Clock to be configured.
781 * @return Nothing
782 */
783void CLOCK_AttachClk(clock_attach_id_t connection);
784/**
785 * @brief Get the actual clock attach id.
786 * This fuction uses the offset in input attach id, then it reads the actual source value in
787 * the register and combine the offset to obtain an actual attach id.
788 * @param attachId : Clock attach id to get.
789 * @return Clock source value.
790 */
791clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);
792/**
793 * @brief Setup peripheral clock dividers.
794 * @param div_name : Clock divider name
795 * @param divided_by_value: Value to be divided
796 * @param reset : Whether to reset the divider counter.
797 * @return Nothing
798 */
799void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
800/**
801 * @brief Setup rtc 1khz clock divider.
802 * @param divided_by_value: Value to be divided
803 * @return Nothing
804 */
805void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);
806/**
807 * @brief Setup rtc 1hz clock divider.
808 * @param divided_by_value: Value to be divided
809 * @return Nothing
810 */
811void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
812
813/**
814 * @brief Set the flexcomm output frequency.
815 * @param id : flexcomm instance id
816 * @param freq : output frequency
817 * @return 0 : the frequency range is out of range.
818 * 1 : switch successfully.
819 */
820uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);
821
822/*! @brief Return Frequency of flexcomm input clock
823 * @param id : flexcomm instance id
824 * @return Frequency value
825 */
826uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);
827
828/*! @brief Return Frequency of selected clock
829 * @return Frequency of selected clock
830 */
831uint32_t CLOCK_GetFreq(clock_name_t clockName);
832/*! @brief Return Frequency of FRO 12MHz
833 * @return Frequency of FRO 12MHz
834 */
835uint32_t CLOCK_GetFro12MFreq(void);
836/*! @brief Return Frequency of FRO 1MHz
837 * @return Frequency of FRO 1MHz
838 */
839uint32_t CLOCK_GetFro1MFreq(void);
840/*! @brief Return Frequency of ClockOut
841 * @return Frequency of ClockOut
842 */
843uint32_t CLOCK_GetClockOutClkFreq(void);
844/*! @brief Return Frequency of Can Clock
845 * @return Frequency of Can.
846 */
847uint32_t CLOCK_GetMCanClkFreq(void);
848/*! @brief Return Frequency of Adc Clock
849 * @return Frequency of Adc.
850 */
851uint32_t CLOCK_GetAdcClkFreq(void);
852/*! @brief Return Frequency of Usb0 Clock
853 * @return Frequency of Usb0 Clock.
854 */
855uint32_t CLOCK_GetUsb0ClkFreq(void);
856/*! @brief Return Frequency of Usb1 Clock
857 * @return Frequency of Usb1 Clock.
858 */
859uint32_t CLOCK_GetUsb1ClkFreq(void);
860/*! @brief Return Frequency of MClk Clock
861 * @return Frequency of MClk Clock.
862 */
863uint32_t CLOCK_GetMclkClkFreq(void);
864/*! @brief Return Frequency of SCTimer Clock
865 * @return Frequency of SCTimer Clock.
866 */
867uint32_t CLOCK_GetSctClkFreq(void);
868/*! @brief Return Frequency of External Clock
869 * @return Frequency of External Clock. If no external clock is used returns 0.
870 */
871uint32_t CLOCK_GetExtClkFreq(void);
872/*! @brief Return Frequency of Watchdog
873 * @return Frequency of Watchdog
874 */
875uint32_t CLOCK_GetWdtClkFreq(void);
876/*! @brief Return Frequency of High-Freq output of FRO
877 * @return Frequency of High-Freq output of FRO
878 */
879uint32_t CLOCK_GetFroHfFreq(void);
880/*! @brief Return Frequency of PLL
881 * @return Frequency of PLL
882 */
883uint32_t CLOCK_GetPll0OutFreq(void);
884/*! @brief Return Frequency of USB PLL
885 * @return Frequency of PLL
886 */
887uint32_t CLOCK_GetPll1OutFreq(void);
888/*! @brief Return Frequency of 32kHz osc
889 * @return Frequency of 32kHz osc
890 */
891uint32_t CLOCK_GetOsc32KFreq(void);
892/*! @brief Return Frequency of Core System
893 * @return Frequency of Core System
894 */
895uint32_t CLOCK_GetCoreSysClkFreq(void);
896/*! @brief Return Frequency of I2S MCLK Clock
897 * @return Frequency of I2S MCLK Clock
898 */
899uint32_t CLOCK_GetI2SMClkFreq(void);
900/*! @brief Return Frequency of PLU CLKIN Clock
901 * @return Frequency of PLU CLKIN Clock
902 */
903uint32_t CLOCK_GetPLUClkInFreq(void);
904/*! @brief Return Frequency of FlexComm Clock
905 * @return Frequency of FlexComm Clock
906 */
907uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
908/*! @brief Return Frequency of High speed SPI Clock
909 * @return Frequency of High speed SPI Clock
910 */
911uint32_t CLOCK_GetHsLspiClkFreq(void);
912/*! @brief Return Frequency of CTimer functional Clock
913 * @return Frequency of CTimer functional Clock
914 */
915uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
916/*! @brief Return Frequency of SystickClock
917 * @return Frequency of Systick Clock
918 */
919uint32_t CLOCK_GetSystickClkFreq(uint32_t id);
920
921/*! @brief Return PLL0 input clock rate
922 * @return PLL0 input clock rate
923 */
924uint32_t CLOCK_GetPLL0InClockRate(void);
925
926/*! @brief Return PLL1 input clock rate
927 * @return PLL1 input clock rate
928 */
929uint32_t CLOCK_GetPLL1InClockRate(void);
930
931/*! @brief Return PLL0 output clock rate
932 * @param recompute : Forces a PLL rate recomputation if true
933 * @return PLL0 output clock rate
934 * @note The PLL rate is cached in the driver in a variable as
935 * the rate computation function can take some time to perform. It
936 * is recommended to use 'false' with the 'recompute' parameter.
937 */
938uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);
939
940/*! @brief Return PLL1 output clock rate
941 * @param recompute : Forces a PLL rate recomputation if true
942 * @return PLL1 output clock rate
943 * @note The PLL rate is cached in the driver in a variable as
944 * the rate computation function can take some time to perform. It
945 * is recommended to use 'false' with the 'recompute' parameter.
946 */
947uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);
948
949/*! @brief Enables and disables PLL0 bypass mode
950 * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass
951 * @return PLL0 output clock rate
952 */
953__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)
954{
955 if (bypass)
956 {
957 SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
958 }
959 else
960 {
961 SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);
962 }
963}
964
965/*! @brief Enables and disables PLL1 bypass mode
966 * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass
967 * @return PLL1 output clock rate
968 */
969__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)
970{
971 if (bypass)
972 {
973 SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
974 }
975 else
976 {
977 SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);
978 }
979}
980
981/*! @brief Check if PLL is locked or not
982 * @return true if the PLL is locked, false if not locked
983 */
984__STATIC_INLINE bool CLOCK_IsPLL0Locked(void)
985{
986 return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);
987}
988
989/*! @brief Check if PLL1 is locked or not
990 * @return true if the PLL1 is locked, false if not locked
991 */
992__STATIC_INLINE bool CLOCK_IsPLL1Locked(void)
993{
994 return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);
995}
996
997/*! @brief Store the current PLL0 rate
998 * @param rate: Current rate of the PLL0
999 * @return Nothing
1000 **/
1001void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
1002
1003/*! @brief PLL configuration structure flags for 'flags' field
1004 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
1005 *
1006 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
1007 * configuration structure must be assigned with the expected PLL frequency. If the
1008 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
1009 * function and the driver will determine the PLL rate from the currently selected
1010 * PLL source. This flag might be used to configure the PLL input clock more accurately
1011 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
1012 *
1013 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
1014 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
1015 * are not used.<br>
1016 */
1017#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
1018#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)
1019/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
1020
1021/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
1022 * See (MF) field in the PLL0SSCG1 register in the UM.
1023 */
1024typedef enum _ss_progmodfm
1025{
1026 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
1027 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
1028 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
1029 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
1030 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
1031 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
1032 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
1033 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
1034} ss_progmodfm_t;
1035
1036/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
1037 * See (MR) field in the PLL0SSCG1 register in the UM.
1038 */
1039typedef enum _ss_progmoddp
1040{
1041 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
1042 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
1043 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
1044 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
1045 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
1046 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
1047 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
1048 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
1049} ss_progmoddp_t;
1050
1051/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
1052 * See (MC) field in the PLL0SSCG1 register in the UM.<br>
1053 * Compensation for low pass filtering of the PLL to get a triangular
1054 * modulation at the output of the PLL, giving a flat frequency spectrum.
1055 */
1056typedef enum _ss_modwvctrl
1057{
1058 kSS_MC_NOC = (0 << 26), /*!< no compensation */
1059 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
1060 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
1061} ss_modwvctrl_t;
1062
1063/*! @brief PLL configuration structure
1064 *
1065 * This structure can be used to configure the settings for a PLL
1066 * setup structure. Fill in the desired configuration for the PLL
1067 * and call the PLL setup function to fill in a PLL setup structure.
1068 */
1069typedef struct _pll_config
1070{
1071 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
1072 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
1073 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
1074 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
1075 PLL_CONFIGFLAG_FORCENOFRACT flag */
1076 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
1077 PLL_CONFIGFLAG_FORCENOFRACT flag */
1078 ss_modwvctrl_t
1079 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
1080 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
1081 PLL_CONFIGFLAG_FORCENOFRACT flag */
1082
1083} pll_config_t;
1084
1085/*! @brief PLL setup structure flags for 'flags' field
1086 * These flags control how the PLL setup function sets up the PLL
1087 */
1088#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
1089#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
1090#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
1091#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
1092
1093/*! @brief PLL0 setup structure
1094 * This structure can be used to pre-build a PLL setup configuration
1095 * at run-time and quickly set the PLL to the configuration. It can be
1096 * populated with the PLL setup function. If powering up or waiting
1097 * for PLL lock, the PLL input clock source should be configured prior
1098 * to PLL setup.
1099 */
1100typedef struct _pll_setup
1101{
1102 uint32_t pllctrl; /*!< PLL control register PLL0CTRL */
1103 uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */
1104 uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */
1105 uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */
1106 uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/
1107 uint32_t pllRate; /*!< Acutal PLL rate */
1108 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
1109} pll_setup_t;
1110
1111/*! @brief PLL status definitions
1112 */
1113typedef enum _pll_error
1114{
1115 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
1116 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
1117 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
1118 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
1119 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
1120 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
1121 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
1122 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
1123} pll_error_t;
1124
1125/*! @brief USB FS clock source definition. */
1126typedef enum _clock_usbfs_src
1127{
1128 kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */
1129 kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */
1130 kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
1131 kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */
1132
1133 kCLOCK_UsbfsSrcNone =
1134 SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */
1135} clock_usbfs_src_t;
1136
1137/*! @brief USBhs clock source definition. */
1138typedef enum _clock_usbhs_src
1139{
1140 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
1141 care the clock source. */
1142} clock_usbhs_src_t;
1143
1144/*! @brief Source of the USB HS PHY. */
1145typedef enum _clock_usb_phy_src
1146{
1147 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
1148} clock_usb_phy_src_t;
1149
1150/*! @brief Return PLL0 output clock rate from setup structure
1151 * @param pSetup : Pointer to a PLL setup structure
1152 * @return System PLL output clock rate the setup structure will generate
1153 */
1154uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);
1155
1156/*! @brief Return PLL1 output clock rate from setup structure
1157 * @param pSetup : Pointer to a PLL setup structure
1158 * @return PLL0 output clock rate the setup structure will generate
1159 */
1160uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup);
1161
1162/*! @brief Set PLL0 output based on the passed PLL setup data
1163 * @param pControl : Pointer to populated PLL control structure to generate setup with
1164 * @param pSetup : Pointer to PLL setup structure to be filled
1165 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1166 * @note Actual frequency for setup may vary from the desired frequency based on the
1167 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
1168 */
1169pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);
1170
1171/*! @brief Set PLL output from PLL setup structure (precise frequency)
1172 * @param pSetup : Pointer to populated PLL setup structure
1173 * @param flagcfg : Flag configuration for PLL config structure
1174 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
1175 * @note This function will power off the PLL, setup the PLL with the
1176 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1177 * and adjust system voltages to the new PLL rate. The function will not
1178 * alter any source clocks (ie, main systen clock) that may use the PLL,
1179 * so these should be setup prior to and after exiting the function.
1180 */
1181pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);
1182
1183/**
1184 * @brief Set PLL output from PLL setup structure (precise frequency)
1185 * @param pSetup : Pointer to populated PLL setup structure
1186 * @return kStatus_PLL_Success on success, or PLL setup error code
1187 * @note This function will power off the PLL, setup the PLL with the
1188 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1189 * and adjust system voltages to the new PLL rate. The function will not
1190 * alter any source clocks (ie, main systen clock) that may use the PLL,
1191 * so these should be setup prior to and after exiting the function.
1192 */
1193pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);
1194
1195/**
1196 * @brief Set PLL output from PLL setup structure (precise frequency)
1197 * @param pSetup : Pointer to populated PLL setup structure
1198 * @return kStatus_PLL_Success on success, or PLL setup error code
1199 * @note This function will power off the PLL, setup the PLL with the
1200 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
1201 * and adjust system voltages to the new PLL rate. The function will not
1202 * alter any source clocks (ie, main systen clock) that may use the PLL,
1203 * so these should be setup prior to and after exiting the function.
1204 */
1205pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);
1206
1207/*! @brief Set PLL0 output based on the multiplier and input frequency
1208 * @param multiply_by : multiplier
1209 * @param input_freq : Clock input frequency of the PLL
1210 * @return Nothing
1211 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
1212 * function does not disable or enable PLL power, wait for PLL lock,
1213 * or adjust system voltages. These must be done in the application.
1214 * The function will not alter any source clocks (ie, main systen clock)
1215 * that may use the PLL, so these should be setup prior to and after
1216 * exiting the function.
1217 */
1218void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);
1219
1220/*! @brief Disable USB clock.
1221 *
1222 * Disable USB clock.
1223 */
1224static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
1225{
1226 CLOCK_DisableClock(clk);
1227}
1228
1229/*! @brief Enable USB Device FS clock.
1230 * @param src : clock source
1231 * @param freq: clock frequency
1232 * Enable USB Device Full Speed clock.
1233 */
1234bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);
1235
1236/*! @brief Enable USB HOST FS clock.
1237 * @param src : clock source
1238 * @param freq: clock frequency
1239 * Enable USB HOST Full Speed clock.
1240 */
1241bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);
1242
1243/*! @brief Enable USB phy clock.
1244 * Enable USB phy clock.
1245 */
1246bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1247
1248/*! @brief Enable USB Device HS clock.
1249 * Enable USB Device High Speed clock.
1250 */
1251bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);
1252
1253/*! @brief Enable USB HOST HS clock.
1254 * Enable USB HOST High Speed clock.
1255 */
1256bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);
1257
1258#if defined(__cplusplus)
1259}
1260#endif /* __cplusplus */
1261
1262/*! @} */
1263
1264#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:01 +0100