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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.h36
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.c369
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.h173
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.c28
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.h31
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.c62
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.h52
8 files changed, 775 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.c
new file mode 100644
index 000000000..e7168a378
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.c
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/**
9 * @file board.c
10 * @brief Board initialization file.
11 */
12
13/* This is an empty template for board specific configuration.*/
14
15#include <stdint.h>
16#include "board.h"
17
18/**
19 * @brief Set up and initialize all required blocks and functions related to the board hardware.
20 */
21void BOARD_InitDebugConsole(void)
22{
23 /* The user initialization should be placed here */
24}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.h
new file mode 100644
index 000000000..40d92ed36
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/board.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/**
9 * @file board.h
10 * @brief Board initialization header file.
11 */
12
13/* This is an empty template for board specific configuration.*/
14
15#ifndef _BOARD_H_
16#define _BOARD_H_
17
18/**
19 * @brief The board name
20 */
21#define BOARD_NAME "board"
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus */
26
27/**
28 * @brief Initialize board specific settings.
29 */
30void BOARD_InitDebugConsole(void);
31
32#if defined(__cplusplus)
33}
34#endif /* __cplusplus */
35
36#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.c
new file mode 100644
index 000000000..bb4352e37
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.c
@@ -0,0 +1,369 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12/*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24/* clang-format off */
25/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26!!GlobalInfo
27product: Clocks v6.0
28processor: LPC55S16
29package_id: LPC55S16JBD100
30mcu_data: ksdk2_0
31processor_version: 0.0.4
32board: LPCXpresso55S16
33 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
34/* clang-format on */
35
36#include "fsl_power.h"
37#include "fsl_clock.h"
38#include "clock_config.h"
39
40/*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44/*******************************************************************************
45 * Variables
46 ******************************************************************************/
47/* System clock frequency. */
48extern uint32_t SystemCoreClock;
49
50/*******************************************************************************
51 ************************ BOARD_InitBootClocks function ************************
52 ******************************************************************************/
53void BOARD_InitBootClocks(void)
54{
55 BOARD_BootClockPLL150M();
56}
57
58/*******************************************************************************
59 ******************** Configuration BOARD_BootClockFRO12M **********************
60 ******************************************************************************/
61/* clang-format off */
62/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
63!!Configuration
64name: BOARD_BootClockFRO12M
65outputs:
66- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
67- {id: System_clock.outFreq, value: 12 MHz}
68 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
69/* clang-format on */
70
71/*******************************************************************************
72 * Variables for BOARD_BootClockFRO12M configuration
73 ******************************************************************************/
74/*******************************************************************************
75 * Code for BOARD_BootClockFRO12M configuration
76 ******************************************************************************/
77void BOARD_BootClockFRO12M(void)
78{
79#ifndef SDK_SECONDARY_CORE
80 /*!< Set up the clock sources */
81 /*!< Configure FRO192M */
82 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
83 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
84 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
85
86 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
87 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
88
89 /*!< Set up dividers */
90 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
91
92 /*!< Set up clock selectors - Attach clocks to the peripheries */
93 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
94
95 /*< Set SystemCoreClock variable. */
96 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
97#endif
98}
99
100/*******************************************************************************
101 ******************* Configuration BOARD_BootClockFROHF96M *********************
102 ******************************************************************************/
103/* clang-format off */
104/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
105!!Configuration
106name: BOARD_BootClockFROHF96M
107outputs:
108- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
109- {id: System_clock.outFreq, value: 96 MHz}
110settings:
111- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
112- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
113sources:
114- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
115 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
116/* clang-format on */
117
118/*******************************************************************************
119 * Variables for BOARD_BootClockFROHF96M configuration
120 ******************************************************************************/
121/*******************************************************************************
122 * Code for BOARD_BootClockFROHF96M configuration
123 ******************************************************************************/
124void BOARD_BootClockFROHF96M(void)
125{
126#ifndef SDK_SECONDARY_CORE
127 /*!< Set up the clock sources */
128 /*!< Configure FRO192M */
129 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
130 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
131 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
132
133 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
134
135 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
136 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
137
138 /*!< Set up dividers */
139 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
140
141 /*!< Set up clock selectors - Attach clocks to the peripheries */
142 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
143
144 /*< Set SystemCoreClock variable. */
145 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
146#endif
147}
148
149/*******************************************************************************
150 ******************** Configuration BOARD_BootClockPLL100M *********************
151 ******************************************************************************/
152/* clang-format off */
153/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
154!!Configuration
155name: BOARD_BootClockPLL100M
156outputs:
157- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
158- {id: System_clock.outFreq, value: 100 MHz}
159settings:
160- {id: PLL0_Mode, value: Normal}
161- {id: ENABLE_CLKIN_ENA, value: Enabled}
162- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
163- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
164- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
165- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
166- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
167sources:
168- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
169 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
170/* clang-format on */
171
172/*******************************************************************************
173 * Variables for BOARD_BootClockPLL100M configuration
174 ******************************************************************************/
175/*******************************************************************************
176 * Code for BOARD_BootClockPLL100M configuration
177 ******************************************************************************/
178void BOARD_BootClockPLL100M(void)
179{
180#ifndef SDK_SECONDARY_CORE
181 /*!< Set up the clock sources */
182 /*!< Configure FRO192M */
183 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
184 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
185 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
186
187 /*!< Configure XTAL32M */
188 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
189 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
190 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
191 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
192 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
193
194 POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
195 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
196
197 /*!< Set up PLL */
198 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
199 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
200 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
201 const pll_setup_t pll0Setup = {
202 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
203 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
204 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
205 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
206 .pllRate = 100000000U,
207 .flags = PLL_SETUPFLAG_WAITLOCK
208 };
209 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
210
211 /*!< Set up dividers */
212 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
213
214 /*!< Set up clock selectors - Attach clocks to the peripheries */
215 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
216
217 /*< Set SystemCoreClock variable. */
218 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
219#endif
220}
221
222/*******************************************************************************
223 ******************** Configuration BOARD_BootClockPLL150M *********************
224 ******************************************************************************/
225/* clang-format off */
226/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
227!!Configuration
228name: BOARD_BootClockPLL150M
229called_from_default_init: true
230outputs:
231- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
232- {id: System_clock.outFreq, value: 150 MHz}
233settings:
234- {id: PLL0_Mode, value: Normal}
235- {id: ENABLE_CLKIN_ENA, value: Enabled}
236- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
237- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
238- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
239- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
240- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
241- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
242sources:
243- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
244 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
245/* clang-format on */
246
247/*******************************************************************************
248 * Variables for BOARD_BootClockPLL150M configuration
249 ******************************************************************************/
250/*******************************************************************************
251 * Code for BOARD_BootClockPLL150M configuration
252 ******************************************************************************/
253void BOARD_BootClockPLL150M(void)
254{
255#ifndef SDK_SECONDARY_CORE
256 /*!< Set up the clock sources */
257 /*!< Configure FRO192M */
258 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
259 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
260 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
261
262 /*!< Configure XTAL32M */
263 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
264 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
265 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
266 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
267 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
268
269 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
270 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
271
272 /*!< Set up PLL */
273 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
274 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
275 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
276 const pll_setup_t pll0Setup = {
277 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
278 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
279 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
280 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
281 .pllRate = 150000000U,
282 .flags = PLL_SETUPFLAG_WAITLOCK
283 };
284 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
285
286 /*!< Set up dividers */
287 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
288
289 /*!< Set up clock selectors - Attach clocks to the peripheries */
290 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
291
292 /*< Set SystemCoreClock variable. */
293 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
294#endif
295}
296
297/*******************************************************************************
298 ******************* Configuration BOARD_BootClockPLL1_150M ********************
299 ******************************************************************************/
300/* clang-format off */
301/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
302!!Configuration
303name: BOARD_BootClockPLL1_150M
304outputs:
305- {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
306- {id: System_clock.outFreq, value: 150 MHz}
307settings:
308- {id: PLL1_Mode, value: Normal}
309- {id: ENABLE_CLKIN_ENA, value: Enabled}
310- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
311- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
312- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
313- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
314- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
315- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
316sources:
317- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
318 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
319/* clang-format on */
320
321/*******************************************************************************
322 * Variables for BOARD_BootClockPLL1_150M configuration
323 ******************************************************************************/
324/*******************************************************************************
325 * Code for BOARD_BootClockPLL1_150M configuration
326 ******************************************************************************/
327void BOARD_BootClockPLL1_150M(void)
328{
329#ifndef SDK_SECONDARY_CORE
330 /*!< Set up the clock sources */
331 /*!< Configure FRO192M */
332 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
333 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
334 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
335
336 /*!< Configure XTAL32M */
337 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
338 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
339 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
340 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
341 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
342
343 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
344 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
345
346 /*!< Set up PLL1 */
347 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
348 POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
349 const pll_setup_t pll1Setup = {
350 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
351 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
352 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
353 .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
354 .pllRate = 150000000U,
355 .flags = PLL_SETUPFLAG_WAITLOCK
356 };
357 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
358
359 /*!< Set up dividers */
360 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
361
362 /*!< Set up clock selectors - Attach clocks to the peripheries */
363 CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
364
365 /*< Set SystemCoreClock variable. */
366 SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
367#endif
368}
369
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.h
new file mode 100644
index 000000000..b9c591c22
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/clock_config.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _CLOCK_CONFIG_H_
14#define _CLOCK_CONFIG_H_
15
16#include "fsl_common.h"
17
18/*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
22#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
23
24/*******************************************************************************
25 ************************ BOARD_InitBootClocks function ************************
26 ******************************************************************************/
27
28#if defined(__cplusplus)
29extern "C" {
30#endif /* __cplusplus*/
31
32/*!
33 * @brief This function executes default configuration of clocks.
34 *
35 */
36void BOARD_InitBootClocks(void);
37
38#if defined(__cplusplus)
39}
40#endif /* __cplusplus*/
41
42/*******************************************************************************
43 ******************** Configuration BOARD_BootClockFRO12M **********************
44 ******************************************************************************/
45/*******************************************************************************
46 * Definitions for BOARD_BootClockFRO12M configuration
47 ******************************************************************************/
48#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
49
50
51/*******************************************************************************
52 * API for BOARD_BootClockFRO12M configuration
53 ******************************************************************************/
54#if defined(__cplusplus)
55extern "C" {
56#endif /* __cplusplus*/
57
58/*!
59 * @brief This function executes configuration of clocks.
60 *
61 */
62void BOARD_BootClockFRO12M(void);
63
64#if defined(__cplusplus)
65}
66#endif /* __cplusplus*/
67
68/*******************************************************************************
69 ******************* Configuration BOARD_BootClockFROHF96M *********************
70 ******************************************************************************/
71/*******************************************************************************
72 * Definitions for BOARD_BootClockFROHF96M configuration
73 ******************************************************************************/
74#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
75
76
77/*******************************************************************************
78 * API for BOARD_BootClockFROHF96M configuration
79 ******************************************************************************/
80#if defined(__cplusplus)
81extern "C" {
82#endif /* __cplusplus*/
83
84/*!
85 * @brief This function executes configuration of clocks.
86 *
87 */
88void BOARD_BootClockFROHF96M(void);
89
90#if defined(__cplusplus)
91}
92#endif /* __cplusplus*/
93
94/*******************************************************************************
95 ******************** Configuration BOARD_BootClockPLL100M *********************
96 ******************************************************************************/
97/*******************************************************************************
98 * Definitions for BOARD_BootClockPLL100M configuration
99 ******************************************************************************/
100#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
101
102
103/*******************************************************************************
104 * API for BOARD_BootClockPLL100M configuration
105 ******************************************************************************/
106#if defined(__cplusplus)
107extern "C" {
108#endif /* __cplusplus*/
109
110/*!
111 * @brief This function executes configuration of clocks.
112 *
113 */
114void BOARD_BootClockPLL100M(void);
115
116#if defined(__cplusplus)
117}
118#endif /* __cplusplus*/
119
120/*******************************************************************************
121 ******************** Configuration BOARD_BootClockPLL150M *********************
122 ******************************************************************************/
123/*******************************************************************************
124 * Definitions for BOARD_BootClockPLL150M configuration
125 ******************************************************************************/
126#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
127
128
129/*******************************************************************************
130 * API for BOARD_BootClockPLL150M configuration
131 ******************************************************************************/
132#if defined(__cplusplus)
133extern "C" {
134#endif /* __cplusplus*/
135
136/*!
137 * @brief This function executes configuration of clocks.
138 *
139 */
140void BOARD_BootClockPLL150M(void);
141
142#if defined(__cplusplus)
143}
144#endif /* __cplusplus*/
145
146/*******************************************************************************
147 ******************* Configuration BOARD_BootClockPLL1_150M ********************
148 ******************************************************************************/
149/*******************************************************************************
150 * Definitions for BOARD_BootClockPLL1_150M configuration
151 ******************************************************************************/
152#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
153
154
155/*******************************************************************************
156 * API for BOARD_BootClockPLL1_150M configuration
157 ******************************************************************************/
158#if defined(__cplusplus)
159extern "C" {
160#endif /* __cplusplus*/
161
162/*!
163 * @brief This function executes configuration of clocks.
164 *
165 */
166void BOARD_BootClockPLL1_150M(void);
167
168#if defined(__cplusplus)
169}
170#endif /* __cplusplus*/
171
172#endif /* _CLOCK_CONFIG_H_ */
173
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.c
new file mode 100644
index 000000000..0ec5f0ac4
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.c
@@ -0,0 +1,28 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
9!!GlobalInfo
10product: Peripherals v1.0
11* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
12
13/**
14 * @file peripherals.c
15 * @brief Peripherals initialization file.
16 */
17
18/* This is an empty template for board specific configuration.*/
19
20#include "peripherals.h"
21
22/**
23 * @brief Set up and initialize all required blocks and functions related to the peripherals hardware.
24 */
25void BOARD_InitBootPeripherals(void)
26{
27 /* The user initialization should be placed here */
28}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.h
new file mode 100644
index 000000000..f45de54cd
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/peripherals.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/**
9 * @file peripherals.h
10 * @brief Peripherals initialization header file.
11 */
12
13/* This is an empty template for board specific configuration.*/
14
15#ifndef _PERIPHERALS_H_
16#define _PERIPHERALS_H_
17
18#if defined(__cplusplus)
19extern "C" {
20#endif /* __cplusplus */
21
22/**
23 * @brief Initialize peripherals specific settings.
24 */
25void BOARD_InitBootPeripherals(void);
26
27#if defined(__cplusplus)
28}
29#endif /* __cplusplus */
30
31#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.c
new file mode 100644
index 000000000..6dc8fdee9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16!!GlobalInfo
17product: Pins v6.0
18processor: LPC55S16
19package_id: LPC55S16JBD100
20mcu_data: ksdk2_0
21processor_version: 0.0.4
22 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
23 */
24/* clang-format on */
25
26#include "fsl_common.h"
27#include "pin_mux.h"
28
29/* FUNCTION ************************************************************************************************************
30 *
31 * Function Name : BOARD_InitBootPins
32 * Description : Calls initialization functions.
33 *
34 * END ****************************************************************************************************************/
35void BOARD_InitBootPins(void)
36{
37 BOARD_InitPins();
38}
39
40/* clang-format off */
41/*
42 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
43BOARD_InitPins:
44- options: {callFromInitBoot: 'true', enableClock: 'true'}
45- pin_list: []
46 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
47 */
48/* clang-format on */
49
50/* FUNCTION ************************************************************************************************************
51 *
52 * Function Name : BOARD_InitPins
53 * Description : Configures pin routing and optionally pin electrical features.
54 *
55 * END ****************************************************************************************************************/
56/* Function assigned for the Cortex-M33 */
57void BOARD_InitPins(void)
58{
59}
60/***********************************************************************************************************************
61 * EOF
62 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.h
new file mode 100644
index 000000000..9a49375bb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC55S16/project_template/pin_mux.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/*!
17 * @addtogroup pin_mux
18 * @{
19 */
20
21/***********************************************************************************************************************
22 * API
23 **********************************************************************************************************************/
24
25#if defined(__cplusplus)
26extern "C" {
27#endif
28
29/*!
30 * @brief Calls initialization functions.
31 *
32 */
33void BOARD_InitBootPins(void);
34
35/*!
36 * @brief Configures pin routing and optionally pin electrical features.
37 *
38 */
39void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */
40
41#if defined(__cplusplus)
42}
43#endif
44
45/*!
46 * @}
47 */
48#endif /* _PIN_MUX_H_ */
49
50/***********************************************************************************************************************
51 * EOF
52 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:12:27 +0100