1 files changed, 235 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h
new file mode 100644
index 000000000..145cea246
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h
@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b200222
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+#ifndef _LPC844_FEATURES_H_
+#define _LPC844_FEATURES_H_
+/* SOC module features */
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PMU availability on the SoC. */
+#define FSL_FEATURE_SOC_PMU_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief SWM availability on the SoC. */
+#define FSL_FEATURE_SOC_SWM_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (2)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+/* ACOMP module features */
+/* @brief Has INTENA bitfile in CTRL reigster. */
+#define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1)
+/* ADC module features */
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (0)
+/* @brief Has ADC Trim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (1)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
+/* CLOCK module features */
+/* @brief GPIOINT clock source. */
+#define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1)
+/* CTIMER module features */
+/* @brief Writing a zero asserts the CTIMER reset. */
+#define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1)
+/* DMA module features */
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+/* FAIM module features */
+/* @brief Size of the FAIM */
+#define FSL_FEATURE_FAIM_SIZE (32)
+/* @brief Page count of the FAIM */
+#define FSL_FEATURE_FAIM_PAGE_COUNT (8)
+/* INPUTMUX module features */
+/* @brief Inputmux clock source. */
+#define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1)
+/* IOCON module features */
+/* No feature definitions */
+/* MRT module features */
+/* @brief Writing a zero asserts the MRT reset. */
+#define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1)
+/* @brief Has no MULTITASK bitfile in MODCFG reigster. */
+#define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1)
+/* @brief Has no INUSE bitfile in STAT reigster. */
+#define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1)
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+/* NVIC module features */
+/* @brief Number of connected outputs. */
+#define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1)
+/* PINT module features */
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+/* SCT module features */
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (8)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8)
+/* @brief Writing a zero asserts the SCT reset. */
+#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7)
+/* SPI module features */
+/* @brief Has SPOL0 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL0 (1)
+/* @brief Has SPOL1 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL1 (1)
+/* @brief Has SPOL2 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL2 (1)
+/* @brief Has SPOL3 bitfile in CFG reigster. */
+#define FSL_FEATURE_SPI_HAS_SSEL3 (1)
+/* SWM module features */
+/* @brief Has SWM PINENABLE0 ACMP I3. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1)
+/* @brief Has SWM PINENABLE0 ACMP I4. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1)
+/* @brief Has SWM PINENABLE0 ACMP I5. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1)
+/* @brief Has SWM PINENABLE1. */
+#define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1)
+/* SYSCON module features */
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536)
+/* @brief IAP has Flash read & write function */
+#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
+/* @brief IAP has FAIM read & write function */
+#define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1)
+/* @brief IAP has read Flash signature function */
+#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
+/* @brief IAP has read extended Flash signature function */
+#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+/* @brief Has PINTSEL register. */
+#define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1)
+/* USART module features */
+/* @brief Has OSR (register OSR). */
+#define FSL_FEATURE_USART_HAS_OSR_REGISTER (1)
+/* @brief Has TXIDLEEN bitfile in INTENSET reigster. */
+#define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1)
+/* @brief Has ABERREN bitfile in INTENSET reigster. */
+#define FSL_FEATURE_USART_HAS_ABERR_CHECK (1)
+/* WKT module features */
+/* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */
+#define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1)
+/* WWDT module features */
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
+#endif /* _LPC844_FEATURES_H_ */

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h new file mode 100644 index 000000000..145cea246 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844_features.h
@@ -0,0 +1,235 @@
	1	/*
	2	** ###################################################################
	3	** Version: rev. 1.2, 2017-06-08
	4	** Build: b200222
	5	**
	6	** Abstract:
	7	** Chip specific module features.
	8	**
	9	** Copyright 2016 Freescale Semiconductor, Inc.
	10	** Copyright 2016-2020 NXP
	11	** All rights reserved.
	12	**
	13	** SPDX-License-Identifier: BSD-3-Clause
	14	**
	15	** http: www.nxp.com
	16	** mail: [email protected]
	17	**
	18	** Revisions:
	19	** - rev. 1.0 (2016-08-12)
	20	** Initial version.
	21	** - rev. 1.1 (2016-11-25)
	22	** Update CANFD and Classic CAN register.
	23	** Add MAC TIMERSTAMP registers.
	24	** - rev. 1.2 (2017-06-08)
	25	** Remove RTC_CTRL_RTC_OSC_BYPASS.
	26	** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
	27	** Remove RESET and HALT from SYSCON_AHBCLKDIV.
	28	**
	29	** ###################################################################
	30	*/
	31
	32	#ifndef _LPC844_FEATURES_H_
	33	#define _LPC844_FEATURES_H_
	34
	35	/* SOC module features */
	36
	37	/* @brief ADC availability on the SoC. */
	38	#define FSL_FEATURE_SOC_ADC_COUNT (1)
	39	/* @brief CRC availability on the SoC. */
	40	#define FSL_FEATURE_SOC_CRC_COUNT (1)
	41	/* @brief CTIMER availability on the SoC. */
	42	#define FSL_FEATURE_SOC_CTIMER_COUNT (1)
	43	/* @brief DMA availability on the SoC. */
	44	#define FSL_FEATURE_SOC_DMA_COUNT (1)
	45	/* @brief GPIO availability on the SoC. */
	46	#define FSL_FEATURE_SOC_GPIO_COUNT (1)
	47	/* @brief I2C availability on the SoC. */
	48	#define FSL_FEATURE_SOC_I2C_COUNT (2)
	49	/* @brief INPUTMUX availability on the SoC. */
	50	#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
	51	/* @brief IOCON availability on the SoC. */
	52	#define FSL_FEATURE_SOC_IOCON_COUNT (1)
	53	/* @brief MRT availability on the SoC. */
	54	#define FSL_FEATURE_SOC_MRT_COUNT (1)
	55	/* @brief MTB availability on the SoC. */
	56	#define FSL_FEATURE_SOC_MTB_COUNT (1)
	57	/* @brief PINT availability on the SoC. */
	58	#define FSL_FEATURE_SOC_PINT_COUNT (1)
	59	/* @brief PMU availability on the SoC. */
	60	#define FSL_FEATURE_SOC_PMU_COUNT (1)
	61	/* @brief SCT availability on the SoC. */
	62	#define FSL_FEATURE_SOC_SCT_COUNT (1)
	63	/* @brief SPI availability on the SoC. */
	64	#define FSL_FEATURE_SOC_SPI_COUNT (2)
	65	/* @brief SWM availability on the SoC. */
	66	#define FSL_FEATURE_SOC_SWM_COUNT (1)
	67	/* @brief SYSCON availability on the SoC. */
	68	#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
	69	/* @brief USART availability on the SoC. */
	70	#define FSL_FEATURE_SOC_USART_COUNT (2)
	71	/* @brief WWDT availability on the SoC. */
	72	#define FSL_FEATURE_SOC_WWDT_COUNT (1)
	73
	74	/* ACOMP module features */
	75
	76	/* @brief Has INTENA bitfile in CTRL reigster. */
	77	#define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1)
	78
	79	/* ADC module features */
	80
	81	/* @brief Do not has input select (register INSEL). */
	82	#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
	83	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	84	#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
	85	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	86	#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0)
	87	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	88	#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
	89	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	90	#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0)
	91	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	92	#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1)
	93	/* @brief Has ASYNMODE bitfile in CTRL reigster. */
	94	#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1)
	95	/* @brief Has startup register. */
	96	#define FSL_FEATURE_ADC_HAS_STARTUP_REG (0)
	97	/* @brief Has ADC Trim register */
	98	#define FSL_FEATURE_ADC_HAS_TRIM_REG (1)
	99	/* @brief Has Calibration register. */
	100	#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
	101
	102	/* CLOCK module features */
	103
	104	/* @brief GPIOINT clock source. */
	105	#define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1)
	106
	107	/* CTIMER module features */
	108
	109	/* @brief Writing a zero asserts the CTIMER reset. */
	110	#define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1)
	111
	112	/* DMA module features */
	113
	114	/* @brief Number of channels */
	115	#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25)
	116	/* @brief Align size of DMA descriptor */
	117	#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
	118	/* @brief DMA head link descriptor table align size */
	119	#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
	120
	121	/* FAIM module features */
	122
	123	/* @brief Size of the FAIM */
	124	#define FSL_FEATURE_FAIM_SIZE (32)
	125	/* @brief Page count of the FAIM */
	126	#define FSL_FEATURE_FAIM_PAGE_COUNT (8)
	127
	128	/* INPUTMUX module features */
	129
	130	/* @brief Inputmux clock source. */
	131	#define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1)
	132
	133	/* IOCON module features */
	134
	135	/* No feature definitions */
	136
	137	/* MRT module features */
	138
	139	/* @brief Writing a zero asserts the MRT reset. */
	140	#define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1)
	141	/* @brief Has no MULTITASK bitfile in MODCFG reigster. */
	142	#define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1)
	143	/* @brief Has no INUSE bitfile in STAT reigster. */
	144	#define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1)
	145	/* @brief number of channels. */
	146	#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
	147
	148	/* NVIC module features */
	149
	150	/* @brief Number of connected outputs. */
	151	#define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1)
	152
	153	/* PINT module features */
	154
	155	/* @brief Number of connected outputs */
	156	#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
	157
	158	/* SCT module features */
	159
	160	/* @brief Number of events */
	161	#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8)
	162	/* @brief Number of states */
	163	#define FSL_FEATURE_SCT_NUMBER_OF_STATES (8)
	164	/* @brief Number of match capture */
	165	#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8)
	166	/* @brief Writing a zero asserts the SCT reset. */
	167	#define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1)
	168	/* @brief Number of outputs */
	169	#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7)
	170
	171	/* SPI module features */
	172
	173	/* @brief Has SPOL0 bitfile in CFG reigster. */
	174	#define FSL_FEATURE_SPI_HAS_SSEL0 (1)
	175	/* @brief Has SPOL1 bitfile in CFG reigster. */
	176	#define FSL_FEATURE_SPI_HAS_SSEL1 (1)
	177	/* @brief Has SPOL2 bitfile in CFG reigster. */
	178	#define FSL_FEATURE_SPI_HAS_SSEL2 (1)
	179	/* @brief Has SPOL3 bitfile in CFG reigster. */
	180	#define FSL_FEATURE_SPI_HAS_SSEL3 (1)
	181
	182	/* SWM module features */
	183
	184	/* @brief Has SWM PINENABLE0 ACMP I3. */
	185	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1)
	186	/* @brief Has SWM PINENABLE0 ACMP I4. */
	187	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1)
	188	/* @brief Has SWM PINENABLE0 ACMP I5. */
	189	#define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1)
	190	/* @brief Has SWM PINENABLE1. */
	191	#define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1)
	192
	193	/* SYSCON module features */
	194
	195	/* @brief Pointer to ROM IAP entry functions */
	196	#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1)
	197	/* @brief Flash page size in bytes */
	198	#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64)
	199	/* @brief Flash sector size in bytes */
	200	#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024)
	201	/* @brief Flash size in bytes */
	202	#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536)
	203	/* @brief IAP has Flash read & write function */
	204	#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1)
	205	/* @brief IAP has FAIM read & write function */
	206	#define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1)
	207	/* @brief IAP has read Flash signature function */
	208	#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0)
	209	/* @brief IAP has read extended Flash signature function */
	210	#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1)
	211	/* @brief Starter register discontinuous. */
	212	#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
	213	/* @brief Has PINTSEL register. */
	214	#define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1)
	215
	216	/* USART module features */
	217
	218	/* @brief Has OSR (register OSR). */
	219	#define FSL_FEATURE_USART_HAS_OSR_REGISTER (1)
	220	/* @brief Has TXIDLEEN bitfile in INTENSET reigster. */
	221	#define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1)
	222	/* @brief Has ABERREN bitfile in INTENSET reigster. */
	223	#define FSL_FEATURE_USART_HAS_ABERR_CHECK (1)
	224
	225	/* WKT module features */
	226
	227	/* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */
	228	#define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1)
	229
	230	/* WWDT module features */
	231
	232	/* @brief Has no RESET register. */
	233	#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
	234
	235	#endif /* _LPC844_FEATURES_H_ */