diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/LPC844')
30 files changed, 15385 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844.h new file mode 100644 index 000000000..607127c37 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/LPC844.h | |||
| @@ -0,0 +1,9706 @@ | |||
| 1 | /* | ||
| 2 | ** ################################################################### | ||
| 3 | ** Processors: LPC844M201JBD48 | ||
| 4 | ** LPC844M201JBD64 | ||
| 5 | ** LPC844M201JHI33 | ||
| 6 | ** LPC844M201JHI48 | ||
| 7 | ** | ||
| 8 | ** Compilers: GNU C Compiler | ||
| 9 | ** IAR ANSI C/C++ Compiler for ARM | ||
| 10 | ** Keil ARM C/C++ Compiler | ||
| 11 | ** MCUXpresso Compiler | ||
| 12 | ** | ||
| 13 | ** Reference manual: LPC84x User manual Rev.1.6 8 Dec 2017 | ||
| 14 | ** Version: rev. 1.2, 2017-06-08 | ||
| 15 | ** Build: b201029 | ||
| 16 | ** | ||
| 17 | ** Abstract: | ||
| 18 | ** CMSIS Peripheral Access Layer for LPC844 | ||
| 19 | ** | ||
| 20 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. | ||
| 21 | ** Copyright 2016-2020 NXP | ||
| 22 | ** All rights reserved. | ||
| 23 | ** | ||
| 24 | ** SPDX-License-Identifier: BSD-3-Clause | ||
| 25 | ** | ||
| 26 | ** http: www.nxp.com | ||
| 27 | ** mail: [email protected] | ||
| 28 | ** | ||
| 29 | ** Revisions: | ||
| 30 | ** - rev. 1.0 (2016-08-12) | ||
| 31 | ** Initial version. | ||
| 32 | ** - rev. 1.1 (2016-11-25) | ||
| 33 | ** Update CANFD and Classic CAN register. | ||
| 34 | ** Add MAC TIMERSTAMP registers. | ||
| 35 | ** - rev. 1.2 (2017-06-08) | ||
| 36 | ** Remove RTC_CTRL_RTC_OSC_BYPASS. | ||
| 37 | ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. | ||
| 38 | ** Remove RESET and HALT from SYSCON_AHBCLKDIV. | ||
| 39 | ** | ||
| 40 | ** ################################################################### | ||
| 41 | */ | ||
| 42 | |||
| 43 | /*! | ||
| 44 | * @file LPC844.h | ||
| 45 | * @version 1.2 | ||
| 46 | * @date 2017-06-08 | ||
| 47 | * @brief CMSIS Peripheral Access Layer for LPC844 | ||
| 48 | * | ||
| 49 | * CMSIS Peripheral Access Layer for LPC844 | ||
| 50 | */ | ||
| 51 | |||
| 52 | #ifndef _LPC844_H_ | ||
| 53 | #define _LPC844_H_ /**< Symbol preventing repeated inclusion */ | ||
| 54 | |||
| 55 | /** Memory map major version (memory maps with equal major version number are | ||
| 56 | * compatible) */ | ||
| 57 | #define MCU_MEM_MAP_VERSION 0x0100U | ||
| 58 | /** Memory map minor version */ | ||
| 59 | #define MCU_MEM_MAP_VERSION_MINOR 0x0002U | ||
| 60 | |||
| 61 | |||
| 62 | /* ---------------------------------------------------------------------------- | ||
| 63 | -- Interrupt vector numbers | ||
| 64 | ---------------------------------------------------------------------------- */ | ||
| 65 | |||
| 66 | /*! | ||
| 67 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers | ||
| 68 | * @{ | ||
| 69 | */ | ||
| 70 | |||
| 71 | /** Interrupt Number Definitions */ | ||
| 72 | #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ | ||
| 73 | |||
| 74 | typedef enum IRQn { | ||
| 75 | /* Auxiliary constants */ | ||
| 76 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ | ||
| 77 | |||
| 78 | /* Core interrupts */ | ||
| 79 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ | ||
| 80 | HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ | ||
| 81 | SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ | ||
| 82 | PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ | ||
| 83 | SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ | ||
| 84 | |||
| 85 | /* Device specific interrupts */ | ||
| 86 | SPI0_IRQn = 0, /**< SPI0 interrupt */ | ||
| 87 | SPI1_IRQn = 1, /**< SPI1 interrupt */ | ||
| 88 | DAC0_IRQn = 2, /**< DAC0 interrupt */ | ||
| 89 | USART0_IRQn = 3, /**< USART0 interrupt */ | ||
| 90 | USART1_IRQn = 4, /**< USART1 interrupt */ | ||
| 91 | USART2_IRQn = 5, /**< USART2 interrupt */ | ||
| 92 | Reserved22_IRQn = 6, /**< Reserved interrupt */ | ||
| 93 | I2C1_IRQn = 7, /**< I2C1 interrupt */ | ||
| 94 | I2C0_IRQn = 8, /**< I2C0 interrupt */ | ||
| 95 | SCT0_IRQn = 9, /**< State configurable timer interrupt */ | ||
| 96 | MRT0_IRQn = 10, /**< Multi-rate timer interrupt */ | ||
| 97 | CMP_CAPT_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */ | ||
| 98 | WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */ | ||
| 99 | BOD_IRQn = 13, /**< BOD interrupts */ | ||
| 100 | FLASH_IRQn = 14, /**< flash interrupt */ | ||
| 101 | WKT_IRQn = 15, /**< Self-wake-up timer interrupt */ | ||
| 102 | ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */ | ||
| 103 | ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */ | ||
| 104 | ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */ | ||
| 105 | ADC0_OVR_IRQn = 19, /**< ADC0 overrun */ | ||
| 106 | DMA0_IRQn = 20, /**< DMA0 interrupt */ | ||
| 107 | I2C2_IRQn = 21, /**< I2C2 interrupt */ | ||
| 108 | I2C3_IRQn = 22, /**< I2C3 interrupt */ | ||
| 109 | CTIMER0_IRQn = 23, /**< Timer interrupt */ | ||
| 110 | PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */ | ||
| 111 | PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */ | ||
| 112 | PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */ | ||
| 113 | PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */ | ||
| 114 | PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */ | ||
| 115 | PIN_INT5_DAC1_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt or DAC1 interrupt */ | ||
| 116 | PIN_INT6_USART3_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt or UART3 interrupt */ | ||
| 117 | PIN_INT7_USART4_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt or UART4 interrupt */ | ||
| 118 | } IRQn_Type; | ||
| 119 | |||
| 120 | /*! | ||
| 121 | * @} | ||
| 122 | */ /* end of group Interrupt_vector_numbers */ | ||
| 123 | |||
| 124 | |||
| 125 | /* ---------------------------------------------------------------------------- | ||
| 126 | -- Cortex M0 Core Configuration | ||
| 127 | ---------------------------------------------------------------------------- */ | ||
| 128 | |||
| 129 | /*! | ||
| 130 | * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration | ||
| 131 | * @{ | ||
| 132 | */ | ||
| 133 | |||
| 134 | #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ | ||
| 135 | #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ | ||
| 136 | #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ | ||
| 137 | #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ | ||
| 138 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ | ||
| 139 | |||
| 140 | #include "core_cm0plus.h" /* Core Peripheral Access Layer */ | ||
| 141 | #include "system_LPC844.h" /* Device specific configuration file */ | ||
| 142 | |||
| 143 | /*! | ||
| 144 | * @} | ||
| 145 | */ /* end of group Cortex_Core_Configuration */ | ||
| 146 | |||
| 147 | |||
| 148 | /* ---------------------------------------------------------------------------- | ||
| 149 | -- Mapping Information | ||
| 150 | ---------------------------------------------------------------------------- */ | ||
| 151 | |||
| 152 | /*! | ||
| 153 | * @addtogroup Mapping_Information Mapping Information | ||
| 154 | * @{ | ||
| 155 | */ | ||
| 156 | |||
| 157 | /** Mapping Information */ | ||
| 158 | /*! | ||
| 159 | * @addtogroup dma_request | ||
| 160 | * @{ | ||
| 161 | */ | ||
| 162 | |||
| 163 | /******************************************************************************* | ||
| 164 | * Definitions | ||
| 165 | ******************************************************************************/ | ||
| 166 | |||
| 167 | /*! | ||
| 168 | * @brief Structure for the DMA hardware request | ||
| 169 | * | ||
| 170 | * Defines the structure for the DMA hardware request collections. The user can configure the | ||
| 171 | * hardware request to trigger the DMA transfer accordingly. The index | ||
| 172 | * of the hardware request varies according to the to SoC. | ||
| 173 | */ | ||
| 174 | typedef enum _dma_request_source | ||
| 175 | { | ||
| 176 | kDmaRequestUSART0_RX_DMA = 0U, /**< USART0 RX DMA */ | ||
| 177 | kDmaRequestUSART0_TX_DMA = 1U, /**< USART0 TX DMA */ | ||
| 178 | kDmaRequestUSART1_RX_DMA = 2U, /**< USART1 RX DMA */ | ||
| 179 | kDmaRequestUSART1_TX_DMA = 3U, /**< USART1 TX DMA */ | ||
| 180 | kDmaRequestUSART2_RX_DMA = 4U, /**< USART2 RX DMA */ | ||
| 181 | kDmaRequestUSART2_TX_DMA = 5U, /**< USART2 TX DMA */ | ||
| 182 | kDmaRequestUSART3_RX_DMA = 6U, /**< USART3 RX DMA */ | ||
| 183 | kDmaRequestUSART3_TX_DMA = 7U, /**< USART3 TX DMA */ | ||
| 184 | kDmaRequestUSART4_RX_DMA = 8U, /**< USART4 RX DMA */ | ||
| 185 | kDmaRequestUSART4_TX_DMA = 9U, /**< USART4 TX DMA */ | ||
| 186 | kDmaRequestSPI0_RX_DMA = 10U, /**< SPI0 RX DMA */ | ||
| 187 | kDmaRequestSPI0_TX_DMA = 11U, /**< SPI0 TX DMA */ | ||
| 188 | kDmaRequestSPI1_RX_DMA = 12U, /**< SPI1 RX DMA */ | ||
| 189 | kDmaRequestSPI1_TX_DMA = 13U, /**< SPI1 TX DMA */ | ||
| 190 | kDmaRequestI2C0_SLV_DMA = 14U, /**< I2C0 SLAVE DMA */ | ||
| 191 | kDmaRequestI2C0_MST_DMA = 15U, /**< I2C0 MASTER DMA */ | ||
| 192 | kDmaRequestI2C1_SLV_DMA = 16U, /**< I2C1 SLAVE DMA */ | ||
| 193 | kDmaRequestI2C1_MST_DMA = 17U, /**< I2C1 MASTER DMA */ | ||
| 194 | kDmaRequestI2C2_SLV_DMA = 18U, /**< I2C2 SLAVE DMA */ | ||
| 195 | kDmaRequestI2C2_MST_DMA = 19U, /**< I2C2 MASTER DMA */ | ||
| 196 | kDmaRequestI2C3_SLV_DMA = 20U, /**< I2C3 SLAVE DMA */ | ||
| 197 | kDmaRequestI2C3_MST_DMA = 21U, /**< I2C3 MASTER DMA */ | ||
| 198 | kDmaRequestDAC0_DMAREQ = 22U, /**< DAC0 DMA REQUEST */ | ||
| 199 | kDmaRequestDAC1_DMAREQ = 23U, /**< DAC1 DMA REQUEST */ | ||
| 200 | kDmaRequestCAPT_DMA = 24U, /**< CAPT DMA */ | ||
| 201 | } dma_request_source_t; | ||
| 202 | |||
| 203 | /* @} */ | ||
| 204 | |||
| 205 | |||
| 206 | /*! | ||
| 207 | * @} | ||
| 208 | */ /* end of group Mapping_Information */ | ||
| 209 | |||
| 210 | |||
| 211 | /* ---------------------------------------------------------------------------- | ||
| 212 | -- Device Peripheral Access Layer | ||
| 213 | ---------------------------------------------------------------------------- */ | ||
| 214 | |||
| 215 | /*! | ||
| 216 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer | ||
| 217 | * @{ | ||
| 218 | */ | ||
| 219 | |||
| 220 | |||
| 221 | /* | ||
| 222 | ** Start of section using anonymous unions | ||
| 223 | */ | ||
| 224 | |||
| 225 | #if defined(__ARMCC_VERSION) | ||
| 226 | #if (__ARMCC_VERSION >= 6010050) | ||
| 227 | #pragma clang diagnostic push | ||
| 228 | #else | ||
| 229 | #pragma push | ||
| 230 | #pragma anon_unions | ||
| 231 | #endif | ||
| 232 | #elif defined(__GNUC__) | ||
| 233 | /* anonymous unions are enabled by default */ | ||
| 234 | #elif defined(__IAR_SYSTEMS_ICC__) | ||
| 235 | #pragma language=extended | ||
| 236 | #else | ||
| 237 | #error Not supported compiler type | ||
| 238 | #endif | ||
| 239 | |||
| 240 | /* ---------------------------------------------------------------------------- | ||
| 241 | -- ACOMP Peripheral Access Layer | ||
| 242 | ---------------------------------------------------------------------------- */ | ||
| 243 | |||
| 244 | /*! | ||
| 245 | * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer | ||
| 246 | * @{ | ||
| 247 | */ | ||
| 248 | |||
| 249 | /** ACOMP - Register Layout Typedef */ | ||
| 250 | typedef struct { | ||
| 251 | __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */ | ||
| 252 | __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */ | ||
| 253 | } ACOMP_Type; | ||
| 254 | |||
| 255 | /* ---------------------------------------------------------------------------- | ||
| 256 | -- ACOMP Register Masks | ||
| 257 | ---------------------------------------------------------------------------- */ | ||
| 258 | |||
| 259 | /*! | ||
| 260 | * @addtogroup ACOMP_Register_Masks ACOMP Register Masks | ||
| 261 | * @{ | ||
| 262 | */ | ||
| 263 | |||
| 264 | /*! @name CTRL - Comparator control register */ | ||
| 265 | /*! @{ */ | ||
| 266 | #define ACOMP_CTRL_EDGESEL_MASK (0x18U) | ||
| 267 | #define ACOMP_CTRL_EDGESEL_SHIFT (3U) | ||
| 268 | /*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): | ||
| 269 | * 0b00..Falling edges | ||
| 270 | * 0b01..Rising edges | ||
| 271 | * 0b10..Both edges | ||
| 272 | * 0b11..Both edges | ||
| 273 | */ | ||
| 274 | #define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK) | ||
| 275 | #define ACOMP_CTRL_COMPSA_MASK (0x40U) | ||
| 276 | #define ACOMP_CTRL_COMPSA_SHIFT (6U) | ||
| 277 | /*! COMPSA - Comparator output control | ||
| 278 | * 0b0..Comparator output is used directly. | ||
| 279 | * 0b1..Comparator output is synchronized to the bus clock for output to other modules. | ||
| 280 | */ | ||
| 281 | #define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK) | ||
| 282 | #define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U) | ||
| 283 | #define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U) | ||
| 284 | /*! COMP_VP_SEL - Selects positive voltage input | ||
| 285 | * 0b000..VOLTAGE_LADDER_OUTPUT | ||
| 286 | * 0b001..ACMP_I1 | ||
| 287 | * 0b010..ACMP_I2 | ||
| 288 | * 0b011..ACMP_I3 | ||
| 289 | * 0b100..ACMP_I4 | ||
| 290 | * 0b101..ACMP_I5 | ||
| 291 | * 0b110..Band gap. Internal reference voltage. | ||
| 292 | * 0b111..DAC0 output | ||
| 293 | */ | ||
| 294 | #define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK) | ||
| 295 | #define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U) | ||
| 296 | #define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U) | ||
| 297 | /*! COMP_VM_SEL - Selects negative voltage input | ||
| 298 | * 0b000..VOLTAGE_LADDER_OUTPUT | ||
| 299 | * 0b001..ACMP_I1 | ||
| 300 | * 0b010..ACMP_I2 | ||
| 301 | * 0b011..ACMP_I3 | ||
| 302 | * 0b100..ACMP_I4 | ||
| 303 | * 0b101..ACMP_I5 | ||
| 304 | * 0b110..Band gap. Internal reference voltage. | ||
| 305 | * 0b111..DAC0 output | ||
| 306 | */ | ||
| 307 | #define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK) | ||
| 308 | #define ACOMP_CTRL_EDGECLR_MASK (0x100000U) | ||
| 309 | #define ACOMP_CTRL_EDGECLR_SHIFT (20U) | ||
| 310 | /*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, | ||
| 311 | * toggle the EDGECLR bit by first writing a 1 and then a 0. | ||
| 312 | */ | ||
| 313 | #define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK) | ||
| 314 | #define ACOMP_CTRL_COMPSTAT_MASK (0x200000U) | ||
| 315 | #define ACOMP_CTRL_COMPSTAT_SHIFT (21U) | ||
| 316 | /*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output. | ||
| 317 | */ | ||
| 318 | #define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK) | ||
| 319 | #define ACOMP_CTRL_COMPEDGE_MASK (0x800000U) | ||
| 320 | #define ACOMP_CTRL_COMPEDGE_SHIFT (23U) | ||
| 321 | /*! COMPEDGE - Comparator edge-detect status. | ||
| 322 | */ | ||
| 323 | #define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK) | ||
| 324 | #define ACOMP_CTRL_INTENA_MASK (0x1000000U) | ||
| 325 | #define ACOMP_CTRL_INTENA_SHIFT (24U) | ||
| 326 | /*! INTENA - Must be set to generate interrupts. | ||
| 327 | */ | ||
| 328 | #define ACOMP_CTRL_INTENA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_INTENA_SHIFT)) & ACOMP_CTRL_INTENA_MASK) | ||
| 329 | #define ACOMP_CTRL_HYS_MASK (0x6000000U) | ||
| 330 | #define ACOMP_CTRL_HYS_SHIFT (25U) | ||
| 331 | /*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain | ||
| 332 | * state, this is the difference between the selected signals, in the opposite direction from the | ||
| 333 | * state being output, that will switch the output. | ||
| 334 | * 0b00..None (the output will switch as the voltages cross) | ||
| 335 | * 0b01..5 mv | ||
| 336 | * 0b10..10 mv | ||
| 337 | * 0b11..20 mv | ||
| 338 | */ | ||
| 339 | #define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK) | ||
| 340 | /*! @} */ | ||
| 341 | |||
| 342 | /*! @name LAD - Voltage ladder register */ | ||
| 343 | /*! @{ */ | ||
| 344 | #define ACOMP_LAD_LADEN_MASK (0x1U) | ||
| 345 | #define ACOMP_LAD_LADEN_SHIFT (0U) | ||
| 346 | /*! LADEN - Voltage ladder enable | ||
| 347 | */ | ||
| 348 | #define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK) | ||
| 349 | #define ACOMP_LAD_LADSEL_MASK (0x3EU) | ||
| 350 | #define ACOMP_LAD_LADSEL_SHIFT (1U) | ||
| 351 | /*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 | ||
| 352 | * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref | ||
| 353 | */ | ||
| 354 | #define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK) | ||
| 355 | #define ACOMP_LAD_LADREF_MASK (0x40U) | ||
| 356 | #define ACOMP_LAD_LADREF_SHIFT (6U) | ||
| 357 | /*! LADREF - Selects the reference voltage Vref for the voltage ladder. | ||
| 358 | * 0b0..Supply pin VDD | ||
| 359 | * 0b1..VDDCMP pin | ||
| 360 | */ | ||
| 361 | #define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK) | ||
| 362 | /*! @} */ | ||
| 363 | |||
| 364 | |||
| 365 | /*! | ||
| 366 | * @} | ||
| 367 | */ /* end of group ACOMP_Register_Masks */ | ||
| 368 | |||
| 369 | |||
| 370 | /* ACOMP - Peripheral instance base addresses */ | ||
| 371 | /** Peripheral ACOMP base address */ | ||
| 372 | #define ACOMP_BASE (0x40024000u) | ||
| 373 | /** Peripheral ACOMP base pointer */ | ||
| 374 | #define ACOMP ((ACOMP_Type *)ACOMP_BASE) | ||
| 375 | /** Array initializer of ACOMP peripheral base addresses */ | ||
| 376 | #define ACOMP_BASE_ADDRS { ACOMP_BASE } | ||
| 377 | /** Array initializer of ACOMP peripheral base pointers */ | ||
| 378 | #define ACOMP_BASE_PTRS { ACOMP } | ||
| 379 | /** Interrupt vectors for the ACOMP peripheral type */ | ||
| 380 | #define ACOMP_IRQS { CMP_CAPT_IRQn } | ||
| 381 | |||
| 382 | /*! | ||
| 383 | * @} | ||
| 384 | */ /* end of group ACOMP_Peripheral_Access_Layer */ | ||
| 385 | |||
| 386 | |||
| 387 | /* ---------------------------------------------------------------------------- | ||
| 388 | -- ADC Peripheral Access Layer | ||
| 389 | ---------------------------------------------------------------------------- */ | ||
| 390 | |||
| 391 | /*! | ||
| 392 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer | ||
| 393 | * @{ | ||
| 394 | */ | ||
| 395 | |||
| 396 | /** ADC - Register Layout Typedef */ | ||
| 397 | typedef struct { | ||
| 398 | __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ | ||
| 399 | uint8_t RESERVED_0[4]; | ||
| 400 | __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ | ||
| 401 | __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ | ||
| 402 | uint8_t RESERVED_1[8]; | ||
| 403 | __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */ | ||
| 404 | __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ | ||
| 405 | __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ | ||
| 406 | __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ | ||
| 407 | __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ | ||
| 408 | __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ | ||
| 409 | __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ | ||
| 410 | __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ | ||
| 411 | __IO uint32_t TRM; /**< ADC Startup register., offset: 0x6C */ | ||
| 412 | } ADC_Type; | ||
| 413 | |||
| 414 | /* ---------------------------------------------------------------------------- | ||
| 415 | -- ADC Register Masks | ||
| 416 | ---------------------------------------------------------------------------- */ | ||
| 417 | |||
| 418 | /*! | ||
| 419 | * @addtogroup ADC_Register_Masks ADC Register Masks | ||
| 420 | * @{ | ||
| 421 | */ | ||
| 422 | |||
| 423 | /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ | ||
| 424 | /*! @{ */ | ||
| 425 | #define ADC_CTRL_CLKDIV_MASK (0xFFU) | ||
| 426 | #define ADC_CTRL_CLKDIV_SHIFT (0U) | ||
| 427 | /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce | ||
| 428 | * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, | ||
| 429 | * software should program the smallest value in this field that yields this maximum clock rate or | ||
| 430 | * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may | ||
| 431 | * be desirable. This field is ignored in the asynchronous operating mode. | ||
| 432 | */ | ||
| 433 | #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) | ||
| 434 | #define ADC_CTRL_ASYNMODE_MASK (0x100U) | ||
| 435 | #define ADC_CTRL_ASYNMODE_SHIFT (8U) | ||
| 436 | /*! ASYNMODE - Select clock mode. | ||
| 437 | * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in | ||
| 438 | * the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to | ||
| 439 | * eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. | ||
| 440 | * In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC | ||
| 441 | * input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger | ||
| 442 | * pulse. | ||
| 443 | * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. | ||
| 444 | */ | ||
| 445 | #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) | ||
| 446 | #define ADC_CTRL_LPWRMODE_MASK (0x400U) | ||
| 447 | #define ADC_CTRL_LPWRMODE_SHIFT (10U) | ||
| 448 | /*! LPWRMODE - The low-power ADC mode | ||
| 449 | * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. | ||
| 450 | * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions | ||
| 451 | * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is | ||
| 452 | * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion | ||
| 453 | * completes, the analog-circuitry will again be powered-down provided no further conversions are pending. | ||
| 454 | * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are | ||
| 455 | * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 | ||
| 456 | * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger | ||
| 457 | * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the | ||
| 458 | * ADC_ENA bit is low. | ||
| 459 | */ | ||
| 460 | #define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK) | ||
| 461 | #define ADC_CTRL_CALMODE_MASK (0x40000000U) | ||
| 462 | #define ADC_CTRL_CALMODE_SHIFT (30U) | ||
| 463 | /*! CALMODE - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be | ||
| 464 | * automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of | ||
| 465 | * this register may be written to concurrently with setting this bit, however once this bit has | ||
| 466 | * been set no further writes to this register are permitted unitl the full calibration cycle has | ||
| 467 | * ended. | ||
| 468 | */ | ||
| 469 | #define ADC_CTRL_CALMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALMODE_SHIFT)) & ADC_CTRL_CALMODE_MASK) | ||
| 470 | /*! @} */ | ||
| 471 | |||
| 472 | /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ | ||
| 473 | /*! @{ */ | ||
| 474 | #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) | ||
| 475 | #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) | ||
| 476 | /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this | ||
| 477 | * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be | ||
| 478 | * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 | ||
| 479 | * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via | ||
| 480 | * software command, ADC conversions will be performed on each enabled channel, in sequence, | ||
| 481 | * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) | ||
| 482 | * is LOW. It is allowed to change this field and set bit 31 in the same write. | ||
| 483 | */ | ||
| 484 | #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) | ||
| 485 | #define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U) | ||
| 486 | #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) | ||
| 487 | /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion | ||
| 488 | * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order | ||
| 489 | * to avoid generating a spurious trigger, it is recommended writing to this field only when | ||
| 490 | * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. | ||
| 491 | */ | ||
| 492 | #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) | ||
| 493 | #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) | ||
| 494 | #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) | ||
| 495 | /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In | ||
| 496 | * order to avoid generating a spurious trigger, it is recommended writing to this field only when | ||
| 497 | * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. | ||
| 498 | * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. | ||
| 499 | * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. | ||
| 500 | */ | ||
| 501 | #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) | ||
| 502 | #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) | ||
| 503 | #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) | ||
| 504 | /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization | ||
| 505 | * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a | ||
| 506 | * conversion. There are slightly different criteria for whether or not this bit can be set | ||
| 507 | * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): | ||
| 508 | * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already | ||
| 509 | * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). | ||
| 510 | * Whether this bit is set or not, a trigger pulse must be maintained for at least one system | ||
| 511 | * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be | ||
| 512 | * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse | ||
| 513 | * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and | ||
| 514 | * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be | ||
| 515 | * maintained for one system clock period. | ||
| 516 | * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. | ||
| 517 | * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. | ||
| 518 | */ | ||
| 519 | #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) | ||
| 520 | #define ADC_SEQ_CTRL_START_MASK (0x4000000U) | ||
| 521 | #define ADC_SEQ_CTRL_START_SHIFT (26U) | ||
| 522 | /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The | ||
| 523 | * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this | ||
| 524 | * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a | ||
| 525 | * conversion sequence. It will consequently always read back as a zero. | ||
| 526 | */ | ||
| 527 | #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) | ||
| 528 | #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) | ||
| 529 | #define ADC_SEQ_CTRL_BURST_SHIFT (27U) | ||
| 530 | /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled | ||
| 531 | * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions | ||
| 532 | * can be halted by clearing this bit. The sequence currently in progress will be completed before | ||
| 533 | * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. | ||
| 534 | */ | ||
| 535 | #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) | ||
| 536 | #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) | ||
| 537 | #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) | ||
| 538 | /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a | ||
| 539 | * single conversion on the next channel in the sequence instead of the default response of | ||
| 540 | * launching an entire sequence of conversions. Once all of the channels comprising a sequence have | ||
| 541 | * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled | ||
| 542 | * channel. Interrupt generation will still occur either after each individual conversion or at | ||
| 543 | * the end of the entire sequence, depending on the state of the MODE bit. | ||
| 544 | */ | ||
| 545 | #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) | ||
| 546 | #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) | ||
| 547 | #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) | ||
| 548 | /*! LOWPRIO - Set priority for sequence A. | ||
| 549 | * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. | ||
| 550 | * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence | ||
| 551 | * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion | ||
| 552 | * currently in progress will be terminated. The A sequence that was interrupted will automatically resume | ||
| 553 | * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the | ||
| 554 | * conversion sequence will resume from that point. | ||
| 555 | */ | ||
| 556 | #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) | ||
| 557 | #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) | ||
| 558 | #define ADC_SEQ_CTRL_MODE_SHIFT (30U) | ||
| 559 | /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence | ||
| 560 | * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each | ||
| 561 | * conversion, or the individual channel result registers at the end of the entire sequence. Impacts | ||
| 562 | * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which | ||
| 563 | * overrun conditions contribute to an overrun interrupt as described below. | ||
| 564 | * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC | ||
| 565 | * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The | ||
| 566 | * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger | ||
| 567 | * if enabled. | ||
| 568 | * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A | ||
| 569 | * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in | ||
| 570 | * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun | ||
| 571 | * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. | ||
| 572 | */ | ||
| 573 | #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) | ||
| 574 | #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) | ||
| 575 | #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) | ||
| 576 | /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be | ||
| 577 | * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state | ||
| 578 | * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered | ||
| 579 | * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care | ||
| 580 | * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE | ||
| 581 | * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be | ||
| 582 | * triggered immediately upon being enabled. | ||
| 583 | * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence | ||
| 584 | * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is | ||
| 585 | * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. | ||
| 586 | * 0b1..Enabled. Sequence n is enabled. | ||
| 587 | */ | ||
| 588 | #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) | ||
| 589 | /*! @} */ | ||
| 590 | |||
| 591 | /* The count of ADC_SEQ_CTRL */ | ||
| 592 | #define ADC_SEQ_CTRL_COUNT (2U) | ||
| 593 | |||
| 594 | /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ | ||
| 595 | /*! @{ */ | ||
| 596 | #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) | ||
| 597 | #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) | ||
| 598 | /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion | ||
| 599 | * performed under conversion sequence associated with this register. The result is a binary | ||
| 600 | * fraction representing the voltage on the currently-selected input channel as it falls within the | ||
| 601 | * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less | ||
| 602 | * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input | ||
| 603 | * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this | ||
| 604 | * result has not yet been read. | ||
| 605 | */ | ||
| 606 | #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) | ||
| 607 | #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) | ||
| 608 | #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) | ||
| 609 | /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or | ||
| 610 | * within the range established by the designated threshold comparison registers (THRn_LOW and | ||
| 611 | * THRn_HIGH). | ||
| 612 | */ | ||
| 613 | #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) | ||
| 614 | #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) | ||
| 615 | #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) | ||
| 616 | /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a | ||
| 617 | * crossing of the threshold level established by the designated LOW threshold comparison register | ||
| 618 | * (THRn_LOW) and, if so, in what direction the crossing occurred. | ||
| 619 | */ | ||
| 620 | #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) | ||
| 621 | #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) | ||
| 622 | #define ADC_SEQ_GDAT_CHN_SHIFT (26U) | ||
| 623 | /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 | ||
| 624 | * identifies channel 0, 0001 channel 1, etc.). | ||
| 625 | */ | ||
| 626 | #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) | ||
| 627 | #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) | ||
| 628 | #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) | ||
| 629 | /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a | ||
| 630 | * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along | ||
| 631 | * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun | ||
| 632 | * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set | ||
| 633 | * to '0' (and if the overrun interrupt is enabled). | ||
| 634 | */ | ||
| 635 | #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) | ||
| 636 | #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) | ||
| 637 | #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) | ||
| 638 | /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded | ||
| 639 | * into the RESULT field. It is cleared whenever this register is read. This bit will cause a | ||
| 640 | * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that | ||
| 641 | * sequence is set to 0 (and if the interrupt is enabled). | ||
| 642 | */ | ||
| 643 | #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) | ||
| 644 | /*! @} */ | ||
| 645 | |||
| 646 | /* The count of ADC_SEQ_GDAT */ | ||
| 647 | #define ADC_SEQ_GDAT_COUNT (2U) | ||
| 648 | |||
| 649 | /*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */ | ||
| 650 | /*! @{ */ | ||
| 651 | #define ADC_DAT_RESULT_MASK (0xFFF0U) | ||
| 652 | #define ADC_DAT_RESULT_SHIFT (4U) | ||
| 653 | /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed | ||
| 654 | * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, | ||
| 655 | * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on | ||
| 656 | * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that | ||
| 657 | * the voltage on the input was close to, equal to, or greater than that on VREFP. | ||
| 658 | */ | ||
| 659 | #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) | ||
| 660 | #define ADC_DAT_THCMPRANGE_MASK (0x30000U) | ||
| 661 | #define ADC_DAT_THCMPRANGE_SHIFT (16U) | ||
| 662 | /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion | ||
| 663 | * was greater than or equal to the value programmed into the designated LOW threshold register | ||
| 664 | * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold | ||
| 665 | * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value | ||
| 666 | * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last | ||
| 667 | * completed conversion was greater than the value programmed into the designated HIGH threshold | ||
| 668 | * register (THRn_HIGH). 0x3 = Reserved. | ||
| 669 | */ | ||
| 670 | #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) | ||
| 671 | #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) | ||
| 672 | #define ADC_DAT_THCMPCROSS_SHIFT (18U) | ||
| 673 | /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The | ||
| 674 | * most recent completed conversion on this channel had the same relationship (above or below) to | ||
| 675 | * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the | ||
| 676 | * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing | ||
| 677 | * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the | ||
| 678 | * previous sample on this channel was above the threshold value established by the designated LOW | ||
| 679 | * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward | ||
| 680 | * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred | ||
| 681 | * - i.e. the previous sample on this channel was below the threshold value established by the | ||
| 682 | * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. | ||
| 683 | */ | ||
| 684 | #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) | ||
| 685 | #define ADC_DAT_CHANNEL_MASK (0x3C000000U) | ||
| 686 | #define ADC_DAT_CHANNEL_SHIFT (26U) | ||
| 687 | /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register | ||
| 688 | * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 | ||
| 689 | * register, etc) | ||
| 690 | */ | ||
| 691 | #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) | ||
| 692 | #define ADC_DAT_OVERRUN_MASK (0x40000000U) | ||
| 693 | #define ADC_DAT_OVERRUN_SHIFT (30U) | ||
| 694 | /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and | ||
| 695 | * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit | ||
| 696 | * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when | ||
| 697 | * the data related to this channel is read from either of the global SEQn_GDAT registers. This | ||
| 698 | * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if | ||
| 699 | * the overrun interrupt is enabled. While it is allowed to include the same channels in both | ||
| 700 | * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the | ||
| 701 | * data registers associated with any of the channels that are shared between the two sequences. Any | ||
| 702 | * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. | ||
| 703 | */ | ||
| 704 | #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) | ||
| 705 | #define ADC_DAT_DATAVALID_MASK (0x80000000U) | ||
| 706 | #define ADC_DAT_DATAVALID_SHIFT (31U) | ||
| 707 | /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is | ||
| 708 | * cleared whenever this register is read or when the data related to this channel is read from | ||
| 709 | * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in | ||
| 710 | * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in | ||
| 711 | * the data registers associated with any of the channels that are shared between the two | ||
| 712 | * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. | ||
| 713 | */ | ||
| 714 | #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) | ||
| 715 | /*! @} */ | ||
| 716 | |||
| 717 | /* The count of ADC_DAT */ | ||
| 718 | #define ADC_DAT_COUNT (12U) | ||
| 719 | |||
| 720 | /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ | ||
| 721 | /*! @{ */ | ||
| 722 | #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) | ||
| 723 | #define ADC_THR0_LOW_THRLOW_SHIFT (4U) | ||
| 724 | /*! THRLOW - Low threshold value against which ADC results will be compared | ||
| 725 | */ | ||
| 726 | #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) | ||
| 727 | /*! @} */ | ||
| 728 | |||
| 729 | /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ | ||
| 730 | /*! @{ */ | ||
| 731 | #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) | ||
| 732 | #define ADC_THR1_LOW_THRLOW_SHIFT (4U) | ||
| 733 | /*! THRLOW - Low threshold value against which ADC results will be compared | ||
| 734 | */ | ||
| 735 | #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) | ||
| 736 | /*! @} */ | ||
| 737 | |||
| 738 | /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ | ||
| 739 | /*! @{ */ | ||
| 740 | #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) | ||
| 741 | #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) | ||
| 742 | /*! THRHIGH - High threshold value against which ADC results will be compared | ||
| 743 | */ | ||
| 744 | #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) | ||
| 745 | /*! @} */ | ||
| 746 | |||
| 747 | /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ | ||
| 748 | /*! @{ */ | ||
| 749 | #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) | ||
| 750 | #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) | ||
| 751 | /*! THRHIGH - High threshold value against which ADC results will be compared | ||
| 752 | */ | ||
| 753 | #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) | ||
| 754 | /*! @} */ | ||
| 755 | |||
| 756 | /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ | ||
| 757 | /*! @{ */ | ||
| 758 | #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) | ||
| 759 | #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) | ||
| 760 | /*! CH0_THRSEL - Threshold select for channel 0. | ||
| 761 | * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. | ||
| 762 | * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. | ||
| 763 | */ | ||
| 764 | #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) | ||
| 765 | #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) | ||
| 766 | #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) | ||
| 767 | /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. | ||
| 768 | */ | ||
| 769 | #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) | ||
| 770 | #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) | ||
| 771 | #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) | ||
| 772 | /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. | ||
| 773 | */ | ||
| 774 | #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) | ||
| 775 | #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) | ||
| 776 | #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) | ||
| 777 | /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. | ||
| 778 | */ | ||
| 779 | #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) | ||
| 780 | #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) | ||
| 781 | #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) | ||
| 782 | /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. | ||
| 783 | */ | ||
| 784 | #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) | ||
| 785 | #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) | ||
| 786 | #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) | ||
| 787 | /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. | ||
| 788 | */ | ||
| 789 | #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) | ||
| 790 | #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) | ||
| 791 | #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) | ||
| 792 | /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. | ||
| 793 | */ | ||
| 794 | #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) | ||
| 795 | #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) | ||
| 796 | #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) | ||
| 797 | /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. | ||
| 798 | */ | ||
| 799 | #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) | ||
| 800 | #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) | ||
| 801 | #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) | ||
| 802 | /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. | ||
| 803 | */ | ||
| 804 | #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) | ||
| 805 | #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) | ||
| 806 | #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) | ||
| 807 | /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. | ||
| 808 | */ | ||
| 809 | #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) | ||
| 810 | #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) | ||
| 811 | #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) | ||
| 812 | /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. | ||
| 813 | */ | ||
| 814 | #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) | ||
| 815 | #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) | ||
| 816 | #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) | ||
| 817 | /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. | ||
| 818 | */ | ||
| 819 | #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) | ||
| 820 | /*! @} */ | ||
| 821 | |||
| 822 | /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ | ||
| 823 | /*! @{ */ | ||
| 824 | #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) | ||
| 825 | #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) | ||
| 826 | /*! SEQA_INTEN - Sequence A interrupt enable. | ||
| 827 | * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. | ||
| 828 | * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of | ||
| 829 | * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of | ||
| 830 | * conversions, depending on the MODE bit in the SEQA_CTRL register. | ||
| 831 | */ | ||
| 832 | #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) | ||
| 833 | #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) | ||
| 834 | #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) | ||
| 835 | /*! SEQB_INTEN - Sequence B interrupt enable. | ||
| 836 | * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. | ||
| 837 | * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of | ||
| 838 | * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of | ||
| 839 | * conversions, depending on the MODE bit in the SEQB_CTRL register. | ||
| 840 | */ | ||
| 841 | #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) | ||
| 842 | #define ADC_INTEN_OVR_INTEN_MASK (0x4U) | ||
| 843 | #define ADC_INTEN_OVR_INTEN_SHIFT (2U) | ||
| 844 | /*! OVR_INTEN - Overrun interrupt enable. | ||
| 845 | * 0b0..Disabled. The overrun interrupt is disabled. | ||
| 846 | * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel | ||
| 847 | * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular | ||
| 848 | * sequence is 0, then an overrun in the global data register for that sequence will also cause this | ||
| 849 | * interrupt/DMA trigger to be asserted. | ||
| 850 | */ | ||
| 851 | #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) | ||
| 852 | #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) | ||
| 853 | #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) | ||
| 854 | /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. | ||
| 855 | * 0b00..Disabled. | ||
| 856 | * 0b01..Outside threshold. | ||
| 857 | * 0b10..Crossing threshold. | ||
| 858 | * 0b11..Reserved | ||
| 859 | */ | ||
| 860 | #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) | ||
| 861 | #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) | ||
| 862 | #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) | ||
| 863 | /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. | ||
| 864 | */ | ||
| 865 | #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) | ||
| 866 | #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) | ||
| 867 | #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) | ||
| 868 | /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. | ||
| 869 | */ | ||
| 870 | #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) | ||
| 871 | #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) | ||
| 872 | #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) | ||
| 873 | /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. | ||
| 874 | */ | ||
| 875 | #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) | ||
| 876 | #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) | ||
| 877 | #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) | ||
| 878 | /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. | ||
| 879 | */ | ||
| 880 | #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) | ||
| 881 | #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) | ||
| 882 | #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) | ||
| 883 | /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. | ||
| 884 | */ | ||
| 885 | #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) | ||
| 886 | #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) | ||
| 887 | #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) | ||
| 888 | /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. | ||
| 889 | */ | ||
| 890 | #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) | ||
| 891 | #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) | ||
| 892 | #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) | ||
| 893 | /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. | ||
| 894 | */ | ||
| 895 | #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) | ||
| 896 | #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) | ||
| 897 | #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) | ||
| 898 | /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. | ||
| 899 | */ | ||
| 900 | #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) | ||
| 901 | #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) | ||
| 902 | #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) | ||
| 903 | /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. | ||
| 904 | */ | ||
| 905 | #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) | ||
| 906 | #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) | ||
| 907 | #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) | ||
| 908 | /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. | ||
| 909 | */ | ||
| 910 | #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) | ||
| 911 | #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) | ||
| 912 | #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) | ||
| 913 | /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. | ||
| 914 | */ | ||
| 915 | #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) | ||
| 916 | /*! @} */ | ||
| 917 | |||
| 918 | /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ | ||
| 919 | /*! @{ */ | ||
| 920 | #define ADC_FLAGS_THCMP0_MASK (0x1U) | ||
| 921 | #define ADC_FLAGS_THCMP0_SHIFT (0U) | ||
| 922 | /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or | ||
| 923 | * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by | ||
| 924 | * writing a 1. | ||
| 925 | */ | ||
| 926 | #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) | ||
| 927 | #define ADC_FLAGS_THCMP1_MASK (0x2U) | ||
| 928 | #define ADC_FLAGS_THCMP1_SHIFT (1U) | ||
| 929 | /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. | ||
| 930 | */ | ||
| 931 | #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) | ||
| 932 | #define ADC_FLAGS_THCMP2_MASK (0x4U) | ||
| 933 | #define ADC_FLAGS_THCMP2_SHIFT (2U) | ||
| 934 | /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. | ||
| 935 | */ | ||
| 936 | #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) | ||
| 937 | #define ADC_FLAGS_THCMP3_MASK (0x8U) | ||
| 938 | #define ADC_FLAGS_THCMP3_SHIFT (3U) | ||
| 939 | /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. | ||
| 940 | */ | ||
| 941 | #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) | ||
| 942 | #define ADC_FLAGS_THCMP4_MASK (0x10U) | ||
| 943 | #define ADC_FLAGS_THCMP4_SHIFT (4U) | ||
| 944 | /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. | ||
| 945 | */ | ||
| 946 | #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) | ||
| 947 | #define ADC_FLAGS_THCMP5_MASK (0x20U) | ||
| 948 | #define ADC_FLAGS_THCMP5_SHIFT (5U) | ||
| 949 | /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. | ||
| 950 | */ | ||
| 951 | #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) | ||
| 952 | #define ADC_FLAGS_THCMP6_MASK (0x40U) | ||
| 953 | #define ADC_FLAGS_THCMP6_SHIFT (6U) | ||
| 954 | /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. | ||
| 955 | */ | ||
| 956 | #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) | ||
| 957 | #define ADC_FLAGS_THCMP7_MASK (0x80U) | ||
| 958 | #define ADC_FLAGS_THCMP7_SHIFT (7U) | ||
| 959 | /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. | ||
| 960 | */ | ||
| 961 | #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) | ||
| 962 | #define ADC_FLAGS_THCMP8_MASK (0x100U) | ||
| 963 | #define ADC_FLAGS_THCMP8_SHIFT (8U) | ||
| 964 | /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. | ||
| 965 | */ | ||
| 966 | #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) | ||
| 967 | #define ADC_FLAGS_THCMP9_MASK (0x200U) | ||
| 968 | #define ADC_FLAGS_THCMP9_SHIFT (9U) | ||
| 969 | /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. | ||
| 970 | */ | ||
| 971 | #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) | ||
| 972 | #define ADC_FLAGS_THCMP10_MASK (0x400U) | ||
| 973 | #define ADC_FLAGS_THCMP10_SHIFT (10U) | ||
| 974 | /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. | ||
| 975 | */ | ||
| 976 | #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) | ||
| 977 | #define ADC_FLAGS_THCMP11_MASK (0x800U) | ||
| 978 | #define ADC_FLAGS_THCMP11_SHIFT (11U) | ||
| 979 | /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. | ||
| 980 | */ | ||
| 981 | #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) | ||
| 982 | #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) | ||
| 983 | #define ADC_FLAGS_OVERRUN0_SHIFT (12U) | ||
| 984 | /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 | ||
| 985 | */ | ||
| 986 | #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) | ||
| 987 | #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) | ||
| 988 | #define ADC_FLAGS_OVERRUN1_SHIFT (13U) | ||
| 989 | /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 | ||
| 990 | */ | ||
| 991 | #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) | ||
| 992 | #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) | ||
| 993 | #define ADC_FLAGS_OVERRUN2_SHIFT (14U) | ||
| 994 | /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 | ||
| 995 | */ | ||
| 996 | #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) | ||
| 997 | #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) | ||
| 998 | #define ADC_FLAGS_OVERRUN3_SHIFT (15U) | ||
| 999 | /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 | ||
| 1000 | */ | ||
| 1001 | #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) | ||
| 1002 | #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) | ||
| 1003 | #define ADC_FLAGS_OVERRUN4_SHIFT (16U) | ||
| 1004 | /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 | ||
| 1005 | */ | ||
| 1006 | #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) | ||
| 1007 | #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) | ||
| 1008 | #define ADC_FLAGS_OVERRUN5_SHIFT (17U) | ||
| 1009 | /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 | ||
| 1010 | */ | ||
| 1011 | #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) | ||
| 1012 | #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) | ||
| 1013 | #define ADC_FLAGS_OVERRUN6_SHIFT (18U) | ||
| 1014 | /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 | ||
| 1015 | */ | ||
| 1016 | #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) | ||
| 1017 | #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) | ||
| 1018 | #define ADC_FLAGS_OVERRUN7_SHIFT (19U) | ||
| 1019 | /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 | ||
| 1020 | */ | ||
| 1021 | #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) | ||
| 1022 | #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) | ||
| 1023 | #define ADC_FLAGS_OVERRUN8_SHIFT (20U) | ||
| 1024 | /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 | ||
| 1025 | */ | ||
| 1026 | #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) | ||
| 1027 | #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) | ||
| 1028 | #define ADC_FLAGS_OVERRUN9_SHIFT (21U) | ||
| 1029 | /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 | ||
| 1030 | */ | ||
| 1031 | #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) | ||
| 1032 | #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) | ||
| 1033 | #define ADC_FLAGS_OVERRUN10_SHIFT (22U) | ||
| 1034 | /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 | ||
| 1035 | */ | ||
| 1036 | #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) | ||
| 1037 | #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) | ||
| 1038 | #define ADC_FLAGS_OVERRUN11_SHIFT (23U) | ||
| 1039 | /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 | ||
| 1040 | */ | ||
| 1041 | #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) | ||
| 1042 | #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) | ||
| 1043 | #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) | ||
| 1044 | /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register | ||
| 1045 | */ | ||
| 1046 | #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) | ||
| 1047 | #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) | ||
| 1048 | #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) | ||
| 1049 | /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register | ||
| 1050 | */ | ||
| 1051 | #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) | ||
| 1052 | #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) | ||
| 1053 | #define ADC_FLAGS_SEQA_INT_SHIFT (28U) | ||
| 1054 | /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, | ||
| 1055 | * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which | ||
| 1056 | * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared | ||
| 1057 | * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register | ||
| 1058 | * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be | ||
| 1059 | * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN | ||
| 1060 | * register. | ||
| 1061 | */ | ||
| 1062 | #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) | ||
| 1063 | #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) | ||
| 1064 | #define ADC_FLAGS_SEQB_INT_SHIFT (29U) | ||
| 1065 | /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, | ||
| 1066 | * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which | ||
| 1067 | * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared | ||
| 1068 | * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register | ||
| 1069 | * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be | ||
| 1070 | * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN | ||
| 1071 | * register. | ||
| 1072 | */ | ||
| 1073 | #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) | ||
| 1074 | #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) | ||
| 1075 | #define ADC_FLAGS_THCMP_INT_SHIFT (30U) | ||
| 1076 | /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in | ||
| 1077 | * the lower bits of this register are set to 1 (due to an enabled out-of-range or | ||
| 1078 | * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be | ||
| 1079 | * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared | ||
| 1080 | * when all of the individual threshold flags are cleared via writing 1s to those bits. | ||
| 1081 | */ | ||
| 1082 | #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) | ||
| 1083 | #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) | ||
| 1084 | #define ADC_FLAGS_OVR_INT_SHIFT (31U) | ||
| 1085 | /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data | ||
| 1086 | * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers | ||
| 1087 | * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this | ||
| 1088 | * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all | ||
| 1089 | * of the individual overrun bits have been cleared via reading the corresponding data registers. | ||
| 1090 | */ | ||
| 1091 | #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) | ||
| 1092 | /*! @} */ | ||
| 1093 | |||
| 1094 | /*! @name TRM - ADC Startup register. */ | ||
| 1095 | /*! @{ */ | ||
| 1096 | #define ADC_TRM_VRANGE_MASK (0x20U) | ||
| 1097 | #define ADC_TRM_VRANGE_SHIFT (5U) | ||
| 1098 | /*! VRANGE - 1.8V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be | ||
| 1099 | * used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be | ||
| 1100 | * spec'd on parts that do not support operation below 2.7V | ||
| 1101 | */ | ||
| 1102 | #define ADC_TRM_VRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TRM_VRANGE_SHIFT)) & ADC_TRM_VRANGE_MASK) | ||
| 1103 | /*! @} */ | ||
| 1104 | |||
| 1105 | |||
| 1106 | /*! | ||
| 1107 | * @} | ||
| 1108 | */ /* end of group ADC_Register_Masks */ | ||
| 1109 | |||
| 1110 | |||
| 1111 | /* ADC - Peripheral instance base addresses */ | ||
| 1112 | /** Peripheral ADC0 base address */ | ||
| 1113 | #define ADC0_BASE (0x4001C000u) | ||
| 1114 | /** Peripheral ADC0 base pointer */ | ||
| 1115 | #define ADC0 ((ADC_Type *)ADC0_BASE) | ||
| 1116 | /** Array initializer of ADC peripheral base addresses */ | ||
| 1117 | #define ADC_BASE_ADDRS { ADC0_BASE } | ||
| 1118 | /** Array initializer of ADC peripheral base pointers */ | ||
| 1119 | #define ADC_BASE_PTRS { ADC0 } | ||
| 1120 | /** Interrupt vectors for the ADC peripheral type */ | ||
| 1121 | #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } | ||
| 1122 | #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } | ||
| 1123 | |||
| 1124 | /*! | ||
| 1125 | * @} | ||
| 1126 | */ /* end of group ADC_Peripheral_Access_Layer */ | ||
| 1127 | |||
| 1128 | |||
| 1129 | /* ---------------------------------------------------------------------------- | ||
| 1130 | -- CRC Peripheral Access Layer | ||
| 1131 | ---------------------------------------------------------------------------- */ | ||
| 1132 | |||
| 1133 | /*! | ||
| 1134 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer | ||
| 1135 | * @{ | ||
| 1136 | */ | ||
| 1137 | |||
| 1138 | /** CRC - Register Layout Typedef */ | ||
| 1139 | typedef struct { | ||
| 1140 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ | ||
| 1141 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ | ||
| 1142 | union { /* offset: 0x8 */ | ||
| 1143 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ | ||
| 1144 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ | ||
| 1145 | }; | ||
| 1146 | } CRC_Type; | ||
| 1147 | |||
| 1148 | /* ---------------------------------------------------------------------------- | ||
| 1149 | -- CRC Register Masks | ||
| 1150 | ---------------------------------------------------------------------------- */ | ||
| 1151 | |||
| 1152 | /*! | ||
| 1153 | * @addtogroup CRC_Register_Masks CRC Register Masks | ||
| 1154 | * @{ | ||
| 1155 | */ | ||
| 1156 | |||
| 1157 | /*! @name MODE - CRC mode register */ | ||
| 1158 | /*! @{ */ | ||
| 1159 | #define CRC_MODE_CRC_POLY_MASK (0x3U) | ||
| 1160 | #define CRC_MODE_CRC_POLY_SHIFT (0U) | ||
| 1161 | /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial | ||
| 1162 | */ | ||
| 1163 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) | ||
| 1164 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) | ||
| 1165 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) | ||
| 1166 | /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) | ||
| 1167 | */ | ||
| 1168 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) | ||
| 1169 | #define CRC_MODE_CMPL_WR_MASK (0x8U) | ||
| 1170 | #define CRC_MODE_CMPL_WR_SHIFT (3U) | ||
| 1171 | /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA | ||
| 1172 | */ | ||
| 1173 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) | ||
| 1174 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) | ||
| 1175 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) | ||
| 1176 | /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM | ||
| 1177 | */ | ||
| 1178 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) | ||
| 1179 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) | ||
| 1180 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) | ||
| 1181 | /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM | ||
| 1182 | */ | ||
| 1183 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) | ||
| 1184 | /*! @} */ | ||
| 1185 | |||
| 1186 | /*! @name SEED - CRC seed register */ | ||
| 1187 | /*! @{ */ | ||
| 1188 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) | ||
| 1189 | #define CRC_SEED_CRC_SEED_SHIFT (0U) | ||
| 1190 | /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with | ||
| 1191 | * selected bit order and 1's complement pre-processes. A write access to this register will | ||
| 1192 | * overrule the CRC calculation in progresses. | ||
| 1193 | */ | ||
| 1194 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) | ||
| 1195 | /*! @} */ | ||
| 1196 | |||
| 1197 | /*! @name SUM - CRC checksum register */ | ||
| 1198 | /*! @{ */ | ||
| 1199 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) | ||
| 1200 | #define CRC_SUM_CRC_SUM_SHIFT (0U) | ||
| 1201 | /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. | ||
| 1202 | */ | ||
| 1203 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) | ||
| 1204 | /*! @} */ | ||
| 1205 | |||
| 1206 | /*! @name WR_DATA - CRC data register */ | ||
| 1207 | /*! @{ */ | ||
| 1208 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) | ||
| 1209 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) | ||
| 1210 | /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with | ||
| 1211 | * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and | ||
| 1212 | * accept back-to-back transactions. | ||
| 1213 | */ | ||
| 1214 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) | ||
| 1215 | /*! @} */ | ||
| 1216 | |||
| 1217 | |||
| 1218 | /*! | ||
| 1219 | * @} | ||
| 1220 | */ /* end of group CRC_Register_Masks */ | ||
| 1221 | |||
| 1222 | |||
| 1223 | /* CRC - Peripheral instance base addresses */ | ||
| 1224 | /** Peripheral CRC base address */ | ||
| 1225 | #define CRC_BASE (0x50000000u) | ||
| 1226 | /** Peripheral CRC base pointer */ | ||
| 1227 | #define CRC ((CRC_Type *)CRC_BASE) | ||
| 1228 | /** Array initializer of CRC peripheral base addresses */ | ||
| 1229 | #define CRC_BASE_ADDRS { CRC_BASE } | ||
| 1230 | /** Array initializer of CRC peripheral base pointers */ | ||
| 1231 | #define CRC_BASE_PTRS { CRC } | ||
| 1232 | |||
| 1233 | /*! | ||
| 1234 | * @} | ||
| 1235 | */ /* end of group CRC_Peripheral_Access_Layer */ | ||
| 1236 | |||
| 1237 | |||
| 1238 | /* ---------------------------------------------------------------------------- | ||
| 1239 | -- CTIMER Peripheral Access Layer | ||
| 1240 | ---------------------------------------------------------------------------- */ | ||
| 1241 | |||
| 1242 | /*! | ||
| 1243 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer | ||
| 1244 | * @{ | ||
| 1245 | */ | ||
| 1246 | |||
| 1247 | /** CTIMER - Register Layout Typedef */ | ||
| 1248 | typedef struct { | ||
| 1249 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ | ||
| 1250 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ | ||
| 1251 | __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ | ||
| 1252 | __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ | ||
| 1253 | __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ | ||
| 1254 | __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ | ||
| 1255 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ | ||
| 1256 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ | ||
| 1257 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ | ||
| 1258 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ | ||
| 1259 | uint8_t RESERVED_0[48]; | ||
| 1260 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ | ||
| 1261 | __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ | ||
| 1262 | __IO uint32_t MSR[4]; /**< Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero., array offset: 0x78, array step: 0x4 */ | ||
| 1263 | } CTIMER_Type; | ||
| 1264 | |||
| 1265 | /* ---------------------------------------------------------------------------- | ||
| 1266 | -- CTIMER Register Masks | ||
| 1267 | ---------------------------------------------------------------------------- */ | ||
| 1268 | |||
| 1269 | /*! | ||
| 1270 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks | ||
| 1271 | * @{ | ||
| 1272 | */ | ||
| 1273 | |||
| 1274 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ | ||
| 1275 | /*! @{ */ | ||
| 1276 | #define CTIMER_IR_MR0INT_MASK (0x1U) | ||
| 1277 | #define CTIMER_IR_MR0INT_SHIFT (0U) | ||
| 1278 | /*! MR0INT - Interrupt flag for match channel 0. | ||
| 1279 | */ | ||
| 1280 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) | ||
| 1281 | #define CTIMER_IR_MR1INT_MASK (0x2U) | ||
| 1282 | #define CTIMER_IR_MR1INT_SHIFT (1U) | ||
| 1283 | /*! MR1INT - Interrupt flag for match channel 1. | ||
| 1284 | */ | ||
| 1285 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) | ||
| 1286 | #define CTIMER_IR_MR2INT_MASK (0x4U) | ||
| 1287 | #define CTIMER_IR_MR2INT_SHIFT (2U) | ||
| 1288 | /*! MR2INT - Interrupt flag for match channel 2. | ||
| 1289 | */ | ||
| 1290 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) | ||
| 1291 | #define CTIMER_IR_MR3INT_MASK (0x8U) | ||
| 1292 | #define CTIMER_IR_MR3INT_SHIFT (3U) | ||
| 1293 | /*! MR3INT - Interrupt flag for match channel 3. | ||
| 1294 | */ | ||
| 1295 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) | ||
| 1296 | #define CTIMER_IR_CR0INT_MASK (0x10U) | ||
| 1297 | #define CTIMER_IR_CR0INT_SHIFT (4U) | ||
| 1298 | /*! CR0INT - Interrupt flag for capture channel 0 event. | ||
| 1299 | */ | ||
| 1300 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) | ||
| 1301 | #define CTIMER_IR_CR1INT_MASK (0x20U) | ||
| 1302 | #define CTIMER_IR_CR1INT_SHIFT (5U) | ||
| 1303 | /*! CR1INT - Interrupt flag for capture channel 1 event. | ||
| 1304 | */ | ||
| 1305 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) | ||
| 1306 | #define CTIMER_IR_CR2INT_MASK (0x40U) | ||
| 1307 | #define CTIMER_IR_CR2INT_SHIFT (6U) | ||
| 1308 | /*! CR2INT - Interrupt flag for capture channel 2 event. | ||
| 1309 | */ | ||
| 1310 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) | ||
| 1311 | #define CTIMER_IR_CR3INT_MASK (0x80U) | ||
| 1312 | #define CTIMER_IR_CR3INT_SHIFT (7U) | ||
| 1313 | /*! CR3INT - Interrupt flag for capture channel 3 event. | ||
| 1314 | */ | ||
| 1315 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) | ||
| 1316 | /*! @} */ | ||
| 1317 | |||
| 1318 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ | ||
| 1319 | /*! @{ */ | ||
| 1320 | #define CTIMER_TCR_CEN_MASK (0x1U) | ||
| 1321 | #define CTIMER_TCR_CEN_SHIFT (0U) | ||
| 1322 | /*! CEN - Counter enable. | ||
| 1323 | * 0b0..Disabled.The counters are disabled. | ||
| 1324 | * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. | ||
| 1325 | */ | ||
| 1326 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) | ||
| 1327 | #define CTIMER_TCR_CRST_MASK (0x2U) | ||
| 1328 | #define CTIMER_TCR_CRST_SHIFT (1U) | ||
| 1329 | /*! CRST - Counter reset. | ||
| 1330 | * 0b0..Disabled. Do nothing. | ||
| 1331 | * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of | ||
| 1332 | * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. | ||
| 1333 | */ | ||
| 1334 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) | ||
| 1335 | /*! @} */ | ||
| 1336 | |||
| 1337 | /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ | ||
| 1338 | /*! @{ */ | ||
| 1339 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) | ||
| 1340 | #define CTIMER_TC_TCVAL_SHIFT (0U) | ||
| 1341 | /*! TCVAL - Timer counter value. | ||
| 1342 | */ | ||
| 1343 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) | ||
| 1344 | /*! @} */ | ||
| 1345 | |||
| 1346 | /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ | ||
| 1347 | /*! @{ */ | ||
| 1348 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) | ||
| 1349 | #define CTIMER_PR_PRVAL_SHIFT (0U) | ||
| 1350 | /*! PRVAL - Prescale counter value. | ||
| 1351 | */ | ||
| 1352 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) | ||
| 1353 | /*! @} */ | ||
| 1354 | |||
| 1355 | /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ | ||
| 1356 | /*! @{ */ | ||
| 1357 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) | ||
| 1358 | #define CTIMER_PC_PCVAL_SHIFT (0U) | ||
| 1359 | /*! PCVAL - Prescale counter value. | ||
| 1360 | */ | ||
| 1361 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) | ||
| 1362 | /*! @} */ | ||
| 1363 | |||
| 1364 | /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ | ||
| 1365 | /*! @{ */ | ||
| 1366 | #define CTIMER_MCR_MR0I_MASK (0x1U) | ||
| 1367 | #define CTIMER_MCR_MR0I_SHIFT (0U) | ||
| 1368 | /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. | ||
| 1369 | */ | ||
| 1370 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) | ||
| 1371 | #define CTIMER_MCR_MR0R_MASK (0x2U) | ||
| 1372 | #define CTIMER_MCR_MR0R_SHIFT (1U) | ||
| 1373 | /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. | ||
| 1374 | */ | ||
| 1375 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) | ||
| 1376 | #define CTIMER_MCR_MR0S_MASK (0x4U) | ||
| 1377 | #define CTIMER_MCR_MR0S_SHIFT (2U) | ||
| 1378 | /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. | ||
| 1379 | */ | ||
| 1380 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) | ||
| 1381 | #define CTIMER_MCR_MR1I_MASK (0x8U) | ||
| 1382 | #define CTIMER_MCR_MR1I_SHIFT (3U) | ||
| 1383 | /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = | ||
| 1384 | * disabled. 1 = enabled. 0 = disabled. 1 = enabled. | ||
| 1385 | */ | ||
| 1386 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) | ||
| 1387 | #define CTIMER_MCR_MR1R_MASK (0x10U) | ||
| 1388 | #define CTIMER_MCR_MR1R_SHIFT (4U) | ||
| 1389 | /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. | ||
| 1390 | */ | ||
| 1391 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) | ||
| 1392 | #define CTIMER_MCR_MR1S_MASK (0x20U) | ||
| 1393 | #define CTIMER_MCR_MR1S_SHIFT (5U) | ||
| 1394 | /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. | ||
| 1395 | */ | ||
| 1396 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) | ||
| 1397 | #define CTIMER_MCR_MR2I_MASK (0x40U) | ||
| 1398 | #define CTIMER_MCR_MR2I_SHIFT (6U) | ||
| 1399 | /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. | ||
| 1400 | */ | ||
| 1401 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) | ||
| 1402 | #define CTIMER_MCR_MR2R_MASK (0x80U) | ||
| 1403 | #define CTIMER_MCR_MR2R_SHIFT (7U) | ||
| 1404 | /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. | ||
| 1405 | */ | ||
| 1406 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) | ||
| 1407 | #define CTIMER_MCR_MR2S_MASK (0x100U) | ||
| 1408 | #define CTIMER_MCR_MR2S_SHIFT (8U) | ||
| 1409 | /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. | ||
| 1410 | */ | ||
| 1411 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) | ||
| 1412 | #define CTIMER_MCR_MR3I_MASK (0x200U) | ||
| 1413 | #define CTIMER_MCR_MR3I_SHIFT (9U) | ||
| 1414 | /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. | ||
| 1415 | */ | ||
| 1416 | #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) | ||
| 1417 | #define CTIMER_MCR_MR3R_MASK (0x400U) | ||
| 1418 | #define CTIMER_MCR_MR3R_SHIFT (10U) | ||
| 1419 | /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. | ||
| 1420 | */ | ||
| 1421 | #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) | ||
| 1422 | #define CTIMER_MCR_MR3S_MASK (0x800U) | ||
| 1423 | #define CTIMER_MCR_MR3S_SHIFT (11U) | ||
| 1424 | /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. | ||
| 1425 | */ | ||
| 1426 | #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) | ||
| 1427 | #define CTIMER_MCR_MR0RL_MASK (0x1000000U) | ||
| 1428 | #define CTIMER_MCR_MR0RL_SHIFT (24U) | ||
| 1429 | /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero | ||
| 1430 | * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. | ||
| 1431 | */ | ||
| 1432 | #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) | ||
| 1433 | #define CTIMER_MCR_MR1RL_MASK (0x2000000U) | ||
| 1434 | #define CTIMER_MCR_MR1RL_SHIFT (25U) | ||
| 1435 | /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero | ||
| 1436 | * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. | ||
| 1437 | */ | ||
| 1438 | #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) | ||
| 1439 | #define CTIMER_MCR_MR2RL_MASK (0x4000000U) | ||
| 1440 | #define CTIMER_MCR_MR2RL_SHIFT (26U) | ||
| 1441 | /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero | ||
| 1442 | * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. | ||
| 1443 | */ | ||
| 1444 | #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) | ||
| 1445 | #define CTIMER_MCR_MR3RL_MASK (0x8000000U) | ||
| 1446 | #define CTIMER_MCR_MR3RL_SHIFT (27U) | ||
| 1447 | /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero | ||
| 1448 | * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. | ||
| 1449 | */ | ||
| 1450 | #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) | ||
| 1451 | /*! @} */ | ||
| 1452 | |||
| 1453 | /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ | ||
| 1454 | /*! @{ */ | ||
| 1455 | #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) | ||
| 1456 | #define CTIMER_MR_MATCH_SHIFT (0U) | ||
| 1457 | /*! MATCH - Timer counter match value. | ||
| 1458 | */ | ||
| 1459 | #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) | ||
| 1460 | /*! @} */ | ||
| 1461 | |||
| 1462 | /* The count of CTIMER_MR */ | ||
| 1463 | #define CTIMER_MR_COUNT (4U) | ||
| 1464 | |||
| 1465 | /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ | ||
| 1466 | /*! @{ */ | ||
| 1467 | #define CTIMER_CCR_CAP0RE_MASK (0x1U) | ||
| 1468 | #define CTIMER_CCR_CAP0RE_SHIFT (0U) | ||
| 1469 | /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with | ||
| 1470 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1471 | */ | ||
| 1472 | #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) | ||
| 1473 | #define CTIMER_CCR_CAP0FE_MASK (0x2U) | ||
| 1474 | #define CTIMER_CCR_CAP0FE_SHIFT (1U) | ||
| 1475 | /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with | ||
| 1476 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1477 | */ | ||
| 1478 | #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) | ||
| 1479 | #define CTIMER_CCR_CAP0I_MASK (0x4U) | ||
| 1480 | #define CTIMER_CCR_CAP0I_SHIFT (2U) | ||
| 1481 | /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. | ||
| 1482 | */ | ||
| 1483 | #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) | ||
| 1484 | #define CTIMER_CCR_CAP1RE_MASK (0x8U) | ||
| 1485 | #define CTIMER_CCR_CAP1RE_SHIFT (3U) | ||
| 1486 | /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with | ||
| 1487 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1488 | */ | ||
| 1489 | #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) | ||
| 1490 | #define CTIMER_CCR_CAP1FE_MASK (0x10U) | ||
| 1491 | #define CTIMER_CCR_CAP1FE_SHIFT (4U) | ||
| 1492 | /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with | ||
| 1493 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1494 | */ | ||
| 1495 | #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) | ||
| 1496 | #define CTIMER_CCR_CAP1I_MASK (0x20U) | ||
| 1497 | #define CTIMER_CCR_CAP1I_SHIFT (5U) | ||
| 1498 | /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. | ||
| 1499 | */ | ||
| 1500 | #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) | ||
| 1501 | #define CTIMER_CCR_CAP2RE_MASK (0x40U) | ||
| 1502 | #define CTIMER_CCR_CAP2RE_SHIFT (6U) | ||
| 1503 | /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with | ||
| 1504 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1505 | */ | ||
| 1506 | #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) | ||
| 1507 | #define CTIMER_CCR_CAP2FE_MASK (0x80U) | ||
| 1508 | #define CTIMER_CCR_CAP2FE_SHIFT (7U) | ||
| 1509 | /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with | ||
| 1510 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1511 | */ | ||
| 1512 | #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) | ||
| 1513 | #define CTIMER_CCR_CAP2I_MASK (0x100U) | ||
| 1514 | #define CTIMER_CCR_CAP2I_SHIFT (8U) | ||
| 1515 | /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. | ||
| 1516 | */ | ||
| 1517 | #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) | ||
| 1518 | #define CTIMER_CCR_CAP3RE_MASK (0x200U) | ||
| 1519 | #define CTIMER_CCR_CAP3RE_SHIFT (9U) | ||
| 1520 | /*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with | ||
| 1521 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1522 | */ | ||
| 1523 | #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) | ||
| 1524 | #define CTIMER_CCR_CAP3FE_MASK (0x400U) | ||
| 1525 | #define CTIMER_CCR_CAP3FE_SHIFT (10U) | ||
| 1526 | /*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with | ||
| 1527 | * the contents of TC. 0 = disabled. 1 = enabled. | ||
| 1528 | */ | ||
| 1529 | #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) | ||
| 1530 | #define CTIMER_CCR_CAP3I_MASK (0x800U) | ||
| 1531 | #define CTIMER_CCR_CAP3I_SHIFT (11U) | ||
| 1532 | /*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. | ||
| 1533 | */ | ||
| 1534 | #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) | ||
| 1535 | /*! @} */ | ||
| 1536 | |||
| 1537 | /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ | ||
| 1538 | /*! @{ */ | ||
| 1539 | #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) | ||
| 1540 | #define CTIMER_CR_CAP_SHIFT (0U) | ||
| 1541 | /*! CAP - Timer counter capture value. | ||
| 1542 | */ | ||
| 1543 | #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) | ||
| 1544 | /*! @} */ | ||
| 1545 | |||
| 1546 | /* The count of CTIMER_CR */ | ||
| 1547 | #define CTIMER_CR_COUNT (4U) | ||
| 1548 | |||
| 1549 | /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ | ||
| 1550 | /*! @{ */ | ||
| 1551 | #define CTIMER_EMR_EM0_MASK (0x1U) | ||
| 1552 | #define CTIMER_EMR_EM0_SHIFT (0U) | ||
| 1553 | /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output | ||
| 1554 | * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, | ||
| 1555 | * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if | ||
| 1556 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 1557 | */ | ||
| 1558 | #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) | ||
| 1559 | #define CTIMER_EMR_EM1_MASK (0x2U) | ||
| 1560 | #define CTIMER_EMR_EM1_SHIFT (1U) | ||
| 1561 | /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output | ||
| 1562 | * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, | ||
| 1563 | * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if | ||
| 1564 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 1565 | */ | ||
| 1566 | #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) | ||
| 1567 | #define CTIMER_EMR_EM2_MASK (0x4U) | ||
| 1568 | #define CTIMER_EMR_EM2_SHIFT (2U) | ||
| 1569 | /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output | ||
| 1570 | * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, | ||
| 1571 | * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if | ||
| 1572 | * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 1573 | */ | ||
| 1574 | #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) | ||
| 1575 | #define CTIMER_EMR_EM3_MASK (0x8U) | ||
| 1576 | #define CTIMER_EMR_EM3_SHIFT (3U) | ||
| 1577 | /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output | ||
| 1578 | * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, | ||
| 1579 | * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins | ||
| 1580 | * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. | ||
| 1581 | */ | ||
| 1582 | #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) | ||
| 1583 | #define CTIMER_EMR_EMC0_MASK (0x30U) | ||
| 1584 | #define CTIMER_EMR_EMC0_SHIFT (4U) | ||
| 1585 | /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. | ||
| 1586 | * 0b00..Do Nothing. | ||
| 1587 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). | ||
| 1588 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). | ||
| 1589 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 1590 | */ | ||
| 1591 | #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) | ||
| 1592 | #define CTIMER_EMR_EMC1_MASK (0xC0U) | ||
| 1593 | #define CTIMER_EMR_EMC1_SHIFT (6U) | ||
| 1594 | /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. | ||
| 1595 | * 0b00..Do Nothing. | ||
| 1596 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). | ||
| 1597 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). | ||
| 1598 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 1599 | */ | ||
| 1600 | #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) | ||
| 1601 | #define CTIMER_EMR_EMC2_MASK (0x300U) | ||
| 1602 | #define CTIMER_EMR_EMC2_SHIFT (8U) | ||
| 1603 | /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. | ||
| 1604 | * 0b00..Do Nothing. | ||
| 1605 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). | ||
| 1606 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). | ||
| 1607 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 1608 | */ | ||
| 1609 | #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) | ||
| 1610 | #define CTIMER_EMR_EMC3_MASK (0xC00U) | ||
| 1611 | #define CTIMER_EMR_EMC3_SHIFT (10U) | ||
| 1612 | /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. | ||
| 1613 | * 0b00..Do Nothing. | ||
| 1614 | * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). | ||
| 1615 | * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). | ||
| 1616 | * 0b11..Toggle. Toggle the corresponding External Match bit/output. | ||
| 1617 | */ | ||
| 1618 | #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) | ||
| 1619 | /*! @} */ | ||
| 1620 | |||
| 1621 | /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ | ||
| 1622 | /*! @{ */ | ||
| 1623 | #define CTIMER_CTCR_CTMODE_MASK (0x3U) | ||
| 1624 | #define CTIMER_CTCR_CTMODE_SHIFT (0U) | ||
| 1625 | /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment | ||
| 1626 | * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC | ||
| 1627 | * is incremented when the Prescale Counter matches the Prescale Register. | ||
| 1628 | * 0b00..Timer Mode. Incremented every rising APB bus clock edge. | ||
| 1629 | * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. | ||
| 1630 | * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. | ||
| 1631 | * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. | ||
| 1632 | */ | ||
| 1633 | #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) | ||
| 1634 | #define CTIMER_CTCR_CINSEL_MASK (0xCU) | ||
| 1635 | #define CTIMER_CTCR_CINSEL_SHIFT (2U) | ||
| 1636 | /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which | ||
| 1637 | * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input | ||
| 1638 | * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be | ||
| 1639 | * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the | ||
| 1640 | * same timer. | ||
| 1641 | * 0b00..Channel 0. CAPn.0 for CTIMERn | ||
| 1642 | * 0b01..Channel 1. CAPn.1 for CTIMERn | ||
| 1643 | * 0b10..Channel 2. CAPn.2 for CTIMERn | ||
| 1644 | * 0b11..Channel 3. CAPn.3 for CTIMERn | ||
| 1645 | */ | ||
| 1646 | #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) | ||
| 1647 | #define CTIMER_CTCR_ENCC_MASK (0x10U) | ||
| 1648 | #define CTIMER_CTCR_ENCC_SHIFT (4U) | ||
| 1649 | /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the | ||
| 1650 | * capture-edge event specified in bits 7:5 occurs. | ||
| 1651 | */ | ||
| 1652 | #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) | ||
| 1653 | #define CTIMER_CTCR_SELCC_MASK (0xE0U) | ||
| 1654 | #define CTIMER_CTCR_SELCC_SHIFT (5U) | ||
| 1655 | /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the | ||
| 1656 | * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to | ||
| 1657 | * 0x3 and 0x6 to 0x7 are reserved. | ||
| 1658 | * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 1659 | * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). | ||
| 1660 | * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 1661 | * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). | ||
| 1662 | * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 1663 | * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 1664 | * 0b110..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 1665 | * 0b111..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). | ||
| 1666 | */ | ||
| 1667 | #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) | ||
| 1668 | /*! @} */ | ||
| 1669 | |||
| 1670 | /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ | ||
| 1671 | /*! @{ */ | ||
| 1672 | #define CTIMER_PWMC_PWMEN0_MASK (0x1U) | ||
| 1673 | #define CTIMER_PWMC_PWMEN0_SHIFT (0U) | ||
| 1674 | /*! PWMEN0 - PWM mode enable for channel0. | ||
| 1675 | * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. | ||
| 1676 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. | ||
| 1677 | */ | ||
| 1678 | #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) | ||
| 1679 | #define CTIMER_PWMC_PWMEN1_MASK (0x2U) | ||
| 1680 | #define CTIMER_PWMC_PWMEN1_SHIFT (1U) | ||
| 1681 | /*! PWMEN1 - PWM mode enable for channel1. | ||
| 1682 | * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. | ||
| 1683 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. | ||
| 1684 | */ | ||
| 1685 | #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) | ||
| 1686 | #define CTIMER_PWMC_PWMEN2_MASK (0x4U) | ||
| 1687 | #define CTIMER_PWMC_PWMEN2_SHIFT (2U) | ||
| 1688 | /*! PWMEN2 - PWM mode enable for channel2. | ||
| 1689 | * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. | ||
| 1690 | * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. | ||
| 1691 | */ | ||
| 1692 | #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) | ||
| 1693 | #define CTIMER_PWMC_PWMEN3_MASK (0x8U) | ||
| 1694 | #define CTIMER_PWMC_PWMEN3_SHIFT (3U) | ||
| 1695 | /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. | ||
| 1696 | * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. | ||
| 1697 | * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. | ||
| 1698 | */ | ||
| 1699 | #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) | ||
| 1700 | /*! @} */ | ||
| 1701 | |||
| 1702 | /*! @name MSR - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. */ | ||
| 1703 | /*! @{ */ | ||
| 1704 | #define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) | ||
| 1705 | #define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) | ||
| 1706 | /*! MATCH_SHADOW - Timer counter match value. | ||
| 1707 | */ | ||
| 1708 | #define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) | ||
| 1709 | /*! @} */ | ||
| 1710 | |||
| 1711 | /* The count of CTIMER_MSR */ | ||
| 1712 | #define CTIMER_MSR_COUNT (4U) | ||
| 1713 | |||
| 1714 | |||
| 1715 | /*! | ||
| 1716 | * @} | ||
| 1717 | */ /* end of group CTIMER_Register_Masks */ | ||
| 1718 | |||
| 1719 | |||
| 1720 | /* CTIMER - Peripheral instance base addresses */ | ||
| 1721 | /** Peripheral CTIMER0 base address */ | ||
| 1722 | #define CTIMER0_BASE (0x40038000u) | ||
| 1723 | /** Peripheral CTIMER0 base pointer */ | ||
| 1724 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) | ||
| 1725 | /** Array initializer of CTIMER peripheral base addresses */ | ||
| 1726 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE } | ||
| 1727 | /** Array initializer of CTIMER peripheral base pointers */ | ||
| 1728 | #define CTIMER_BASE_PTRS { CTIMER0 } | ||
| 1729 | /** Interrupt vectors for the CTIMER peripheral type */ | ||
| 1730 | #define CTIMER_IRQS { CTIMER0_IRQn } | ||
| 1731 | |||
| 1732 | /*! | ||
| 1733 | * @} | ||
| 1734 | */ /* end of group CTIMER_Peripheral_Access_Layer */ | ||
| 1735 | |||
| 1736 | |||
| 1737 | /* ---------------------------------------------------------------------------- | ||
| 1738 | -- DMA Peripheral Access Layer | ||
| 1739 | ---------------------------------------------------------------------------- */ | ||
| 1740 | |||
| 1741 | /*! | ||
| 1742 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer | ||
| 1743 | * @{ | ||
| 1744 | */ | ||
| 1745 | |||
| 1746 | /** DMA - Register Layout Typedef */ | ||
| 1747 | typedef struct { | ||
| 1748 | __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ | ||
| 1749 | __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ | ||
| 1750 | __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ | ||
| 1751 | uint8_t RESERVED_0[20]; | ||
| 1752 | struct { /* offset: 0x20, array step: 0x5C */ | ||
| 1753 | __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ | ||
| 1754 | uint8_t RESERVED_0[4]; | ||
| 1755 | __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ | ||
| 1756 | uint8_t RESERVED_1[4]; | ||
| 1757 | __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ | ||
| 1758 | uint8_t RESERVED_2[4]; | ||
| 1759 | __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ | ||
| 1760 | uint8_t RESERVED_3[4]; | ||
| 1761 | __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ | ||
| 1762 | uint8_t RESERVED_4[4]; | ||
| 1763 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ | ||
| 1764 | uint8_t RESERVED_5[4]; | ||
| 1765 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ | ||
| 1766 | uint8_t RESERVED_6[4]; | ||
| 1767 | __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ | ||
| 1768 | uint8_t RESERVED_7[4]; | ||
| 1769 | __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ | ||
| 1770 | uint8_t RESERVED_8[4]; | ||
| 1771 | __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ | ||
| 1772 | uint8_t RESERVED_9[4]; | ||
| 1773 | __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ | ||
| 1774 | uint8_t RESERVED_10[4]; | ||
| 1775 | __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ | ||
| 1776 | } COMMON[1]; | ||
| 1777 | uint8_t RESERVED_1[900]; | ||
| 1778 | struct { /* offset: 0x400, array step: 0x10 */ | ||
| 1779 | __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ | ||
| 1780 | __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ | ||
| 1781 | __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ | ||
| 1782 | uint8_t RESERVED_0[4]; | ||
| 1783 | } CHANNEL[25]; | ||
| 1784 | } DMA_Type; | ||
| 1785 | |||
| 1786 | /* ---------------------------------------------------------------------------- | ||
| 1787 | -- DMA Register Masks | ||
| 1788 | ---------------------------------------------------------------------------- */ | ||
| 1789 | |||
| 1790 | /*! | ||
| 1791 | * @addtogroup DMA_Register_Masks DMA Register Masks | ||
| 1792 | * @{ | ||
| 1793 | */ | ||
| 1794 | |||
| 1795 | /*! @name CTRL - DMA control. */ | ||
| 1796 | /*! @{ */ | ||
| 1797 | #define DMA_CTRL_ENABLE_MASK (0x1U) | ||
| 1798 | #define DMA_CTRL_ENABLE_SHIFT (0U) | ||
| 1799 | /*! ENABLE - DMA controller master enable. | ||
| 1800 | * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when | ||
| 1801 | * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. | ||
| 1802 | * 0b1..Enabled. The DMA controller is enabled. | ||
| 1803 | */ | ||
| 1804 | #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) | ||
| 1805 | /*! @} */ | ||
| 1806 | |||
| 1807 | /*! @name INTSTAT - Interrupt status. */ | ||
| 1808 | /*! @{ */ | ||
| 1809 | #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) | ||
| 1810 | #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) | ||
| 1811 | /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. | ||
| 1812 | * 0b0..Not pending. No enabled interrupts are pending. | ||
| 1813 | * 0b1..Pending. At least one enabled interrupt is pending. | ||
| 1814 | */ | ||
| 1815 | #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) | ||
| 1816 | #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) | ||
| 1817 | #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) | ||
| 1818 | /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. | ||
| 1819 | * 0b0..Not pending. No error interrupts are pending. | ||
| 1820 | * 0b1..Pending. At least one error interrupt is pending. | ||
| 1821 | */ | ||
| 1822 | #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) | ||
| 1823 | /*! @} */ | ||
| 1824 | |||
| 1825 | /*! @name SRAMBASE - SRAM address of the channel configuration table. */ | ||
| 1826 | /*! @{ */ | ||
| 1827 | #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) | ||
| 1828 | #define DMA_SRAMBASE_OFFSET_SHIFT (9U) | ||
| 1829 | /*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the | ||
| 1830 | * table must begin on a 512 byte boundary. | ||
| 1831 | */ | ||
| 1832 | #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) | ||
| 1833 | /*! @} */ | ||
| 1834 | |||
| 1835 | /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ | ||
| 1836 | /*! @{ */ | ||
| 1837 | #define DMA_COMMON_ENABLESET_ENA_MASK (0x1FFFFFFU) | ||
| 1838 | #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) | ||
| 1839 | /*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = | ||
| 1840 | * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. | ||
| 1841 | */ | ||
| 1842 | #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) | ||
| 1843 | /*! @} */ | ||
| 1844 | |||
| 1845 | /* The count of DMA_COMMON_ENABLESET */ | ||
| 1846 | #define DMA_COMMON_ENABLESET_COUNT (1U) | ||
| 1847 | |||
| 1848 | /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ | ||
| 1849 | /*! @{ */ | ||
| 1850 | #define DMA_COMMON_ENABLECLR_CLR_MASK (0x1FFFFFFU) | ||
| 1851 | #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) | ||
| 1852 | /*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears | ||
| 1853 | * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits | ||
| 1854 | * are reserved. | ||
| 1855 | */ | ||
| 1856 | #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) | ||
| 1857 | /*! @} */ | ||
| 1858 | |||
| 1859 | /* The count of DMA_COMMON_ENABLECLR */ | ||
| 1860 | #define DMA_COMMON_ENABLECLR_COUNT (1U) | ||
| 1861 | |||
| 1862 | /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ | ||
| 1863 | /*! @{ */ | ||
| 1864 | #define DMA_COMMON_ACTIVE_ACT_MASK (0x1FFFFFFU) | ||
| 1865 | #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) | ||
| 1866 | /*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 1867 | * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. | ||
| 1868 | */ | ||
| 1869 | #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) | ||
| 1870 | /*! @} */ | ||
| 1871 | |||
| 1872 | /* The count of DMA_COMMON_ACTIVE */ | ||
| 1873 | #define DMA_COMMON_ACTIVE_COUNT (1U) | ||
| 1874 | |||
| 1875 | /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ | ||
| 1876 | /*! @{ */ | ||
| 1877 | #define DMA_COMMON_BUSY_BSY_MASK (0x1FFFFFFU) | ||
| 1878 | #define DMA_COMMON_BUSY_BSY_SHIFT (0U) | ||
| 1879 | /*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = | ||
| 1880 | * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. | ||
| 1881 | */ | ||
| 1882 | #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) | ||
| 1883 | /*! @} */ | ||
| 1884 | |||
| 1885 | /* The count of DMA_COMMON_BUSY */ | ||
| 1886 | #define DMA_COMMON_BUSY_COUNT (1U) | ||
| 1887 | |||
| 1888 | /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ | ||
| 1889 | /*! @{ */ | ||
| 1890 | #define DMA_COMMON_ERRINT_ERR_MASK (0x1FFFFFFU) | ||
| 1891 | #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) | ||
| 1892 | /*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 1893 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is | ||
| 1894 | * not active. 1 = error interrupt is active. | ||
| 1895 | */ | ||
| 1896 | #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) | ||
| 1897 | /*! @} */ | ||
| 1898 | |||
| 1899 | /* The count of DMA_COMMON_ERRINT */ | ||
| 1900 | #define DMA_COMMON_ERRINT_COUNT (1U) | ||
| 1901 | |||
| 1902 | /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ | ||
| 1903 | /*! @{ */ | ||
| 1904 | #define DMA_COMMON_INTENSET_INTEN_MASK (0x1FFFFFFU) | ||
| 1905 | #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) | ||
| 1906 | /*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The | ||
| 1907 | * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = | ||
| 1908 | * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. | ||
| 1909 | */ | ||
| 1910 | #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) | ||
| 1911 | /*! @} */ | ||
| 1912 | |||
| 1913 | /* The count of DMA_COMMON_INTENSET */ | ||
| 1914 | #define DMA_COMMON_INTENSET_COUNT (1U) | ||
| 1915 | |||
| 1916 | /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ | ||
| 1917 | /*! @{ */ | ||
| 1918 | #define DMA_COMMON_INTENCLR_CLR_MASK (0x1FFFFFFU) | ||
| 1919 | #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) | ||
| 1920 | /*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n | ||
| 1921 | * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are | ||
| 1922 | * reserved. | ||
| 1923 | */ | ||
| 1924 | #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) | ||
| 1925 | /*! @} */ | ||
| 1926 | |||
| 1927 | /* The count of DMA_COMMON_INTENCLR */ | ||
| 1928 | #define DMA_COMMON_INTENCLR_COUNT (1U) | ||
| 1929 | |||
| 1930 | /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ | ||
| 1931 | /*! @{ */ | ||
| 1932 | #define DMA_COMMON_INTA_IA_MASK (0x1FFFFFFU) | ||
| 1933 | #define DMA_COMMON_INTA_IA_SHIFT (0U) | ||
| 1934 | /*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 1935 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 1936 | * interrupt A is not active. 1 = the DMA channel interrupt A is active. | ||
| 1937 | */ | ||
| 1938 | #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) | ||
| 1939 | /*! @} */ | ||
| 1940 | |||
| 1941 | /* The count of DMA_COMMON_INTA */ | ||
| 1942 | #define DMA_COMMON_INTA_COUNT (1U) | ||
| 1943 | |||
| 1944 | /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ | ||
| 1945 | /*! @{ */ | ||
| 1946 | #define DMA_COMMON_INTB_IB_MASK (0x1FFFFFFU) | ||
| 1947 | #define DMA_COMMON_INTB_IB_SHIFT (0U) | ||
| 1948 | /*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of | ||
| 1949 | * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel | ||
| 1950 | * interrupt B is not active. 1 = the DMA channel interrupt B is active. | ||
| 1951 | */ | ||
| 1952 | #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) | ||
| 1953 | /*! @} */ | ||
| 1954 | |||
| 1955 | /* The count of DMA_COMMON_INTB */ | ||
| 1956 | #define DMA_COMMON_INTB_COUNT (1U) | ||
| 1957 | |||
| 1958 | /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ | ||
| 1959 | /*! @{ */ | ||
| 1960 | #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) | ||
| 1961 | #define DMA_COMMON_SETVALID_SV_SHIFT (0U) | ||
| 1962 | /*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits | ||
| 1963 | * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the | ||
| 1964 | * VALIDPENDING control bit for DMA channel n | ||
| 1965 | */ | ||
| 1966 | #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) | ||
| 1967 | /*! @} */ | ||
| 1968 | |||
| 1969 | /* The count of DMA_COMMON_SETVALID */ | ||
| 1970 | #define DMA_COMMON_SETVALID_COUNT (1U) | ||
| 1971 | |||
| 1972 | /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ | ||
| 1973 | /*! @{ */ | ||
| 1974 | #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) | ||
| 1975 | #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) | ||
| 1976 | /*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number | ||
| 1977 | * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = | ||
| 1978 | * sets the TRIG bit for DMA channel n. | ||
| 1979 | */ | ||
| 1980 | #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) | ||
| 1981 | /*! @} */ | ||
| 1982 | |||
| 1983 | /* The count of DMA_COMMON_SETTRIG */ | ||
| 1984 | #define DMA_COMMON_SETTRIG_COUNT (1U) | ||
| 1985 | |||
| 1986 | /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ | ||
| 1987 | /*! @{ */ | ||
| 1988 | #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) | ||
| 1989 | #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) | ||
| 1990 | /*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. | ||
| 1991 | * 1 = aborts DMA operations on channel n. | ||
| 1992 | */ | ||
| 1993 | #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) | ||
| 1994 | /*! @} */ | ||
| 1995 | |||
| 1996 | /* The count of DMA_COMMON_ABORT */ | ||
| 1997 | #define DMA_COMMON_ABORT_COUNT (1U) | ||
| 1998 | |||
| 1999 | /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ | ||
| 2000 | /*! @{ */ | ||
| 2001 | #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) | ||
| 2002 | #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) | ||
| 2003 | /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory | ||
| 2004 | * move, any peripheral DMA request associated with that channel can be disabled to prevent any | ||
| 2005 | * interaction between the peripheral and the DMA controller. | ||
| 2006 | * 0b0..Disabled. Peripheral DMA requests are disabled. | ||
| 2007 | * 0b1..Enabled. Peripheral DMA requests are enabled. | ||
| 2008 | */ | ||
| 2009 | #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) | ||
| 2010 | #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) | ||
| 2011 | #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) | ||
| 2012 | /*! HWTRIGEN - Hardware Triggering Enable for this channel. | ||
| 2013 | * 0b0..Disabled. Hardware triggering is not used. | ||
| 2014 | * 0b1..Enabled. Use hardware triggering. | ||
| 2015 | */ | ||
| 2016 | #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) | ||
| 2017 | #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) | ||
| 2018 | #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) | ||
| 2019 | /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. | ||
| 2020 | * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. | ||
| 2021 | * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. | ||
| 2022 | */ | ||
| 2023 | #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) | ||
| 2024 | #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) | ||
| 2025 | #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) | ||
| 2026 | /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. | ||
| 2027 | * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. | ||
| 2028 | * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = | ||
| 2029 | * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the | ||
| 2030 | * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger | ||
| 2031 | * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the | ||
| 2032 | * current BURSTPOWER length are completed. | ||
| 2033 | */ | ||
| 2034 | #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) | ||
| 2035 | #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) | ||
| 2036 | #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) | ||
| 2037 | /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. | ||
| 2038 | * 0b0..Single transfer. Hardware trigger causes a single transfer. | ||
| 2039 | * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a | ||
| 2040 | * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a | ||
| 2041 | * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is | ||
| 2042 | * complete. | ||
| 2043 | */ | ||
| 2044 | #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) | ||
| 2045 | #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) | ||
| 2046 | #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) | ||
| 2047 | /*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when | ||
| 2048 | * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). | ||
| 2049 | * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many | ||
| 2050 | * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that | ||
| 2051 | * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: | ||
| 2052 | * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = | ||
| 2053 | * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The | ||
| 2054 | * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even | ||
| 2055 | * multiple of the burst size. | ||
| 2056 | */ | ||
| 2057 | #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) | ||
| 2058 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) | ||
| 2059 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) | ||
| 2060 | /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is | ||
| 2061 | * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this | ||
| 2062 | * could be used to read several sequential registers from a peripheral for each DMA burst, | ||
| 2063 | * reading the same registers again for each burst. | ||
| 2064 | * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. | ||
| 2065 | * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. | ||
| 2066 | */ | ||
| 2067 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) | ||
| 2068 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) | ||
| 2069 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) | ||
| 2070 | /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is | ||
| 2071 | * 'wrapped', meaning that the destination address range for each burst will be the same. As an | ||
| 2072 | * example, this could be used to write several sequential registers to a peripheral for each DMA | ||
| 2073 | * burst, writing the same registers again for each burst. | ||
| 2074 | * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. | ||
| 2075 | * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. | ||
| 2076 | */ | ||
| 2077 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) | ||
| 2078 | #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) | ||
| 2079 | #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) | ||
| 2080 | /*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority | ||
| 2081 | * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. | ||
| 2082 | */ | ||
| 2083 | #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) | ||
| 2084 | /*! @} */ | ||
| 2085 | |||
| 2086 | /* The count of DMA_CHANNEL_CFG */ | ||
| 2087 | #define DMA_CHANNEL_CFG_COUNT (25U) | ||
| 2088 | |||
| 2089 | /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ | ||
| 2090 | /*! @{ */ | ||
| 2091 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) | ||
| 2092 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) | ||
| 2093 | /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the | ||
| 2094 | * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. | ||
| 2095 | * 0b0..No effect. No effect on DMA operation. | ||
| 2096 | * 0b1..Valid pending. | ||
| 2097 | */ | ||
| 2098 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) | ||
| 2099 | #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) | ||
| 2100 | #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) | ||
| 2101 | /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is | ||
| 2102 | * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. | ||
| 2103 | * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. | ||
| 2104 | * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. | ||
| 2105 | */ | ||
| 2106 | #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) | ||
| 2107 | /*! @} */ | ||
| 2108 | |||
| 2109 | /* The count of DMA_CHANNEL_CTLSTAT */ | ||
| 2110 | #define DMA_CHANNEL_CTLSTAT_COUNT (25U) | ||
| 2111 | |||
| 2112 | /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ | ||
| 2113 | /*! @{ */ | ||
| 2114 | #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) | ||
| 2115 | #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) | ||
| 2116 | /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor | ||
| 2117 | * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. | ||
| 2118 | * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. | ||
| 2119 | * 0b1..Valid. The current channel descriptor is considered valid. | ||
| 2120 | */ | ||
| 2121 | #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) | ||
| 2122 | #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) | ||
| 2123 | #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) | ||
| 2124 | /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current | ||
| 2125 | * descriptor is exhausted. Reloading allows ping-pong and linked transfers. | ||
| 2126 | * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. | ||
| 2127 | * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. | ||
| 2128 | */ | ||
| 2129 | #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) | ||
| 2130 | #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) | ||
| 2131 | #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) | ||
| 2132 | /*! SWTRIG - Software Trigger. | ||
| 2133 | * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by | ||
| 2134 | * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. | ||
| 2135 | * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not | ||
| 2136 | * be used with level triggering when TRIGBURST = 0. | ||
| 2137 | */ | ||
| 2138 | #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) | ||
| 2139 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) | ||
| 2140 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) | ||
| 2141 | /*! CLRTRIG - Clear Trigger. | ||
| 2142 | * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. | ||
| 2143 | * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted | ||
| 2144 | */ | ||
| 2145 | #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) | ||
| 2146 | #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) | ||
| 2147 | #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) | ||
| 2148 | /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between | ||
| 2149 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 2150 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 2151 | * 0b0..No effect. | ||
| 2152 | * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. | ||
| 2153 | */ | ||
| 2154 | #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) | ||
| 2155 | #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) | ||
| 2156 | #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) | ||
| 2157 | /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between | ||
| 2158 | * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By | ||
| 2159 | * convention, interrupt A may be used when only one interrupt flag is needed. | ||
| 2160 | * 0b0..No effect. | ||
| 2161 | * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. | ||
| 2162 | */ | ||
| 2163 | #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) | ||
| 2164 | #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) | ||
| 2165 | #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) | ||
| 2166 | /*! WIDTH - Transfer width used for this DMA channel. | ||
| 2167 | * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). | ||
| 2168 | * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). | ||
| 2169 | * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). | ||
| 2170 | * 0b11..Reserved. Reserved setting, do not use. | ||
| 2171 | */ | ||
| 2172 | #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) | ||
| 2173 | #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) | ||
| 2174 | #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) | ||
| 2175 | /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. | ||
| 2176 | * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. | ||
| 2177 | * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is | ||
| 2178 | * the usual case when the source is memory. | ||
| 2179 | * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 2180 | * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 2181 | */ | ||
| 2182 | #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) | ||
| 2183 | #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) | ||
| 2184 | #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) | ||
| 2185 | /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. | ||
| 2186 | * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when | ||
| 2187 | * the destination is a peripheral device. | ||
| 2188 | * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. | ||
| 2189 | * This is the usual case when the destination is memory. | ||
| 2190 | * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. | ||
| 2191 | * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. | ||
| 2192 | */ | ||
| 2193 | #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) | ||
| 2194 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) | ||
| 2195 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) | ||
| 2196 | /*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes | ||
| 2197 | * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller | ||
| 2198 | * uses this bit field during transfer to count down. Hence, it cannot be used by software to read | ||
| 2199 | * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 | ||
| 2200 | * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of | ||
| 2201 | * 1,024 transfers will be performed. | ||
| 2202 | */ | ||
| 2203 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) | ||
| 2204 | /*! @} */ | ||
| 2205 | |||
| 2206 | /* The count of DMA_CHANNEL_XFERCFG */ | ||
| 2207 | #define DMA_CHANNEL_XFERCFG_COUNT (25U) | ||
| 2208 | |||
| 2209 | |||
| 2210 | /*! | ||
| 2211 | * @} | ||
| 2212 | */ /* end of group DMA_Register_Masks */ | ||
| 2213 | |||
| 2214 | |||
| 2215 | /* DMA - Peripheral instance base addresses */ | ||
| 2216 | /** Peripheral DMA0 base address */ | ||
| 2217 | #define DMA0_BASE (0x50008000u) | ||
| 2218 | /** Peripheral DMA0 base pointer */ | ||
| 2219 | #define DMA0 ((DMA_Type *)DMA0_BASE) | ||
| 2220 | /** Array initializer of DMA peripheral base addresses */ | ||
| 2221 | #define DMA_BASE_ADDRS { DMA0_BASE } | ||
| 2222 | /** Array initializer of DMA peripheral base pointers */ | ||
| 2223 | #define DMA_BASE_PTRS { DMA0 } | ||
| 2224 | /** Interrupt vectors for the DMA peripheral type */ | ||
| 2225 | #define DMA_IRQS { DMA0_IRQn } | ||
| 2226 | |||
| 2227 | /*! | ||
| 2228 | * @} | ||
| 2229 | */ /* end of group DMA_Peripheral_Access_Layer */ | ||
| 2230 | |||
| 2231 | |||
| 2232 | /* ---------------------------------------------------------------------------- | ||
| 2233 | -- FLASH_CTRL Peripheral Access Layer | ||
| 2234 | ---------------------------------------------------------------------------- */ | ||
| 2235 | |||
| 2236 | /*! | ||
| 2237 | * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer | ||
| 2238 | * @{ | ||
| 2239 | */ | ||
| 2240 | |||
| 2241 | /** FLASH_CTRL - Register Layout Typedef */ | ||
| 2242 | typedef struct { | ||
| 2243 | uint8_t RESERVED_0[16]; | ||
| 2244 | __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */ | ||
| 2245 | uint8_t RESERVED_1[12]; | ||
| 2246 | __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */ | ||
| 2247 | __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */ | ||
| 2248 | uint8_t RESERVED_2[4]; | ||
| 2249 | __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */ | ||
| 2250 | uint8_t RESERVED_3[4016]; | ||
| 2251 | __I uint32_t FMSTAT; /**< Flash signature generation status bit, offset: 0xFE0 */ | ||
| 2252 | uint8_t RESERVED_4[4]; | ||
| 2253 | __O uint32_t FMSTATCLR; /**< Clear FLASH signature generation status bit, offset: 0xFE8 */ | ||
| 2254 | } FLASH_CTRL_Type; | ||
| 2255 | |||
| 2256 | /* ---------------------------------------------------------------------------- | ||
| 2257 | -- FLASH_CTRL Register Masks | ||
| 2258 | ---------------------------------------------------------------------------- */ | ||
| 2259 | |||
| 2260 | /*! | ||
| 2261 | * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks | ||
| 2262 | * @{ | ||
| 2263 | */ | ||
| 2264 | |||
| 2265 | /*! @name FLASHCFG - Flash configuration register */ | ||
| 2266 | /*! @{ */ | ||
| 2267 | #define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U) | ||
| 2268 | #define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U) | ||
| 2269 | /*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. | ||
| 2270 | * 0b00..1 system clock flash access time. | ||
| 2271 | * 0b01..2 system clock flash access time. | ||
| 2272 | * 0b10..3 system clock flash access time. | ||
| 2273 | * 0b11..Reserved. | ||
| 2274 | */ | ||
| 2275 | #define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK) | ||
| 2276 | /*! @} */ | ||
| 2277 | |||
| 2278 | /*! @name FMSSTART - Flash signature start address register */ | ||
| 2279 | /*! @{ */ | ||
| 2280 | #define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU) | ||
| 2281 | #define FLASH_CTRL_FMSSTART_START_SHIFT (0U) | ||
| 2282 | /*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]). | ||
| 2283 | */ | ||
| 2284 | #define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK) | ||
| 2285 | /*! @} */ | ||
| 2286 | |||
| 2287 | /*! @name FMSSTOP - Flash signaure stop address register */ | ||
| 2288 | /*! @{ */ | ||
| 2289 | #define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU) | ||
| 2290 | #define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U) | ||
| 2291 | /*! STOPA - Stop address for signature generation (the word specified by STOP is included in the | ||
| 2292 | * address range). The address is in units of memory words, not bytes. | ||
| 2293 | */ | ||
| 2294 | #define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK) | ||
| 2295 | #define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U) | ||
| 2296 | #define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U) | ||
| 2297 | /*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature | ||
| 2298 | * generation, this bit is automatically cleared. | ||
| 2299 | */ | ||
| 2300 | #define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK) | ||
| 2301 | /*! @} */ | ||
| 2302 | |||
| 2303 | /*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */ | ||
| 2304 | /*! @{ */ | ||
| 2305 | #define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU) | ||
| 2306 | #define FLASH_CTRL_FMSW0_SIG_SHIFT (0U) | ||
| 2307 | /*! SIG - 32-bit signature. | ||
| 2308 | */ | ||
| 2309 | #define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK) | ||
| 2310 | /*! @} */ | ||
| 2311 | |||
| 2312 | /*! @name FMSTAT - Flash signature generation status bit */ | ||
| 2313 | /*! @{ */ | ||
| 2314 | #define FLASH_CTRL_FMSTAT_SIG_DONE_MASK (0x2U) | ||
| 2315 | #define FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT (1U) | ||
| 2316 | /*! SIG_DONE - This status bit is set at the end of signature computation | ||
| 2317 | */ | ||
| 2318 | #define FLASH_CTRL_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTAT_SIG_DONE_SHIFT)) & FLASH_CTRL_FMSTAT_SIG_DONE_MASK) | ||
| 2319 | /*! @} */ | ||
| 2320 | |||
| 2321 | /*! @name FMSTATCLR - Clear FLASH signature generation status bit */ | ||
| 2322 | /*! @{ */ | ||
| 2323 | #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK (0x2U) | ||
| 2324 | #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT (1U) | ||
| 2325 | /*! SIG_DONE_CLR - When the bit is written to 1, the SIGNATURE_DONE bit is cleared. | ||
| 2326 | */ | ||
| 2327 | #define FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FLASH_CTRL_FMSTATCLR_SIG_DONE_CLR_MASK) | ||
| 2328 | /*! @} */ | ||
| 2329 | |||
| 2330 | |||
| 2331 | /*! | ||
| 2332 | * @} | ||
| 2333 | */ /* end of group FLASH_CTRL_Register_Masks */ | ||
| 2334 | |||
| 2335 | |||
| 2336 | /* FLASH_CTRL - Peripheral instance base addresses */ | ||
| 2337 | /** Peripheral FLASH_CTRL base address */ | ||
| 2338 | #define FLASH_CTRL_BASE (0x40040000u) | ||
| 2339 | /** Peripheral FLASH_CTRL base pointer */ | ||
| 2340 | #define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE) | ||
| 2341 | /** Array initializer of FLASH_CTRL peripheral base addresses */ | ||
| 2342 | #define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE } | ||
| 2343 | /** Array initializer of FLASH_CTRL peripheral base pointers */ | ||
| 2344 | #define FLASH_CTRL_BASE_PTRS { FLASH_CTRL } | ||
| 2345 | /** Interrupt vectors for the FLASH_CTRL peripheral type */ | ||
| 2346 | #define FLASH_CTRL_IRQS { FLASH_IRQn } | ||
| 2347 | |||
| 2348 | /*! | ||
| 2349 | * @} | ||
| 2350 | */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */ | ||
| 2351 | |||
| 2352 | |||
| 2353 | /* ---------------------------------------------------------------------------- | ||
| 2354 | -- GPIO Peripheral Access Layer | ||
| 2355 | ---------------------------------------------------------------------------- */ | ||
| 2356 | |||
| 2357 | /*! | ||
| 2358 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer | ||
| 2359 | * @{ | ||
| 2360 | */ | ||
| 2361 | |||
| 2362 | /** GPIO - Register Layout Typedef */ | ||
| 2363 | typedef struct { | ||
| 2364 | __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ | ||
| 2365 | uint8_t RESERVED_0[4032]; | ||
| 2366 | __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ | ||
| 2367 | uint8_t RESERVED_1[3840]; | ||
| 2368 | __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ | ||
| 2369 | uint8_t RESERVED_2[120]; | ||
| 2370 | __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ | ||
| 2371 | uint8_t RESERVED_3[120]; | ||
| 2372 | __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ | ||
| 2373 | uint8_t RESERVED_4[120]; | ||
| 2374 | __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ | ||
| 2375 | uint8_t RESERVED_5[120]; | ||
| 2376 | __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ | ||
| 2377 | uint8_t RESERVED_6[120]; | ||
| 2378 | __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ | ||
| 2379 | uint8_t RESERVED_7[120]; | ||
| 2380 | __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ | ||
| 2381 | uint8_t RESERVED_8[120]; | ||
| 2382 | __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ | ||
| 2383 | uint8_t RESERVED_9[120]; | ||
| 2384 | __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ | ||
| 2385 | uint8_t RESERVED_10[120]; | ||
| 2386 | __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ | ||
| 2387 | } GPIO_Type; | ||
| 2388 | |||
| 2389 | /* ---------------------------------------------------------------------------- | ||
| 2390 | -- GPIO Register Masks | ||
| 2391 | ---------------------------------------------------------------------------- */ | ||
| 2392 | |||
| 2393 | /*! | ||
| 2394 | * @addtogroup GPIO_Register_Masks GPIO Register Masks | ||
| 2395 | * @{ | ||
| 2396 | */ | ||
| 2397 | |||
| 2398 | /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ | ||
| 2399 | /*! @{ */ | ||
| 2400 | #define GPIO_B_PBYTE_MASK (0x1U) | ||
| 2401 | #define GPIO_B_PBYTE_SHIFT (0U) | ||
| 2402 | /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, | ||
| 2403 | * except that pins configured as analog I/O always read as 0. One register for each port pin. | ||
| 2404 | * Supported pins depends on the specific device and package. Write: loads the pin's output bit. | ||
| 2405 | * One register for each port pin. Supported pins depends on the specific device and package. | ||
| 2406 | */ | ||
| 2407 | #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) | ||
| 2408 | /*! @} */ | ||
| 2409 | |||
| 2410 | /* The count of GPIO_B */ | ||
| 2411 | #define GPIO_B_COUNT (2U) | ||
| 2412 | |||
| 2413 | /* The count of GPIO_B */ | ||
| 2414 | #define GPIO_B_COUNT2 (32U) | ||
| 2415 | |||
| 2416 | /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ | ||
| 2417 | /*! @{ */ | ||
| 2418 | #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) | ||
| 2419 | #define GPIO_W_PWORD_SHIFT (0U) | ||
| 2420 | /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is | ||
| 2421 | * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be | ||
| 2422 | * read. Writing any value other than 0 will set the output bit. One register for each port pin. | ||
| 2423 | * Supported pins depends on the specific device and package. | ||
| 2424 | */ | ||
| 2425 | #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) | ||
| 2426 | /*! @} */ | ||
| 2427 | |||
| 2428 | /* The count of GPIO_W */ | ||
| 2429 | #define GPIO_W_COUNT (2U) | ||
| 2430 | |||
| 2431 | /* The count of GPIO_W */ | ||
| 2432 | #define GPIO_W_COUNT2 (32U) | ||
| 2433 | |||
| 2434 | /*! @name DIR - Direction registers */ | ||
| 2435 | /*! @{ */ | ||
| 2436 | #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) | ||
| 2437 | #define GPIO_DIR_DIRP_SHIFT (0U) | ||
| 2438 | /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported | ||
| 2439 | * pins depends on the specific device and package. 0 = input. 1 = output. | ||
| 2440 | */ | ||
| 2441 | #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) | ||
| 2442 | /*! @} */ | ||
| 2443 | |||
| 2444 | /* The count of GPIO_DIR */ | ||
| 2445 | #define GPIO_DIR_COUNT (2U) | ||
| 2446 | |||
| 2447 | /*! @name MASK - Mask register */ | ||
| 2448 | /*! @{ */ | ||
| 2449 | #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) | ||
| 2450 | #define GPIO_MASK_MASKP_SHIFT (0U) | ||
| 2451 | /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = | ||
| 2452 | * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = | ||
| 2453 | * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit | ||
| 2454 | * not affected. | ||
| 2455 | */ | ||
| 2456 | #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) | ||
| 2457 | /*! @} */ | ||
| 2458 | |||
| 2459 | /* The count of GPIO_MASK */ | ||
| 2460 | #define GPIO_MASK_COUNT (2U) | ||
| 2461 | |||
| 2462 | /*! @name PIN - Port pin register */ | ||
| 2463 | /*! @{ */ | ||
| 2464 | #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) | ||
| 2465 | #define GPIO_PIN_PORT_SHIFT (0U) | ||
| 2466 | /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported | ||
| 2467 | * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. | ||
| 2468 | * 1 = Read: pin is high; write: set output bit. | ||
| 2469 | */ | ||
| 2470 | #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) | ||
| 2471 | /*! @} */ | ||
| 2472 | |||
| 2473 | /* The count of GPIO_PIN */ | ||
| 2474 | #define GPIO_PIN_COUNT (2U) | ||
| 2475 | |||
| 2476 | /*! @name MPIN - Masked port register */ | ||
| 2477 | /*! @{ */ | ||
| 2478 | #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) | ||
| 2479 | #define GPIO_MPIN_MPORTP_SHIFT (0U) | ||
| 2480 | /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 2481 | * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK | ||
| 2482 | * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 | ||
| 2483 | * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit | ||
| 2484 | * if the corresponding bit in the MASK register is 0. | ||
| 2485 | */ | ||
| 2486 | #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) | ||
| 2487 | /*! @} */ | ||
| 2488 | |||
| 2489 | /* The count of GPIO_MPIN */ | ||
| 2490 | #define GPIO_MPIN_COUNT (2U) | ||
| 2491 | |||
| 2492 | /*! @name SET - Write: Set register for port Read: output bits for port */ | ||
| 2493 | /*! @{ */ | ||
| 2494 | #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) | ||
| 2495 | #define GPIO_SET_SETP_SHIFT (0U) | ||
| 2496 | /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 2497 | * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output | ||
| 2498 | * bit; write: set output bit. | ||
| 2499 | */ | ||
| 2500 | #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) | ||
| 2501 | /*! @} */ | ||
| 2502 | |||
| 2503 | /* The count of GPIO_SET */ | ||
| 2504 | #define GPIO_SET_COUNT (2U) | ||
| 2505 | |||
| 2506 | /*! @name CLR - Clear port */ | ||
| 2507 | /*! @{ */ | ||
| 2508 | #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) | ||
| 2509 | #define GPIO_CLR_CLRP_SHIFT (0U) | ||
| 2510 | /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the | ||
| 2511 | * specific device and package. 0 = No operation. 1 = Clear output bit. | ||
| 2512 | */ | ||
| 2513 | #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) | ||
| 2514 | /*! @} */ | ||
| 2515 | |||
| 2516 | /* The count of GPIO_CLR */ | ||
| 2517 | #define GPIO_CLR_COUNT (2U) | ||
| 2518 | |||
| 2519 | /*! @name NOT - Toggle port */ | ||
| 2520 | /*! @{ */ | ||
| 2521 | #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) | ||
| 2522 | #define GPIO_NOT_NOTP_SHIFT (0U) | ||
| 2523 | /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the | ||
| 2524 | * specific device and package. 0 = no operation. 1 = Toggle output bit. | ||
| 2525 | */ | ||
| 2526 | #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) | ||
| 2527 | /*! @} */ | ||
| 2528 | |||
| 2529 | /* The count of GPIO_NOT */ | ||
| 2530 | #define GPIO_NOT_COUNT (2U) | ||
| 2531 | |||
| 2532 | /*! @name DIRSET - Set pin direction bits for port */ | ||
| 2533 | /*! @{ */ | ||
| 2534 | #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) | ||
| 2535 | #define GPIO_DIRSET_DIRSETP_SHIFT (0U) | ||
| 2536 | /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 2537 | * the specific device and package. 0 = No operation. 1 = Set direction bit. | ||
| 2538 | */ | ||
| 2539 | #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) | ||
| 2540 | /*! @} */ | ||
| 2541 | |||
| 2542 | /* The count of GPIO_DIRSET */ | ||
| 2543 | #define GPIO_DIRSET_COUNT (2U) | ||
| 2544 | |||
| 2545 | /*! @name DIRCLR - Clear pin direction bits for port */ | ||
| 2546 | /*! @{ */ | ||
| 2547 | #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) | ||
| 2548 | #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) | ||
| 2549 | /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on | ||
| 2550 | * the specific device and package. 0 = No operation. 1 = Clear direction bit. | ||
| 2551 | */ | ||
| 2552 | #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) | ||
| 2553 | /*! @} */ | ||
| 2554 | |||
| 2555 | /* The count of GPIO_DIRCLR */ | ||
| 2556 | #define GPIO_DIRCLR_COUNT (2U) | ||
| 2557 | |||
| 2558 | /*! @name DIRNOT - Toggle pin direction bits for port */ | ||
| 2559 | /*! @{ */ | ||
| 2560 | #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) | ||
| 2561 | #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) | ||
| 2562 | /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends | ||
| 2563 | * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. | ||
| 2564 | */ | ||
| 2565 | #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) | ||
| 2566 | /*! @} */ | ||
| 2567 | |||
| 2568 | /* The count of GPIO_DIRNOT */ | ||
| 2569 | #define GPIO_DIRNOT_COUNT (2U) | ||
| 2570 | |||
| 2571 | |||
| 2572 | /*! | ||
| 2573 | * @} | ||
| 2574 | */ /* end of group GPIO_Register_Masks */ | ||
| 2575 | |||
| 2576 | |||
| 2577 | /* GPIO - Peripheral instance base addresses */ | ||
| 2578 | /** Peripheral GPIO base address */ | ||
| 2579 | #define GPIO_BASE (0xA0000000u) | ||
| 2580 | /** Peripheral GPIO base pointer */ | ||
| 2581 | #define GPIO ((GPIO_Type *)GPIO_BASE) | ||
| 2582 | /** Array initializer of GPIO peripheral base addresses */ | ||
| 2583 | #define GPIO_BASE_ADDRS { GPIO_BASE } | ||
| 2584 | /** Array initializer of GPIO peripheral base pointers */ | ||
| 2585 | #define GPIO_BASE_PTRS { GPIO } | ||
| 2586 | |||
| 2587 | /*! | ||
| 2588 | * @} | ||
| 2589 | */ /* end of group GPIO_Peripheral_Access_Layer */ | ||
| 2590 | |||
| 2591 | |||
| 2592 | /* ---------------------------------------------------------------------------- | ||
| 2593 | -- I2C Peripheral Access Layer | ||
| 2594 | ---------------------------------------------------------------------------- */ | ||
| 2595 | |||
| 2596 | /*! | ||
| 2597 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer | ||
| 2598 | * @{ | ||
| 2599 | */ | ||
| 2600 | |||
| 2601 | /** I2C - Register Layout Typedef */ | ||
| 2602 | typedef struct { | ||
| 2603 | __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */ | ||
| 2604 | __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */ | ||
| 2605 | __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */ | ||
| 2606 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */ | ||
| 2607 | __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */ | ||
| 2608 | __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */ | ||
| 2609 | __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */ | ||
| 2610 | uint8_t RESERVED_0[4]; | ||
| 2611 | __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */ | ||
| 2612 | __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */ | ||
| 2613 | __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */ | ||
| 2614 | uint8_t RESERVED_1[20]; | ||
| 2615 | __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */ | ||
| 2616 | __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */ | ||
| 2617 | __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */ | ||
| 2618 | __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */ | ||
| 2619 | uint8_t RESERVED_2[36]; | ||
| 2620 | __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */ | ||
| 2621 | } I2C_Type; | ||
| 2622 | |||
| 2623 | /* ---------------------------------------------------------------------------- | ||
| 2624 | -- I2C Register Masks | ||
| 2625 | ---------------------------------------------------------------------------- */ | ||
| 2626 | |||
| 2627 | /*! | ||
| 2628 | * @addtogroup I2C_Register_Masks I2C Register Masks | ||
| 2629 | * @{ | ||
| 2630 | */ | ||
| 2631 | |||
| 2632 | /*! @name CFG - Configuration for shared functions. */ | ||
| 2633 | /*! @{ */ | ||
| 2634 | #define I2C_CFG_MSTEN_MASK (0x1U) | ||
| 2635 | #define I2C_CFG_MSTEN_SHIFT (0U) | ||
| 2636 | /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not | ||
| 2637 | * changed, but the Master function is internally reset. | ||
| 2638 | * 0b0..Disabled. The I2C Master function is disabled. | ||
| 2639 | * 0b1..Enabled. The I2C Master function is enabled. | ||
| 2640 | */ | ||
| 2641 | #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) | ||
| 2642 | #define I2C_CFG_SLVEN_MASK (0x2U) | ||
| 2643 | #define I2C_CFG_SLVEN_SHIFT (1U) | ||
| 2644 | /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not | ||
| 2645 | * changed, but the Slave function is internally reset. | ||
| 2646 | * 0b0..Disabled. The I2C slave function is disabled. | ||
| 2647 | * 0b1..Enabled. The I2C slave function is enabled. | ||
| 2648 | */ | ||
| 2649 | #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) | ||
| 2650 | #define I2C_CFG_MONEN_MASK (0x4U) | ||
| 2651 | #define I2C_CFG_MONEN_SHIFT (2U) | ||
| 2652 | /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not | ||
| 2653 | * changed, but the Monitor function is internally reset. | ||
| 2654 | * 0b0..Disabled. The I2C Monitor function is disabled. | ||
| 2655 | * 0b1..Enabled. The I2C Monitor function is enabled. | ||
| 2656 | */ | ||
| 2657 | #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) | ||
| 2658 | #define I2C_CFG_TIMEOUTEN_MASK (0x8U) | ||
| 2659 | #define I2C_CFG_TIMEOUTEN_SHIFT (3U) | ||
| 2660 | /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. | ||
| 2661 | * 0b0..Disabled. Time-out function is disabled. | ||
| 2662 | * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause | ||
| 2663 | * interrupts if they are enabled. Typically, only one time-out will be used in a system. | ||
| 2664 | */ | ||
| 2665 | #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) | ||
| 2666 | #define I2C_CFG_MONCLKSTR_MASK (0x10U) | ||
| 2667 | #define I2C_CFG_MONCLKSTR_SHIFT (4U) | ||
| 2668 | /*! MONCLKSTR - Monitor function Clock Stretching. | ||
| 2669 | * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able | ||
| 2670 | * to read data provided by the Monitor function before it is overwritten. This mode may be used when | ||
| 2671 | * non-invasive monitoring is critical. | ||
| 2672 | * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can | ||
| 2673 | * read all incoming data supplied by the Monitor function. | ||
| 2674 | */ | ||
| 2675 | #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) | ||
| 2676 | /*! @} */ | ||
| 2677 | |||
| 2678 | /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ | ||
| 2679 | /*! @{ */ | ||
| 2680 | #define I2C_STAT_MSTPENDING_MASK (0x1U) | ||
| 2681 | #define I2C_STAT_MSTPENDING_SHIFT (0U) | ||
| 2682 | /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on | ||
| 2683 | * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what | ||
| 2684 | * type of software service if any the master expects. This flag will cause an interrupt when set | ||
| 2685 | * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling | ||
| 2686 | * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle | ||
| 2687 | * state, and no communication is needed, mask this interrupt. | ||
| 2688 | * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. | ||
| 2689 | * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the | ||
| 2690 | * idle state, it is waiting to receive or transmit data or the NACK bit. | ||
| 2691 | */ | ||
| 2692 | #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) | ||
| 2693 | #define I2C_STAT_MSTSTATE_MASK (0xEU) | ||
| 2694 | #define I2C_STAT_MSTSTATE_SHIFT (1U) | ||
| 2695 | /*! MSTSTATE - Master State code. The master state code reflects the master state when the | ||
| 2696 | * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field | ||
| 2697 | * indicates a specific required service for the Master function. All other values are reserved. See | ||
| 2698 | * Table 400 for details of state values and appropriate responses. | ||
| 2699 | * 0b000..Idle. The Master function is available to be used for a new transaction. | ||
| 2700 | * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. | ||
| 2701 | * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. | ||
| 2702 | * 0b011..NACK Address. Slave NACKed address. | ||
| 2703 | * 0b100..NACK Data. Slave NACKed transmitted data. | ||
| 2704 | */ | ||
| 2705 | #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) | ||
| 2706 | #define I2C_STAT_MSTARBLOSS_MASK (0x10U) | ||
| 2707 | #define I2C_STAT_MSTARBLOSS_SHIFT (4U) | ||
| 2708 | /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to | ||
| 2709 | * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. | ||
| 2710 | * 0b0..No Arbitration Loss has occurred. | ||
| 2711 | * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master | ||
| 2712 | * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, | ||
| 2713 | * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. | ||
| 2714 | */ | ||
| 2715 | #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) | ||
| 2716 | #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) | ||
| 2717 | #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) | ||
| 2718 | /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to | ||
| 2719 | * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. | ||
| 2720 | * 0b0..No Start/Stop Error has occurred. | ||
| 2721 | * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is | ||
| 2722 | * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an | ||
| 2723 | * idle state, no action is required. A request for a Start could be made, or software could attempt to insure | ||
| 2724 | * that the bus has not stalled. | ||
| 2725 | */ | ||
| 2726 | #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) | ||
| 2727 | #define I2C_STAT_SLVPENDING_MASK (0x100U) | ||
| 2728 | #define I2C_STAT_SLVPENDING_SHIFT (8U) | ||
| 2729 | /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue | ||
| 2730 | * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if | ||
| 2731 | * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the | ||
| 2732 | * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is | ||
| 2733 | * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time | ||
| 2734 | * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section | ||
| 2735 | * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are | ||
| 2736 | * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must | ||
| 2737 | * also be detected automatically, since the address must be acknowledged before the clock can be | ||
| 2738 | * stretched. | ||
| 2739 | * 0b0..In progress. The Slave function does not currently need service. | ||
| 2740 | * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. | ||
| 2741 | */ | ||
| 2742 | #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) | ||
| 2743 | #define I2C_STAT_SLVSTATE_MASK (0x600U) | ||
| 2744 | #define I2C_STAT_SLVSTATE_SHIFT (9U) | ||
| 2745 | /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for | ||
| 2746 | * the Slave function. All other values are reserved. See Table 401 for state values and actions. | ||
| 2747 | * note that the occurrence of some states and how they are handled are affected by DMA mode and | ||
| 2748 | * Automatic Operation modes. | ||
| 2749 | * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. | ||
| 2750 | * 0b01..Slave receive. Received data is available (Slave Receiver mode). | ||
| 2751 | * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). | ||
| 2752 | */ | ||
| 2753 | #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) | ||
| 2754 | #define I2C_STAT_SLVNOTSTR_MASK (0x800U) | ||
| 2755 | #define I2C_STAT_SLVNOTSTR_SHIFT (11U) | ||
| 2756 | /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. | ||
| 2757 | * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave | ||
| 2758 | * operation. This read-only flag reflects the slave function status in real time. | ||
| 2759 | * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. | ||
| 2760 | * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or | ||
| 2761 | * Power-down mode could be entered at this time. | ||
| 2762 | */ | ||
| 2763 | #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) | ||
| 2764 | #define I2C_STAT_SLVIDX_MASK (0x3000U) | ||
| 2765 | #define I2C_STAT_SLVIDX_SHIFT (12U) | ||
| 2766 | /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been | ||
| 2767 | * selected by receiving an address that matches one of the slave addresses defined by any enabled | ||
| 2768 | * slave address registers, and provides an identification of the address that was matched. It is | ||
| 2769 | * possible that more than one address could be matched, but only one match can be reported here. | ||
| 2770 | * 0b00..Address 0. Slave address 0 was matched. | ||
| 2771 | * 0b01..Address 1. Slave address 1 was matched. | ||
| 2772 | * 0b10..Address 2. Slave address 2 was matched. | ||
| 2773 | * 0b11..Address 3. Slave address 3 was matched. | ||
| 2774 | */ | ||
| 2775 | #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) | ||
| 2776 | #define I2C_STAT_SLVSEL_MASK (0x4000U) | ||
| 2777 | #define I2C_STAT_SLVSEL_SHIFT (14U) | ||
| 2778 | /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave | ||
| 2779 | * function to acknowledge the address, or when the address has been automatically acknowledged. | ||
| 2780 | * It is cleared when another address cycle presents an address that does not match an enabled | ||
| 2781 | * address on the Slave function, when slave software decides to NACK a matched address, when | ||
| 2782 | * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of | ||
| 2783 | * Automatic Operation. SLVSEL is not cleared if software NACKs data. | ||
| 2784 | * 0b0..Not selected. The Slave function is not currently selected. | ||
| 2785 | * 0b1..Selected. The Slave function is currently selected. | ||
| 2786 | */ | ||
| 2787 | #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) | ||
| 2788 | #define I2C_STAT_SLVDESEL_MASK (0x8000U) | ||
| 2789 | #define I2C_STAT_SLVDESEL_SHIFT (15U) | ||
| 2790 | /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via | ||
| 2791 | * INTENSET. This flag can be cleared by writing a 1 to this bit. | ||
| 2792 | * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently | ||
| 2793 | * selected. That information can be found in the SLVSEL flag. | ||
| 2794 | * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag | ||
| 2795 | * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. | ||
| 2796 | */ | ||
| 2797 | #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) | ||
| 2798 | #define I2C_STAT_MONRDY_MASK (0x10000U) | ||
| 2799 | #define I2C_STAT_MONRDY_SHIFT (16U) | ||
| 2800 | /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. | ||
| 2801 | * 0b0..No data. The Monitor function does not currently have data available. | ||
| 2802 | * 0b1..Data waiting. The Monitor function has data waiting to be read. | ||
| 2803 | */ | ||
| 2804 | #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) | ||
| 2805 | #define I2C_STAT_MONOV_MASK (0x20000U) | ||
| 2806 | #define I2C_STAT_MONOV_SHIFT (17U) | ||
| 2807 | /*! MONOV - Monitor Overflow flag. | ||
| 2808 | * 0b0..No overrun. Monitor data has not overrun. | ||
| 2809 | * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not | ||
| 2810 | * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. | ||
| 2811 | */ | ||
| 2812 | #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) | ||
| 2813 | #define I2C_STAT_MONACTIVE_MASK (0x40000U) | ||
| 2814 | #define I2C_STAT_MONACTIVE_SHIFT (18U) | ||
| 2815 | /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to | ||
| 2816 | * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred | ||
| 2817 | * more recently than a bus Stop. | ||
| 2818 | * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. | ||
| 2819 | * 0b1..Active. The Monitor function considers the I2C bus to be active. | ||
| 2820 | */ | ||
| 2821 | #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) | ||
| 2822 | #define I2C_STAT_MONIDLE_MASK (0x80000U) | ||
| 2823 | #define I2C_STAT_MONIDLE_SHIFT (19U) | ||
| 2824 | /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change | ||
| 2825 | * from active to inactive. This can be used by software to decide when to process data | ||
| 2826 | * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the | ||
| 2827 | * INTENSET register. The flag can be cleared by writing a 1 to this bit. | ||
| 2828 | * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. | ||
| 2829 | * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. | ||
| 2830 | */ | ||
| 2831 | #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) | ||
| 2832 | #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) | ||
| 2833 | #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) | ||
| 2834 | /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been | ||
| 2835 | * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock | ||
| 2836 | * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus | ||
| 2837 | * is idle. | ||
| 2838 | * 0b0..No time-out. I2C bus events have not caused a time-out. | ||
| 2839 | * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. | ||
| 2840 | */ | ||
| 2841 | #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) | ||
| 2842 | #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) | ||
| 2843 | #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) | ||
| 2844 | /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the | ||
| 2845 | * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. | ||
| 2846 | * 0b0..No time-out. SCL low time has not caused a time-out. | ||
| 2847 | * 0b1..Time-out. SCL low time has caused a time-out. | ||
| 2848 | */ | ||
| 2849 | #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) | ||
| 2850 | /*! @} */ | ||
| 2851 | |||
| 2852 | /*! @name INTENSET - Interrupt Enable Set and read register. */ | ||
| 2853 | /*! @{ */ | ||
| 2854 | #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) | ||
| 2855 | #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) | ||
| 2856 | /*! MSTPENDINGEN - Master Pending interrupt Enable. | ||
| 2857 | * 0b0..Disabled. The MstPending interrupt is disabled. | ||
| 2858 | * 0b1..Enabled. The MstPending interrupt is enabled. | ||
| 2859 | */ | ||
| 2860 | #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) | ||
| 2861 | #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) | ||
| 2862 | #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) | ||
| 2863 | /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. | ||
| 2864 | * 0b0..Disabled. The MstArbLoss interrupt is disabled. | ||
| 2865 | * 0b1..Enabled. The MstArbLoss interrupt is enabled. | ||
| 2866 | */ | ||
| 2867 | #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) | ||
| 2868 | #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) | ||
| 2869 | #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) | ||
| 2870 | /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. | ||
| 2871 | * 0b0..Disabled. The MstStStpErr interrupt is disabled. | ||
| 2872 | * 0b1..Enabled. The MstStStpErr interrupt is enabled. | ||
| 2873 | */ | ||
| 2874 | #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) | ||
| 2875 | #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) | ||
| 2876 | #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) | ||
| 2877 | /*! SLVPENDINGEN - Slave Pending interrupt Enable. | ||
| 2878 | * 0b0..Disabled. The SlvPending interrupt is disabled. | ||
| 2879 | * 0b1..Enabled. The SlvPending interrupt is enabled. | ||
| 2880 | */ | ||
| 2881 | #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) | ||
| 2882 | #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) | ||
| 2883 | #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) | ||
| 2884 | /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. | ||
| 2885 | * 0b0..Disabled. The SlvNotStr interrupt is disabled. | ||
| 2886 | * 0b1..Enabled. The SlvNotStr interrupt is enabled. | ||
| 2887 | */ | ||
| 2888 | #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) | ||
| 2889 | #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) | ||
| 2890 | #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) | ||
| 2891 | /*! SLVDESELEN - Slave Deselect interrupt Enable. | ||
| 2892 | * 0b0..Disabled. The SlvDeSel interrupt is disabled. | ||
| 2893 | * 0b1..Enabled. The SlvDeSel interrupt is enabled. | ||
| 2894 | */ | ||
| 2895 | #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) | ||
| 2896 | #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) | ||
| 2897 | #define I2C_INTENSET_MONRDYEN_SHIFT (16U) | ||
| 2898 | /*! MONRDYEN - Monitor data Ready interrupt Enable. | ||
| 2899 | * 0b0..Disabled. The MonRdy interrupt is disabled. | ||
| 2900 | * 0b1..Enabled. The MonRdy interrupt is enabled. | ||
| 2901 | */ | ||
| 2902 | #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) | ||
| 2903 | #define I2C_INTENSET_MONOVEN_MASK (0x20000U) | ||
| 2904 | #define I2C_INTENSET_MONOVEN_SHIFT (17U) | ||
| 2905 | /*! MONOVEN - Monitor Overrun interrupt Enable. | ||
| 2906 | * 0b0..Disabled. The MonOv interrupt is disabled. | ||
| 2907 | * 0b1..Enabled. The MonOv interrupt is enabled. | ||
| 2908 | */ | ||
| 2909 | #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) | ||
| 2910 | #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) | ||
| 2911 | #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) | ||
| 2912 | /*! MONIDLEEN - Monitor Idle interrupt Enable. | ||
| 2913 | * 0b0..Disabled. The MonIdle interrupt is disabled. | ||
| 2914 | * 0b1..Enabled. The MonIdle interrupt is enabled. | ||
| 2915 | */ | ||
| 2916 | #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) | ||
| 2917 | #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) | ||
| 2918 | #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) | ||
| 2919 | /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. | ||
| 2920 | * 0b0..Disabled. The Event time-out interrupt is disabled. | ||
| 2921 | * 0b1..Enabled. The Event time-out interrupt is enabled. | ||
| 2922 | */ | ||
| 2923 | #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) | ||
| 2924 | #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) | ||
| 2925 | #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) | ||
| 2926 | /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. | ||
| 2927 | * 0b0..Disabled. The SCL time-out interrupt is disabled. | ||
| 2928 | * 0b1..Enabled. The SCL time-out interrupt is enabled. | ||
| 2929 | */ | ||
| 2930 | #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) | ||
| 2931 | /*! @} */ | ||
| 2932 | |||
| 2933 | /*! @name INTENCLR - Interrupt Enable Clear register. */ | ||
| 2934 | /*! @{ */ | ||
| 2935 | #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) | ||
| 2936 | #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) | ||
| 2937 | /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding | ||
| 2938 | * bit in the INTENSET register if implemented. | ||
| 2939 | */ | ||
| 2940 | #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) | ||
| 2941 | #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) | ||
| 2942 | #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) | ||
| 2943 | /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. | ||
| 2944 | */ | ||
| 2945 | #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) | ||
| 2946 | #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) | ||
| 2947 | #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) | ||
| 2948 | /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. | ||
| 2949 | */ | ||
| 2950 | #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) | ||
| 2951 | #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) | ||
| 2952 | #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) | ||
| 2953 | /*! SLVPENDINGCLR - Slave Pending interrupt clear. | ||
| 2954 | */ | ||
| 2955 | #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) | ||
| 2956 | #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) | ||
| 2957 | #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) | ||
| 2958 | /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. | ||
| 2959 | */ | ||
| 2960 | #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) | ||
| 2961 | #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) | ||
| 2962 | #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) | ||
| 2963 | /*! SLVDESELCLR - Slave Deselect interrupt clear. | ||
| 2964 | */ | ||
| 2965 | #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) | ||
| 2966 | #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) | ||
| 2967 | #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) | ||
| 2968 | /*! MONRDYCLR - Monitor data Ready interrupt clear. | ||
| 2969 | */ | ||
| 2970 | #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) | ||
| 2971 | #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) | ||
| 2972 | #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) | ||
| 2973 | /*! MONOVCLR - Monitor Overrun interrupt clear. | ||
| 2974 | */ | ||
| 2975 | #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) | ||
| 2976 | #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) | ||
| 2977 | #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) | ||
| 2978 | /*! MONIDLECLR - Monitor Idle interrupt clear. | ||
| 2979 | */ | ||
| 2980 | #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) | ||
| 2981 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) | ||
| 2982 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) | ||
| 2983 | /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. | ||
| 2984 | */ | ||
| 2985 | #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) | ||
| 2986 | #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) | ||
| 2987 | #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) | ||
| 2988 | /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. | ||
| 2989 | */ | ||
| 2990 | #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) | ||
| 2991 | /*! @} */ | ||
| 2992 | |||
| 2993 | /*! @name TIMEOUT - Time-out value register. */ | ||
| 2994 | /*! @{ */ | ||
| 2995 | #define I2C_TIMEOUT_TOMIN_MASK (0xFU) | ||
| 2996 | #define I2C_TIMEOUT_TOMIN_SHIFT (0U) | ||
| 2997 | /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum | ||
| 2998 | * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. | ||
| 2999 | */ | ||
| 3000 | #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) | ||
| 3001 | #define I2C_TIMEOUT_TO_MASK (0xFFF0U) | ||
| 3002 | #define I2C_TIMEOUT_TO_SHIFT (4U) | ||
| 3003 | /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C | ||
| 3004 | * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, | ||
| 3005 | * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A | ||
| 3006 | * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after | ||
| 3007 | * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the | ||
| 3008 | * I2C function clock. | ||
| 3009 | */ | ||
| 3010 | #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) | ||
| 3011 | /*! @} */ | ||
| 3012 | |||
| 3013 | /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ | ||
| 3014 | /*! @{ */ | ||
| 3015 | #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) | ||
| 3016 | #define I2C_CLKDIV_DIVVAL_SHIFT (0U) | ||
| 3017 | /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that | ||
| 3018 | * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = | ||
| 3019 | * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is | ||
| 3020 | * divided by 65,536 before use. | ||
| 3021 | */ | ||
| 3022 | #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) | ||
| 3023 | /*! @} */ | ||
| 3024 | |||
| 3025 | /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ | ||
| 3026 | /*! @{ */ | ||
| 3027 | #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) | ||
| 3028 | #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) | ||
| 3029 | /*! MSTPENDING - Master Pending. | ||
| 3030 | */ | ||
| 3031 | #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) | ||
| 3032 | #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) | ||
| 3033 | #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) | ||
| 3034 | /*! MSTARBLOSS - Master Arbitration Loss flag. | ||
| 3035 | */ | ||
| 3036 | #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) | ||
| 3037 | #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) | ||
| 3038 | #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) | ||
| 3039 | /*! MSTSTSTPERR - Master Start/Stop Error flag. | ||
| 3040 | */ | ||
| 3041 | #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) | ||
| 3042 | #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) | ||
| 3043 | #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) | ||
| 3044 | /*! SLVPENDING - Slave Pending. | ||
| 3045 | */ | ||
| 3046 | #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) | ||
| 3047 | #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) | ||
| 3048 | #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) | ||
| 3049 | /*! SLVNOTSTR - Slave Not Stretching status. | ||
| 3050 | */ | ||
| 3051 | #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) | ||
| 3052 | #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) | ||
| 3053 | #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) | ||
| 3054 | /*! SLVDESEL - Slave Deselected flag. | ||
| 3055 | */ | ||
| 3056 | #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) | ||
| 3057 | #define I2C_INTSTAT_MONRDY_MASK (0x10000U) | ||
| 3058 | #define I2C_INTSTAT_MONRDY_SHIFT (16U) | ||
| 3059 | /*! MONRDY - Monitor Ready. | ||
| 3060 | */ | ||
| 3061 | #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) | ||
| 3062 | #define I2C_INTSTAT_MONOV_MASK (0x20000U) | ||
| 3063 | #define I2C_INTSTAT_MONOV_SHIFT (17U) | ||
| 3064 | /*! MONOV - Monitor Overflow flag. | ||
| 3065 | */ | ||
| 3066 | #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) | ||
| 3067 | #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) | ||
| 3068 | #define I2C_INTSTAT_MONIDLE_SHIFT (19U) | ||
| 3069 | /*! MONIDLE - Monitor Idle flag. | ||
| 3070 | */ | ||
| 3071 | #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) | ||
| 3072 | #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) | ||
| 3073 | #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) | ||
| 3074 | /*! EVENTTIMEOUT - Event time-out Interrupt flag. | ||
| 3075 | */ | ||
| 3076 | #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) | ||
| 3077 | #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) | ||
| 3078 | #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) | ||
| 3079 | /*! SCLTIMEOUT - SCL time-out Interrupt flag. | ||
| 3080 | */ | ||
| 3081 | #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) | ||
| 3082 | /*! @} */ | ||
| 3083 | |||
| 3084 | /*! @name MSTCTL - Master control register. */ | ||
| 3085 | /*! @{ */ | ||
| 3086 | #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) | ||
| 3087 | #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) | ||
| 3088 | /*! MSTCONTINUE - Master Continue. | ||
| 3089 | * 0b0..No effect. | ||
| 3090 | * 0b1..Informs the Master function to continue to the next operation. | ||
| 3091 | */ | ||
| 3092 | #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) | ||
| 3093 | #define I2C_MSTCTL_MSTSTART_MASK (0x2U) | ||
| 3094 | #define I2C_MSTCTL_MSTSTART_SHIFT (1U) | ||
| 3095 | /*! MSTSTART - Master Start control. | ||
| 3096 | * 0b0..No effect. | ||
| 3097 | * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. | ||
| 3098 | */ | ||
| 3099 | #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) | ||
| 3100 | #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) | ||
| 3101 | #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) | ||
| 3102 | /*! MSTSTOP - Master Stop control. | ||
| 3103 | * 0b0..No effect. | ||
| 3104 | * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave | ||
| 3105 | * if the master is receiving data from the slave (Master Receiver mode). | ||
| 3106 | */ | ||
| 3107 | #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) | ||
| 3108 | #define I2C_MSTCTL_MSTDMA_MASK (0x8U) | ||
| 3109 | #define I2C_MSTCTL_MSTDMA_SHIFT (3U) | ||
| 3110 | /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type | ||
| 3111 | * operations such as Start, address, Stop, and address match must always be done with software, | ||
| 3112 | * typically via an interrupt. Address acknowledgement must also be done by software except when | ||
| 3113 | * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by | ||
| 3114 | * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA | ||
| 3115 | * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is | ||
| 3116 | * read/write. | ||
| 3117 | * 0b0..Disable. No DMA requests are generated for master operation. | ||
| 3118 | * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating | ||
| 3119 | * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. | ||
| 3120 | */ | ||
| 3121 | #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) | ||
| 3122 | /*! @} */ | ||
| 3123 | |||
| 3124 | /*! @name MSTTIME - Master timing configuration. */ | ||
| 3125 | /*! @{ */ | ||
| 3126 | #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) | ||
| 3127 | #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) | ||
| 3128 | /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this | ||
| 3129 | * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This | ||
| 3130 | * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters | ||
| 3131 | * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. | ||
| 3132 | * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. | ||
| 3133 | * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. | ||
| 3134 | * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. | ||
| 3135 | * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. | ||
| 3136 | * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. | ||
| 3137 | * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. | ||
| 3138 | * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. | ||
| 3139 | * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. | ||
| 3140 | */ | ||
| 3141 | #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) | ||
| 3142 | #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) | ||
| 3143 | #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) | ||
| 3144 | /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this | ||
| 3145 | * master on SCL. Other masters in a multi-master system could shorten this time. This | ||
| 3146 | * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters | ||
| 3147 | * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. | ||
| 3148 | * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. | ||
| 3149 | * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . | ||
| 3150 | * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. | ||
| 3151 | * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. | ||
| 3152 | * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. | ||
| 3153 | * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. | ||
| 3154 | * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. | ||
| 3155 | * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. | ||
| 3156 | */ | ||
| 3157 | #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) | ||
| 3158 | /*! @} */ | ||
| 3159 | |||
| 3160 | /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ | ||
| 3161 | /*! @{ */ | ||
| 3162 | #define I2C_MSTDAT_DATA_MASK (0xFFU) | ||
| 3163 | #define I2C_MSTDAT_DATA_SHIFT (0U) | ||
| 3164 | /*! DATA - Master function data register. Read: read the most recently received data for the Master | ||
| 3165 | * function. Write: transmit data using the Master function. | ||
| 3166 | */ | ||
| 3167 | #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) | ||
| 3168 | /*! @} */ | ||
| 3169 | |||
| 3170 | /*! @name SLVCTL - Slave control register. */ | ||
| 3171 | /*! @{ */ | ||
| 3172 | #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) | ||
| 3173 | #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) | ||
| 3174 | /*! SLVCONTINUE - Slave Continue. | ||
| 3175 | * 0b0..No effect. | ||
| 3176 | * 0b1..Informs the Slave function to continue to the next operation. | ||
| 3177 | */ | ||
| 3178 | #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) | ||
| 3179 | #define I2C_SLVCTL_SLVNACK_MASK (0x2U) | ||
| 3180 | #define I2C_SLVCTL_SLVNACK_SHIFT (1U) | ||
| 3181 | /*! SLVNACK - Slave NACK. | ||
| 3182 | * 0b0..No effect. | ||
| 3183 | * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). | ||
| 3184 | */ | ||
| 3185 | #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) | ||
| 3186 | #define I2C_SLVCTL_SLVDMA_MASK (0x8U) | ||
| 3187 | #define I2C_SLVCTL_SLVDMA_SHIFT (3U) | ||
| 3188 | /*! SLVDMA - Slave DMA enable. | ||
| 3189 | * 0b0..Disabled. No DMA requests are issued for Slave mode operation. | ||
| 3190 | * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. | ||
| 3191 | */ | ||
| 3192 | #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) | ||
| 3193 | /*! @} */ | ||
| 3194 | |||
| 3195 | /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ | ||
| 3196 | /*! @{ */ | ||
| 3197 | #define I2C_SLVDAT_DATA_MASK (0xFFU) | ||
| 3198 | #define I2C_SLVDAT_DATA_SHIFT (0U) | ||
| 3199 | /*! DATA - Slave function data register. Read: read the most recently received data for the Slave | ||
| 3200 | * function. Write: transmit data using the Slave function. | ||
| 3201 | */ | ||
| 3202 | #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) | ||
| 3203 | /*! @} */ | ||
| 3204 | |||
| 3205 | /*! @name SLVADR - Slave address register. */ | ||
| 3206 | /*! @{ */ | ||
| 3207 | #define I2C_SLVADR_SADISABLE_MASK (0x1U) | ||
| 3208 | #define I2C_SLVADR_SADISABLE_SHIFT (0U) | ||
| 3209 | /*! SADISABLE - Slave Address n Disable. | ||
| 3210 | * 0b0..Enabled. Slave Address n is enabled. | ||
| 3211 | * 0b1..Ignored Slave Address n is ignored. | ||
| 3212 | */ | ||
| 3213 | #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) | ||
| 3214 | #define I2C_SLVADR_SLVADR_MASK (0xFEU) | ||
| 3215 | #define I2C_SLVADR_SLVADR_SHIFT (1U) | ||
| 3216 | /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. | ||
| 3217 | */ | ||
| 3218 | #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) | ||
| 3219 | /*! @} */ | ||