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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/drivers/fsl_clock.h
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/LPC844/drivers/fsl_clock.h
@@ -0,0 +1,697 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22/*! @name Driver version */
23/*@{*/
24/*! @brief CLOCK driver version 2.3.2. */
25#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
26/*@}*/
27
28/* Definition for delay API in clock driver, users can redefine it to the real application. */
29#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (30000000UL)
31#endif
32
33/*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38extern volatile uint32_t g_Wdt_Osc_Freq;
39
40/*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48extern volatile uint32_t g_Ext_Clk_Freq;
49
50/*! @brief FRO clock setting API address in ROM. */
51#define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F0026F5U)
52/*! @brief FAIM base address*/
53#define CLOCK_FAIM_BASE (0x50010000U)
54
55/*! @brief Clock ip name array for ADC. */
56#define ADC_CLOCKS \
57 { \
58 kCLOCK_Adc, \
59 }
60/*! @brief Clock ip name array for ACMP. */
61#define ACMP_CLOCKS \
62 { \
63 kCLOCK_Acmp, \
64 }
65/*! @brief Clock ip name array for SWM. */
66#define SWM_CLOCKS \
67 { \
68 kCLOCK_Swm, \
69 }
70/*! @brief Clock ip name array for ROM. */
71#define ROM_CLOCKS \
72 { \
73 kCLOCK_Rom, \
74 }
75/*! @brief Clock ip name array for SRAM. */
76#define SRAM_CLOCKS \
77 { \
78 kCLOCK_Ram0_1, \
79 }
80/*! @brief Clock ip name array for IOCON. */
81#define IOCON_CLOCKS \
82 { \
83 kCLOCK_Iocon, \
84 }
85/*! @brief Clock ip name array for GPIO. */
86#define GPIO_CLOCKS \
87 { \
88 kCLOCK_Gpio0, kCLOCK_Gpio1, \
89 }
90/*! @brief Clock ip name array for GPIO_INT. */
91#define GPIO_INT_CLOCKS \
92 { \
93 kCLOCK_GpioInt, \
94 }
95/*! @brief Clock ip name array for DMA. */
96#define DMA_CLOCKS \
97 { \
98 kCLOCK_Dma, \
99 }
100/*! @brief Clock ip name array for CRC. */
101#define CRC_CLOCKS \
102 { \
103 kCLOCK_Crc, \
104 }
105/*! @brief Clock ip name array for WWDT. */
106#define WWDT_CLOCKS \
107 { \
108 kCLOCK_Wwdt, \
109 }
110/*! @brief Clock ip name array for SCT0. */
111#define SCT_CLOCKS \
112 { \
113 kCLOCK_Sct, \
114 }
115/*! @brief Clock ip name array for I2C. */
116#define I2C_CLOCKS \
117 { \
118 kCLOCK_I2c0, kCLOCK_I2c1, \
119 }
120/*! @brief Clock ip name array for I2C. */
121#define USART_CLOCKS \
122 { \
123 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
124 }
125/*! @brief Clock ip name array for SPI. */
126#define SPI_CLOCKS \
127 { \
128 kCLOCK_Spi0, kCLOCK_Spi1, \
129 }
130/*! @brief Clock ip name array for CTIMER. */
131#define CTIMER_CLOCKS \
132 { \
133 kCLOCK_Ctimer0, \
134 }
135/*! @brief Clock ip name array for MTB. */
136#define MTB_CLOCKS \
137 { \
138 kCLOCK_Mtb, \
139 }
140/*! @brief Clock ip name array for MRT. */
141#define MRT_CLOCKS \
142 { \
143 kCLOCK_Mrt, \
144 }
145/*! @brief Clock ip name array for WKT. */
146#define WKT_CLOCKS \
147 { \
148 kCLOCK_Wkt, \
149 }
150
151/*! @brief Internal used Clock definition only. */
152#define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
153#define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
154#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
155/* clock mux register definition */
156#define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
157#define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
158#define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
159#define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
160#define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
161#define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
162/* clock divider register definition */
163#define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
164#define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
165/* watch dog oscillator definition */
166#define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
167#define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)(x)&0xFFFFFFU)
168#define CLK_WDT_OSC_GET_REG(x) (((uint32_t)(x) >> 24U) & 0xFFU)
169/* Fractional clock register map */
170#define CLK_FRG_DIV_REG_MAP(base) (*(base))
171#define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
172#define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
173/* register offset */
174#define SYS_AHB_CLK_CTRL0 (0U)
175/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
176typedef enum _clock_ip_name
177{
178 kCLOCK_IpInvalid = 0U,
179 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U),
180 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U),
181 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U),
182 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U),
183 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U),
184 kCLOCK_Sct = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 8U),
185 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U),
186 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U),
187 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U),
188 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 12U),
189 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U),
190 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U),
191 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U),
192 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 16U),
193 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U),
194 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U),
195 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U),
196 kCLOCK_Gpio1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 20U),
197 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U),
198 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U),
199 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U),
200 kCLOCK_Mtb = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 26U),
201 kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U),
202 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 29U),
203 kCLOCK_Uart3 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 30U),
204 kCLOCK_Uart4 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 31U),
205} clock_ip_name_t;
206
207/*! @brief Clock name used to get clock frequency. */
208typedef enum _clock_name
209{
210 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
211 kCLOCK_MainClk, /*!< Main clock */
212
213 kCLOCK_Fro, /*!< FRO18/24/30 */
214 kCLOCK_FroDiv, /*!< FRO div clock */
215 kCLOCK_ExtClk, /*!< External Clock */
216 kCLOCK_PllOut, /*!< PLL Output */
217 kCLOCK_WdtOsc, /*!< Watchdog Oscillator */
218 kCLOCK_Frg0, /*!< fractional rate0 */
219 kCLOCK_Frg1, /*!< fractional rate1 */
220} clock_name_t;
221
222/*! @brief Clock Mux Switches
223 *CLK_MUX_DEFINE(reg, mux)
224 *reg is used to define the mux register
225 *mux is used to define the mux value
226 *
227 */
228typedef enum _clock_select
229{
230 kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U),
231 kADC_Clk_From_SysPll = CLK_MUX_DEFINE(ADCCLKSEL, 1U),
232
233 kSCT_Clk_From_Fro = CLK_MUX_DEFINE(SCTCLKSEL, 0U),
234 kSCT_Clk_From_MainClk = CLK_MUX_DEFINE(SCTCLKSEL, 1U),
235 kSCT_Clk_From_SysPll = CLK_MUX_DEFINE(SCTCLKSEL, 2U),
236
237 kEXT_Clk_From_SysOsc = CLK_MUX_DEFINE(EXTCLKSEL, 0U),
238 kEXT_Clk_From_ClkIn = CLK_MUX_DEFINE(EXTCLKSEL, 1U),
239
240 kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U),
241 kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U),
242 kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U),
243 kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U),
244 kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U),
245
246 kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U),
247 kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U),
248 kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U),
249 kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U),
250 kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U),
251
252 kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U),
253 kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U),
254 kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U),
255 kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U),
256 kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U),
257
258 kUART3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[3U], 0U),
259 kUART3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[3U], 1U),
260 kUART3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 2U),
261 kUART3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 3U),
262 kUART3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[3U], 4U),
263
264 kUART4_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[4U], 0U),
265 kUART4_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[4U], 1U),
266 kUART4_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 2U),
267 kUART4_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 3U),
268 kUART4_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[4U], 4U),
269
270 kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U),
271 kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U),
272 kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U),
273 kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U),
274 kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U),
275
276 kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[6U], 0U),
277 kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[6U], 1U),
278 kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 2U),
279 kI2C1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 3U),
280 kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[6U], 4U),
281
282 kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[9U], 0U),
283 kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[9U], 1U),
284 kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 2U),
285 kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 3U),
286 kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[9U], 4U),
287
288 kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[10U], 0U),
289 kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[10U], 1U),
290 kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 2U),
291 kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 3U),
292 kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[10U], 4U),
293
294 kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 0U),
295 kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 1U),
296 kFRG0_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 2U),
297
298 kFRG1_Clk_From_Fro = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 0U),
299 kFRG1_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 1U),
300 kFRG1_Clk_From_SysPll = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 2U),
301
302 kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U),
303 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U),
304 kCLKOUT_From_SysPll = CLK_MUX_DEFINE(CLKOUTSEL, 2U),
305 kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U),
306 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 4U),
307} clock_select_t;
308
309/*! @brief Clock divider
310 */
311typedef enum _clock_divider
312{
313 kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV),
314 kCLOCK_DivSctClk = CLK_DIV_DEFINE(SCTCLKDIV),
315 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV),
316
317 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6),
318 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5),
319 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4),
320 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3),
321 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2),
322 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1),
323 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0),
324} clock_divider_t;
325
326/*! @brief watch dog analog output frequency */
327typedef enum _clock_wdt_analog_freq
328{
329 kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
330 kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
331 kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
332 kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
333 kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
334 kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
335 kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
336 kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
337 kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
338 kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
339 kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
340 kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
341 kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
342 kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
343 kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
344 kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
345} clock_wdt_analog_freq_t;
346
347/*! @brief fro output frequency source definition */
348typedef enum _clock_fro_src
349{
350 kCLOCK_FroSrcLpwrBootValue = 0U, /*!< fro source from the fro oscillator divided by low power boot value */
351 kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT, /*!< fre source from the fro oscillator directly */
352} clock_fro_src_t;
353
354/*! @brief fro oscillator output frequency value definition */
355typedef enum _clock_fro_osc_freq
356{
357 kCLOCK_FroOscOut18M = 18000U, /*!< FRO oscillator output 18M */
358 kCLOCK_FroOscOut24M = 24000U, /*!< FRO oscillator output 24M */
359 kCLOCK_FroOscOut30M = 30000U, /*!< FRO oscillator output 30M */
360} clock_fro_osc_freq_t;
361
362/*! @brief PLL clock definition.*/
363typedef enum _clock_sys_pll_src
364{
365 kCLOCK_SysPllSrcFRO = 0U, /*!< system pll source from FRO */
366 kCLOCK_SysPllSrcExtClk = 1U, /*!< system pll source from external clock */
367 kCLOCK_SysPllSrcWdtOsc = 2U, /*!< system pll source from watchdog oscillator */
368 kCLOCK_SysPllSrcFroDiv = 3U, /*!< system pll source from FRO divided clock */
369} clock_sys_pll_src;
370
371/*!< Main clock source definition */
372typedef enum _clock_main_clk_src
373{
374 kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
375 kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
376 kCLOCK_MainClkSrcWdtOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
377 kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
378 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U), /*!< main clock source from system pll */
379} clock_main_clk_src_t;
380
381/*! @brief PLL configuration structure */
382typedef struct _clock_sys_pll
383{
384 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
385 clock_sys_pll_src src; /*!< System pll clock source */
386} clock_sys_pll_t;
387
388/*******************************************************************************
389 * API
390 ******************************************************************************/
391
392#if defined(__cplusplus)
393extern "C" {
394#endif /* __cplusplus */
395
396/*!
397 * @name Clock gate, mux, and divider.
398 * @{
399 */
400
401/*
402 *! @brief enable ip clock.
403 *
404 * @param clk clock ip definition.
405 */
406static inline void CLOCK_EnableClock(clock_ip_name_t clk)
407{
408 SYSCON->SYSAHBCLKCTRL0 |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
409}
410
411/*
412 *!@brief disable ip clock.
413 *
414 * @param clk clock ip definition.
415 */
416static inline void CLOCK_DisableClock(clock_ip_name_t clk)
417{
418 SYSCON->SYSAHBCLKCTRL0 &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
419}
420
421/*
422 *! @brief Configure the clock selection muxes.
423 * @param mux : Clock to be configured.
424 * @return Nothing
425 */
426static inline void CLOCK_Select(clock_select_t sel)
427{
428 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
429}
430
431/*
432 *! @brief Setup peripheral clock dividers.
433 * @param name : Clock divider name
434 * @param value: Value to be divided
435 * @return Nothing
436 */
437static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
438{
439 CLK_DIV_GET_REG(name) = value & 0xFFU;
440}
441
442/*
443 *! @brief Get peripheral clock dividers.
444 * @param name : Clock divider name
445 * @return clock divider value
446 */
447static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
448{
449 return CLK_DIV_GET_REG(name) & 0xFFU;
450}
451
452/*
453 *! @brief Setup Core clock dividers.
454 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
455 * @param value: Value to be divided
456 * @return Nothing
457 */
458static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
459{
460 assert(value != 0U);
461
462 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
463}
464
465/*! @brief Set main clock reference source.
466 * @param src, reference clock_main_clk_src_t to set the main clock source.
467 */
468void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
469
470/*! @brief Set FRO clock source
471 * @param src, please reference _clock_fro_src definition.
472 *
473 */
474void CLOCK_SetFroOutClkSrc(clock_fro_src_t src);
475
476/*
477 *! @brief Set Fractional generator multiplier value.
478 * @param base: Fractional generator register address
479 * @param mul : FRG multiplier value.
480 * @return Nothing
481 */
482static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
483{
484 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
485 CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
486}
487/* @} */
488
489/*!
490 * @name Get frequency
491 * @{
492 */
493
494/*! @brief Return Frequency of FRG0 Clock.
495 * @return Frequency of FRG0 Clock.
496 */
497uint32_t CLOCK_GetFRG0ClkFreq(void);
498
499/*! @brief Return Frequency of FRG1 Clock.
500 * @return Frequency of FRG1 Clock.
501 */
502uint32_t CLOCK_GetFRG1ClkFreq(void);
503
504/*! @brief Return Frequency of Main Clock.
505 * @return Frequency of Main Clock.
506 */
507uint32_t CLOCK_GetMainClkFreq(void);
508
509/*! @brief Return Frequency of FRO.
510 * @return Frequency of FRO.
511 */
512uint32_t CLOCK_GetFroFreq(void);
513
514/*! @brief Return Frequency of core.
515 * @return Frequency of core.
516 */
517static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
518{
519 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
520}
521
522/*! @brief Return Frequency of ClockOut
523 * @return Frequency of ClockOut
524 */
525uint32_t CLOCK_GetClockOutClkFreq(void);
526
527/*! @brief Get UART0 frequency
528 * @retval UART0 frequency value.
529 */
530uint32_t CLOCK_GetUart0ClkFreq(void);
531
532/*! @brief Get UART1 frequency
533 * @retval UART1 frequency value.
534 */
535uint32_t CLOCK_GetUart1ClkFreq(void);
536
537/*! @brief Get UART2 frequency
538 * @retval UART2 frequency value.
539 */
540uint32_t CLOCK_GetUart2ClkFreq(void);
541
542/*! @brief Get UART3 frequency
543 * @retval UART3 frequency value.
544 */
545uint32_t CLOCK_GetUart3ClkFreq(void);
546
547/*! @brief Get UART4 frequency
548 * @retval UART4 frequency value.
549 */
550uint32_t CLOCK_GetUart4ClkFreq(void);
551
552/*! @brief Return Frequency of selected clock
553 * @return Frequency of selected clock
554 */
555uint32_t CLOCK_GetFreq(clock_name_t clockName);
556
557/*! @brief Return System PLL input clock rate
558 * @return System PLL input clock rate
559 */
560uint32_t CLOCK_GetSystemPLLInClockRate(void);
561
562/*! @brief Return Frequency of System PLL
563 * @return Frequency of PLL
564 */
565static inline uint32_t CLOCK_GetSystemPLLFreq(void)
566{
567 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
568}
569
570/*! @brief Get watch dog OSC frequency
571 * @retval watch dog OSC frequency value.
572 */
573static inline uint32_t CLOCK_GetWdtOscFreq(void)
574{
575 return g_Wdt_Osc_Freq;
576}
577
578/*! @brief Get external clock frequency
579 * @retval external clock frequency value.
580 */
581static inline uint32_t CLOCK_GetExtClkFreq(void)
582{
583 return g_Ext_Clk_Freq;
584}
585/* @} */
586
587/*!
588 * @name PLL operations
589 * @{
590 */
591
592/*! @brief System PLL initialize.
593 * @param config System PLL configurations.
594 */
595void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
596
597/*! @brief System PLL Deinitialize.*/
598static inline void CLOCK_DenitSystemPll(void)
599{
600 /* Power off PLL */
601 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
602}
603
604/* @} */
605
606/*!
607 * @name Fractional clock operations
608 * @{
609 */
610
611/*! @brief Set FRG0 output frequency.
612 * @param freq, target output frequency,freq < input and (input / freq) < 2 should be satisfy.
613 * @retval true - successfully, false - input argument is invalid.
614 *
615 */
616bool CLOCK_SetFRG0ClkFreq(uint32_t freq);
617
618/*! @brief Set FRG1 output frequency.
619 * @param freq, target output frequency,freq < input and (input / freq) < 2 should be satisfy.
620 * @retval true - successfully, false - input argument is invalid.
621 *
622 */
623bool CLOCK_SetFRG1ClkFreq(uint32_t freq);
624
625/* @} */
626
627/*!
628 * @name External/internal oscillator clock operations
629 * @{
630 */
631
632/*! @brief Init external CLK IN, select the CLKIN as the external clock source.
633 * @param clkInFreq external clock in frequency.
634 */
635void CLOCK_InitExtClkin(uint32_t clkInFreq);
636
637/*! @brief Init SYS OSC
638 * @param oscFreq oscillator frequency value.
639 */
640void CLOCK_InitSysOsc(uint32_t oscFreq);
641
642/*! @brief XTALIN init function
643 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
644 * @param xtalInFreq XTALIN frequency value
645 * @return Frequency of PLL
646 */
647void CLOCK_InitXtalin(uint32_t xtalInFreq);
648
649/*! @brief Deinit SYS OSC
650 * @param config oscillator configuration.
651 */
652static inline void CLOCK_DeinitSysOsc(void)
653{
654 /* Deinit system osc power */
655 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
656}
657
658/*! @brief Init watch dog OSC
659 * Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
660 * listed frequency value. The watchdog oscillator is the clock source with the lowest power
661 * consumption. If accurate timing is required, use the FRO or system oscillator.
662 * The frequency of the watchdog oscillator is undefined after reset. The watchdog
663 * oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
664 * using the watchdog oscillator.
665 * Watchdog osc output frequency = wdtOscFreq / wdtOscDiv, should in range 9.3KHZ to 2.3MHZ.
666 * @param wdtOscFreq watch dog analog part output frequency, reference _wdt_analog_output_freq.
667 * @param wdtOscDiv watch dog analog part output frequency divider, shoule be a value >= 2U and multiple of 2
668 */
669void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
670
671/*! @brief Deinit watch dog OSC
672 * @param config oscillator configuration.
673 */
674static inline void CLOCK_DeinitWdtOsc(void)
675{
676 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_WDTOSC_PD_MASK;
677}
678
679/*! @brief Set FRO oscillator output frequency.
680 * Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
681 * @param freq, please reference clock_fro_osc_freq_t definition, frequency must be one of 18000, 24000 or 30000 KHz.
682 *
683 */
684static inline void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq)
685{
686 (*((void (*)(uint32_t freq))(CLOCK_FRO_SETTING_API_ROM_ADDRESS)))(freq);
687}
688
689/* @} */
690
691#if defined(__cplusplus)
692}
693#endif /* __cplusplus */
694
695/*! @} */
696
697#endif /* _FSL_CLOCK_H_ */
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